1 or cluster_n > 1):\n if cutlass.const_expr(cluster_n == 1):\n return block_reduce(warp_val, warp_op, reduction_buffer, init_val)\n else:\n return cluster_reduce(\n warp_val, warp_op, reduction_buffer, mbar_ptr, cluster_n, init_val\n )\n else:\n return warp_val\n\n\n# =============================================================================\n# Predicate Utility\n# =============================================================================\n\n\n@cute.jit\ndef predicate_k(tXcX: cute.Tensor, limit: int) -> cute.Tensor:\n \"\"\"Create predicate tensor for bounds checking.\"\"\"\n tXpX = cute.make_rmem_tensor(\n cute.make_layout(\n (\n cute.size(tXcX, mode=[0, 1]),\n cute.size(tXcX, mode=[1]),\n cute.size(tXcX, mode=[2]),\n ),\n stride=(cute.size(tXcX, mode=[2]), 0, 1),\n ),\n cutlass.Boolean,\n )\n for rest_v in cutlass.range_constexpr(tXpX.shape[0]):\n for rest_k in cutlass.range_constexpr(tXpX.shape[2]):\n tXpX[rest_v, 0, rest_k] = cute.elem_less(\n tXcX[(0, rest_v), 0, rest_k][1], limit\n )\n return tXpX\n\n\n# =============================================================================\n# Helper Functions for SF Block Processing (block_size=16)\n# =============================================================================\n\n\n@cute.jit\ndef load_8_half2(\n mX: cute.Tensor, mW: cute.Tensor, row_offset: Int32, col_offset: Int32, H: int\n):\n \"\"\"Load 16 elements (8 half2 pairs) of X and W from global memory.\n\n Returns:\n x_h2: rmem_tensor of shape (8,) containing X as half2\n w_h2: rmem_tensor of shape (8,) containing W as half2\n \"\"\"\n x_h2 = cute.make_rmem_tensor((8,), Uint32)\n w_h2 = cute.make_rmem_tensor((8,), Uint32)\n\n # Load X (2 x 128-bit loads = 16 elements)\n x_ptr0 = get_ptr_as_int64(mX, row_offset * H + col_offset)\n x_ptr1 = get_ptr_as_int64(mX, row_offset * H + col_offset + Int32(8))\n x_h2[0], x_h2[1], x_h2[2], x_h2[3] = ld_global_v4_u32(x_ptr0)\n x_h2[4], x_h2[5], x_h2[6], x_h2[7] = ld_global_v4_u32(x_ptr1)\n\n # Load W (2 x 128-bit loads = 16 elements)\n w_ptr0 = get_ptr_as_int64(mW, col_offset)\n w_ptr1 = get_ptr_as_int64(mW, col_offset + Int32(8))\n w_h2[0], w_h2[1], w_h2[2], w_h2[3] = ld_global_v4_u32(w_ptr0)\n w_h2[4], w_h2[5], w_h2[6], w_h2[7] = ld_global_v4_u32(w_ptr1)\n\n return x_h2, w_h2\n\n\n@cute.jit\ndef half2_mul_8(x_h2: cute.Tensor, w_h2: cute.Tensor) -> cute.Tensor:\n \"\"\"Multiply 8 half2 pairs element-wise.\"\"\"\n xw_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n xw_h2[i] = half2_mul(x_h2[i], w_h2[i])\n return xw_h2\n\n\n@cute.jit\ndef bfloat2_mul_8(x_h2: cute.Tensor, w_h2: cute.Tensor) -> cute.Tensor:\n \"\"\"Multiply 8 bfloat2 pairs element-wise.\"\"\"\n xw_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n xw_h2[i] = bfloat2_mul(x_h2[i], w_h2[i])\n return xw_h2\n\n\n@cute.jit\ndef half2_max_abs_8(xw_h2: cute.Tensor) -> Uint32:\n \"\"\"Compute max absolute value across 8 half2 values using tree reduction.\"\"\"\n # Compute abs for all 8 values\n abs_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n abs_h2[i] = habs2(xw_h2[i])\n\n # Tree reduction: 8 -> 4 -> 2 -> 1\n max_01 = hmax2(abs_h2[0], abs_h2[1])\n max_23 = hmax2(abs_h2[2], abs_h2[3])\n max_45 = hmax2(abs_h2[4], abs_h2[5])\n max_67 = hmax2(abs_h2[6], abs_h2[7])\n max_0123 = hmax2(max_01, max_23)\n max_4567 = hmax2(max_45, max_67)\n return hmax2(max_0123, max_4567)\n\n\n@cute.jit\ndef bfloat2_max_abs_8(xw_h2: cute.Tensor) -> Uint32:\n \"\"\"Compute max absolute value across 8 bfloat2 values using tree reduction.\"\"\"\n # Compute abs for all 8 values\n abs_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n abs_h2[i] = bfloat2_habs2(xw_h2[i])\n\n # Tree reduction: 8 -> 4 -> 2 -> 1\n max_01 = bfloat2_hmax2(abs_h2[0], abs_h2[1])\n max_23 = bfloat2_hmax2(abs_h2[2], abs_h2[3])\n max_45 = bfloat2_hmax2(abs_h2[4], abs_h2[5])\n max_67 = bfloat2_hmax2(abs_h2[6], abs_h2[7])\n max_0123 = bfloat2_hmax2(max_01, max_23)\n max_4567 = bfloat2_hmax2(max_45, max_67)\n return bfloat2_hmax2(max_0123, max_4567)\n\n\n@cute.jit\ndef half2_to_float16(xw_h2: cute.Tensor, scale: Float32) -> cute.Tensor:\n \"\"\"Convert 8 half2 to 16 float32 with scaling.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(8):\n y_f32[i * 2], y_f32[i * 2 + 1] = half2_to_float2_scaled(xw_h2[i], scale)\n return y_f32\n\n\n@cute.jit\ndef bfloat2_to_float16(xw_h2: cute.Tensor, scale: Float32) -> cute.Tensor:\n \"\"\"Convert 8 bfloat2 to 16 float32 with scaling.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(8):\n y_f32[i * 2], y_f32[i * 2 + 1] = bfloat2_to_float2_scaled(xw_h2[i], scale)\n return y_f32\n\n\n@cute.jit\ndef quantize_and_pack_16(y_f32: cute.Tensor, inv_scale: Float32) -> Uint64:\n \"\"\"Quantize 16 float32 values to FP4 and pack into uint64.\"\"\"\n # Scale values\n q = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n q[i] = y_f32[i] * inv_scale\n\n # Convert to E2M1 and pack\n packed_lo = cvt_e2m1x8_f32(q[0], q[1], q[2], q[3], q[4], q[5], q[6], q[7])\n packed_hi = cvt_e2m1x8_f32(q[8], q[9], q[10], q[11], q[12], q[13], q[14], q[15])\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n# =============================================================================\n# Helper Functions for Float32 SF Block Processing\n# =============================================================================\n\n\n@cute.jit\ndef load_f32_16_from_smem(\n sH: cute.Tensor, row_idx: Int32, col_offset: Int32\n) -> cute.Tensor:\n \"\"\"Load 16 Float32 values from shared memory.\"\"\"\n h_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n h_f32[i] = Float32(sH[row_idx, col_offset + i])\n return h_f32\n\n\n@cute.jit\ndef compute_y_and_max_abs_f32(\n h_f32: cute.Tensor, w_f32: cute.Tensor, rstd: Float32\n) -> Tuple[cute.Tensor, Float32]:\n \"\"\"Compute y = h * rstd * w and max_abs for 16 Float32 values.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n\n # Compute y and track max_abs\n y_f32[0] = h_f32[0] * rstd * w_f32[0]\n max_abs = fabs_f32(y_f32[0])\n\n for i in cutlass.range_constexpr(1, 16):\n y_f32[i] = h_f32[i] * rstd * w_f32[i]\n max_abs = fmax_f32(max_abs, fabs_f32(y_f32[i]))\n\n return y_f32, max_abs\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nCommon utilities for FP4 quantization kernels using CuTe-DSL.\n\nThis module contains shared PTX intrinsics, helper functions, and reduction\nutilities used by both rmsnorm_fp4quant.py and add_rmsnorm_fp4quant.py.\n\"\"\"\n\nimport functools\nimport math\nimport operator\nfrom typing import Callable, Tuple\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Int64, Uint32, Uint64\nfrom cutlass.cutlass_dsl import T, dsl_user_op\nfrom cutlass._mlir.dialects import llvm\n\n\n# =============================================================================\n# Constants\n# =============================================================================\n\nFLOAT4_E2M1_MAX = 6.0 # Maximum value representable in FP4 E2M1\nFLOAT8_E4M3_MAX = 448.0 # Maximum value representable in FP8 E4M3\nSF_VEC_SIZE = 16 # Elements per scale factor block\nCOPY_BITS = 128 # 128-bit vectorized loads\n\n\n# =============================================================================\n# Architecture Detection\n# =============================================================================\n\n\n@functools.lru_cache(maxsize=16)\ndef get_sm_version(device: int | torch.device | str | None = None) -> int:\n \"\"\"Get the SM version of a CUDA device.\n\n Args:\n device: CUDA device to query. Can be an int (device index), torch.device,\n device string (e.g., 'cuda:0'), or None to use current device.\n\n Returns:\n SM version as an integer (e.g., 100 for SM100).\n \"\"\"\n if not torch.cuda.is_available():\n return 80\n if device is None:\n device = torch.cuda.current_device()\n props = torch.cuda.get_device_properties(device)\n return props.major * 10 + props.minor\n\n\n# =============================================================================\n# PTX Intrinsics - Cluster Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef set_block_rank(\n smem_ptr: cute.Pointer, peer_cta_rank_in_cluster: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Map smem pointer to address at another CTA rank in the cluster.\"\"\"\n smem_ptr_i32 = smem_ptr.toint(loc=loc, ip=ip).ir_value()\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [smem_ptr_i32, peer_cta_rank_in_cluster.ir_value()],\n \"mapa.shared::cluster.u32 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef store_shared_remote(\n val: Float32,\n smem_ptr: cute.Pointer,\n mbar_ptr: cute.Pointer,\n peer_cta_rank_in_cluster: Int32,\n *,\n loc=None,\n ip=None,\n) -> None:\n \"\"\"Store Float32 value to shared memory on a remote CTA in the cluster.\"\"\"\n remote_smem_ptr_i32 = set_block_rank(\n smem_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n ).ir_value()\n remote_mbar_ptr_i32 = set_block_rank(\n mbar_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n ).ir_value()\n llvm.inline_asm(\n None,\n [remote_smem_ptr_i32, val.ir_value(loc=loc, ip=ip), remote_mbar_ptr_i32],\n \"st.async.shared::cluster.mbarrier::complete_tx::bytes.f32 [$0], $1, [$2];\",\n \"r,f,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef elem_pointer(x: cute.Tensor, coord, *, loc=None, ip=None) -> cute.Pointer:\n \"\"\"Get pointer to element at coordinate in tensor.\"\"\"\n return x.iterator + cute.crd2idx(coord, x.layout, loc=loc, ip=ip)\n\n\n# =============================================================================\n# PTX Intrinsics - 128-bit Vectorized Global Loads/Stores\n# =============================================================================\n\n\n@dsl_user_op\ndef ld_global_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) from global memory.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.global.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef ld_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) using generic addressing (works for GMEM and SMEM).\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef st_global_u64(base_ptr: Int64, value: Uint64, *, loc=None, ip=None):\n \"\"\"Store 64 bits to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Uint64(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.u64 [$0], $1;\",\n \"l,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef st_global_u32(base_ptr: Int64, value: Uint32, *, loc=None, ip=None):\n \"\"\"Store 32 bits to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Uint32(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.u32 [$0], $1;\",\n \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef get_ptr_as_int64(tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None) -> Int64:\n \"\"\"Get the memory address of tensor[offset] as Int64.\n\n WARNING: This uses ptrtoint which strips address space information.\n For SMEM tensors, the resulting Int64 is a raw SMEM offset that does NOT\n work with generic-addressing loads (ld.v4.u32). Use only with explicit\n address-space loads (ld.global.*) or for global memory tensors.\n \"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n ptr_int = llvm.ptrtoint(T.i64(), elem_ptr.llvm_ptr, loc=loc, ip=ip)\n return Int64(ptr_int)\n\n\n@dsl_user_op\ndef get_smem_ptr_as_int32(\n tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Get the shared-memory byte address of tensor[offset] as Int32.\n\n Uses Pointer.toint() which preserves the SMEM address space (addrspace 3),\n returning a 32-bit SMEM address suitable for ld.shared.* instructions.\n \"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n return elem_ptr.toint(loc=loc, ip=ip)\n\n\n@dsl_user_op\ndef ld_shared_v4_u32(\n smem_addr: Int32, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) from shared memory via ld.shared.v4.u32.\n\n Args:\n smem_addr: 32-bit shared memory address (from get_smem_ptr_as_int32).\n\n Returns:\n 4 Uint32 values (16 bytes total, e.g. 8 packed fp16 elements).\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int32(smem_addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef pack_16bit_to_u32(lo, hi, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two 16-bit scalar values (fp16 or bf16) into one Uint32 (half2/bfloat2).\n\n Uses PTX mov.b32 to bitwise-pack two 16-bit register values into a single\n 32-bit register, suitable for half2/bfloat2 SIMD operations.\n \"\"\"\n lo_ir = lo.ir_value(loc=loc, ip=ip)\n hi_ir = hi.ir_value(loc=loc, ip=ip)\n lo_i16 = llvm.bitcast(T.i16(), lo_ir, loc=loc, ip=ip)\n hi_i16 = llvm.bitcast(T.i16(), hi_ir, loc=loc, ip=ip)\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [lo_i16, hi_i16],\n \"mov.b32 $0, {$1, $2};\",\n \"=r,h,h\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# PTX Intrinsics - Math Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef rcp_approx_ftz(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Fast reciprocal using PTX rcp.approx.ftz.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"rcp.approx.ftz.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fmin_f32(a: Float32, b: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute min of two float32 values using PTX min.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"min.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fmax_f32(a: Float32, b: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute max of two float32 values using PTX max.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"max.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fabs_f32(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute absolute value of float32 using PTX abs.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"abs.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Half2 SIMD Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef half2_mul(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Multiply two Half2 values element-wise: (a.x*b.x, a.y*b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"mul.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hadd2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Add two Half2 values element-wise: (a.x+b.x, a.y+b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"add.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef habs2(x: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Half2 absolute value - clears sign bits of both fp16 values.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"and.b32 $0, $1, 0x7FFF7FFF;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hmax2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Half2 max - element-wise max of 2 fp16 pairs.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"max.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hmax_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 fp16 values in half2 as float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $1;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef half2_to_float2_scaled(\n h2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> Tuple[Float32, Float32]:\n \"\"\"Convert half2 to float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(h2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $2;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n# =============================================================================\n# BFloat2 SIMD Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef bfloat2_mul(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Multiply two BFloat2 values element-wise: (a.x*b.x, a.y*b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"mul.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_add(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Add two BFloat2 values element-wise: (a.x+b.x, a.y+b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"add.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_habs2(x: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"BFloat16x2 absolute value - clears sign bits of both bf16 values.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"and.b32 $0, $1, 0x7FFF7FFF;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"BFloat16x2 max - element-wise max of 2 bf16 pairs.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"max.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 bf16 values in bfloat2 as float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $1, 0xFFFF;\n shr.b32 hi, $1, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_to_float2_scaled(\n bf2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> Tuple[Float32, Float32]:\n \"\"\"Convert bfloat16x2 to float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(bf2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $2, 0xFFFF;\n shr.b32 hi, $2, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n# =============================================================================\n# FP8 E4M3 Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32_to_e4m3(a: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Convert float32 to E4M3 using native cvt.rn.satfinite.e4m3x2.f32.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .f32 zero;\n mov.f32 zero, 0f00000000;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, zero, $1;\n cvt.u32.u16 $0, fp8_pair;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef cvt_e4m3x4_to_f32x4(\n packed: Uint32, *, loc=None, ip=None\n) -> tuple[Float32, Float32, Float32, Float32]:\n \"\"\"Convert 4 packed E4M3 bytes (in a uint32) to 4 float32 values.\n\n Uses e4m3x2 → f16x2 → f32 conversion path (SM89+/PTX ISA 7.8+).\n Input: uint32 containing bytes [b0, b1, b2, b3] (low to high).\n Output: (f0, f1, f2, f3) as Float32.\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32(), T.f32(), T.f32()]),\n [Uint32(packed).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 pair_lo, pair_hi;\n .reg .b32 h2_lo, h2_hi;\n .reg .b16 h0, h1, h2, h3;\n mov.b32 {pair_lo, pair_hi}, $4;\n cvt.rn.f16x2.e4m3x2 h2_lo, pair_lo;\n cvt.rn.f16x2.e4m3x2 h2_hi, pair_hi;\n mov.b32 {h0, h1}, h2_lo;\n mov.b32 {h2, h3}, h2_hi;\n cvt.f32.f16 $0, h0;\n cvt.f32.f16 $1, h1;\n cvt.f32.f16 $2, h2;\n cvt.f32.f16 $3, h3;\n }\n \"\"\",\n \"=f,=f,=f,=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n f2 = llvm.extractvalue(T.f32(), result, [2], loc=loc, ip=ip)\n f3 = llvm.extractvalue(T.f32(), result, [3], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1), Float32(f2), Float32(f3)\n\n\n@dsl_user_op\ndef cvt_f32x2_to_half2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two float32 values into a half2 (uint32 containing two fp16 values).\n\n Uses cvt.rn.f16.f32 for each value, then packs into a single uint32.\n Matches __float22half2_rn() behavior in CUDA.\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n cvt.rn.f16.f32 h0, $1;\n cvt.rn.f16.f32 h1, $2;\n mov.b32 $0, {h0, h1};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fp8_e4m3_to_f32_and_rcp(fp8_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Convert FP8 E4M3 to float32 AND compute reciprocal.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .u32 exp_u, mant_u;\n .reg .s32 exp_s;\n .reg .f32 exp_f, mant_f, fp8_float, result;\n\n setp.eq.u32 p_zero, $1, 0;\n and.b32 mant_u, $1, 7;\n shr.b32 exp_u, $1, 3;\n and.b32 exp_u, exp_u, 15;\n sub.s32 exp_s, exp_u, 7;\n cvt.rn.f32.s32 exp_f, exp_s;\n ex2.approx.f32 exp_f, exp_f;\n cvt.rn.f32.u32 mant_f, mant_u;\n fma.rn.f32 mant_f, mant_f, 0f3E000000, 0f3F800000;\n mul.f32 fp8_float, exp_f, mant_f;\n rcp.approx.ftz.f32 result, fp8_float;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_compute_output_scale(\n fp8_val: Uint32, global_scale: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute NVFP4 output_scale matching the CUDA kernel exactly.\n\n Converts E4M3 scale factor to float via hardware f16x2 path, then computes\n rcp(float_scale * rcp(global_scale)). Returns 0 when scale is zero.\n\n This matches quantization_utils.cuh:\n SFValue = static_cast<float>(tmp);\n outputScale = rcp_approx(SFValue * rcp_approx(SFScaleVal));\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(fp8_val).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n .reg .f32 scale_f32, rcp_gs, product, result;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 scale_f32, h_lo;\n\n rcp.approx.ftz.f32 rcp_gs, $2;\n mul.f32 product, scale_f32, rcp_gs;\n rcp.approx.ftz.f32 result, product;\n\n setp.eq.f32 p_zero, scale_f32, 0f00000000;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# UE8M0 Intrinsics (for MXFP4)\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32_to_ue8m0(max_val: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"\n Convert float32 max value to UE8M0 scale factor.\n\n UE8M0 is unsigned 8-bit exponent-only format:\n - value = 2^(ue8m0 - 127)\n - ue8m0 = ceil(log2(max_val)) + 127\n\n Uses lg2.approx.f32 for fast log2 approximation.\n Uses cvt.rpi (round towards positive infinity, i.e., ceiling).\n Returns value clamped to [0, 255].\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(max_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero, p_neg, p_ovf;\n .reg .f32 log2_val;\n .reg .s32 exp_int, result;\n\n // Check for zero/negative\n setp.le.f32 p_zero, $1, 0f00000000;\n\n // Compute ceil(log2(max_val)) using cvt.rpi (round towards +inf)\n lg2.approx.f32 log2_val, $1;\n cvt.rpi.s32.f32 exp_int, log2_val;\n\n // Add bias and clamp to [0, 255]\n add.s32 result, exp_int, 127;\n setp.lt.s32 p_neg, result, 0;\n setp.gt.s32 p_ovf, result, 255;\n selp.s32 result, 0, result, p_neg;\n selp.s32 result, 255, result, p_ovf;\n selp.s32 $0, 0, result, p_zero;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef ue8m0_to_output_scale(ue8m0_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"\n Convert UE8M0 to output_scale for MXFP4 quantization.\n\n UE8M0 value = 2^(ue8m0 - 127)\n Returns 1 / 2^(ue8m0 - 127) = 2^(127 - ue8m0)\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(ue8m0_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .s32 neg_exp;\n .reg .f32 neg_exp_f, result;\n\n // Check for zero\n setp.eq.u32 p_zero, $1, 0;\n\n // Compute 2^(127 - ue8m0) = 1 / 2^(ue8m0 - 127)\n sub.s32 neg_exp, 127, $1;\n cvt.rn.f32.s32 neg_exp_f, neg_exp;\n ex2.approx.f32 result, neg_exp_f;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# E2M1 Conversion\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_e2m1x8_f32(\n v0: Float32,\n v1: Float32,\n v2: Float32,\n v3: Float32,\n v4: Float32,\n v5: Float32,\n v6: Float32,\n v7: Float32,\n *,\n loc=None,\n ip=None,\n) -> Uint32:\n \"\"\"Convert eight float32 values to eight E2M1 (4-bit) values packed into uint32.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n Float32(v2).ir_value(loc=loc, ip=ip),\n Float32(v3).ir_value(loc=loc, ip=ip),\n Float32(v4).ir_value(loc=loc, ip=ip),\n Float32(v5).ir_value(loc=loc, ip=ip),\n Float32(v6).ir_value(loc=loc, ip=ip),\n Float32(v7).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 byte0, byte1, byte2, byte3;\n cvt.rn.satfinite.e2m1x2.f32 byte0, $2, $1;\n cvt.rn.satfinite.e2m1x2.f32 byte1, $4, $3;\n cvt.rn.satfinite.e2m1x2.f32 byte2, $6, $5;\n cvt.rn.satfinite.e2m1x2.f32 byte3, $8, $7;\n mov.b32 $0, {byte0, byte1, byte2, byte3};\n }\n \"\"\",\n \"=r,f,f,f,f,f,f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Warp, Block, and Cluster Reduction Utilities\n# =============================================================================\n\n\n@cute.jit\ndef warp_reduce(val, op, width: cutlass.Constexpr[int] = 32):\n \"\"\"Reduce across threads in a warp using butterfly shuffle.\"\"\"\n if cutlass.const_expr(isinstance(val, cute.TensorSSA)):\n res = cute.make_rmem_tensor(val.shape, val.dtype)\n res.store(val)\n for i in cutlass.range_constexpr(cute.size(val.shape)):\n res[i] = warp_reduce(res[i], op, width)\n return res.load()\n else:\n for i in cutlass.range_constexpr(int(math.log2(width))):\n val = op(val, cute.arch.shuffle_sync_bfly(val, offset=1 << i))\n return val\n\n\n@cute.jit\ndef block_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n init_val: Float32,\n) -> Float32:\n \"\"\"Block reduction across multiple warps using shared memory.\"\"\"\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n warps_per_row = cute.size(reduction_buffer.shape[1])\n row_idx = warp_idx // warps_per_row\n col_idx = warp_idx % warps_per_row\n\n if lane_idx == 0:\n reduction_buffer[row_idx, col_idx] = val\n cute.arch.barrier()\n\n block_reduce_val = init_val\n if lane_idx < warps_per_row:\n block_reduce_val = reduction_buffer[row_idx, lane_idx]\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef cluster_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n mbar_ptr: cute.Pointer,\n cluster_n: cutlass.Constexpr[int],\n init_val: Float32,\n) -> Float32:\n \"\"\"Cluster reduction across multiple CTAs using mbarrier.\"\"\"\n cta_rank_in_cluster = cute.arch.block_idx_in_cluster()\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n\n rows_per_block = reduction_buffer.shape[0]\n warps_per_row = reduction_buffer.shape[1][0]\n\n row_idx = warp_idx // warps_per_row\n col_idx = warp_idx % warps_per_row\n\n # Warp 0 sets up mbarrier transaction count\n if warp_idx == 0:\n with cute.arch.elect_one():\n num_warps = rows_per_block * warps_per_row\n expected_bytes = num_warps * cluster_n * 4\n cute.arch.mbarrier_arrive_and_expect_tx(mbar_ptr, expected_bytes)\n\n # Each lane < cluster_n writes to a different CTA's shared memory\n if lane_idx < cluster_n:\n store_shared_remote(\n val,\n elem_pointer(reduction_buffer, (row_idx, (col_idx, cta_rank_in_cluster))),\n mbar_ptr,\n peer_cta_rank_in_cluster=lane_idx,\n )\n\n # Wait for all cluster writes\n cute.arch.mbarrier_wait(mbar_ptr, phase=0)\n\n # Reduce across all values\n num_total = warps_per_row * cluster_n\n num_iter = cute.ceil_div(num_total, 32)\n\n block_reduce_val = init_val\n for i in cutlass.range_constexpr(num_iter):\n idx = lane_idx + i * 32\n if idx < num_total:\n block_reduce_val = op(block_reduce_val, reduction_buffer[row_idx, idx])\n\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef row_reduce(\n x: cute.TensorSSA,\n op: cute.ReductionOp,\n threads_per_row: cutlass.Constexpr[int],\n reduction_buffer: cute.Tensor,\n mbar_ptr,\n cluster_n: cutlass.Constexpr[int],\n init_val: Float32,\n):\n \"\"\"Row reduction with optional cluster support.\"\"\"\n local_val = x.reduce(op, init_val=init_val, reduction_profile=0)\n\n warp_op = {\n cute.ReductionOp.ADD: operator.add,\n cute.ReductionOp.MAX: cute.arch.fmax,\n }[op]\n warp_width = min(threads_per_row, 32)\n warp_val = warp_reduce(local_val, warp_op, width=warp_width)\n\n warps_per_row = max(threads_per_row // 32, 1)\n\n if cutlass.const_expr(warps_per_row > 1 or cluster_n > 1):\n if cutlass.const_expr(cluster_n == 1):\n return block_reduce(warp_val, warp_op, reduction_buffer, init_val)\n else:\n return cluster_reduce(\n warp_val, warp_op, reduction_buffer, mbar_ptr, cluster_n, init_val\n )\n else:\n return warp_val\n\n\n# =============================================================================\n# Predicate Utility\n# =============================================================================\n\n\n@cute.jit\ndef predicate_k(tXcX: cute.Tensor, limit: int) -> cute.Tensor:\n \"\"\"Create predicate tensor for bounds checking.\"\"\"\n tXpX = cute.make_rmem_tensor(\n cute.make_layout(\n (\n cute.size(tXcX, mode=[0, 1]),\n cute.size(tXcX, mode=[1]),\n cute.size(tXcX, mode=[2]),\n ),\n stride=(cute.size(tXcX, mode=[2]), 0, 1),\n ),\n cutlass.Boolean,\n )\n for rest_v in cutlass.range_constexpr(tXpX.shape[0]):\n for rest_k in cutlass.range_constexpr(tXpX.shape[2]):\n tXpX[rest_v, 0, rest_k] = cute.elem_less(\n tXcX[(0, rest_v), 0, rest_k][1], limit\n )\n return tXpX\n\n\n# =============================================================================\n# Helper Functions for SF Block Processing (block_size=16)\n# =============================================================================\n\n\n@cute.jit\ndef load_8_half2(\n mX: cute.Tensor, mW: cute.Tensor, row_offset: Int32, col_offset: Int32, H: int\n):\n \"\"\"Load 16 elements (8 half2 pairs) of X and W from global memory.\n\n Returns:\n x_h2: rmem_tensor of shape (8,) containing X as half2\n w_h2: rmem_tensor of shape (8,) containing W as half2\n \"\"\"\n x_h2 = cute.make_rmem_tensor((8,), Uint32)\n w_h2 = cute.make_rmem_tensor((8,), Uint32)\n\n # Load X (2 x 128-bit loads = 16 elements)\n x_ptr0 = get_ptr_as_int64(mX, row_offset * H + col_offset)\n x_ptr1 = get_ptr_as_int64(mX, row_offset * H + col_offset + Int32(8))\n x_h2[0], x_h2[1], x_h2[2], x_h2[3] = ld_global_v4_u32(x_ptr0)\n x_h2[4], x_h2[5], x_h2[6], x_h2[7] = ld_global_v4_u32(x_ptr1)\n\n # Load W (2 x 128-bit loads = 16 elements)\n w_ptr0 = get_ptr_as_int64(mW, col_offset)\n w_ptr1 = get_ptr_as_int64(mW, col_offset + Int32(8))\n w_h2[0], w_h2[1], w_h2[2], w_h2[3] = ld_global_v4_u32(w_ptr0)\n w_h2[4], w_h2[5], w_h2[6], w_h2[7] = ld_global_v4_u32(w_ptr1)\n\n return x_h2, w_h2\n\n\n@cute.jit\ndef half2_mul_8(x_h2: cute.Tensor, w_h2: cute.Tensor) -> cute.Tensor:\n \"\"\"Multiply 8 half2 pairs element-wise.\"\"\"\n xw_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n xw_h2[i] = half2_mul(x_h2[i], w_h2[i])\n return xw_h2\n\n\n@cute.jit\ndef bfloat2_mul_8(x_h2: cute.Tensor, w_h2: cute.Tensor) -> cute.Tensor:\n \"\"\"Multiply 8 bfloat2 pairs element-wise.\"\"\"\n xw_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n xw_h2[i] = bfloat2_mul(x_h2[i], w_h2[i])\n return xw_h2\n\n\n@cute.jit\ndef half2_max_abs_8(xw_h2: cute.Tensor) -> Uint32:\n \"\"\"Compute max absolute value across 8 half2 values using tree reduction.\"\"\"\n # Compute abs for all 8 values\n abs_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n abs_h2[i] = habs2(xw_h2[i])\n\n # Tree reduction: 8 -> 4 -> 2 -> 1\n max_01 = hmax2(abs_h2[0], abs_h2[1])\n max_23 = hmax2(abs_h2[2], abs_h2[3])\n max_45 = hmax2(abs_h2[4], abs_h2[5])\n max_67 = hmax2(abs_h2[6], abs_h2[7])\n max_0123 = hmax2(max_01, max_23)\n max_4567 = hmax2(max_45, max_67)\n return hmax2(max_0123, max_4567)\n\n\n@cute.jit\ndef bfloat2_max_abs_8(xw_h2: cute.Tensor) -> Uint32:\n \"\"\"Compute max absolute value across 8 bfloat2 values using tree reduction.\"\"\"\n # Compute abs for all 8 values\n abs_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n abs_h2[i] = bfloat2_habs2(xw_h2[i])\n\n # Tree reduction: 8 -> 4 -> 2 -> 1\n max_01 = bfloat2_hmax2(abs_h2[0], abs_h2[1])\n max_23 = bfloat2_hmax2(abs_h2[2], abs_h2[3])\n max_45 = bfloat2_hmax2(abs_h2[4], abs_h2[5])\n max_67 = bfloat2_hmax2(abs_h2[6], abs_h2[7])\n max_0123 = bfloat2_hmax2(max_01, max_23)\n max_4567 = bfloat2_hmax2(max_45, max_67)\n return bfloat2_hmax2(max_0123, max_4567)\n\n\n@cute.jit\ndef half2_to_float16(xw_h2: cute.Tensor, scale: Float32) -> cute.Tensor:\n \"\"\"Convert 8 half2 to 16 float32 with scaling.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(8):\n y_f32[i * 2], y_f32[i * 2 + 1] = half2_to_float2_scaled(xw_h2[i], scale)\n return y_f32\n\n\n@cute.jit\ndef bfloat2_to_float16(xw_h2: cute.Tensor, scale: Float32) -> cute.Tensor:\n \"\"\"Convert 8 bfloat2 to 16 float32 with scaling.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(8):\n y_f32[i * 2], y_f32[i * 2 + 1] = bfloat2_to_float2_scaled(xw_h2[i], scale)\n return y_f32\n\n\n@cute.jit\ndef quantize_and_pack_16(y_f32: cute.Tensor, inv_scale: Float32) -> Uint64:\n \"\"\"Quantize 16 float32 values to FP4 and pack into uint64.\"\"\"\n # Scale values\n q = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n q[i] = y_f32[i] * inv_scale\n\n # Convert to E2M1 and pack\n packed_lo = cvt_e2m1x8_f32(q[0], q[1], q[2], q[3], q[4], q[5], q[6], q[7])\n packed_hi = cvt_e2m1x8_f32(q[8], q[9], q[10], q[11], q[12], q[13], q[14], q[15])\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n# =============================================================================\n# Helper Functions for Float32 SF Block Processing\n# =============================================================================\n\n\n@cute.jit\ndef load_f32_16_from_smem(\n sH: cute.Tensor, row_idx: Int32, col_offset: Int32\n) -> cute.Tensor:\n \"\"\"Load 16 Float32 values from shared memory.\"\"\"\n h_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n h_f32[i] = Float32(sH[row_idx, col_offset + i])\n return h_f32\n\n\n@cute.jit\ndef compute_y_and_max_abs_f32(\n h_f32: cute.Tensor, w_f32: cute.Tensor, rstd: Float32\n) -> Tuple[cute.Tensor, Float32]:\n \"\"\"Compute y = h * rstd * w and max_abs for 16 Float32 values.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n\n # Compute y and track max_abs\n y_f32[0] = h_f32[0] * rstd * w_f32[0]\n max_abs = fabs_f32(y_f32[0])\n\n for i in cutlass.range_constexpr(1, 16):\n y_f32[i] = h_f32[i] * rstd * w_f32[i]\n max_abs = fmax_f32(max_abs, fabs_f32(y_f32[i]))\n\n return y_f32, max_abs\n"},"diff":{"kind":"string","value":"--- flashinfer/cute_dsl/fp4_common.py\n+++ flashinfer/cute_dsl/fp4_common.py\n@@ -190,6 +190,23 @@\n ],\n \"st.global.u64 [$0], $1;\",\n \"l,l\",\n+ has_side_effects=True,\n+ is_align_stack=False,\n+ asm_dialect=llvm.AsmDialect.AD_ATT,\n+ )\n+\n+\n+@dsl_user_op\n+def st_global_u32(base_ptr: Int64, value: Uint32, *, loc=None, ip=None):\n+ \"\"\"Store 32 bits to global memory.\"\"\"\n+ llvm.inline_asm(\n+ None,\n+ [\n+ Int64(base_ptr).ir_value(loc=loc, ip=ip),\n+ Uint32(value).ir_value(loc=loc, ip=ip),\n+ ],\n+ \"st.global.u32 [$0], $1;\",\n+ \"l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,"},"lines_added":{"kind":"number","value":17,"string":"17"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":6,"string":"6"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200"],"string":"[\n \"B200\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["5x","1.42x","1.37x","1.41x","1.39x","1.34x","1.32x"],"string":"[\n \"5x\",\n \"1.42x\",\n \"1.37x\",\n \"1.41x\",\n \"1.39x\",\n \"1.34x\",\n \"1.32x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/fp4_common.py).\n\nGoal: perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels\nTarget hardware: B200\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nCommon utilities for FP4 quantization kernels using CuTe-DSL.\n\nThis module contains shared PTX intrinsics, helper functions, and reduction\nutilities used by both rmsnorm_fp4quant.py and add_rmsnorm_fp4quant.py.\n\"\"\"\n\nimport functools\nimport math\nimport operator\nfrom typing import Callable, Tuple\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Int64, Uint32, Uint64\nfrom cutlass.cutlass_dsl import T, dsl_user_op\nfrom cutlass._mlir.dialects import llvm\n\n\n# =============================================================================\n# Constants\n# =============================================================================\n\nFLOAT4_E2M1_MAX = 6.0 # Maximum value representable in FP4 E2M1\nFLOAT8_E4M3_MAX = 448.0 # Maximum value representable in FP8 E4M3\nSF_VEC_SIZE = 16 # Elements per scale factor block\nCOPY_BITS = 128 # 128-bit vectorized loads\n\n\n# =============================================================================\n# Architecture Detection\n# =============================================================================\n\n\n@functools.lru_cache(maxsize=16)\ndef get_sm_version(device: int | torch.device | str | None = None) -> int:\n \"\"\"Get the SM version of a CUDA device.\n\n Args:\n device: CUDA device to query. Can be an int (device index), torch.device,\n device string (e.g., 'cuda:0'), or None to use current device.\n\n Returns:\n SM version as an integer (e.g., 100 for SM100).\n \"\"\"\n if not torch.cuda.is_available():\n return 80\n if device is None:\n device = torch.cuda.current_device()\n props = torch.cuda.get_device_properties(device)\n return props.major * 10 + props.minor\n\n\n# =============================================================================\n# PTX Intrinsics - Cluster Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef set_block_rank(\n smem_ptr: cute.Pointer, peer_cta_rank_in_cluster: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Map smem pointer to address at another CTA rank in the cluster.\"\"\"\n smem_ptr_i32 = smem_ptr.toint(loc=loc, ip=ip).ir_value()\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [smem_ptr_i32, peer_cta_rank_in_cluster.ir_value()],\n \"mapa.shared::cluster.u32 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef store_shared_remote(\n val: Float32,\n smem_ptr: cute.Pointer,\n mbar_ptr: cute.Pointer,\n peer_cta_rank_in_cluster: Int32,\n *,\n loc=None,\n ip=None,\n) -> None:\n \"\"\"Store Float32 value to shared memory on a remote CTA in the cluster.\"\"\"\n remote_smem_ptr_i32 = set_block_rank(\n smem_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n ).ir_value()\n remote_mbar_ptr_i32 = set_block_rank(\n mbar_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n ).ir_value()\n llvm.inline_asm(\n None,\n [remote_smem_ptr_i32, val.ir_value(loc=loc, ip=ip), remote_mbar_ptr_i32],\n \"st.async.shared::cluster.mbarrier::complete_tx::bytes.f32 [$0], $1, [$2];\",\n \"r,f,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef elem_pointer(x: cute.Tensor, coord, *, loc=None, ip=None) -> cute.Pointer:\n \"\"\"Get pointer to element at coordinate in tensor.\"\"\"\n return x.iterator + cute.crd2idx(coord, x.layout, loc=loc, ip=ip)\n\n\n# =============================================================================\n# PTX Intrinsics - 128-bit Vectorized Global Loads/Stores\n# =============================================================================\n\n\n@dsl_user_op\ndef ld_global_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) from global memory.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.global.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef ld_v4_u32(\n base_ptr: Int64, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) using generic addressing (works for GMEM and SMEM).\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int64(base_ptr).ir_value(loc=loc, ip=ip)],\n \"ld.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,l\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef st_global_u64(base_ptr: Int64, value: Uint64, *, loc=None, ip=None):\n \"\"\"Store 64 bits to global memory.\"\"\"\n llvm.inline_asm(\n None,\n [\n Int64(base_ptr).ir_value(loc=loc, ip=ip),\n Uint64(value).ir_value(loc=loc, ip=ip),\n ],\n \"st.global.u64 [$0], $1;\",\n \"l,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef get_ptr_as_int64(tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None) -> Int64:\n \"\"\"Get the memory address of tensor[offset] as Int64.\n\n WARNING: This uses ptrtoint which strips address space information.\n For SMEM tensors, the resulting Int64 is a raw SMEM offset that does NOT\n work with generic-addressing loads (ld.v4.u32). Use only with explicit\n address-space loads (ld.global.*) or for global memory tensors.\n \"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n ptr_int = llvm.ptrtoint(T.i64(), elem_ptr.llvm_ptr, loc=loc, ip=ip)\n return Int64(ptr_int)\n\n\n@dsl_user_op\ndef get_smem_ptr_as_int32(\n tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Get the shared-memory byte address of tensor[offset] as Int32.\n\n Uses Pointer.toint() which preserves the SMEM address space (addrspace 3),\n returning a 32-bit SMEM address suitable for ld.shared.* instructions.\n \"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n return elem_ptr.toint(loc=loc, ip=ip)\n\n\n@dsl_user_op\ndef ld_shared_v4_u32(\n smem_addr: Int32, *, loc=None, ip=None\n) -> Tuple[Uint32, Uint32, Uint32, Uint32]:\n \"\"\"Load 128 bits (4 x uint32) from shared memory via ld.shared.v4.u32.\n\n Args:\n smem_addr: 32-bit shared memory address (from get_smem_ptr_as_int32).\n\n Returns:\n 4 Uint32 values (16 bytes total, e.g. 8 packed fp16 elements).\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.i32(), T.i32(), T.i32(), T.i32()]),\n [Int32(smem_addr).ir_value(loc=loc, ip=ip)],\n \"ld.shared.v4.u32 {$0, $1, $2, $3}, [$4];\",\n \"=r,=r,=r,=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n v0 = llvm.extractvalue(T.i32(), result, [0], loc=loc, ip=ip)\n v1 = llvm.extractvalue(T.i32(), result, [1], loc=loc, ip=ip)\n v2 = llvm.extractvalue(T.i32(), result, [2], loc=loc, ip=ip)\n v3 = llvm.extractvalue(T.i32(), result, [3], loc=loc, ip=ip)\n return Uint32(v0), Uint32(v1), Uint32(v2), Uint32(v3)\n\n\n@dsl_user_op\ndef pack_16bit_to_u32(lo, hi, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two 16-bit scalar values (fp16 or bf16) into one Uint32 (half2/bfloat2).\n\n Uses PTX mov.b32 to bitwise-pack two 16-bit register values into a single\n 32-bit register, suitable for half2/bfloat2 SIMD operations.\n \"\"\"\n lo_ir = lo.ir_value(loc=loc, ip=ip)\n hi_ir = hi.ir_value(loc=loc, ip=ip)\n lo_i16 = llvm.bitcast(T.i16(), lo_ir, loc=loc, ip=ip)\n hi_i16 = llvm.bitcast(T.i16(), hi_ir, loc=loc, ip=ip)\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [lo_i16, hi_i16],\n \"mov.b32 $0, {$1, $2};\",\n \"=r,h,h\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# PTX Intrinsics - Math Operations\n# =============================================================================\n\n\n@dsl_user_op\ndef rcp_approx_ftz(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Fast reciprocal using PTX rcp.approx.ftz.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"rcp.approx.ftz.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fmin_f32(a: Float32, b: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute min of two float32 values using PTX min.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"min.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fmax_f32(a: Float32, b: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute max of two float32 values using PTX max.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip), Float32(b).ir_value(loc=loc, ip=ip)],\n \"max.f32 $0, $1, $2;\",\n \"=f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fabs_f32(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Compute absolute value of float32 using PTX abs.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"abs.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Half2 SIMD Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef half2_mul(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Multiply two Half2 values element-wise: (a.x*b.x, a.y*b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"mul.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hadd2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Add two Half2 values element-wise: (a.x+b.x, a.y+b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"add.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef habs2(x: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Half2 absolute value - clears sign bits of both fp16 values.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"and.b32 $0, $1, 0x7FFF7FFF;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hmax2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Half2 max - element-wise max of 2 fp16 pairs.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"max.f16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef hmax_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 fp16 values in half2 as float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $1;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef half2_to_float2_scaled(\n h2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> Tuple[Float32, Float32]:\n \"\"\"Convert half2 to float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(h2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $2;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n# =============================================================================\n# BFloat2 SIMD Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef bfloat2_mul(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Multiply two BFloat2 values element-wise: (a.x*b.x, a.y*b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"mul.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_add(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Add two BFloat2 values element-wise: (a.x+b.x, a.y+b.y).\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"add.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_habs2(x: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"BFloat16x2 absolute value - clears sign bits of both bf16 values.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"and.b32 $0, $1, 0x7FFF7FFF;\",\n \"=r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax2(a: Uint32, b: Uint32, *, loc=None, ip=None) -> Uint32:\n \"\"\"BFloat16x2 max - element-wise max of 2 bf16 pairs.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Uint32(a).ir_value(loc=loc, ip=ip), Uint32(b).ir_value(loc=loc, ip=ip)],\n \"max.bf16x2 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 bf16 values in bfloat2 as float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $1, 0xFFFF;\n shr.b32 hi, $1, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_to_float2_scaled(\n bf2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> Tuple[Float32, Float32]:\n \"\"\"Convert bfloat16x2 to float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(bf2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $2, 0xFFFF;\n shr.b32 hi, $2, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n# =============================================================================\n# FP8 E4M3 Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32_to_e4m3(a: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Convert float32 to E4M3 using native cvt.rn.satfinite.e4m3x2.f32.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .f32 zero;\n mov.f32 zero, 0f00000000;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, zero, $1;\n cvt.u32.u16 $0, fp8_pair;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef cvt_e4m3x4_to_f32x4(\n packed: Uint32, *, loc=None, ip=None\n) -> tuple[Float32, Float32, Float32, Float32]:\n \"\"\"Convert 4 packed E4M3 bytes (in a uint32) to 4 float32 values.\n\n Uses e4m3x2 → f16x2 → f32 conversion path (SM89+/PTX ISA 7.8+).\n Input: uint32 containing bytes [b0, b1, b2, b3] (low to high).\n Output: (f0, f1, f2, f3) as Float32.\n \"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32(), T.f32(), T.f32()]),\n [Uint32(packed).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 pair_lo, pair_hi;\n .reg .b32 h2_lo, h2_hi;\n .reg .b16 h0, h1, h2, h3;\n mov.b32 {pair_lo, pair_hi}, $4;\n cvt.rn.f16x2.e4m3x2 h2_lo, pair_lo;\n cvt.rn.f16x2.e4m3x2 h2_hi, pair_hi;\n mov.b32 {h0, h1}, h2_lo;\n mov.b32 {h2, h3}, h2_hi;\n cvt.f32.f16 $0, h0;\n cvt.f32.f16 $1, h1;\n cvt.f32.f16 $2, h2;\n cvt.f32.f16 $3, h3;\n }\n \"\"\",\n \"=f,=f,=f,=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n f2 = llvm.extractvalue(T.f32(), result, [2], loc=loc, ip=ip)\n f3 = llvm.extractvalue(T.f32(), result, [3], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1), Float32(f2), Float32(f3)\n\n\n@dsl_user_op\ndef cvt_f32x2_to_half2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"Pack two float32 values into a half2 (uint32 containing two fp16 values).\n\n Uses cvt.rn.f16.f32 for each value, then packs into a single uint32.\n Matches __float22half2_rn() behavior in CUDA.\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(a).ir_value(loc=loc, ip=ip),\n Float32(b).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n cvt.rn.f16.f32 h0, $1;\n cvt.rn.f16.f32 h1, $2;\n mov.b32 $0, {h0, h1};\n }\n \"\"\",\n \"=r,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef fp8_e4m3_to_f32_and_rcp(fp8_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Convert FP8 E4M3 to float32 AND compute reciprocal.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(fp8_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .u32 exp_u, mant_u;\n .reg .s32 exp_s;\n .reg .f32 exp_f, mant_f, fp8_float, result;\n\n setp.eq.u32 p_zero, $1, 0;\n and.b32 mant_u, $1, 7;\n shr.b32 exp_u, $1, 3;\n and.b32 exp_u, exp_u, 15;\n sub.s32 exp_s, exp_u, 7;\n cvt.rn.f32.s32 exp_f, exp_s;\n ex2.approx.f32 exp_f, exp_f;\n cvt.rn.f32.u32 mant_f, mant_u;\n fma.rn.f32 mant_f, mant_f, 0f3E000000, 0f3F800000;\n mul.f32 fp8_float, exp_f, mant_f;\n rcp.approx.ftz.f32 result, fp8_float;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef nvfp4_compute_output_scale(\n fp8_val: Uint32, global_scale: Float32, *, loc=None, ip=None\n) -> Float32:\n \"\"\"Compute NVFP4 output_scale matching the CUDA kernel exactly.\n\n Converts E4M3 scale factor to float via hardware f16x2 path, then computes\n rcp(float_scale * rcp(global_scale)). Returns 0 when scale is zero.\n\n This matches quantization_utils.cuh:\n SFValue = static_cast<float>(tmp);\n outputScale = rcp_approx(SFValue * rcp_approx(SFScaleVal));\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [\n Uint32(fp8_val).ir_value(loc=loc, ip=ip),\n Float32(global_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .b16 fp8_pair;\n .reg .b32 h2_32;\n .reg .b16 h_lo, h_hi;\n .reg .f32 scale_f32, rcp_gs, product, result;\n\n cvt.u16.u32 fp8_pair, $1;\n cvt.rn.f16x2.e4m3x2 h2_32, fp8_pair;\n mov.b32 {h_lo, h_hi}, h2_32;\n cvt.f32.f16 scale_f32, h_lo;\n\n rcp.approx.ftz.f32 rcp_gs, $2;\n mul.f32 product, scale_f32, rcp_gs;\n rcp.approx.ftz.f32 result, product;\n\n setp.eq.f32 p_zero, scale_f32, 0f00000000;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# UE8M0 Intrinsics (for MXFP4)\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_f32_to_ue8m0(max_val: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"\n Convert float32 max value to UE8M0 scale factor.\n\n UE8M0 is unsigned 8-bit exponent-only format:\n - value = 2^(ue8m0 - 127)\n - ue8m0 = ceil(log2(max_val)) + 127\n\n Uses lg2.approx.f32 for fast log2 approximation.\n Uses cvt.rpi (round towards positive infinity, i.e., ceiling).\n Returns value clamped to [0, 255].\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(max_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero, p_neg, p_ovf;\n .reg .f32 log2_val;\n .reg .s32 exp_int, result;\n\n // Check for zero/negative\n setp.le.f32 p_zero, $1, 0f00000000;\n\n // Compute ceil(log2(max_val)) using cvt.rpi (round towards +inf)\n lg2.approx.f32 log2_val, $1;\n cvt.rpi.s32.f32 exp_int, log2_val;\n\n // Add bias and clamp to [0, 255]\n add.s32 result, exp_int, 127;\n setp.lt.s32 p_neg, result, 0;\n setp.gt.s32 p_ovf, result, 255;\n selp.s32 result, 0, result, p_neg;\n selp.s32 result, 255, result, p_ovf;\n selp.s32 $0, 0, result, p_zero;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef ue8m0_to_output_scale(ue8m0_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"\n Convert UE8M0 to output_scale for MXFP4 quantization.\n\n UE8M0 value = 2^(ue8m0 - 127)\n Returns 1 / 2^(ue8m0 - 127) = 2^(127 - ue8m0)\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(ue8m0_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .s32 neg_exp;\n .reg .f32 neg_exp_f, result;\n\n // Check for zero\n setp.eq.u32 p_zero, $1, 0;\n\n // Compute 2^(127 - ue8m0) = 1 / 2^(ue8m0 - 127)\n sub.s32 neg_exp, 127, $1;\n cvt.rn.f32.s32 neg_exp_f, neg_exp;\n ex2.approx.f32 result, neg_exp_f;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# E2M1 Conversion\n# =============================================================================\n\n\n@dsl_user_op\ndef cvt_e2m1x8_f32(\n v0: Float32,\n v1: Float32,\n v2: Float32,\n v3: Float32,\n v4: Float32,\n v5: Float32,\n v6: Float32,\n v7: Float32,\n *,\n loc=None,\n ip=None,\n) -> Uint32:\n \"\"\"Convert eight float32 values to eight E2M1 (4-bit) values packed into uint32.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n Float32(v2).ir_value(loc=loc, ip=ip),\n Float32(v3).ir_value(loc=loc, ip=ip),\n Float32(v4).ir_value(loc=loc, ip=ip),\n Float32(v5).ir_value(loc=loc, ip=ip),\n Float32(v6).ir_value(loc=loc, ip=ip),\n Float32(v7).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 byte0, byte1, byte2, byte3;\n cvt.rn.satfinite.e2m1x2.f32 byte0, $2, $1;\n cvt.rn.satfinite.e2m1x2.f32 byte1, $4, $3;\n cvt.rn.satfinite.e2m1x2.f32 byte2, $6, $5;\n cvt.rn.satfinite.e2m1x2.f32 byte3, $8, $7;\n mov.b32 $0, {byte0, byte1, byte2, byte3};\n }\n \"\"\",\n \"=r,f,f,f,f,f,f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Warp, Block, and Cluster Reduction Utilities\n# =============================================================================\n\n\n@cute.jit\ndef warp_reduce(val, op, width: cutlass.Constexpr[int] = 32):\n \"\"\"Reduce across threads in a warp using butterfly shuffle.\"\"\"\n if cutlass.const_expr(isinstance(val, cute.TensorSSA)):\n res = cute.make_rmem_tensor(val.shape, val.dtype)\n res.store(val)\n for i in cutlass.range_constexpr(cute.size(val.shape)):\n res[i] = warp_reduce(res[i], op, width)\n return res.load()\n else:\n for i in cutlass.range_constexpr(int(math.log2(width))):\n val = op(val, cute.arch.shuffle_sync_bfly(val, offset=1 << i))\n return val\n\n\n@cute.jit\ndef block_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n init_val: Float32,\n) -> Float32:\n \"\"\"Block reduction across multiple warps using shared memory.\"\"\"\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n warps_per_row = cute.size(reduction_buffer.shape[1])\n row_idx = warp_idx // warps_per_row\n col_idx = warp_idx % warps_per_row\n\n if lane_idx == 0:\n reduction_buffer[row_idx, col_idx] = val\n cute.arch.barrier()\n\n block_reduce_val = init_val\n if lane_idx < warps_per_row:\n block_reduce_val = reduction_buffer[row_idx, lane_idx]\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef cluster_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n mbar_ptr: cute.Pointer,\n cluster_n: cutlass.Constexpr[int],\n init_val: Float32,\n) -> Float32:\n \"\"\"Cluster reduction across multiple CTAs using mbarrier.\"\"\"\n cta_rank_in_cluster = cute.arch.block_idx_in_cluster()\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n\n rows_per_block = reduction_buffer.shape[0]\n warps_per_row = reduction_buffer.shape[1][0]\n\n row_idx = warp_idx // warps_per_row\n col_idx = warp_idx % warps_per_row\n\n # Warp 0 sets up mbarrier transaction count\n if warp_idx == 0:\n with cute.arch.elect_one():\n num_warps = rows_per_block * warps_per_row\n expected_bytes = num_warps * cluster_n * 4\n cute.arch.mbarrier_arrive_and_expect_tx(mbar_ptr, expected_bytes)\n\n # Each lane < cluster_n writes to a different CTA's shared memory\n if lane_idx < cluster_n:\n store_shared_remote(\n val,\n elem_pointer(reduction_buffer, (row_idx, (col_idx, cta_rank_in_cluster))),\n mbar_ptr,\n peer_cta_rank_in_cluster=lane_idx,\n )\n\n # Wait for all cluster writes\n cute.arch.mbarrier_wait(mbar_ptr, phase=0)\n\n # Reduce across all values\n num_total = warps_per_row * cluster_n\n num_iter = cute.ceil_div(num_total, 32)\n\n block_reduce_val = init_val\n for i in cutlass.range_constexpr(num_iter):\n idx = lane_idx + i * 32\n if idx < num_total:\n block_reduce_val = op(block_reduce_val, reduction_buffer[row_idx, idx])\n\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef row_reduce(\n x: cute.TensorSSA,\n op: cute.ReductionOp,\n threads_per_row: cutlass.Constexpr[int],\n reduction_buffer: cute.Tensor,\n mbar_ptr,\n cluster_n: cutlass.Constexpr[int],\n init_val: Float32,\n):\n \"\"\"Row reduction with optional cluster support.\"\"\"\n local_val = x.reduce(op, init_val=init_val, reduction_profile=0)\n\n warp_op = {\n cute.ReductionOp.ADD: operator.add,\n cute.ReductionOp.MAX: cute.arch.fmax,\n }[op]\n warp_width = min(threads_per_row, 32)\n warp_val = warp_reduce(local_val, warp_op, width=warp_width)\n\n warps_per_row = max(threads_per_row // 32, 1)\n\n if cutlass.const_expr(warps_per_row > 1 or cluster_n > 1):\n if cutlass.const_expr(cluster_n == 1):\n return block_reduce(warp_val, warp_op, reduction_buffer, init_val)\n else:\n return cluster_reduce(\n warp_val, warp_op, reduction_buffer, mbar_ptr, cluster_n, init_val\n )\n else:\n return warp_val\n\n\n# =============================================================================\n# Predicate Utility\n# =============================================================================\n\n\n@cute.jit\ndef predicate_k(tXcX: cute.Tensor, limit: int) -> cute.Tensor:\n \"\"\"Create predicate tensor for bounds checking.\"\"\"\n tXpX = cute.make_rmem_tensor(\n cute.make_layout(\n (\n cute.size(tXcX, mode=[0, 1]),\n cute.size(tXcX, mode=[1]),\n cute.size(tXcX, mode=[2]),\n ),\n stride=(cute.size(tXcX, mode=[2]), 0, 1),\n ),\n cutlass.Boolean,\n )\n for rest_v in cutlass.range_constexpr(tXpX.shape[0]):\n for rest_k in cutlass.range_constexpr(tXpX.shape[2]):\n tXpX[rest_v, 0, rest_k] = cute.elem_less(\n tXcX[(0, rest_v), 0, rest_k][1], limit\n )\n return tXpX\n\n\n# =============================================================================\n# Helper Functions for SF Block Processing (block_size=16)\n# =============================================================================\n\n\n@cute.jit\ndef load_8_half2(\n mX: cute.Tensor, mW: cute.Tensor, row_offset: Int32, col_offset: Int32, H: int\n):\n \"\"\"Load 16 elements (8 half2 pairs) of X and W from global memory.\n\n Returns:\n x_h2: rmem_tensor of shape (8,) containing X as half2\n w_h2: rmem_tensor of shape (8,) containing W as half2\n \"\"\"\n x_h2 = cute.make_rmem_tensor((8,), Uint32)\n w_h2 = cute.make_rmem_tensor((8,), Uint32)\n\n # Load X (2 x 128-bit loads = 16 elements)\n x_ptr0 = get_ptr_as_int64(mX, row_offset * H + col_offset)\n x_ptr1 = get_ptr_as_int64(mX, row_offset * H + col_offset + Int32(8))\n x_h2[0], x_h2[1], x_h2[2], x_h2[3] = ld_global_v4_u32(x_ptr0)\n x_h2[4], x_h2[5], x_h2[6], x_h2[7] = ld_global_v4_u32(x_ptr1)\n\n # Load W (2 x 128-bit loads = 16 elements)\n w_ptr0 = get_ptr_as_int64(mW, col_offset)\n w_ptr1 = get_ptr_as_int64(mW, col_offset + Int32(8))\n w_h2[0], w_h2[1], w_h2[2], w_h2[3] = ld_global_v4_u32(w_ptr0)\n w_h2[4], w_h2[5], w_h2[6], w_h2[7] = ld_global_v4_u32(w_ptr1)\n\n return x_h2, w_h2\n\n\n@cute.jit\ndef half2_mul_8(x_h2: cute.Tensor, w_h2: cute.Tensor) -> cute.Tensor:\n \"\"\"Multiply 8 half2 pairs element-wise.\"\"\"\n xw_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n xw_h2[i] = half2_mul(x_h2[i], w_h2[i])\n return xw_h2\n\n\n@cute.jit\ndef bfloat2_mul_8(x_h2: cute.Tensor, w_h2: cute.Tensor) -> cute.Tensor:\n \"\"\"Multiply 8 bfloat2 pairs element-wise.\"\"\"\n xw_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n xw_h2[i] = bfloat2_mul(x_h2[i], w_h2[i])\n return xw_h2\n\n\n@cute.jit\ndef half2_max_abs_8(xw_h2: cute.Tensor) -> Uint32:\n \"\"\"Compute max absolute value across 8 half2 values using tree reduction.\"\"\"\n # Compute abs for all 8 values\n abs_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n abs_h2[i] = habs2(xw_h2[i])\n\n # Tree reduction: 8 -> 4 -> 2 -> 1\n max_01 = hmax2(abs_h2[0], abs_h2[1])\n max_23 = hmax2(abs_h2[2], abs_h2[3])\n max_45 = hmax2(abs_h2[4], abs_h2[5])\n max_67 = hmax2(abs_h2[6], abs_h2[7])\n max_0123 = hmax2(max_01, max_23)\n max_4567 = hmax2(max_45, max_67)\n return hmax2(max_0123, max_4567)\n\n\n@cute.jit\ndef bfloat2_max_abs_8(xw_h2: cute.Tensor) -> Uint32:\n \"\"\"Compute max absolute value across 8 bfloat2 values using tree reduction.\"\"\"\n # Compute abs for all 8 values\n abs_h2 = cute.make_rmem_tensor((8,), Uint32)\n for i in cutlass.range_constexpr(8):\n abs_h2[i] = bfloat2_habs2(xw_h2[i])\n\n # Tree reduction: 8 -> 4 -> 2 -> 1\n max_01 = bfloat2_hmax2(abs_h2[0], abs_h2[1])\n max_23 = bfloat2_hmax2(abs_h2[2], abs_h2[3])\n max_45 = bfloat2_hmax2(abs_h2[4], abs_h2[5])\n max_67 = bfloat2_hmax2(abs_h2[6], abs_h2[7])\n max_0123 = bfloat2_hmax2(max_01, max_23)\n max_4567 = bfloat2_hmax2(max_45, max_67)\n return bfloat2_hmax2(max_0123, max_4567)\n\n\n@cute.jit\ndef half2_to_float16(xw_h2: cute.Tensor, scale: Float32) -> cute.Tensor:\n \"\"\"Convert 8 half2 to 16 float32 with scaling.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(8):\n y_f32[i * 2], y_f32[i * 2 + 1] = half2_to_float2_scaled(xw_h2[i], scale)\n return y_f32\n\n\n@cute.jit\ndef bfloat2_to_float16(xw_h2: cute.Tensor, scale: Float32) -> cute.Tensor:\n \"\"\"Convert 8 bfloat2 to 16 float32 with scaling.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(8):\n y_f32[i * 2], y_f32[i * 2 + 1] = bfloat2_to_float2_scaled(xw_h2[i], scale)\n return y_f32\n\n\n@cute.jit\ndef quantize_and_pack_16(y_f32: cute.Tensor, inv_scale: Float32) -> Uint64:\n \"\"\"Quantize 16 float32 values to FP4 and pack into uint64.\"\"\"\n # Scale values\n q = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n q[i] = y_f32[i] * inv_scale\n\n # Convert to E2M1 and pack\n packed_lo = cvt_e2m1x8_f32(q[0], q[1], q[2], q[3], q[4], q[5], q[6], q[7])\n packed_hi = cvt_e2m1x8_f32(q[8], q[9], q[10], q[11], q[12], q[13], q[14], q[15])\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n# =============================================================================\n# Helper Functions for Float32 SF Block Processing\n# =============================================================================\n\n\n@cute.jit\ndef load_f32_16_from_smem(\n sH: cute.Tensor, row_idx: Int32, col_offset: Int32\n) -> cute.Tensor:\n \"\"\"Load 16 Float32 values from shared memory.\"\"\"\n h_f32 = cute.make_rmem_tensor((16,), Float32)\n for i in cutlass.range_constexpr(16):\n h_f32[i] = Float32(sH[row_idx, col_offset + i])\n return h_f32\n\n\n@cute.jit\ndef compute_y_and_max_abs_f32(\n h_f32: cute.Tensor, w_f32: cute.Tensor, rstd: Float32\n) -> Tuple[cute.Tensor, Float32]:\n \"\"\"Compute y = h * rstd * w and max_abs for 16 Float32 values.\"\"\"\n y_f32 = cute.make_rmem_tensor((16,), Float32)\n\n # Compute y and track max_abs\n y_f32[0] = h_f32[0] * rstd * w_f32[0]\n max_abs = fabs_f32(y_f32[0])\n\n for i in cutlass.range_constexpr(1, 16):\n y_f32[i] = h_f32[i] * rstd * w_f32[i]\n max_abs = fmax_f32(max_abs, fabs_f32(y_f32[i]))\n\n return y_f32, max_abs\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n**Summary**\n- Adopt dual-path kernel architecture (linear flat + swizzled row-based) for MXFP4 and NVFP4 CuTe-DSL quantization kernels.\n- Architecture chanes to MXFP8 quantization for better perf.\n- Expand benchmark scripts and test coverage across all three quantization kernels. Compares exact output match between CUDA & CuTe-DSL backends\n- **All mxfp4, mxfp8, and nvfp4 quantization have exact bitwise match in for CUDA vs. CuTe DSL backends in both the output and scaling factors.**\n\n**Kernel changes**\n`mxfp8_quantize.py`\n- Adaptive 2T/SF dispatch: 2 threads per SF block for large problems (total_sf >= 65536), 4 threads for small problems for better memory bandwidth utilization.\n- Integer UE8M0 conversion (float_to_ue8m0_fast, ue8m0_to_inv_scale_fast): replaces SFU-based lg2.approx/ex2.approx with integer bit manipulation, freeing the SFU pipeline\n- reduce_max_2threads: 1-shuffle XOR reduction for the 2T path\n- Remove unused self.dtype and self.K attributes \n \n`mxfp4_quantize.py`\n- Add swizzled kernel. Previously only supported linear layout. \n- Swizzled kernel: small-K multi-row path and large-K column-loop path, compile-time selected via const_expr(needs_col_loop)\n- Inline padding for swizzled layout (row and column) — eliminates the expensive separate flat-iteration padding passes that caused 5x+ regression at small M \n- Dynamic thread count via _compute_optimal_threads(K) for 100% thread utilization \n \n`nvfp4_quantize.py`\n- Same dual-path split: NVFP4QuantizeLinearKernel + NVFP4QuantizeSwizzledKernel \n- Supports all three SF layouts (128x4, 8x4, linear) with compile-time dispatch \n- Remove unused self.row_tile_size and self.ROW_ITERATIONS from TMA kernel \n \n `quantization_cute_dsl_utils.py`\n- ue8m0_to_inv_scale_fast: integer bit construction replacing ex2.approx \n- reduce_max_2threads: 1-shuffle reduction for 2T/SF MXFP8 path \n- 2T/SF constants: ELTS_PER_THREAD, THREADS_PER_SF, SF_BLOCKS_PER_WARP + legacy 4T variants \n- MXFP8_2T_SF_THRESHOLD = 65536 \n\n**Test changes**\n- `test_fp4_quantize.py` and `test_fp8_quantize.py`: Add more problem sizes. \n- `test_fp4_quantize_padding.py`: Add both-backend parametrization and CUDA-vs-CuTe-DSL parity test for linear layout padding.\n\n**Perf comparison between backends on B200**\n\n<details>\n <summary>Click to see mxfp8 performance comparison</summary>\n\nLinear (gmean 1.42x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp8_backend_comparison_linear_bfloat16\" src=\"https://github.com/user-attachments/assets/21b630ff-d1a7-427b-9e59-5b6417c498c6\" />\n\nSwizzled (gmean 1.37x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp8_backend_comparison_swizzled_bfloat16\" src=\"https://github.com/user-attachments/assets/f9d19958-df34-4fc9-8351-6b9348aba8c6\" />\n\n\n</details>\n\n<details>\n <summary>Click to see mxfp4 performance comparison</summary>\n\nLinear (gmean 1.41x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp4_quantize_backend_comparison_linear_bfloat16\" src=\"https://github.com/user-attachments/assets/e050a38d-600e-43c1-92eb-f0b51e22accf\" />\n\n\nSwizzled (gmean 1.39x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp4_quantize_backend_comparison_swizzled_bfloat16\" src=\"https://github.com/user-attachments/assets/d4e4cd72-baad-4057-9523-63cd6665bf6e\" />\n\n</details>\n\n<details>\n <summary>Click to see nvfp4 performance comparison</summary>\n\nLinear (gmean 1.34x)\n\n<img width=\"1644\" height=\"1477\" alt=\"nvfp4_quantize_backend_comparison_linear_bfloat16\" src=\"https://github.com/user-attachments/assets/532ef7f2-0a41-406c-8eda-0f16436672c1\" />\n\n\nSwizzled (gmean 1.32x)\n\n<img width=\"1644\" height=\"1477\" alt=\"nvfp4_quantize_backend_comparison_swizzled_bfloat16\" src=\"https://github.com/user-attachments/assets/9694e1d3-e92e-45c9-81b5-527dca4e6cd1\" />\n\n\n</details>\n\n<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Benchmarks now run and report both linear and swizzled scale-factor layouts separately, generating distinct heatmaps/tables and layout-aware labels.\n * Added a new NVFP4 quantization benchmark with bandwidth and comparison modes.\n\n* **Refactor**\n * Quantize kernels split into layout-specific implementations and introduced dual-mode threading optimizations for better performance across sizes.\n\n* **Tests**\n * Expanded parameter sweeps, added backend parameterization, and capability-aware skips.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Linear\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.42, \"speedup\": 1.42}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Swizzled\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.37, \"speedup\": 1.37}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Linear\", \"batch_matrix\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.41, \"speedup\": 1.41}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Swizzled\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.39, \"speedup\": 1.39}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Linear\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.34, \"speedup\": 1.34}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Swizzled\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.32, \"speedup\": 1.32}]"},"kernel_speedup":{"kind":"number","value":1.38,"string":"1.38"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1171,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"d476c61c3f8bcbbca30755b330a0c10b141dede3"},"date":{"kind":"string","value":"2026-04-01T12:08:51-07:00"},"pr_number":{"kind":"number","value":2904,"string":"2,904"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2904"},"title":{"kind":"string","value":"perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904)"},"message":{"kind":"string","value":"perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n**Summary**\n- Adopt dual-path kernel architecture (linear flat + swizzled row-based)\nfor MXFP4 and NVFP4 CuTe-DSL quantization kernels.\n- Architecture chanes to MXFP8 quantization for better perf.\n- Expand benchmark scripts and test coverage across all three\nquantization kernels. Compares exact output match between CUDA &\nCuTe-DSL backends\n- **All mxfp4, mxfp8, and nvfp4 quantization have exact bitwise match in\nfor CUDA vs. CuTe DSL backends in both the output and scaling factors.**\n\n**Kernel changes**\n`mxfp8_quantize.py`\n- Adaptive 2T/SF dispatch: 2 threads per SF block for large problems\n(total_sf >= 65536), 4 threads for small problems for better memory\nbandwidth utilization.\n- Integer UE8M0 conversion (float_to_ue8m0_fast,\nue8m0_to_inv_scale_fast): replaces SFU-based lg2.approx/ex2.approx with\ninteger bit manipulation, freeing the SFU pipeline\n- reduce_max_2threads: 1-shuffle XOR reduction for the 2T path\n- Remove unused self.dtype and self.K attributes \n`mxfp4_quantize.py`\n- Add swizzled kernel. Previously only supported linear layout.\n- Swizzled kernel: small-K multi-row path and large-K column-loop path,\ncompile-time selected via const_expr(needs_col_loop)\n- Inline padding for swizzled layout (row and column) — eliminates the\nexpensive separate flat-iteration padding passes that caused 5x+\nregression at small M\n- Dynamic thread count via _compute_optimal_threads(K) for 100% thread\nutilization\n`nvfp4_quantize.py`\n- Same dual-path split: NVFP4QuantizeLinearKernel +\nNVFP4QuantizeSwizzledKernel\n- Supports all three SF layouts (128x4, 8x4, linear) with compile-time\ndispatch\n- Remove unused self.row_tile_size and self.ROW_ITERATIONS from TMA\nkernel\n `quantization_cute_dsl_utils.py`\n- ue8m0_to_inv_scale_fast: integer bit construction replacing ex2.approx\n- reduce_max_2threads: 1-shuffle reduction for 2T/SF MXFP8 path\n- 2T/SF constants: ELTS_PER_THREAD, THREADS_PER_SF, SF_BLOCKS_PER_WARP +\nlegacy 4T variants\n- MXFP8_2T_SF_THRESHOLD = 65536 \n\n**Test changes**\n- `test_fp4_quantize.py` and `test_fp8_quantize.py`: Add more problem\nsizes.\n- `test_fp4_quantize_padding.py`: Add both-backend parametrization and\nCUDA-vs-CuTe-DSL parity test for linear layout padding.\n\n**Perf comparison between backends on B200**\n\n<details>\n <summary>Click to see mxfp8 performance comparison</summary>\n\nLinear (gmean 1.42x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"mxfp8_backend_comparison_linear_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/21b630ff-d1a7-427b-9e59-5b6417c498c6\"\n/>\n\nSwizzled (gmean 1.37x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"mxfp8_backend_comparison_swizzled_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/f9d19958-df34-4fc9-8351-6b9348aba8c6\"\n/>\n\n\n</details>\n\n<details>\n <summary>Click to see mxfp4 performance comparison</summary>\n\nLinear (gmean 1.41x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"mxfp4_quantize_backend_comparison_linear_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/e050a38d-600e-43c1-92eb-f0b51e22accf\"\n/>\n\n\nSwizzled (gmean 1.39x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"mxfp4_quantize_backend_comparison_swizzled_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/d4e4cd72-baad-4057-9523-63cd6665bf6e\"\n/>\n\n</details>\n\n<details>\n <summary>Click to see nvfp4 performance comparison</summary>\n\nLinear (gmean 1.34x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"nvfp4_quantize_backend_comparison_linear_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/532ef7f2-0a41-406c-8eda-0f16436672c1\"\n/>\n\n\nSwizzled (gmean 1.32x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"nvfp4_quantize_backend_comparison_swizzled_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/9694e1d3-e92e-45c9-81b5-527dca4e6cd1\"\n/>\n\n\n</details>\n\n<!-- What does this PR do? Briefly describe the changes and why they’re\nneeded. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* Benchmarks now run and report both linear and swizzled scale-factor\nlayouts separately, generating distinct heatmaps/tables and layout-aware\nlabels.\n* Added a new NVFP4 quantization benchmark with bandwidth and comparison\nmodes.\n\n* **Refactor**\n* Quantize kernels split into layout-specific implementations and\nintroduced dual-mode threading optimizations for better performance\nacross sizes.\n\n* **Tests**\n* Expanded parameter sweeps, added backend parameterization, and\ncapability-aware skips.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"flashinfer/quantization/kernels/mxfp8_quantize.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nMXFP8 Quantization using CuTe-DSL\n=================================\n\nHigh-performance MXFP8 quantization kernel using CuTe-DSL.\nSupports both linear and swizzled (128x4) scale factor layouts.\n\nKey features:\n- Half2/BFloat2 SIMD for max-abs computation\n- 4-thread cooperation per scale factor block\n- Dual-path optimization: linear layout (SF-block based) and swizzled layout (row-based)\n- Vectorized 128-bit global loads/stores\n- M-agnostic compilation: kernels are compiled once per K dimension\n\"\"\"\n\nimport functools\nfrom typing import Callable, Tuple\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Uint8\n\nfrom ...api_logging import flashinfer_api\nfrom ...cute_dsl.fp4_common import (\n ld_global_v4_u32,\n st_global_u64,\n get_ptr_as_int64,\n)\nfrom ...cute_dsl.utils import get_num_sm\nfrom ..quantization_cute_dsl_utils import (\n # Constants\n SF_VEC_SIZE,\n INV_FLOAT8_E4M3_MAX,\n WARP_SIZE,\n ELTS_PER_THREAD,\n THREADS_PER_SF,\n SF_BLOCKS_PER_WARP,\n ROW_TILE_SIZE,\n # Low-level intrinsics\n hmax_reduce_to_f32,\n bfloat2_hmax_reduce_to_f32,\n float_to_ue8m0_fast,\n ue8m0_to_inv_scale_fast,\n reduce_max_4threads,\n compute_sf_index_swizzled_128x4_gpu,\n # High-level helpers\n half2_max_abs_4,\n bfloat2_max_abs_4,\n half2x4_to_fp8x8_packed,\n bfloat2x4_to_fp8x8_packed,\n)\n\n\n# Blocks per SM for occupancy target\n_BLOCKS_PER_SM = 4\n\n# Maximum threads per block (all modern NVIDIA GPUs support 1024)\n_MAX_THREADS_PER_BLOCK = 1024\n\n\n# Warp configuration bounds\n_MIN_WARPS = 4 # Minimum for reasonable occupancy (128 threads)\n_MAX_WARPS = 32 # Maximum to avoid register pressure (1024 threads)\n_DEFAULT_WARPS = 16 # Default when no optimization needed\n\n\ndef _compute_optimal_warps_for_k(K: int) -> int:\n \"\"\"\n Compute optimal WARPS_PER_BLOCK for 100% thread utilization.\n\n For the swizzled kernel, we need:\n (WARPS × 8) % num_sf_blocks == 0\n\n where num_sf_blocks = K / 32.\n\n This ensures that col_units_per_block is evenly divisible by\n num_sf_blocks_per_row, so all threads are utilized.\n\n We prefer LARGER warp counts (up to _MAX_WARPS) for better occupancy,\n while maintaining 100% thread utilization.\n\n Args:\n K: Number of columns (must be divisible by 32)\n\n Returns:\n Optimal number of warps per block\n \"\"\"\n import math\n\n num_sf_blocks = K // SF_VEC_SIZE # K / 32\n\n # For 100% utilization: (WARPS * 8) % num_sf_blocks == 0\n # WARPS must be a multiple of: num_sf_blocks / gcd(num_sf_blocks, 8)\n gcd_val = math.gcd(num_sf_blocks, 8)\n warp_multiple = num_sf_blocks // gcd_val\n\n # Find LARGEST valid WARPS in range [_MIN_WARPS, _MAX_WARPS]\n # that is a multiple of warp_multiple (for best occupancy)\n if warp_multiple <= _MAX_WARPS:\n # Find largest multiple of warp_multiple that fits in [_MIN_WARPS, _MAX_WARPS]\n warps = (_MAX_WARPS // warp_multiple) * warp_multiple\n if warps >= _MIN_WARPS:\n return warps\n # If largest multiple is below _MIN_WARPS, use the smallest valid one\n warps = warp_multiple\n while warps < _MIN_WARPS:\n warps += warp_multiple\n if warps <= _MAX_WARPS:\n return warps\n\n # If warp_multiple is too large, fall back to default\n # This shouldn't happen for reasonable K values\n return _DEFAULT_WARPS\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Linear Layout\n# =============================================================================\n\n\nclass MXFP8QuantizeLinearKernel:\n \"\"\"\n MXFP8 quantization kernel optimized for LINEAR layout.\n Uses SF-block based iteration for efficient memory access.\n\n This kernel is M-agnostic: compiled once per (K, dtype, pdl) combination.\n M-dependent values (total_sf_blocks, num_blocks) are passed at runtime.\n \"\"\"\n\n WARPS_PER_BLOCK = 16 # 16 warps = 512 threads per block\n SF_BLOCKS_PER_TB = WARPS_PER_BLOCK * SF_BLOCKS_PER_WARP\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n enable_pdl: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.enable_pdl = enable_pdl\n\n assert K % SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // SF_VEC_SIZE\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n total_sf_blocks: Int32,\n num_blocks: Int32,\n stream,\n ):\n threads_per_block = self.WARPS_PER_BLOCK * WARP_SIZE\n\n self.kernel(mInput, mOutput, mScales, total_sf_blocks).launch(\n grid=[num_blocks, 1, 1],\n block=[threads_per_block, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n total_sf_blocks: Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n warp_idx = tidx // WARP_SIZE\n lane_idx = tidx % WARP_SIZE\n\n sf_idx_in_warp = lane_idx // THREADS_PER_SF\n thread_in_sf = lane_idx % THREADS_PER_SF\n\n sf_blocks_per_tb = self.WARPS_PER_BLOCK * SF_BLOCKS_PER_WARP\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n\n sf_idx_base = (\n bidx * sf_blocks_per_tb + warp_idx * SF_BLOCKS_PER_WARP + sf_idx_in_warp\n )\n\n sf_idx = sf_idx_base\n while sf_idx < total_sf_blocks:\n row_idx = sf_idx // num_sf_blocks_per_row\n col_idx = sf_idx % num_sf_blocks_per_row\n\n base_elem = col_idx * SF_VEC_SIZE\n thread_elem_offset = thread_in_sf * ELTS_PER_THREAD\n elem_idx = base_elem + thread_elem_offset\n\n row_input = mInput[row_idx, None]\n input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n\n v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n\n # Compute max absolute value across 8 elements (4 half2/bfloat2)\n if cutlass.const_expr(self.is_bfloat16):\n max0123 = bfloat2_max_abs_4(v0, v1, v2, v3)\n local_max = bfloat2_hmax_reduce_to_f32(max0123)\n else:\n max0123 = half2_max_abs_4(v0, v1, v2, v3)\n local_max = hmax_reduce_to_f32(max0123)\n\n # 4-thread reduction for this SF block\n global_max = reduce_max_4threads(local_max)\n\n # Compute UE8M0 scale factor\n inv_e4m3_max = Float32(INV_FLOAT8_E4M3_MAX)\n normalized_max = global_max * inv_e4m3_max\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0 = scale_ue8m0_u32.to(Uint8)\n\n # Compute inverse scale for quantization\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n\n # Quantize to FP8 E4M3 and pack for vectorized store\n if cutlass.const_expr(self.is_bfloat16):\n fp8_packed = bfloat2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n else:\n fp8_packed = half2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n\n row_output = mOutput[row_idx, None]\n output_ptr_i64 = get_ptr_as_int64(row_output, elem_idx)\n st_global_u64(output_ptr_i64, fp8_packed)\n\n if thread_in_sf == Int32(0):\n mScales[sf_idx] = scale_ue8m0\n\n sf_idx = sf_idx + grid_dim_x * sf_blocks_per_tb\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Swizzled Layout\n# =============================================================================\n\n\nclass MXFP8QuantizeSwizzledKernel:\n \"\"\"\n MXFP8 quantization kernel optimized for SWIZZLED layout.\n\n Key optimizations:\n - Multi-row processing: threads process multiple rows per block when K is small\n - Row-based iteration with grid-stride loop\n - Padding row fast path - only zero out scale factors\n\n Thread utilization optimization:\n - Dynamic WARPS_PER_BLOCK based on K for 100% thread utilization\n - For small K: Multiple rows processed per block iteration\n - For large K: Single row with column loop\n\n This kernel is M-agnostic: compiled once per (K, dtype, pdl) combination.\n M-dependent values (M, padded_M) are passed at runtime.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n enable_pdl: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.enable_pdl = enable_pdl\n\n assert K % SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // SF_VEC_SIZE\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n # Compute optimal warps for 100% thread utilization\n self.warps_per_block = _compute_optimal_warps_for_k(K)\n\n # Multi-row processing constants (compile-time)\n threads_per_block = self.warps_per_block * WARP_SIZE\n col_units_per_block = threads_per_block // THREADS_PER_SF\n\n # threads_per_row = num_sf_blocks_per_row * THREADS_PER_SF = K / 8\n self.threads_per_row = self.num_sf_blocks_per_row * THREADS_PER_SF\n\n # rows_per_block = col_units_per_block // num_sf_blocks_per_row\n # With optimal warps, this should divide evenly for small K\n if self.num_sf_blocks_per_row <= col_units_per_block:\n self.rows_per_block = col_units_per_block // self.num_sf_blocks_per_row\n self.needs_col_loop = False\n else:\n self.rows_per_block = 1\n self.needs_col_loop = True\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n stream,\n ):\n threads_per_block = self.warps_per_block * WARP_SIZE\n\n self.kernel(mInput, mOutput, mScales, M, padded_M).launch(\n grid=[num_blocks, 1, 1],\n block=[threads_per_block, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n ):\n \"\"\"\n Multi-row kernel for swizzled layout.\n\n When K is small: each block processes multiple rows simultaneously.\n When K is large: each block processes one row with column loop.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Compile-time constants\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n threads_per_row = self.threads_per_row\n rows_per_block = self.rows_per_block\n\n if cutlass.const_expr(self.needs_col_loop):\n # Large K path: single row per block iteration with column loop\n # This is the original algorithm for K > 4096\n col_unit_idx = tidx // THREADS_PER_SF\n thread_in_unit = tidx % THREADS_PER_SF\n threads_per_block = self.warps_per_block * WARP_SIZE\n col_units_per_block = threads_per_block // THREADS_PER_SF\n\n row_idx = bidx\n while row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - only zero out scale factors\n sf_col_idx = col_unit_idx\n while sf_col_idx < padded_sf_cols:\n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + col_units_per_block\n else:\n # Normal path: process actual data row with column loop\n sf_col_idx = col_unit_idx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_idx = (\n sf_col_idx * SF_VEC_SIZE + thread_in_unit * ELTS_PER_THREAD\n )\n\n row_input = mInput[row_idx, None]\n input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n\n if cutlass.const_expr(self.is_bfloat16):\n max0123 = bfloat2_max_abs_4(v0, v1, v2, v3)\n local_max = bfloat2_hmax_reduce_to_f32(max0123)\n else:\n max0123 = half2_max_abs_4(v0, v1, v2, v3)\n local_max = hmax_reduce_to_f32(max0123)\n\n global_max = reduce_max_4threads(local_max)\n inv_e4m3_max = Float32(INV_FLOAT8_E4M3_MAX)\n normalized_max = global_max * inv_e4m3_max\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0 = scale_ue8m0_u32.to(Uint8)\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n\n if cutlass.const_expr(self.is_bfloat16):\n fp8_packed = bfloat2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n else:\n fp8_packed = half2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n\n row_output = mOutput[row_idx, None]\n output_ptr_i64 = get_ptr_as_int64(row_output, elem_idx)\n st_global_u64(output_ptr_i64, fp8_packed)\n\n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = scale_ue8m0\n\n sf_col_idx = sf_col_idx + col_units_per_block\n\n # Handle padding columns\n sf_col_idx = num_sf_blocks_per_row + col_unit_idx\n while sf_col_idx < padded_sf_cols:\n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + col_units_per_block\n\n row_idx = row_idx + grid_dim_x\n else:\n # Small K path: multi-row processing (K <= 4096)\n # Each block processes rows_per_block rows simultaneously\n # Thread mapping: tidx -> (row_in_block, sf_col_idx, thread_in_unit)\n row_in_block = tidx // threads_per_row\n local_tidx = tidx % threads_per_row\n sf_col_idx = local_tidx // THREADS_PER_SF\n thread_in_unit = local_tidx % THREADS_PER_SF\n\n # Grid-stride loop over row batches\n row_batch_idx = bidx\n # Initialize row_idx before while loop (CuTe DSL requires variables\n # modified in while loops to be defined before the loop)\n row_idx = row_batch_idx * rows_per_block + row_in_block\n while row_batch_idx * rows_per_block < padded_M:\n # Check if this thread's row is valid\n if row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - zero out scale factors\n # Each thread handles one SF column (no column loop needed)\n if sf_col_idx < padded_sf_cols and thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n else:\n # Normal path: process actual data\n if sf_col_idx < num_sf_blocks_per_row:\n elem_idx = (\n sf_col_idx * SF_VEC_SIZE\n + thread_in_unit * ELTS_PER_THREAD\n )\n\n row_input = mInput[row_idx, None]\n input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n\n if cutlass.const_expr(self.is_bfloat16):\n max0123 = bfloat2_max_abs_4(v0, v1, v2, v3)\n local_max = bfloat2_hmax_reduce_to_f32(max0123)\n else:\n max0123 = half2_max_abs_4(v0, v1, v2, v3)\n local_max = hmax_reduce_to_f32(max0123)\n\n global_max = reduce_max_4threads(local_max)\n inv_e4m3_max = Float32(INV_FLOAT8_E4M3_MAX)\n normalized_max = global_max * inv_e4m3_max\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0 = scale_ue8m0_u32.to(Uint8)\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n\n if cutlass.const_expr(self.is_bfloat16):\n fp8_packed = bfloat2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n else:\n fp8_packed = half2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n\n row_output = mOutput[row_idx, None]\n output_ptr_i64 = get_ptr_as_int64(row_output, elem_idx)\n st_global_u64(output_ptr_i64, fp8_packed)\n\n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = scale_ue8m0\n\n # Handle padding SF columns (for this row)\n # Threads with sf_col_idx in [num_sf_blocks_per_row, padded_sf_cols)\n if (\n sf_col_idx >= num_sf_blocks_per_row\n and sf_col_idx < padded_sf_cols\n and thread_in_unit == Int32(0)\n ):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n\n row_batch_idx = row_batch_idx + grid_dim_x\n # Update row_idx for next iteration\n row_idx = row_batch_idx * rows_per_block + row_in_block\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# PyTorch Integration with TVM-FFI\n# =============================================================================\n\n\n@functools.cache\ndef _get_compiled_kernel_linear(\n is_bfloat16: bool,\n K: int,\n enable_pdl: bool = False,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile LINEAR layout kernel with TVM-FFI.\n\n Cached by (K, dtype, pdl) - M-agnostic, device-independent compilation.\n\n Returns:\n Tuple of (compiled_kernel, sf_blocks_per_tb) where sf_blocks_per_tb\n is used by the caller to compute num_blocks at runtime.\n \"\"\"\n cutlass_dtype = cutlass.BFloat16 if is_bfloat16 else cutlass.Float16\n kernel_obj = MXFP8QuantizeLinearKernel(cutlass_dtype, K, enable_pdl)\n\n # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n\n # Create fake tensors for compilation\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy total_sf_blocks\n Int32(1), # Dummy num_blocks\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, kernel_obj.SF_BLOCKS_PER_TB\n\n\n@functools.cache\ndef _get_compiled_kernel_swizzled(\n is_bfloat16: bool,\n K: int,\n enable_pdl: bool = False,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile SWIZZLED layout kernel with TVM-FFI.\n\n Cached by (K, dtype, pdl) - M-agnostic, device-independent compilation.\n\n Returns:\n Tuple of (compiled_kernel, rows_per_block) where rows_per_block\n is used by the caller to compute num_blocks at runtime.\n \"\"\"\n cutlass_dtype = cutlass.BFloat16 if is_bfloat16 else cutlass.Float16\n kernel_obj = MXFP8QuantizeSwizzledKernel(cutlass_dtype, K, enable_pdl)\n\n # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n\n # Create fake tensors for compilation\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(128), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, kernel_obj.rows_per_block\n\n\n@flashinfer_api\ndef mxfp8_quantize_cute_dsl(\n input: torch.Tensor,\n is_sf_swizzled_layout: bool = True,\n alignment: int = 32,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n \"\"\"\n Quantize input tensor to MXFP8 format using CuTe-DSL kernel.\n\n This is a GPU implementation with dual-path optimization:\n - LINEAR layout: SF-block based iteration (fast)\n - SWIZZLED layout: Row-based iteration with padding fast path (optimized)\n\n The kernel is compiled once per (K, dtype, pdl) combination and handles\n varying M (batch size) at runtime without recompilation.\n\n Args:\n input: Input tensor of shape [M, K] with dtype fp16/bf16\n is_sf_swizzled_layout: Whether to use 128x4 swizzled layout (True) or linear (False)\n alignment: Alignment for K dimension (default 32, must be multiple of SF_VEC_SIZE)\n enable_pdl: Whether to enable PDL (Programmatic Dependent Launch).\n If None, automatically detects based on device capability (SM >= 9.0).\n\n Returns:\n Tuple of:\n - fp8_tensor: Quantized tensor of shape [M, padded_K] with dtype float8_e4m3fn\n - scale_tensor: Scale factors as uint8 tensor\n \"\"\"\n from ...utils import device_support_pdl\n\n assert input.dtype in (torch.float16, torch.bfloat16), (\n f\"Input dtype must be float16 or bfloat16, got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n assert alignment % SF_VEC_SIZE == 0, (\n f\"alignment must be divisible by SF_VEC_SIZE={SF_VEC_SIZE}\"\n )\n\n # Auto-detect PDL support based on device capability\n if enable_pdl is None:\n enable_pdl = device_support_pdl(input.device)\n\n if input.dim() > 2:\n m = input.numel() // input.shape[-1]\n k = input.shape[-1]\n input = input.reshape(m, k)\n else:\n m, k = input.shape\n\n assert k % SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by SF_VEC_SIZE={SF_VEC_SIZE}\"\n )\n\n padded_k = ((k + alignment - 1) // alignment) * alignment\n\n if padded_k > k:\n # Pad input with zeros - padding columns must be zero to produce zero FP8 output\n input_padded = torch.zeros(m, padded_k, dtype=input.dtype, device=input.device)\n input_padded[:, :k] = input\n else:\n input_padded = input.contiguous()\n\n is_bfloat16 = input.dtype == torch.bfloat16\n\n # Cached device-specific target grid for grid size computation\n target_grid = get_num_sm(input.device) * _BLOCKS_PER_SM\n\n # Compute M-dependent values outside the cached kernel\n num_sf_blocks_per_row = padded_k // SF_VEC_SIZE\n\n if is_sf_swizzled_layout:\n # Swizzled layout: compute padded_M and scale_output_size\n padded_m = ((m + ROW_TILE_SIZE - 1) // ROW_TILE_SIZE) * ROW_TILE_SIZE\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n scale_output_size = padded_m * padded_sf_cols\n\n kernel_fn, rows_per_block = _get_compiled_kernel_swizzled(\n is_bfloat16, padded_k, enable_pdl\n )\n\n num_blocks = min((padded_m + rows_per_block - 1) // rows_per_block, target_grid)\n\n fp8_output = torch.empty(m, padded_k, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(input_padded, fp8_output, scale_output, m, padded_m, num_blocks)\n else:\n # Linear layout: compute total_sf_blocks\n total_sf_blocks = m * num_sf_blocks_per_row\n scale_output_size = total_sf_blocks\n\n kernel_fn, sf_blocks_per_tb = _get_compiled_kernel_linear(\n is_bfloat16, padded_k, enable_pdl\n )\n\n num_blocks = min(\n (total_sf_blocks + sf_blocks_per_tb - 1) // sf_blocks_per_tb, target_grid\n )\n\n fp8_output = torch.empty(m, padded_k, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(input_padded, fp8_output, scale_output, total_sf_blocks, num_blocks)\n\n fp8_tensor = fp8_output.view(torch.float8_e4m3fn)\n\n return fp8_tensor, scale_output\n\n\n__all__ = [\n \"MXFP8QuantizeLinearKernel\",\n \"MXFP8QuantizeSwizzledKernel\",\n \"mxfp8_quantize_cute_dsl\",\n \"_get_compiled_kernel_linear\",\n \"_get_compiled_kernel_swizzled\",\n]\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nMXFP8 Quantization using CuTe-DSL\n=================================\n\nHigh-performance MXFP8 quantization kernel using CuTe-DSL.\nSupports both linear and swizzled (128x4) scale factor layouts.\n\nKey features:\n- Half2/BFloat2 SIMD for max-abs computation\n- 4-thread cooperation per scale factor block\n- Dual-path optimization: linear layout (SF-block based) and swizzled layout (row-based)\n- Vectorized 128-bit global loads/stores\n- M-agnostic compilation: kernels are compiled once per K dimension\n\"\"\"\n\nimport functools\nfrom typing import Callable, Tuple\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Uint8\n\nfrom ...api_logging import flashinfer_api\nfrom ...cute_dsl.fp4_common import (\n ld_global_v4_u32,\n st_global_u64,\n get_ptr_as_int64,\n)\nfrom ...cute_dsl.utils import get_num_sm\nfrom ..quantization_cute_dsl_utils import (\n # Constants\n SF_VEC_SIZE,\n INV_FLOAT8_E4M3_MAX,\n WARP_SIZE,\n ELTS_PER_THREAD,\n THREADS_PER_SF,\n SF_BLOCKS_PER_WARP,\n ELTS_PER_THREAD_SMALL,\n THREADS_PER_SF_SMALL,\n SF_BLOCKS_PER_WARP_SMALL,\n MXFP8_2T_SF_THRESHOLD,\n ROW_TILE_SIZE,\n # Low-level intrinsics\n hmax_reduce_to_f32,\n bfloat2_hmax_reduce_to_f32,\n float_to_ue8m0_fast,\n ue8m0_to_inv_scale_fast,\n reduce_max_2threads,\n reduce_max_4threads,\n compute_sf_index_swizzled_128x4_gpu,\n # High-level helpers\n half2_max_abs_4,\n half2_max_abs_8,\n bfloat2_max_abs_4,\n bfloat2_max_abs_8,\n half2x4_to_fp8x8_packed,\n bfloat2x4_to_fp8x8_packed,\n)\n\n\n# Blocks per SM for occupancy target\n_BLOCKS_PER_SM = 4\n\n# Maximum threads per block (all modern NVIDIA GPUs support 1024)\n_MAX_THREADS_PER_BLOCK = 1024\n\n\n# Warp configuration bounds\n_MIN_WARPS = 4 # Minimum for reasonable occupancy (128 threads)\n_MAX_WARPS = 32 # Maximum to avoid register pressure (1024 threads)\n_DEFAULT_WARPS = 16 # Default when no optimization needed\n\n\ndef _compute_optimal_warps(K: int, sf_blocks_per_warp: int = SF_BLOCKS_PER_WARP) -> int:\n \"\"\"\n Compute optimal WARPS_PER_BLOCK for 100% thread utilization.\n\n For the swizzled kernel, we need:\n (WARPS x sf_blocks_per_warp) % num_sf_blocks == 0\n\n where num_sf_blocks = K / 32.\n\n This ensures that col_units_per_block is evenly divisible by\n num_sf_blocks_per_row, so all threads are utilized.\n\n We prefer LARGER warp counts (up to _MAX_WARPS) for better occupancy,\n while maintaining 100% thread utilization.\n\n Args:\n K: Number of columns (must be divisible by 32)\n sf_blocks_per_warp: SF blocks per warp for the selected thread\n configuration (16 for 2T/SF, 8 for 4T/SF)\n\n Returns:\n Optimal number of warps per block\n \"\"\"\n import math\n\n num_sf_blocks = K // SF_VEC_SIZE # K / 32\n\n # For 100% utilization: (WARPS * sf_blocks_per_warp) % num_sf_blocks == 0\n # WARPS must be a multiple of: num_sf_blocks / gcd(num_sf_blocks, sf_blocks_per_warp)\n gcd_val = math.gcd(num_sf_blocks, sf_blocks_per_warp)\n warp_multiple = num_sf_blocks // gcd_val\n\n # Find LARGEST valid WARPS in range [_MIN_WARPS, _MAX_WARPS]\n # that is a multiple of warp_multiple (for best occupancy)\n if warp_multiple <= _MAX_WARPS:\n # Find largest multiple of warp_multiple that fits in [_MIN_WARPS, _MAX_WARPS]\n warps = (_MAX_WARPS // warp_multiple) * warp_multiple\n if warps >= _MIN_WARPS:\n return warps\n # If largest multiple is below _MIN_WARPS, use the smallest valid one\n warps = warp_multiple\n while warps < _MIN_WARPS:\n warps += warp_multiple\n if warps <= _MAX_WARPS:\n return warps\n\n # If warp_multiple is too large, fall back to default\n # This shouldn't happen for reasonable K values\n return _DEFAULT_WARPS\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Linear Layout — Flat SF-Block Iteration\n# =============================================================================\n\n\nclass MXFP8QuantizeLinearKernel:\n \"\"\"\n MXFP8 quantization kernel optimized for LINEAR layout.\n\n Uses flat SF-block iteration for efficient memory access. Row and\n column indices are derived from the flat SF index via integer division.\n\n No padding passes are needed since for linear layout:\n - padded_m == m (no row padding)\n - padded_sf_cols == num_sf_blocks_per_row (no column padding)\n\n Adaptive thread configuration (compile-time selected via use_2t_per_sf):\n - 2T/SF (large problems): 2 threads per SF block, 16 elements per thread,\n 1 shuffle reduction, 16 SF blocks per warp\n - 4T/SF (small problems): 4 threads per SF block, 8 elements per thread,\n 2 shuffle reductions, 8 SF blocks per warp\n\n This kernel is M-agnostic: compiled once per (K, dtype, pdl, use_2t)\n combination.\n \"\"\"\n\n WARPS_PER_BLOCK = 16 # 16 warps = 512 threads per block\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n enable_pdl: bool = False,\n use_2t_per_sf: bool = True,\n ):\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.enable_pdl = enable_pdl\n self.use_2t_per_sf = use_2t_per_sf\n\n if use_2t_per_sf:\n self._elts_per_thread = ELTS_PER_THREAD\n self._threads_per_sf = THREADS_PER_SF\n self._sf_blocks_per_warp = SF_BLOCKS_PER_WARP\n else:\n self._elts_per_thread = ELTS_PER_THREAD_SMALL\n self._threads_per_sf = THREADS_PER_SF_SMALL\n self._sf_blocks_per_warp = SF_BLOCKS_PER_WARP_SMALL\n\n self.SF_BLOCKS_PER_TB = self.WARPS_PER_BLOCK * self._sf_blocks_per_warp\n\n assert K % SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // SF_VEC_SIZE\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n total_sf_blocks: Int32,\n num_blocks: Int32,\n stream,\n ):\n threads_per_block = self.WARPS_PER_BLOCK * WARP_SIZE\n\n self.kernel(mInput, mOutput, mScales, total_sf_blocks).launch(\n grid=[num_blocks, 1, 1],\n block=[threads_per_block, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n total_sf_blocks: Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n warp_idx = tidx // WARP_SIZE\n lane_idx = tidx % WARP_SIZE\n\n threads_per_sf = self._threads_per_sf\n sf_blocks_per_warp = self._sf_blocks_per_warp\n elts_per_thread = self._elts_per_thread\n\n sf_idx_in_warp = lane_idx // threads_per_sf\n thread_in_sf = lane_idx % threads_per_sf\n\n sf_blocks_per_tb = self.WARPS_PER_BLOCK * sf_blocks_per_warp\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n\n sf_idx_base = (\n bidx * sf_blocks_per_tb + warp_idx * sf_blocks_per_warp + sf_idx_in_warp\n )\n\n sf_idx = sf_idx_base\n while sf_idx < total_sf_blocks:\n row_idx = sf_idx // num_sf_blocks_per_row\n col_idx = sf_idx % num_sf_blocks_per_row\n\n base_elem = col_idx * SF_VEC_SIZE\n thread_elem_offset = thread_in_sf * elts_per_thread\n elem_idx = base_elem + thread_elem_offset\n\n row_input = mInput[row_idx, None]\n\n if cutlass.const_expr(self.use_2t_per_sf):\n # 2T/SF path: load 16 elements (2x128-bit), 1-shuffle reduction\n input_ptr_lo = get_ptr_as_int64(row_input, elem_idx)\n input_ptr_hi = get_ptr_as_int64(row_input, elem_idx + Int32(8))\n v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_lo)\n v4, v5, v6, v7 = ld_global_v4_u32(input_ptr_hi)\n\n if cutlass.const_expr(self.is_bfloat16):\n max_all = bfloat2_max_abs_8(v0, v1, v2, v3, v4, v5, v6, v7)\n local_max = bfloat2_hmax_reduce_to_f32(max_all)\n else:\n max_all = half2_max_abs_8(v0, v1, v2, v3, v4, v5, v6, v7)\n local_max = hmax_reduce_to_f32(max_all)\n\n global_max = reduce_max_2threads(local_max)\n else:\n # 4T/SF path: load 8 elements (1x128-bit), 2-shuffle reduction\n input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n\n if cutlass.const_expr(self.is_bfloat16):\n max0123 = bfloat2_max_abs_4(v0, v1, v2, v3)\n local_max = bfloat2_hmax_reduce_to_f32(max0123)\n else:\n max0123 = half2_max_abs_4(v0, v1, v2, v3)\n local_max = hmax_reduce_to_f32(max0123)\n\n global_max = reduce_max_4threads(local_max)\n\n # Compute UE8M0 scale factor\n inv_e4m3_max = Float32(INV_FLOAT8_E4M3_MAX)\n normalized_max = global_max * inv_e4m3_max\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0 = scale_ue8m0_u32.to(Uint8)\n\n # Compute inverse scale for quantization\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n\n # Quantize to FP8 E4M3 and pack for vectorized store\n if cutlass.const_expr(self.use_2t_per_sf):\n if cutlass.const_expr(self.is_bfloat16):\n fp8_lo = bfloat2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n fp8_hi = bfloat2x4_to_fp8x8_packed(v4, v5, v6, v7, inv_scale)\n else:\n fp8_lo = half2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n fp8_hi = half2x4_to_fp8x8_packed(v4, v5, v6, v7, inv_scale)\n\n row_output = mOutput[row_idx, None]\n st_global_u64(get_ptr_as_int64(row_output, elem_idx), fp8_lo)\n st_global_u64(get_ptr_as_int64(row_output, elem_idx + Int32(8)), fp8_hi)\n else:\n if cutlass.const_expr(self.is_bfloat16):\n fp8_packed = bfloat2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n else:\n fp8_packed = half2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n\n row_output = mOutput[row_idx, None]\n output_ptr_i64 = get_ptr_as_int64(row_output, elem_idx)\n st_global_u64(output_ptr_i64, fp8_packed)\n\n if thread_in_sf == Int32(0):\n mScales[sf_idx] = scale_ue8m0\n\n sf_idx = sf_idx + grid_dim_x * sf_blocks_per_tb\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Swizzled Layout — Row-Based Iteration\n# =============================================================================\n\n\nclass MXFP8QuantizeSwizzledKernel:\n \"\"\"\n MXFP8 quantization kernel optimized for SWIZZLED layout.\n\n Key optimizations:\n - Multi-row processing: threads process multiple rows per block when K is small\n - Row-based iteration with grid-stride loop\n - Padding row fast path - only zero out scale factors\n\n Thread utilization optimization:\n - Dynamic WARPS_PER_BLOCK based on K for 100% thread utilization\n - For small K: Multiple rows processed per block iteration\n - For large K: Single row with column loop\n\n For MXFP8, each SF block (32 elements) is processed by _threads_per_sf\n threads (2 or 4), so threads_per_row = num_sf_blocks_per_row * _threads_per_sf.\n\n This kernel is M-agnostic: compiled once per (K, dtype, pdl, use_2t)\n combination. M-dependent values (M, padded_M) are passed at runtime.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n enable_pdl: bool = False,\n use_2t_per_sf: bool = True,\n ):\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.enable_pdl = enable_pdl\n self.use_2t_per_sf = use_2t_per_sf\n\n if use_2t_per_sf:\n self._elts_per_thread = ELTS_PER_THREAD\n self._threads_per_sf = THREADS_PER_SF\n self._sf_blocks_per_warp = SF_BLOCKS_PER_WARP\n else:\n self._elts_per_thread = ELTS_PER_THREAD_SMALL\n self._threads_per_sf = THREADS_PER_SF_SMALL\n self._sf_blocks_per_warp = SF_BLOCKS_PER_WARP_SMALL\n\n assert K % SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // SF_VEC_SIZE\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n # Compute optimal warps for 100% thread utilization\n self.warps_per_block = _compute_optimal_warps(K, self._sf_blocks_per_warp)\n\n # Multi-row processing constants (compile-time)\n threads_per_block = self.warps_per_block * WARP_SIZE\n col_units_per_block = threads_per_block // self._threads_per_sf\n\n # threads_per_row = num_sf_blocks_per_row * _threads_per_sf\n self.threads_per_row = self.num_sf_blocks_per_row * self._threads_per_sf\n\n # rows_per_block = col_units_per_block // num_sf_blocks_per_row\n # With optimal warps, this should divide evenly for small K\n if self.num_sf_blocks_per_row <= col_units_per_block:\n self.rows_per_block = col_units_per_block // self.num_sf_blocks_per_row\n self.needs_col_loop = False\n else:\n self.rows_per_block = 1\n self.needs_col_loop = True\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n stream,\n ):\n threads_per_block = self.warps_per_block * WARP_SIZE\n\n self.kernel(mInput, mOutput, mScales, M, padded_M).launch(\n grid=[num_blocks, 1, 1],\n block=[threads_per_block, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n ):\n \"\"\"\n Multi-row kernel for swizzled layout.\n\n When K is small: each block processes multiple rows simultaneously.\n When K is large: each block processes one row with column loop.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Compile-time constants\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n threads_per_row = self.threads_per_row\n rows_per_block = self.rows_per_block\n\n _threads_per_sf = self._threads_per_sf\n _elts_per_thread = self._elts_per_thread\n\n if cutlass.const_expr(self.needs_col_loop):\n # Large K path: single row per block iteration with column loop\n col_unit_idx = tidx // _threads_per_sf\n thread_in_unit = tidx % _threads_per_sf\n threads_per_block = self.warps_per_block * WARP_SIZE\n col_units_per_block = threads_per_block // _threads_per_sf\n\n row_idx = bidx\n while row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - only zero out scale factors\n sf_col_idx = col_unit_idx\n while sf_col_idx < padded_sf_cols:\n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + col_units_per_block\n else:\n # Normal path: process actual data row with column loop\n sf_col_idx = col_unit_idx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_idx = (\n sf_col_idx * SF_VEC_SIZE + thread_in_unit * _elts_per_thread\n )\n\n row_input = mInput[row_idx, None]\n\n if cutlass.const_expr(self.use_2t_per_sf):\n input_ptr_lo = get_ptr_as_int64(row_input, elem_idx)\n input_ptr_hi = get_ptr_as_int64(\n row_input, elem_idx + Int32(8)\n )\n v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_lo)\n v4, v5, v6, v7 = ld_global_v4_u32(input_ptr_hi)\n if cutlass.const_expr(self.is_bfloat16):\n local_max = bfloat2_hmax_reduce_to_f32(\n bfloat2_max_abs_8(v0, v1, v2, v3, v4, v5, v6, v7)\n )\n else:\n local_max = hmax_reduce_to_f32(\n half2_max_abs_8(v0, v1, v2, v3, v4, v5, v6, v7)\n )\n global_max = reduce_max_2threads(local_max)\n else:\n input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n if cutlass.const_expr(self.is_bfloat16):\n local_max = bfloat2_hmax_reduce_to_f32(\n bfloat2_max_abs_4(v0, v1, v2, v3)\n )\n else:\n local_max = hmax_reduce_to_f32(\n half2_max_abs_4(v0, v1, v2, v3)\n )\n global_max = reduce_max_4threads(local_max)\n\n inv_e4m3_max = Float32(INV_FLOAT8_E4M3_MAX)\n normalized_max = global_max * inv_e4m3_max\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0 = scale_ue8m0_u32.to(Uint8)\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n\n row_output = mOutput[row_idx, None]\n if cutlass.const_expr(self.use_2t_per_sf):\n if cutlass.const_expr(self.is_bfloat16):\n fp8_lo = bfloat2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n fp8_hi = bfloat2x4_to_fp8x8_packed(\n v4, v5, v6, v7, inv_scale\n )\n else:\n fp8_lo = half2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n fp8_hi = half2x4_to_fp8x8_packed(\n v4, v5, v6, v7, inv_scale\n )\n st_global_u64(\n get_ptr_as_int64(row_output, elem_idx), fp8_lo\n )\n st_global_u64(\n get_ptr_as_int64(row_output, elem_idx + Int32(8)),\n fp8_hi,\n )\n else:\n if cutlass.const_expr(self.is_bfloat16):\n fp8_packed = bfloat2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n else:\n fp8_packed = half2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n st_global_u64(\n get_ptr_as_int64(row_output, elem_idx), fp8_packed\n )\n\n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = scale_ue8m0\n\n sf_col_idx = sf_col_idx + col_units_per_block\n\n # Handle padding columns\n sf_col_idx = num_sf_blocks_per_row + col_unit_idx\n while sf_col_idx < padded_sf_cols:\n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + col_units_per_block\n\n row_idx = row_idx + grid_dim_x\n else:\n # Small K path: multi-row processing (K <= 4096)\n # Each block processes rows_per_block rows simultaneously\n # Thread mapping: tidx -> (row_in_block, sf_col_idx, thread_in_unit)\n row_in_block = tidx // threads_per_row\n local_tidx = tidx % threads_per_row\n sf_col_idx = local_tidx // _threads_per_sf\n thread_in_unit = local_tidx % _threads_per_sf\n\n # Grid-stride loop over row batches\n row_batch_idx = bidx\n # Initialize row_idx before while loop (CuTe DSL requires variables\n # modified in while loops to be defined before the loop)\n row_idx = row_batch_idx * rows_per_block + row_in_block\n while row_batch_idx * rows_per_block < padded_M:\n # Check if this thread's row is valid\n if row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - zero out ALL scale factors\n # Thread-stride loop since padded_sf_cols may exceed\n # num_sf_blocks_per_row (when K/32 is not a multiple of 4)\n if thread_in_unit == Int32(0):\n pad_col = sf_col_idx\n while pad_col < padded_sf_cols:\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, pad_col, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n pad_col = pad_col + num_sf_blocks_per_row\n else:\n # Normal path: process actual data\n if sf_col_idx < num_sf_blocks_per_row:\n elem_idx = (\n sf_col_idx * SF_VEC_SIZE\n + thread_in_unit * _elts_per_thread\n )\n\n row_input = mInput[row_idx, None]\n\n if cutlass.const_expr(self.use_2t_per_sf):\n input_ptr_lo = get_ptr_as_int64(row_input, elem_idx)\n input_ptr_hi = get_ptr_as_int64(\n row_input, elem_idx + Int32(8)\n )\n v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_lo)\n v4, v5, v6, v7 = ld_global_v4_u32(input_ptr_hi)\n if cutlass.const_expr(self.is_bfloat16):\n local_max = bfloat2_hmax_reduce_to_f32(\n bfloat2_max_abs_8(\n v0, v1, v2, v3, v4, v5, v6, v7\n )\n )\n else:\n local_max = hmax_reduce_to_f32(\n half2_max_abs_8(v0, v1, v2, v3, v4, v5, v6, v7)\n )\n global_max = reduce_max_2threads(local_max)\n else:\n input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n if cutlass.const_expr(self.is_bfloat16):\n local_max = bfloat2_hmax_reduce_to_f32(\n bfloat2_max_abs_4(v0, v1, v2, v3)\n )\n else:\n local_max = hmax_reduce_to_f32(\n half2_max_abs_4(v0, v1, v2, v3)\n )\n global_max = reduce_max_4threads(local_max)\n\n inv_e4m3_max = Float32(INV_FLOAT8_E4M3_MAX)\n scale_ue8m0_u32 = float_to_ue8m0_fast(\n global_max * inv_e4m3_max\n )\n scale_ue8m0 = scale_ue8m0_u32.to(Uint8)\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n\n row_output = mOutput[row_idx, None]\n if cutlass.const_expr(self.use_2t_per_sf):\n if cutlass.const_expr(self.is_bfloat16):\n fp8_lo = bfloat2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n fp8_hi = bfloat2x4_to_fp8x8_packed(\n v4, v5, v6, v7, inv_scale\n )\n else:\n fp8_lo = half2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n fp8_hi = half2x4_to_fp8x8_packed(\n v4, v5, v6, v7, inv_scale\n )\n st_global_u64(\n get_ptr_as_int64(row_output, elem_idx), fp8_lo\n )\n st_global_u64(\n get_ptr_as_int64(row_output, elem_idx + Int32(8)),\n fp8_hi,\n )\n else:\n if cutlass.const_expr(self.is_bfloat16):\n fp8_packed = bfloat2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n else:\n fp8_packed = half2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n st_global_u64(\n get_ptr_as_int64(row_output, elem_idx), fp8_packed\n )\n\n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = scale_ue8m0\n\n # Handle padding SF columns for this row\n # Thread-stride loop starting from first padding column\n if cutlass.const_expr(\n self.num_sf_blocks_per_row != self.padded_sf_cols\n ):\n if thread_in_unit == Int32(0):\n pad_col = num_sf_blocks_per_row + sf_col_idx\n while pad_col < padded_sf_cols:\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, pad_col, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n pad_col = pad_col + num_sf_blocks_per_row\n\n row_batch_idx = row_batch_idx + grid_dim_x\n # Update row_idx for next iteration\n row_idx = row_batch_idx * rows_per_block + row_in_block\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# PyTorch Integration with TVM-FFI\n# =============================================================================\n\n\n@functools.cache\ndef _get_compiled_kernel_mxfp8_linear(\n is_bfloat16: bool,\n K: int,\n enable_pdl: bool = False,\n use_2t_per_sf: bool = True,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile LINEAR layout kernel with TVM-FFI.\n\n Cached by (K, dtype, pdl, use_2t) - M-agnostic, device-independent\n compilation.\n\n Returns:\n Tuple of (compiled_kernel, sf_blocks_per_tb) where sf_blocks_per_tb\n is used by the caller to compute num_blocks at runtime.\n \"\"\"\n cutlass_dtype = cutlass.BFloat16 if is_bfloat16 else cutlass.Float16\n kernel_obj = MXFP8QuantizeLinearKernel(cutlass_dtype, K, enable_pdl, use_2t_per_sf)\n\n # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n\n # Create fake tensors for compilation\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy total_sf_blocks\n Int32(1), # Dummy num_blocks\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, kernel_obj.SF_BLOCKS_PER_TB\n\n\n@functools.cache\ndef _get_compiled_kernel_mxfp8_swizzled(\n is_bfloat16: bool,\n K: int,\n enable_pdl: bool = False,\n use_2t_per_sf: bool = True,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile SWIZZLED layout kernel with TVM-FFI.\n\n Cached by (K, dtype, pdl, use_2t) - M-agnostic, device-independent\n compilation.\n\n Returns:\n Tuple of (compiled_kernel, rows_per_block) where rows_per_block\n is used by the caller to compute num_blocks at runtime.\n \"\"\"\n cutlass_dtype = cutlass.BFloat16 if is_bfloat16 else cutlass.Float16\n kernel_obj = MXFP8QuantizeSwizzledKernel(\n cutlass_dtype, K, enable_pdl, use_2t_per_sf\n )\n\n # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n\n # Create fake tensors for compilation\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(128), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, kernel_obj.rows_per_block\n\n\n@flashinfer_api\ndef mxfp8_quantize_cute_dsl(\n input: torch.Tensor,\n is_sf_swizzled_layout: bool = True,\n alignment: int = 32,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n \"\"\"\n Quantize input tensor to MXFP8 format using CuTe-DSL kernel.\n\n This is a GPU implementation with dual-path optimization:\n - LINEAR layout: SF-block based iteration (fast)\n - SWIZZLED layout: Row-based iteration with padding fast path (optimized)\n\n The kernel is compiled once per (K, dtype, pdl) combination and handles\n varying M (batch size) at runtime without recompilation.\n\n Args:\n input: Input tensor of shape [M, K] with dtype fp16/bf16\n is_sf_swizzled_layout: Whether to use 128x4 swizzled layout (True) or linear (False)\n alignment: Alignment for K dimension (default 32, must be multiple of SF_VEC_SIZE)\n enable_pdl: Whether to enable PDL (Programmatic Dependent Launch).\n If None, automatically detects based on device capability (SM >= 9.0).\n\n Returns:\n Tuple of:\n - fp8_tensor: Quantized tensor of shape [M, padded_K] with dtype float8_e4m3fn\n - scale_tensor: Scale factors as uint8 tensor\n \"\"\"\n from ...utils import device_support_pdl\n\n assert input.dtype in (torch.float16, torch.bfloat16), (\n f\"Input dtype must be float16 or bfloat16, got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n assert alignment % SF_VEC_SIZE == 0, (\n f\"alignment must be divisible by SF_VEC_SIZE={SF_VEC_SIZE}\"\n )\n\n # Auto-detect PDL support based on device capability.\n # If caller passes True explicitly, still check hardware support.\n enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n\n if input.dim() > 2:\n m = input.numel() // input.shape[-1]\n k = input.shape[-1]\n input = input.reshape(m, k)\n else:\n m, k = input.shape\n\n assert k % SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by SF_VEC_SIZE={SF_VEC_SIZE}\"\n )\n\n padded_k = ((k + alignment - 1) // alignment) * alignment\n\n if padded_k > k:\n # Pad input with zeros - padding columns must be zero to produce zero FP8 output\n input_padded = torch.zeros(m, padded_k, dtype=input.dtype, device=input.device)\n input_padded[:, :k] = input\n else:\n input_padded = input.contiguous()\n\n is_bfloat16 = input.dtype == torch.bfloat16\n\n # Cached device-specific target grid for grid size computation\n target_grid = get_num_sm(input.device) * _BLOCKS_PER_SM\n\n # Compute M-dependent values outside the cached kernel\n num_sf_blocks_per_row = padded_k // SF_VEC_SIZE\n\n # Choose 2T/SF (optimized) vs 4T/SF (legacy) based on problem size.\n # 2T/SF doubles memory-level parallelism per warp but halves the grid,\n # so it only helps when there are enough SF blocks to fill all SMs.\n total_sf_blocks_for_dispatch = m * num_sf_blocks_per_row\n use_2t = total_sf_blocks_for_dispatch >= MXFP8_2T_SF_THRESHOLD\n\n if is_sf_swizzled_layout:\n # Swizzled layout: compute padded_M and scale_output_size\n padded_m = ((m + ROW_TILE_SIZE - 1) // ROW_TILE_SIZE) * ROW_TILE_SIZE\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n scale_output_size = padded_m * padded_sf_cols\n\n kernel_fn, rows_per_block = _get_compiled_kernel_mxfp8_swizzled(\n is_bfloat16, padded_k, enable_pdl, use_2t\n )\n\n num_blocks = min((padded_m + rows_per_block - 1) // rows_per_block, target_grid)\n\n fp8_output = torch.empty(m, padded_k, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(input_padded, fp8_output, scale_output, m, padded_m, num_blocks)\n else:\n # Linear layout: compute total_sf_blocks\n total_sf_blocks = m * num_sf_blocks_per_row\n scale_output_size = total_sf_blocks\n\n kernel_fn, sf_blocks_per_tb = _get_compiled_kernel_mxfp8_linear(\n is_bfloat16, padded_k, enable_pdl, use_2t\n )\n\n num_blocks = min(\n (total_sf_blocks + sf_blocks_per_tb - 1) // sf_blocks_per_tb, target_grid\n )\n\n fp8_output = torch.empty(m, padded_k, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(input_padded, fp8_output, scale_output, total_sf_blocks, num_blocks)\n\n fp8_tensor = fp8_output.view(torch.float8_e4m3fn)\n\n return fp8_tensor, scale_output\n\n\n__all__ = [\n \"MXFP8QuantizeLinearKernel\",\n \"MXFP8QuantizeSwizzledKernel\",\n \"mxfp8_quantize_cute_dsl\",\n \"_get_compiled_kernel_mxfp8_linear\",\n \"_get_compiled_kernel_mxfp8_swizzled\",\n]\n"},"diff":{"kind":"string","value":"--- flashinfer/quantization/kernels/mxfp8_quantize.py\n+++ flashinfer/quantization/kernels/mxfp8_quantize.py\n@@ -50,17 +50,24 @@\n ELTS_PER_THREAD,\n THREADS_PER_SF,\n SF_BLOCKS_PER_WARP,\n+ ELTS_PER_THREAD_SMALL,\n+ THREADS_PER_SF_SMALL,\n+ SF_BLOCKS_PER_WARP_SMALL,\n+ MXFP8_2T_SF_THRESHOLD,\n ROW_TILE_SIZE,\n # Low-level intrinsics\n hmax_reduce_to_f32,\n bfloat2_hmax_reduce_to_f32,\n float_to_ue8m0_fast,\n ue8m0_to_inv_scale_fast,\n+ reduce_max_2threads,\n reduce_max_4threads,\n compute_sf_index_swizzled_128x4_gpu,\n # High-level helpers\n half2_max_abs_4,\n+ half2_max_abs_8,\n bfloat2_max_abs_4,\n+ bfloat2_max_abs_8,\n half2x4_to_fp8x8_packed,\n bfloat2x4_to_fp8x8_packed,\n )\n@@ -79,12 +86,12 @@\n _DEFAULT_WARPS = 16 # Default when no optimization needed\n \n \n-def _compute_optimal_warps_for_k(K: int) -> int:\n+def _compute_optimal_warps(K: int, sf_blocks_per_warp: int = SF_BLOCKS_PER_WARP) -> int:\n \"\"\"\n Compute optimal WARPS_PER_BLOCK for 100% thread utilization.\n \n For the swizzled kernel, we need:\n- (WARPS × 8) % num_sf_blocks == 0\n+ (WARPS x sf_blocks_per_warp) % num_sf_blocks == 0\n \n where num_sf_blocks = K / 32.\n \n@@ -96,6 +103,8 @@\n \n Args:\n K: Number of columns (must be divisible by 32)\n+ sf_blocks_per_warp: SF blocks per warp for the selected thread\n+ configuration (16 for 2T/SF, 8 for 4T/SF)\n \n Returns:\n Optimal number of warps per block\n@@ -104,9 +113,9 @@\n \n num_sf_blocks = K // SF_VEC_SIZE # K / 32\n \n- # For 100% utilization: (WARPS * 8) % num_sf_blocks == 0\n- # WARPS must be a multiple of: num_sf_blocks / gcd(num_sf_blocks, 8)\n- gcd_val = math.gcd(num_sf_blocks, 8)\n+ # For 100% utilization: (WARPS * sf_blocks_per_warp) % num_sf_blocks == 0\n+ # WARPS must be a multiple of: num_sf_blocks / gcd(num_sf_blocks, sf_blocks_per_warp)\n+ gcd_val = math.gcd(num_sf_blocks, sf_blocks_per_warp)\n warp_multiple = num_sf_blocks // gcd_val\n \n # Find LARGEST valid WARPS in range [_MIN_WARPS, _MAX_WARPS]\n@@ -129,32 +138,54 @@\n \n \n # =============================================================================\n-# CuTe-DSL Kernel Class for Linear Layout\n+# CuTe-DSL Kernel Class for Linear Layout — Flat SF-Block Iteration\n # =============================================================================\n \n \n class MXFP8QuantizeLinearKernel:\n \"\"\"\n MXFP8 quantization kernel optimized for LINEAR layout.\n- Uses SF-block based iteration for efficient memory access.\n-\n- This kernel is M-agnostic: compiled once per (K, dtype, pdl) combination.\n- M-dependent values (total_sf_blocks, num_blocks) are passed at runtime.\n+\n+ Uses flat SF-block iteration for efficient memory access. Row and\n+ column indices are derived from the flat SF index via integer division.\n+\n+ No padding passes are needed since for linear layout:\n+ - padded_m == m (no row padding)\n+ - padded_sf_cols == num_sf_blocks_per_row (no column padding)\n+\n+ Adaptive thread configuration (compile-time selected via use_2t_per_sf):\n+ - 2T/SF (large problems): 2 threads per SF block, 16 elements per thread,\n+ 1 shuffle reduction, 16 SF blocks per warp\n+ - 4T/SF (small problems): 4 threads per SF block, 8 elements per thread,\n+ 2 shuffle reductions, 8 SF blocks per warp\n+\n+ This kernel is M-agnostic: compiled once per (K, dtype, pdl, use_2t)\n+ combination.\n \"\"\"\n \n WARPS_PER_BLOCK = 16 # 16 warps = 512 threads per block\n- SF_BLOCKS_PER_TB = WARPS_PER_BLOCK * SF_BLOCKS_PER_WARP\n \n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n enable_pdl: bool = False,\n+ use_2t_per_sf: bool = True,\n ):\n- self.dtype = dtype\n- self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.enable_pdl = enable_pdl\n+ self.use_2t_per_sf = use_2t_per_sf\n+\n+ if use_2t_per_sf:\n+ self._elts_per_thread = ELTS_PER_THREAD\n+ self._threads_per_sf = THREADS_PER_SF\n+ self._sf_blocks_per_warp = SF_BLOCKS_PER_WARP\n+ else:\n+ self._elts_per_thread = ELTS_PER_THREAD_SMALL\n+ self._threads_per_sf = THREADS_PER_SF_SMALL\n+ self._sf_blocks_per_warp = SF_BLOCKS_PER_WARP_SMALL\n+\n+ self.SF_BLOCKS_PER_TB = self.WARPS_PER_BLOCK * self._sf_blocks_per_warp\n \n assert K % SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // SF_VEC_SIZE\n@@ -198,14 +229,18 @@\n warp_idx = tidx // WARP_SIZE\n lane_idx = tidx % WARP_SIZE\n \n- sf_idx_in_warp = lane_idx // THREADS_PER_SF\n- thread_in_sf = lane_idx % THREADS_PER_SF\n-\n- sf_blocks_per_tb = self.WARPS_PER_BLOCK * SF_BLOCKS_PER_WARP\n+ threads_per_sf = self._threads_per_sf\n+ sf_blocks_per_warp = self._sf_blocks_per_warp\n+ elts_per_thread = self._elts_per_thread\n+\n+ sf_idx_in_warp = lane_idx // threads_per_sf\n+ thread_in_sf = lane_idx % threads_per_sf\n+\n+ sf_blocks_per_tb = self.WARPS_PER_BLOCK * sf_blocks_per_warp\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n \n sf_idx_base = (\n- bidx * sf_blocks_per_tb + warp_idx * SF_BLOCKS_PER_WARP + sf_idx_in_warp\n+ bidx * sf_blocks_per_tb + warp_idx * sf_blocks_per_warp + sf_idx_in_warp\n )\n \n sf_idx = sf_idx_base\n@@ -214,24 +249,39 @@\n col_idx = sf_idx % num_sf_blocks_per_row\n \n base_elem = col_idx * SF_VEC_SIZE\n- thread_elem_offset = thread_in_sf * ELTS_PER_THREAD\n+ thread_elem_offset = thread_in_sf * elts_per_thread\n elem_idx = base_elem + thread_elem_offset\n \n row_input = mInput[row_idx, None]\n- input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n-\n- v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n-\n- # Compute max absolute value across 8 elements (4 half2/bfloat2)\n- if cutlass.const_expr(self.is_bfloat16):\n- max0123 = bfloat2_max_abs_4(v0, v1, v2, v3)\n- local_max = bfloat2_hmax_reduce_to_f32(max0123)\n+\n+ if cutlass.const_expr(self.use_2t_per_sf):\n+ # 2T/SF path: load 16 elements (2x128-bit), 1-shuffle reduction\n+ input_ptr_lo = get_ptr_as_int64(row_input, elem_idx)\n+ input_ptr_hi = get_ptr_as_int64(row_input, elem_idx + Int32(8))\n+ v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_lo)\n+ v4, v5, v6, v7 = ld_global_v4_u32(input_ptr_hi)\n+\n+ if cutlass.const_expr(self.is_bfloat16):\n+ max_all = bfloat2_max_abs_8(v0, v1, v2, v3, v4, v5, v6, v7)\n+ local_max = bfloat2_hmax_reduce_to_f32(max_all)\n+ else:\n+ max_all = half2_max_abs_8(v0, v1, v2, v3, v4, v5, v6, v7)\n+ local_max = hmax_reduce_to_f32(max_all)\n+\n+ global_max = reduce_max_2threads(local_max)\n else:\n- max0123 = half2_max_abs_4(v0, v1, v2, v3)\n- local_max = hmax_reduce_to_f32(max0123)\n-\n- # 4-thread reduction for this SF block\n- global_max = reduce_max_4threads(local_max)\n+ # 4T/SF path: load 8 elements (1x128-bit), 2-shuffle reduction\n+ input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n+ v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n+\n+ if cutlass.const_expr(self.is_bfloat16):\n+ max0123 = bfloat2_max_abs_4(v0, v1, v2, v3)\n+ local_max = bfloat2_hmax_reduce_to_f32(max0123)\n+ else:\n+ max0123 = half2_max_abs_4(v0, v1, v2, v3)\n+ local_max = hmax_reduce_to_f32(max0123)\n+\n+ global_max = reduce_max_4threads(local_max)\n \n # Compute UE8M0 scale factor\n inv_e4m3_max = Float32(INV_FLOAT8_E4M3_MAX)\n@@ -243,14 +293,26 @@\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n \n # Quantize to FP8 E4M3 and pack for vectorized store\n- if cutlass.const_expr(self.is_bfloat16):\n- fp8_packed = bfloat2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n+ if cutlass.const_expr(self.use_2t_per_sf):\n+ if cutlass.const_expr(self.is_bfloat16):\n+ fp8_lo = bfloat2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n+ fp8_hi = bfloat2x4_to_fp8x8_packed(v4, v5, v6, v7, inv_scale)\n+ else:\n+ fp8_lo = half2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n+ fp8_hi = half2x4_to_fp8x8_packed(v4, v5, v6, v7, inv_scale)\n+\n+ row_output = mOutput[row_idx, None]\n+ st_global_u64(get_ptr_as_int64(row_output, elem_idx), fp8_lo)\n+ st_global_u64(get_ptr_as_int64(row_output, elem_idx + Int32(8)), fp8_hi)\n else:\n- fp8_packed = half2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n-\n- row_output = mOutput[row_idx, None]\n- output_ptr_i64 = get_ptr_as_int64(row_output, elem_idx)\n- st_global_u64(output_ptr_i64, fp8_packed)\n+ if cutlass.const_expr(self.is_bfloat16):\n+ fp8_packed = bfloat2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n+ else:\n+ fp8_packed = half2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n+\n+ row_output = mOutput[row_idx, None]\n+ output_ptr_i64 = get_ptr_as_int64(row_output, elem_idx)\n+ st_global_u64(output_ptr_i64, fp8_packed)\n \n if thread_in_sf == Int32(0):\n mScales[sf_idx] = scale_ue8m0\n@@ -263,7 +325,7 @@\n \n \n # =============================================================================\n-# CuTe-DSL Kernel Class for Swizzled Layout\n+# CuTe-DSL Kernel Class for Swizzled Layout — Row-Based Iteration\n # =============================================================================\n \n \n@@ -281,8 +343,11 @@\n - For small K: Multiple rows processed per block iteration\n - For large K: Single row with column loop\n \n- This kernel is M-agnostic: compiled once per (K, dtype, pdl) combination.\n- M-dependent values (M, padded_M) are passed at runtime.\n+ For MXFP8, each SF block (32 elements) is processed by _threads_per_sf\n+ threads (2 or 4), so threads_per_row = num_sf_blocks_per_row * _threads_per_sf.\n+\n+ This kernel is M-agnostic: compiled once per (K, dtype, pdl, use_2t)\n+ combination. M-dependent values (M, padded_M) are passed at runtime.\n \"\"\"\n \n def __init__(\n@@ -290,25 +355,34 @@\n dtype: cutlass.Numeric,\n K: int,\n enable_pdl: bool = False,\n+ use_2t_per_sf: bool = True,\n ):\n- self.dtype = dtype\n- self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.enable_pdl = enable_pdl\n+ self.use_2t_per_sf = use_2t_per_sf\n+\n+ if use_2t_per_sf:\n+ self._elts_per_thread = ELTS_PER_THREAD\n+ self._threads_per_sf = THREADS_PER_SF\n+ self._sf_blocks_per_warp = SF_BLOCKS_PER_WARP\n+ else:\n+ self._elts_per_thread = ELTS_PER_THREAD_SMALL\n+ self._threads_per_sf = THREADS_PER_SF_SMALL\n+ self._sf_blocks_per_warp = SF_BLOCKS_PER_WARP_SMALL\n \n assert K % SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // SF_VEC_SIZE\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n \n # Compute optimal warps for 100% thread utilization\n- self.warps_per_block = _compute_optimal_warps_for_k(K)\n+ self.warps_per_block = _compute_optimal_warps(K, self._sf_blocks_per_warp)\n \n # Multi-row processing constants (compile-time)\n threads_per_block = self.warps_per_block * WARP_SIZE\n- col_units_per_block = threads_per_block // THREADS_PER_SF\n-\n- # threads_per_row = num_sf_blocks_per_row * THREADS_PER_SF = K / 8\n- self.threads_per_row = self.num_sf_blocks_per_row * THREADS_PER_SF\n+ col_units_per_block = threads_per_block // self._threads_per_sf\n+\n+ # threads_per_row = num_sf_blocks_per_row * _threads_per_sf\n+ self.threads_per_row = self.num_sf_blocks_per_row * self._threads_per_sf\n \n # rows_per_block = col_units_per_block // num_sf_blocks_per_row\n # With optimal warps, this should divide evenly for small K\n@@ -369,13 +443,15 @@\n threads_per_row = self.threads_per_row\n rows_per_block = self.rows_per_block\n \n+ _threads_per_sf = self._threads_per_sf\n+ _elts_per_thread = self._elts_per_thread\n+\n if cutlass.const_expr(self.needs_col_loop):\n # Large K path: single row per block iteration with column loop\n- # This is the original algorithm for K > 4096\n- col_unit_idx = tidx // THREADS_PER_SF\n- thread_in_unit = tidx % THREADS_PER_SF\n+ col_unit_idx = tidx // _threads_per_sf\n+ thread_in_unit = tidx % _threads_per_sf\n threads_per_block = self.warps_per_block * WARP_SIZE\n- col_units_per_block = threads_per_block // THREADS_PER_SF\n+ col_units_per_block = threads_per_block // _threads_per_sf\n \n row_idx = bidx\n while row_idx < padded_M:\n@@ -396,39 +472,81 @@\n sf_col_idx = col_unit_idx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_idx = (\n- sf_col_idx * SF_VEC_SIZE + thread_in_unit * ELTS_PER_THREAD\n+ sf_col_idx * SF_VEC_SIZE + thread_in_unit * _elts_per_thread\n )\n \n row_input = mInput[row_idx, None]\n- input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n- v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n-\n- if cutlass.const_expr(self.is_bfloat16):\n- max0123 = bfloat2_max_abs_4(v0, v1, v2, v3)\n- local_max = bfloat2_hmax_reduce_to_f32(max0123)\n+\n+ if cutlass.const_expr(self.use_2t_per_sf):\n+ input_ptr_lo = get_ptr_as_int64(row_input, elem_idx)\n+ input_ptr_hi = get_ptr_as_int64(\n+ row_input, elem_idx + Int32(8)\n+ )\n+ v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_lo)\n+ v4, v5, v6, v7 = ld_global_v4_u32(input_ptr_hi)\n+ if cutlass.const_expr(self.is_bfloat16):\n+ local_max = bfloat2_hmax_reduce_to_f32(\n+ bfloat2_max_abs_8(v0, v1, v2, v3, v4, v5, v6, v7)\n+ )\n+ else:\n+ local_max = hmax_reduce_to_f32(\n+ half2_max_abs_8(v0, v1, v2, v3, v4, v5, v6, v7)\n+ )\n+ global_max = reduce_max_2threads(local_max)\n else:\n- max0123 = half2_max_abs_4(v0, v1, v2, v3)\n- local_max = hmax_reduce_to_f32(max0123)\n-\n- global_max = reduce_max_4threads(local_max)\n+ input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n+ v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n+ if cutlass.const_expr(self.is_bfloat16):\n+ local_max = bfloat2_hmax_reduce_to_f32(\n+ bfloat2_max_abs_4(v0, v1, v2, v3)\n+ )\n+ else:\n+ local_max = hmax_reduce_to_f32(\n+ half2_max_abs_4(v0, v1, v2, v3)\n+ )\n+ global_max = reduce_max_4threads(local_max)\n+\n inv_e4m3_max = Float32(INV_FLOAT8_E4M3_MAX)\n normalized_max = global_max * inv_e4m3_max\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0 = scale_ue8m0_u32.to(Uint8)\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n \n- if cutlass.const_expr(self.is_bfloat16):\n- fp8_packed = bfloat2x4_to_fp8x8_packed(\n- v0, v1, v2, v3, inv_scale\n+ row_output = mOutput[row_idx, None]\n+ if cutlass.const_expr(self.use_2t_per_sf):\n+ if cutlass.const_expr(self.is_bfloat16):\n+ fp8_lo = bfloat2x4_to_fp8x8_packed(\n+ v0, v1, v2, v3, inv_scale\n+ )\n+ fp8_hi = bfloat2x4_to_fp8x8_packed(\n+ v4, v5, v6, v7, inv_scale\n+ )\n+ else:\n+ fp8_lo = half2x4_to_fp8x8_packed(\n+ v0, v1, v2, v3, inv_scale\n+ )\n+ fp8_hi = half2x4_to_fp8x8_packed(\n+ v4, v5, v6, v7, inv_scale\n+ )\n+ st_global_u64(\n+ get_ptr_as_int64(row_output, elem_idx), fp8_lo\n+ )\n+ st_global_u64(\n+ get_ptr_as_int64(row_output, elem_idx + Int32(8)),\n+ fp8_hi,\n )\n else:\n- fp8_packed = half2x4_to_fp8x8_packed(\n- v0, v1, v2, v3, inv_scale\n+ if cutlass.const_expr(self.is_bfloat16):\n+ fp8_packed = bfloat2x4_to_fp8x8_packed(\n+ v0, v1, v2, v3, inv_scale\n+ )\n+ else:\n+ fp8_packed = half2x4_to_fp8x8_packed(\n+ v0, v1, v2, v3, inv_scale\n+ )\n+ st_global_u64(\n+ get_ptr_as_int64(row_output, elem_idx), fp8_packed\n )\n-\n- row_output = mOutput[row_idx, None]\n- output_ptr_i64 = get_ptr_as_int64(row_output, elem_idx)\n- st_global_u64(output_ptr_i64, fp8_packed)\n \n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n@@ -455,8 +573,8 @@\n # Thread mapping: tidx -> (row_in_block, sf_col_idx, thread_in_unit)\n row_in_block = tidx // threads_per_row\n local_tidx = tidx % threads_per_row\n- sf_col_idx = local_tidx // THREADS_PER_SF\n- thread_in_unit = local_tidx % THREADS_PER_SF\n+ sf_col_idx = local_tidx // _threads_per_sf\n+ thread_in_unit = local_tidx % _threads_per_sf\n \n # Grid-stride loop over row batches\n row_batch_idx = bidx\n@@ -469,51 +587,100 @@\n is_padding_row = row_idx >= M\n \n if is_padding_row:\n- # Fast path: padding row - zero out scale factors\n- # Each thread handles one SF column (no column loop needed)\n- if sf_col_idx < padded_sf_cols and thread_in_unit == Int32(0):\n- sf_offset = compute_sf_index_swizzled_128x4_gpu(\n- row_idx, sf_col_idx, padded_sf_cols\n- )\n- mScales[sf_offset] = Uint8(0)\n+ # Fast path: padding row - zero out ALL scale factors\n+ # Thread-stride loop since padded_sf_cols may exceed\n+ # num_sf_blocks_per_row (when K/32 is not a multiple of 4)\n+ if thread_in_unit == Int32(0):\n+ pad_col = sf_col_idx\n+ while pad_col < padded_sf_cols:\n+ sf_offset = compute_sf_index_swizzled_128x4_gpu(\n+ row_idx, pad_col, padded_sf_cols\n+ )\n+ mScales[sf_offset] = Uint8(0)\n+ pad_col = pad_col + num_sf_blocks_per_row\n else:\n # Normal path: process actual data\n if sf_col_idx < num_sf_blocks_per_row:\n elem_idx = (\n sf_col_idx * SF_VEC_SIZE\n- + thread_in_unit * ELTS_PER_THREAD\n+ + thread_in_unit * _elts_per_thread\n )\n \n row_input = mInput[row_idx, None]\n- input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n- v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n-\n- if cutlass.const_expr(self.is_bfloat16):\n- max0123 = bfloat2_max_abs_4(v0, v1, v2, v3)\n- local_max = bfloat2_hmax_reduce_to_f32(max0123)\n+\n+ if cutlass.const_expr(self.use_2t_per_sf):\n+ input_ptr_lo = get_ptr_as_int64(row_input, elem_idx)\n+ input_ptr_hi = get_ptr_as_int64(\n+ row_input, elem_idx + Int32(8)\n+ )\n+ v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_lo)\n+ v4, v5, v6, v7 = ld_global_v4_u32(input_ptr_hi)\n+ if cutlass.const_expr(self.is_bfloat16):\n+ local_max = bfloat2_hmax_reduce_to_f32(\n+ bfloat2_max_abs_8(\n+ v0, v1, v2, v3, v4, v5, v6, v7\n+ )\n+ )\n+ else:\n+ local_max = hmax_reduce_to_f32(\n+ half2_max_abs_8(v0, v1, v2, v3, v4, v5, v6, v7)\n+ )\n+ global_max = reduce_max_2threads(local_max)\n else:\n- max0123 = half2_max_abs_4(v0, v1, v2, v3)\n- local_max = hmax_reduce_to_f32(max0123)\n-\n- global_max = reduce_max_4threads(local_max)\n+ input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n+ v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n+ if cutlass.const_expr(self.is_bfloat16):\n+ local_max = bfloat2_hmax_reduce_to_f32(\n+ bfloat2_max_abs_4(v0, v1, v2, v3)\n+ )\n+ else:\n+ local_max = hmax_reduce_to_f32(\n+ half2_max_abs_4(v0, v1, v2, v3)\n+ )\n+ global_max = reduce_max_4threads(local_max)\n+\n inv_e4m3_max = Float32(INV_FLOAT8_E4M3_MAX)\n- normalized_max = global_max * inv_e4m3_max\n- scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n+ scale_ue8m0_u32 = float_to_ue8m0_fast(\n+ global_max * inv_e4m3_max\n+ )\n scale_ue8m0 = scale_ue8m0_u32.to(Uint8)\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n \n- if cutlass.const_expr(self.is_bfloat16):\n- fp8_packed = bfloat2x4_to_fp8x8_packed(\n- v0, v1, v2, v3, inv_scale\n+ row_output = mOutput[row_idx, None]\n+ if cutlass.const_expr(self.use_2t_per_sf):\n+ if cutlass.const_expr(self.is_bfloat16):\n+ fp8_lo = bfloat2x4_to_fp8x8_packed(\n+ v0, v1, v2, v3, inv_scale\n+ )\n+ fp8_hi = bfloat2x4_to_fp8x8_packed(\n+ v4, v5, v6, v7, inv_scale\n+ )\n+ else:\n+ fp8_lo = half2x4_to_fp8x8_packed(\n+ v0, v1, v2, v3, inv_scale\n+ )\n+ fp8_hi = half2x4_to_fp8x8_packed(\n+ v4, v5, v6, v7, inv_scale\n+ )\n+ st_global_u64(\n+ get_ptr_as_int64(row_output, elem_idx), fp8_lo\n+ )\n+ st_global_u64(\n+ get_ptr_as_int64(row_output, elem_idx + Int32(8)),\n+ fp8_hi,\n )\n else:\n- fp8_packed = half2x4_to_fp8x8_packed(\n- v0, v1, v2, v3, inv_scale\n- )\n-\n- row_output = mOutput[row_idx, None]\n- output_ptr_i64 = get_ptr_as_int64(row_output, elem_idx)\n- st_global_u64(output_ptr_i64, fp8_packed)\n+ if cutlass.const_expr(self.is_bfloat16):\n+ fp8_packed = bfloat2x4_to_fp8x8_packed(\n+ v0, v1, v2, v3, inv_scale\n+ )\n+ else:\n+ fp8_packed = half2x4_to_fp8x8_packed(\n+ v0, v1, v2, v3, inv_scale\n+ )\n+ st_global_u64(\n+ get_ptr_as_int64(row_output, elem_idx), fp8_packed\n+ )\n \n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n@@ -521,17 +688,19 @@\n )\n mScales[sf_offset] = scale_ue8m0\n \n- # Handle padding SF columns (for this row)\n- # Threads with sf_col_idx in [num_sf_blocks_per_row, padded_sf_cols)\n- if (\n- sf_col_idx >= num_sf_blocks_per_row\n- and sf_col_idx < padded_sf_cols\n- and thread_in_unit == Int32(0)\n+ # Handle padding SF columns for this row\n+ # Thread-stride loop starting from first padding column\n+ if cutlass.const_expr(\n+ self.num_sf_blocks_per_row != self.padded_sf_cols\n ):\n- sf_offset = compute_sf_index_swizzled_128x4_gpu(\n- row_idx, sf_col_idx, padded_sf_cols\n- )\n- mScales[sf_offset] = Uint8(0)\n+ if thread_in_unit == Int32(0):\n+ pad_col = num_sf_blocks_per_row + sf_col_idx\n+ while pad_col < padded_sf_cols:\n+ sf_offset = compute_sf_index_swizzled_128x4_gpu(\n+ row_idx, pad_col, padded_sf_cols\n+ )\n+ mScales[sf_offset] = Uint8(0)\n+ pad_col = pad_col + num_sf_blocks_per_row\n \n row_batch_idx = row_batch_idx + grid_dim_x\n # Update row_idx for next iteration\n@@ -548,22 +717,24 @@\n \n \n @functools.cache\n-def _get_compiled_kernel_linear(\n+def _get_compiled_kernel_mxfp8_linear(\n is_bfloat16: bool,\n K: int,\n enable_pdl: bool = False,\n+ use_2t_per_sf: bool = True,\n ) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile LINEAR layout kernel with TVM-FFI.\n \n- Cached by (K, dtype, pdl) - M-agnostic, device-independent compilation.\n+ Cached by (K, dtype, pdl, use_2t) - M-agnostic, device-independent\n+ compilation.\n \n Returns:\n Tuple of (compiled_kernel, sf_blocks_per_tb) where sf_blocks_per_tb\n is used by the caller to compute num_blocks at runtime.\n \"\"\"\n cutlass_dtype = cutlass.BFloat16 if is_bfloat16 else cutlass.Float16\n- kernel_obj = MXFP8QuantizeLinearKernel(cutlass_dtype, K, enable_pdl)\n+ kernel_obj = MXFP8QuantizeLinearKernel(cutlass_dtype, K, enable_pdl, use_2t_per_sf)\n \n # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n@@ -596,22 +767,26 @@\n \n \n @functools.cache\n-def _get_compiled_kernel_swizzled(\n+def _get_compiled_kernel_mxfp8_swizzled(\n is_bfloat16: bool,\n K: int,\n enable_pdl: bool = False,\n+ use_2t_per_sf: bool = True,\n ) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile SWIZZLED layout kernel with TVM-FFI.\n \n- Cached by (K, dtype, pdl) - M-agnostic, device-independent compilation.\n+ Cached by (K, dtype, pdl, use_2t) - M-agnostic, device-independent\n+ compilation.\n \n Returns:\n Tuple of (compiled_kernel, rows_per_block) where rows_per_block\n is used by the caller to compute num_blocks at runtime.\n \"\"\"\n cutlass_dtype = cutlass.BFloat16 if is_bfloat16 else cutlass.Float16\n- kernel_obj = MXFP8QuantizeSwizzledKernel(cutlass_dtype, K, enable_pdl)\n+ kernel_obj = MXFP8QuantizeSwizzledKernel(\n+ cutlass_dtype, K, enable_pdl, use_2t_per_sf\n+ )\n \n # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n@@ -683,9 +858,9 @@\n f\"alignment must be divisible by SF_VEC_SIZE={SF_VEC_SIZE}\"\n )\n \n- # Auto-detect PDL support based on device capability\n- if enable_pdl is None:\n- enable_pdl = device_support_pdl(input.device)\n+ # Auto-detect PDL support based on device capability.\n+ # If caller passes True explicitly, still check hardware support.\n+ enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n \n if input.dim() > 2:\n m = input.numel() // input.shape[-1]\n@@ -715,14 +890,20 @@\n # Compute M-dependent values outside the cached kernel\n num_sf_blocks_per_row = padded_k // SF_VEC_SIZE\n \n+ # Choose 2T/SF (optimized) vs 4T/SF (legacy) based on problem size.\n+ # 2T/SF doubles memory-level parallelism per warp but halves the grid,\n+ # so it only helps when there are enough SF blocks to fill all SMs.\n+ total_sf_blocks_for_dispatch = m * num_sf_blocks_per_row\n+ use_2t = total_sf_blocks_for_dispatch >= MXFP8_2T_SF_THRESHOLD\n+\n if is_sf_swizzled_layout:\n # Swizzled layout: compute padded_M and scale_output_size\n padded_m = ((m + ROW_TILE_SIZE - 1) // ROW_TILE_SIZE) * ROW_TILE_SIZE\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n scale_output_size = padded_m * padded_sf_cols\n \n- kernel_fn, rows_per_block = _get_compiled_kernel_swizzled(\n- is_bfloat16, padded_k, enable_pdl\n+ kernel_fn, rows_per_block = _get_compiled_kernel_mxfp8_swizzled(\n+ is_bfloat16, padded_k, enable_pdl, use_2t\n )\n \n num_blocks = min((padded_m + rows_per_block - 1) // rows_per_block, target_grid)\n@@ -738,8 +919,8 @@\n total_sf_blocks = m * num_sf_blocks_per_row\n scale_output_size = total_sf_blocks\n \n- kernel_fn, sf_blocks_per_tb = _get_compiled_kernel_linear(\n- is_bfloat16, padded_k, enable_pdl\n+ kernel_fn, sf_blocks_per_tb = _get_compiled_kernel_mxfp8_linear(\n+ is_bfloat16, padded_k, enable_pdl, use_2t\n )\n \n num_blocks = min(\n@@ -762,6 +943,6 @@\n \"MXFP8QuantizeLinearKernel\",\n \"MXFP8QuantizeSwizzledKernel\",\n \"mxfp8_quantize_cute_dsl\",\n- \"_get_compiled_kernel_linear\",\n- \"_get_compiled_kernel_swizzled\",\n+ \"_get_compiled_kernel_mxfp8_linear\",\n+ \"_get_compiled_kernel_mxfp8_swizzled\",\n ]"},"lines_added":{"kind":"number","value":311,"string":"311"},"lines_removed":{"kind":"number","value":130,"string":"130"},"files_in_commit":{"kind":"number","value":6,"string":"6"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200"],"string":"[\n \"B200\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["5x","1.42x","1.37x","1.41x","1.39x","1.34x","1.32x"],"string":"[\n \"5x\",\n \"1.42x\",\n \"1.37x\",\n \"1.41x\",\n \"1.39x\",\n \"1.34x\",\n \"1.32x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/quantization/kernels/mxfp8_quantize.py).\n\nGoal: perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels\nTarget hardware: B200\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nMXFP8 Quantization using CuTe-DSL\n=================================\n\nHigh-performance MXFP8 quantization kernel using CuTe-DSL.\nSupports both linear and swizzled (128x4) scale factor layouts.\n\nKey features:\n- Half2/BFloat2 SIMD for max-abs computation\n- 4-thread cooperation per scale factor block\n- Dual-path optimization: linear layout (SF-block based) and swizzled layout (row-based)\n- Vectorized 128-bit global loads/stores\n- M-agnostic compilation: kernels are compiled once per K dimension\n\"\"\"\n\nimport functools\nfrom typing import Callable, Tuple\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Uint8\n\nfrom ...api_logging import flashinfer_api\nfrom ...cute_dsl.fp4_common import (\n ld_global_v4_u32,\n st_global_u64,\n get_ptr_as_int64,\n)\nfrom ...cute_dsl.utils import get_num_sm\nfrom ..quantization_cute_dsl_utils import (\n # Constants\n SF_VEC_SIZE,\n INV_FLOAT8_E4M3_MAX,\n WARP_SIZE,\n ELTS_PER_THREAD,\n THREADS_PER_SF,\n SF_BLOCKS_PER_WARP,\n ROW_TILE_SIZE,\n # Low-level intrinsics\n hmax_reduce_to_f32,\n bfloat2_hmax_reduce_to_f32,\n float_to_ue8m0_fast,\n ue8m0_to_inv_scale_fast,\n reduce_max_4threads,\n compute_sf_index_swizzled_128x4_gpu,\n # High-level helpers\n half2_max_abs_4,\n bfloat2_max_abs_4,\n half2x4_to_fp8x8_packed,\n bfloat2x4_to_fp8x8_packed,\n)\n\n\n# Blocks per SM for occupancy target\n_BLOCKS_PER_SM = 4\n\n# Maximum threads per block (all modern NVIDIA GPUs support 1024)\n_MAX_THREADS_PER_BLOCK = 1024\n\n\n# Warp configuration bounds\n_MIN_WARPS = 4 # Minimum for reasonable occupancy (128 threads)\n_MAX_WARPS = 32 # Maximum to avoid register pressure (1024 threads)\n_DEFAULT_WARPS = 16 # Default when no optimization needed\n\n\ndef _compute_optimal_warps_for_k(K: int) -> int:\n \"\"\"\n Compute optimal WARPS_PER_BLOCK for 100% thread utilization.\n\n For the swizzled kernel, we need:\n (WARPS × 8) % num_sf_blocks == 0\n\n where num_sf_blocks = K / 32.\n\n This ensures that col_units_per_block is evenly divisible by\n num_sf_blocks_per_row, so all threads are utilized.\n\n We prefer LARGER warp counts (up to _MAX_WARPS) for better occupancy,\n while maintaining 100% thread utilization.\n\n Args:\n K: Number of columns (must be divisible by 32)\n\n Returns:\n Optimal number of warps per block\n \"\"\"\n import math\n\n num_sf_blocks = K // SF_VEC_SIZE # K / 32\n\n # For 100% utilization: (WARPS * 8) % num_sf_blocks == 0\n # WARPS must be a multiple of: num_sf_blocks / gcd(num_sf_blocks, 8)\n gcd_val = math.gcd(num_sf_blocks, 8)\n warp_multiple = num_sf_blocks // gcd_val\n\n # Find LARGEST valid WARPS in range [_MIN_WARPS, _MAX_WARPS]\n # that is a multiple of warp_multiple (for best occupancy)\n if warp_multiple <= _MAX_WARPS:\n # Find largest multiple of warp_multiple that fits in [_MIN_WARPS, _MAX_WARPS]\n warps = (_MAX_WARPS // warp_multiple) * warp_multiple\n if warps >= _MIN_WARPS:\n return warps\n # If largest multiple is below _MIN_WARPS, use the smallest valid one\n warps = warp_multiple\n while warps < _MIN_WARPS:\n warps += warp_multiple\n if warps <= _MAX_WARPS:\n return warps\n\n # If warp_multiple is too large, fall back to default\n # This shouldn't happen for reasonable K values\n return _DEFAULT_WARPS\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Linear Layout\n# =============================================================================\n\n\nclass MXFP8QuantizeLinearKernel:\n \"\"\"\n MXFP8 quantization kernel optimized for LINEAR layout.\n Uses SF-block based iteration for efficient memory access.\n\n This kernel is M-agnostic: compiled once per (K, dtype, pdl) combination.\n M-dependent values (total_sf_blocks, num_blocks) are passed at runtime.\n \"\"\"\n\n WARPS_PER_BLOCK = 16 # 16 warps = 512 threads per block\n SF_BLOCKS_PER_TB = WARPS_PER_BLOCK * SF_BLOCKS_PER_WARP\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n enable_pdl: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.enable_pdl = enable_pdl\n\n assert K % SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // SF_VEC_SIZE\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n total_sf_blocks: Int32,\n num_blocks: Int32,\n stream,\n ):\n threads_per_block = self.WARPS_PER_BLOCK * WARP_SIZE\n\n self.kernel(mInput, mOutput, mScales, total_sf_blocks).launch(\n grid=[num_blocks, 1, 1],\n block=[threads_per_block, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n total_sf_blocks: Int32,\n ):\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n warp_idx = tidx // WARP_SIZE\n lane_idx = tidx % WARP_SIZE\n\n sf_idx_in_warp = lane_idx // THREADS_PER_SF\n thread_in_sf = lane_idx % THREADS_PER_SF\n\n sf_blocks_per_tb = self.WARPS_PER_BLOCK * SF_BLOCKS_PER_WARP\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n\n sf_idx_base = (\n bidx * sf_blocks_per_tb + warp_idx * SF_BLOCKS_PER_WARP + sf_idx_in_warp\n )\n\n sf_idx = sf_idx_base\n while sf_idx < total_sf_blocks:\n row_idx = sf_idx // num_sf_blocks_per_row\n col_idx = sf_idx % num_sf_blocks_per_row\n\n base_elem = col_idx * SF_VEC_SIZE\n thread_elem_offset = thread_in_sf * ELTS_PER_THREAD\n elem_idx = base_elem + thread_elem_offset\n\n row_input = mInput[row_idx, None]\n input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n\n v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n\n # Compute max absolute value across 8 elements (4 half2/bfloat2)\n if cutlass.const_expr(self.is_bfloat16):\n max0123 = bfloat2_max_abs_4(v0, v1, v2, v3)\n local_max = bfloat2_hmax_reduce_to_f32(max0123)\n else:\n max0123 = half2_max_abs_4(v0, v1, v2, v3)\n local_max = hmax_reduce_to_f32(max0123)\n\n # 4-thread reduction for this SF block\n global_max = reduce_max_4threads(local_max)\n\n # Compute UE8M0 scale factor\n inv_e4m3_max = Float32(INV_FLOAT8_E4M3_MAX)\n normalized_max = global_max * inv_e4m3_max\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0 = scale_ue8m0_u32.to(Uint8)\n\n # Compute inverse scale for quantization\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n\n # Quantize to FP8 E4M3 and pack for vectorized store\n if cutlass.const_expr(self.is_bfloat16):\n fp8_packed = bfloat2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n else:\n fp8_packed = half2x4_to_fp8x8_packed(v0, v1, v2, v3, inv_scale)\n\n row_output = mOutput[row_idx, None]\n output_ptr_i64 = get_ptr_as_int64(row_output, elem_idx)\n st_global_u64(output_ptr_i64, fp8_packed)\n\n if thread_in_sf == Int32(0):\n mScales[sf_idx] = scale_ue8m0\n\n sf_idx = sf_idx + grid_dim_x * sf_blocks_per_tb\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Swizzled Layout\n# =============================================================================\n\n\nclass MXFP8QuantizeSwizzledKernel:\n \"\"\"\n MXFP8 quantization kernel optimized for SWIZZLED layout.\n\n Key optimizations:\n - Multi-row processing: threads process multiple rows per block when K is small\n - Row-based iteration with grid-stride loop\n - Padding row fast path - only zero out scale factors\n\n Thread utilization optimization:\n - Dynamic WARPS_PER_BLOCK based on K for 100% thread utilization\n - For small K: Multiple rows processed per block iteration\n - For large K: Single row with column loop\n\n This kernel is M-agnostic: compiled once per (K, dtype, pdl) combination.\n M-dependent values (M, padded_M) are passed at runtime.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n enable_pdl: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.enable_pdl = enable_pdl\n\n assert K % SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // SF_VEC_SIZE\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n # Compute optimal warps for 100% thread utilization\n self.warps_per_block = _compute_optimal_warps_for_k(K)\n\n # Multi-row processing constants (compile-time)\n threads_per_block = self.warps_per_block * WARP_SIZE\n col_units_per_block = threads_per_block // THREADS_PER_SF\n\n # threads_per_row = num_sf_blocks_per_row * THREADS_PER_SF = K / 8\n self.threads_per_row = self.num_sf_blocks_per_row * THREADS_PER_SF\n\n # rows_per_block = col_units_per_block // num_sf_blocks_per_row\n # With optimal warps, this should divide evenly for small K\n if self.num_sf_blocks_per_row <= col_units_per_block:\n self.rows_per_block = col_units_per_block // self.num_sf_blocks_per_row\n self.needs_col_loop = False\n else:\n self.rows_per_block = 1\n self.needs_col_loop = True\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n stream,\n ):\n threads_per_block = self.warps_per_block * WARP_SIZE\n\n self.kernel(mInput, mOutput, mScales, M, padded_M).launch(\n grid=[num_blocks, 1, 1],\n block=[threads_per_block, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n ):\n \"\"\"\n Multi-row kernel for swizzled layout.\n\n When K is small: each block processes multiple rows simultaneously.\n When K is large: each block processes one row with column loop.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Compile-time constants\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n threads_per_row = self.threads_per_row\n rows_per_block = self.rows_per_block\n\n if cutlass.const_expr(self.needs_col_loop):\n # Large K path: single row per block iteration with column loop\n # This is the original algorithm for K > 4096\n col_unit_idx = tidx // THREADS_PER_SF\n thread_in_unit = tidx % THREADS_PER_SF\n threads_per_block = self.warps_per_block * WARP_SIZE\n col_units_per_block = threads_per_block // THREADS_PER_SF\n\n row_idx = bidx\n while row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - only zero out scale factors\n sf_col_idx = col_unit_idx\n while sf_col_idx < padded_sf_cols:\n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + col_units_per_block\n else:\n # Normal path: process actual data row with column loop\n sf_col_idx = col_unit_idx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_idx = (\n sf_col_idx * SF_VEC_SIZE + thread_in_unit * ELTS_PER_THREAD\n )\n\n row_input = mInput[row_idx, None]\n input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n\n if cutlass.const_expr(self.is_bfloat16):\n max0123 = bfloat2_max_abs_4(v0, v1, v2, v3)\n local_max = bfloat2_hmax_reduce_to_f32(max0123)\n else:\n max0123 = half2_max_abs_4(v0, v1, v2, v3)\n local_max = hmax_reduce_to_f32(max0123)\n\n global_max = reduce_max_4threads(local_max)\n inv_e4m3_max = Float32(INV_FLOAT8_E4M3_MAX)\n normalized_max = global_max * inv_e4m3_max\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0 = scale_ue8m0_u32.to(Uint8)\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n\n if cutlass.const_expr(self.is_bfloat16):\n fp8_packed = bfloat2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n else:\n fp8_packed = half2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n\n row_output = mOutput[row_idx, None]\n output_ptr_i64 = get_ptr_as_int64(row_output, elem_idx)\n st_global_u64(output_ptr_i64, fp8_packed)\n\n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = scale_ue8m0\n\n sf_col_idx = sf_col_idx + col_units_per_block\n\n # Handle padding columns\n sf_col_idx = num_sf_blocks_per_row + col_unit_idx\n while sf_col_idx < padded_sf_cols:\n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + col_units_per_block\n\n row_idx = row_idx + grid_dim_x\n else:\n # Small K path: multi-row processing (K <= 4096)\n # Each block processes rows_per_block rows simultaneously\n # Thread mapping: tidx -> (row_in_block, sf_col_idx, thread_in_unit)\n row_in_block = tidx // threads_per_row\n local_tidx = tidx % threads_per_row\n sf_col_idx = local_tidx // THREADS_PER_SF\n thread_in_unit = local_tidx % THREADS_PER_SF\n\n # Grid-stride loop over row batches\n row_batch_idx = bidx\n # Initialize row_idx before while loop (CuTe DSL requires variables\n # modified in while loops to be defined before the loop)\n row_idx = row_batch_idx * rows_per_block + row_in_block\n while row_batch_idx * rows_per_block < padded_M:\n # Check if this thread's row is valid\n if row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - zero out scale factors\n # Each thread handles one SF column (no column loop needed)\n if sf_col_idx < padded_sf_cols and thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n else:\n # Normal path: process actual data\n if sf_col_idx < num_sf_blocks_per_row:\n elem_idx = (\n sf_col_idx * SF_VEC_SIZE\n + thread_in_unit * ELTS_PER_THREAD\n )\n\n row_input = mInput[row_idx, None]\n input_ptr_i64 = get_ptr_as_int64(row_input, elem_idx)\n v0, v1, v2, v3 = ld_global_v4_u32(input_ptr_i64)\n\n if cutlass.const_expr(self.is_bfloat16):\n max0123 = bfloat2_max_abs_4(v0, v1, v2, v3)\n local_max = bfloat2_hmax_reduce_to_f32(max0123)\n else:\n max0123 = half2_max_abs_4(v0, v1, v2, v3)\n local_max = hmax_reduce_to_f32(max0123)\n\n global_max = reduce_max_4threads(local_max)\n inv_e4m3_max = Float32(INV_FLOAT8_E4M3_MAX)\n normalized_max = global_max * inv_e4m3_max\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0 = scale_ue8m0_u32.to(Uint8)\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n\n if cutlass.const_expr(self.is_bfloat16):\n fp8_packed = bfloat2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n else:\n fp8_packed = half2x4_to_fp8x8_packed(\n v0, v1, v2, v3, inv_scale\n )\n\n row_output = mOutput[row_idx, None]\n output_ptr_i64 = get_ptr_as_int64(row_output, elem_idx)\n st_global_u64(output_ptr_i64, fp8_packed)\n\n if thread_in_unit == Int32(0):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = scale_ue8m0\n\n # Handle padding SF columns (for this row)\n # Threads with sf_col_idx in [num_sf_blocks_per_row, padded_sf_cols)\n if (\n sf_col_idx >= num_sf_blocks_per_row\n and sf_col_idx < padded_sf_cols\n and thread_in_unit == Int32(0)\n ):\n sf_offset = compute_sf_index_swizzled_128x4_gpu(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n\n row_batch_idx = row_batch_idx + grid_dim_x\n # Update row_idx for next iteration\n row_idx = row_batch_idx * rows_per_block + row_in_block\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# PyTorch Integration with TVM-FFI\n# =============================================================================\n\n\n@functools.cache\ndef _get_compiled_kernel_linear(\n is_bfloat16: bool,\n K: int,\n enable_pdl: bool = False,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile LINEAR layout kernel with TVM-FFI.\n\n Cached by (K, dtype, pdl) - M-agnostic, device-independent compilation.\n\n Returns:\n Tuple of (compiled_kernel, sf_blocks_per_tb) where sf_blocks_per_tb\n is used by the caller to compute num_blocks at runtime.\n \"\"\"\n cutlass_dtype = cutlass.BFloat16 if is_bfloat16 else cutlass.Float16\n kernel_obj = MXFP8QuantizeLinearKernel(cutlass_dtype, K, enable_pdl)\n\n # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n\n # Create fake tensors for compilation\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy total_sf_blocks\n Int32(1), # Dummy num_blocks\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, kernel_obj.SF_BLOCKS_PER_TB\n\n\n@functools.cache\ndef _get_compiled_kernel_swizzled(\n is_bfloat16: bool,\n K: int,\n enable_pdl: bool = False,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile SWIZZLED layout kernel with TVM-FFI.\n\n Cached by (K, dtype, pdl) - M-agnostic, device-independent compilation.\n\n Returns:\n Tuple of (compiled_kernel, rows_per_block) where rows_per_block\n is used by the caller to compute num_blocks at runtime.\n \"\"\"\n cutlass_dtype = cutlass.BFloat16 if is_bfloat16 else cutlass.Float16\n kernel_obj = MXFP8QuantizeSwizzledKernel(cutlass_dtype, K, enable_pdl)\n\n # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n\n # Create fake tensors for compilation\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(128), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, kernel_obj.rows_per_block\n\n\n@flashinfer_api\ndef mxfp8_quantize_cute_dsl(\n input: torch.Tensor,\n is_sf_swizzled_layout: bool = True,\n alignment: int = 32,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n \"\"\"\n Quantize input tensor to MXFP8 format using CuTe-DSL kernel.\n\n This is a GPU implementation with dual-path optimization:\n - LINEAR layout: SF-block based iteration (fast)\n - SWIZZLED layout: Row-based iteration with padding fast path (optimized)\n\n The kernel is compiled once per (K, dtype, pdl) combination and handles\n varying M (batch size) at runtime without recompilation.\n\n Args:\n input: Input tensor of shape [M, K] with dtype fp16/bf16\n is_sf_swizzled_layout: Whether to use 128x4 swizzled layout (True) or linear (False)\n alignment: Alignment for K dimension (default 32, must be multiple of SF_VEC_SIZE)\n enable_pdl: Whether to enable PDL (Programmatic Dependent Launch).\n If None, automatically detects based on device capability (SM >= 9.0).\n\n Returns:\n Tuple of:\n - fp8_tensor: Quantized tensor of shape [M, padded_K] with dtype float8_e4m3fn\n - scale_tensor: Scale factors as uint8 tensor\n \"\"\"\n from ...utils import device_support_pdl\n\n assert input.dtype in (torch.float16, torch.bfloat16), (\n f\"Input dtype must be float16 or bfloat16, got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n assert alignment % SF_VEC_SIZE == 0, (\n f\"alignment must be divisible by SF_VEC_SIZE={SF_VEC_SIZE}\"\n )\n\n # Auto-detect PDL support based on device capability\n if enable_pdl is None:\n enable_pdl = device_support_pdl(input.device)\n\n if input.dim() > 2:\n m = input.numel() // input.shape[-1]\n k = input.shape[-1]\n input = input.reshape(m, k)\n else:\n m, k = input.shape\n\n assert k % SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by SF_VEC_SIZE={SF_VEC_SIZE}\"\n )\n\n padded_k = ((k + alignment - 1) // alignment) * alignment\n\n if padded_k > k:\n # Pad input with zeros - padding columns must be zero to produce zero FP8 output\n input_padded = torch.zeros(m, padded_k, dtype=input.dtype, device=input.device)\n input_padded[:, :k] = input\n else:\n input_padded = input.contiguous()\n\n is_bfloat16 = input.dtype == torch.bfloat16\n\n # Cached device-specific target grid for grid size computation\n target_grid = get_num_sm(input.device) * _BLOCKS_PER_SM\n\n # Compute M-dependent values outside the cached kernel\n num_sf_blocks_per_row = padded_k // SF_VEC_SIZE\n\n if is_sf_swizzled_layout:\n # Swizzled layout: compute padded_M and scale_output_size\n padded_m = ((m + ROW_TILE_SIZE - 1) // ROW_TILE_SIZE) * ROW_TILE_SIZE\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n scale_output_size = padded_m * padded_sf_cols\n\n kernel_fn, rows_per_block = _get_compiled_kernel_swizzled(\n is_bfloat16, padded_k, enable_pdl\n )\n\n num_blocks = min((padded_m + rows_per_block - 1) // rows_per_block, target_grid)\n\n fp8_output = torch.empty(m, padded_k, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(input_padded, fp8_output, scale_output, m, padded_m, num_blocks)\n else:\n # Linear layout: compute total_sf_blocks\n total_sf_blocks = m * num_sf_blocks_per_row\n scale_output_size = total_sf_blocks\n\n kernel_fn, sf_blocks_per_tb = _get_compiled_kernel_linear(\n is_bfloat16, padded_k, enable_pdl\n )\n\n num_blocks = min(\n (total_sf_blocks + sf_blocks_per_tb - 1) // sf_blocks_per_tb, target_grid\n )\n\n fp8_output = torch.empty(m, padded_k, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(input_padded, fp8_output, scale_output, total_sf_blocks, num_blocks)\n\n fp8_tensor = fp8_output.view(torch.float8_e4m3fn)\n\n return fp8_tensor, scale_output\n\n\n__all__ = [\n \"MXFP8QuantizeLinearKernel\",\n \"MXFP8QuantizeSwizzledKernel\",\n \"mxfp8_quantize_cute_dsl\",\n \"_get_compiled_kernel_linear\",\n \"_get_compiled_kernel_swizzled\",\n]\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n**Summary**\n- Adopt dual-path kernel architecture (linear flat + swizzled row-based) for MXFP4 and NVFP4 CuTe-DSL quantization kernels.\n- Architecture chanes to MXFP8 quantization for better perf.\n- Expand benchmark scripts and test coverage across all three quantization kernels. Compares exact output match between CUDA & CuTe-DSL backends\n- **All mxfp4, mxfp8, and nvfp4 quantization have exact bitwise match in for CUDA vs. CuTe DSL backends in both the output and scaling factors.**\n\n**Kernel changes**\n`mxfp8_quantize.py`\n- Adaptive 2T/SF dispatch: 2 threads per SF block for large problems (total_sf >= 65536), 4 threads for small problems for better memory bandwidth utilization.\n- Integer UE8M0 conversion (float_to_ue8m0_fast, ue8m0_to_inv_scale_fast): replaces SFU-based lg2.approx/ex2.approx with integer bit manipulation, freeing the SFU pipeline\n- reduce_max_2threads: 1-shuffle XOR reduction for the 2T path\n- Remove unused self.dtype and self.K attributes \n \n`mxfp4_quantize.py`\n- Add swizzled kernel. Previously only supported linear layout. \n- Swizzled kernel: small-K multi-row path and large-K column-loop path, compile-time selected via const_expr(needs_col_loop)\n- Inline padding for swizzled layout (row and column) — eliminates the expensive separate flat-iteration padding passes that caused 5x+ regression at small M \n- Dynamic thread count via _compute_optimal_threads(K) for 100% thread utilization \n \n`nvfp4_quantize.py`\n- Same dual-path split: NVFP4QuantizeLinearKernel + NVFP4QuantizeSwizzledKernel \n- Supports all three SF layouts (128x4, 8x4, linear) with compile-time dispatch \n- Remove unused self.row_tile_size and self.ROW_ITERATIONS from TMA kernel \n \n `quantization_cute_dsl_utils.py`\n- ue8m0_to_inv_scale_fast: integer bit construction replacing ex2.approx \n- reduce_max_2threads: 1-shuffle reduction for 2T/SF MXFP8 path \n- 2T/SF constants: ELTS_PER_THREAD, THREADS_PER_SF, SF_BLOCKS_PER_WARP + legacy 4T variants \n- MXFP8_2T_SF_THRESHOLD = 65536 \n\n**Test changes**\n- `test_fp4_quantize.py` and `test_fp8_quantize.py`: Add more problem sizes. \n- `test_fp4_quantize_padding.py`: Add both-backend parametrization and CUDA-vs-CuTe-DSL parity test for linear layout padding.\n\n**Perf comparison between backends on B200**\n\n<details>\n <summary>Click to see mxfp8 performance comparison</summary>\n\nLinear (gmean 1.42x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp8_backend_comparison_linear_bfloat16\" src=\"https://github.com/user-attachments/assets/21b630ff-d1a7-427b-9e59-5b6417c498c6\" />\n\nSwizzled (gmean 1.37x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp8_backend_comparison_swizzled_bfloat16\" src=\"https://github.com/user-attachments/assets/f9d19958-df34-4fc9-8351-6b9348aba8c6\" />\n\n\n</details>\n\n<details>\n <summary>Click to see mxfp4 performance comparison</summary>\n\nLinear (gmean 1.41x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp4_quantize_backend_comparison_linear_bfloat16\" src=\"https://github.com/user-attachments/assets/e050a38d-600e-43c1-92eb-f0b51e22accf\" />\n\n\nSwizzled (gmean 1.39x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp4_quantize_backend_comparison_swizzled_bfloat16\" src=\"https://github.com/user-attachments/assets/d4e4cd72-baad-4057-9523-63cd6665bf6e\" />\n\n</details>\n\n<details>\n <summary>Click to see nvfp4 performance comparison</summary>\n\nLinear (gmean 1.34x)\n\n<img width=\"1644\" height=\"1477\" alt=\"nvfp4_quantize_backend_comparison_linear_bfloat16\" src=\"https://github.com/user-attachments/assets/532ef7f2-0a41-406c-8eda-0f16436672c1\" />\n\n\nSwizzled (gmean 1.32x)\n\n<img width=\"1644\" height=\"1477\" alt=\"nvfp4_quantize_backend_comparison_swizzled_bfloat16\" src=\"https://github.com/user-attachments/assets/9694e1d3-e92e-45c9-81b5-527dca4e6cd1\" />\n\n\n</details>\n\n<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Benchmarks now run and report both linear and swizzled scale-factor layouts separately, generating distinct heatmaps/tables and layout-aware labels.\n * Added a new NVFP4 quantization benchmark with bandwidth and comparison modes.\n\n* **Refactor**\n * Quantize kernels split into layout-specific implementations and introduced dual-mode threading optimizations for better performance across sizes.\n\n* **Tests**\n * Expanded parameter sweeps, added backend parameterization, and capability-aware skips.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Linear\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.42, \"speedup\": 1.42}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Swizzled\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.37, \"speedup\": 1.37}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Linear\", \"batch_matrix\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.41, \"speedup\": 1.41}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Swizzled\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.39, \"speedup\": 1.39}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Linear\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.34, \"speedup\": 1.34}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Swizzled\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.32, \"speedup\": 1.32}]"},"kernel_speedup":{"kind":"number","value":1.38,"string":"1.38"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1172,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"d476c61c3f8bcbbca30755b330a0c10b141dede3"},"date":{"kind":"string","value":"2026-04-01T12:08:51-07:00"},"pr_number":{"kind":"number","value":2904,"string":"2,904"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2904"},"title":{"kind":"string","value":"perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904)"},"message":{"kind":"string","value":"perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n**Summary**\n- Adopt dual-path kernel architecture (linear flat + swizzled row-based)\nfor MXFP4 and NVFP4 CuTe-DSL quantization kernels.\n- Architecture chanes to MXFP8 quantization for better perf.\n- Expand benchmark scripts and test coverage across all three\nquantization kernels. Compares exact output match between CUDA &\nCuTe-DSL backends\n- **All mxfp4, mxfp8, and nvfp4 quantization have exact bitwise match in\nfor CUDA vs. CuTe DSL backends in both the output and scaling factors.**\n\n**Kernel changes**\n`mxfp8_quantize.py`\n- Adaptive 2T/SF dispatch: 2 threads per SF block for large problems\n(total_sf >= 65536), 4 threads for small problems for better memory\nbandwidth utilization.\n- Integer UE8M0 conversion (float_to_ue8m0_fast,\nue8m0_to_inv_scale_fast): replaces SFU-based lg2.approx/ex2.approx with\ninteger bit manipulation, freeing the SFU pipeline\n- reduce_max_2threads: 1-shuffle XOR reduction for the 2T path\n- Remove unused self.dtype and self.K attributes \n`mxfp4_quantize.py`\n- Add swizzled kernel. Previously only supported linear layout.\n- Swizzled kernel: small-K multi-row path and large-K column-loop path,\ncompile-time selected via const_expr(needs_col_loop)\n- Inline padding for swizzled layout (row and column) — eliminates the\nexpensive separate flat-iteration padding passes that caused 5x+\nregression at small M\n- Dynamic thread count via _compute_optimal_threads(K) for 100% thread\nutilization\n`nvfp4_quantize.py`\n- Same dual-path split: NVFP4QuantizeLinearKernel +\nNVFP4QuantizeSwizzledKernel\n- Supports all three SF layouts (128x4, 8x4, linear) with compile-time\ndispatch\n- Remove unused self.row_tile_size and self.ROW_ITERATIONS from TMA\nkernel\n `quantization_cute_dsl_utils.py`\n- ue8m0_to_inv_scale_fast: integer bit construction replacing ex2.approx\n- reduce_max_2threads: 1-shuffle reduction for 2T/SF MXFP8 path\n- 2T/SF constants: ELTS_PER_THREAD, THREADS_PER_SF, SF_BLOCKS_PER_WARP +\nlegacy 4T variants\n- MXFP8_2T_SF_THRESHOLD = 65536 \n\n**Test changes**\n- `test_fp4_quantize.py` and `test_fp8_quantize.py`: Add more problem\nsizes.\n- `test_fp4_quantize_padding.py`: Add both-backend parametrization and\nCUDA-vs-CuTe-DSL parity test for linear layout padding.\n\n**Perf comparison between backends on B200**\n\n<details>\n <summary>Click to see mxfp8 performance comparison</summary>\n\nLinear (gmean 1.42x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"mxfp8_backend_comparison_linear_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/21b630ff-d1a7-427b-9e59-5b6417c498c6\"\n/>\n\nSwizzled (gmean 1.37x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"mxfp8_backend_comparison_swizzled_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/f9d19958-df34-4fc9-8351-6b9348aba8c6\"\n/>\n\n\n</details>\n\n<details>\n <summary>Click to see mxfp4 performance comparison</summary>\n\nLinear (gmean 1.41x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"mxfp4_quantize_backend_comparison_linear_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/e050a38d-600e-43c1-92eb-f0b51e22accf\"\n/>\n\n\nSwizzled (gmean 1.39x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"mxfp4_quantize_backend_comparison_swizzled_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/d4e4cd72-baad-4057-9523-63cd6665bf6e\"\n/>\n\n</details>\n\n<details>\n <summary>Click to see nvfp4 performance comparison</summary>\n\nLinear (gmean 1.34x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"nvfp4_quantize_backend_comparison_linear_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/532ef7f2-0a41-406c-8eda-0f16436672c1\"\n/>\n\n\nSwizzled (gmean 1.32x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"nvfp4_quantize_backend_comparison_swizzled_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/9694e1d3-e92e-45c9-81b5-527dca4e6cd1\"\n/>\n\n\n</details>\n\n<!-- What does this PR do? Briefly describe the changes and why they’re\nneeded. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* Benchmarks now run and report both linear and swizzled scale-factor\nlayouts separately, generating distinct heatmaps/tables and layout-aware\nlabels.\n* Added a new NVFP4 quantization benchmark with bandwidth and comparison\nmodes.\n\n* **Refactor**\n* Quantize kernels split into layout-specific implementations and\nintroduced dual-mode threading optimizations for better performance\nacross sizes.\n\n* **Tests**\n* Expanded parameter sweeps, added backend parameterization, and\ncapability-aware skips.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"flashinfer/quantization/kernels/nvfp4_quantize.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nNVFP4 Quantization using CuTe-DSL\n=================================\n\nNVFP4 quantization kernel using CuTe-DSL.\nSupports multiple scale factor layouts: swizzled 128x4, swizzled 8x4, and linear.\n\nKey differences from MXFP4:\n- sf_vec_size=16 (vs 32 for MXFP4)\n- E4M3 scale factors (vs UE8M0 for MXFP4)\n- User-provided global_scale (vs auto-computed for MXFP4)\n\"\"\"\n\nimport functools\nfrom typing import Callable, Tuple\n\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.cute.nvgpu.cpasync as cpasync\nimport cutlass.pipeline as pipeline\nfrom cutlass.pipeline import pipeline_init_arrive, pipeline_init_wait\nimport torch\nfrom cutlass import Float32, Int32, Uint8\n\nfrom ...api_logging import flashinfer_api\nfrom ...cute_dsl.fp4_common import get_ptr_as_int64, st_global_u64\nfrom ...cute_dsl.utils import get_num_sm\nfrom ..quantization_cute_dsl_utils import (\n NVFP4_SF_VEC_SIZE,\n ROW_TILE_SIZE,\n compute_sf_index_swizzled_128x4_gpu,\n compute_sf_index_swizzled_8x4_gpu,\n compute_sf_index_linear_gpu,\n half2_max_abs_8 as half2_max_abs_8_fn,\n bfloat2_max_abs_8 as bfloat2_max_abs_8_fn,\n hmax_reduce_to_f32,\n bfloat2_hmax_reduce_to_f32,\n half2x8_to_e2m1x16_packed,\n bfloat2x8_to_e2m1x16_packed,\n process_nvfp4_block_half,\n process_nvfp4_block_bfloat,\n process_nvfp4_block_fp8,\n)\n\nSF_LAYOUT_128x4 = 0\nSF_LAYOUT_8x4 = 1\nSF_LAYOUT_LINEAR = 2\n\n_BLOCKS_PER_SM = 4\n_MAX_THREADS_PER_BLOCK = 1024\n_MIN_THREADS = 128\n_MAX_THREADS = 512\n_DEFAULT_THREADS = 256\n\n\ndef _compute_optimal_threads_for_k(K: int) -> int:\n \"\"\"\n Compute optimal thread count for 100% thread utilization.\n\n For NVFP4, each thread processes one SF block (16 elements).\n threads_per_row = K / 16 = num_sf_blocks_per_row\n\n We prefer LARGER thread counts (up to _MAX_THREADS) for better occupancy,\n while maintaining 100% thread utilization.\n \"\"\"\n threads_per_row = K // NVFP4_SF_VEC_SIZE\n\n if threads_per_row >= _MAX_THREADS:\n return _MAX_THREADS\n\n if threads_per_row <= _MAX_THREADS:\n threads = (_MAX_THREADS // threads_per_row) * threads_per_row\n if threads >= _MIN_THREADS:\n return threads\n threads = threads_per_row\n while threads < _MIN_THREADS:\n threads += threads_per_row\n if threads <= _MAX_THREADS:\n return threads\n\n return _DEFAULT_THREADS\n\n\ndef _compute_swizzled_layout_sf_size(\n total_row: int, total_column: int, row_size: int = 128\n) -> int:\n \"\"\"Compute size of swizzled scale factor buffer.\"\"\"\n padded_row = (total_row + row_size - 1) // row_size * row_size\n padded_column = (total_column + 3) // 4 * 4\n return padded_row * padded_column\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for NVFP4 Swizzled Layout\n# =============================================================================\n\n\nclass NVFP4QuantizeSwizzledKernel:\n \"\"\"\n NVFP4 quantization kernel supporting multiple scale factor layouts.\n\n Supported layouts:\n - 128x4 (swizzled): Optimized for GEMM with large tileN\n - 8x4 (swizzled): Optimized for GEMM with small tileN\n - linear: Simple row-major layout, no swizzling\n\n Key features:\n - E4M3 scale factors (FP8 format) with user-provided global_scale\n - sf_vec_size=16 (each thread processes 16 elements)\n - Multi-row processing when K is small, column loop when K is large\n - Row-based iteration with grid-stride loop\n - Padding row fast path for zeroing scale factors\n\n This kernel is M-agnostic: compiled once per (K, dtype, sf_layout, pdl)\n combination. M-dependent values (M, padded_M) and global_scale are passed\n at runtime.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n\n if sf_layout == SF_LAYOUT_LINEAR:\n self.padded_sf_cols = self.num_sf_blocks_per_row\n self.row_tile_size = 1\n elif sf_layout == SF_LAYOUT_8x4:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n self.row_tile_size = 8\n else:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n self.row_tile_size = ROW_TILE_SIZE # 128\n\n self.num_threads = _compute_optimal_threads_for_k(K)\n\n self.threads_per_row = self.num_sf_blocks_per_row\n\n if self.threads_per_row <= self.num_threads:\n self.rows_per_block = self.num_threads // self.threads_per_row\n self.needs_col_loop = False\n else:\n self.rows_per_block = 1\n self.needs_col_loop = True\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n \"\"\"Compute scale factor offset based on layout (compile-time dispatch).\"\"\"\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n if cutlass.const_expr(self.sf_is_8x4):\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_linear_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n mGlobalScale: cute.Tensor,\n stream,\n ):\n threads_per_block = self.num_threads\n\n self.kernel(mInput, mOutput, mScales, M, padded_M, mGlobalScale).launch(\n grid=[num_blocks, 1, 1],\n block=[threads_per_block, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n mGlobalScale: cute.Tensor,\n ):\n \"\"\"\n NVFP4 quantization kernel with swizzled scale factor layout.\n\n Dual-path kernel with compile-time selection:\n - Small K path: Multi-row processing for improved thread utilization\n - Large K path: Single row with column loop\n\n Each thread processes one SF block (16 elements):\n 1. Load 16 elements (2 x 128-bit for fp16/bf16, 1 x 128-bit for fp8)\n 2. Compute max absolute value using SIMD reduction\n 3. Compute E4M3 scale: cvt_f32_to_e4m3(global_scale * max / 6.0)\n 4. Store scale factor using layout-specific indexing\n 5. Back-convert E4M3, compute output_scale = global_scale / scale_back\n 6. Scale elements and convert to E2M1\n 7. Store 8 bytes (16 FP4 values)\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Read global_scale from device memory (avoids CPU-GPU sync at launch)\n global_scale = Float32(mGlobalScale[Int32(0)])\n\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n num_threads = self.num_threads\n rows_per_block = self.rows_per_block\n threads_per_row = self.threads_per_row\n\n if cutlass.const_expr(not self.needs_col_loop):\n # ===== SMALL K PATH: Multi-row processing =====\n row_in_block = tidx // threads_per_row\n sf_idx_in_row = tidx % threads_per_row\n\n row_batch_idx = bidx\n total_row_batches = cute.ceil_div(padded_M, rows_per_block)\n\n while row_batch_idx < total_row_batches:\n base_row = row_batch_idx * rows_per_block\n row_idx = base_row + row_in_block\n\n if row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n local_sf_idx = sf_idx_in_row\n while local_sf_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, local_sf_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n local_sf_idx = local_sf_idx + threads_per_row\n else:\n if sf_idx_in_row < num_sf_blocks_per_row:\n elem_base = sf_idx_in_row * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n if cutlass.const_expr(self.is_fp8):\n scale_fp8, packed64 = process_nvfp4_block_fp8(\n row_input, elem_base, global_scale\n )\n elif cutlass.const_expr(self.is_bfloat16):\n scale_fp8, packed64 = process_nvfp4_block_bfloat(\n row_input, elem_base, global_scale\n )\n else:\n scale_fp8, packed64 = process_nvfp4_block_half(\n row_input, elem_base, global_scale\n )\n\n sf_offset = self._compute_sf_offset(\n row_idx, sf_idx_in_row, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n\n row_output = mOutput[row_idx, None]\n out_base = sf_idx_in_row * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n padding_sf_start = num_sf_blocks_per_row + sf_idx_in_row\n while padding_sf_start < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, padding_sf_start, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n padding_sf_start = padding_sf_start + threads_per_row\n\n row_batch_idx = row_batch_idx + grid_dim_x\n\n else:\n # ===== LARGE K PATH: Single row with column loop =====\n row_idx = bidx\n while row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n sf_idx = Int32(tidx)\n\n if is_padding_row:\n while sf_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, sf_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_idx = sf_idx + num_threads\n else:\n num_sf_iters = (\n num_sf_blocks_per_row + num_threads - 1\n ) // num_threads\n\n for sf_iter in range(num_sf_iters):\n local_sf_idx = sf_iter * num_threads + tidx\n\n if local_sf_idx < num_sf_blocks_per_row:\n elem_base = local_sf_idx * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n if cutlass.const_expr(self.is_fp8):\n scale_fp8, packed64 = process_nvfp4_block_fp8(\n row_input, elem_base, global_scale\n )\n elif cutlass.const_expr(self.is_bfloat16):\n scale_fp8, packed64 = process_nvfp4_block_bfloat(\n row_input, elem_base, global_scale\n )\n else:\n scale_fp8, packed64 = process_nvfp4_block_half(\n row_input, elem_base, global_scale\n )\n\n sf_offset = self._compute_sf_offset(\n row_idx, local_sf_idx, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n\n row_output = mOutput[row_idx, None]\n out_base = local_sf_idx * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n padding_sf_start = num_sf_blocks_per_row + tidx\n while padding_sf_start < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, padding_sf_start, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n padding_sf_start = padding_sf_start + num_threads\n\n row_idx = row_idx + grid_dim_x\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL TMA Kernel Class for NVFP4\n# =============================================================================\n\n_TMA_ROW_TILE = 16\n_TMA_COL_TILE = 64 # Per-warp column tile\n_TMA_NUM_CONSUMER_WARPS = 8\n_TMA_NUM_STAGES = 4\n_TMA_COLS_PER_STAGE = _TMA_NUM_CONSUMER_WARPS * _TMA_COL_TILE # 512\n\n\ndef _round_up(x: int, d: int) -> int:\n return ((x + d - 1) // d) * d\n\n\nclass NVFP4QuantizeTMAKernel:\n \"\"\"\n TMA-based NVFP4 quantization kernel with pipelined producer-consumer\n warp specialization, matching the CUDA TMA kernel architecture.\n\n Architecture (matches csrc/nv_internal/.../quantization.cuh):\n - 1 producer warp (warp 0) issues TMA G2S loads into staged SMEM buffers\n - 8 consumer warps (warps 1-8) read from SMEM, quantize, write to GMEM\n - PipelineTmaAsync manages multi-stage buffering (4 stages)\n - Each TMA tile: [16, 512] = 16 rows x 8 warps x 64 cols per warp\n - Each consumer warp: 4 threads/row x 8 rows/warp, 2 row iterations\n - Each thread: 16 elements (1 SF block) via 2 x ld.shared.v4.u32\n - Grid-stride loop over row tiles, inner loop over K/512 col chunks\n\n Effective when M >= 1024 and K is a multiple of 512.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n\n assert not self.is_fp8, \"FP8 input not yet supported for TMA kernel\"\n assert K % _TMA_COLS_PER_STAGE == 0, (\n f\"K ({K}) must be a multiple of {_TMA_COLS_PER_STAGE} for TMA kernel\"\n )\n\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n self.num_col_chunks = K // _TMA_COLS_PER_STAGE\n\n if sf_layout == SF_LAYOUT_LINEAR:\n self.padded_sf_cols = self.num_sf_blocks_per_row\n self.row_tile_size = 1\n elif sf_layout == SF_LAYOUT_8x4:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n self.row_tile_size = 8\n else:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n self.row_tile_size = ROW_TILE_SIZE\n\n self.num_consumer_warps = _TMA_NUM_CONSUMER_WARPS # 8\n self.num_stages = _TMA_NUM_STAGES\n self.producer_warp_id = 0 # Warp 0 is producer (matches CUDA kernel)\n self.threads_per_cta = 32 * (self.num_consumer_warps + 1) # 288\n self.rows_per_block = _TMA_ROW_TILE\n self.buffer_align_bytes = 1024\n self.cluster_shape_mn = (1, 1)\n self.elems_per_stage = _TMA_ROW_TILE * _TMA_COLS_PER_STAGE # 8192\n\n # Thread indexing constants (matches CUDA TmaKernelTraitsTwoBytes)\n self.THREADS_PER_ROW = 4 # laneIdx % 4\n self.ROWS_PER_WARP = 8 # 32 / 4\n self.ROW_ITERATIONS = _TMA_ROW_TILE // self.ROWS_PER_WARP # 2\n self.ELTS_PER_THREAD = NVFP4_SF_VEC_SIZE # 16\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n if cutlass.const_expr(self.sf_is_8x4):\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_linear_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def _quantize_sf_block(\n self,\n h0: cutlass.Uint32,\n h1: cutlass.Uint32,\n h2: cutlass.Uint32,\n h3: cutlass.Uint32,\n h4: cutlass.Uint32,\n h5: cutlass.Uint32,\n h6: cutlass.Uint32,\n h7: cutlass.Uint32,\n global_row: Int32,\n sf_col: Int32,\n global_scale: Float32,\n M: Int32,\n padded_M: Int32,\n padded_sf_cols: Int32,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n ):\n \"\"\"Quantize one 16-element SF block and write results to GMEM.\"\"\"\n from ...cute_dsl.fp4_common import (\n cvt_f32_to_e4m3,\n nvfp4_compute_output_scale,\n rcp_approx_ftz,\n )\n\n if global_row < padded_M:\n is_padding_row = global_row >= M\n\n if is_padding_row:\n sf_offset = self._compute_sf_offset(global_row, sf_col, padded_sf_cols)\n mScales[sf_offset] = Uint8(0)\n else:\n if cutlass.const_expr(self.is_bfloat16):\n block_max_h2 = bfloat2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n else:\n block_max_h2 = half2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & cutlass.Uint32(0xFF))\n\n output_scale = nvfp4_compute_output_scale(scale_fp8_u32, global_scale)\n\n if cutlass.const_expr(self.is_bfloat16):\n packed64 = bfloat2x8_to_e2m1x16_packed(\n h0, h1, h2, h3, h4, h5, h6, h7, output_scale\n )\n else:\n packed64 = half2x8_to_e2m1x16_packed(\n h0, h1, h2, h3, h4, h5, h6, h7, output_scale\n )\n\n sf_offset = self._compute_sf_offset(global_row, sf_col, padded_sf_cols)\n mScales[sf_offset] = scale_fp8\n\n row_output = mOutput[global_row, None]\n out_base = sf_col * Int32(NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n mGlobalScale: cute.Tensor,\n stream,\n ):\n # 3D global tensor: [padded_M, K/64, 64] so each warp's 64-col\n # stripe is the contiguous innermost dimension, matching the CUDA\n # TMA kernel's 3D tensor map.\n gInput = cute.make_tensor(\n mInput.iterator,\n cute.make_layout(\n (padded_M, self.K // _TMA_COL_TILE, _TMA_COL_TILE),\n stride=(self.K, _TMA_COL_TILE, 1),\n ),\n )\n\n # SMEM layout per stage: [rows=16, warps=8, cols_per_warp=64]\n # with SWIZZLE_128B applied. Within each warp's [16, 64] tile the\n # row stride is 64 elems = 128 bytes, putting row bits in the S=3\n # range of the swizzle so different rows map to different banks.\n smem_swizzle = cute.make_swizzle(3, 4, 3) # SWIZZLE_128B for 2B types\n smem_outer_single = cute.make_layout(\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n stride=(_TMA_COL_TILE, _TMA_ROW_TILE * _TMA_COL_TILE, 1),\n )\n smem_single_composed = cute.make_composed_layout(\n smem_swizzle, 0, smem_outer_single\n )\n\n cta_tiler = (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE)\n tma_atom, tma_tensor = cpasync.make_tiled_tma_atom(\n cpasync.CopyBulkTensorTileG2SOp(),\n gInput,\n smem_single_composed,\n cta_tiler,\n )\n\n total_smem_elems = self.elems_per_stage * self.num_stages\n # Staged outer layout (no swizzle — swizzle passed separately)\n smem_outer_staged = cute.make_layout(\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE, self.num_stages),\n stride=(\n _TMA_COL_TILE,\n _TMA_ROW_TILE * _TMA_COL_TILE,\n 1,\n self.elems_per_stage,\n ),\n )\n # Flat layout for manual-swizzle consumer reads\n smem_layout_flat = cute.make_layout((total_smem_elems,))\n\n self.num_tma_load_bytes = cute.size_in_bytes(self.dtype, smem_outer_single)\n\n @cute.struct\n class SharedStorage:\n load_full_mbar: cute.struct.MemRange[cutlass.Int64, self.num_stages]\n load_empty_mbar: cute.struct.MemRange[cutlass.Int64, self.num_stages]\n smem_data: cute.struct.Align[\n cute.struct.MemRange[self.dtype, total_smem_elems],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n tma_atom,\n tma_tensor,\n mOutput,\n mScales,\n M,\n padded_M,\n mGlobalScale,\n smem_outer_staged,\n smem_swizzle,\n smem_layout_flat,\n ).launch(\n grid=[num_blocks, 1, 1],\n block=[self.threads_per_cta, 1, 1],\n max_number_threads=[\n self.threads_per_cta,\n 1,\n 1,\n ], # __launch_bounds__(288, 2)\n min_blocks_per_mp=2,\n cluster=(*self.cluster_shape_mn, 1),\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n tma_atom: cute.CopyAtom,\n gInput_tma: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n mGlobalScale: cute.Tensor,\n smem_outer_staged: cute.Layout,\n smem_swizzle: cute.Swizzle,\n smem_layout_flat: cute.Layout,\n ):\n from ...cute_dsl.fp4_common import (\n get_smem_ptr_as_int32,\n ld_shared_v4_u32,\n )\n\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n lane_idx = tidx % 32\n\n global_scale = Float32(mGlobalScale[Int32(0)])\n padded_sf_cols = self.padded_sf_cols\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n num_col_chunks = self.num_col_chunks\n elems_per_stage = self.elems_per_stage\n\n # ---- SMEM allocation ----\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n load_mbar_ptr = storage.load_full_mbar.data_ptr()\n # Swizzled tensor for TMA partition (address-space-correct writes)\n sData_staged = storage.smem_data.get_tensor(\n smem_outer_staged, swizzle=smem_swizzle\n )\n # Flat tensor for manual-swizzle consumer reads\n sData_flat = storage.smem_data.get_tensor(smem_layout_flat)\n\n # ---- Pipeline setup ----\n load_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=load_mbar_ptr,\n num_stages=self.num_stages,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread, 1),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread, self.num_consumer_warps\n ),\n tx_count=self.num_tma_load_bytes,\n cta_layout_vmnk=cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)), (1,)\n ),\n defer_sync=True,\n )\n\n pipeline_init_arrive(cluster_shape_mn=self.cluster_shape_mn, is_relaxed=True)\n pipeline_init_wait(cluster_shape_mn=self.cluster_shape_mn)\n\n # ---- TMA partition (3D: rows × warps × cols_per_warp) ----\n gSrc_tiled = cute.local_tile(\n gInput_tma,\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n (None, None, None),\n )\n tAsA, tAgA = cpasync.tma_partition(\n tma_atom,\n 0,\n cute.make_layout(1),\n cute.group_modes(sData_staged, 0, 3), # Group 3 tile modes\n cute.group_modes(gSrc_tiled, 0, 3),\n )\n\n num_row_tiles = cute.ceil_div(padded_M, _TMA_ROW_TILE)\n\n # ---- Consumer thread indexing (matches CUDA TmaKernelTraitsTwoBytes) ----\n # 4 threads per row, 8 rows per warp, 2 row iterations per stage\n col_idx_local = lane_idx % Int32(self.THREADS_PER_ROW)\n row_idx_local = lane_idx // Int32(self.THREADS_PER_ROW)\n\n # ======== Producer warp (warp 0) ========\n if warp_idx == self.producer_warp_id:\n producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_stages\n )\n\n row_tile_idx = bidx\n while row_tile_idx < num_row_tiles:\n col_chunk = Int32(0)\n while col_chunk < num_col_chunks:\n load_pipeline.producer_acquire(producer_state)\n\n cute.copy(\n tma_atom,\n tAgA[(None, row_tile_idx, col_chunk, 0)],\n tAsA[(None, producer_state.index)],\n tma_bar_ptr=load_pipeline.producer_get_barrier(producer_state),\n )\n\n producer_state.advance()\n col_chunk = col_chunk + Int32(1)\n\n row_tile_idx = row_tile_idx + grid_dim_x\n\n load_pipeline.producer_tail(producer_state)\n\n # ======== Consumer warps (warps 1-8) ========\n if warp_idx > 0:\n consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_stages\n )\n\n # 0-indexed consumer warp id\n consumer_warp_idx = warp_idx - Int32(1)\n\n # Pre-compute warp tile base offset (constant per warp)\n # SMEM 3D layout: [rows=16, warps=8, cols=64] per stage\n # stride: [64, 1024, 1] → warp tile base = warp * 1024\n warp_tile_elems = _TMA_ROW_TILE * _TMA_COL_TILE # 1024\n warp_tile_base = consumer_warp_idx * Int32(warp_tile_elems)\n\n # Float4 base position for this thread (0, 2, 4, 6)\n f4_base = col_idx_local * Int32(2)\n\n # Global column offset for SF index: warp's column within K\n base_col_in_stage = consumer_warp_idx * Int32(\n _TMA_COL_TILE\n ) + col_idx_local * Int32(self.ELTS_PER_THREAD)\n\n row_tile_idx = bidx\n while row_tile_idx < num_row_tiles:\n base_row = row_tile_idx * Int32(_TMA_ROW_TILE)\n\n col_chunk = Int32(0)\n while col_chunk < num_col_chunks:\n load_pipeline.consumer_wait(consumer_state)\n stage = consumer_state.index\n\n # ---- Read ALL SMEM data with SWIZZLE_128B addressing ----\n # Within each warp's [16,64] tile, the XOR pattern matches\n # CUDA's load_input_vec: float4_idx ^= row & 7\n # Physical elem offset in warp tile for (row, float4 f):\n # row * 64 + (f ^ (row & 7)) * 8\n stage_base = stage * Int32(elems_per_stage)\n\n # Row iteration 0 (row_idx_local = 0..7)\n r0_xor = row_idx_local & Int32(7)\n r0_f4_0 = f4_base ^ r0_xor\n r0_f4_1 = (f4_base + Int32(1)) ^ r0_xor\n r0_row_base = (\n stage_base\n + warp_tile_base\n + row_idx_local * Int32(_TMA_COL_TILE)\n )\n r0_addr_0 = get_smem_ptr_as_int32(\n sData_flat, r0_row_base + r0_f4_0 * Int32(8)\n )\n r0_addr_1 = get_smem_ptr_as_int32(\n sData_flat, r0_row_base + r0_f4_1 * Int32(8)\n )\n r0_h0, r0_h1, r0_h2, r0_h3 = ld_shared_v4_u32(r0_addr_0)\n r0_h4, r0_h5, r0_h6, r0_h7 = ld_shared_v4_u32(r0_addr_1)\n\n # Row iteration 1 (row = row_idx_local + 8)\n r1_row = row_idx_local + Int32(self.ROWS_PER_WARP)\n r1_xor = r1_row & Int32(7)\n r1_f4_0 = f4_base ^ r1_xor\n r1_f4_1 = (f4_base + Int32(1)) ^ r1_xor\n r1_row_base = (\n stage_base + warp_tile_base + r1_row * Int32(_TMA_COL_TILE)\n )\n r1_addr_0 = get_smem_ptr_as_int32(\n sData_flat, r1_row_base + r1_f4_0 * Int32(8)\n )\n r1_addr_1 = get_smem_ptr_as_int32(\n sData_flat, r1_row_base + r1_f4_1 * Int32(8)\n )\n r1_h0, r1_h1, r1_h2, r1_h3 = ld_shared_v4_u32(r1_addr_0)\n r1_h4, r1_h5, r1_h6, r1_h7 = ld_shared_v4_u32(r1_addr_1)\n\n # ---- Quantize and write: both row iterations ----\n # Global column base for SF index computation\n global_col_base = col_chunk * Int32(_TMA_COLS_PER_STAGE)\n sf_col = (global_col_base + base_col_in_stage) // Int32(\n NVFP4_SF_VEC_SIZE\n )\n\n # Row iteration 0\n global_row_0 = base_row + row_idx_local\n self._quantize_sf_block(\n r0_h0,\n r0_h1,\n r0_h2,\n r0_h3,\n r0_h4,\n r0_h5,\n r0_h6,\n r0_h7,\n global_row_0,\n sf_col,\n global_scale,\n M,\n padded_M,\n padded_sf_cols,\n mOutput,\n mScales,\n )\n\n # Row iteration 1\n global_row_1 = base_row + row_idx_local + Int32(self.ROWS_PER_WARP)\n self._quantize_sf_block(\n r1_h0,\n r1_h1,\n r1_h2,\n r1_h3,\n r1_h4,\n r1_h5,\n r1_h6,\n r1_h7,\n global_row_1,\n sf_col,\n global_scale,\n M,\n padded_M,\n padded_sf_cols,\n mOutput,\n mScales,\n )\n\n # ---- Release pipeline after all work (matches CUDA pattern) ----\n load_pipeline.consumer_release(consumer_state)\n consumer_state.advance()\n\n col_chunk = col_chunk + Int32(1)\n\n # Zero padding SF columns for swizzled layouts\n if cutlass.const_expr(self.sf_layout != SF_LAYOUT_LINEAR):\n consumer_tid = (warp_idx - Int32(1)) * Int32(32) + lane_idx\n if consumer_tid < _TMA_ROW_TILE:\n pad_row_idx = base_row + consumer_tid\n if pad_row_idx < padded_M:\n padding_sf = Int32(num_sf_blocks_per_row)\n while padding_sf < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n pad_row_idx, padding_sf, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n padding_sf = padding_sf + Int32(1)\n\n row_tile_idx = row_tile_idx + grid_dim_x\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# PyTorch Integration with TVM-FFI\n# =============================================================================\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile NVFP4 kernel with TVM-FFI.\n\n Cached by (K, dtype_key, sf_layout, pdl) - M-agnostic, device-independent\n compilation.\n\n Args:\n dtype_key: One of \"float16\", \"bfloat16\", \"float8_e4m3fn\".\n\n Returns:\n Tuple of (compiled_kernel, rows_per_block) where rows_per_block\n is used by the caller to compute num_blocks at runtime.\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n \"float8_e4m3fn\": cutlass.Float8E4M3FN,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n kernel_obj = NVFP4QuantizeSwizzledKernel(\n cutlass_dtype, K, sf_layout=sf_layout, enable_pdl=enable_pdl\n )\n\n sym_m = cute.sym_int()\n\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(128), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, kernel_obj.rows_per_block\n\n\n_TMA_MIN_M = 1024\n# TMA wins when the total problem is large enough to amortize pipeline overhead.\n# Empirically, floor(log2(M)) + floor(log2(K)) >= 25 is the crossover where TMA\n# outperforms the default vectorized-load kernel, validated on B200 and SM120.\n# We use bit_length()-1 (i.e., floor(log2)) rather than m*k to keep the boundary\n# aligned with the power-of-2 grid it was tuned on.\n_TMA_LOG2_MK_THRESHOLD = 25\n\n\ndef _should_use_tma(m: int, k: int, dtype: torch.dtype) -> bool:\n \"\"\"Determine if TMA kernel should be used based on problem dimensions.\"\"\"\n if dtype == torch.float8_e4m3fn:\n return False\n if k % _TMA_COLS_PER_STAGE != 0:\n return False\n if m < _TMA_MIN_M:\n return False\n # Use log2(M) + log2(K) threshold for the crossover point\n return m.bit_length() - 1 + k.bit_length() - 1 >= _TMA_LOG2_MK_THRESHOLD\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4_tma(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile TMA-based NVFP4 kernel with TVM-FFI.\n\n Cached by (K, dtype_key, sf_layout, pdl).\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n kernel_obj = NVFP4QuantizeTMAKernel(\n cutlass_dtype, K, sf_layout=sf_layout, enable_pdl=enable_pdl\n )\n\n sym_m = cute.sym_int()\n sym_padded_m = cute.sym_int()\n\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_padded_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(1024), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, kernel_obj.rows_per_block\n\n\n@flashinfer_api\ndef nvfp4_quantize_cute_dsl(\n input: torch.Tensor,\n global_scale: torch.Tensor,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n \"\"\"\n Quantize input tensor to NVFP4 format using CuTe-DSL kernel.\n\n This is a GPU implementation matching FlashInfer's nvfp4_quantize() behavior:\n - E4M3 scale factors (FP8)\n - E2M1 output format (4-bit, 2 values per byte)\n - Supports 128x4, 8x4, and linear scale factor layouts\n - sf_vec_size=16\n\n The kernel is compiled once per (K, dtype, sf_layout, pdl) combination and\n handles varying M (batch size) at runtime without recompilation.\n\n Args:\n input: Input tensor of shape [M, K] with dtype fp16/bf16/float8_e4m3fn\n global_scale: Scalar tensor (float32) for NVFP4 global scale factor\n sf_layout: Scale factor layout (0=128x4, 1=8x4, 2=linear).\n enable_pdl: Whether to enable PDL (Programmatic Dependent Launch).\n If None, automatically detects based on device capability (SM >= 9.0).\n\n Returns:\n Tuple of:\n - fp4_tensor: Quantized tensor of shape [M, K/2] with dtype uint8\n - scale_tensor: E4M3 scale factors as uint8 tensor\n reshaped to [padded_rows, K/16]\n \"\"\"\n from ...utils import device_support_pdl\n\n _valid_sf_layouts = (SF_LAYOUT_128x4, SF_LAYOUT_8x4, SF_LAYOUT_LINEAR)\n assert sf_layout in _valid_sf_layouts, (\n f\"sf_layout must be one of {_valid_sf_layouts}, got {sf_layout}\"\n )\n _supported_dtypes = (torch.float16, torch.bfloat16, torch.float8_e4m3fn)\n assert input.dtype in _supported_dtypes, (\n f\"Input dtype must be one of {_supported_dtypes}, got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n\n if enable_pdl is None:\n enable_pdl = device_support_pdl(input.device)\n\n if input.dim() > 2:\n m = input.numel() // input.shape[-1]\n k = input.shape[-1]\n input = input.reshape(m, k)\n else:\n m, k = input.shape\n\n assert k % NVFP4_SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by NVFP4_SF_VEC_SIZE={NVFP4_SF_VEC_SIZE}\"\n )\n\n input = input.contiguous()\n\n _torch_to_dtype_key = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n torch.float8_e4m3fn: \"float8_e4m3fn\",\n }\n dtype_key = _torch_to_dtype_key[input.dtype]\n\n if isinstance(global_scale, torch.Tensor):\n global_scale_tensor = (\n global_scale.float().reshape(1).contiguous().to(input.device)\n )\n else:\n global_scale_tensor = torch.tensor(\n [float(global_scale)], dtype=torch.float32, device=input.device\n )\n\n num_sm = get_num_sm(input.device)\n\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n\n use_tma = _should_use_tma(m, k, input.dtype)\n\n if use_tma:\n tma_row_tile = _TMA_ROW_TILE\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = _round_up(m, tma_row_tile)\n padded_sf_cols = num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n padded_m = _round_up(m, max(tma_row_tile, 8))\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n else:\n padded_m = _round_up(m, max(tma_row_tile, ROW_TILE_SIZE))\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n\n scale_output_size = padded_m * padded_sf_cols\n\n kernel_fn, rows_per_block = _get_compiled_kernel_nvfp4_tma(\n dtype_key, k, sf_layout, enable_pdl\n )\n\n # Match CUDA TMA kernel: grid = min(row_tiles, SM_count * 2)\n tma_target_grid = num_sm * 2\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block, tma_target_grid\n )\n\n input_padded = input\n if padded_m > m:\n input_padded = torch.zeros(\n padded_m, k, dtype=input.dtype, device=input.device\n )\n input_padded[:m, :] = input\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input_padded,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_tensor,\n )\n\n if sf_layout == SF_LAYOUT_LINEAR:\n scale_output = scale_output[: m * num_sf_blocks_per_row]\n\n # Reshape using padded_sf_cols for swizzled layouts (the buffer is\n # physically padded and stores data in swizzled order). For linear\n # layout the padding is already trimmed above.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n # Non-TMA path\n if sf_layout == SF_LAYOUT_LINEAR:\n row_tile_size = 1\n padded_m = m\n padded_sf_cols = num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n row_tile_size = 8\n padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n else:\n row_tile_size = ROW_TILE_SIZE # 128\n padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n\n scale_output_size = padded_m * padded_sf_cols\n\n kernel_fn, rows_per_block = _get_compiled_kernel_nvfp4(\n dtype_key, k, sf_layout, enable_pdl\n )\n\n default_target_grid = num_sm * _BLOCKS_PER_SM\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block, default_target_grid\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input, fp4_output, scale_output, m, padded_m, num_blocks, global_scale_tensor\n )\n\n # Reshape using padded_sf_cols: for swizzled layouts the buffer includes\n # column padding; for linear layout padded_sf_cols == num_sf_blocks_per_row.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n\n__all__ = [\n \"SF_LAYOUT_128x4\",\n \"SF_LAYOUT_8x4\",\n \"SF_LAYOUT_LINEAR\",\n \"NVFP4QuantizeSwizzledKernel\",\n \"NVFP4QuantizeTMAKernel\",\n \"nvfp4_quantize_cute_dsl\",\n \"_get_compiled_kernel_nvfp4\",\n \"_get_compiled_kernel_nvfp4_tma\",\n]\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nNVFP4 Quantization using CuTe-DSL\n=================================\n\nNVFP4 quantization kernel using CuTe-DSL.\nSupports multiple scale factor layouts: swizzled 128x4, swizzled 8x4, and linear.\n\nDual-path optimization following the MXFP4 pattern:\n- Linear layout: flat SF-block iteration for 100% thread utilization\n- Swizzled layout: row-based iteration with multi-row / column-loop paths\n\nKey differences from MXFP4:\n- sf_vec_size=16 (vs 32 for MXFP4)\n- E4M3 scale factors (vs UE8M0 for MXFP4)\n- User-provided global_scale (vs auto-computed for MXFP4)\n- 3 layouts: 128x4, 8x4, linear (vs 128x4, linear for MXFP4)\n\"\"\"\n\nimport functools\nfrom typing import Callable, Tuple\n\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.cute.nvgpu.cpasync as cpasync\nimport cutlass.pipeline as pipeline\nfrom cutlass.pipeline import pipeline_init_arrive, pipeline_init_wait\nimport torch\nfrom cutlass import Float32, Int32, Uint8\n\nfrom ...api_logging import flashinfer_api\nfrom ...cute_dsl.fp4_common import get_ptr_as_int64, st_global_u64\nfrom ...cute_dsl.utils import get_num_sm\nfrom ..quantization_cute_dsl_utils import (\n NVFP4_SF_VEC_SIZE,\n WARP_SIZE,\n ROW_TILE_SIZE,\n compute_sf_index_swizzled_128x4_gpu,\n compute_sf_index_swizzled_8x4_gpu,\n compute_sf_index_linear_gpu,\n half2_max_abs_8 as half2_max_abs_8_fn,\n bfloat2_max_abs_8 as bfloat2_max_abs_8_fn,\n hmax_reduce_to_f32,\n bfloat2_hmax_reduce_to_f32,\n half2x8_to_e2m1x16_packed,\n bfloat2x8_to_e2m1x16_packed,\n process_nvfp4_block_half,\n process_nvfp4_block_bfloat,\n process_nvfp4_block_fp8,\n)\n\nSF_LAYOUT_128x4 = 0\nSF_LAYOUT_8x4 = 1\nSF_LAYOUT_LINEAR = 2\n\n# Blocks per SM for occupancy target\n_BLOCKS_PER_SM = 4\n\n# Maximum threads per block\n_MAX_THREADS_PER_BLOCK = 1024\n\n# Thread count bounds for swizzled kernel\n_MIN_THREADS = 128\n_MAX_THREADS = 512\n\n# Linear kernel: fixed 16 warps (512 threads), 1 SF block per thread\n_LINEAR_WARPS_PER_BLOCK = 16\n_LINEAR_SF_BLOCKS_PER_TB = _LINEAR_WARPS_PER_BLOCK * WARP_SIZE # 512\n\n\ndef _compute_optimal_threads(K: int) -> int:\n \"\"\"\n Compute optimal thread count for 100% utilization in the swizzled kernel.\n\n For NVFP4, each thread processes 1 SF block (16 elements), so:\n threads_per_row = K / 16\n\n We want num_threads to be a multiple of threads_per_row so that\n rows_per_block = num_threads / threads_per_row is an integer.\n\n We prefer LARGER thread counts (up to _MAX_THREADS) for better occupancy.\n\n If threads_per_row > _MAX_THREADS, we use _MAX_THREADS with a column loop.\n\n Args:\n K: Number of columns (must be divisible by 16)\n\n Returns:\n Optimal number of threads per block\n \"\"\"\n threads_per_row = K // NVFP4_SF_VEC_SIZE # K / 16\n\n if threads_per_row > _MAX_THREADS:\n # Column loop mode: use maximum threads\n return _MAX_THREADS\n\n # Find largest multiple of threads_per_row in [_MIN_THREADS, _MAX_THREADS]\n largest = (_MAX_THREADS // threads_per_row) * threads_per_row\n if largest >= _MIN_THREADS:\n return largest\n\n # If largest multiple is below _MIN_THREADS, use smallest valid one\n candidate = threads_per_row\n while candidate < _MIN_THREADS:\n candidate += threads_per_row\n if candidate <= _MAX_THREADS:\n return candidate\n\n # Fallback (shouldn't happen for reasonable K)\n return _MAX_THREADS\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Linear Layout — Flat SF-Block Iteration\n# =============================================================================\n\n\nclass NVFP4QuantizeLinearKernel:\n \"\"\"\n NVFP4 quantization kernel optimized for LINEAR layout.\n\n Uses flat SF-block iteration for efficient memory access. Row and\n column indices are derived from the flat SF index via integer division.\n\n No padding passes are needed since for linear layout:\n - padded_m == m (no row padding)\n - padded_sf_cols == num_sf_blocks_per_row (no column padding)\n\n This kernel is M-agnostic: compiled once per (K, dtype, pdl) combination.\n Each thread handles one SF block (16 elements).\n \"\"\"\n\n WARPS_PER_BLOCK = _LINEAR_WARPS_PER_BLOCK\n SF_BLOCKS_PER_TB = _LINEAR_SF_BLOCKS_PER_TB\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n enable_pdl: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n total_sf_blocks: Int32,\n num_blocks: Int32,\n mGlobalScale: cute.Tensor,\n stream,\n ):\n threads_per_block = self.WARPS_PER_BLOCK * WARP_SIZE\n\n self.kernel(mInput, mOutput, mScales, M, total_sf_blocks, mGlobalScale).launch(\n grid=[num_blocks, 1, 1],\n block=[threads_per_block, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n total_sf_blocks: Int32,\n mGlobalScale: cute.Tensor,\n ):\n \"\"\"\n NVFP4 quantization with flat SF-block iteration for linear layout.\n\n Each thread handles one SF block (16 elements). Row and column\n indices are derived from the flat SF index.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Read global_scale from device memory (avoids CPU-GPU sync at launch)\n global_scale = Float32(mGlobalScale[Int32(0)])\n\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n sf_blocks_per_tb = self.SF_BLOCKS_PER_TB\n stride = grid_dim_x * sf_blocks_per_tb\n\n # Flat SF-block iteration\n sf_idx = bidx * sf_blocks_per_tb + tidx\n\n while sf_idx < total_sf_blocks:\n row_idx = sf_idx // num_sf_blocks_per_row\n col_idx = sf_idx % num_sf_blocks_per_row\n\n elem_base = col_idx * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n # Process block: load, compute scale, convert to E2M1\n if cutlass.const_expr(self.is_fp8):\n scale_fp8, packed64 = process_nvfp4_block_fp8(\n row_input, elem_base, global_scale\n )\n elif cutlass.const_expr(self.is_bfloat16):\n scale_fp8, packed64 = process_nvfp4_block_bfloat(\n row_input, elem_base, global_scale\n )\n else:\n scale_fp8, packed64 = process_nvfp4_block_half(\n row_input, elem_base, global_scale\n )\n\n # Write scale factor using linear indexing\n sf_offset = compute_sf_index_linear_gpu(\n row_idx, col_idx, num_sf_blocks_per_row\n )\n mScales[sf_offset] = scale_fp8\n\n # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = col_idx * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n sf_idx = sf_idx + stride\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for Swizzled Layout — Row-Based Iteration\n# =============================================================================\n\n\nclass NVFP4QuantizeSwizzledKernel:\n \"\"\"\n NVFP4 quantization kernel optimized for SWIZZLED (128x4 or 8x4) layout.\n\n Key optimizations:\n - Multi-row processing: threads process multiple rows per block when K is small\n - Row-based iteration with grid-stride loop\n - Padding row fast path - only zero out scale factors\n\n Thread utilization optimization:\n - Dynamic thread count based on K for 100% thread utilization\n - For small K: Multiple rows processed per block iteration\n - For large K: Single row with column loop\n\n For NVFP4, each thread processes 1 SF block (16 elements) independently,\n so threads_per_row = num_sf_blocks_per_row = K/16.\n\n This kernel is M-agnostic: compiled once per (K, dtype, sf_layout, pdl)\n combination. M-dependent values (M, padded_M) are passed at runtime.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n # Compute optimal thread count for 100% utilization\n self.num_threads = _compute_optimal_threads(K)\n self.threads_per_row = self.num_sf_blocks_per_row # 1 thread per SF block\n\n # Multi-row processing constants (compile-time)\n if self.threads_per_row <= self.num_threads:\n self.rows_per_block = self.num_threads // self.threads_per_row\n self.needs_col_loop = False\n else:\n self.rows_per_block = 1\n self.needs_col_loop = True\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n \"\"\"Compute scale factor offset based on layout (compile-time dispatch).\"\"\"\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n mGlobalScale: cute.Tensor,\n stream,\n ):\n self.kernel(mInput, mOutput, mScales, M, padded_M, mGlobalScale).launch(\n grid=[num_blocks, 1, 1],\n block=[self.num_threads, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n mGlobalScale: cute.Tensor,\n ):\n \"\"\"\n Row-based kernel for swizzled layout.\n\n When K is small: each block processes multiple rows simultaneously.\n When K is large: each block processes one row with column loop.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Read global_scale from device memory (avoids CPU-GPU sync at launch)\n global_scale = Float32(mGlobalScale[Int32(0)])\n\n # Compile-time constants\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n threads_per_row = self.threads_per_row\n rows_per_block = self.rows_per_block\n\n if cutlass.const_expr(self.needs_col_loop):\n # Large K path: single row per block iteration with column loop\n # Each thread maps to one SF block; threads stride over columns\n num_threads = self.num_threads\n\n row_idx = bidx\n while row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - only zero out scale factors\n sf_col_idx = tidx\n while sf_col_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + num_threads\n else:\n # Normal path: process actual data row with column loop\n sf_col_idx = tidx\n while sf_col_idx < num_sf_blocks_per_row:\n elem_base = sf_col_idx * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n # Process block: load, compute scale, convert to E2M1\n if cutlass.const_expr(self.is_fp8):\n scale_fp8, packed64 = process_nvfp4_block_fp8(\n row_input, elem_base, global_scale\n )\n elif cutlass.const_expr(self.is_bfloat16):\n scale_fp8, packed64 = process_nvfp4_block_bfloat(\n row_input, elem_base, global_scale\n )\n else:\n scale_fp8, packed64 = process_nvfp4_block_half(\n row_input, elem_base, global_scale\n )\n\n # Write scale factor using swizzled indexing\n sf_offset = self._compute_sf_offset(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n\n # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = sf_col_idx * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n sf_col_idx = sf_col_idx + num_threads\n\n # Handle padding columns for this row\n sf_col_idx = num_sf_blocks_per_row + tidx\n while sf_col_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, sf_col_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_col_idx = sf_col_idx + num_threads\n\n row_idx = row_idx + grid_dim_x\n else:\n # Small K path: multi-row processing\n # Thread mapping: tidx -> (row_in_block, sf_idx_in_row)\n row_in_block = tidx // threads_per_row\n sf_idx_in_row = tidx % threads_per_row\n\n # Grid-stride loop over row batches\n row_batch_idx = bidx\n # Initialize row_idx before while loop (CuTe DSL requires variables\n # modified in while loops to be defined before the loop)\n row_idx = row_batch_idx * rows_per_block + row_in_block\n while row_batch_idx * rows_per_block < padded_M:\n if row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n # Fast path: padding row - zero out ALL padded_sf_cols\n # Thread-stride loop since padded_sf_cols may exceed\n # threads_per_row (e.g. K=32: threads_per_row=2,\n # padded_sf_cols=4)\n local_sf_idx = sf_idx_in_row\n while local_sf_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, local_sf_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n local_sf_idx = local_sf_idx + threads_per_row\n else:\n # Normal path: process actual data\n if sf_idx_in_row < num_sf_blocks_per_row:\n elem_base = sf_idx_in_row * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n # Process block: load, compute scale, convert to E2M1\n if cutlass.const_expr(self.is_fp8):\n scale_fp8, packed64 = process_nvfp4_block_fp8(\n row_input, elem_base, global_scale\n )\n elif cutlass.const_expr(self.is_bfloat16):\n scale_fp8, packed64 = process_nvfp4_block_bfloat(\n row_input, elem_base, global_scale\n )\n else:\n scale_fp8, packed64 = process_nvfp4_block_half(\n row_input, elem_base, global_scale\n )\n\n # Write scale factor using swizzled indexing\n sf_offset = self._compute_sf_offset(\n row_idx, sf_idx_in_row, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n\n # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = sf_idx_in_row * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n # Handle padding SF columns for this row\n # Thread-stride loop starting from first padding column\n if cutlass.const_expr(\n self.num_sf_blocks_per_row != self.padded_sf_cols\n ):\n pad_col = num_sf_blocks_per_row + sf_idx_in_row\n while pad_col < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, pad_col, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n pad_col = pad_col + threads_per_row\n\n row_batch_idx = row_batch_idx + grid_dim_x\n # Update row_idx for next iteration\n row_idx = row_batch_idx * rows_per_block + row_in_block\n\n # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL TMA Kernel Class for NVFP4\n# =============================================================================\n\n_TMA_ROW_TILE = 16\n_TMA_COL_TILE = 64 # Per-warp column tile\n_TMA_NUM_CONSUMER_WARPS = 8\n_TMA_NUM_STAGES = 4\n_TMA_COLS_PER_STAGE = _TMA_NUM_CONSUMER_WARPS * _TMA_COL_TILE # 512\n\n\ndef _round_up(x: int, d: int) -> int:\n return ((x + d - 1) // d) * d\n\n\nclass NVFP4QuantizeTMAKernel:\n \"\"\"\n TMA-based NVFP4 quantization kernel with pipelined producer-consumer\n warp specialization, matching the CUDA TMA kernel architecture.\n\n Architecture (matches csrc/nv_internal/.../quantization.cuh):\n - 1 producer warp (warp 0) issues TMA G2S loads into staged SMEM buffers\n - 8 consumer warps (warps 1-8) read from SMEM, quantize, write to GMEM\n - PipelineTmaAsync manages multi-stage buffering (4 stages)\n - Each TMA tile: [16, 512] = 16 rows x 8 warps x 64 cols per warp\n - Each consumer warp: 4 threads/row x 8 rows/warp, 2 row iterations\n - Each thread: 16 elements (1 SF block) via 2 x ld.shared.v4.u32\n - Grid-stride loop over row tiles, inner loop over K/512 col chunks\n\n Effective when M >= 1024 and K is a multiple of 512.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n\n assert not self.is_fp8, \"FP8 input not yet supported for TMA kernel\"\n assert K % _TMA_COLS_PER_STAGE == 0, (\n f\"K ({K}) must be a multiple of {_TMA_COLS_PER_STAGE} for TMA kernel\"\n )\n\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n self.num_col_chunks = K // _TMA_COLS_PER_STAGE\n\n if sf_layout == SF_LAYOUT_LINEAR:\n self.padded_sf_cols = self.num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n else:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n\n self.num_consumer_warps = _TMA_NUM_CONSUMER_WARPS # 8\n self.num_stages = _TMA_NUM_STAGES\n self.producer_warp_id = 0 # Warp 0 is producer (matches CUDA kernel)\n self.threads_per_cta = 32 * (self.num_consumer_warps + 1) # 288\n self.rows_per_block = _TMA_ROW_TILE\n self.buffer_align_bytes = 1024\n self.cluster_shape_mn = (1, 1)\n self.elems_per_stage = _TMA_ROW_TILE * _TMA_COLS_PER_STAGE # 8192\n\n # Thread indexing constants (matches CUDA TmaKernelTraitsTwoBytes)\n self.THREADS_PER_ROW = 4 # laneIdx % 4\n self.ROWS_PER_WARP = 8 # 32 / 4\n self.ELTS_PER_THREAD = NVFP4_SF_VEC_SIZE # 16\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n if cutlass.const_expr(self.sf_is_8x4):\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_linear_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def _quantize_sf_block(\n self,\n h0: cutlass.Uint32,\n h1: cutlass.Uint32,\n h2: cutlass.Uint32,\n h3: cutlass.Uint32,\n h4: cutlass.Uint32,\n h5: cutlass.Uint32,\n h6: cutlass.Uint32,\n h7: cutlass.Uint32,\n global_row: Int32,\n sf_col: Int32,\n global_scale: Float32,\n M: Int32,\n padded_M: Int32,\n padded_sf_cols: Int32,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n ):\n \"\"\"Quantize one 16-element SF block and write results to GMEM.\"\"\"\n from ...cute_dsl.fp4_common import (\n cvt_f32_to_e4m3,\n nvfp4_compute_output_scale,\n rcp_approx_ftz,\n )\n\n if global_row < padded_M:\n is_padding_row = global_row >= M\n\n if is_padding_row:\n sf_offset = self._compute_sf_offset(global_row, sf_col, padded_sf_cols)\n mScales[sf_offset] = Uint8(0)\n else:\n if cutlass.const_expr(self.is_bfloat16):\n block_max_h2 = bfloat2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n else:\n block_max_h2 = half2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & cutlass.Uint32(0xFF))\n\n output_scale = nvfp4_compute_output_scale(scale_fp8_u32, global_scale)\n\n if cutlass.const_expr(self.is_bfloat16):\n packed64 = bfloat2x8_to_e2m1x16_packed(\n h0, h1, h2, h3, h4, h5, h6, h7, output_scale\n )\n else:\n packed64 = half2x8_to_e2m1x16_packed(\n h0, h1, h2, h3, h4, h5, h6, h7, output_scale\n )\n\n sf_offset = self._compute_sf_offset(global_row, sf_col, padded_sf_cols)\n mScales[sf_offset] = scale_fp8\n\n row_output = mOutput[global_row, None]\n out_base = sf_col * Int32(NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n mGlobalScale: cute.Tensor,\n stream,\n ):\n # 3D global tensor: [padded_M, K/64, 64] so each warp's 64-col\n # stripe is the contiguous innermost dimension, matching the CUDA\n # TMA kernel's 3D tensor map.\n gInput = cute.make_tensor(\n mInput.iterator,\n cute.make_layout(\n (padded_M, self.K // _TMA_COL_TILE, _TMA_COL_TILE),\n stride=(self.K, _TMA_COL_TILE, 1),\n ),\n )\n\n # SMEM layout per stage: [rows=16, warps=8, cols_per_warp=64]\n # with SWIZZLE_128B applied. Within each warp's [16, 64] tile the\n # row stride is 64 elems = 128 bytes, putting row bits in the S=3\n # range of the swizzle so different rows map to different banks.\n smem_swizzle = cute.make_swizzle(3, 4, 3) # SWIZZLE_128B for 2B types\n smem_outer_single = cute.make_layout(\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n stride=(_TMA_COL_TILE, _TMA_ROW_TILE * _TMA_COL_TILE, 1),\n )\n smem_single_composed = cute.make_composed_layout(\n smem_swizzle, 0, smem_outer_single\n )\n\n cta_tiler = (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE)\n tma_atom, tma_tensor = cpasync.make_tiled_tma_atom(\n cpasync.CopyBulkTensorTileG2SOp(),\n gInput,\n smem_single_composed,\n cta_tiler,\n )\n\n total_smem_elems = self.elems_per_stage * self.num_stages\n # Staged outer layout (no swizzle — swizzle passed separately)\n smem_outer_staged = cute.make_layout(\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE, self.num_stages),\n stride=(\n _TMA_COL_TILE,\n _TMA_ROW_TILE * _TMA_COL_TILE,\n 1,\n self.elems_per_stage,\n ),\n )\n # Flat layout for manual-swizzle consumer reads\n smem_layout_flat = cute.make_layout((total_smem_elems,))\n\n self.num_tma_load_bytes = cute.size_in_bytes(self.dtype, smem_outer_single)\n\n @cute.struct\n class SharedStorage:\n load_full_mbar: cute.struct.MemRange[cutlass.Int64, self.num_stages]\n load_empty_mbar: cute.struct.MemRange[cutlass.Int64, self.num_stages]\n smem_data: cute.struct.Align[\n cute.struct.MemRange[self.dtype, total_smem_elems],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n tma_atom,\n tma_tensor,\n mOutput,\n mScales,\n M,\n padded_M,\n mGlobalScale,\n smem_outer_staged,\n smem_swizzle,\n smem_layout_flat,\n ).launch(\n grid=[num_blocks, 1, 1],\n block=[self.threads_per_cta, 1, 1],\n max_number_threads=[\n self.threads_per_cta,\n 1,\n 1,\n ], # __launch_bounds__(288, 2)\n min_blocks_per_mp=2,\n cluster=(*self.cluster_shape_mn, 1),\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n tma_atom: cute.CopyAtom,\n gInput_tma: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n mGlobalScale: cute.Tensor,\n smem_outer_staged: cute.Layout,\n smem_swizzle: cute.Swizzle,\n smem_layout_flat: cute.Layout,\n ):\n from ...cute_dsl.fp4_common import (\n get_smem_ptr_as_int32,\n ld_shared_v4_u32,\n )\n\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n lane_idx = tidx % 32\n\n global_scale = Float32(mGlobalScale[Int32(0)])\n padded_sf_cols = self.padded_sf_cols\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n num_col_chunks = self.num_col_chunks\n elems_per_stage = self.elems_per_stage\n\n # ---- SMEM allocation ----\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n load_mbar_ptr = storage.load_full_mbar.data_ptr()\n # Swizzled tensor for TMA partition (address-space-correct writes)\n sData_staged = storage.smem_data.get_tensor(\n smem_outer_staged, swizzle=smem_swizzle\n )\n # Flat tensor for manual-swizzle consumer reads\n sData_flat = storage.smem_data.get_tensor(smem_layout_flat)\n\n # ---- Pipeline setup ----\n load_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=load_mbar_ptr,\n num_stages=self.num_stages,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread, 1),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread, self.num_consumer_warps\n ),\n tx_count=self.num_tma_load_bytes,\n cta_layout_vmnk=cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)), (1,)\n ),\n defer_sync=True,\n )\n\n pipeline_init_arrive(cluster_shape_mn=self.cluster_shape_mn, is_relaxed=True)\n pipeline_init_wait(cluster_shape_mn=self.cluster_shape_mn)\n\n # ---- TMA partition (3D: rows x warps x cols_per_warp) ----\n gSrc_tiled = cute.local_tile(\n gInput_tma,\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n (None, None, None),\n )\n tAsA, tAgA = cpasync.tma_partition(\n tma_atom,\n 0,\n cute.make_layout(1),\n cute.group_modes(sData_staged, 0, 3), # Group 3 tile modes\n cute.group_modes(gSrc_tiled, 0, 3),\n )\n\n num_row_tiles = cute.ceil_div(padded_M, _TMA_ROW_TILE)\n\n # ---- Consumer thread indexing (matches CUDA TmaKernelTraitsTwoBytes) ----\n # 4 threads per row, 8 rows per warp, 2 row iterations per stage\n col_idx_local = lane_idx % Int32(self.THREADS_PER_ROW)\n row_idx_local = lane_idx // Int32(self.THREADS_PER_ROW)\n\n # ======== Producer warp (warp 0) ========\n if warp_idx == self.producer_warp_id:\n producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_stages\n )\n\n row_tile_idx = bidx\n while row_tile_idx < num_row_tiles:\n col_chunk = Int32(0)\n while col_chunk < num_col_chunks:\n load_pipeline.producer_acquire(producer_state)\n\n cute.copy(\n tma_atom,\n tAgA[(None, row_tile_idx, col_chunk, 0)],\n tAsA[(None, producer_state.index)],\n tma_bar_ptr=load_pipeline.producer_get_barrier(producer_state),\n )\n\n producer_state.advance()\n col_chunk = col_chunk + Int32(1)\n\n row_tile_idx = row_tile_idx + grid_dim_x\n\n load_pipeline.producer_tail(producer_state)\n\n # ======== Consumer warps (warps 1-8) ========\n if warp_idx > 0:\n consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_stages\n )\n\n # 0-indexed consumer warp id\n consumer_warp_idx = warp_idx - Int32(1)\n\n # Pre-compute warp tile base offset (constant per warp)\n # SMEM 3D layout: [rows=16, warps=8, cols=64] per stage\n # stride: [64, 1024, 1] → warp tile base = warp * 1024\n warp_tile_elems = _TMA_ROW_TILE * _TMA_COL_TILE # 1024\n warp_tile_base = consumer_warp_idx * Int32(warp_tile_elems)\n\n # Float4 base position for this thread (0, 2, 4, 6)\n f4_base = col_idx_local * Int32(2)\n\n # Global column offset for SF index: warp's column within K\n base_col_in_stage = consumer_warp_idx * Int32(\n _TMA_COL_TILE\n ) + col_idx_local * Int32(self.ELTS_PER_THREAD)\n\n row_tile_idx = bidx\n while row_tile_idx < num_row_tiles:\n base_row = row_tile_idx * Int32(_TMA_ROW_TILE)\n\n col_chunk = Int32(0)\n while col_chunk < num_col_chunks:\n load_pipeline.consumer_wait(consumer_state)\n stage = consumer_state.index\n\n # ---- Read ALL SMEM data with SWIZZLE_128B addressing ----\n # Within each warp's [16,64] tile, the XOR pattern matches\n # CUDA's load_input_vec: float4_idx ^= row & 7\n # Physical elem offset in warp tile for (row, float4 f):\n # row * 64 + (f ^ (row & 7)) * 8\n stage_base = stage * Int32(elems_per_stage)\n\n # Row iteration 0 (row_idx_local = 0..7)\n r0_xor = row_idx_local & Int32(7)\n r0_f4_0 = f4_base ^ r0_xor\n r0_f4_1 = (f4_base + Int32(1)) ^ r0_xor\n r0_row_base = (\n stage_base\n + warp_tile_base\n + row_idx_local * Int32(_TMA_COL_TILE)\n )\n r0_addr_0 = get_smem_ptr_as_int32(\n sData_flat, r0_row_base + r0_f4_0 * Int32(8)\n )\n r0_addr_1 = get_smem_ptr_as_int32(\n sData_flat, r0_row_base + r0_f4_1 * Int32(8)\n )\n r0_h0, r0_h1, r0_h2, r0_h3 = ld_shared_v4_u32(r0_addr_0)\n r0_h4, r0_h5, r0_h6, r0_h7 = ld_shared_v4_u32(r0_addr_1)\n\n # Row iteration 1 (row = row_idx_local + 8)\n r1_row = row_idx_local + Int32(self.ROWS_PER_WARP)\n r1_xor = r1_row & Int32(7)\n r1_f4_0 = f4_base ^ r1_xor\n r1_f4_1 = (f4_base + Int32(1)) ^ r1_xor\n r1_row_base = (\n stage_base + warp_tile_base + r1_row * Int32(_TMA_COL_TILE)\n )\n r1_addr_0 = get_smem_ptr_as_int32(\n sData_flat, r1_row_base + r1_f4_0 * Int32(8)\n )\n r1_addr_1 = get_smem_ptr_as_int32(\n sData_flat, r1_row_base + r1_f4_1 * Int32(8)\n )\n r1_h0, r1_h1, r1_h2, r1_h3 = ld_shared_v4_u32(r1_addr_0)\n r1_h4, r1_h5, r1_h6, r1_h7 = ld_shared_v4_u32(r1_addr_1)\n\n # ---- Quantize and write: both row iterations ----\n # Global column base for SF index computation\n global_col_base = col_chunk * Int32(_TMA_COLS_PER_STAGE)\n sf_col = (global_col_base + base_col_in_stage) // Int32(\n NVFP4_SF_VEC_SIZE\n )\n\n # Row iteration 0\n global_row_0 = base_row + row_idx_local\n self._quantize_sf_block(\n r0_h0,\n r0_h1,\n r0_h2,\n r0_h3,\n r0_h4,\n r0_h5,\n r0_h6,\n r0_h7,\n global_row_0,\n sf_col,\n global_scale,\n M,\n padded_M,\n padded_sf_cols,\n mOutput,\n mScales,\n )\n\n # Row iteration 1\n global_row_1 = base_row + row_idx_local + Int32(self.ROWS_PER_WARP)\n self._quantize_sf_block(\n r1_h0,\n r1_h1,\n r1_h2,\n r1_h3,\n r1_h4,\n r1_h5,\n r1_h6,\n r1_h7,\n global_row_1,\n sf_col,\n global_scale,\n M,\n padded_M,\n padded_sf_cols,\n mOutput,\n mScales,\n )\n\n # ---- Release pipeline after all work (matches CUDA pattern) ----\n load_pipeline.consumer_release(consumer_state)\n consumer_state.advance()\n\n col_chunk = col_chunk + Int32(1)\n\n # Zero padding SF columns for swizzled layouts\n if cutlass.const_expr(self.sf_layout != SF_LAYOUT_LINEAR):\n consumer_tid = (warp_idx - Int32(1)) * Int32(32) + lane_idx\n if consumer_tid < _TMA_ROW_TILE:\n pad_row_idx = base_row + consumer_tid\n if pad_row_idx < padded_M:\n padding_sf = Int32(num_sf_blocks_per_row)\n while padding_sf < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n pad_row_idx, padding_sf, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n padding_sf = padding_sf + Int32(1)\n\n row_tile_idx = row_tile_idx + grid_dim_x\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# PyTorch Integration with TVM-FFI\n# =============================================================================\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile NVFP4 kernel with TVM-FFI.\n\n Cached by (K, dtype_key, sf_layout, pdl) - M-agnostic, device-independent\n compilation.\n\n Args:\n dtype_key: One of \"float16\", \"bfloat16\", \"float8_e4m3fn\".\n\n Returns:\n For linear layout: (compiled_kernel, sf_blocks_per_tb)\n For swizzled layout: (compiled_kernel, rows_per_block)\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n \"float8_e4m3fn\": cutlass.Float8E4M3FN,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n\n # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n sym_scale_size = cute.sym_int()\n\n # Common fake tensors\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n if sf_layout == SF_LAYOUT_LINEAR:\n linear_obj = NVFP4QuantizeLinearKernel(cutlass_dtype, K, enable_pdl)\n\n compiled_kernel = cute.compile(\n linear_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(1), # Dummy total_sf_blocks\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, linear_obj.SF_BLOCKS_PER_TB\n else:\n swizzled_obj = NVFP4QuantizeSwizzledKernel(\n cutlass_dtype, K, sf_layout=sf_layout, enable_pdl=enable_pdl\n )\n\n compiled_kernel = cute.compile(\n swizzled_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(128), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, swizzled_obj.rows_per_block\n\n\n_TMA_MIN_M = 1024\n# TMA wins when the total problem is large enough to amortize pipeline overhead.\n# Empirically, floor(log2(M)) + floor(log2(K)) >= 25 is the crossover where TMA\n# outperforms the default vectorized-load kernel, validated on B200 and SM120.\n# We use bit_length()-1 (i.e., floor(log2)) rather than m*k to keep the boundary\n# aligned with the power-of-2 grid it was tuned on.\n_TMA_LOG2_MK_THRESHOLD = 25\n\n\ndef _should_use_tma(m: int, k: int, dtype: torch.dtype) -> bool:\n \"\"\"Determine if TMA kernel should be used based on problem dimensions.\"\"\"\n if dtype == torch.float8_e4m3fn:\n return False\n if k % _TMA_COLS_PER_STAGE != 0:\n return False\n if m < _TMA_MIN_M:\n return False\n # Use log2(M) + log2(K) threshold for the crossover point\n return m.bit_length() - 1 + k.bit_length() - 1 >= _TMA_LOG2_MK_THRESHOLD\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4_tma(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile TMA-based NVFP4 kernel with TVM-FFI.\n\n Cached by (K, dtype_key, sf_layout, pdl).\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n kernel_obj = NVFP4QuantizeTMAKernel(\n cutlass_dtype, K, sf_layout=sf_layout, enable_pdl=enable_pdl\n )\n\n sym_m = cute.sym_int()\n sym_padded_m = cute.sym_int()\n\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_padded_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(1024), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, kernel_obj.rows_per_block\n\n\n@flashinfer_api\ndef nvfp4_quantize_cute_dsl(\n input: torch.Tensor,\n global_scale: torch.Tensor,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n \"\"\"\n Quantize input tensor to NVFP4 format using CuTe-DSL kernel.\n\n This is a GPU implementation matching FlashInfer's nvfp4_quantize() behavior:\n - E4M3 scale factors (FP8)\n - E2M1 output format (4-bit, 2 values per byte)\n - Supports 128x4, 8x4, and linear scale factor layouts\n - sf_vec_size=16\n\n The kernel is compiled once per (K, dtype, sf_layout, pdl) combination and\n handles varying M (batch size) at runtime without recompilation.\n\n Args:\n input: Input tensor of shape [M, K] with dtype fp16/bf16/float8_e4m3fn\n global_scale: Scalar tensor (float32) for NVFP4 global scale factor\n sf_layout: Scale factor layout (0=128x4, 1=8x4, 2=linear).\n enable_pdl: Whether to enable PDL (Programmatic Dependent Launch).\n If None, automatically detects based on device capability (SM >= 9.0).\n\n Returns:\n Tuple of:\n - fp4_tensor: Quantized tensor of shape [M, K/2] with dtype uint8\n - scale_tensor: E4M3 scale factors as uint8 tensor\n reshaped to [padded_rows, K/16]\n \"\"\"\n from ...utils import device_support_pdl\n\n _valid_sf_layouts = (SF_LAYOUT_128x4, SF_LAYOUT_8x4, SF_LAYOUT_LINEAR)\n assert sf_layout in _valid_sf_layouts, (\n f\"sf_layout must be one of {_valid_sf_layouts}, got {sf_layout}\"\n )\n _supported_dtypes = (torch.float16, torch.bfloat16, torch.float8_e4m3fn)\n assert input.dtype in _supported_dtypes, (\n f\"Input dtype must be one of {_supported_dtypes}, got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n\n enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n\n if input.dim() > 2:\n m = input.numel() // input.shape[-1]\n k = input.shape[-1]\n input = input.reshape(m, k)\n else:\n m, k = input.shape\n\n assert k % NVFP4_SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by NVFP4_SF_VEC_SIZE={NVFP4_SF_VEC_SIZE}\"\n )\n\n input = input.contiguous()\n\n _torch_to_dtype_key = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n torch.float8_e4m3fn: \"float8_e4m3fn\",\n }\n dtype_key = _torch_to_dtype_key[input.dtype]\n\n if isinstance(global_scale, torch.Tensor):\n global_scale_tensor = (\n global_scale.float().reshape(1).contiguous().to(input.device)\n )\n else:\n global_scale_tensor = torch.tensor(\n [float(global_scale)], dtype=torch.float32, device=input.device\n )\n\n num_sm = get_num_sm(input.device)\n\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n\n use_tma = _should_use_tma(m, k, input.dtype)\n\n if use_tma:\n tma_row_tile = _TMA_ROW_TILE\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = _round_up(m, tma_row_tile)\n padded_sf_cols = num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n padded_m = _round_up(m, max(tma_row_tile, 8))\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n else:\n padded_m = _round_up(m, max(tma_row_tile, ROW_TILE_SIZE))\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n\n scale_output_size = padded_m * padded_sf_cols\n\n kernel_fn, rows_per_block = _get_compiled_kernel_nvfp4_tma(\n dtype_key, k, sf_layout, enable_pdl\n )\n\n # Match CUDA TMA kernel: grid = min(row_tiles, SM_count * 2)\n tma_target_grid = num_sm * 2\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block, tma_target_grid\n )\n\n input_padded = input\n if padded_m > m:\n input_padded = torch.zeros(\n padded_m, k, dtype=input.dtype, device=input.device\n )\n input_padded[:m, :] = input\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input_padded,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_tensor,\n )\n\n if sf_layout == SF_LAYOUT_LINEAR:\n scale_output = scale_output[: m * num_sf_blocks_per_row]\n\n # Reshape using padded_sf_cols for swizzled layouts (the buffer is\n # physically padded and stores data in swizzled order). For linear\n # layout the padding is already trimmed above.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n # Non-TMA path: dual-path dispatch\n # Get or compile kernel (device-independent)\n kernel_fn, block_unit = _get_compiled_kernel_nvfp4(\n dtype_key, k, sf_layout, enable_pdl\n )\n\n target_grid = num_sm * _BLOCKS_PER_SM\n\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = m\n padded_sf_cols = num_sf_blocks_per_row\n total_sf_blocks = m * num_sf_blocks_per_row\n scale_output_size = total_sf_blocks\n\n sf_blocks_per_tb = block_unit\n num_blocks = min(\n (total_sf_blocks + sf_blocks_per_tb - 1) // sf_blocks_per_tb,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n total_sf_blocks,\n num_blocks,\n global_scale_tensor,\n )\n else:\n if sf_layout == SF_LAYOUT_8x4:\n row_tile_size = 8\n else:\n row_tile_size = ROW_TILE_SIZE # 128\n padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n scale_output_size = padded_m * padded_sf_cols\n\n rows_per_block = block_unit\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block,\n target_grid,\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_tensor,\n )\n\n # Reshape using padded_sf_cols: for swizzled layouts the buffer includes\n # column padding; for linear layout padded_sf_cols == num_sf_blocks_per_row.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n\n__all__ = [\n \"SF_LAYOUT_128x4\",\n \"SF_LAYOUT_8x4\",\n \"SF_LAYOUT_LINEAR\",\n \"NVFP4QuantizeLinearKernel\",\n \"NVFP4QuantizeSwizzledKernel\",\n \"NVFP4QuantizeTMAKernel\",\n \"nvfp4_quantize_cute_dsl\",\n \"_get_compiled_kernel_nvfp4\",\n \"_get_compiled_kernel_nvfp4_tma\",\n]\n"},"diff":{"kind":"string","value":"--- flashinfer/quantization/kernels/nvfp4_quantize.py\n+++ flashinfer/quantization/kernels/nvfp4_quantize.py\n@@ -19,10 +19,15 @@\n NVFP4 quantization kernel using CuTe-DSL.\n Supports multiple scale factor layouts: swizzled 128x4, swizzled 8x4, and linear.\n \n+Dual-path optimization following the MXFP4 pattern:\n+- Linear layout: flat SF-block iteration for 100% thread utilization\n+- Swizzled layout: row-based iteration with multi-row / column-loop paths\n+\n Key differences from MXFP4:\n - sf_vec_size=16 (vs 32 for MXFP4)\n - E4M3 scale factors (vs UE8M0 for MXFP4)\n - User-provided global_scale (vs auto-computed for MXFP4)\n+- 3 layouts: 128x4, 8x4, linear (vs 128x4, linear for MXFP4)\n \"\"\"\n \n import functools\n@@ -41,6 +46,7 @@\n from ...cute_dsl.utils import get_num_sm\n from ..quantization_cute_dsl_utils import (\n NVFP4_SF_VEC_SIZE,\n+ WARP_SIZE,\n ROW_TILE_SIZE,\n compute_sf_index_swizzled_128x4_gpu,\n compute_sf_index_swizzled_8x4_gpu,\n@@ -60,74 +66,221 @@\n SF_LAYOUT_8x4 = 1\n SF_LAYOUT_LINEAR = 2\n \n+# Blocks per SM for occupancy target\n _BLOCKS_PER_SM = 4\n+\n+# Maximum threads per block\n _MAX_THREADS_PER_BLOCK = 1024\n+\n+# Thread count bounds for swizzled kernel\n _MIN_THREADS = 128\n _MAX_THREADS = 512\n-_DEFAULT_THREADS = 256\n-\n-\n-def _compute_optimal_threads_for_k(K: int) -> int:\n+\n+# Linear kernel: fixed 16 warps (512 threads), 1 SF block per thread\n+_LINEAR_WARPS_PER_BLOCK = 16\n+_LINEAR_SF_BLOCKS_PER_TB = _LINEAR_WARPS_PER_BLOCK * WARP_SIZE # 512\n+\n+\n+def _compute_optimal_threads(K: int) -> int:\n \"\"\"\n- Compute optimal thread count for 100% thread utilization.\n-\n- For NVFP4, each thread processes one SF block (16 elements).\n- threads_per_row = K / 16 = num_sf_blocks_per_row\n-\n- We prefer LARGER thread counts (up to _MAX_THREADS) for better occupancy,\n- while maintaining 100% thread utilization.\n+ Compute optimal thread count for 100% utilization in the swizzled kernel.\n+\n+ For NVFP4, each thread processes 1 SF block (16 elements), so:\n+ threads_per_row = K / 16\n+\n+ We want num_threads to be a multiple of threads_per_row so that\n+ rows_per_block = num_threads / threads_per_row is an integer.\n+\n+ We prefer LARGER thread counts (up to _MAX_THREADS) for better occupancy.\n+\n+ If threads_per_row > _MAX_THREADS, we use _MAX_THREADS with a column loop.\n+\n+ Args:\n+ K: Number of columns (must be divisible by 16)\n+\n+ Returns:\n+ Optimal number of threads per block\n \"\"\"\n- threads_per_row = K // NVFP4_SF_VEC_SIZE\n-\n- if threads_per_row >= _MAX_THREADS:\n+ threads_per_row = K // NVFP4_SF_VEC_SIZE # K / 16\n+\n+ if threads_per_row > _MAX_THREADS:\n+ # Column loop mode: use maximum threads\n return _MAX_THREADS\n \n- if threads_per_row <= _MAX_THREADS:\n- threads = (_MAX_THREADS // threads_per_row) * threads_per_row\n- if threads >= _MIN_THREADS:\n- return threads\n- threads = threads_per_row\n- while threads < _MIN_THREADS:\n- threads += threads_per_row\n- if threads <= _MAX_THREADS:\n- return threads\n-\n- return _DEFAULT_THREADS\n-\n-\n-def _compute_swizzled_layout_sf_size(\n- total_row: int, total_column: int, row_size: int = 128\n-) -> int:\n- \"\"\"Compute size of swizzled scale factor buffer.\"\"\"\n- padded_row = (total_row + row_size - 1) // row_size * row_size\n- padded_column = (total_column + 3) // 4 * 4\n- return padded_row * padded_column\n+ # Find largest multiple of threads_per_row in [_MIN_THREADS, _MAX_THREADS]\n+ largest = (_MAX_THREADS // threads_per_row) * threads_per_row\n+ if largest >= _MIN_THREADS:\n+ return largest\n+\n+ # If largest multiple is below _MIN_THREADS, use smallest valid one\n+ candidate = threads_per_row\n+ while candidate < _MIN_THREADS:\n+ candidate += threads_per_row\n+ if candidate <= _MAX_THREADS:\n+ return candidate\n+\n+ # Fallback (shouldn't happen for reasonable K)\n+ return _MAX_THREADS\n \n \n # =============================================================================\n-# CuTe-DSL Kernel Class for NVFP4 Swizzled Layout\n+# CuTe-DSL Kernel Class for Linear Layout — Flat SF-Block Iteration\n+# =============================================================================\n+\n+\n+class NVFP4QuantizeLinearKernel:\n+ \"\"\"\n+ NVFP4 quantization kernel optimized for LINEAR layout.\n+\n+ Uses flat SF-block iteration for efficient memory access. Row and\n+ column indices are derived from the flat SF index via integer division.\n+\n+ No padding passes are needed since for linear layout:\n+ - padded_m == m (no row padding)\n+ - padded_sf_cols == num_sf_blocks_per_row (no column padding)\n+\n+ This kernel is M-agnostic: compiled once per (K, dtype, pdl) combination.\n+ Each thread handles one SF block (16 elements).\n+ \"\"\"\n+\n+ WARPS_PER_BLOCK = _LINEAR_WARPS_PER_BLOCK\n+ SF_BLOCKS_PER_TB = _LINEAR_SF_BLOCKS_PER_TB\n+\n+ def __init__(\n+ self,\n+ dtype: cutlass.Numeric,\n+ K: int,\n+ enable_pdl: bool = False,\n+ ):\n+ self.dtype = dtype\n+ self.K = K\n+ self.is_bfloat16 = dtype == cutlass.BFloat16\n+ self.is_fp8 = dtype == cutlass.Float8E4M3FN\n+ self.enable_pdl = enable_pdl\n+\n+ assert K % NVFP4_SF_VEC_SIZE == 0\n+ self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n+\n+ @cute.jit\n+ def __call__(\n+ self,\n+ mInput: cute.Tensor,\n+ mOutput: cute.Tensor,\n+ mScales: cute.Tensor,\n+ M: Int32,\n+ total_sf_blocks: Int32,\n+ num_blocks: Int32,\n+ mGlobalScale: cute.Tensor,\n+ stream,\n+ ):\n+ threads_per_block = self.WARPS_PER_BLOCK * WARP_SIZE\n+\n+ self.kernel(mInput, mOutput, mScales, M, total_sf_blocks, mGlobalScale).launch(\n+ grid=[num_blocks, 1, 1],\n+ block=[threads_per_block, 1, 1],\n+ max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n+ min_blocks_per_mp=_BLOCKS_PER_SM,\n+ stream=stream,\n+ use_pdl=self.enable_pdl,\n+ )\n+\n+ @cute.kernel\n+ def kernel(\n+ self,\n+ mInput: cute.Tensor,\n+ mOutput: cute.Tensor,\n+ mScales: cute.Tensor,\n+ M: Int32,\n+ total_sf_blocks: Int32,\n+ mGlobalScale: cute.Tensor,\n+ ):\n+ \"\"\"\n+ NVFP4 quantization with flat SF-block iteration for linear layout.\n+\n+ Each thread handles one SF block (16 elements). Row and column\n+ indices are derived from the flat SF index.\n+ \"\"\"\n+ tidx, _, _ = cute.arch.thread_idx()\n+ bidx, _, _ = cute.arch.block_idx()\n+ grid_dim_x, _, _ = cute.arch.grid_dim()\n+\n+ if cutlass.const_expr(self.enable_pdl):\n+ cute.arch.griddepcontrol_wait()\n+\n+ # Read global_scale from device memory (avoids CPU-GPU sync at launch)\n+ global_scale = Float32(mGlobalScale[Int32(0)])\n+\n+ num_sf_blocks_per_row = self.num_sf_blocks_per_row\n+ sf_blocks_per_tb = self.SF_BLOCKS_PER_TB\n+ stride = grid_dim_x * sf_blocks_per_tb\n+\n+ # Flat SF-block iteration\n+ sf_idx = bidx * sf_blocks_per_tb + tidx\n+\n+ while sf_idx < total_sf_blocks:\n+ row_idx = sf_idx // num_sf_blocks_per_row\n+ col_idx = sf_idx % num_sf_blocks_per_row\n+\n+ elem_base = col_idx * NVFP4_SF_VEC_SIZE\n+ row_input = mInput[row_idx, None]\n+\n+ # Process block: load, compute scale, convert to E2M1\n+ if cutlass.const_expr(self.is_fp8):\n+ scale_fp8, packed64 = process_nvfp4_block_fp8(\n+ row_input, elem_base, global_scale\n+ )\n+ elif cutlass.const_expr(self.is_bfloat16):\n+ scale_fp8, packed64 = process_nvfp4_block_bfloat(\n+ row_input, elem_base, global_scale\n+ )\n+ else:\n+ scale_fp8, packed64 = process_nvfp4_block_half(\n+ row_input, elem_base, global_scale\n+ )\n+\n+ # Write scale factor using linear indexing\n+ sf_offset = compute_sf_index_linear_gpu(\n+ row_idx, col_idx, num_sf_blocks_per_row\n+ )\n+ mScales[sf_offset] = scale_fp8\n+\n+ # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n+ row_output = mOutput[row_idx, None]\n+ out_base = col_idx * (NVFP4_SF_VEC_SIZE // 2)\n+ out_ptr = get_ptr_as_int64(row_output, out_base)\n+ st_global_u64(out_ptr, packed64)\n+\n+ sf_idx = sf_idx + stride\n+\n+ # PDL: Signal that dependent kernels can start early\n+ if cutlass.const_expr(self.enable_pdl):\n+ cute.arch.griddepcontrol_launch_dependents()\n+\n+\n+# =============================================================================\n+# CuTe-DSL Kernel Class for Swizzled Layout — Row-Based Iteration\n # =============================================================================\n \n \n class NVFP4QuantizeSwizzledKernel:\n \"\"\"\n- NVFP4 quantization kernel supporting multiple scale factor layouts.\n-\n- Supported layouts:\n- - 128x4 (swizzled): Optimized for GEMM with large tileN\n- - 8x4 (swizzled): Optimized for GEMM with small tileN\n- - linear: Simple row-major layout, no swizzling\n-\n- Key features:\n- - E4M3 scale factors (FP8 format) with user-provided global_scale\n- - sf_vec_size=16 (each thread processes 16 elements)\n- - Multi-row processing when K is small, column loop when K is large\n+ NVFP4 quantization kernel optimized for SWIZZLED (128x4 or 8x4) layout.\n+\n+ Key optimizations:\n+ - Multi-row processing: threads process multiple rows per block when K is small\n - Row-based iteration with grid-stride loop\n- - Padding row fast path for zeroing scale factors\n+ - Padding row fast path - only zero out scale factors\n+\n+ Thread utilization optimization:\n+ - Dynamic thread count based on K for 100% thread utilization\n+ - For small K: Multiple rows processed per block iteration\n+ - For large K: Single row with column loop\n+\n+ For NVFP4, each thread processes 1 SF block (16 elements) independently,\n+ so threads_per_row = num_sf_blocks_per_row = K/16.\n \n This kernel is M-agnostic: compiled once per (K, dtype, sf_layout, pdl)\n- combination. M-dependent values (M, padded_M) and global_scale are passed\n- at runtime.\n+ combination. M-dependent values (M, padded_M) are passed at runtime.\n \"\"\"\n \n def __init__(\n@@ -148,21 +301,13 @@\n \n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n-\n- if sf_layout == SF_LAYOUT_LINEAR:\n- self.padded_sf_cols = self.num_sf_blocks_per_row\n- self.row_tile_size = 1\n- elif sf_layout == SF_LAYOUT_8x4:\n- self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n- self.row_tile_size = 8\n- else:\n- self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n- self.row_tile_size = ROW_TILE_SIZE # 128\n-\n- self.num_threads = _compute_optimal_threads_for_k(K)\n-\n- self.threads_per_row = self.num_sf_blocks_per_row\n-\n+ self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n+\n+ # Compute optimal thread count for 100% utilization\n+ self.num_threads = _compute_optimal_threads(K)\n+ self.threads_per_row = self.num_sf_blocks_per_row # 1 thread per SF block\n+\n+ # Multi-row processing constants (compile-time)\n if self.threads_per_row <= self.num_threads:\n self.rows_per_block = self.num_threads // self.threads_per_row\n self.needs_col_loop = False\n@@ -178,10 +323,7 @@\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n- if cutlass.const_expr(self.sf_is_8x4):\n- return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n- else:\n- return compute_sf_index_linear_gpu(row_idx, col_idx, padded_cols)\n+ return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n \n @cute.jit\n def __call__(\n@@ -195,11 +337,9 @@\n mGlobalScale: cute.Tensor,\n stream,\n ):\n- threads_per_block = self.num_threads\n-\n self.kernel(mInput, mOutput, mScales, M, padded_M, mGlobalScale).launch(\n grid=[num_blocks, 1, 1],\n- block=[threads_per_block, 1, 1],\n+ block=[self.num_threads, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n@@ -217,20 +357,10 @@\n mGlobalScale: cute.Tensor,\n ):\n \"\"\"\n- NVFP4 quantization kernel with swizzled scale factor layout.\n-\n- Dual-path kernel with compile-time selection:\n- - Small K path: Multi-row processing for improved thread utilization\n- - Large K path: Single row with column loop\n-\n- Each thread processes one SF block (16 elements):\n- 1. Load 16 elements (2 x 128-bit for fp16/bf16, 1 x 128-bit for fp8)\n- 2. Compute max absolute value using SIMD reduction\n- 3. Compute E4M3 scale: cvt_f32_to_e4m3(global_scale * max / 6.0)\n- 4. Store scale factor using layout-specific indexing\n- 5. Back-convert E4M3, compute output_scale = global_scale / scale_back\n- 6. Scale elements and convert to E2M1\n- 7. Store 8 bytes (16 FP4 values)\n+ Row-based kernel for swizzled layout.\n+\n+ When K is small: each block processes multiple rows simultaneously.\n+ When K is large: each block processes one row with column loop.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n@@ -242,28 +372,95 @@\n # Read global_scale from device memory (avoids CPU-GPU sync at launch)\n global_scale = Float32(mGlobalScale[Int32(0)])\n \n+ # Compile-time constants\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n- num_threads = self.num_threads\n+ threads_per_row = self.threads_per_row\n rows_per_block = self.rows_per_block\n- threads_per_row = self.threads_per_row\n-\n- if cutlass.const_expr(not self.needs_col_loop):\n- # ===== SMALL K PATH: Multi-row processing =====\n+\n+ if cutlass.const_expr(self.needs_col_loop):\n+ # Large K path: single row per block iteration with column loop\n+ # Each thread maps to one SF block; threads stride over columns\n+ num_threads = self.num_threads\n+\n+ row_idx = bidx\n+ while row_idx < padded_M:\n+ is_padding_row = row_idx >= M\n+\n+ if is_padding_row:\n+ # Fast path: padding row - only zero out scale factors\n+ sf_col_idx = tidx\n+ while sf_col_idx < padded_sf_cols:\n+ sf_offset = self._compute_sf_offset(\n+ row_idx, sf_col_idx, padded_sf_cols\n+ )\n+ mScales[sf_offset] = Uint8(0)\n+ sf_col_idx = sf_col_idx + num_threads\n+ else:\n+ # Normal path: process actual data row with column loop\n+ sf_col_idx = tidx\n+ while sf_col_idx < num_sf_blocks_per_row:\n+ elem_base = sf_col_idx * NVFP4_SF_VEC_SIZE\n+ row_input = mInput[row_idx, None]\n+\n+ # Process block: load, compute scale, convert to E2M1\n+ if cutlass.const_expr(self.is_fp8):\n+ scale_fp8, packed64 = process_nvfp4_block_fp8(\n+ row_input, elem_base, global_scale\n+ )\n+ elif cutlass.const_expr(self.is_bfloat16):\n+ scale_fp8, packed64 = process_nvfp4_block_bfloat(\n+ row_input, elem_base, global_scale\n+ )\n+ else:\n+ scale_fp8, packed64 = process_nvfp4_block_half(\n+ row_input, elem_base, global_scale\n+ )\n+\n+ # Write scale factor using swizzled indexing\n+ sf_offset = self._compute_sf_offset(\n+ row_idx, sf_col_idx, padded_sf_cols\n+ )\n+ mScales[sf_offset] = scale_fp8\n+\n+ # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n+ row_output = mOutput[row_idx, None]\n+ out_base = sf_col_idx * (NVFP4_SF_VEC_SIZE // 2)\n+ out_ptr = get_ptr_as_int64(row_output, out_base)\n+ st_global_u64(out_ptr, packed64)\n+\n+ sf_col_idx = sf_col_idx + num_threads\n+\n+ # Handle padding columns for this row\n+ sf_col_idx = num_sf_blocks_per_row + tidx\n+ while sf_col_idx < padded_sf_cols:\n+ sf_offset = self._compute_sf_offset(\n+ row_idx, sf_col_idx, padded_sf_cols\n+ )\n+ mScales[sf_offset] = Uint8(0)\n+ sf_col_idx = sf_col_idx + num_threads\n+\n+ row_idx = row_idx + grid_dim_x\n+ else:\n+ # Small K path: multi-row processing\n+ # Thread mapping: tidx -> (row_in_block, sf_idx_in_row)\n row_in_block = tidx // threads_per_row\n sf_idx_in_row = tidx % threads_per_row\n \n+ # Grid-stride loop over row batches\n row_batch_idx = bidx\n- total_row_batches = cute.ceil_div(padded_M, rows_per_block)\n-\n- while row_batch_idx < total_row_batches:\n- base_row = row_batch_idx * rows_per_block\n- row_idx = base_row + row_in_block\n-\n+ # Initialize row_idx before while loop (CuTe DSL requires variables\n+ # modified in while loops to be defined before the loop)\n+ row_idx = row_batch_idx * rows_per_block + row_in_block\n+ while row_batch_idx * rows_per_block < padded_M:\n if row_idx < padded_M:\n is_padding_row = row_idx >= M\n \n if is_padding_row:\n+ # Fast path: padding row - zero out ALL padded_sf_cols\n+ # Thread-stride loop since padded_sf_cols may exceed\n+ # threads_per_row (e.g. K=32: threads_per_row=2,\n+ # padded_sf_cols=4)\n local_sf_idx = sf_idx_in_row\n while local_sf_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n@@ -272,10 +469,12 @@\n mScales[sf_offset] = Uint8(0)\n local_sf_idx = local_sf_idx + threads_per_row\n else:\n+ # Normal path: process actual data\n if sf_idx_in_row < num_sf_blocks_per_row:\n elem_base = sf_idx_in_row * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n \n+ # Process block: load, compute scale, convert to E2M1\n if cutlass.const_expr(self.is_fp8):\n scale_fp8, packed64 = process_nvfp4_block_fp8(\n row_input, elem_base, global_scale\n@@ -289,86 +488,36 @@\n row_input, elem_base, global_scale\n )\n \n+ # Write scale factor using swizzled indexing\n sf_offset = self._compute_sf_offset(\n row_idx, sf_idx_in_row, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n \n+ # Store 8 bytes (16 FP4 values = 1 x st.global.u64)\n row_output = mOutput[row_idx, None]\n out_base = sf_idx_in_row * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n \n- padding_sf_start = num_sf_blocks_per_row + sf_idx_in_row\n- while padding_sf_start < padded_sf_cols:\n- sf_offset = self._compute_sf_offset(\n- row_idx, padding_sf_start, padded_sf_cols\n- )\n- mScales[sf_offset] = Uint8(0)\n- padding_sf_start = padding_sf_start + threads_per_row\n+ # Handle padding SF columns for this row\n+ # Thread-stride loop starting from first padding column\n+ if cutlass.const_expr(\n+ self.num_sf_blocks_per_row != self.padded_sf_cols\n+ ):\n+ pad_col = num_sf_blocks_per_row + sf_idx_in_row\n+ while pad_col < padded_sf_cols:\n+ sf_offset = self._compute_sf_offset(\n+ row_idx, pad_col, padded_sf_cols\n+ )\n+ mScales[sf_offset] = Uint8(0)\n+ pad_col = pad_col + threads_per_row\n \n row_batch_idx = row_batch_idx + grid_dim_x\n-\n- else:\n- # ===== LARGE K PATH: Single row with column loop =====\n- row_idx = bidx\n- while row_idx < padded_M:\n- is_padding_row = row_idx >= M\n-\n- sf_idx = Int32(tidx)\n-\n- if is_padding_row:\n- while sf_idx < padded_sf_cols:\n- sf_offset = self._compute_sf_offset(\n- row_idx, sf_idx, padded_sf_cols\n- )\n- mScales[sf_offset] = Uint8(0)\n- sf_idx = sf_idx + num_threads\n- else:\n- num_sf_iters = (\n- num_sf_blocks_per_row + num_threads - 1\n- ) // num_threads\n-\n- for sf_iter in range(num_sf_iters):\n- local_sf_idx = sf_iter * num_threads + tidx\n-\n- if local_sf_idx < num_sf_blocks_per_row:\n- elem_base = local_sf_idx * NVFP4_SF_VEC_SIZE\n- row_input = mInput[row_idx, None]\n-\n- if cutlass.const_expr(self.is_fp8):\n- scale_fp8, packed64 = process_nvfp4_block_fp8(\n- row_input, elem_base, global_scale\n- )\n- elif cutlass.const_expr(self.is_bfloat16):\n- scale_fp8, packed64 = process_nvfp4_block_bfloat(\n- row_input, elem_base, global_scale\n- )\n- else:\n- scale_fp8, packed64 = process_nvfp4_block_half(\n- row_input, elem_base, global_scale\n- )\n-\n- sf_offset = self._compute_sf_offset(\n- row_idx, local_sf_idx, padded_sf_cols\n- )\n- mScales[sf_offset] = scale_fp8\n-\n- row_output = mOutput[row_idx, None]\n- out_base = local_sf_idx * (NVFP4_SF_VEC_SIZE // 2)\n- out_ptr = get_ptr_as_int64(row_output, out_base)\n- st_global_u64(out_ptr, packed64)\n-\n- padding_sf_start = num_sf_blocks_per_row + tidx\n- while padding_sf_start < padded_sf_cols:\n- sf_offset = self._compute_sf_offset(\n- row_idx, padding_sf_start, padded_sf_cols\n- )\n- mScales[sf_offset] = Uint8(0)\n- padding_sf_start = padding_sf_start + num_threads\n-\n- row_idx = row_idx + grid_dim_x\n-\n+ # Update row_idx for next iteration\n+ row_idx = row_batch_idx * rows_per_block + row_in_block\n+\n+ # PDL: Signal that dependent kernels can start early\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n \n@@ -431,13 +580,10 @@\n \n if sf_layout == SF_LAYOUT_LINEAR:\n self.padded_sf_cols = self.num_sf_blocks_per_row\n- self.row_tile_size = 1\n elif sf_layout == SF_LAYOUT_8x4:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n- self.row_tile_size = 8\n else:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n- self.row_tile_size = ROW_TILE_SIZE\n \n self.num_consumer_warps = _TMA_NUM_CONSUMER_WARPS # 8\n self.num_stages = _TMA_NUM_STAGES\n@@ -451,7 +597,6 @@\n # Thread indexing constants (matches CUDA TmaKernelTraitsTwoBytes)\n self.THREADS_PER_ROW = 4 # laneIdx % 4\n self.ROWS_PER_WARP = 8 # 32 / 4\n- self.ROW_ITERATIONS = _TMA_ROW_TILE // self.ROWS_PER_WARP # 2\n self.ELTS_PER_THREAD = NVFP4_SF_VEC_SIZE # 16\n \n @cute.jit\n@@ -693,7 +838,7 @@\n pipeline_init_arrive(cluster_shape_mn=self.cluster_shape_mn, is_relaxed=True)\n pipeline_init_wait(cluster_shape_mn=self.cluster_shape_mn)\n \n- # ---- TMA partition (3D: rows × warps × cols_per_warp) ----\n+ # ---- TMA partition (3D: rows x warps x cols_per_warp) ----\n gSrc_tiled = cute.local_tile(\n gInput_tma,\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n@@ -911,8 +1056,8 @@\n dtype_key: One of \"float16\", \"bfloat16\", \"float8_e4m3fn\".\n \n Returns:\n- Tuple of (compiled_kernel, rows_per_block) where rows_per_block\n- is used by the caller to compute num_blocks at runtime.\n+ For linear layout: (compiled_kernel, sf_blocks_per_tb)\n+ For swizzled layout: (compiled_kernel, rows_per_block)\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n@@ -920,19 +1065,18 @@\n \"float8_e4m3fn\": cutlass.Float8E4M3FN,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n- kernel_obj = NVFP4QuantizeSwizzledKernel(\n- cutlass_dtype, K, sf_layout=sf_layout, enable_pdl=enable_pdl\n- )\n-\n+\n+ # Use symbolic M for dynamic batch sizes\n sym_m = cute.sym_int()\n-\n+ sym_scale_size = cute.sym_int()\n+\n+ # Common fake tensors\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n- sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n@@ -941,20 +1085,42 @@\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n \n- compiled_kernel = cute.compile(\n- kernel_obj,\n- input_fake,\n- output_fake,\n- scales_fake,\n- Int32(1), # Dummy M\n- Int32(128), # Dummy padded_M\n- Int32(1), # Dummy num_blocks\n- global_scale_fake,\n- stream_fake,\n- options=\"--enable-tvm-ffi\",\n- )\n-\n- return compiled_kernel, kernel_obj.rows_per_block\n+ if sf_layout == SF_LAYOUT_LINEAR:\n+ linear_obj = NVFP4QuantizeLinearKernel(cutlass_dtype, K, enable_pdl)\n+\n+ compiled_kernel = cute.compile(\n+ linear_obj,\n+ input_fake,\n+ output_fake,\n+ scales_fake,\n+ Int32(1), # Dummy M\n+ Int32(1), # Dummy total_sf_blocks\n+ Int32(1), # Dummy num_blocks\n+ global_scale_fake,\n+ stream_fake,\n+ options=\"--enable-tvm-ffi\",\n+ )\n+\n+ return compiled_kernel, linear_obj.SF_BLOCKS_PER_TB\n+ else:\n+ swizzled_obj = NVFP4QuantizeSwizzledKernel(\n+ cutlass_dtype, K, sf_layout=sf_layout, enable_pdl=enable_pdl\n+ )\n+\n+ compiled_kernel = cute.compile(\n+ swizzled_obj,\n+ input_fake,\n+ output_fake,\n+ scales_fake,\n+ Int32(1), # Dummy M\n+ Int32(128), # Dummy padded_M\n+ Int32(1), # Dummy num_blocks\n+ global_scale_fake,\n+ stream_fake,\n+ options=\"--enable-tvm-ffi\",\n+ )\n+\n+ return compiled_kernel, swizzled_obj.rows_per_block\n \n \n _TMA_MIN_M = 1024\n@@ -1077,8 +1243,7 @@\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n \n- if enable_pdl is None:\n- enable_pdl = device_support_pdl(input.device)\n+ enable_pdl = device_support_pdl(input.device) if enable_pdl is not False else False\n \n if input.dim() > 2:\n m = input.numel() // input.shape[-1]\n@@ -1171,39 +1336,69 @@\n \n return fp4_output, scale_output\n \n- # Non-TMA path\n+ # Non-TMA path: dual-path dispatch\n+ # Get or compile kernel (device-independent)\n+ kernel_fn, block_unit = _get_compiled_kernel_nvfp4(\n+ dtype_key, k, sf_layout, enable_pdl\n+ )\n+\n+ target_grid = num_sm * _BLOCKS_PER_SM\n+\n if sf_layout == SF_LAYOUT_LINEAR:\n- row_tile_size = 1\n padded_m = m\n padded_sf_cols = num_sf_blocks_per_row\n- elif sf_layout == SF_LAYOUT_8x4:\n- row_tile_size = 8\n+ total_sf_blocks = m * num_sf_blocks_per_row\n+ scale_output_size = total_sf_blocks\n+\n+ sf_blocks_per_tb = block_unit\n+ num_blocks = min(\n+ (total_sf_blocks + sf_blocks_per_tb - 1) // sf_blocks_per_tb,\n+ target_grid,\n+ )\n+\n+ fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n+ scale_output = torch.empty(\n+ scale_output_size, dtype=torch.uint8, device=input.device\n+ )\n+\n+ kernel_fn(\n+ input,\n+ fp4_output,\n+ scale_output,\n+ m,\n+ total_sf_blocks,\n+ num_blocks,\n+ global_scale_tensor,\n+ )\n+ else:\n+ if sf_layout == SF_LAYOUT_8x4:\n+ row_tile_size = 8\n+ else:\n+ row_tile_size = ROW_TILE_SIZE # 128\n padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n- else:\n- row_tile_size = ROW_TILE_SIZE # 128\n- padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n- padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n-\n- scale_output_size = padded_m * padded_sf_cols\n-\n- kernel_fn, rows_per_block = _get_compiled_kernel_nvfp4(\n- dtype_key, k, sf_layout, enable_pdl\n- )\n-\n- default_target_grid = num_sm * _BLOCKS_PER_SM\n- num_blocks = min(\n- (padded_m + rows_per_block - 1) // rows_per_block, default_target_grid\n- )\n-\n- fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n- scale_output = torch.empty(\n- scale_output_size, dtype=torch.uint8, device=input.device\n- )\n-\n- kernel_fn(\n- input, fp4_output, scale_output, m, padded_m, num_blocks, global_scale_tensor\n- )\n+ scale_output_size = padded_m * padded_sf_cols\n+\n+ rows_per_block = block_unit\n+ num_blocks = min(\n+ (padded_m + rows_per_block - 1) // rows_per_block,\n+ target_grid,\n+ )\n+\n+ fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n+ scale_output = torch.empty(\n+ scale_output_size, dtype=torch.uint8, device=input.device\n+ )\n+\n+ kernel_fn(\n+ input,\n+ fp4_output,\n+ scale_output,\n+ m,\n+ padded_m,\n+ num_blocks,\n+ global_scale_tensor,\n+ )\n \n # Reshape using padded_sf_cols: for swizzled layouts the buffer includes\n # column padding; for linear layout padded_sf_cols == num_sf_blocks_per_row.\n@@ -1216,6 +1411,7 @@\n \"SF_LAYOUT_128x4\",\n \"SF_LAYOUT_8x4\",\n \"SF_LAYOUT_LINEAR\",\n+ \"NVFP4QuantizeLinearKernel\",\n \"NVFP4QuantizeSwizzledKernel\",\n \"NVFP4QuantizeTMAKernel\",\n \"nvfp4_quantize_cute_dsl\","},"lines_added":{"kind":"number","value":417,"string":"417"},"lines_removed":{"kind":"number","value":221,"string":"221"},"files_in_commit":{"kind":"number","value":6,"string":"6"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200"],"string":"[\n \"B200\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["5x","1.42x","1.37x","1.41x","1.39x","1.34x","1.32x"],"string":"[\n \"5x\",\n \"1.42x\",\n \"1.37x\",\n \"1.41x\",\n \"1.39x\",\n \"1.34x\",\n \"1.32x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/quantization/kernels/nvfp4_quantize.py).\n\nGoal: perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels\nTarget hardware: B200\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nNVFP4 Quantization using CuTe-DSL\n=================================\n\nNVFP4 quantization kernel using CuTe-DSL.\nSupports multiple scale factor layouts: swizzled 128x4, swizzled 8x4, and linear.\n\nKey differences from MXFP4:\n- sf_vec_size=16 (vs 32 for MXFP4)\n- E4M3 scale factors (vs UE8M0 for MXFP4)\n- User-provided global_scale (vs auto-computed for MXFP4)\n\"\"\"\n\nimport functools\nfrom typing import Callable, Tuple\n\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.cute.nvgpu.cpasync as cpasync\nimport cutlass.pipeline as pipeline\nfrom cutlass.pipeline import pipeline_init_arrive, pipeline_init_wait\nimport torch\nfrom cutlass import Float32, Int32, Uint8\n\nfrom ...api_logging import flashinfer_api\nfrom ...cute_dsl.fp4_common import get_ptr_as_int64, st_global_u64\nfrom ...cute_dsl.utils import get_num_sm\nfrom ..quantization_cute_dsl_utils import (\n NVFP4_SF_VEC_SIZE,\n ROW_TILE_SIZE,\n compute_sf_index_swizzled_128x4_gpu,\n compute_sf_index_swizzled_8x4_gpu,\n compute_sf_index_linear_gpu,\n half2_max_abs_8 as half2_max_abs_8_fn,\n bfloat2_max_abs_8 as bfloat2_max_abs_8_fn,\n hmax_reduce_to_f32,\n bfloat2_hmax_reduce_to_f32,\n half2x8_to_e2m1x16_packed,\n bfloat2x8_to_e2m1x16_packed,\n process_nvfp4_block_half,\n process_nvfp4_block_bfloat,\n process_nvfp4_block_fp8,\n)\n\nSF_LAYOUT_128x4 = 0\nSF_LAYOUT_8x4 = 1\nSF_LAYOUT_LINEAR = 2\n\n_BLOCKS_PER_SM = 4\n_MAX_THREADS_PER_BLOCK = 1024\n_MIN_THREADS = 128\n_MAX_THREADS = 512\n_DEFAULT_THREADS = 256\n\n\ndef _compute_optimal_threads_for_k(K: int) -> int:\n \"\"\"\n Compute optimal thread count for 100% thread utilization.\n\n For NVFP4, each thread processes one SF block (16 elements).\n threads_per_row = K / 16 = num_sf_blocks_per_row\n\n We prefer LARGER thread counts (up to _MAX_THREADS) for better occupancy,\n while maintaining 100% thread utilization.\n \"\"\"\n threads_per_row = K // NVFP4_SF_VEC_SIZE\n\n if threads_per_row >= _MAX_THREADS:\n return _MAX_THREADS\n\n if threads_per_row <= _MAX_THREADS:\n threads = (_MAX_THREADS // threads_per_row) * threads_per_row\n if threads >= _MIN_THREADS:\n return threads\n threads = threads_per_row\n while threads < _MIN_THREADS:\n threads += threads_per_row\n if threads <= _MAX_THREADS:\n return threads\n\n return _DEFAULT_THREADS\n\n\ndef _compute_swizzled_layout_sf_size(\n total_row: int, total_column: int, row_size: int = 128\n) -> int:\n \"\"\"Compute size of swizzled scale factor buffer.\"\"\"\n padded_row = (total_row + row_size - 1) // row_size * row_size\n padded_column = (total_column + 3) // 4 * 4\n return padded_row * padded_column\n\n\n# =============================================================================\n# CuTe-DSL Kernel Class for NVFP4 Swizzled Layout\n# =============================================================================\n\n\nclass NVFP4QuantizeSwizzledKernel:\n \"\"\"\n NVFP4 quantization kernel supporting multiple scale factor layouts.\n\n Supported layouts:\n - 128x4 (swizzled): Optimized for GEMM with large tileN\n - 8x4 (swizzled): Optimized for GEMM with small tileN\n - linear: Simple row-major layout, no swizzling\n\n Key features:\n - E4M3 scale factors (FP8 format) with user-provided global_scale\n - sf_vec_size=16 (each thread processes 16 elements)\n - Multi-row processing when K is small, column loop when K is large\n - Row-based iteration with grid-stride loop\n - Padding row fast path for zeroing scale factors\n\n This kernel is M-agnostic: compiled once per (K, dtype, sf_layout, pdl)\n combination. M-dependent values (M, padded_M) and global_scale are passed\n at runtime.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n\n assert K % NVFP4_SF_VEC_SIZE == 0\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n\n if sf_layout == SF_LAYOUT_LINEAR:\n self.padded_sf_cols = self.num_sf_blocks_per_row\n self.row_tile_size = 1\n elif sf_layout == SF_LAYOUT_8x4:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n self.row_tile_size = 8\n else:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n self.row_tile_size = ROW_TILE_SIZE # 128\n\n self.num_threads = _compute_optimal_threads_for_k(K)\n\n self.threads_per_row = self.num_sf_blocks_per_row\n\n if self.threads_per_row <= self.num_threads:\n self.rows_per_block = self.num_threads // self.threads_per_row\n self.needs_col_loop = False\n else:\n self.rows_per_block = 1\n self.needs_col_loop = True\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n \"\"\"Compute scale factor offset based on layout (compile-time dispatch).\"\"\"\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n if cutlass.const_expr(self.sf_is_8x4):\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_linear_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n mGlobalScale: cute.Tensor,\n stream,\n ):\n threads_per_block = self.num_threads\n\n self.kernel(mInput, mOutput, mScales, M, padded_M, mGlobalScale).launch(\n grid=[num_blocks, 1, 1],\n block=[threads_per_block, 1, 1],\n max_number_threads=[_MAX_THREADS_PER_BLOCK, 1, 1],\n min_blocks_per_mp=_BLOCKS_PER_SM,\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n mGlobalScale: cute.Tensor,\n ):\n \"\"\"\n NVFP4 quantization kernel with swizzled scale factor layout.\n\n Dual-path kernel with compile-time selection:\n - Small K path: Multi-row processing for improved thread utilization\n - Large K path: Single row with column loop\n\n Each thread processes one SF block (16 elements):\n 1. Load 16 elements (2 x 128-bit for fp16/bf16, 1 x 128-bit for fp8)\n 2. Compute max absolute value using SIMD reduction\n 3. Compute E4M3 scale: cvt_f32_to_e4m3(global_scale * max / 6.0)\n 4. Store scale factor using layout-specific indexing\n 5. Back-convert E4M3, compute output_scale = global_scale / scale_back\n 6. Scale elements and convert to E2M1\n 7. Store 8 bytes (16 FP4 values)\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n # Read global_scale from device memory (avoids CPU-GPU sync at launch)\n global_scale = Float32(mGlobalScale[Int32(0)])\n\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n padded_sf_cols = self.padded_sf_cols\n num_threads = self.num_threads\n rows_per_block = self.rows_per_block\n threads_per_row = self.threads_per_row\n\n if cutlass.const_expr(not self.needs_col_loop):\n # ===== SMALL K PATH: Multi-row processing =====\n row_in_block = tidx // threads_per_row\n sf_idx_in_row = tidx % threads_per_row\n\n row_batch_idx = bidx\n total_row_batches = cute.ceil_div(padded_M, rows_per_block)\n\n while row_batch_idx < total_row_batches:\n base_row = row_batch_idx * rows_per_block\n row_idx = base_row + row_in_block\n\n if row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n if is_padding_row:\n local_sf_idx = sf_idx_in_row\n while local_sf_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, local_sf_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n local_sf_idx = local_sf_idx + threads_per_row\n else:\n if sf_idx_in_row < num_sf_blocks_per_row:\n elem_base = sf_idx_in_row * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n if cutlass.const_expr(self.is_fp8):\n scale_fp8, packed64 = process_nvfp4_block_fp8(\n row_input, elem_base, global_scale\n )\n elif cutlass.const_expr(self.is_bfloat16):\n scale_fp8, packed64 = process_nvfp4_block_bfloat(\n row_input, elem_base, global_scale\n )\n else:\n scale_fp8, packed64 = process_nvfp4_block_half(\n row_input, elem_base, global_scale\n )\n\n sf_offset = self._compute_sf_offset(\n row_idx, sf_idx_in_row, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n\n row_output = mOutput[row_idx, None]\n out_base = sf_idx_in_row * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n padding_sf_start = num_sf_blocks_per_row + sf_idx_in_row\n while padding_sf_start < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, padding_sf_start, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n padding_sf_start = padding_sf_start + threads_per_row\n\n row_batch_idx = row_batch_idx + grid_dim_x\n\n else:\n # ===== LARGE K PATH: Single row with column loop =====\n row_idx = bidx\n while row_idx < padded_M:\n is_padding_row = row_idx >= M\n\n sf_idx = Int32(tidx)\n\n if is_padding_row:\n while sf_idx < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, sf_idx, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n sf_idx = sf_idx + num_threads\n else:\n num_sf_iters = (\n num_sf_blocks_per_row + num_threads - 1\n ) // num_threads\n\n for sf_iter in range(num_sf_iters):\n local_sf_idx = sf_iter * num_threads + tidx\n\n if local_sf_idx < num_sf_blocks_per_row:\n elem_base = local_sf_idx * NVFP4_SF_VEC_SIZE\n row_input = mInput[row_idx, None]\n\n if cutlass.const_expr(self.is_fp8):\n scale_fp8, packed64 = process_nvfp4_block_fp8(\n row_input, elem_base, global_scale\n )\n elif cutlass.const_expr(self.is_bfloat16):\n scale_fp8, packed64 = process_nvfp4_block_bfloat(\n row_input, elem_base, global_scale\n )\n else:\n scale_fp8, packed64 = process_nvfp4_block_half(\n row_input, elem_base, global_scale\n )\n\n sf_offset = self._compute_sf_offset(\n row_idx, local_sf_idx, padded_sf_cols\n )\n mScales[sf_offset] = scale_fp8\n\n row_output = mOutput[row_idx, None]\n out_base = local_sf_idx * (NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n padding_sf_start = num_sf_blocks_per_row + tidx\n while padding_sf_start < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n row_idx, padding_sf_start, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n padding_sf_start = padding_sf_start + num_threads\n\n row_idx = row_idx + grid_dim_x\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# CuTe-DSL TMA Kernel Class for NVFP4\n# =============================================================================\n\n_TMA_ROW_TILE = 16\n_TMA_COL_TILE = 64 # Per-warp column tile\n_TMA_NUM_CONSUMER_WARPS = 8\n_TMA_NUM_STAGES = 4\n_TMA_COLS_PER_STAGE = _TMA_NUM_CONSUMER_WARPS * _TMA_COL_TILE # 512\n\n\ndef _round_up(x: int, d: int) -> int:\n return ((x + d - 1) // d) * d\n\n\nclass NVFP4QuantizeTMAKernel:\n \"\"\"\n TMA-based NVFP4 quantization kernel with pipelined producer-consumer\n warp specialization, matching the CUDA TMA kernel architecture.\n\n Architecture (matches csrc/nv_internal/.../quantization.cuh):\n - 1 producer warp (warp 0) issues TMA G2S loads into staged SMEM buffers\n - 8 consumer warps (warps 1-8) read from SMEM, quantize, write to GMEM\n - PipelineTmaAsync manages multi-stage buffering (4 stages)\n - Each TMA tile: [16, 512] = 16 rows x 8 warps x 64 cols per warp\n - Each consumer warp: 4 threads/row x 8 rows/warp, 2 row iterations\n - Each thread: 16 elements (1 SF block) via 2 x ld.shared.v4.u32\n - Grid-stride loop over row tiles, inner loop over K/512 col chunks\n\n Effective when M >= 1024 and K is a multiple of 512.\n \"\"\"\n\n def __init__(\n self,\n dtype: cutlass.Numeric,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n ):\n self.dtype = dtype\n self.K = K\n self.is_bfloat16 = dtype == cutlass.BFloat16\n self.is_fp8 = dtype == cutlass.Float8E4M3FN\n self.enable_pdl = enable_pdl\n self.sf_layout = sf_layout\n self.sf_is_128x4 = sf_layout == SF_LAYOUT_128x4\n self.sf_is_8x4 = sf_layout == SF_LAYOUT_8x4\n\n assert not self.is_fp8, \"FP8 input not yet supported for TMA kernel\"\n assert K % _TMA_COLS_PER_STAGE == 0, (\n f\"K ({K}) must be a multiple of {_TMA_COLS_PER_STAGE} for TMA kernel\"\n )\n\n self.num_sf_blocks_per_row = K // NVFP4_SF_VEC_SIZE\n self.num_col_chunks = K // _TMA_COLS_PER_STAGE\n\n if sf_layout == SF_LAYOUT_LINEAR:\n self.padded_sf_cols = self.num_sf_blocks_per_row\n self.row_tile_size = 1\n elif sf_layout == SF_LAYOUT_8x4:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n self.row_tile_size = 8\n else:\n self.padded_sf_cols = ((self.num_sf_blocks_per_row + 3) // 4) * 4\n self.row_tile_size = ROW_TILE_SIZE\n\n self.num_consumer_warps = _TMA_NUM_CONSUMER_WARPS # 8\n self.num_stages = _TMA_NUM_STAGES\n self.producer_warp_id = 0 # Warp 0 is producer (matches CUDA kernel)\n self.threads_per_cta = 32 * (self.num_consumer_warps + 1) # 288\n self.rows_per_block = _TMA_ROW_TILE\n self.buffer_align_bytes = 1024\n self.cluster_shape_mn = (1, 1)\n self.elems_per_stage = _TMA_ROW_TILE * _TMA_COLS_PER_STAGE # 8192\n\n # Thread indexing constants (matches CUDA TmaKernelTraitsTwoBytes)\n self.THREADS_PER_ROW = 4 # laneIdx % 4\n self.ROWS_PER_WARP = 8 # 32 / 4\n self.ROW_ITERATIONS = _TMA_ROW_TILE // self.ROWS_PER_WARP # 2\n self.ELTS_PER_THREAD = NVFP4_SF_VEC_SIZE # 16\n\n @cute.jit\n def _compute_sf_offset(\n self, row_idx: Int32, col_idx: Int32, padded_cols: Int32\n ) -> Int32:\n if cutlass.const_expr(self.sf_is_128x4):\n return compute_sf_index_swizzled_128x4_gpu(row_idx, col_idx, padded_cols)\n else:\n if cutlass.const_expr(self.sf_is_8x4):\n return compute_sf_index_swizzled_8x4_gpu(row_idx, col_idx, padded_cols)\n else:\n return compute_sf_index_linear_gpu(row_idx, col_idx, padded_cols)\n\n @cute.jit\n def _quantize_sf_block(\n self,\n h0: cutlass.Uint32,\n h1: cutlass.Uint32,\n h2: cutlass.Uint32,\n h3: cutlass.Uint32,\n h4: cutlass.Uint32,\n h5: cutlass.Uint32,\n h6: cutlass.Uint32,\n h7: cutlass.Uint32,\n global_row: Int32,\n sf_col: Int32,\n global_scale: Float32,\n M: Int32,\n padded_M: Int32,\n padded_sf_cols: Int32,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n ):\n \"\"\"Quantize one 16-element SF block and write results to GMEM.\"\"\"\n from ...cute_dsl.fp4_common import (\n cvt_f32_to_e4m3,\n nvfp4_compute_output_scale,\n rcp_approx_ftz,\n )\n\n if global_row < padded_M:\n is_padding_row = global_row >= M\n\n if is_padding_row:\n sf_offset = self._compute_sf_offset(global_row, sf_col, padded_sf_cols)\n mScales[sf_offset] = Uint8(0)\n else:\n if cutlass.const_expr(self.is_bfloat16):\n block_max_h2 = bfloat2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n else:\n block_max_h2 = half2_max_abs_8_fn(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & cutlass.Uint32(0xFF))\n\n output_scale = nvfp4_compute_output_scale(scale_fp8_u32, global_scale)\n\n if cutlass.const_expr(self.is_bfloat16):\n packed64 = bfloat2x8_to_e2m1x16_packed(\n h0, h1, h2, h3, h4, h5, h6, h7, output_scale\n )\n else:\n packed64 = half2x8_to_e2m1x16_packed(\n h0, h1, h2, h3, h4, h5, h6, h7, output_scale\n )\n\n sf_offset = self._compute_sf_offset(global_row, sf_col, padded_sf_cols)\n mScales[sf_offset] = scale_fp8\n\n row_output = mOutput[global_row, None]\n out_base = sf_col * Int32(NVFP4_SF_VEC_SIZE // 2)\n out_ptr = get_ptr_as_int64(row_output, out_base)\n st_global_u64(out_ptr, packed64)\n\n @cute.jit\n def __call__(\n self,\n mInput: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n num_blocks: Int32,\n mGlobalScale: cute.Tensor,\n stream,\n ):\n # 3D global tensor: [padded_M, K/64, 64] so each warp's 64-col\n # stripe is the contiguous innermost dimension, matching the CUDA\n # TMA kernel's 3D tensor map.\n gInput = cute.make_tensor(\n mInput.iterator,\n cute.make_layout(\n (padded_M, self.K // _TMA_COL_TILE, _TMA_COL_TILE),\n stride=(self.K, _TMA_COL_TILE, 1),\n ),\n )\n\n # SMEM layout per stage: [rows=16, warps=8, cols_per_warp=64]\n # with SWIZZLE_128B applied. Within each warp's [16, 64] tile the\n # row stride is 64 elems = 128 bytes, putting row bits in the S=3\n # range of the swizzle so different rows map to different banks.\n smem_swizzle = cute.make_swizzle(3, 4, 3) # SWIZZLE_128B for 2B types\n smem_outer_single = cute.make_layout(\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n stride=(_TMA_COL_TILE, _TMA_ROW_TILE * _TMA_COL_TILE, 1),\n )\n smem_single_composed = cute.make_composed_layout(\n smem_swizzle, 0, smem_outer_single\n )\n\n cta_tiler = (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE)\n tma_atom, tma_tensor = cpasync.make_tiled_tma_atom(\n cpasync.CopyBulkTensorTileG2SOp(),\n gInput,\n smem_single_composed,\n cta_tiler,\n )\n\n total_smem_elems = self.elems_per_stage * self.num_stages\n # Staged outer layout (no swizzle — swizzle passed separately)\n smem_outer_staged = cute.make_layout(\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE, self.num_stages),\n stride=(\n _TMA_COL_TILE,\n _TMA_ROW_TILE * _TMA_COL_TILE,\n 1,\n self.elems_per_stage,\n ),\n )\n # Flat layout for manual-swizzle consumer reads\n smem_layout_flat = cute.make_layout((total_smem_elems,))\n\n self.num_tma_load_bytes = cute.size_in_bytes(self.dtype, smem_outer_single)\n\n @cute.struct\n class SharedStorage:\n load_full_mbar: cute.struct.MemRange[cutlass.Int64, self.num_stages]\n load_empty_mbar: cute.struct.MemRange[cutlass.Int64, self.num_stages]\n smem_data: cute.struct.Align[\n cute.struct.MemRange[self.dtype, total_smem_elems],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n self.kernel(\n tma_atom,\n tma_tensor,\n mOutput,\n mScales,\n M,\n padded_M,\n mGlobalScale,\n smem_outer_staged,\n smem_swizzle,\n smem_layout_flat,\n ).launch(\n grid=[num_blocks, 1, 1],\n block=[self.threads_per_cta, 1, 1],\n max_number_threads=[\n self.threads_per_cta,\n 1,\n 1,\n ], # __launch_bounds__(288, 2)\n min_blocks_per_mp=2,\n cluster=(*self.cluster_shape_mn, 1),\n stream=stream,\n use_pdl=self.enable_pdl,\n )\n\n @cute.kernel\n def kernel(\n self,\n tma_atom: cute.CopyAtom,\n gInput_tma: cute.Tensor,\n mOutput: cute.Tensor,\n mScales: cute.Tensor,\n M: Int32,\n padded_M: Int32,\n mGlobalScale: cute.Tensor,\n smem_outer_staged: cute.Layout,\n smem_swizzle: cute.Swizzle,\n smem_layout_flat: cute.Layout,\n ):\n from ...cute_dsl.fp4_common import (\n get_smem_ptr_as_int32,\n ld_shared_v4_u32,\n )\n\n tidx, _, _ = cute.arch.thread_idx()\n bidx, _, _ = cute.arch.block_idx()\n grid_dim_x, _, _ = cute.arch.grid_dim()\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_wait()\n\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n lane_idx = tidx % 32\n\n global_scale = Float32(mGlobalScale[Int32(0)])\n padded_sf_cols = self.padded_sf_cols\n num_sf_blocks_per_row = self.num_sf_blocks_per_row\n num_col_chunks = self.num_col_chunks\n elems_per_stage = self.elems_per_stage\n\n # ---- SMEM allocation ----\n smem = cutlass.utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n load_mbar_ptr = storage.load_full_mbar.data_ptr()\n # Swizzled tensor for TMA partition (address-space-correct writes)\n sData_staged = storage.smem_data.get_tensor(\n smem_outer_staged, swizzle=smem_swizzle\n )\n # Flat tensor for manual-swizzle consumer reads\n sData_flat = storage.smem_data.get_tensor(smem_layout_flat)\n\n # ---- Pipeline setup ----\n load_pipeline = pipeline.PipelineTmaAsync.create(\n barrier_storage=load_mbar_ptr,\n num_stages=self.num_stages,\n producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread, 1),\n consumer_group=pipeline.CooperativeGroup(\n pipeline.Agent.Thread, self.num_consumer_warps\n ),\n tx_count=self.num_tma_load_bytes,\n cta_layout_vmnk=cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)), (1,)\n ),\n defer_sync=True,\n )\n\n pipeline_init_arrive(cluster_shape_mn=self.cluster_shape_mn, is_relaxed=True)\n pipeline_init_wait(cluster_shape_mn=self.cluster_shape_mn)\n\n # ---- TMA partition (3D: rows × warps × cols_per_warp) ----\n gSrc_tiled = cute.local_tile(\n gInput_tma,\n (_TMA_ROW_TILE, _TMA_NUM_CONSUMER_WARPS, _TMA_COL_TILE),\n (None, None, None),\n )\n tAsA, tAgA = cpasync.tma_partition(\n tma_atom,\n 0,\n cute.make_layout(1),\n cute.group_modes(sData_staged, 0, 3), # Group 3 tile modes\n cute.group_modes(gSrc_tiled, 0, 3),\n )\n\n num_row_tiles = cute.ceil_div(padded_M, _TMA_ROW_TILE)\n\n # ---- Consumer thread indexing (matches CUDA TmaKernelTraitsTwoBytes) ----\n # 4 threads per row, 8 rows per warp, 2 row iterations per stage\n col_idx_local = lane_idx % Int32(self.THREADS_PER_ROW)\n row_idx_local = lane_idx // Int32(self.THREADS_PER_ROW)\n\n # ======== Producer warp (warp 0) ========\n if warp_idx == self.producer_warp_id:\n producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_stages\n )\n\n row_tile_idx = bidx\n while row_tile_idx < num_row_tiles:\n col_chunk = Int32(0)\n while col_chunk < num_col_chunks:\n load_pipeline.producer_acquire(producer_state)\n\n cute.copy(\n tma_atom,\n tAgA[(None, row_tile_idx, col_chunk, 0)],\n tAsA[(None, producer_state.index)],\n tma_bar_ptr=load_pipeline.producer_get_barrier(producer_state),\n )\n\n producer_state.advance()\n col_chunk = col_chunk + Int32(1)\n\n row_tile_idx = row_tile_idx + grid_dim_x\n\n load_pipeline.producer_tail(producer_state)\n\n # ======== Consumer warps (warps 1-8) ========\n if warp_idx > 0:\n consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_stages\n )\n\n # 0-indexed consumer warp id\n consumer_warp_idx = warp_idx - Int32(1)\n\n # Pre-compute warp tile base offset (constant per warp)\n # SMEM 3D layout: [rows=16, warps=8, cols=64] per stage\n # stride: [64, 1024, 1] → warp tile base = warp * 1024\n warp_tile_elems = _TMA_ROW_TILE * _TMA_COL_TILE # 1024\n warp_tile_base = consumer_warp_idx * Int32(warp_tile_elems)\n\n # Float4 base position for this thread (0, 2, 4, 6)\n f4_base = col_idx_local * Int32(2)\n\n # Global column offset for SF index: warp's column within K\n base_col_in_stage = consumer_warp_idx * Int32(\n _TMA_COL_TILE\n ) + col_idx_local * Int32(self.ELTS_PER_THREAD)\n\n row_tile_idx = bidx\n while row_tile_idx < num_row_tiles:\n base_row = row_tile_idx * Int32(_TMA_ROW_TILE)\n\n col_chunk = Int32(0)\n while col_chunk < num_col_chunks:\n load_pipeline.consumer_wait(consumer_state)\n stage = consumer_state.index\n\n # ---- Read ALL SMEM data with SWIZZLE_128B addressing ----\n # Within each warp's [16,64] tile, the XOR pattern matches\n # CUDA's load_input_vec: float4_idx ^= row & 7\n # Physical elem offset in warp tile for (row, float4 f):\n # row * 64 + (f ^ (row & 7)) * 8\n stage_base = stage * Int32(elems_per_stage)\n\n # Row iteration 0 (row_idx_local = 0..7)\n r0_xor = row_idx_local & Int32(7)\n r0_f4_0 = f4_base ^ r0_xor\n r0_f4_1 = (f4_base + Int32(1)) ^ r0_xor\n r0_row_base = (\n stage_base\n + warp_tile_base\n + row_idx_local * Int32(_TMA_COL_TILE)\n )\n r0_addr_0 = get_smem_ptr_as_int32(\n sData_flat, r0_row_base + r0_f4_0 * Int32(8)\n )\n r0_addr_1 = get_smem_ptr_as_int32(\n sData_flat, r0_row_base + r0_f4_1 * Int32(8)\n )\n r0_h0, r0_h1, r0_h2, r0_h3 = ld_shared_v4_u32(r0_addr_0)\n r0_h4, r0_h5, r0_h6, r0_h7 = ld_shared_v4_u32(r0_addr_1)\n\n # Row iteration 1 (row = row_idx_local + 8)\n r1_row = row_idx_local + Int32(self.ROWS_PER_WARP)\n r1_xor = r1_row & Int32(7)\n r1_f4_0 = f4_base ^ r1_xor\n r1_f4_1 = (f4_base + Int32(1)) ^ r1_xor\n r1_row_base = (\n stage_base + warp_tile_base + r1_row * Int32(_TMA_COL_TILE)\n )\n r1_addr_0 = get_smem_ptr_as_int32(\n sData_flat, r1_row_base + r1_f4_0 * Int32(8)\n )\n r1_addr_1 = get_smem_ptr_as_int32(\n sData_flat, r1_row_base + r1_f4_1 * Int32(8)\n )\n r1_h0, r1_h1, r1_h2, r1_h3 = ld_shared_v4_u32(r1_addr_0)\n r1_h4, r1_h5, r1_h6, r1_h7 = ld_shared_v4_u32(r1_addr_1)\n\n # ---- Quantize and write: both row iterations ----\n # Global column base for SF index computation\n global_col_base = col_chunk * Int32(_TMA_COLS_PER_STAGE)\n sf_col = (global_col_base + base_col_in_stage) // Int32(\n NVFP4_SF_VEC_SIZE\n )\n\n # Row iteration 0\n global_row_0 = base_row + row_idx_local\n self._quantize_sf_block(\n r0_h0,\n r0_h1,\n r0_h2,\n r0_h3,\n r0_h4,\n r0_h5,\n r0_h6,\n r0_h7,\n global_row_0,\n sf_col,\n global_scale,\n M,\n padded_M,\n padded_sf_cols,\n mOutput,\n mScales,\n )\n\n # Row iteration 1\n global_row_1 = base_row + row_idx_local + Int32(self.ROWS_PER_WARP)\n self._quantize_sf_block(\n r1_h0,\n r1_h1,\n r1_h2,\n r1_h3,\n r1_h4,\n r1_h5,\n r1_h6,\n r1_h7,\n global_row_1,\n sf_col,\n global_scale,\n M,\n padded_M,\n padded_sf_cols,\n mOutput,\n mScales,\n )\n\n # ---- Release pipeline after all work (matches CUDA pattern) ----\n load_pipeline.consumer_release(consumer_state)\n consumer_state.advance()\n\n col_chunk = col_chunk + Int32(1)\n\n # Zero padding SF columns for swizzled layouts\n if cutlass.const_expr(self.sf_layout != SF_LAYOUT_LINEAR):\n consumer_tid = (warp_idx - Int32(1)) * Int32(32) + lane_idx\n if consumer_tid < _TMA_ROW_TILE:\n pad_row_idx = base_row + consumer_tid\n if pad_row_idx < padded_M:\n padding_sf = Int32(num_sf_blocks_per_row)\n while padding_sf < padded_sf_cols:\n sf_offset = self._compute_sf_offset(\n pad_row_idx, padding_sf, padded_sf_cols\n )\n mScales[sf_offset] = Uint8(0)\n padding_sf = padding_sf + Int32(1)\n\n row_tile_idx = row_tile_idx + grid_dim_x\n\n if cutlass.const_expr(self.enable_pdl):\n cute.arch.griddepcontrol_launch_dependents()\n\n\n# =============================================================================\n# PyTorch Integration with TVM-FFI\n# =============================================================================\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile NVFP4 kernel with TVM-FFI.\n\n Cached by (K, dtype_key, sf_layout, pdl) - M-agnostic, device-independent\n compilation.\n\n Args:\n dtype_key: One of \"float16\", \"bfloat16\", \"float8_e4m3fn\".\n\n Returns:\n Tuple of (compiled_kernel, rows_per_block) where rows_per_block\n is used by the caller to compute num_blocks at runtime.\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n \"float8_e4m3fn\": cutlass.Float8E4M3FN,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n kernel_obj = NVFP4QuantizeSwizzledKernel(\n cutlass_dtype, K, sf_layout=sf_layout, enable_pdl=enable_pdl\n )\n\n sym_m = cute.sym_int()\n\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(128), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, kernel_obj.rows_per_block\n\n\n_TMA_MIN_M = 1024\n# TMA wins when the total problem is large enough to amortize pipeline overhead.\n# Empirically, floor(log2(M)) + floor(log2(K)) >= 25 is the crossover where TMA\n# outperforms the default vectorized-load kernel, validated on B200 and SM120.\n# We use bit_length()-1 (i.e., floor(log2)) rather than m*k to keep the boundary\n# aligned with the power-of-2 grid it was tuned on.\n_TMA_LOG2_MK_THRESHOLD = 25\n\n\ndef _should_use_tma(m: int, k: int, dtype: torch.dtype) -> bool:\n \"\"\"Determine if TMA kernel should be used based on problem dimensions.\"\"\"\n if dtype == torch.float8_e4m3fn:\n return False\n if k % _TMA_COLS_PER_STAGE != 0:\n return False\n if m < _TMA_MIN_M:\n return False\n # Use log2(M) + log2(K) threshold for the crossover point\n return m.bit_length() - 1 + k.bit_length() - 1 >= _TMA_LOG2_MK_THRESHOLD\n\n\n@functools.cache\ndef _get_compiled_kernel_nvfp4_tma(\n dtype_key: str,\n K: int,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool = False,\n) -> Tuple[Callable, int]:\n \"\"\"\n Get or compile TMA-based NVFP4 kernel with TVM-FFI.\n\n Cached by (K, dtype_key, sf_layout, pdl).\n \"\"\"\n _dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n }\n cutlass_dtype = _dtype_map[dtype_key]\n kernel_obj = NVFP4QuantizeTMAKernel(\n cutlass_dtype, K, sf_layout=sf_layout, enable_pdl=enable_pdl\n )\n\n sym_m = cute.sym_int()\n sym_padded_m = cute.sym_int()\n\n input_fake = cute.runtime.make_fake_compact_tensor(\n cutlass_dtype, (sym_padded_m, K), stride_order=(1, 0), assumed_align=16\n )\n output_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_m, K // 2), stride_order=(1, 0), assumed_align=16\n )\n sym_scale_size = cute.sym_int()\n scales_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Uint8, (sym_scale_size,), assumed_align=16\n )\n global_scale_fake = cute.runtime.make_fake_compact_tensor(\n cutlass.Float32, (1,), assumed_align=4\n )\n stream_fake = cute.runtime.make_fake_stream(use_tvm_ffi_env_stream=True)\n\n compiled_kernel = cute.compile(\n kernel_obj,\n input_fake,\n output_fake,\n scales_fake,\n Int32(1), # Dummy M\n Int32(1024), # Dummy padded_M\n Int32(1), # Dummy num_blocks\n global_scale_fake,\n stream_fake,\n options=\"--enable-tvm-ffi\",\n )\n\n return compiled_kernel, kernel_obj.rows_per_block\n\n\n@flashinfer_api\ndef nvfp4_quantize_cute_dsl(\n input: torch.Tensor,\n global_scale: torch.Tensor,\n sf_layout: int = SF_LAYOUT_128x4,\n enable_pdl: bool | None = None,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n \"\"\"\n Quantize input tensor to NVFP4 format using CuTe-DSL kernel.\n\n This is a GPU implementation matching FlashInfer's nvfp4_quantize() behavior:\n - E4M3 scale factors (FP8)\n - E2M1 output format (4-bit, 2 values per byte)\n - Supports 128x4, 8x4, and linear scale factor layouts\n - sf_vec_size=16\n\n The kernel is compiled once per (K, dtype, sf_layout, pdl) combination and\n handles varying M (batch size) at runtime without recompilation.\n\n Args:\n input: Input tensor of shape [M, K] with dtype fp16/bf16/float8_e4m3fn\n global_scale: Scalar tensor (float32) for NVFP4 global scale factor\n sf_layout: Scale factor layout (0=128x4, 1=8x4, 2=linear).\n enable_pdl: Whether to enable PDL (Programmatic Dependent Launch).\n If None, automatically detects based on device capability (SM >= 9.0).\n\n Returns:\n Tuple of:\n - fp4_tensor: Quantized tensor of shape [M, K/2] with dtype uint8\n - scale_tensor: E4M3 scale factors as uint8 tensor\n reshaped to [padded_rows, K/16]\n \"\"\"\n from ...utils import device_support_pdl\n\n _valid_sf_layouts = (SF_LAYOUT_128x4, SF_LAYOUT_8x4, SF_LAYOUT_LINEAR)\n assert sf_layout in _valid_sf_layouts, (\n f\"sf_layout must be one of {_valid_sf_layouts}, got {sf_layout}\"\n )\n _supported_dtypes = (torch.float16, torch.bfloat16, torch.float8_e4m3fn)\n assert input.dtype in _supported_dtypes, (\n f\"Input dtype must be one of {_supported_dtypes}, got {input.dtype}\"\n )\n assert input.is_cuda, \"Input must be on CUDA device\"\n\n if enable_pdl is None:\n enable_pdl = device_support_pdl(input.device)\n\n if input.dim() > 2:\n m = input.numel() // input.shape[-1]\n k = input.shape[-1]\n input = input.reshape(m, k)\n else:\n m, k = input.shape\n\n assert k % NVFP4_SF_VEC_SIZE == 0, (\n f\"K ({k}) must be divisible by NVFP4_SF_VEC_SIZE={NVFP4_SF_VEC_SIZE}\"\n )\n\n input = input.contiguous()\n\n _torch_to_dtype_key = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n torch.float8_e4m3fn: \"float8_e4m3fn\",\n }\n dtype_key = _torch_to_dtype_key[input.dtype]\n\n if isinstance(global_scale, torch.Tensor):\n global_scale_tensor = (\n global_scale.float().reshape(1).contiguous().to(input.device)\n )\n else:\n global_scale_tensor = torch.tensor(\n [float(global_scale)], dtype=torch.float32, device=input.device\n )\n\n num_sm = get_num_sm(input.device)\n\n num_sf_blocks_per_row = k // NVFP4_SF_VEC_SIZE\n\n use_tma = _should_use_tma(m, k, input.dtype)\n\n if use_tma:\n tma_row_tile = _TMA_ROW_TILE\n if sf_layout == SF_LAYOUT_LINEAR:\n padded_m = _round_up(m, tma_row_tile)\n padded_sf_cols = num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n padded_m = _round_up(m, max(tma_row_tile, 8))\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n else:\n padded_m = _round_up(m, max(tma_row_tile, ROW_TILE_SIZE))\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n\n scale_output_size = padded_m * padded_sf_cols\n\n kernel_fn, rows_per_block = _get_compiled_kernel_nvfp4_tma(\n dtype_key, k, sf_layout, enable_pdl\n )\n\n # Match CUDA TMA kernel: grid = min(row_tiles, SM_count * 2)\n tma_target_grid = num_sm * 2\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block, tma_target_grid\n )\n\n input_padded = input\n if padded_m > m:\n input_padded = torch.zeros(\n padded_m, k, dtype=input.dtype, device=input.device\n )\n input_padded[:m, :] = input\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input_padded,\n fp4_output,\n scale_output,\n m,\n padded_m,\n num_blocks,\n global_scale_tensor,\n )\n\n if sf_layout == SF_LAYOUT_LINEAR:\n scale_output = scale_output[: m * num_sf_blocks_per_row]\n\n # Reshape using padded_sf_cols for swizzled layouts (the buffer is\n # physically padded and stores data in swizzled order). For linear\n # layout the padding is already trimmed above.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n # Non-TMA path\n if sf_layout == SF_LAYOUT_LINEAR:\n row_tile_size = 1\n padded_m = m\n padded_sf_cols = num_sf_blocks_per_row\n elif sf_layout == SF_LAYOUT_8x4:\n row_tile_size = 8\n padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n else:\n row_tile_size = ROW_TILE_SIZE # 128\n padded_m = ((m + row_tile_size - 1) // row_tile_size) * row_tile_size\n padded_sf_cols = ((num_sf_blocks_per_row + 3) // 4) * 4\n\n scale_output_size = padded_m * padded_sf_cols\n\n kernel_fn, rows_per_block = _get_compiled_kernel_nvfp4(\n dtype_key, k, sf_layout, enable_pdl\n )\n\n default_target_grid = num_sm * _BLOCKS_PER_SM\n num_blocks = min(\n (padded_m + rows_per_block - 1) // rows_per_block, default_target_grid\n )\n\n fp4_output = torch.empty(m, k // 2, dtype=torch.uint8, device=input.device)\n scale_output = torch.empty(\n scale_output_size, dtype=torch.uint8, device=input.device\n )\n\n kernel_fn(\n input, fp4_output, scale_output, m, padded_m, num_blocks, global_scale_tensor\n )\n\n # Reshape using padded_sf_cols: for swizzled layouts the buffer includes\n # column padding; for linear layout padded_sf_cols == num_sf_blocks_per_row.\n scale_output = scale_output.reshape(-1, padded_sf_cols)\n\n return fp4_output, scale_output\n\n\n__all__ = [\n \"SF_LAYOUT_128x4\",\n \"SF_LAYOUT_8x4\",\n \"SF_LAYOUT_LINEAR\",\n \"NVFP4QuantizeSwizzledKernel\",\n \"NVFP4QuantizeTMAKernel\",\n \"nvfp4_quantize_cute_dsl\",\n \"_get_compiled_kernel_nvfp4\",\n \"_get_compiled_kernel_nvfp4_tma\",\n]\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n**Summary**\n- Adopt dual-path kernel architecture (linear flat + swizzled row-based) for MXFP4 and NVFP4 CuTe-DSL quantization kernels.\n- Architecture chanes to MXFP8 quantization for better perf.\n- Expand benchmark scripts and test coverage across all three quantization kernels. Compares exact output match between CUDA & CuTe-DSL backends\n- **All mxfp4, mxfp8, and nvfp4 quantization have exact bitwise match in for CUDA vs. CuTe DSL backends in both the output and scaling factors.**\n\n**Kernel changes**\n`mxfp8_quantize.py`\n- Adaptive 2T/SF dispatch: 2 threads per SF block for large problems (total_sf >= 65536), 4 threads for small problems for better memory bandwidth utilization.\n- Integer UE8M0 conversion (float_to_ue8m0_fast, ue8m0_to_inv_scale_fast): replaces SFU-based lg2.approx/ex2.approx with integer bit manipulation, freeing the SFU pipeline\n- reduce_max_2threads: 1-shuffle XOR reduction for the 2T path\n- Remove unused self.dtype and self.K attributes \n \n`mxfp4_quantize.py`\n- Add swizzled kernel. Previously only supported linear layout. \n- Swizzled kernel: small-K multi-row path and large-K column-loop path, compile-time selected via const_expr(needs_col_loop)\n- Inline padding for swizzled layout (row and column) — eliminates the expensive separate flat-iteration padding passes that caused 5x+ regression at small M \n- Dynamic thread count via _compute_optimal_threads(K) for 100% thread utilization \n \n`nvfp4_quantize.py`\n- Same dual-path split: NVFP4QuantizeLinearKernel + NVFP4QuantizeSwizzledKernel \n- Supports all three SF layouts (128x4, 8x4, linear) with compile-time dispatch \n- Remove unused self.row_tile_size and self.ROW_ITERATIONS from TMA kernel \n \n `quantization_cute_dsl_utils.py`\n- ue8m0_to_inv_scale_fast: integer bit construction replacing ex2.approx \n- reduce_max_2threads: 1-shuffle reduction for 2T/SF MXFP8 path \n- 2T/SF constants: ELTS_PER_THREAD, THREADS_PER_SF, SF_BLOCKS_PER_WARP + legacy 4T variants \n- MXFP8_2T_SF_THRESHOLD = 65536 \n\n**Test changes**\n- `test_fp4_quantize.py` and `test_fp8_quantize.py`: Add more problem sizes. \n- `test_fp4_quantize_padding.py`: Add both-backend parametrization and CUDA-vs-CuTe-DSL parity test for linear layout padding.\n\n**Perf comparison between backends on B200**\n\n<details>\n <summary>Click to see mxfp8 performance comparison</summary>\n\nLinear (gmean 1.42x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp8_backend_comparison_linear_bfloat16\" src=\"https://github.com/user-attachments/assets/21b630ff-d1a7-427b-9e59-5b6417c498c6\" />\n\nSwizzled (gmean 1.37x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp8_backend_comparison_swizzled_bfloat16\" src=\"https://github.com/user-attachments/assets/f9d19958-df34-4fc9-8351-6b9348aba8c6\" />\n\n\n</details>\n\n<details>\n <summary>Click to see mxfp4 performance comparison</summary>\n\nLinear (gmean 1.41x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp4_quantize_backend_comparison_linear_bfloat16\" src=\"https://github.com/user-attachments/assets/e050a38d-600e-43c1-92eb-f0b51e22accf\" />\n\n\nSwizzled (gmean 1.39x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp4_quantize_backend_comparison_swizzled_bfloat16\" src=\"https://github.com/user-attachments/assets/d4e4cd72-baad-4057-9523-63cd6665bf6e\" />\n\n</details>\n\n<details>\n <summary>Click to see nvfp4 performance comparison</summary>\n\nLinear (gmean 1.34x)\n\n<img width=\"1644\" height=\"1477\" alt=\"nvfp4_quantize_backend_comparison_linear_bfloat16\" src=\"https://github.com/user-attachments/assets/532ef7f2-0a41-406c-8eda-0f16436672c1\" />\n\n\nSwizzled (gmean 1.32x)\n\n<img width=\"1644\" height=\"1477\" alt=\"nvfp4_quantize_backend_comparison_swizzled_bfloat16\" src=\"https://github.com/user-attachments/assets/9694e1d3-e92e-45c9-81b5-527dca4e6cd1\" />\n\n\n</details>\n\n<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Benchmarks now run and report both linear and swizzled scale-factor layouts separately, generating distinct heatmaps/tables and layout-aware labels.\n * Added a new NVFP4 quantization benchmark with bandwidth and comparison modes.\n\n* **Refactor**\n * Quantize kernels split into layout-specific implementations and introduced dual-mode threading optimizations for better performance across sizes.\n\n* **Tests**\n * Expanded parameter sweeps, added backend parameterization, and capability-aware skips.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Linear\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.42, \"speedup\": 1.42}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Swizzled\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.37, \"speedup\": 1.37}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Linear\", \"batch_matrix\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.41, \"speedup\": 1.41}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Swizzled\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.39, \"speedup\": 1.39}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Linear\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.34, \"speedup\": 1.34}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Swizzled\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.32, \"speedup\": 1.32}]"},"kernel_speedup":{"kind":"number","value":1.38,"string":"1.38"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1173,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"d476c61c3f8bcbbca30755b330a0c10b141dede3"},"date":{"kind":"string","value":"2026-04-01T12:08:51-07:00"},"pr_number":{"kind":"number","value":2904,"string":"2,904"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2904"},"title":{"kind":"string","value":"perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904)"},"message":{"kind":"string","value":"perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n**Summary**\n- Adopt dual-path kernel architecture (linear flat + swizzled row-based)\nfor MXFP4 and NVFP4 CuTe-DSL quantization kernels.\n- Architecture chanes to MXFP8 quantization for better perf.\n- Expand benchmark scripts and test coverage across all three\nquantization kernels. Compares exact output match between CUDA &\nCuTe-DSL backends\n- **All mxfp4, mxfp8, and nvfp4 quantization have exact bitwise match in\nfor CUDA vs. CuTe DSL backends in both the output and scaling factors.**\n\n**Kernel changes**\n`mxfp8_quantize.py`\n- Adaptive 2T/SF dispatch: 2 threads per SF block for large problems\n(total_sf >= 65536), 4 threads for small problems for better memory\nbandwidth utilization.\n- Integer UE8M0 conversion (float_to_ue8m0_fast,\nue8m0_to_inv_scale_fast): replaces SFU-based lg2.approx/ex2.approx with\ninteger bit manipulation, freeing the SFU pipeline\n- reduce_max_2threads: 1-shuffle XOR reduction for the 2T path\n- Remove unused self.dtype and self.K attributes \n`mxfp4_quantize.py`\n- Add swizzled kernel. Previously only supported linear layout.\n- Swizzled kernel: small-K multi-row path and large-K column-loop path,\ncompile-time selected via const_expr(needs_col_loop)\n- Inline padding for swizzled layout (row and column) — eliminates the\nexpensive separate flat-iteration padding passes that caused 5x+\nregression at small M\n- Dynamic thread count via _compute_optimal_threads(K) for 100% thread\nutilization\n`nvfp4_quantize.py`\n- Same dual-path split: NVFP4QuantizeLinearKernel +\nNVFP4QuantizeSwizzledKernel\n- Supports all three SF layouts (128x4, 8x4, linear) with compile-time\ndispatch\n- Remove unused self.row_tile_size and self.ROW_ITERATIONS from TMA\nkernel\n `quantization_cute_dsl_utils.py`\n- ue8m0_to_inv_scale_fast: integer bit construction replacing ex2.approx\n- reduce_max_2threads: 1-shuffle reduction for 2T/SF MXFP8 path\n- 2T/SF constants: ELTS_PER_THREAD, THREADS_PER_SF, SF_BLOCKS_PER_WARP +\nlegacy 4T variants\n- MXFP8_2T_SF_THRESHOLD = 65536 \n\n**Test changes**\n- `test_fp4_quantize.py` and `test_fp8_quantize.py`: Add more problem\nsizes.\n- `test_fp4_quantize_padding.py`: Add both-backend parametrization and\nCUDA-vs-CuTe-DSL parity test for linear layout padding.\n\n**Perf comparison between backends on B200**\n\n<details>\n <summary>Click to see mxfp8 performance comparison</summary>\n\nLinear (gmean 1.42x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"mxfp8_backend_comparison_linear_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/21b630ff-d1a7-427b-9e59-5b6417c498c6\"\n/>\n\nSwizzled (gmean 1.37x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"mxfp8_backend_comparison_swizzled_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/f9d19958-df34-4fc9-8351-6b9348aba8c6\"\n/>\n\n\n</details>\n\n<details>\n <summary>Click to see mxfp4 performance comparison</summary>\n\nLinear (gmean 1.41x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"mxfp4_quantize_backend_comparison_linear_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/e050a38d-600e-43c1-92eb-f0b51e22accf\"\n/>\n\n\nSwizzled (gmean 1.39x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"mxfp4_quantize_backend_comparison_swizzled_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/d4e4cd72-baad-4057-9523-63cd6665bf6e\"\n/>\n\n</details>\n\n<details>\n <summary>Click to see nvfp4 performance comparison</summary>\n\nLinear (gmean 1.34x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"nvfp4_quantize_backend_comparison_linear_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/532ef7f2-0a41-406c-8eda-0f16436672c1\"\n/>\n\n\nSwizzled (gmean 1.32x)\n\n<img width=\"1644\" height=\"1477\"\nalt=\"nvfp4_quantize_backend_comparison_swizzled_bfloat16\"\nsrc=\"https://github.com/user-attachments/assets/9694e1d3-e92e-45c9-81b5-527dca4e6cd1\"\n/>\n\n\n</details>\n\n<!-- What does this PR do? Briefly describe the changes and why they’re\nneeded. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* Benchmarks now run and report both linear and swizzled scale-factor\nlayouts separately, generating distinct heatmaps/tables and layout-aware\nlabels.\n* Added a new NVFP4 quantization benchmark with bandwidth and comparison\nmodes.\n\n* **Refactor**\n* Quantize kernels split into layout-specific implementations and\nintroduced dual-mode threading optimizations for better performance\nacross sizes.\n\n* **Tests**\n* Expanded parameter sweeps, added backend parameterization, and\ncapability-aware skips.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"flashinfer/quantization/quantization_cute_dsl_utils.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nCommon utilities for quantization kernels using CuTe-DSL.\n\nThis module contains shared PTX intrinsics and helper functions for MXFP8\nand MXFP4 quantization kernels.\n\"\"\"\n\nimport cutlass.cute as cute\nfrom cutlass import Float32, Int32, Uint32, Uint64\nfrom cutlass._mlir.dialects import llvm\nfrom cutlass.cutlass_dsl import T, dsl_user_op\n\nfrom ..cute_dsl.fp4_common import habs2, hmax2, bfloat2_habs2, bfloat2_hmax2\n\n\n# =============================================================================\n# MXFP8 Constants\n# =============================================================================\n\n# Scale factor vector size: each scale factor covers 32 elements\nSF_VEC_SIZE = 32\n\n# Inverse of max representable value in FP8 E4M3 format (1/448)\nINV_FLOAT8_E4M3_MAX = 1.0 / 448.0\n\n# Thread organization constants\nWARP_SIZE = 32\nELTS_PER_THREAD = 8 # Each thread handles 8 FP16 elements (128 bits)\nTHREADS_PER_SF = SF_VEC_SIZE // ELTS_PER_THREAD # 32 / 8 = 4 threads per SF block\nSF_BLOCKS_PER_WARP = WARP_SIZE // THREADS_PER_SF # 32 / 4 = 8 SF blocks per warp\n\n# Row tiling for swizzled layout (128x4 pattern)\nROW_TILE_SIZE = 128\n\n\n# =============================================================================\n# NVFP4 Constants\n# =============================================================================\n\n# Scale factor vector size for NVFP4: each scale factor covers 16 elements\nNVFP4_SF_VEC_SIZE = 16\n\n# =============================================================================\n# MXFP4 Constants\n# =============================================================================\n\n# Scale factor vector size for MXFP4: each scale factor covers 32 elements\nMXFP4_SF_VEC_SIZE = 32\n\n# Elements per thread for MXFP4: each thread handles 32 elements (one full SF block)\nMXFP4_ELTS_PER_THREAD = 32\n\n# Inverse of max representable value in FP4 E2M1 format (1/6)\nINV_FLOAT4_E2M1_MAX = 1.0 / 6.0\n\n# Global scale factor for MXFP4: 448 * 6 = 2688\nMXFP4_GLOBAL_SCALE_FACTOR = 448.0 * 6.0\n\n\n# =============================================================================\n# Half2 SIMD Intrinsics for Max Reduction\n# =============================================================================\n\n\n@dsl_user_op\ndef hmax_reduce_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 FP16 values in a Half2 as Float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $1;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax_reduce_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 BF16 values as Float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $1, 0xFFFF;\n shr.b32 hi, $1, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# Fast UE8M0 Conversion\n# =============================================================================\n\n\n@dsl_user_op\ndef float_to_ue8m0_fast(value: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"\n Convert float to UE8M0 format using exact IEEE 754 bit manipulation.\n\n Matches the hardware __nv_cvt_float_to_e8m0(value, __NV_SATFINITE, cudaRoundPosInf):\n - Extract biased exponent from IEEE 754 float\n - If mantissa is nonzero, add 1 (round towards +inf / ceil behavior)\n - Clamp to [0, 254] (255 = NaN in E8M0)\n - Return 0 for zero/negative input\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(value).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero, p_has_mant, p_ovf;\n .reg .u32 bits, exp_biased, mantissa, bump, result;\n\n setp.le.f32 p_zero, $1, 0f00000000;\n\n mov.b32 bits, $1;\n shr.b32 exp_biased, bits, 23;\n and.b32 exp_biased, exp_biased, 255;\n and.b32 mantissa, bits, 0x7FFFFF;\n\n setp.ne.u32 p_has_mant, mantissa, 0;\n selp.u32 bump, 1, 0, p_has_mant;\n add.u32 result, exp_biased, bump;\n\n setp.gt.u32 p_ovf, result, 254;\n selp.u32 result, 254, result, p_ovf;\n selp.u32 $0, 0, result, p_zero;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef ue8m0_to_inv_scale_fast(ue8m0_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"\n Convert UE8M0 to inverse scale using fast ex2.approx.\n\n Inverse scale = 2^(127 - ue8m0)\n Returns 0 for ue8m0 == 0.\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(ue8m0_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .s32 neg_exp;\n .reg .f32 neg_exp_f, result;\n\n setp.eq.u32 p_zero, $1, 0;\n sub.s32 neg_exp, 127, $1;\n cvt.rn.f32.s32 neg_exp_f, neg_exp;\n ex2.approx.f32 result, neg_exp_f;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# FP8 Conversion with Scaling\n# =============================================================================\n\n\n@dsl_user_op\ndef half2_to_fp8x2_scaled(\n h2: Uint32, inv_scale: Float32, *, loc=None, ip=None\n) -> Uint32:\n \"\"\"Convert Half2 to 2 FP8 E4M3 values with scaling.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Uint32(h2).ir_value(loc=loc, ip=ip),\n Float32(inv_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n .reg .b16 fp8_pair;\n\n mov.b32 {h0, h1}, $1;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n mul.f32 f0, f0, $2;\n mul.f32 f1, f1, $2;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, f1, f0;\n cvt.u32.u16 $0, fp8_pair;\n }\n \"\"\",\n \"=r,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_to_fp8x2_scaled(\n bf2: Uint32, inv_scale: Float32, *, loc=None, ip=None\n) -> Uint32:\n \"\"\"Convert BFloat16x2 to 2 FP8 E4M3 values with scaling.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Uint32(bf2).ir_value(loc=loc, ip=ip),\n Float32(inv_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n .reg .b16 fp8_pair;\n\n and.b32 lo, $1, 0xFFFF;\n shr.b32 hi, $1, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n mul.f32 f0, f0, $2;\n mul.f32 f1, f1, $2;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, f1, f0;\n cvt.u32.u16 $0, fp8_pair;\n }\n \"\"\",\n \"=r,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef pack_fp8x8_to_u64(\n fp8_01: Uint32, fp8_23: Uint32, fp8_45: Uint32, fp8_67: Uint32, *, loc=None, ip=None\n) -> Uint64:\n \"\"\"Pack 8 FP8 values into a 64-bit value for vectorized store.\"\"\"\n return Uint64(\n llvm.inline_asm(\n T.i64(),\n [\n Uint32(fp8_01).ir_value(loc=loc, ip=ip),\n Uint32(fp8_23).ir_value(loc=loc, ip=ip),\n Uint32(fp8_45).ir_value(loc=loc, ip=ip),\n Uint32(fp8_67).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .b32 t01, t23, t45, t67;\n\n and.b32 t01, $1, 0xFFFF;\n and.b32 t23, $2, 0xFFFF;\n and.b32 t45, $3, 0xFFFF;\n and.b32 t67, $4, 0xFFFF;\n\n shl.b32 t23, t23, 16;\n or.b32 lo, t01, t23;\n\n shl.b32 t67, t67, 16;\n or.b32 hi, t45, t67;\n\n mov.b64 $0, {lo, hi};\n }\n \"\"\",\n \"=l,r,r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# E2M1 (FP4) Conversion for MXFP4\n# =============================================================================\n\n\n@dsl_user_op\ndef half2_to_float2_scaled(\n h2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> tuple[Float32, Float32]:\n \"\"\"Convert Half2 to Float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(h2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $2;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n@dsl_user_op\ndef bfloat2_to_float2_scaled(\n bf2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> tuple[Float32, Float32]:\n \"\"\"Convert BFloat16x2 to Float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(bf2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $2, 0xFFFF;\n shr.b32 hi, $2, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n@dsl_user_op\ndef cvt_e2m1x8_f32(\n v0: Float32,\n v1: Float32,\n v2: Float32,\n v3: Float32,\n v4: Float32,\n v5: Float32,\n v6: Float32,\n v7: Float32,\n *,\n loc=None,\n ip=None,\n) -> Uint32:\n \"\"\"\n Convert eight float32 values to eight E2M1 (4-bit) values packed into uint32.\n\n Uses cvt.rn.satfinite.e2m1x2.f32 PTX instruction to convert pairs of f32\n to pairs of 4-bit E2M1 values, then packs all 8 values into a single u32.\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n Float32(v2).ir_value(loc=loc, ip=ip),\n Float32(v3).ir_value(loc=loc, ip=ip),\n Float32(v4).ir_value(loc=loc, ip=ip),\n Float32(v5).ir_value(loc=loc, ip=ip),\n Float32(v6).ir_value(loc=loc, ip=ip),\n Float32(v7).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 byte0, byte1, byte2, byte3;\n cvt.rn.satfinite.e2m1x2.f32 byte0, $2, $1;\n cvt.rn.satfinite.e2m1x2.f32 byte1, $4, $3;\n cvt.rn.satfinite.e2m1x2.f32 byte2, $6, $5;\n cvt.rn.satfinite.e2m1x2.f32 byte3, $8, $7;\n mov.b32 $0, {byte0, byte1, byte2, byte3};\n }\n \"\"\",\n \"=r,f,f,f,f,f,f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Warp Shuffle for 4-Thread Reduction\n# =============================================================================\n\n\n@cute.jit\ndef shuffle_xor_f32(val: Float32, offset: int) -> Float32:\n \"\"\"XOR shuffle for float32 values.\"\"\"\n return cute.arch.shuffle_sync_bfly(val, offset=offset)\n\n\n@cute.jit\ndef reduce_max_4threads(val: Float32) -> Float32:\n \"\"\"Reduce max across 4 consecutive threads using 2 XOR shuffles.\"\"\"\n from ..cute_dsl.fp4_common import fmax_f32\n\n other = shuffle_xor_f32(val, 1)\n val = fmax_f32(val, other)\n other = shuffle_xor_f32(val, 2)\n val = fmax_f32(val, other)\n return val\n\n\n# =============================================================================\n# Swizzled Index Computation (GPU-side)\n# =============================================================================\n\n\n@cute.jit\ndef compute_sf_index_swizzled_128x4_gpu(\n row_idx: Int32,\n col_idx: Int32,\n padded_cols: Int32,\n) -> Int32:\n \"\"\"Compute swizzled 128x4 scale factor index on GPU.\"\"\"\n kColumnGroup0Size = Int32(4)\n kRowGroup0Size = Int32(32)\n kRowGroup1Size = Int32(128)\n\n columnIdxInGroup0 = col_idx % kColumnGroup0Size\n columnGroupIdx = col_idx // kColumnGroup0Size\n columnGroupStride = Int32(512)\n\n rowIdxInGroup0 = row_idx % kRowGroup0Size\n rowIdxInGroup1 = (row_idx % kRowGroup1Size) // kRowGroup0Size\n rowGroupIdx = row_idx // kRowGroup1Size\n\n rowGroup1Stride = Int32(4)\n rowGroup0Stride = Int32(16)\n rowGroupStride = kRowGroup1Size * padded_cols\n\n offset = (\n columnIdxInGroup0\n + columnGroupIdx * columnGroupStride\n + rowIdxInGroup0 * rowGroup0Stride\n + rowIdxInGroup1 * rowGroup1Stride\n + rowGroupIdx * rowGroupStride\n )\n\n return offset\n\n\n@cute.jit\ndef compute_sf_index_swizzled_8x4_gpu(\n row_idx: Int32,\n col_idx: Int32,\n padded_cols: Int32,\n) -> Int32:\n \"\"\"Compute swizzled 8x4 scale factor index on GPU.\n\n Layout: [numMTiles, numKTiles, 8 (mTile), 4 (kTile)]\n Tile size: 32 elements (8 rows x 4 cols).\n \"\"\"\n kMTileSize = Int32(8)\n kKTileSize = Int32(4)\n kTileElements = Int32(32)\n\n innerKIdx = col_idx % kKTileSize\n innerMIdx = row_idx % kMTileSize\n kTileIdx = col_idx // kKTileSize\n mTileIdx = row_idx // kMTileSize\n\n numKTiles = (padded_cols + kKTileSize - Int32(1)) // kKTileSize\n\n offset = (\n mTileIdx * (numKTiles * kTileElements)\n + kTileIdx * kTileElements\n + innerMIdx * kKTileSize\n + innerKIdx\n )\n\n return offset\n\n\n@cute.jit\ndef compute_sf_index_linear_gpu(\n row_idx: Int32,\n col_idx: Int32,\n num_cols: Int32,\n) -> Int32:\n \"\"\"Compute linear (row-major) scale factor index on GPU.\"\"\"\n return row_idx * num_cols + col_idx\n\n\n# =============================================================================\n# High-Level Helper Functions for MXFP8 Quantization\n# =============================================================================\n\n\n@cute.jit\ndef half2_max_abs_4(v0: Uint32, v1: Uint32, v2: Uint32, v3: Uint32) -> Uint32:\n \"\"\"\n Compute max absolute value across 4 half2 values (8 FP16 elements).\n\n Uses tree reduction: 4 -> 2 -> 1 half2 values.\n Returns a half2 containing the max absolute value in both lanes.\n \"\"\"\n abs0 = habs2(v0)\n abs1 = habs2(v1)\n abs2 = habs2(v2)\n abs3 = habs2(v3)\n max01 = hmax2(abs0, abs1)\n max23 = hmax2(abs2, abs3)\n return hmax2(max01, max23)\n\n\n@cute.jit\ndef bfloat2_max_abs_4(v0: Uint32, v1: Uint32, v2: Uint32, v3: Uint32) -> Uint32:\n \"\"\"\n Compute max absolute value across 4 bfloat2 values (8 BF16 elements).\n\n Uses tree reduction: 4 -> 2 -> 1 bfloat2 values.\n Returns a bfloat2 containing the max absolute value in both lanes.\n \"\"\"\n abs0 = bfloat2_habs2(v0)\n abs1 = bfloat2_habs2(v1)\n abs2 = bfloat2_habs2(v2)\n abs3 = bfloat2_habs2(v3)\n max01 = bfloat2_hmax2(abs0, abs1)\n max23 = bfloat2_hmax2(abs2, abs3)\n return bfloat2_hmax2(max01, max23)\n\n\n@cute.jit\ndef half2x4_to_fp8x8_packed(\n v0: Uint32, v1: Uint32, v2: Uint32, v3: Uint32, inv_scale: Float32\n) -> Uint64:\n \"\"\"\n Convert 4 half2 values (8 FP16) to 8 FP8 E4M3 and pack into u64.\n\n Each half2 is converted to 2 FP8 values using the inverse scale,\n then all 8 FP8 values are packed into a single 64-bit value for\n efficient vectorized store.\n \"\"\"\n fp8_01 = half2_to_fp8x2_scaled(v0, inv_scale)\n fp8_23 = half2_to_fp8x2_scaled(v1, inv_scale)\n fp8_45 = half2_to_fp8x2_scaled(v2, inv_scale)\n fp8_67 = half2_to_fp8x2_scaled(v3, inv_scale)\n return pack_fp8x8_to_u64(fp8_01, fp8_23, fp8_45, fp8_67)\n\n\n@cute.jit\ndef bfloat2x4_to_fp8x8_packed(\n v0: Uint32, v1: Uint32, v2: Uint32, v3: Uint32, inv_scale: Float32\n) -> Uint64:\n \"\"\"\n Convert 4 bfloat2 values (8 BF16) to 8 FP8 E4M3 and pack into u64.\n\n Each bfloat2 is converted to 2 FP8 values using the inverse scale,\n then all 8 FP8 values are packed into a single 64-bit value for\n efficient vectorized store.\n \"\"\"\n fp8_01 = bfloat2_to_fp8x2_scaled(v0, inv_scale)\n fp8_23 = bfloat2_to_fp8x2_scaled(v1, inv_scale)\n fp8_45 = bfloat2_to_fp8x2_scaled(v2, inv_scale)\n fp8_67 = bfloat2_to_fp8x2_scaled(v3, inv_scale)\n return pack_fp8x8_to_u64(fp8_01, fp8_23, fp8_45, fp8_67)\n\n\n# =============================================================================\n# MXFP4 High-Level Helper Functions\n# =============================================================================\n\n\n@cute.jit\ndef half2_max_abs_8(\n v0: Uint32,\n v1: Uint32,\n v2: Uint32,\n v3: Uint32,\n v4: Uint32,\n v5: Uint32,\n v6: Uint32,\n v7: Uint32,\n) -> Uint32:\n \"\"\"\n Compute max absolute value across 8 half2 values (16 FP16 elements).\n\n Uses tree reduction: 8 -> 4 -> 2 -> 1 half2 values.\n Returns a half2 containing the max absolute value in both lanes.\n \"\"\"\n abs0 = habs2(v0)\n abs1 = habs2(v1)\n abs2 = habs2(v2)\n abs3 = habs2(v3)\n abs4 = habs2(v4)\n abs5 = habs2(v5)\n abs6 = habs2(v6)\n abs7 = habs2(v7)\n\n max01 = hmax2(abs0, abs1)\n max23 = hmax2(abs2, abs3)\n max45 = hmax2(abs4, abs5)\n max67 = hmax2(abs6, abs7)\n\n max0123 = hmax2(max01, max23)\n max4567 = hmax2(max45, max67)\n\n return hmax2(max0123, max4567)\n\n\n@cute.jit\ndef bfloat2_max_abs_8(\n v0: Uint32,\n v1: Uint32,\n v2: Uint32,\n v3: Uint32,\n v4: Uint32,\n v5: Uint32,\n v6: Uint32,\n v7: Uint32,\n) -> Uint32:\n \"\"\"\n Compute max absolute value across 8 bfloat2 values (16 BF16 elements).\n\n Uses tree reduction: 8 -> 4 -> 2 -> 1 bfloat2 values.\n Returns a bfloat2 containing the max absolute value in both lanes.\n \"\"\"\n abs0 = bfloat2_habs2(v0)\n abs1 = bfloat2_habs2(v1)\n abs2 = bfloat2_habs2(v2)\n abs3 = bfloat2_habs2(v3)\n abs4 = bfloat2_habs2(v4)\n abs5 = bfloat2_habs2(v5)\n abs6 = bfloat2_habs2(v6)\n abs7 = bfloat2_habs2(v7)\n\n max01 = bfloat2_hmax2(abs0, abs1)\n max23 = bfloat2_hmax2(abs2, abs3)\n max45 = bfloat2_hmax2(abs4, abs5)\n max67 = bfloat2_hmax2(abs6, abs7)\n\n max0123 = bfloat2_hmax2(max01, max23)\n max4567 = bfloat2_hmax2(max45, max67)\n\n return bfloat2_hmax2(max0123, max4567)\n\n\n@cute.jit\ndef process_mxfp4_block_half(row_tensor, elem_base: Int32) -> tuple:\n \"\"\"\n Process a 32-element MXFP4 block for half precision input.\n\n Loads 32 FP16 elements, computes the UE8M0 scale factor, converts to E2M1,\n and packs the result into two u64 values.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n\n Returns:\n (scale_ue8m0_u32, scale_ue8m0_u8, packed64_0, packed64_1):\n - scale_ue8m0_u32: Scale factor as Uint32 (for inv_scale computation)\n - scale_ue8m0_u8: Scale factor as Uint8 (for storage)\n - packed64_0, packed64_1: Two Uint64 containing 16 E2M1 values each\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n get_ptr_as_int64,\n hmax2,\n ld_global_v4_u32,\n rcp_approx_ftz,\n )\n\n # Load 32 elements (4 x 128-bit = 16 half2 values)\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n ptr2 = get_ptr_as_int64(row_tensor, elem_base + Int32(16))\n ptr3 = get_ptr_as_int64(row_tensor, elem_base + Int32(24))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n h8, h9, h10, h11 = ld_global_v4_u32(ptr2)\n h12, h13, h14, h15 = ld_global_v4_u32(ptr3)\n\n # Compute max absolute value across 32 elements\n max_first = half2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n max_second = half2_max_abs_8(h8, h9, h10, h11, h12, h13, h14, h15)\n block_max_h2 = hmax2(max_first, max_second)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n # Compute UE8M0 scale factor (rcp_approx matches CUDA's rcp.approx.ftz(6.0f))\n normalized_max = block_max * rcp_approx_ftz(Float32(6.0))\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0_u8 = scale_ue8m0_u32.to(Uint8)\n\n # Compute inverse scale and convert to E2M1 packed format\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n packed64_0, packed64_1 = half2x16_to_e2m1x32_packed(\n h0,\n h1,\n h2,\n h3,\n h4,\n h5,\n h6,\n h7,\n h8,\n h9,\n h10,\n h11,\n h12,\n h13,\n h14,\n h15,\n inv_scale,\n )\n\n return scale_ue8m0_u32, scale_ue8m0_u8, packed64_0, packed64_1\n\n\n@cute.jit\ndef process_mxfp4_block_bfloat(row_tensor, elem_base: Int32) -> tuple:\n \"\"\"\n Process a 32-element MXFP4 block for bfloat16 precision input.\n\n Loads 32 BF16 elements, computes the UE8M0 scale factor, converts to E2M1,\n and packs the result into two u64 values.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n\n Returns:\n (scale_ue8m0_u32, scale_ue8m0_u8, packed64_0, packed64_1):\n - scale_ue8m0_u32: Scale factor as Uint32 (for inv_scale computation)\n - scale_ue8m0_u8: Scale factor as Uint8 (for storage)\n - packed64_0, packed64_1: Two Uint64 containing 16 E2M1 values each\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n bfloat2_hmax2,\n get_ptr_as_int64,\n ld_global_v4_u32,\n rcp_approx_ftz,\n )\n\n # Load 32 elements (4 x 128-bit = 16 bfloat2 values)\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n ptr2 = get_ptr_as_int64(row_tensor, elem_base + Int32(16))\n ptr3 = get_ptr_as_int64(row_tensor, elem_base + Int32(24))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n h8, h9, h10, h11 = ld_global_v4_u32(ptr2)\n h12, h13, h14, h15 = ld_global_v4_u32(ptr3)\n\n # Compute max absolute value across 32 elements\n max_first = bfloat2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n max_second = bfloat2_max_abs_8(h8, h9, h10, h11, h12, h13, h14, h15)\n block_max_h2 = bfloat2_hmax2(max_first, max_second)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n\n # Compute UE8M0 scale factor (rcp_approx matches CUDA's rcp.approx.ftz(6.0f))\n normalized_max = block_max * rcp_approx_ftz(Float32(6.0))\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0_u8 = scale_ue8m0_u32.to(Uint8)\n\n # Compute inverse scale and convert to E2M1 packed format\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n packed64_0, packed64_1 = bfloat2x16_to_e2m1x32_packed(\n h0,\n h1,\n h2,\n h3,\n h4,\n h5,\n h6,\n h7,\n h8,\n h9,\n h10,\n h11,\n h12,\n h13,\n h14,\n h15,\n inv_scale,\n )\n\n return scale_ue8m0_u32, scale_ue8m0_u8, packed64_0, packed64_1\n\n\n@cute.jit\ndef ld_32_elements(row_tensor, elem_base: Int32) -> tuple:\n \"\"\"\n Load 32 elements (16 half2/bfloat2 values) from a row tensor.\n\n This loads 4 x 128-bit vectors (4 x v4_u32) starting at elem_base.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n\n Returns:\n Tuple of 16 Uint32 values (h0-h15), each containing 2 fp16/bf16 elements\n \"\"\"\n from ..cute_dsl.fp4_common import get_ptr_as_int64, ld_global_v4_u32\n\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n ptr2 = get_ptr_as_int64(row_tensor, elem_base + Int32(16))\n ptr3 = get_ptr_as_int64(row_tensor, elem_base + Int32(24))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0) # Elements 0-7\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1) # Elements 8-15\n h8, h9, h10, h11 = ld_global_v4_u32(ptr2) # Elements 16-23\n h12, h13, h14, h15 = ld_global_v4_u32(ptr3) # Elements 24-31\n\n return h0, h1, h2, h3, h4, h5, h6, h7, h8, h9, h10, h11, h12, h13, h14, h15\n\n\n@cute.jit\ndef half2x16_to_e2m1x32_packed(\n h0: Uint32,\n h1: Uint32,\n h2: Uint32,\n h3: Uint32,\n h4: Uint32,\n h5: Uint32,\n h6: Uint32,\n h7: Uint32,\n h8: Uint32,\n h9: Uint32,\n h10: Uint32,\n h11: Uint32,\n h12: Uint32,\n h13: Uint32,\n h14: Uint32,\n h15: Uint32,\n inv_scale: Float32,\n) -> tuple:\n \"\"\"\n Convert 16 half2 values (32 FP16) to 32 E2M1 and pack into two u64.\n\n Each half2 is converted to 2 float32 values using inv_scale,\n then groups of 8 floats are converted to 8 E2M1 values packed into u32,\n and finally combined into two u64 values for vectorized store.\n\n Returns:\n (packed64_0, packed64_1): Two Uint64 containing 16 E2M1 values each\n \"\"\"\n # Scale and convert each half2 to 2 float32\n s0, s1 = half2_to_float2_scaled(h0, inv_scale)\n s2, s3 = half2_to_float2_scaled(h1, inv_scale)\n s4, s5 = half2_to_float2_scaled(h2, inv_scale)\n s6, s7 = half2_to_float2_scaled(h3, inv_scale)\n s8, s9 = half2_to_float2_scaled(h4, inv_scale)\n s10, s11 = half2_to_float2_scaled(h5, inv_scale)\n s12, s13 = half2_to_float2_scaled(h6, inv_scale)\n s14, s15 = half2_to_float2_scaled(h7, inv_scale)\n s16, s17 = half2_to_float2_scaled(h8, inv_scale)\n s18, s19 = half2_to_float2_scaled(h9, inv_scale)\n s20, s21 = half2_to_float2_scaled(h10, inv_scale)\n s22, s23 = half2_to_float2_scaled(h11, inv_scale)\n s24, s25 = half2_to_float2_scaled(h12, inv_scale)\n s26, s27 = half2_to_float2_scaled(h13, inv_scale)\n s28, s29 = half2_to_float2_scaled(h14, inv_scale)\n s30, s31 = half2_to_float2_scaled(h15, inv_scale)\n\n # Convert to E2M1 (4 x 8 floats -> 4 x uint32)\n packed0 = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed1 = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n packed2 = cvt_e2m1x8_f32(s16, s17, s18, s19, s20, s21, s22, s23)\n packed3 = cvt_e2m1x8_f32(s24, s25, s26, s27, s28, s29, s30, s31)\n\n # Pack into 2 x 64-bit values\n packed64_0 = (Uint64(packed1) << Uint64(32)) | Uint64(packed0)\n packed64_1 = (Uint64(packed3) << Uint64(32)) | Uint64(packed2)\n\n return packed64_0, packed64_1\n\n\n@cute.jit\ndef bfloat2x16_to_e2m1x32_packed(\n h0: Uint32,\n h1: Uint32,\n h2: Uint32,\n h3: Uint32,\n h4: Uint32,\n h5: Uint32,\n h6: Uint32,\n h7: Uint32,\n h8: Uint32,\n h9: Uint32,\n h10: Uint32,\n h11: Uint32,\n h12: Uint32,\n h13: Uint32,\n h14: Uint32,\n h15: Uint32,\n inv_scale: Float32,\n) -> tuple:\n \"\"\"\n Convert 16 bfloat2 values (32 BF16) to 32 E2M1 and pack into two u64.\n\n Each bfloat2 is converted to 2 float32 values using inv_scale,\n then groups of 8 floats are converted to 8 E2M1 values packed into u32,\n and finally combined into two u64 values for vectorized store.\n\n Returns:\n (packed64_0, packed64_1): Two Uint64 containing 16 E2M1 values each\n \"\"\"\n # Scale and convert each bfloat2 to 2 float32\n s0, s1 = bfloat2_to_float2_scaled(h0, inv_scale)\n s2, s3 = bfloat2_to_float2_scaled(h1, inv_scale)\n s4, s5 = bfloat2_to_float2_scaled(h2, inv_scale)\n s6, s7 = bfloat2_to_float2_scaled(h3, inv_scale)\n s8, s9 = bfloat2_to_float2_scaled(h4, inv_scale)\n s10, s11 = bfloat2_to_float2_scaled(h5, inv_scale)\n s12, s13 = bfloat2_to_float2_scaled(h6, inv_scale)\n s14, s15 = bfloat2_to_float2_scaled(h7, inv_scale)\n s16, s17 = bfloat2_to_float2_scaled(h8, inv_scale)\n s18, s19 = bfloat2_to_float2_scaled(h9, inv_scale)\n s20, s21 = bfloat2_to_float2_scaled(h10, inv_scale)\n s22, s23 = bfloat2_to_float2_scaled(h11, inv_scale)\n s24, s25 = bfloat2_to_float2_scaled(h12, inv_scale)\n s26, s27 = bfloat2_to_float2_scaled(h13, inv_scale)\n s28, s29 = bfloat2_to_float2_scaled(h14, inv_scale)\n s30, s31 = bfloat2_to_float2_scaled(h15, inv_scale)\n\n # Convert to E2M1 (4 x 8 floats -> 4 x uint32)\n packed0 = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed1 = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n packed2 = cvt_e2m1x8_f32(s16, s17, s18, s19, s20, s21, s22, s23)\n packed3 = cvt_e2m1x8_f32(s24, s25, s26, s27, s28, s29, s30, s31)\n\n # Pack into 2 x 64-bit values\n packed64_0 = (Uint64(packed1) << Uint64(32)) | Uint64(packed0)\n packed64_1 = (Uint64(packed3) << Uint64(32)) | Uint64(packed2)\n\n return packed64_0, packed64_1\n\n\n# =============================================================================\n# NVFP4 High-Level Helper Functions (sf_vec_size=16, E4M3 scale factors)\n# =============================================================================\n\n\n@cute.jit\ndef half2x8_to_e2m1x16_packed(\n h0: Uint32,\n h1: Uint32,\n h2: Uint32,\n h3: Uint32,\n h4: Uint32,\n h5: Uint32,\n h6: Uint32,\n h7: Uint32,\n inv_scale: Float32,\n) -> Uint64:\n \"\"\"\n Convert 8 half2 values (16 FP16) to 16 E2M1 and pack into u64.\n\n Returns:\n Uint64 containing 16 E2M1 values (8 bytes)\n \"\"\"\n s0, s1 = half2_to_float2_scaled(h0, inv_scale)\n s2, s3 = half2_to_float2_scaled(h1, inv_scale)\n s4, s5 = half2_to_float2_scaled(h2, inv_scale)\n s6, s7 = half2_to_float2_scaled(h3, inv_scale)\n s8, s9 = half2_to_float2_scaled(h4, inv_scale)\n s10, s11 = half2_to_float2_scaled(h5, inv_scale)\n s12, s13 = half2_to_float2_scaled(h6, inv_scale)\n s14, s15 = half2_to_float2_scaled(h7, inv_scale)\n\n packed_lo = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed_hi = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n@cute.jit\ndef bfloat2x8_to_e2m1x16_packed(\n h0: Uint32,\n h1: Uint32,\n h2: Uint32,\n h3: Uint32,\n h4: Uint32,\n h5: Uint32,\n h6: Uint32,\n h7: Uint32,\n inv_scale: Float32,\n) -> Uint64:\n \"\"\"\n Convert 8 bfloat2 values (16 BF16) to 16 E2M1 and pack into u64.\n\n Returns:\n Uint64 containing 16 E2M1 values (8 bytes)\n \"\"\"\n s0, s1 = bfloat2_to_float2_scaled(h0, inv_scale)\n s2, s3 = bfloat2_to_float2_scaled(h1, inv_scale)\n s4, s5 = bfloat2_to_float2_scaled(h2, inv_scale)\n s6, s7 = bfloat2_to_float2_scaled(h3, inv_scale)\n s8, s9 = bfloat2_to_float2_scaled(h4, inv_scale)\n s10, s11 = bfloat2_to_float2_scaled(h5, inv_scale)\n s12, s13 = bfloat2_to_float2_scaled(h6, inv_scale)\n s14, s15 = bfloat2_to_float2_scaled(h7, inv_scale)\n\n packed_lo = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed_hi = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n@cute.jit\ndef process_nvfp4_block_half(\n row_tensor, elem_base: Int32, global_scale: Float32\n) -> tuple:\n \"\"\"\n Process a 16-element NVFP4 block for half precision input.\n\n Loads 16 FP16 elements, computes the E4M3 scale factor using global_scale,\n converts to E2M1, and packs the result into a u64 value.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n global_scale: User-provided global scale factor\n\n Returns:\n (scale_e4m3_u8, packed64):\n - scale_e4m3_u8: E4M3 scale factor as Uint8\n - packed64: Uint64 containing 16 E2M1 values\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n cvt_f32_to_e4m3,\n get_ptr_as_int64,\n ld_global_v4_u32,\n nvfp4_compute_output_scale,\n rcp_approx_ftz,\n )\n\n # Load 16 elements (2 x 128-bit = 8 half2 values)\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n\n # Compute max absolute value across 16 elements\n block_max_h2 = half2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n # E4M3 scale factor computation\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n\n # output_scale = rcp(float(E4M3(scale)) * rcp(global_scale)), matching CUDA\n output_scale = nvfp4_compute_output_scale(scale_fp8_u32, global_scale)\n\n # Convert to E2M1 and pack\n packed64 = half2x8_to_e2m1x16_packed(h0, h1, h2, h3, h4, h5, h6, h7, output_scale)\n\n return scale_fp8, packed64\n\n\n@cute.jit\ndef process_nvfp4_block_bfloat(\n row_tensor, elem_base: Int32, global_scale: Float32\n) -> tuple:\n \"\"\"\n Process a 16-element NVFP4 block for bfloat16 precision input.\n\n Loads 16 BF16 elements, computes the E4M3 scale factor using global_scale,\n converts to E2M1, and packs the result into a u64 value.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n global_scale: User-provided global scale factor\n\n Returns:\n (scale_e4m3_u8, packed64):\n - scale_e4m3_u8: E4M3 scale factor as Uint8\n - packed64: Uint64 containing 16 E2M1 values\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n cvt_f32_to_e4m3,\n get_ptr_as_int64,\n ld_global_v4_u32,\n nvfp4_compute_output_scale,\n rcp_approx_ftz,\n )\n\n # Load 16 elements (2 x 128-bit = 8 bfloat2 values)\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n\n # Compute max absolute value across 16 elements\n block_max_h2 = bfloat2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n\n # E4M3 scale factor computation\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n\n # output_scale = rcp(float(E4M3(scale)) * rcp(global_scale)), matching CUDA\n output_scale = nvfp4_compute_output_scale(scale_fp8_u32, global_scale)\n\n # Convert to E2M1 and pack\n packed64 = bfloat2x8_to_e2m1x16_packed(h0, h1, h2, h3, h4, h5, h6, h7, output_scale)\n\n return scale_fp8, packed64\n\n\n@cute.jit\ndef fp8x16_to_e2m1x16_packed(\n w0: Uint32,\n w1: Uint32,\n w2: Uint32,\n w3: Uint32,\n output_scale: Float32,\n) -> Uint64:\n \"\"\"Convert 16 packed FP8 E4M3 values (4 x uint32) to 16 E2M1 values packed as Uint64.\n\n Each uint32 contains 4 E4M3 bytes. Output is 16 E2M1 nibbles packed into 8 bytes.\n \"\"\"\n from ..cute_dsl.fp4_common import cvt_e4m3x4_to_f32x4\n\n f0, f1, f2, f3 = cvt_e4m3x4_to_f32x4(w0)\n f4, f5, f6, f7 = cvt_e4m3x4_to_f32x4(w1)\n f8, f9, f10, f11 = cvt_e4m3x4_to_f32x4(w2)\n f12, f13, f14, f15 = cvt_e4m3x4_to_f32x4(w3)\n\n s0 = f0 * output_scale\n s1 = f1 * output_scale\n s2 = f2 * output_scale\n s3 = f3 * output_scale\n s4 = f4 * output_scale\n s5 = f5 * output_scale\n s6 = f6 * output_scale\n s7 = f7 * output_scale\n s8 = f8 * output_scale\n s9 = f9 * output_scale\n s10 = f10 * output_scale\n s11 = f11 * output_scale\n s12 = f12 * output_scale\n s13 = f13 * output_scale\n s14 = f14 * output_scale\n s15 = f15 * output_scale\n\n packed_lo = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed_hi = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n@cute.jit\ndef fp8_max_abs_16(w0: Uint32, w1: Uint32, w2: Uint32, w3: Uint32) -> Float32:\n \"\"\"Compute max absolute value across 16 FP8 E4M3 values (4 x uint32).\n\n Converts all 16 values to float32, takes abs, and reduces to a single max.\n \"\"\"\n from ..cute_dsl.fp4_common import cvt_e4m3x4_to_f32x4\n\n f0, f1, f2, f3 = cvt_e4m3x4_to_f32x4(w0)\n f4, f5, f6, f7 = cvt_e4m3x4_to_f32x4(w1)\n f8, f9, f10, f11 = cvt_e4m3x4_to_f32x4(w2)\n f12, f13, f14, f15 = cvt_e4m3x4_to_f32x4(w3)\n\n from ..cute_dsl.fp4_common import fabs_f32, fmax_f32\n\n a0 = fabs_f32(f0)\n a1 = fabs_f32(f1)\n a2 = fabs_f32(f2)\n a3 = fabs_f32(f3)\n a4 = fabs_f32(f4)\n a5 = fabs_f32(f5)\n a6 = fabs_f32(f6)\n a7 = fabs_f32(f7)\n a8 = fabs_f32(f8)\n a9 = fabs_f32(f9)\n a10 = fabs_f32(f10)\n a11 = fabs_f32(f11)\n a12 = fabs_f32(f12)\n a13 = fabs_f32(f13)\n a14 = fabs_f32(f14)\n a15 = fabs_f32(f15)\n\n m01 = fmax_f32(a0, a1)\n m23 = fmax_f32(a2, a3)\n m45 = fmax_f32(a4, a5)\n m67 = fmax_f32(a6, a7)\n m89 = fmax_f32(a8, a9)\n m1011 = fmax_f32(a10, a11)\n m1213 = fmax_f32(a12, a13)\n m1415 = fmax_f32(a14, a15)\n\n m0123 = fmax_f32(m01, m23)\n m4567 = fmax_f32(m45, m67)\n m891011 = fmax_f32(m89, m1011)\n m12131415 = fmax_f32(m1213, m1415)\n\n m_lo = fmax_f32(m0123, m4567)\n m_hi = fmax_f32(m891011, m12131415)\n\n return fmax_f32(m_lo, m_hi)\n\n\n@cute.jit\ndef process_nvfp4_block_fp8(\n row_tensor, elem_base: Int32, global_scale: Float32\n) -> tuple:\n \"\"\"\n Process a 16-element NVFP4 block for FP8 E4M3 input.\n\n Matches the CUDA cvt_warp_fp8_to_fp4 behavior: FP8 values are first converted\n to float32, pre-scaled by 6/global_scale, and converted to half2. From there,\n the standard half2 pipeline is used for max-abs reduction, scale factor\n computation, and E2M1 conversion.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n global_scale: User-provided global scale factor\n\n Returns:\n (scale_e4m3_u8, packed64):\n - scale_e4m3_u8: E4M3 scale factor as Uint8\n - packed64: Uint64 containing 16 E2M1 values\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n cvt_e4m3x4_to_f32x4,\n cvt_f32_to_e4m3,\n cvt_f32x2_to_half2,\n get_ptr_as_int64,\n ld_global_v4_u32,\n nvfp4_compute_output_scale,\n rcp_approx_ftz,\n )\n\n # Load 16 FP8 elements (1 x 128-bit = 4 x uint32 = 16 bytes)\n ptr = get_ptr_as_int64(row_tensor, elem_base)\n w0, w1, w2, w3 = ld_global_v4_u32(ptr)\n\n # Convert FP8 to float32 and pre-scale by 6/global_scale (matching CUDA)\n prescale = Float32(6.0) * rcp_approx_ftz(global_scale)\n\n f0, f1, f2, f3 = cvt_e4m3x4_to_f32x4(w0)\n f4, f5, f6, f7 = cvt_e4m3x4_to_f32x4(w1)\n f8, f9, f10, f11 = cvt_e4m3x4_to_f32x4(w2)\n f12, f13, f14, f15 = cvt_e4m3x4_to_f32x4(w3)\n\n # Pack pre-scaled float pairs into half2 (matching __float22half2_rn in CUDA)\n h0 = cvt_f32x2_to_half2(f0 * prescale, f1 * prescale)\n h1 = cvt_f32x2_to_half2(f2 * prescale, f3 * prescale)\n h2 = cvt_f32x2_to_half2(f4 * prescale, f5 * prescale)\n h3 = cvt_f32x2_to_half2(f6 * prescale, f7 * prescale)\n h4 = cvt_f32x2_to_half2(f8 * prescale, f9 * prescale)\n h5 = cvt_f32x2_to_half2(f10 * prescale, f11 * prescale)\n h6 = cvt_f32x2_to_half2(f12 * prescale, f13 * prescale)\n h7 = cvt_f32x2_to_half2(f14 * prescale, f15 * prescale)\n\n # From here, use the same half2 pipeline as process_nvfp4_block_half\n block_max_h2 = half2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n # E4M3 scale factor computation\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n\n # output_scale = rcp(float(E4M3(scale)) * rcp(global_scale)), matching CUDA\n output_scale = nvfp4_compute_output_scale(scale_fp8_u32, global_scale)\n\n # Convert pre-scaled half2 values to E2M1 and pack\n packed64 = half2x8_to_e2m1x16_packed(h0, h1, h2, h3, h4, h5, h6, h7, output_scale)\n\n return scale_fp8, packed64\n\n\n__all__ = [\n # NVFP4 Constants\n \"NVFP4_SF_VEC_SIZE\",\n # MXFP8 Constants\n \"SF_VEC_SIZE\",\n \"INV_FLOAT8_E4M3_MAX\",\n \"WARP_SIZE\",\n \"ELTS_PER_THREAD\",\n \"THREADS_PER_SF\",\n \"SF_BLOCKS_PER_WARP\",\n \"ROW_TILE_SIZE\",\n # MXFP4 Constants\n \"MXFP4_SF_VEC_SIZE\",\n \"MXFP4_ELTS_PER_THREAD\",\n \"INV_FLOAT4_E2M1_MAX\",\n \"MXFP4_GLOBAL_SCALE_FACTOR\",\n # Low-level intrinsics (MXFP8)\n \"hmax_reduce_to_f32\",\n \"bfloat2_hmax_reduce_to_f32\",\n \"float_to_ue8m0_fast\",\n \"ue8m0_to_inv_scale_fast\",\n \"reduce_max_4threads\",\n \"compute_sf_index_swizzled_128x4_gpu\",\n \"compute_sf_index_swizzled_8x4_gpu\",\n \"compute_sf_index_linear_gpu\",\n # Low-level intrinsics (MXFP4 - E2M1 conversion)\n \"half2_to_float2_scaled\",\n \"bfloat2_to_float2_scaled\",\n \"cvt_e2m1x8_f32\",\n # High-level helper functions (MXFP8)\n \"half2_max_abs_4\",\n \"bfloat2_max_abs_4\",\n \"half2x4_to_fp8x8_packed\",\n \"bfloat2x4_to_fp8x8_packed\",\n # High-level helper functions (MXFP4)\n \"half2_max_abs_8\",\n \"bfloat2_max_abs_8\",\n \"process_mxfp4_block_half\",\n \"process_mxfp4_block_bfloat\",\n \"ld_32_elements\",\n \"half2x16_to_e2m1x32_packed\",\n \"bfloat2x16_to_e2m1x32_packed\",\n # High-level helper functions (NVFP4)\n \"half2x8_to_e2m1x16_packed\",\n \"bfloat2x8_to_e2m1x16_packed\",\n \"process_nvfp4_block_half\",\n \"process_nvfp4_block_bfloat\",\n # High-level helper functions (NVFP4 - FP8 input)\n \"fp8x16_to_e2m1x16_packed\",\n \"fp8_max_abs_16\",\n \"process_nvfp4_block_fp8\",\n]\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nCommon utilities for quantization kernels using CuTe-DSL.\n\nThis module contains shared PTX intrinsics and helper functions for MXFP8\nand MXFP4 quantization kernels.\n\"\"\"\n\nimport cutlass.cute as cute\nfrom cutlass import Float32, Int32, Uint32, Uint64\nfrom cutlass._mlir.dialects import llvm\nfrom cutlass.cutlass_dsl import T, dsl_user_op\n\nfrom ..cute_dsl.fp4_common import habs2, hmax2, bfloat2_habs2, bfloat2_hmax2\n\n\n# =============================================================================\n# MXFP8 Constants\n# =============================================================================\n\n# Scale factor vector size: each scale factor covers 32 elements\nSF_VEC_SIZE = 32\n\n# Inverse of max representable value in FP8 E4M3 format (1/448)\nINV_FLOAT8_E4M3_MAX = 1.0 / 448.0\n\n# Thread organization constants\nWARP_SIZE = 32\n\n# Default: optimized 2-thread-per-SF configuration for large problems\nELTS_PER_THREAD = 16 # Each thread handles 16 FP16 elements (2 × 128-bit loads)\nTHREADS_PER_SF = SF_VEC_SIZE // ELTS_PER_THREAD # 32 / 16 = 2 threads per SF block\nSF_BLOCKS_PER_WARP = WARP_SIZE // THREADS_PER_SF # 32 / 2 = 16 SF blocks per warp\n\n# Legacy: 4-thread-per-SF configuration for small problems (better grid occupancy)\nELTS_PER_THREAD_SMALL = 8\nTHREADS_PER_SF_SMALL = SF_VEC_SIZE // ELTS_PER_THREAD_SMALL # 32 / 8 = 4\nSF_BLOCKS_PER_WARP_SMALL = WARP_SIZE // THREADS_PER_SF_SMALL # 32 / 4 = 8\n\n# Threshold: use 2T/SF when total_sf_blocks >= this value (M*K >= 2M elements)\nMXFP8_2T_SF_THRESHOLD = 65536\n\n# Row tiling for swizzled layout (128x4 pattern)\nROW_TILE_SIZE = 128\n\n\n# =============================================================================\n# NVFP4 Constants\n# =============================================================================\n\n# Scale factor vector size for NVFP4: each scale factor covers 16 elements\nNVFP4_SF_VEC_SIZE = 16\n\n# =============================================================================\n# MXFP4 Constants\n# =============================================================================\n\n# Scale factor vector size for MXFP4: each scale factor covers 32 elements\nMXFP4_SF_VEC_SIZE = 32\n\n# Elements per thread for MXFP4: each thread handles 32 elements (one full SF block)\nMXFP4_ELTS_PER_THREAD = 32\n\n# Inverse of max representable value in FP4 E2M1 format (1/6)\nINV_FLOAT4_E2M1_MAX = 1.0 / 6.0\n\n# Global scale factor for MXFP4: 448 * 6 = 2688\nMXFP4_GLOBAL_SCALE_FACTOR = 448.0 * 6.0\n\n\n# =============================================================================\n# Half2 SIMD Intrinsics for Max Reduction\n# =============================================================================\n\n\n@dsl_user_op\ndef hmax_reduce_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 FP16 values in a Half2 as Float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $1;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax_reduce_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 BF16 values as Float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $1, 0xFFFF;\n shr.b32 hi, $1, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# Fast UE8M0 Conversion\n# =============================================================================\n\n\n@dsl_user_op\ndef float_to_ue8m0_fast(value: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"\n Convert float to UE8M0 format using exact IEEE 754 bit manipulation.\n\n Matches the hardware __nv_cvt_float_to_e8m0(value, __NV_SATFINITE, cudaRoundPosInf):\n - Extract biased exponent from IEEE 754 float\n - If mantissa is nonzero, add 1 (round towards +inf / ceil behavior)\n - Clamp to [0, 254] (255 = NaN in E8M0)\n - Return 0 for zero/negative input\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(value).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero, p_has_mant, p_ovf;\n .reg .u32 bits, exp_biased, mantissa, bump, result;\n\n setp.le.f32 p_zero, $1, 0f00000000;\n\n mov.b32 bits, $1;\n shr.b32 exp_biased, bits, 23;\n and.b32 exp_biased, exp_biased, 255;\n and.b32 mantissa, bits, 0x7FFFFF;\n\n setp.ne.u32 p_has_mant, mantissa, 0;\n selp.u32 bump, 1, 0, p_has_mant;\n add.u32 result, exp_biased, bump;\n\n setp.gt.u32 p_ovf, result, 254;\n selp.u32 result, 254, result, p_ovf;\n selp.u32 $0, 0, result, p_zero;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef ue8m0_to_inv_scale_fast(ue8m0_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"\n Convert UE8M0 to inverse scale using integer bit construction.\n\n Constructs a float32 with exponent = (254 - ue8m0) and zero mantissa,\n which is exactly 2^(127 - ue8m0). No SFU dependency.\n Returns 0 for ue8m0 == 0.\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(ue8m0_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .s32 new_exp;\n .reg .b32 float_bits;\n .reg .pred p_zero;\n\n setp.eq.u32 p_zero, $1, 0;\n sub.s32 new_exp, 254, $1;\n max.s32 new_exp, new_exp, 0;\n shl.b32 float_bits, new_exp, 23;\n mov.b32 $0, float_bits;\n @p_zero mov.b32 $0, 0;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# FP8 Conversion with Scaling\n# =============================================================================\n\n\n@dsl_user_op\ndef half2_to_fp8x2_scaled(\n h2: Uint32, inv_scale: Float32, *, loc=None, ip=None\n) -> Uint32:\n \"\"\"Convert Half2 to 2 FP8 E4M3 values with scaling.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Uint32(h2).ir_value(loc=loc, ip=ip),\n Float32(inv_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n .reg .b16 fp8_pair;\n\n mov.b32 {h0, h1}, $1;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n mul.f32 f0, f0, $2;\n mul.f32 f1, f1, $2;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, f1, f0;\n cvt.u32.u16 $0, fp8_pair;\n }\n \"\"\",\n \"=r,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_to_fp8x2_scaled(\n bf2: Uint32, inv_scale: Float32, *, loc=None, ip=None\n) -> Uint32:\n \"\"\"Convert BFloat16x2 to 2 FP8 E4M3 values with scaling.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Uint32(bf2).ir_value(loc=loc, ip=ip),\n Float32(inv_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n .reg .b16 fp8_pair;\n\n and.b32 lo, $1, 0xFFFF;\n shr.b32 hi, $1, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n mul.f32 f0, f0, $2;\n mul.f32 f1, f1, $2;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, f1, f0;\n cvt.u32.u16 $0, fp8_pair;\n }\n \"\"\",\n \"=r,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef pack_fp8x8_to_u64(\n fp8_01: Uint32, fp8_23: Uint32, fp8_45: Uint32, fp8_67: Uint32, *, loc=None, ip=None\n) -> Uint64:\n \"\"\"Pack 8 FP8 values into a 64-bit value for vectorized store.\"\"\"\n return Uint64(\n llvm.inline_asm(\n T.i64(),\n [\n Uint32(fp8_01).ir_value(loc=loc, ip=ip),\n Uint32(fp8_23).ir_value(loc=loc, ip=ip),\n Uint32(fp8_45).ir_value(loc=loc, ip=ip),\n Uint32(fp8_67).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .b32 t01, t23, t45, t67;\n\n and.b32 t01, $1, 0xFFFF;\n and.b32 t23, $2, 0xFFFF;\n and.b32 t45, $3, 0xFFFF;\n and.b32 t67, $4, 0xFFFF;\n\n shl.b32 t23, t23, 16;\n or.b32 lo, t01, t23;\n\n shl.b32 t67, t67, 16;\n or.b32 hi, t45, t67;\n\n mov.b64 $0, {lo, hi};\n }\n \"\"\",\n \"=l,r,r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# E2M1 (FP4) Conversion for MXFP4\n# =============================================================================\n\n\n@dsl_user_op\ndef half2_to_float2_scaled(\n h2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> tuple[Float32, Float32]:\n \"\"\"Convert Half2 to Float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(h2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $2;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n@dsl_user_op\ndef bfloat2_to_float2_scaled(\n bf2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> tuple[Float32, Float32]:\n \"\"\"Convert BFloat16x2 to Float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(bf2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $2, 0xFFFF;\n shr.b32 hi, $2, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n@dsl_user_op\ndef cvt_e2m1x8_f32(\n v0: Float32,\n v1: Float32,\n v2: Float32,\n v3: Float32,\n v4: Float32,\n v5: Float32,\n v6: Float32,\n v7: Float32,\n *,\n loc=None,\n ip=None,\n) -> Uint32:\n \"\"\"\n Convert eight float32 values to eight E2M1 (4-bit) values packed into uint32.\n\n Uses cvt.rn.satfinite.e2m1x2.f32 PTX instruction to convert pairs of f32\n to pairs of 4-bit E2M1 values, then packs all 8 values into a single u32.\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n Float32(v2).ir_value(loc=loc, ip=ip),\n Float32(v3).ir_value(loc=loc, ip=ip),\n Float32(v4).ir_value(loc=loc, ip=ip),\n Float32(v5).ir_value(loc=loc, ip=ip),\n Float32(v6).ir_value(loc=loc, ip=ip),\n Float32(v7).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 byte0, byte1, byte2, byte3;\n cvt.rn.satfinite.e2m1x2.f32 byte0, $2, $1;\n cvt.rn.satfinite.e2m1x2.f32 byte1, $4, $3;\n cvt.rn.satfinite.e2m1x2.f32 byte2, $6, $5;\n cvt.rn.satfinite.e2m1x2.f32 byte3, $8, $7;\n mov.b32 $0, {byte0, byte1, byte2, byte3};\n }\n \"\"\",\n \"=r,f,f,f,f,f,f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Warp Shuffle for 4-Thread Reduction\n# =============================================================================\n\n\n@cute.jit\ndef shuffle_xor_f32(val: Float32, offset: int) -> Float32:\n \"\"\"XOR shuffle for float32 values.\"\"\"\n return cute.arch.shuffle_sync_bfly(val, offset=offset)\n\n\n@cute.jit\ndef reduce_max_2threads(val: Float32) -> Float32:\n \"\"\"Reduce max across 2 consecutive threads using 1 XOR shuffle.\"\"\"\n from ..cute_dsl.fp4_common import fmax_f32\n\n other = shuffle_xor_f32(val, 1)\n val = fmax_f32(val, other)\n return val\n\n\n@cute.jit\ndef reduce_max_4threads(val: Float32) -> Float32:\n \"\"\"Reduce max across 4 consecutive threads using 2 XOR shuffles.\n\n Kept for backward compatibility with MXFP4 kernels.\n \"\"\"\n from ..cute_dsl.fp4_common import fmax_f32\n\n other = shuffle_xor_f32(val, 1)\n val = fmax_f32(val, other)\n other = shuffle_xor_f32(val, 2)\n val = fmax_f32(val, other)\n return val\n\n\n# =============================================================================\n# Swizzled Index Computation (GPU-side)\n# =============================================================================\n\n\n@cute.jit\ndef compute_sf_index_swizzled_128x4_gpu(\n row_idx: Int32,\n col_idx: Int32,\n padded_cols: Int32,\n) -> Int32:\n \"\"\"Compute swizzled 128x4 scale factor index on GPU.\"\"\"\n kColumnGroup0Size = Int32(4)\n kRowGroup0Size = Int32(32)\n kRowGroup1Size = Int32(128)\n\n columnIdxInGroup0 = col_idx % kColumnGroup0Size\n columnGroupIdx = col_idx // kColumnGroup0Size\n columnGroupStride = Int32(512)\n\n rowIdxInGroup0 = row_idx % kRowGroup0Size\n rowIdxInGroup1 = (row_idx % kRowGroup1Size) // kRowGroup0Size\n rowGroupIdx = row_idx // kRowGroup1Size\n\n rowGroup1Stride = Int32(4)\n rowGroup0Stride = Int32(16)\n rowGroupStride = kRowGroup1Size * padded_cols\n\n offset = (\n columnIdxInGroup0\n + columnGroupIdx * columnGroupStride\n + rowIdxInGroup0 * rowGroup0Stride\n + rowIdxInGroup1 * rowGroup1Stride\n + rowGroupIdx * rowGroupStride\n )\n\n return offset\n\n\n@cute.jit\ndef compute_sf_index_swizzled_8x4_gpu(\n row_idx: Int32,\n col_idx: Int32,\n padded_cols: Int32,\n) -> Int32:\n \"\"\"Compute swizzled 8x4 scale factor index on GPU.\n\n Layout: [numMTiles, numKTiles, 8 (mTile), 4 (kTile)]\n Tile size: 32 elements (8 rows x 4 cols).\n \"\"\"\n kMTileSize = Int32(8)\n kKTileSize = Int32(4)\n kTileElements = Int32(32)\n\n innerKIdx = col_idx % kKTileSize\n innerMIdx = row_idx % kMTileSize\n kTileIdx = col_idx // kKTileSize\n mTileIdx = row_idx // kMTileSize\n\n numKTiles = (padded_cols + kKTileSize - Int32(1)) // kKTileSize\n\n offset = (\n mTileIdx * (numKTiles * kTileElements)\n + kTileIdx * kTileElements\n + innerMIdx * kKTileSize\n + innerKIdx\n )\n\n return offset\n\n\n@cute.jit\ndef compute_sf_index_linear_gpu(\n row_idx: Int32,\n col_idx: Int32,\n num_cols: Int32,\n) -> Int32:\n \"\"\"Compute linear (row-major) scale factor index on GPU.\"\"\"\n return row_idx * num_cols + col_idx\n\n\n# =============================================================================\n# High-Level Helper Functions for MXFP8 Quantization\n# =============================================================================\n\n\n@cute.jit\ndef half2_max_abs_4(v0: Uint32, v1: Uint32, v2: Uint32, v3: Uint32) -> Uint32:\n \"\"\"\n Compute max absolute value across 4 half2 values (8 FP16 elements).\n\n Uses tree reduction: 4 -> 2 -> 1 half2 values.\n Returns a half2 containing the max absolute value in both lanes.\n \"\"\"\n abs0 = habs2(v0)\n abs1 = habs2(v1)\n abs2 = habs2(v2)\n abs3 = habs2(v3)\n max01 = hmax2(abs0, abs1)\n max23 = hmax2(abs2, abs3)\n return hmax2(max01, max23)\n\n\n@cute.jit\ndef bfloat2_max_abs_4(v0: Uint32, v1: Uint32, v2: Uint32, v3: Uint32) -> Uint32:\n \"\"\"\n Compute max absolute value across 4 bfloat2 values (8 BF16 elements).\n\n Uses tree reduction: 4 -> 2 -> 1 bfloat2 values.\n Returns a bfloat2 containing the max absolute value in both lanes.\n \"\"\"\n abs0 = bfloat2_habs2(v0)\n abs1 = bfloat2_habs2(v1)\n abs2 = bfloat2_habs2(v2)\n abs3 = bfloat2_habs2(v3)\n max01 = bfloat2_hmax2(abs0, abs1)\n max23 = bfloat2_hmax2(abs2, abs3)\n return bfloat2_hmax2(max01, max23)\n\n\n@cute.jit\ndef half2x4_to_fp8x8_packed(\n v0: Uint32, v1: Uint32, v2: Uint32, v3: Uint32, inv_scale: Float32\n) -> Uint64:\n \"\"\"\n Convert 4 half2 values (8 FP16) to 8 FP8 E4M3 and pack into u64.\n\n Each half2 is converted to 2 FP8 values using the inverse scale,\n then all 8 FP8 values are packed into a single 64-bit value for\n efficient vectorized store.\n \"\"\"\n fp8_01 = half2_to_fp8x2_scaled(v0, inv_scale)\n fp8_23 = half2_to_fp8x2_scaled(v1, inv_scale)\n fp8_45 = half2_to_fp8x2_scaled(v2, inv_scale)\n fp8_67 = half2_to_fp8x2_scaled(v3, inv_scale)\n return pack_fp8x8_to_u64(fp8_01, fp8_23, fp8_45, fp8_67)\n\n\n@cute.jit\ndef bfloat2x4_to_fp8x8_packed(\n v0: Uint32, v1: Uint32, v2: Uint32, v3: Uint32, inv_scale: Float32\n) -> Uint64:\n \"\"\"\n Convert 4 bfloat2 values (8 BF16) to 8 FP8 E4M3 and pack into u64.\n\n Each bfloat2 is converted to 2 FP8 values using the inverse scale,\n then all 8 FP8 values are packed into a single 64-bit value for\n efficient vectorized store.\n \"\"\"\n fp8_01 = bfloat2_to_fp8x2_scaled(v0, inv_scale)\n fp8_23 = bfloat2_to_fp8x2_scaled(v1, inv_scale)\n fp8_45 = bfloat2_to_fp8x2_scaled(v2, inv_scale)\n fp8_67 = bfloat2_to_fp8x2_scaled(v3, inv_scale)\n return pack_fp8x8_to_u64(fp8_01, fp8_23, fp8_45, fp8_67)\n\n\n# =============================================================================\n# MXFP4 High-Level Helper Functions\n# =============================================================================\n\n\n@cute.jit\ndef half2_max_abs_8(\n v0: Uint32,\n v1: Uint32,\n v2: Uint32,\n v3: Uint32,\n v4: Uint32,\n v5: Uint32,\n v6: Uint32,\n v7: Uint32,\n) -> Uint32:\n \"\"\"\n Compute max absolute value across 8 half2 values (16 FP16 elements).\n\n Uses tree reduction: 8 -> 4 -> 2 -> 1 half2 values.\n Returns a half2 containing the max absolute value in both lanes.\n \"\"\"\n abs0 = habs2(v0)\n abs1 = habs2(v1)\n abs2 = habs2(v2)\n abs3 = habs2(v3)\n abs4 = habs2(v4)\n abs5 = habs2(v5)\n abs6 = habs2(v6)\n abs7 = habs2(v7)\n\n max01 = hmax2(abs0, abs1)\n max23 = hmax2(abs2, abs3)\n max45 = hmax2(abs4, abs5)\n max67 = hmax2(abs6, abs7)\n\n max0123 = hmax2(max01, max23)\n max4567 = hmax2(max45, max67)\n\n return hmax2(max0123, max4567)\n\n\n@cute.jit\ndef bfloat2_max_abs_8(\n v0: Uint32,\n v1: Uint32,\n v2: Uint32,\n v3: Uint32,\n v4: Uint32,\n v5: Uint32,\n v6: Uint32,\n v7: Uint32,\n) -> Uint32:\n \"\"\"\n Compute max absolute value across 8 bfloat2 values (16 BF16 elements).\n\n Uses tree reduction: 8 -> 4 -> 2 -> 1 bfloat2 values.\n Returns a bfloat2 containing the max absolute value in both lanes.\n \"\"\"\n abs0 = bfloat2_habs2(v0)\n abs1 = bfloat2_habs2(v1)\n abs2 = bfloat2_habs2(v2)\n abs3 = bfloat2_habs2(v3)\n abs4 = bfloat2_habs2(v4)\n abs5 = bfloat2_habs2(v5)\n abs6 = bfloat2_habs2(v6)\n abs7 = bfloat2_habs2(v7)\n\n max01 = bfloat2_hmax2(abs0, abs1)\n max23 = bfloat2_hmax2(abs2, abs3)\n max45 = bfloat2_hmax2(abs4, abs5)\n max67 = bfloat2_hmax2(abs6, abs7)\n\n max0123 = bfloat2_hmax2(max01, max23)\n max4567 = bfloat2_hmax2(max45, max67)\n\n return bfloat2_hmax2(max0123, max4567)\n\n\n@cute.jit\ndef process_mxfp4_block_half(row_tensor, elem_base: Int32) -> tuple:\n \"\"\"\n Process a 32-element MXFP4 block for half precision input.\n\n Loads 32 FP16 elements, computes the UE8M0 scale factor, converts to E2M1,\n and packs the result into two u64 values.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n\n Returns:\n (scale_ue8m0_u32, scale_ue8m0_u8, packed64_0, packed64_1):\n - scale_ue8m0_u32: Scale factor as Uint32 (for inv_scale computation)\n - scale_ue8m0_u8: Scale factor as Uint8 (for storage)\n - packed64_0, packed64_1: Two Uint64 containing 16 E2M1 values each\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n get_ptr_as_int64,\n hmax2,\n ld_global_v4_u32,\n rcp_approx_ftz,\n )\n\n # Load 32 elements (4 x 128-bit = 16 half2 values)\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n ptr2 = get_ptr_as_int64(row_tensor, elem_base + Int32(16))\n ptr3 = get_ptr_as_int64(row_tensor, elem_base + Int32(24))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n h8, h9, h10, h11 = ld_global_v4_u32(ptr2)\n h12, h13, h14, h15 = ld_global_v4_u32(ptr3)\n\n # Compute max absolute value across 32 elements\n max_first = half2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n max_second = half2_max_abs_8(h8, h9, h10, h11, h12, h13, h14, h15)\n block_max_h2 = hmax2(max_first, max_second)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n # Compute UE8M0 scale factor (rcp_approx matches CUDA's rcp.approx.ftz(6.0f))\n normalized_max = block_max * rcp_approx_ftz(Float32(6.0))\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0_u8 = scale_ue8m0_u32.to(Uint8)\n\n # Compute inverse scale and convert to E2M1 packed format\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n packed64_0, packed64_1 = half2x16_to_e2m1x32_packed(\n h0,\n h1,\n h2,\n h3,\n h4,\n h5,\n h6,\n h7,\n h8,\n h9,\n h10,\n h11,\n h12,\n h13,\n h14,\n h15,\n inv_scale,\n )\n\n return scale_ue8m0_u32, scale_ue8m0_u8, packed64_0, packed64_1\n\n\n@cute.jit\ndef process_mxfp4_block_bfloat(row_tensor, elem_base: Int32) -> tuple:\n \"\"\"\n Process a 32-element MXFP4 block for bfloat16 precision input.\n\n Loads 32 BF16 elements, computes the UE8M0 scale factor, converts to E2M1,\n and packs the result into two u64 values.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n\n Returns:\n (scale_ue8m0_u32, scale_ue8m0_u8, packed64_0, packed64_1):\n - scale_ue8m0_u32: Scale factor as Uint32 (for inv_scale computation)\n - scale_ue8m0_u8: Scale factor as Uint8 (for storage)\n - packed64_0, packed64_1: Two Uint64 containing 16 E2M1 values each\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n bfloat2_hmax2,\n get_ptr_as_int64,\n ld_global_v4_u32,\n rcp_approx_ftz,\n )\n\n # Load 32 elements (4 x 128-bit = 16 bfloat2 values)\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n ptr2 = get_ptr_as_int64(row_tensor, elem_base + Int32(16))\n ptr3 = get_ptr_as_int64(row_tensor, elem_base + Int32(24))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n h8, h9, h10, h11 = ld_global_v4_u32(ptr2)\n h12, h13, h14, h15 = ld_global_v4_u32(ptr3)\n\n # Compute max absolute value across 32 elements\n max_first = bfloat2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n max_second = bfloat2_max_abs_8(h8, h9, h10, h11, h12, h13, h14, h15)\n block_max_h2 = bfloat2_hmax2(max_first, max_second)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n\n # Compute UE8M0 scale factor (rcp_approx matches CUDA's rcp.approx.ftz(6.0f))\n normalized_max = block_max * rcp_approx_ftz(Float32(6.0))\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0_u8 = scale_ue8m0_u32.to(Uint8)\n\n # Compute inverse scale and convert to E2M1 packed format\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n packed64_0, packed64_1 = bfloat2x16_to_e2m1x32_packed(\n h0,\n h1,\n h2,\n h3,\n h4,\n h5,\n h6,\n h7,\n h8,\n h9,\n h10,\n h11,\n h12,\n h13,\n h14,\n h15,\n inv_scale,\n )\n\n return scale_ue8m0_u32, scale_ue8m0_u8, packed64_0, packed64_1\n\n\n@cute.jit\ndef ld_32_elements(row_tensor, elem_base: Int32) -> tuple:\n \"\"\"\n Load 32 elements (16 half2/bfloat2 values) from a row tensor.\n\n This loads 4 x 128-bit vectors (4 x v4_u32) starting at elem_base.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n\n Returns:\n Tuple of 16 Uint32 values (h0-h15), each containing 2 fp16/bf16 elements\n \"\"\"\n from ..cute_dsl.fp4_common import get_ptr_as_int64, ld_global_v4_u32\n\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n ptr2 = get_ptr_as_int64(row_tensor, elem_base + Int32(16))\n ptr3 = get_ptr_as_int64(row_tensor, elem_base + Int32(24))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0) # Elements 0-7\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1) # Elements 8-15\n h8, h9, h10, h11 = ld_global_v4_u32(ptr2) # Elements 16-23\n h12, h13, h14, h15 = ld_global_v4_u32(ptr3) # Elements 24-31\n\n return h0, h1, h2, h3, h4, h5, h6, h7, h8, h9, h10, h11, h12, h13, h14, h15\n\n\n@cute.jit\ndef half2x16_to_e2m1x32_packed(\n h0: Uint32,\n h1: Uint32,\n h2: Uint32,\n h3: Uint32,\n h4: Uint32,\n h5: Uint32,\n h6: Uint32,\n h7: Uint32,\n h8: Uint32,\n h9: Uint32,\n h10: Uint32,\n h11: Uint32,\n h12: Uint32,\n h13: Uint32,\n h14: Uint32,\n h15: Uint32,\n inv_scale: Float32,\n) -> tuple:\n \"\"\"\n Convert 16 half2 values (32 FP16) to 32 E2M1 and pack into two u64.\n\n Each half2 is converted to 2 float32 values using inv_scale,\n then groups of 8 floats are converted to 8 E2M1 values packed into u32,\n and finally combined into two u64 values for vectorized store.\n\n Returns:\n (packed64_0, packed64_1): Two Uint64 containing 16 E2M1 values each\n \"\"\"\n # Scale and convert each half2 to 2 float32\n s0, s1 = half2_to_float2_scaled(h0, inv_scale)\n s2, s3 = half2_to_float2_scaled(h1, inv_scale)\n s4, s5 = half2_to_float2_scaled(h2, inv_scale)\n s6, s7 = half2_to_float2_scaled(h3, inv_scale)\n s8, s9 = half2_to_float2_scaled(h4, inv_scale)\n s10, s11 = half2_to_float2_scaled(h5, inv_scale)\n s12, s13 = half2_to_float2_scaled(h6, inv_scale)\n s14, s15 = half2_to_float2_scaled(h7, inv_scale)\n s16, s17 = half2_to_float2_scaled(h8, inv_scale)\n s18, s19 = half2_to_float2_scaled(h9, inv_scale)\n s20, s21 = half2_to_float2_scaled(h10, inv_scale)\n s22, s23 = half2_to_float2_scaled(h11, inv_scale)\n s24, s25 = half2_to_float2_scaled(h12, inv_scale)\n s26, s27 = half2_to_float2_scaled(h13, inv_scale)\n s28, s29 = half2_to_float2_scaled(h14, inv_scale)\n s30, s31 = half2_to_float2_scaled(h15, inv_scale)\n\n # Convert to E2M1 (4 x 8 floats -> 4 x uint32)\n packed0 = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed1 = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n packed2 = cvt_e2m1x8_f32(s16, s17, s18, s19, s20, s21, s22, s23)\n packed3 = cvt_e2m1x8_f32(s24, s25, s26, s27, s28, s29, s30, s31)\n\n # Pack into 2 x 64-bit values\n packed64_0 = (Uint64(packed1) << Uint64(32)) | Uint64(packed0)\n packed64_1 = (Uint64(packed3) << Uint64(32)) | Uint64(packed2)\n\n return packed64_0, packed64_1\n\n\n@cute.jit\ndef bfloat2x16_to_e2m1x32_packed(\n h0: Uint32,\n h1: Uint32,\n h2: Uint32,\n h3: Uint32,\n h4: Uint32,\n h5: Uint32,\n h6: Uint32,\n h7: Uint32,\n h8: Uint32,\n h9: Uint32,\n h10: Uint32,\n h11: Uint32,\n h12: Uint32,\n h13: Uint32,\n h14: Uint32,\n h15: Uint32,\n inv_scale: Float32,\n) -> tuple:\n \"\"\"\n Convert 16 bfloat2 values (32 BF16) to 32 E2M1 and pack into two u64.\n\n Each bfloat2 is converted to 2 float32 values using inv_scale,\n then groups of 8 floats are converted to 8 E2M1 values packed into u32,\n and finally combined into two u64 values for vectorized store.\n\n Returns:\n (packed64_0, packed64_1): Two Uint64 containing 16 E2M1 values each\n \"\"\"\n # Scale and convert each bfloat2 to 2 float32\n s0, s1 = bfloat2_to_float2_scaled(h0, inv_scale)\n s2, s3 = bfloat2_to_float2_scaled(h1, inv_scale)\n s4, s5 = bfloat2_to_float2_scaled(h2, inv_scale)\n s6, s7 = bfloat2_to_float2_scaled(h3, inv_scale)\n s8, s9 = bfloat2_to_float2_scaled(h4, inv_scale)\n s10, s11 = bfloat2_to_float2_scaled(h5, inv_scale)\n s12, s13 = bfloat2_to_float2_scaled(h6, inv_scale)\n s14, s15 = bfloat2_to_float2_scaled(h7, inv_scale)\n s16, s17 = bfloat2_to_float2_scaled(h8, inv_scale)\n s18, s19 = bfloat2_to_float2_scaled(h9, inv_scale)\n s20, s21 = bfloat2_to_float2_scaled(h10, inv_scale)\n s22, s23 = bfloat2_to_float2_scaled(h11, inv_scale)\n s24, s25 = bfloat2_to_float2_scaled(h12, inv_scale)\n s26, s27 = bfloat2_to_float2_scaled(h13, inv_scale)\n s28, s29 = bfloat2_to_float2_scaled(h14, inv_scale)\n s30, s31 = bfloat2_to_float2_scaled(h15, inv_scale)\n\n # Convert to E2M1 (4 x 8 floats -> 4 x uint32)\n packed0 = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed1 = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n packed2 = cvt_e2m1x8_f32(s16, s17, s18, s19, s20, s21, s22, s23)\n packed3 = cvt_e2m1x8_f32(s24, s25, s26, s27, s28, s29, s30, s31)\n\n # Pack into 2 x 64-bit values\n packed64_0 = (Uint64(packed1) << Uint64(32)) | Uint64(packed0)\n packed64_1 = (Uint64(packed3) << Uint64(32)) | Uint64(packed2)\n\n return packed64_0, packed64_1\n\n\n# =============================================================================\n# NVFP4 High-Level Helper Functions (sf_vec_size=16, E4M3 scale factors)\n# =============================================================================\n\n\n@cute.jit\ndef half2x8_to_e2m1x16_packed(\n h0: Uint32,\n h1: Uint32,\n h2: Uint32,\n h3: Uint32,\n h4: Uint32,\n h5: Uint32,\n h6: Uint32,\n h7: Uint32,\n inv_scale: Float32,\n) -> Uint64:\n \"\"\"\n Convert 8 half2 values (16 FP16) to 16 E2M1 and pack into u64.\n\n Returns:\n Uint64 containing 16 E2M1 values (8 bytes)\n \"\"\"\n s0, s1 = half2_to_float2_scaled(h0, inv_scale)\n s2, s3 = half2_to_float2_scaled(h1, inv_scale)\n s4, s5 = half2_to_float2_scaled(h2, inv_scale)\n s6, s7 = half2_to_float2_scaled(h3, inv_scale)\n s8, s9 = half2_to_float2_scaled(h4, inv_scale)\n s10, s11 = half2_to_float2_scaled(h5, inv_scale)\n s12, s13 = half2_to_float2_scaled(h6, inv_scale)\n s14, s15 = half2_to_float2_scaled(h7, inv_scale)\n\n packed_lo = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed_hi = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n@cute.jit\ndef bfloat2x8_to_e2m1x16_packed(\n h0: Uint32,\n h1: Uint32,\n h2: Uint32,\n h3: Uint32,\n h4: Uint32,\n h5: Uint32,\n h6: Uint32,\n h7: Uint32,\n inv_scale: Float32,\n) -> Uint64:\n \"\"\"\n Convert 8 bfloat2 values (16 BF16) to 16 E2M1 and pack into u64.\n\n Returns:\n Uint64 containing 16 E2M1 values (8 bytes)\n \"\"\"\n s0, s1 = bfloat2_to_float2_scaled(h0, inv_scale)\n s2, s3 = bfloat2_to_float2_scaled(h1, inv_scale)\n s4, s5 = bfloat2_to_float2_scaled(h2, inv_scale)\n s6, s7 = bfloat2_to_float2_scaled(h3, inv_scale)\n s8, s9 = bfloat2_to_float2_scaled(h4, inv_scale)\n s10, s11 = bfloat2_to_float2_scaled(h5, inv_scale)\n s12, s13 = bfloat2_to_float2_scaled(h6, inv_scale)\n s14, s15 = bfloat2_to_float2_scaled(h7, inv_scale)\n\n packed_lo = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed_hi = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n@cute.jit\ndef process_nvfp4_block_half(\n row_tensor, elem_base: Int32, global_scale: Float32\n) -> tuple:\n \"\"\"\n Process a 16-element NVFP4 block for half precision input.\n\n Loads 16 FP16 elements, computes the E4M3 scale factor using global_scale,\n converts to E2M1, and packs the result into a u64 value.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n global_scale: User-provided global scale factor\n\n Returns:\n (scale_e4m3_u8, packed64):\n - scale_e4m3_u8: E4M3 scale factor as Uint8\n - packed64: Uint64 containing 16 E2M1 values\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n cvt_f32_to_e4m3,\n get_ptr_as_int64,\n ld_global_v4_u32,\n nvfp4_compute_output_scale,\n rcp_approx_ftz,\n )\n\n # Load 16 elements (2 x 128-bit = 8 half2 values)\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n\n # Compute max absolute value across 16 elements\n block_max_h2 = half2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n # E4M3 scale factor computation\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n\n # output_scale = rcp(float(E4M3(scale)) * rcp(global_scale)), matching CUDA\n output_scale = nvfp4_compute_output_scale(scale_fp8_u32, global_scale)\n\n # Convert to E2M1 and pack\n packed64 = half2x8_to_e2m1x16_packed(h0, h1, h2, h3, h4, h5, h6, h7, output_scale)\n\n return scale_fp8, packed64\n\n\n@cute.jit\ndef process_nvfp4_block_bfloat(\n row_tensor, elem_base: Int32, global_scale: Float32\n) -> tuple:\n \"\"\"\n Process a 16-element NVFP4 block for bfloat16 precision input.\n\n Loads 16 BF16 elements, computes the E4M3 scale factor using global_scale,\n converts to E2M1, and packs the result into a u64 value.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n global_scale: User-provided global scale factor\n\n Returns:\n (scale_e4m3_u8, packed64):\n - scale_e4m3_u8: E4M3 scale factor as Uint8\n - packed64: Uint64 containing 16 E2M1 values\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n cvt_f32_to_e4m3,\n get_ptr_as_int64,\n ld_global_v4_u32,\n nvfp4_compute_output_scale,\n rcp_approx_ftz,\n )\n\n # Load 16 elements (2 x 128-bit = 8 bfloat2 values)\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n\n # Compute max absolute value across 16 elements\n block_max_h2 = bfloat2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n\n # E4M3 scale factor computation\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n\n # output_scale = rcp(float(E4M3(scale)) * rcp(global_scale)), matching CUDA\n output_scale = nvfp4_compute_output_scale(scale_fp8_u32, global_scale)\n\n # Convert to E2M1 and pack\n packed64 = bfloat2x8_to_e2m1x16_packed(h0, h1, h2, h3, h4, h5, h6, h7, output_scale)\n\n return scale_fp8, packed64\n\n\n@cute.jit\ndef fp8x16_to_e2m1x16_packed(\n w0: Uint32,\n w1: Uint32,\n w2: Uint32,\n w3: Uint32,\n output_scale: Float32,\n) -> Uint64:\n \"\"\"Convert 16 packed FP8 E4M3 values (4 x uint32) to 16 E2M1 values packed as Uint64.\n\n Each uint32 contains 4 E4M3 bytes. Output is 16 E2M1 nibbles packed into 8 bytes.\n \"\"\"\n from ..cute_dsl.fp4_common import cvt_e4m3x4_to_f32x4\n\n f0, f1, f2, f3 = cvt_e4m3x4_to_f32x4(w0)\n f4, f5, f6, f7 = cvt_e4m3x4_to_f32x4(w1)\n f8, f9, f10, f11 = cvt_e4m3x4_to_f32x4(w2)\n f12, f13, f14, f15 = cvt_e4m3x4_to_f32x4(w3)\n\n s0 = f0 * output_scale\n s1 = f1 * output_scale\n s2 = f2 * output_scale\n s3 = f3 * output_scale\n s4 = f4 * output_scale\n s5 = f5 * output_scale\n s6 = f6 * output_scale\n s7 = f7 * output_scale\n s8 = f8 * output_scale\n s9 = f9 * output_scale\n s10 = f10 * output_scale\n s11 = f11 * output_scale\n s12 = f12 * output_scale\n s13 = f13 * output_scale\n s14 = f14 * output_scale\n s15 = f15 * output_scale\n\n packed_lo = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed_hi = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n@cute.jit\ndef fp8_max_abs_16(w0: Uint32, w1: Uint32, w2: Uint32, w3: Uint32) -> Float32:\n \"\"\"Compute max absolute value across 16 FP8 E4M3 values (4 x uint32).\n\n Converts all 16 values to float32, takes abs, and reduces to a single max.\n \"\"\"\n from ..cute_dsl.fp4_common import cvt_e4m3x4_to_f32x4\n\n f0, f1, f2, f3 = cvt_e4m3x4_to_f32x4(w0)\n f4, f5, f6, f7 = cvt_e4m3x4_to_f32x4(w1)\n f8, f9, f10, f11 = cvt_e4m3x4_to_f32x4(w2)\n f12, f13, f14, f15 = cvt_e4m3x4_to_f32x4(w3)\n\n from ..cute_dsl.fp4_common import fabs_f32, fmax_f32\n\n a0 = fabs_f32(f0)\n a1 = fabs_f32(f1)\n a2 = fabs_f32(f2)\n a3 = fabs_f32(f3)\n a4 = fabs_f32(f4)\n a5 = fabs_f32(f5)\n a6 = fabs_f32(f6)\n a7 = fabs_f32(f7)\n a8 = fabs_f32(f8)\n a9 = fabs_f32(f9)\n a10 = fabs_f32(f10)\n a11 = fabs_f32(f11)\n a12 = fabs_f32(f12)\n a13 = fabs_f32(f13)\n a14 = fabs_f32(f14)\n a15 = fabs_f32(f15)\n\n m01 = fmax_f32(a0, a1)\n m23 = fmax_f32(a2, a3)\n m45 = fmax_f32(a4, a5)\n m67 = fmax_f32(a6, a7)\n m89 = fmax_f32(a8, a9)\n m1011 = fmax_f32(a10, a11)\n m1213 = fmax_f32(a12, a13)\n m1415 = fmax_f32(a14, a15)\n\n m0123 = fmax_f32(m01, m23)\n m4567 = fmax_f32(m45, m67)\n m891011 = fmax_f32(m89, m1011)\n m12131415 = fmax_f32(m1213, m1415)\n\n m_lo = fmax_f32(m0123, m4567)\n m_hi = fmax_f32(m891011, m12131415)\n\n return fmax_f32(m_lo, m_hi)\n\n\n@cute.jit\ndef process_nvfp4_block_fp8(\n row_tensor, elem_base: Int32, global_scale: Float32\n) -> tuple:\n \"\"\"\n Process a 16-element NVFP4 block for FP8 E4M3 input.\n\n Matches the CUDA cvt_warp_fp8_to_fp4 behavior: FP8 values are first converted\n to float32, pre-scaled by 6/global_scale, and converted to half2. From there,\n the standard half2 pipeline is used for max-abs reduction, scale factor\n computation, and E2M1 conversion.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n global_scale: User-provided global scale factor\n\n Returns:\n (scale_e4m3_u8, packed64):\n - scale_e4m3_u8: E4M3 scale factor as Uint8\n - packed64: Uint64 containing 16 E2M1 values\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n cvt_e4m3x4_to_f32x4,\n cvt_f32_to_e4m3,\n cvt_f32x2_to_half2,\n get_ptr_as_int64,\n ld_global_v4_u32,\n nvfp4_compute_output_scale,\n rcp_approx_ftz,\n )\n\n # Load 16 FP8 elements (1 x 128-bit = 4 x uint32 = 16 bytes)\n ptr = get_ptr_as_int64(row_tensor, elem_base)\n w0, w1, w2, w3 = ld_global_v4_u32(ptr)\n\n # Convert FP8 to float32 and pre-scale by 6/global_scale (matching CUDA)\n prescale = Float32(6.0) * rcp_approx_ftz(global_scale)\n\n f0, f1, f2, f3 = cvt_e4m3x4_to_f32x4(w0)\n f4, f5, f6, f7 = cvt_e4m3x4_to_f32x4(w1)\n f8, f9, f10, f11 = cvt_e4m3x4_to_f32x4(w2)\n f12, f13, f14, f15 = cvt_e4m3x4_to_f32x4(w3)\n\n # Pack pre-scaled float pairs into half2 (matching __float22half2_rn in CUDA)\n h0 = cvt_f32x2_to_half2(f0 * prescale, f1 * prescale)\n h1 = cvt_f32x2_to_half2(f2 * prescale, f3 * prescale)\n h2 = cvt_f32x2_to_half2(f4 * prescale, f5 * prescale)\n h3 = cvt_f32x2_to_half2(f6 * prescale, f7 * prescale)\n h4 = cvt_f32x2_to_half2(f8 * prescale, f9 * prescale)\n h5 = cvt_f32x2_to_half2(f10 * prescale, f11 * prescale)\n h6 = cvt_f32x2_to_half2(f12 * prescale, f13 * prescale)\n h7 = cvt_f32x2_to_half2(f14 * prescale, f15 * prescale)\n\n # From here, use the same half2 pipeline as process_nvfp4_block_half\n block_max_h2 = half2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n # E4M3 scale factor computation\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n\n # output_scale = rcp(float(E4M3(scale)) * rcp(global_scale)), matching CUDA\n output_scale = nvfp4_compute_output_scale(scale_fp8_u32, global_scale)\n\n # Convert pre-scaled half2 values to E2M1 and pack\n packed64 = half2x8_to_e2m1x16_packed(h0, h1, h2, h3, h4, h5, h6, h7, output_scale)\n\n return scale_fp8, packed64\n\n\n__all__ = [\n # NVFP4 Constants\n \"NVFP4_SF_VEC_SIZE\",\n # MXFP8 Constants\n \"SF_VEC_SIZE\",\n \"INV_FLOAT8_E4M3_MAX\",\n \"WARP_SIZE\",\n \"ELTS_PER_THREAD\",\n \"THREADS_PER_SF\",\n \"SF_BLOCKS_PER_WARP\",\n \"ELTS_PER_THREAD_SMALL\",\n \"THREADS_PER_SF_SMALL\",\n \"SF_BLOCKS_PER_WARP_SMALL\",\n \"MXFP8_2T_SF_THRESHOLD\",\n \"ROW_TILE_SIZE\",\n # MXFP4 Constants\n \"MXFP4_SF_VEC_SIZE\",\n \"MXFP4_ELTS_PER_THREAD\",\n \"INV_FLOAT4_E2M1_MAX\",\n \"MXFP4_GLOBAL_SCALE_FACTOR\",\n # Low-level intrinsics (MXFP8)\n \"hmax_reduce_to_f32\",\n \"bfloat2_hmax_reduce_to_f32\",\n \"float_to_ue8m0_fast\",\n \"ue8m0_to_inv_scale_fast\",\n \"reduce_max_2threads\",\n \"reduce_max_4threads\",\n \"compute_sf_index_swizzled_128x4_gpu\",\n \"compute_sf_index_swizzled_8x4_gpu\",\n \"compute_sf_index_linear_gpu\",\n # Low-level intrinsics (MXFP4 - E2M1 conversion)\n \"half2_to_float2_scaled\",\n \"bfloat2_to_float2_scaled\",\n \"cvt_e2m1x8_f32\",\n # High-level helper functions (MXFP8)\n \"half2_max_abs_4\",\n \"bfloat2_max_abs_4\",\n \"half2x4_to_fp8x8_packed\",\n \"bfloat2x4_to_fp8x8_packed\",\n # High-level helper functions (MXFP4)\n \"half2_max_abs_8\",\n \"bfloat2_max_abs_8\",\n \"process_mxfp4_block_half\",\n \"process_mxfp4_block_bfloat\",\n \"ld_32_elements\",\n \"half2x16_to_e2m1x32_packed\",\n \"bfloat2x16_to_e2m1x32_packed\",\n # High-level helper functions (NVFP4)\n \"half2x8_to_e2m1x16_packed\",\n \"bfloat2x8_to_e2m1x16_packed\",\n \"process_nvfp4_block_half\",\n \"process_nvfp4_block_bfloat\",\n # High-level helper functions (NVFP4 - FP8 input)\n \"fp8x16_to_e2m1x16_packed\",\n \"fp8_max_abs_16\",\n \"process_nvfp4_block_fp8\",\n]\n"},"diff":{"kind":"string","value":"--- flashinfer/quantization/quantization_cute_dsl_utils.py\n+++ flashinfer/quantization/quantization_cute_dsl_utils.py\n@@ -39,9 +39,19 @@\n \n # Thread organization constants\n WARP_SIZE = 32\n-ELTS_PER_THREAD = 8 # Each thread handles 8 FP16 elements (128 bits)\n-THREADS_PER_SF = SF_VEC_SIZE // ELTS_PER_THREAD # 32 / 8 = 4 threads per SF block\n-SF_BLOCKS_PER_WARP = WARP_SIZE // THREADS_PER_SF # 32 / 4 = 8 SF blocks per warp\n+\n+# Default: optimized 2-thread-per-SF configuration for large problems\n+ELTS_PER_THREAD = 16 # Each thread handles 16 FP16 elements (2 × 128-bit loads)\n+THREADS_PER_SF = SF_VEC_SIZE // ELTS_PER_THREAD # 32 / 16 = 2 threads per SF block\n+SF_BLOCKS_PER_WARP = WARP_SIZE // THREADS_PER_SF # 32 / 2 = 16 SF blocks per warp\n+\n+# Legacy: 4-thread-per-SF configuration for small problems (better grid occupancy)\n+ELTS_PER_THREAD_SMALL = 8\n+THREADS_PER_SF_SMALL = SF_VEC_SIZE // ELTS_PER_THREAD_SMALL # 32 / 8 = 4\n+SF_BLOCKS_PER_WARP_SMALL = WARP_SIZE // THREADS_PER_SF_SMALL # 32 / 4 = 8\n+\n+# Threshold: use 2T/SF when total_sf_blocks >= this value (M*K >= 2M elements)\n+MXFP8_2T_SF_THRESHOLD = 65536\n \n # Row tiling for swizzled layout (128x4 pattern)\n ROW_TILE_SIZE = 128\n@@ -187,9 +197,10 @@\n @dsl_user_op\n def ue8m0_to_inv_scale_fast(ue8m0_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"\n- Convert UE8M0 to inverse scale using fast ex2.approx.\n-\n- Inverse scale = 2^(127 - ue8m0)\n+ Convert UE8M0 to inverse scale using integer bit construction.\n+\n+ Constructs a float32 with exponent = (254 - ue8m0) and zero mantissa,\n+ which is exactly 2^(127 - ue8m0). No SFU dependency.\n Returns 0 for ue8m0 == 0.\n \"\"\"\n return Float32(\n@@ -198,15 +209,16 @@\n [Uint32(ue8m0_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n+ .reg .s32 new_exp;\n+ .reg .b32 float_bits;\n .reg .pred p_zero;\n- .reg .s32 neg_exp;\n- .reg .f32 neg_exp_f, result;\n \n setp.eq.u32 p_zero, $1, 0;\n- sub.s32 neg_exp, 127, $1;\n- cvt.rn.f32.s32 neg_exp_f, neg_exp;\n- ex2.approx.f32 result, neg_exp_f;\n- selp.f32 $0, 0f00000000, result, p_zero;\n+ sub.s32 new_exp, 254, $1;\n+ max.s32 new_exp, new_exp, 0;\n+ shl.b32 float_bits, new_exp, 23;\n+ mov.b32 $0, float_bits;\n+ @p_zero mov.b32 $0, 0;\n }\n \"\"\",\n \"=f,r\",\n@@ -481,8 +493,21 @@\n \n \n @cute.jit\n+def reduce_max_2threads(val: Float32) -> Float32:\n+ \"\"\"Reduce max across 2 consecutive threads using 1 XOR shuffle.\"\"\"\n+ from ..cute_dsl.fp4_common import fmax_f32\n+\n+ other = shuffle_xor_f32(val, 1)\n+ val = fmax_f32(val, other)\n+ return val\n+\n+\n+@cute.jit\n def reduce_max_4threads(val: Float32) -> Float32:\n- \"\"\"Reduce max across 4 consecutive threads using 2 XOR shuffles.\"\"\"\n+ \"\"\"Reduce max across 4 consecutive threads using 2 XOR shuffles.\n+\n+ Kept for backward compatibility with MXFP4 kernels.\n+ \"\"\"\n from ..cute_dsl.fp4_common import fmax_f32\n \n other = shuffle_xor_f32(val, 1)\n@@ -1388,6 +1413,10 @@\n \"ELTS_PER_THREAD\",\n \"THREADS_PER_SF\",\n \"SF_BLOCKS_PER_WARP\",\n+ \"ELTS_PER_THREAD_SMALL\",\n+ \"THREADS_PER_SF_SMALL\",\n+ \"SF_BLOCKS_PER_WARP_SMALL\",\n+ \"MXFP8_2T_SF_THRESHOLD\",\n \"ROW_TILE_SIZE\",\n # MXFP4 Constants\n \"MXFP4_SF_VEC_SIZE\",\n@@ -1399,6 +1428,7 @@\n \"bfloat2_hmax_reduce_to_f32\",\n \"float_to_ue8m0_fast\",\n \"ue8m0_to_inv_scale_fast\",\n+ \"reduce_max_2threads\",\n \"reduce_max_4threads\",\n \"compute_sf_index_swizzled_128x4_gpu\",\n \"compute_sf_index_swizzled_8x4_gpu\","},"lines_added":{"kind":"number","value":43,"string":"43"},"lines_removed":{"kind":"number","value":13,"string":"13"},"files_in_commit":{"kind":"number","value":6,"string":"6"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200"],"string":"[\n \"B200\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["5x","1.42x","1.37x","1.41x","1.39x","1.34x","1.32x"],"string":"[\n \"5x\",\n \"1.42x\",\n \"1.37x\",\n \"1.41x\",\n \"1.39x\",\n \"1.34x\",\n \"1.32x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/quantization/quantization_cute_dsl_utils.py).\n\nGoal: perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels\nTarget hardware: B200\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nCommon utilities for quantization kernels using CuTe-DSL.\n\nThis module contains shared PTX intrinsics and helper functions for MXFP8\nand MXFP4 quantization kernels.\n\"\"\"\n\nimport cutlass.cute as cute\nfrom cutlass import Float32, Int32, Uint32, Uint64\nfrom cutlass._mlir.dialects import llvm\nfrom cutlass.cutlass_dsl import T, dsl_user_op\n\nfrom ..cute_dsl.fp4_common import habs2, hmax2, bfloat2_habs2, bfloat2_hmax2\n\n\n# =============================================================================\n# MXFP8 Constants\n# =============================================================================\n\n# Scale factor vector size: each scale factor covers 32 elements\nSF_VEC_SIZE = 32\n\n# Inverse of max representable value in FP8 E4M3 format (1/448)\nINV_FLOAT8_E4M3_MAX = 1.0 / 448.0\n\n# Thread organization constants\nWARP_SIZE = 32\nELTS_PER_THREAD = 8 # Each thread handles 8 FP16 elements (128 bits)\nTHREADS_PER_SF = SF_VEC_SIZE // ELTS_PER_THREAD # 32 / 8 = 4 threads per SF block\nSF_BLOCKS_PER_WARP = WARP_SIZE // THREADS_PER_SF # 32 / 4 = 8 SF blocks per warp\n\n# Row tiling for swizzled layout (128x4 pattern)\nROW_TILE_SIZE = 128\n\n\n# =============================================================================\n# NVFP4 Constants\n# =============================================================================\n\n# Scale factor vector size for NVFP4: each scale factor covers 16 elements\nNVFP4_SF_VEC_SIZE = 16\n\n# =============================================================================\n# MXFP4 Constants\n# =============================================================================\n\n# Scale factor vector size for MXFP4: each scale factor covers 32 elements\nMXFP4_SF_VEC_SIZE = 32\n\n# Elements per thread for MXFP4: each thread handles 32 elements (one full SF block)\nMXFP4_ELTS_PER_THREAD = 32\n\n# Inverse of max representable value in FP4 E2M1 format (1/6)\nINV_FLOAT4_E2M1_MAX = 1.0 / 6.0\n\n# Global scale factor for MXFP4: 448 * 6 = 2688\nMXFP4_GLOBAL_SCALE_FACTOR = 448.0 * 6.0\n\n\n# =============================================================================\n# Half2 SIMD Intrinsics for Max Reduction\n# =============================================================================\n\n\n@dsl_user_op\ndef hmax_reduce_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 FP16 values in a Half2 as Float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $1;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_hmax_reduce_to_f32(x: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"Extract max of 2 BF16 values as Float32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(x).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $1, 0xFFFF;\n shr.b32 hi, $1, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n max.f32 $0, f0, f1;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# Fast UE8M0 Conversion\n# =============================================================================\n\n\n@dsl_user_op\ndef float_to_ue8m0_fast(value: Float32, *, loc=None, ip=None) -> Uint32:\n \"\"\"\n Convert float to UE8M0 format using exact IEEE 754 bit manipulation.\n\n Matches the hardware __nv_cvt_float_to_e8m0(value, __NV_SATFINITE, cudaRoundPosInf):\n - Extract biased exponent from IEEE 754 float\n - If mantissa is nonzero, add 1 (round towards +inf / ceil behavior)\n - Clamp to [0, 254] (255 = NaN in E8M0)\n - Return 0 for zero/negative input\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [Float32(value).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero, p_has_mant, p_ovf;\n .reg .u32 bits, exp_biased, mantissa, bump, result;\n\n setp.le.f32 p_zero, $1, 0f00000000;\n\n mov.b32 bits, $1;\n shr.b32 exp_biased, bits, 23;\n and.b32 exp_biased, exp_biased, 255;\n and.b32 mantissa, bits, 0x7FFFFF;\n\n setp.ne.u32 p_has_mant, mantissa, 0;\n selp.u32 bump, 1, 0, p_has_mant;\n add.u32 result, exp_biased, bump;\n\n setp.gt.u32 p_ovf, result, 254;\n selp.u32 result, 254, result, p_ovf;\n selp.u32 $0, 0, result, p_zero;\n }\n \"\"\",\n \"=r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef ue8m0_to_inv_scale_fast(ue8m0_val: Uint32, *, loc=None, ip=None) -> Float32:\n \"\"\"\n Convert UE8M0 to inverse scale using fast ex2.approx.\n\n Inverse scale = 2^(127 - ue8m0)\n Returns 0 for ue8m0 == 0.\n \"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Uint32(ue8m0_val).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .pred p_zero;\n .reg .s32 neg_exp;\n .reg .f32 neg_exp_f, result;\n\n setp.eq.u32 p_zero, $1, 0;\n sub.s32 neg_exp, 127, $1;\n cvt.rn.f32.s32 neg_exp_f, neg_exp;\n ex2.approx.f32 result, neg_exp_f;\n selp.f32 $0, 0f00000000, result, p_zero;\n }\n \"\"\",\n \"=f,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# FP8 Conversion with Scaling\n# =============================================================================\n\n\n@dsl_user_op\ndef half2_to_fp8x2_scaled(\n h2: Uint32, inv_scale: Float32, *, loc=None, ip=None\n) -> Uint32:\n \"\"\"Convert Half2 to 2 FP8 E4M3 values with scaling.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Uint32(h2).ir_value(loc=loc, ip=ip),\n Float32(inv_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n .reg .b16 fp8_pair;\n\n mov.b32 {h0, h1}, $1;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n mul.f32 f0, f0, $2;\n mul.f32 f1, f1, $2;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, f1, f0;\n cvt.u32.u16 $0, fp8_pair;\n }\n \"\"\",\n \"=r,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef bfloat2_to_fp8x2_scaled(\n bf2: Uint32, inv_scale: Float32, *, loc=None, ip=None\n) -> Uint32:\n \"\"\"Convert BFloat16x2 to 2 FP8 E4M3 values with scaling.\"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Uint32(bf2).ir_value(loc=loc, ip=ip),\n Float32(inv_scale).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n .reg .b16 fp8_pair;\n\n and.b32 lo, $1, 0xFFFF;\n shr.b32 hi, $1, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n mul.f32 f0, f0, $2;\n mul.f32 f1, f1, $2;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, f1, f0;\n cvt.u32.u16 $0, fp8_pair;\n }\n \"\"\",\n \"=r,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n@dsl_user_op\ndef pack_fp8x8_to_u64(\n fp8_01: Uint32, fp8_23: Uint32, fp8_45: Uint32, fp8_67: Uint32, *, loc=None, ip=None\n) -> Uint64:\n \"\"\"Pack 8 FP8 values into a 64-bit value for vectorized store.\"\"\"\n return Uint64(\n llvm.inline_asm(\n T.i64(),\n [\n Uint32(fp8_01).ir_value(loc=loc, ip=ip),\n Uint32(fp8_23).ir_value(loc=loc, ip=ip),\n Uint32(fp8_45).ir_value(loc=loc, ip=ip),\n Uint32(fp8_67).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .b32 t01, t23, t45, t67;\n\n and.b32 t01, $1, 0xFFFF;\n and.b32 t23, $2, 0xFFFF;\n and.b32 t45, $3, 0xFFFF;\n and.b32 t67, $4, 0xFFFF;\n\n shl.b32 t23, t23, 16;\n or.b32 lo, t01, t23;\n\n shl.b32 t67, t67, 16;\n or.b32 hi, t45, t67;\n\n mov.b64 $0, {lo, hi};\n }\n \"\"\",\n \"=l,r,r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n )\n\n\n# =============================================================================\n# E2M1 (FP4) Conversion for MXFP4\n# =============================================================================\n\n\n@dsl_user_op\ndef half2_to_float2_scaled(\n h2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> tuple[Float32, Float32]:\n \"\"\"Convert Half2 to Float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(h2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 h0, h1;\n .reg .f32 f0, f1;\n mov.b32 {h0, h1}, $2;\n cvt.f32.f16 f0, h0;\n cvt.f32.f16 f1, h1;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n@dsl_user_op\ndef bfloat2_to_float2_scaled(\n bf2: Uint32, scale: Float32, *, loc=None, ip=None\n) -> tuple[Float32, Float32]:\n \"\"\"Convert BFloat16x2 to Float2 AND multiply by scale.\"\"\"\n result = llvm.inline_asm(\n llvm.StructType.get_literal([T.f32(), T.f32()]),\n [Uint32(bf2).ir_value(loc=loc, ip=ip), Float32(scale).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 lo, hi;\n .reg .f32 f0, f1;\n and.b32 lo, $2, 0xFFFF;\n shr.b32 hi, $2, 16;\n shl.b32 lo, lo, 16;\n shl.b32 hi, hi, 16;\n mov.b32 f0, lo;\n mov.b32 f1, hi;\n mul.f32 $0, f0, $3;\n mul.f32 $1, f1, $3;\n }\n \"\"\",\n \"=f,=f,r,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n loc=loc,\n ip=ip,\n )\n\n f0 = llvm.extractvalue(T.f32(), result, [0], loc=loc, ip=ip)\n f1 = llvm.extractvalue(T.f32(), result, [1], loc=loc, ip=ip)\n\n return Float32(f0), Float32(f1)\n\n\n@dsl_user_op\ndef cvt_e2m1x8_f32(\n v0: Float32,\n v1: Float32,\n v2: Float32,\n v3: Float32,\n v4: Float32,\n v5: Float32,\n v6: Float32,\n v7: Float32,\n *,\n loc=None,\n ip=None,\n) -> Uint32:\n \"\"\"\n Convert eight float32 values to eight E2M1 (4-bit) values packed into uint32.\n\n Uses cvt.rn.satfinite.e2m1x2.f32 PTX instruction to convert pairs of f32\n to pairs of 4-bit E2M1 values, then packs all 8 values into a single u32.\n \"\"\"\n return Uint32(\n llvm.inline_asm(\n T.i32(),\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n Float32(v2).ir_value(loc=loc, ip=ip),\n Float32(v3).ir_value(loc=loc, ip=ip),\n Float32(v4).ir_value(loc=loc, ip=ip),\n Float32(v5).ir_value(loc=loc, ip=ip),\n Float32(v6).ir_value(loc=loc, ip=ip),\n Float32(v7).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b8 byte0, byte1, byte2, byte3;\n cvt.rn.satfinite.e2m1x2.f32 byte0, $2, $1;\n cvt.rn.satfinite.e2m1x2.f32 byte1, $4, $3;\n cvt.rn.satfinite.e2m1x2.f32 byte2, $6, $5;\n cvt.rn.satfinite.e2m1x2.f32 byte3, $8, $7;\n mov.b32 $0, {byte0, byte1, byte2, byte3};\n }\n \"\"\",\n \"=r,f,f,f,f,f,f,f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n# =============================================================================\n# Warp Shuffle for 4-Thread Reduction\n# =============================================================================\n\n\n@cute.jit\ndef shuffle_xor_f32(val: Float32, offset: int) -> Float32:\n \"\"\"XOR shuffle for float32 values.\"\"\"\n return cute.arch.shuffle_sync_bfly(val, offset=offset)\n\n\n@cute.jit\ndef reduce_max_4threads(val: Float32) -> Float32:\n \"\"\"Reduce max across 4 consecutive threads using 2 XOR shuffles.\"\"\"\n from ..cute_dsl.fp4_common import fmax_f32\n\n other = shuffle_xor_f32(val, 1)\n val = fmax_f32(val, other)\n other = shuffle_xor_f32(val, 2)\n val = fmax_f32(val, other)\n return val\n\n\n# =============================================================================\n# Swizzled Index Computation (GPU-side)\n# =============================================================================\n\n\n@cute.jit\ndef compute_sf_index_swizzled_128x4_gpu(\n row_idx: Int32,\n col_idx: Int32,\n padded_cols: Int32,\n) -> Int32:\n \"\"\"Compute swizzled 128x4 scale factor index on GPU.\"\"\"\n kColumnGroup0Size = Int32(4)\n kRowGroup0Size = Int32(32)\n kRowGroup1Size = Int32(128)\n\n columnIdxInGroup0 = col_idx % kColumnGroup0Size\n columnGroupIdx = col_idx // kColumnGroup0Size\n columnGroupStride = Int32(512)\n\n rowIdxInGroup0 = row_idx % kRowGroup0Size\n rowIdxInGroup1 = (row_idx % kRowGroup1Size) // kRowGroup0Size\n rowGroupIdx = row_idx // kRowGroup1Size\n\n rowGroup1Stride = Int32(4)\n rowGroup0Stride = Int32(16)\n rowGroupStride = kRowGroup1Size * padded_cols\n\n offset = (\n columnIdxInGroup0\n + columnGroupIdx * columnGroupStride\n + rowIdxInGroup0 * rowGroup0Stride\n + rowIdxInGroup1 * rowGroup1Stride\n + rowGroupIdx * rowGroupStride\n )\n\n return offset\n\n\n@cute.jit\ndef compute_sf_index_swizzled_8x4_gpu(\n row_idx: Int32,\n col_idx: Int32,\n padded_cols: Int32,\n) -> Int32:\n \"\"\"Compute swizzled 8x4 scale factor index on GPU.\n\n Layout: [numMTiles, numKTiles, 8 (mTile), 4 (kTile)]\n Tile size: 32 elements (8 rows x 4 cols).\n \"\"\"\n kMTileSize = Int32(8)\n kKTileSize = Int32(4)\n kTileElements = Int32(32)\n\n innerKIdx = col_idx % kKTileSize\n innerMIdx = row_idx % kMTileSize\n kTileIdx = col_idx // kKTileSize\n mTileIdx = row_idx // kMTileSize\n\n numKTiles = (padded_cols + kKTileSize - Int32(1)) // kKTileSize\n\n offset = (\n mTileIdx * (numKTiles * kTileElements)\n + kTileIdx * kTileElements\n + innerMIdx * kKTileSize\n + innerKIdx\n )\n\n return offset\n\n\n@cute.jit\ndef compute_sf_index_linear_gpu(\n row_idx: Int32,\n col_idx: Int32,\n num_cols: Int32,\n) -> Int32:\n \"\"\"Compute linear (row-major) scale factor index on GPU.\"\"\"\n return row_idx * num_cols + col_idx\n\n\n# =============================================================================\n# High-Level Helper Functions for MXFP8 Quantization\n# =============================================================================\n\n\n@cute.jit\ndef half2_max_abs_4(v0: Uint32, v1: Uint32, v2: Uint32, v3: Uint32) -> Uint32:\n \"\"\"\n Compute max absolute value across 4 half2 values (8 FP16 elements).\n\n Uses tree reduction: 4 -> 2 -> 1 half2 values.\n Returns a half2 containing the max absolute value in both lanes.\n \"\"\"\n abs0 = habs2(v0)\n abs1 = habs2(v1)\n abs2 = habs2(v2)\n abs3 = habs2(v3)\n max01 = hmax2(abs0, abs1)\n max23 = hmax2(abs2, abs3)\n return hmax2(max01, max23)\n\n\n@cute.jit\ndef bfloat2_max_abs_4(v0: Uint32, v1: Uint32, v2: Uint32, v3: Uint32) -> Uint32:\n \"\"\"\n Compute max absolute value across 4 bfloat2 values (8 BF16 elements).\n\n Uses tree reduction: 4 -> 2 -> 1 bfloat2 values.\n Returns a bfloat2 containing the max absolute value in both lanes.\n \"\"\"\n abs0 = bfloat2_habs2(v0)\n abs1 = bfloat2_habs2(v1)\n abs2 = bfloat2_habs2(v2)\n abs3 = bfloat2_habs2(v3)\n max01 = bfloat2_hmax2(abs0, abs1)\n max23 = bfloat2_hmax2(abs2, abs3)\n return bfloat2_hmax2(max01, max23)\n\n\n@cute.jit\ndef half2x4_to_fp8x8_packed(\n v0: Uint32, v1: Uint32, v2: Uint32, v3: Uint32, inv_scale: Float32\n) -> Uint64:\n \"\"\"\n Convert 4 half2 values (8 FP16) to 8 FP8 E4M3 and pack into u64.\n\n Each half2 is converted to 2 FP8 values using the inverse scale,\n then all 8 FP8 values are packed into a single 64-bit value for\n efficient vectorized store.\n \"\"\"\n fp8_01 = half2_to_fp8x2_scaled(v0, inv_scale)\n fp8_23 = half2_to_fp8x2_scaled(v1, inv_scale)\n fp8_45 = half2_to_fp8x2_scaled(v2, inv_scale)\n fp8_67 = half2_to_fp8x2_scaled(v3, inv_scale)\n return pack_fp8x8_to_u64(fp8_01, fp8_23, fp8_45, fp8_67)\n\n\n@cute.jit\ndef bfloat2x4_to_fp8x8_packed(\n v0: Uint32, v1: Uint32, v2: Uint32, v3: Uint32, inv_scale: Float32\n) -> Uint64:\n \"\"\"\n Convert 4 bfloat2 values (8 BF16) to 8 FP8 E4M3 and pack into u64.\n\n Each bfloat2 is converted to 2 FP8 values using the inverse scale,\n then all 8 FP8 values are packed into a single 64-bit value for\n efficient vectorized store.\n \"\"\"\n fp8_01 = bfloat2_to_fp8x2_scaled(v0, inv_scale)\n fp8_23 = bfloat2_to_fp8x2_scaled(v1, inv_scale)\n fp8_45 = bfloat2_to_fp8x2_scaled(v2, inv_scale)\n fp8_67 = bfloat2_to_fp8x2_scaled(v3, inv_scale)\n return pack_fp8x8_to_u64(fp8_01, fp8_23, fp8_45, fp8_67)\n\n\n# =============================================================================\n# MXFP4 High-Level Helper Functions\n# =============================================================================\n\n\n@cute.jit\ndef half2_max_abs_8(\n v0: Uint32,\n v1: Uint32,\n v2: Uint32,\n v3: Uint32,\n v4: Uint32,\n v5: Uint32,\n v6: Uint32,\n v7: Uint32,\n) -> Uint32:\n \"\"\"\n Compute max absolute value across 8 half2 values (16 FP16 elements).\n\n Uses tree reduction: 8 -> 4 -> 2 -> 1 half2 values.\n Returns a half2 containing the max absolute value in both lanes.\n \"\"\"\n abs0 = habs2(v0)\n abs1 = habs2(v1)\n abs2 = habs2(v2)\n abs3 = habs2(v3)\n abs4 = habs2(v4)\n abs5 = habs2(v5)\n abs6 = habs2(v6)\n abs7 = habs2(v7)\n\n max01 = hmax2(abs0, abs1)\n max23 = hmax2(abs2, abs3)\n max45 = hmax2(abs4, abs5)\n max67 = hmax2(abs6, abs7)\n\n max0123 = hmax2(max01, max23)\n max4567 = hmax2(max45, max67)\n\n return hmax2(max0123, max4567)\n\n\n@cute.jit\ndef bfloat2_max_abs_8(\n v0: Uint32,\n v1: Uint32,\n v2: Uint32,\n v3: Uint32,\n v4: Uint32,\n v5: Uint32,\n v6: Uint32,\n v7: Uint32,\n) -> Uint32:\n \"\"\"\n Compute max absolute value across 8 bfloat2 values (16 BF16 elements).\n\n Uses tree reduction: 8 -> 4 -> 2 -> 1 bfloat2 values.\n Returns a bfloat2 containing the max absolute value in both lanes.\n \"\"\"\n abs0 = bfloat2_habs2(v0)\n abs1 = bfloat2_habs2(v1)\n abs2 = bfloat2_habs2(v2)\n abs3 = bfloat2_habs2(v3)\n abs4 = bfloat2_habs2(v4)\n abs5 = bfloat2_habs2(v5)\n abs6 = bfloat2_habs2(v6)\n abs7 = bfloat2_habs2(v7)\n\n max01 = bfloat2_hmax2(abs0, abs1)\n max23 = bfloat2_hmax2(abs2, abs3)\n max45 = bfloat2_hmax2(abs4, abs5)\n max67 = bfloat2_hmax2(abs6, abs7)\n\n max0123 = bfloat2_hmax2(max01, max23)\n max4567 = bfloat2_hmax2(max45, max67)\n\n return bfloat2_hmax2(max0123, max4567)\n\n\n@cute.jit\ndef process_mxfp4_block_half(row_tensor, elem_base: Int32) -> tuple:\n \"\"\"\n Process a 32-element MXFP4 block for half precision input.\n\n Loads 32 FP16 elements, computes the UE8M0 scale factor, converts to E2M1,\n and packs the result into two u64 values.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n\n Returns:\n (scale_ue8m0_u32, scale_ue8m0_u8, packed64_0, packed64_1):\n - scale_ue8m0_u32: Scale factor as Uint32 (for inv_scale computation)\n - scale_ue8m0_u8: Scale factor as Uint8 (for storage)\n - packed64_0, packed64_1: Two Uint64 containing 16 E2M1 values each\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n get_ptr_as_int64,\n hmax2,\n ld_global_v4_u32,\n rcp_approx_ftz,\n )\n\n # Load 32 elements (4 x 128-bit = 16 half2 values)\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n ptr2 = get_ptr_as_int64(row_tensor, elem_base + Int32(16))\n ptr3 = get_ptr_as_int64(row_tensor, elem_base + Int32(24))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n h8, h9, h10, h11 = ld_global_v4_u32(ptr2)\n h12, h13, h14, h15 = ld_global_v4_u32(ptr3)\n\n # Compute max absolute value across 32 elements\n max_first = half2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n max_second = half2_max_abs_8(h8, h9, h10, h11, h12, h13, h14, h15)\n block_max_h2 = hmax2(max_first, max_second)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n # Compute UE8M0 scale factor (rcp_approx matches CUDA's rcp.approx.ftz(6.0f))\n normalized_max = block_max * rcp_approx_ftz(Float32(6.0))\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0_u8 = scale_ue8m0_u32.to(Uint8)\n\n # Compute inverse scale and convert to E2M1 packed format\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n packed64_0, packed64_1 = half2x16_to_e2m1x32_packed(\n h0,\n h1,\n h2,\n h3,\n h4,\n h5,\n h6,\n h7,\n h8,\n h9,\n h10,\n h11,\n h12,\n h13,\n h14,\n h15,\n inv_scale,\n )\n\n return scale_ue8m0_u32, scale_ue8m0_u8, packed64_0, packed64_1\n\n\n@cute.jit\ndef process_mxfp4_block_bfloat(row_tensor, elem_base: Int32) -> tuple:\n \"\"\"\n Process a 32-element MXFP4 block for bfloat16 precision input.\n\n Loads 32 BF16 elements, computes the UE8M0 scale factor, converts to E2M1,\n and packs the result into two u64 values.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n\n Returns:\n (scale_ue8m0_u32, scale_ue8m0_u8, packed64_0, packed64_1):\n - scale_ue8m0_u32: Scale factor as Uint32 (for inv_scale computation)\n - scale_ue8m0_u8: Scale factor as Uint8 (for storage)\n - packed64_0, packed64_1: Two Uint64 containing 16 E2M1 values each\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n bfloat2_hmax2,\n get_ptr_as_int64,\n ld_global_v4_u32,\n rcp_approx_ftz,\n )\n\n # Load 32 elements (4 x 128-bit = 16 bfloat2 values)\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n ptr2 = get_ptr_as_int64(row_tensor, elem_base + Int32(16))\n ptr3 = get_ptr_as_int64(row_tensor, elem_base + Int32(24))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n h8, h9, h10, h11 = ld_global_v4_u32(ptr2)\n h12, h13, h14, h15 = ld_global_v4_u32(ptr3)\n\n # Compute max absolute value across 32 elements\n max_first = bfloat2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n max_second = bfloat2_max_abs_8(h8, h9, h10, h11, h12, h13, h14, h15)\n block_max_h2 = bfloat2_hmax2(max_first, max_second)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n\n # Compute UE8M0 scale factor (rcp_approx matches CUDA's rcp.approx.ftz(6.0f))\n normalized_max = block_max * rcp_approx_ftz(Float32(6.0))\n scale_ue8m0_u32 = float_to_ue8m0_fast(normalized_max)\n scale_ue8m0_u8 = scale_ue8m0_u32.to(Uint8)\n\n # Compute inverse scale and convert to E2M1 packed format\n inv_scale = ue8m0_to_inv_scale_fast(scale_ue8m0_u32)\n packed64_0, packed64_1 = bfloat2x16_to_e2m1x32_packed(\n h0,\n h1,\n h2,\n h3,\n h4,\n h5,\n h6,\n h7,\n h8,\n h9,\n h10,\n h11,\n h12,\n h13,\n h14,\n h15,\n inv_scale,\n )\n\n return scale_ue8m0_u32, scale_ue8m0_u8, packed64_0, packed64_1\n\n\n@cute.jit\ndef ld_32_elements(row_tensor, elem_base: Int32) -> tuple:\n \"\"\"\n Load 32 elements (16 half2/bfloat2 values) from a row tensor.\n\n This loads 4 x 128-bit vectors (4 x v4_u32) starting at elem_base.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n\n Returns:\n Tuple of 16 Uint32 values (h0-h15), each containing 2 fp16/bf16 elements\n \"\"\"\n from ..cute_dsl.fp4_common import get_ptr_as_int64, ld_global_v4_u32\n\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n ptr2 = get_ptr_as_int64(row_tensor, elem_base + Int32(16))\n ptr3 = get_ptr_as_int64(row_tensor, elem_base + Int32(24))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0) # Elements 0-7\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1) # Elements 8-15\n h8, h9, h10, h11 = ld_global_v4_u32(ptr2) # Elements 16-23\n h12, h13, h14, h15 = ld_global_v4_u32(ptr3) # Elements 24-31\n\n return h0, h1, h2, h3, h4, h5, h6, h7, h8, h9, h10, h11, h12, h13, h14, h15\n\n\n@cute.jit\ndef half2x16_to_e2m1x32_packed(\n h0: Uint32,\n h1: Uint32,\n h2: Uint32,\n h3: Uint32,\n h4: Uint32,\n h5: Uint32,\n h6: Uint32,\n h7: Uint32,\n h8: Uint32,\n h9: Uint32,\n h10: Uint32,\n h11: Uint32,\n h12: Uint32,\n h13: Uint32,\n h14: Uint32,\n h15: Uint32,\n inv_scale: Float32,\n) -> tuple:\n \"\"\"\n Convert 16 half2 values (32 FP16) to 32 E2M1 and pack into two u64.\n\n Each half2 is converted to 2 float32 values using inv_scale,\n then groups of 8 floats are converted to 8 E2M1 values packed into u32,\n and finally combined into two u64 values for vectorized store.\n\n Returns:\n (packed64_0, packed64_1): Two Uint64 containing 16 E2M1 values each\n \"\"\"\n # Scale and convert each half2 to 2 float32\n s0, s1 = half2_to_float2_scaled(h0, inv_scale)\n s2, s3 = half2_to_float2_scaled(h1, inv_scale)\n s4, s5 = half2_to_float2_scaled(h2, inv_scale)\n s6, s7 = half2_to_float2_scaled(h3, inv_scale)\n s8, s9 = half2_to_float2_scaled(h4, inv_scale)\n s10, s11 = half2_to_float2_scaled(h5, inv_scale)\n s12, s13 = half2_to_float2_scaled(h6, inv_scale)\n s14, s15 = half2_to_float2_scaled(h7, inv_scale)\n s16, s17 = half2_to_float2_scaled(h8, inv_scale)\n s18, s19 = half2_to_float2_scaled(h9, inv_scale)\n s20, s21 = half2_to_float2_scaled(h10, inv_scale)\n s22, s23 = half2_to_float2_scaled(h11, inv_scale)\n s24, s25 = half2_to_float2_scaled(h12, inv_scale)\n s26, s27 = half2_to_float2_scaled(h13, inv_scale)\n s28, s29 = half2_to_float2_scaled(h14, inv_scale)\n s30, s31 = half2_to_float2_scaled(h15, inv_scale)\n\n # Convert to E2M1 (4 x 8 floats -> 4 x uint32)\n packed0 = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed1 = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n packed2 = cvt_e2m1x8_f32(s16, s17, s18, s19, s20, s21, s22, s23)\n packed3 = cvt_e2m1x8_f32(s24, s25, s26, s27, s28, s29, s30, s31)\n\n # Pack into 2 x 64-bit values\n packed64_0 = (Uint64(packed1) << Uint64(32)) | Uint64(packed0)\n packed64_1 = (Uint64(packed3) << Uint64(32)) | Uint64(packed2)\n\n return packed64_0, packed64_1\n\n\n@cute.jit\ndef bfloat2x16_to_e2m1x32_packed(\n h0: Uint32,\n h1: Uint32,\n h2: Uint32,\n h3: Uint32,\n h4: Uint32,\n h5: Uint32,\n h6: Uint32,\n h7: Uint32,\n h8: Uint32,\n h9: Uint32,\n h10: Uint32,\n h11: Uint32,\n h12: Uint32,\n h13: Uint32,\n h14: Uint32,\n h15: Uint32,\n inv_scale: Float32,\n) -> tuple:\n \"\"\"\n Convert 16 bfloat2 values (32 BF16) to 32 E2M1 and pack into two u64.\n\n Each bfloat2 is converted to 2 float32 values using inv_scale,\n then groups of 8 floats are converted to 8 E2M1 values packed into u32,\n and finally combined into two u64 values for vectorized store.\n\n Returns:\n (packed64_0, packed64_1): Two Uint64 containing 16 E2M1 values each\n \"\"\"\n # Scale and convert each bfloat2 to 2 float32\n s0, s1 = bfloat2_to_float2_scaled(h0, inv_scale)\n s2, s3 = bfloat2_to_float2_scaled(h1, inv_scale)\n s4, s5 = bfloat2_to_float2_scaled(h2, inv_scale)\n s6, s7 = bfloat2_to_float2_scaled(h3, inv_scale)\n s8, s9 = bfloat2_to_float2_scaled(h4, inv_scale)\n s10, s11 = bfloat2_to_float2_scaled(h5, inv_scale)\n s12, s13 = bfloat2_to_float2_scaled(h6, inv_scale)\n s14, s15 = bfloat2_to_float2_scaled(h7, inv_scale)\n s16, s17 = bfloat2_to_float2_scaled(h8, inv_scale)\n s18, s19 = bfloat2_to_float2_scaled(h9, inv_scale)\n s20, s21 = bfloat2_to_float2_scaled(h10, inv_scale)\n s22, s23 = bfloat2_to_float2_scaled(h11, inv_scale)\n s24, s25 = bfloat2_to_float2_scaled(h12, inv_scale)\n s26, s27 = bfloat2_to_float2_scaled(h13, inv_scale)\n s28, s29 = bfloat2_to_float2_scaled(h14, inv_scale)\n s30, s31 = bfloat2_to_float2_scaled(h15, inv_scale)\n\n # Convert to E2M1 (4 x 8 floats -> 4 x uint32)\n packed0 = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed1 = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n packed2 = cvt_e2m1x8_f32(s16, s17, s18, s19, s20, s21, s22, s23)\n packed3 = cvt_e2m1x8_f32(s24, s25, s26, s27, s28, s29, s30, s31)\n\n # Pack into 2 x 64-bit values\n packed64_0 = (Uint64(packed1) << Uint64(32)) | Uint64(packed0)\n packed64_1 = (Uint64(packed3) << Uint64(32)) | Uint64(packed2)\n\n return packed64_0, packed64_1\n\n\n# =============================================================================\n# NVFP4 High-Level Helper Functions (sf_vec_size=16, E4M3 scale factors)\n# =============================================================================\n\n\n@cute.jit\ndef half2x8_to_e2m1x16_packed(\n h0: Uint32,\n h1: Uint32,\n h2: Uint32,\n h3: Uint32,\n h4: Uint32,\n h5: Uint32,\n h6: Uint32,\n h7: Uint32,\n inv_scale: Float32,\n) -> Uint64:\n \"\"\"\n Convert 8 half2 values (16 FP16) to 16 E2M1 and pack into u64.\n\n Returns:\n Uint64 containing 16 E2M1 values (8 bytes)\n \"\"\"\n s0, s1 = half2_to_float2_scaled(h0, inv_scale)\n s2, s3 = half2_to_float2_scaled(h1, inv_scale)\n s4, s5 = half2_to_float2_scaled(h2, inv_scale)\n s6, s7 = half2_to_float2_scaled(h3, inv_scale)\n s8, s9 = half2_to_float2_scaled(h4, inv_scale)\n s10, s11 = half2_to_float2_scaled(h5, inv_scale)\n s12, s13 = half2_to_float2_scaled(h6, inv_scale)\n s14, s15 = half2_to_float2_scaled(h7, inv_scale)\n\n packed_lo = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed_hi = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n@cute.jit\ndef bfloat2x8_to_e2m1x16_packed(\n h0: Uint32,\n h1: Uint32,\n h2: Uint32,\n h3: Uint32,\n h4: Uint32,\n h5: Uint32,\n h6: Uint32,\n h7: Uint32,\n inv_scale: Float32,\n) -> Uint64:\n \"\"\"\n Convert 8 bfloat2 values (16 BF16) to 16 E2M1 and pack into u64.\n\n Returns:\n Uint64 containing 16 E2M1 values (8 bytes)\n \"\"\"\n s0, s1 = bfloat2_to_float2_scaled(h0, inv_scale)\n s2, s3 = bfloat2_to_float2_scaled(h1, inv_scale)\n s4, s5 = bfloat2_to_float2_scaled(h2, inv_scale)\n s6, s7 = bfloat2_to_float2_scaled(h3, inv_scale)\n s8, s9 = bfloat2_to_float2_scaled(h4, inv_scale)\n s10, s11 = bfloat2_to_float2_scaled(h5, inv_scale)\n s12, s13 = bfloat2_to_float2_scaled(h6, inv_scale)\n s14, s15 = bfloat2_to_float2_scaled(h7, inv_scale)\n\n packed_lo = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed_hi = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n@cute.jit\ndef process_nvfp4_block_half(\n row_tensor, elem_base: Int32, global_scale: Float32\n) -> tuple:\n \"\"\"\n Process a 16-element NVFP4 block for half precision input.\n\n Loads 16 FP16 elements, computes the E4M3 scale factor using global_scale,\n converts to E2M1, and packs the result into a u64 value.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n global_scale: User-provided global scale factor\n\n Returns:\n (scale_e4m3_u8, packed64):\n - scale_e4m3_u8: E4M3 scale factor as Uint8\n - packed64: Uint64 containing 16 E2M1 values\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n cvt_f32_to_e4m3,\n get_ptr_as_int64,\n ld_global_v4_u32,\n nvfp4_compute_output_scale,\n rcp_approx_ftz,\n )\n\n # Load 16 elements (2 x 128-bit = 8 half2 values)\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n\n # Compute max absolute value across 16 elements\n block_max_h2 = half2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n # E4M3 scale factor computation\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n\n # output_scale = rcp(float(E4M3(scale)) * rcp(global_scale)), matching CUDA\n output_scale = nvfp4_compute_output_scale(scale_fp8_u32, global_scale)\n\n # Convert to E2M1 and pack\n packed64 = half2x8_to_e2m1x16_packed(h0, h1, h2, h3, h4, h5, h6, h7, output_scale)\n\n return scale_fp8, packed64\n\n\n@cute.jit\ndef process_nvfp4_block_bfloat(\n row_tensor, elem_base: Int32, global_scale: Float32\n) -> tuple:\n \"\"\"\n Process a 16-element NVFP4 block for bfloat16 precision input.\n\n Loads 16 BF16 elements, computes the E4M3 scale factor using global_scale,\n converts to E2M1, and packs the result into a u64 value.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n global_scale: User-provided global scale factor\n\n Returns:\n (scale_e4m3_u8, packed64):\n - scale_e4m3_u8: E4M3 scale factor as Uint8\n - packed64: Uint64 containing 16 E2M1 values\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n cvt_f32_to_e4m3,\n get_ptr_as_int64,\n ld_global_v4_u32,\n nvfp4_compute_output_scale,\n rcp_approx_ftz,\n )\n\n # Load 16 elements (2 x 128-bit = 8 bfloat2 values)\n ptr0 = get_ptr_as_int64(row_tensor, elem_base)\n ptr1 = get_ptr_as_int64(row_tensor, elem_base + Int32(8))\n\n h0, h1, h2, h3 = ld_global_v4_u32(ptr0)\n h4, h5, h6, h7 = ld_global_v4_u32(ptr1)\n\n # Compute max absolute value across 16 elements\n block_max_h2 = bfloat2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = bfloat2_hmax_reduce_to_f32(block_max_h2)\n\n # E4M3 scale factor computation\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n\n # output_scale = rcp(float(E4M3(scale)) * rcp(global_scale)), matching CUDA\n output_scale = nvfp4_compute_output_scale(scale_fp8_u32, global_scale)\n\n # Convert to E2M1 and pack\n packed64 = bfloat2x8_to_e2m1x16_packed(h0, h1, h2, h3, h4, h5, h6, h7, output_scale)\n\n return scale_fp8, packed64\n\n\n@cute.jit\ndef fp8x16_to_e2m1x16_packed(\n w0: Uint32,\n w1: Uint32,\n w2: Uint32,\n w3: Uint32,\n output_scale: Float32,\n) -> Uint64:\n \"\"\"Convert 16 packed FP8 E4M3 values (4 x uint32) to 16 E2M1 values packed as Uint64.\n\n Each uint32 contains 4 E4M3 bytes. Output is 16 E2M1 nibbles packed into 8 bytes.\n \"\"\"\n from ..cute_dsl.fp4_common import cvt_e4m3x4_to_f32x4\n\n f0, f1, f2, f3 = cvt_e4m3x4_to_f32x4(w0)\n f4, f5, f6, f7 = cvt_e4m3x4_to_f32x4(w1)\n f8, f9, f10, f11 = cvt_e4m3x4_to_f32x4(w2)\n f12, f13, f14, f15 = cvt_e4m3x4_to_f32x4(w3)\n\n s0 = f0 * output_scale\n s1 = f1 * output_scale\n s2 = f2 * output_scale\n s3 = f3 * output_scale\n s4 = f4 * output_scale\n s5 = f5 * output_scale\n s6 = f6 * output_scale\n s7 = f7 * output_scale\n s8 = f8 * output_scale\n s9 = f9 * output_scale\n s10 = f10 * output_scale\n s11 = f11 * output_scale\n s12 = f12 * output_scale\n s13 = f13 * output_scale\n s14 = f14 * output_scale\n s15 = f15 * output_scale\n\n packed_lo = cvt_e2m1x8_f32(s0, s1, s2, s3, s4, s5, s6, s7)\n packed_hi = cvt_e2m1x8_f32(s8, s9, s10, s11, s12, s13, s14, s15)\n\n return (Uint64(packed_hi) << Uint64(32)) | Uint64(packed_lo)\n\n\n@cute.jit\ndef fp8_max_abs_16(w0: Uint32, w1: Uint32, w2: Uint32, w3: Uint32) -> Float32:\n \"\"\"Compute max absolute value across 16 FP8 E4M3 values (4 x uint32).\n\n Converts all 16 values to float32, takes abs, and reduces to a single max.\n \"\"\"\n from ..cute_dsl.fp4_common import cvt_e4m3x4_to_f32x4\n\n f0, f1, f2, f3 = cvt_e4m3x4_to_f32x4(w0)\n f4, f5, f6, f7 = cvt_e4m3x4_to_f32x4(w1)\n f8, f9, f10, f11 = cvt_e4m3x4_to_f32x4(w2)\n f12, f13, f14, f15 = cvt_e4m3x4_to_f32x4(w3)\n\n from ..cute_dsl.fp4_common import fabs_f32, fmax_f32\n\n a0 = fabs_f32(f0)\n a1 = fabs_f32(f1)\n a2 = fabs_f32(f2)\n a3 = fabs_f32(f3)\n a4 = fabs_f32(f4)\n a5 = fabs_f32(f5)\n a6 = fabs_f32(f6)\n a7 = fabs_f32(f7)\n a8 = fabs_f32(f8)\n a9 = fabs_f32(f9)\n a10 = fabs_f32(f10)\n a11 = fabs_f32(f11)\n a12 = fabs_f32(f12)\n a13 = fabs_f32(f13)\n a14 = fabs_f32(f14)\n a15 = fabs_f32(f15)\n\n m01 = fmax_f32(a0, a1)\n m23 = fmax_f32(a2, a3)\n m45 = fmax_f32(a4, a5)\n m67 = fmax_f32(a6, a7)\n m89 = fmax_f32(a8, a9)\n m1011 = fmax_f32(a10, a11)\n m1213 = fmax_f32(a12, a13)\n m1415 = fmax_f32(a14, a15)\n\n m0123 = fmax_f32(m01, m23)\n m4567 = fmax_f32(m45, m67)\n m891011 = fmax_f32(m89, m1011)\n m12131415 = fmax_f32(m1213, m1415)\n\n m_lo = fmax_f32(m0123, m4567)\n m_hi = fmax_f32(m891011, m12131415)\n\n return fmax_f32(m_lo, m_hi)\n\n\n@cute.jit\ndef process_nvfp4_block_fp8(\n row_tensor, elem_base: Int32, global_scale: Float32\n) -> tuple:\n \"\"\"\n Process a 16-element NVFP4 block for FP8 E4M3 input.\n\n Matches the CUDA cvt_warp_fp8_to_fp4 behavior: FP8 values are first converted\n to float32, pre-scaled by 6/global_scale, and converted to half2. From there,\n the standard half2 pipeline is used for max-abs reduction, scale factor\n computation, and E2M1 conversion.\n\n Args:\n row_tensor: Row tensor slice (mInput[row_idx, None])\n elem_base: Starting element index\n global_scale: User-provided global scale factor\n\n Returns:\n (scale_e4m3_u8, packed64):\n - scale_e4m3_u8: E4M3 scale factor as Uint8\n - packed64: Uint64 containing 16 E2M1 values\n \"\"\"\n from cutlass import Uint8\n\n from ..cute_dsl.fp4_common import (\n cvt_e4m3x4_to_f32x4,\n cvt_f32_to_e4m3,\n cvt_f32x2_to_half2,\n get_ptr_as_int64,\n ld_global_v4_u32,\n nvfp4_compute_output_scale,\n rcp_approx_ftz,\n )\n\n # Load 16 FP8 elements (1 x 128-bit = 4 x uint32 = 16 bytes)\n ptr = get_ptr_as_int64(row_tensor, elem_base)\n w0, w1, w2, w3 = ld_global_v4_u32(ptr)\n\n # Convert FP8 to float32 and pre-scale by 6/global_scale (matching CUDA)\n prescale = Float32(6.0) * rcp_approx_ftz(global_scale)\n\n f0, f1, f2, f3 = cvt_e4m3x4_to_f32x4(w0)\n f4, f5, f6, f7 = cvt_e4m3x4_to_f32x4(w1)\n f8, f9, f10, f11 = cvt_e4m3x4_to_f32x4(w2)\n f12, f13, f14, f15 = cvt_e4m3x4_to_f32x4(w3)\n\n # Pack pre-scaled float pairs into half2 (matching __float22half2_rn in CUDA)\n h0 = cvt_f32x2_to_half2(f0 * prescale, f1 * prescale)\n h1 = cvt_f32x2_to_half2(f2 * prescale, f3 * prescale)\n h2 = cvt_f32x2_to_half2(f4 * prescale, f5 * prescale)\n h3 = cvt_f32x2_to_half2(f6 * prescale, f7 * prescale)\n h4 = cvt_f32x2_to_half2(f8 * prescale, f9 * prescale)\n h5 = cvt_f32x2_to_half2(f10 * prescale, f11 * prescale)\n h6 = cvt_f32x2_to_half2(f12 * prescale, f13 * prescale)\n h7 = cvt_f32x2_to_half2(f14 * prescale, f15 * prescale)\n\n # From here, use the same half2 pipeline as process_nvfp4_block_half\n block_max_h2 = half2_max_abs_8(h0, h1, h2, h3, h4, h5, h6, h7)\n block_max = hmax_reduce_to_f32(block_max_h2)\n\n # E4M3 scale factor computation\n fp4_max_rcp = rcp_approx_ftz(Float32(6.0))\n scale_float = global_scale * (block_max * fp4_max_rcp)\n scale_fp8_u32 = cvt_f32_to_e4m3(scale_float)\n scale_fp8 = Uint8(scale_fp8_u32 & Uint32(0xFF))\n\n # output_scale = rcp(float(E4M3(scale)) * rcp(global_scale)), matching CUDA\n output_scale = nvfp4_compute_output_scale(scale_fp8_u32, global_scale)\n\n # Convert pre-scaled half2 values to E2M1 and pack\n packed64 = half2x8_to_e2m1x16_packed(h0, h1, h2, h3, h4, h5, h6, h7, output_scale)\n\n return scale_fp8, packed64\n\n\n__all__ = [\n # NVFP4 Constants\n \"NVFP4_SF_VEC_SIZE\",\n # MXFP8 Constants\n \"SF_VEC_SIZE\",\n \"INV_FLOAT8_E4M3_MAX\",\n \"WARP_SIZE\",\n \"ELTS_PER_THREAD\",\n \"THREADS_PER_SF\",\n \"SF_BLOCKS_PER_WARP\",\n \"ROW_TILE_SIZE\",\n # MXFP4 Constants\n \"MXFP4_SF_VEC_SIZE\",\n \"MXFP4_ELTS_PER_THREAD\",\n \"INV_FLOAT4_E2M1_MAX\",\n \"MXFP4_GLOBAL_SCALE_FACTOR\",\n # Low-level intrinsics (MXFP8)\n \"hmax_reduce_to_f32\",\n \"bfloat2_hmax_reduce_to_f32\",\n \"float_to_ue8m0_fast\",\n \"ue8m0_to_inv_scale_fast\",\n \"reduce_max_4threads\",\n \"compute_sf_index_swizzled_128x4_gpu\",\n \"compute_sf_index_swizzled_8x4_gpu\",\n \"compute_sf_index_linear_gpu\",\n # Low-level intrinsics (MXFP4 - E2M1 conversion)\n \"half2_to_float2_scaled\",\n \"bfloat2_to_float2_scaled\",\n \"cvt_e2m1x8_f32\",\n # High-level helper functions (MXFP8)\n \"half2_max_abs_4\",\n \"bfloat2_max_abs_4\",\n \"half2x4_to_fp8x8_packed\",\n \"bfloat2x4_to_fp8x8_packed\",\n # High-level helper functions (MXFP4)\n \"half2_max_abs_8\",\n \"bfloat2_max_abs_8\",\n \"process_mxfp4_block_half\",\n \"process_mxfp4_block_bfloat\",\n \"ld_32_elements\",\n \"half2x16_to_e2m1x32_packed\",\n \"bfloat2x16_to_e2m1x32_packed\",\n # High-level helper functions (NVFP4)\n \"half2x8_to_e2m1x16_packed\",\n \"bfloat2x8_to_e2m1x16_packed\",\n \"process_nvfp4_block_half\",\n \"process_nvfp4_block_bfloat\",\n # High-level helper functions (NVFP4 - FP8 input)\n \"fp8x16_to_e2m1x16_packed\",\n \"fp8_max_abs_16\",\n \"process_nvfp4_block_fp8\",\n]\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n**Summary**\n- Adopt dual-path kernel architecture (linear flat + swizzled row-based) for MXFP4 and NVFP4 CuTe-DSL quantization kernels.\n- Architecture chanes to MXFP8 quantization for better perf.\n- Expand benchmark scripts and test coverage across all three quantization kernels. Compares exact output match between CUDA & CuTe-DSL backends\n- **All mxfp4, mxfp8, and nvfp4 quantization have exact bitwise match in for CUDA vs. CuTe DSL backends in both the output and scaling factors.**\n\n**Kernel changes**\n`mxfp8_quantize.py`\n- Adaptive 2T/SF dispatch: 2 threads per SF block for large problems (total_sf >= 65536), 4 threads for small problems for better memory bandwidth utilization.\n- Integer UE8M0 conversion (float_to_ue8m0_fast, ue8m0_to_inv_scale_fast): replaces SFU-based lg2.approx/ex2.approx with integer bit manipulation, freeing the SFU pipeline\n- reduce_max_2threads: 1-shuffle XOR reduction for the 2T path\n- Remove unused self.dtype and self.K attributes \n \n`mxfp4_quantize.py`\n- Add swizzled kernel. Previously only supported linear layout. \n- Swizzled kernel: small-K multi-row path and large-K column-loop path, compile-time selected via const_expr(needs_col_loop)\n- Inline padding for swizzled layout (row and column) — eliminates the expensive separate flat-iteration padding passes that caused 5x+ regression at small M \n- Dynamic thread count via _compute_optimal_threads(K) for 100% thread utilization \n \n`nvfp4_quantize.py`\n- Same dual-path split: NVFP4QuantizeLinearKernel + NVFP4QuantizeSwizzledKernel \n- Supports all three SF layouts (128x4, 8x4, linear) with compile-time dispatch \n- Remove unused self.row_tile_size and self.ROW_ITERATIONS from TMA kernel \n \n `quantization_cute_dsl_utils.py`\n- ue8m0_to_inv_scale_fast: integer bit construction replacing ex2.approx \n- reduce_max_2threads: 1-shuffle reduction for 2T/SF MXFP8 path \n- 2T/SF constants: ELTS_PER_THREAD, THREADS_PER_SF, SF_BLOCKS_PER_WARP + legacy 4T variants \n- MXFP8_2T_SF_THRESHOLD = 65536 \n\n**Test changes**\n- `test_fp4_quantize.py` and `test_fp8_quantize.py`: Add more problem sizes. \n- `test_fp4_quantize_padding.py`: Add both-backend parametrization and CUDA-vs-CuTe-DSL parity test for linear layout padding.\n\n**Perf comparison between backends on B200**\n\n<details>\n <summary>Click to see mxfp8 performance comparison</summary>\n\nLinear (gmean 1.42x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp8_backend_comparison_linear_bfloat16\" src=\"https://github.com/user-attachments/assets/21b630ff-d1a7-427b-9e59-5b6417c498c6\" />\n\nSwizzled (gmean 1.37x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp8_backend_comparison_swizzled_bfloat16\" src=\"https://github.com/user-attachments/assets/f9d19958-df34-4fc9-8351-6b9348aba8c6\" />\n\n\n</details>\n\n<details>\n <summary>Click to see mxfp4 performance comparison</summary>\n\nLinear (gmean 1.41x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp4_quantize_backend_comparison_linear_bfloat16\" src=\"https://github.com/user-attachments/assets/e050a38d-600e-43c1-92eb-f0b51e22accf\" />\n\n\nSwizzled (gmean 1.39x)\n\n<img width=\"1644\" height=\"1477\" alt=\"mxfp4_quantize_backend_comparison_swizzled_bfloat16\" src=\"https://github.com/user-attachments/assets/d4e4cd72-baad-4057-9523-63cd6665bf6e\" />\n\n</details>\n\n<details>\n <summary>Click to see nvfp4 performance comparison</summary>\n\nLinear (gmean 1.34x)\n\n<img width=\"1644\" height=\"1477\" alt=\"nvfp4_quantize_backend_comparison_linear_bfloat16\" src=\"https://github.com/user-attachments/assets/532ef7f2-0a41-406c-8eda-0f16436672c1\" />\n\n\nSwizzled (gmean 1.32x)\n\n<img width=\"1644\" height=\"1477\" alt=\"nvfp4_quantize_backend_comparison_swizzled_bfloat16\" src=\"https://github.com/user-attachments/assets/9694e1d3-e92e-45c9-81b5-527dca4e6cd1\" />\n\n\n</details>\n\n<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Benchmarks now run and report both linear and swizzled scale-factor layouts separately, generating distinct heatmaps/tables and layout-aware labels.\n * Added a new NVFP4 quantization benchmark with bandwidth and comparison modes.\n\n* **Refactor**\n * Quantize kernels split into layout-specific implementations and introduced dual-mode threading optimizations for better performance across sizes.\n\n* **Tests**\n * Expanded parameter sweeps, added backend parameterization, and capability-aware skips.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Linear\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.42, \"speedup\": 1.42}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Swizzled\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.37, \"speedup\": 1.37}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Linear\", \"batch_matrix\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.41, \"speedup\": 1.41}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Swizzled\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.39, \"speedup\": 1.39}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Linear\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.34, \"speedup\": 1.34}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"Swizzled\", \"batch_size\": null, \"metric\": \"performance\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.32, \"speedup\": 1.32}]"},"kernel_speedup":{"kind":"number","value":1.38,"string":"1.38"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1174,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"e679e45383d2621681a06c39670448be59a817c9"},"date":{"kind":"string","value":"2026-03-20T21:38:48+02:00"},"pr_number":{"kind":"number","value":2821,"string":"2,821"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2821"},"title":{"kind":"string","value":"fix: Autotuner _find_nearest_profile non-power-of-2 num_tokens, create launchers for all supported tileN in trtllm fused MoE (#2821)"},"message":{"kind":"string","value":"fix: Autotuner _find_nearest_profile non-power-of-2 num_tokens, create launchers for all supported tileN in trtllm fused MoE (#2821)\n\n## 📌 Description\n\nIt fixes two autotuner related bugs:\n1. Revert back the autotuner fix that was reverted in\nhttps://github.com/flashinfer-ai/flashinfer/pull/2697\n2. Fix the issue that\nhttps://github.com/flashinfer-ai/flashinfer/pull/2697 revealed, which is\ntrtllm fused MoE kernel launcher crash when it receives tileN that is\nsupported but filtered out by `computeSelectedTileN`, by creating kernel\nlaunchers for all supported tileN values.\n\nThis PR continues the work in\nhttps://github.com/flashinfer-ai/flashinfer/pull/2695 by @danisereb to\nrevert bugfix 1 and to fix bug 2.\n\nMore technical details:\n### Bug 1:\nWhen given num_tokens that isn't a power-of-2, the autotuner (python\nside) fails to find its appropriate entry in the autotuner cache, so it\nfalls back to passing default, which means passing `[-1, -1]` as the\n`(tileN, tactic)` to the CPP.\nIt was fixed in [this\nPR](https://github.com/flashinfer-ai/flashinfer/pull/2617/changes#diff-1964ab957d8185d04b0d5f0cb02d0c7c0a3260ac0a6c573167af6875ab0b0e87L729-L734)\nbut soon after merge, it was reverted\n[here](https://github.com/flashinfer-ai/flashinfer/pull/2697), as it\nexposed the next bug.\n\n### Bug 2 (exposed after fixing bug 1):\nCrash in fused MoE kernel launcher on forward pass on some values of\nnum_tokens. The crash is at `launchers_map.at(tile_N)` in\n`trtllm_fused_moe_kernel_launcher.cu`. It happens because:\nThe python side of the autotuner profiles num_tokens that are power of\n2, and each such value represents the range until the next power of 2.\ne.g.: The profile for the range `[2048, 4095]` is done on\nnum_tokens=2048.\n\n`computeSelectedTileN` function in `trtllm_fused_moe_kernel_launcher.cu`\nreduces the set of supported tileN values (to reduce the autotuner's\nsearch space), by choosing specific values from the supported tileN\nsorted list, the values are: `roundUpToPowerOfTwo(num_tokens * topK /\nnumExperts)`, its previous one, and its next 2 values (max value is\n256). So values in the same range can get different sets of tileN\nvalues.\nFor example, on Nemotron 3 Super NVFP4:\n- `num_tokens=2048` -> `2048*22/512 = 88`, which rounds up to 128, so\nthe tileN set is `(64, 128, 256)`\n- `num_tokens=3003` -> `3003*22/512 = 129.03`, which rounds up to 256,\nso the tileN set is `(128, 256)`\nIn case `tileN=64` was found to be the fastest on `num_tokens=2048` for\nrange `[2048, 4095]`, when given `num_tokens=3003`, the python side\nwould pass `[64, someTactic]` to the CPP, but for `num_tokens=3003`,\nthere's no launcher for `tileN=64` as `computeSelectedTileN` filtered it\nout.\n\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n* Stricter MoE tile validation and ensured all supported tiles are\navailable at launch to avoid missing kernel configurations.\n* Autotuner mapping for linked dynamic dimensions now yields consistent\ncached bucket values.\n\n* **Tests**\n* Added SM100 MoE autotuner integration tests (including\ninvalid-cached-tactic checks).\n* Re-enabled and expanded autotuner unit tests and added a test utility\nto reset the autotuner.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nSigned-off-by: Daniel Serebrenik <daserebrenik@nvidia.com>\nSigned-off-by: amitz-nv <203509407+amitz-nv@users.noreply.github.com>\nCo-authored-by: Daniel Serebrenik <daserebrenik@nvidia.com>"},"path":{"kind":"string","value":"csrc/trtllm_fused_moe_kernel_launcher.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <cuda_runtime.h>\n#include <flashinfer/exception.h>\n#include <nvrtc.h>\n\n#include <algorithm>\n#include <cmath>\n#include <cstring>\n#include <iomanip>\n#include <iostream>\n#include <set>\n#include <unordered_map>\n#include <vector>\n\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/GemmGatedActOptions.h\"\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/trtllm/gen/DtypeDecl.h\"\n#include \"flashinfer/trtllm/fused_moe/DevKernel.h\"\n#include \"flashinfer/trtllm/fused_moe/RoutingKernel.h\"\n#include \"flashinfer/trtllm/fused_moe/runner.h\"\n#include \"nv_internal/tensorrt_llm/kernels/quantization.h\"\n#include \"nv_internal/tensorrt_llm/thop/utils.h\"\n#include \"tvm_ffi_utils.h\"\n\nnamespace flashinfer {\n\nnamespace btg = batchedGemm::trtllm::gen;\nusing tensorrt_llm::kernels::trtllmgen_moe::MoE::ActivationType;\nusing tensorrt_llm::kernels::trtllmgen_moe::Routing::RoutingMethodType;\nusing tvm::ffi::Array;\nusing tvm::ffi::Optional;\n\nenum class Fp8QuantizationType {\n NoneFp8,\n DeepSeekFp8,\n MxFp8,\n PerTensorFp8,\n};\n\ninline std::string fp8QuantizationTypeToString(Fp8QuantizationType quantization_type) {\n switch (quantization_type) {\n default:\n case Fp8QuantizationType::NoneFp8:\n return \"NoneFp8\";\n case Fp8QuantizationType::DeepSeekFp8:\n return \"DeepSeekFp8\";\n case Fp8QuantizationType::MxFp8:\n return \"MxFp8\";\n case Fp8QuantizationType::PerTensorFp8:\n return \"PerTensorFp8\";\n }\n}\n\ninline ActivationType validateAndCastActivationType(int64_t act_type) {\n TVM_FFI_ICHECK(act_type >= 0 && act_type < static_cast<int64_t>(ActivationType::InvalidType))\n << \"Invalid activation type: \" << act_type;\n return static_cast<ActivationType>(act_type);\n}\n\n// Utility function to compute the next power of two\ninline int32_t nextPowerOfTwo(float value) {\n int32_t n = static_cast<int32_t>(std::ceil(value));\n if (n <= 1) return 1;\n\n // If n is already a power of 2, return it\n if ((n & (n - 1)) == 0) return n;\n\n // Find the next power of 2\n n--;\n n |= n >> 1;\n n |= n >> 2;\n n |= n >> 4;\n n |= n >> 8;\n n |= n >> 16;\n n++;\n\n return n;\n}\n\nstd::set<int32_t> computeSelectedTileN(std::vector<int32_t> const& supported_tile_nums,\n int64_t const num_tokens, int64_t const top_k,\n int64_t const num_local_experts) {\n float const avg_tokens_per_expert = static_cast<float>(num_tokens * top_k) / num_local_experts;\n // assume supported_tile_nums is sorted\n int32_t tile_tokens_dim = std::clamp(nextPowerOfTwo(avg_tokens_per_expert),\n supported_tile_nums.front(), supported_tile_nums.back());\n auto it = std::find(supported_tile_nums.begin(), supported_tile_nums.end(), tile_tokens_dim);\n\n std::set<int32_t> selected_tile_nums;\n selected_tile_nums.insert(tile_tokens_dim);\n if (std::next(it) != supported_tile_nums.end()) {\n selected_tile_nums.insert(*std::next(it));\n if (std::next(std::next(it)) != supported_tile_nums.end()) {\n selected_tile_nums.insert(*std::next(std::next(it)));\n }\n }\n if (it != supported_tile_nums.begin()) {\n selected_tile_nums.insert(*std::prev(it));\n }\n\n return selected_tile_nums;\n}\n\nclass FusedMoeLauncher {\n protected:\n Optional<TensorView> routing_logits;\n Optional<TensorView> routing_bias;\n TensorView hidden_states;\n TensorView gemm1_weights;\n Optional<TensorView> output1_scales_scalar;\n Optional<TensorView> output1_scales_gate_scalar;\n TensorView gemm2_weights;\n Optional<TensorView> output2_scales_scalar;\n\n int64_t tile_tokens_dim{};\n int64_t routing_method_type{};\n bool use_shuffled_weight{};\n batchedGemm::gemm::MatrixLayout weight_layout{batchedGemm::gemm::MatrixLayout::MajorK};\n\n std::tuple<int, int> device_version;\n std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs> args;\n tensorrt_llm::kernels::trtllmgen_moe::MoE::MoEWorkspace workspace;\n\n btg::Dtype mDtypeAct{btg::Dtype::Bfloat16};\n btg::Dtype mDtypeWeights{btg::Dtype::Bfloat16};\n btg::Dtype mRoutingBiasDtype{\n btg::Dtype::Bfloat16}; // Dtype for expert weights in routing, based on routing bias\n ActivationType activation_type{ActivationType::Swiglu};\n\n int64_t intermediate_size_factor{2};\n\n public:\n // Constructor that initializes all TensorView members\n FusedMoeLauncher(const Optional<TensorView>& routing_logits,\n const Optional<TensorView>& routing_bias, const TensorView& hidden_states,\n const TensorView& gemm1_weights,\n const Optional<TensorView>& output1_scales_scalar,\n const Optional<TensorView>& output1_scales_gate_scalar,\n const TensorView& gemm2_weights,\n const Optional<TensorView>& output2_scales_scalar)\n : routing_logits(routing_logits),\n routing_bias(routing_bias),\n hidden_states(hidden_states),\n gemm1_weights(gemm1_weights),\n output1_scales_scalar(output1_scales_scalar),\n output1_scales_gate_scalar(output1_scales_gate_scalar),\n gemm2_weights(gemm2_weights),\n output2_scales_scalar(output2_scales_scalar),\n tile_tokens_dim{},\n routing_method_type{},\n use_shuffled_weight{},\n weight_layout{batchedGemm::gemm::MatrixLayout::MajorK},\n mDtypeAct{btg::Dtype::Bfloat16},\n mDtypeWeights{btg::Dtype::Bfloat16},\n activation_type{ActivationType::Swiglu},\n intermediate_size_factor{2} {}\n\n protected:\n // Initialize common data necessary for later.\n // May throw exception from TVM_FFI_ICHECK.\n void init_common(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, ActivationType activation_type);\n\n // Routing logits [num_tokens, num_experts]\n void check_routing_logits_shape() const {\n if (routing_logits.has_value()) {\n TVM_FFI_ICHECK_EQ(routing_logits.value().ndim(), 2) << \"routing_logits must be 2D.\";\n TVM_FFI_ICHECK_EQ(routing_logits.value().size(0), hidden_states.size(0))\n << \"routing_logits and hidden_states must have the same number of tokens.\";\n TVM_FFI_ICHECK_EQ(routing_logits.value().size(1), args->num_experts)\n << \"routing_logits dim1 must match num_experts.\";\n }\n }\n\n // Routing bias [num_experts]\n void check_routing_bias_shape() const {\n if (routing_bias.has_value()) {\n TVM_FFI_ICHECK_EQ(routing_bias.value().ndim(), 1) << \"routing_bias must be 1D.\";\n TVM_FFI_ICHECK_EQ(routing_bias.value().size(0), args->num_experts)\n << \"routing_bias has incorrect shape.\";\n }\n }\n\n // Hidden states [num_tokens, hidden_size]\n void check_hidden_states_shape() const {\n TVM_FFI_ICHECK_EQ(hidden_states.ndim(), 2) << \"hidden_states must be 2D.\";\n TVM_FFI_ICHECK_EQ(hidden_states.size(1), args->intermediate_size)\n << \"hidden_states has incorrect shape.\";\n }\n\n // GEMM1 or GEMM2 weights [num_experts, M, K] or [num_experts, K/block_k, M, block_k]\n void check_weights_shape(std::string which_weights) const {\n TensorView weights = (which_weights == \"gemm1\") ? gemm1_weights : gemm2_weights;\n if (which_weights != \"gemm1\" && which_weights != \"gemm2\") {\n TVM_FFI_LOG_AND_THROW(InternalError) << \"Internal error: which_weights = \" << which_weights;\n }\n\n int64_t Mn = 0, K = 0;\n if (weight_layout == batchedGemm::gemm::MatrixLayout::MajorK) {\n // MajorK [num_experts, M, K]\n Mn = weights.size(1);\n K = weights.size(2);\n } else if (weight_layout == batchedGemm::gemm::MatrixLayout::BlockMajorK) {\n // BlockMajorK [num_experts, K/block_k, M, block_k]\n Mn = weights.size(2);\n int64_t block_k = weights.size(3);\n K = weights.size(1) * block_k;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"Unsupported weight_layout: \" << (int)weight_layout;\n }\n if (which_weights == \"gemm1\") {\n // Gated MoE activations (e.g. Swiglu/Geglu) pack gate+up projections in GEMM1,\n // so Mn = 2 * intermediate_size and must be even.\n if (intermediate_size_factor == 2) {\n TVM_FFI_ICHECK_EQ(Mn % 2, 0) << which_weights << \" weights Mn dimension must be even.\";\n }\n // Non-gated activations (e.g. Relu2) use a single projection in GEMM1,\n // so Mn = intermediate_size. This check covers both gated and non-gated cases.\n TVM_FFI_ICHECK_EQ(args->intermediate_size * intermediate_size_factor, Mn)\n << \"intermediate_size has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(K, hidden_states.size(1))\n << which_weights << \" weights K dimension must be equal to hidden_size.\";\n } else if (which_weights == \"gemm2\") {\n // GEMM2 always consumes the post-activation hidden of size intermediate_size.\n TVM_FFI_ICHECK_EQ(K, args->intermediate_size)\n << which_weights << \" weights K dimension must be equal to intermediate_size.\";\n }\n }\n\n void check_routing_common() const {\n TVM_FFI_ICHECK(args->top_k > 0 && args->top_k <= args->num_experts)\n << \"top_k must be between 1 and num_experts\";\n TVM_FFI_ICHECK(args->local_num_experts > 0 && args->local_num_experts <= args->num_experts)\n << \"local_num_experts must be between 1 and num_experts\";\n TVM_FFI_ICHECK(args->local_expert_offset >= 0 &&\n args->local_expert_offset + args->local_num_experts <= args->num_experts)\n << \"expert offset and count must be within valid range\";\n\n check_routing_logits_shape();\n\n if (routing_bias.has_value()) {\n check_routing_bias_shape();\n }\n }\n\n // Routing phase workspace tensors (allocated in prepare_routing() or prepare_routing_common())\n Tensor num_tokens_per_expert;\n Tensor total_num_padded_tokens;\n Tensor expanded_idx_to_permuted_idx;\n Tensor permuted_idx_to_token_idx;\n Tensor expert_weights;\n Tensor expert_indexes;\n Tensor expert_count_histogram;\n Tensor cta_idx_xy_to_batch_idx;\n Tensor cta_idx_xy_to_mn_limit;\n Tensor num_non_exiting_ctas;\n\n void prepare_routing_common() {\n // Allocate routing phase workspace tensors\n num_tokens_per_expert = alloc_tensor({args->num_experts}, dl_int32, hidden_states.device());\n int32_t max_num_padded_tokens =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::getMaxPermutedPaddedCount(\n args->num_tokens, args->top_k, args->num_experts, tile_tokens_dim);\n\n total_num_padded_tokens = alloc_tensor({1}, dl_int32, hidden_states.device());\n\n expanded_idx_to_permuted_idx =\n alloc_tensor({args->num_tokens * args->top_k}, dl_int32, hidden_states.device());\n\n permuted_idx_to_token_idx =\n alloc_tensor({max_num_padded_tokens}, dl_int32, hidden_states.device());\n\n expert_indexes =\n alloc_tensor({args->num_tokens, args->top_k}, dl_int32, hidden_states.device());\n\n // expert_weights allocation should be done by derived class since data type could vary\n\n int64_t const size_of_expert_count_histogram = std::max(args->num_experts * 2, 256 * 2);\n expert_count_histogram = alloc_tensor({size_of_expert_count_histogram},\n dl_int32, // 256 is the max number of threads per block\n // and max number of experts\n hidden_states.device());\n\n int32_t max_num_ctas = tensorrt_llm::kernels::trtllmgen_moe::Routing::getMaxNumCtasInBatchDim(\n args->num_tokens, args->top_k, args->num_experts, tile_tokens_dim);\n\n cta_idx_xy_to_batch_idx = alloc_tensor({max_num_ctas}, dl_int32, hidden_states.device());\n\n cta_idx_xy_to_mn_limit = alloc_tensor({max_num_ctas}, dl_int32, hidden_states.device());\n\n num_non_exiting_ctas = alloc_tensor({1}, dl_int32, hidden_states.device());\n\n workspace.total_num_padded_tokens = static_cast<int*>(total_num_padded_tokens.data_ptr());\n workspace.total_max_padded_tokens = max_num_padded_tokens;\n workspace.ProjUpTileN = tile_tokens_dim;\n workspace.routing_expert_indexes = static_cast<int*>(expert_indexes.data_ptr());\n workspace.permuted_idx_size = static_cast<int*>(total_num_padded_tokens.data_ptr());\n workspace.expanded_idx_to_permuted_idx =\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr());\n workspace.permuted_idx_to_token_idx = static_cast<int*>(permuted_idx_to_token_idx.data_ptr());\n // workspace.expert_weights will be set by derived class after expert_weights allocation\n workspace.cta_idx_xy_to_batch_idx = static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr());\n workspace.cta_idx_xy_to_mn_limit = static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr());\n workspace.num_non_exiting_ctas = static_cast<int*>(num_non_exiting_ctas.data_ptr());\n }\n\n void check_moe_common() const {\n // Hidden states [num_tokens, hidden_size]\n TVM_FFI_ICHECK_EQ(hidden_states.ndim(), 2) << \"hidden_states must be 2D.\";\n }\n\n // MoE computation phase workspace tensors (allocated in prepare_moe() or prepare_moe_common())\n Tensor gemm1_output;\n Tensor activation_output;\n Tensor gemm2_output;\n Tensor workspace_fc1;\n Tensor workspace_fc2;\n Tensor output;\n int64_t moe_tactic{-1};\n std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner> moe_runner;\n\n void prepare_moe_common(int64_t& moe_tactic) {\n using RunnerType = tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner;\n // For FP8 block-scale (E4m3 activations, E4m3 weights) with DeepSeek FP8, use the\n // weights-only Runner constructor to match the original kernel path and numerics.\n if (this->mDtypeAct == btg::Dtype::E4m3 && this->mDtypeWeights == btg::Dtype::E4m3 &&\n args->mUseDeepSeekFp8) {\n moe_runner = std::make_unique<RunnerType>(this->mDtypeWeights, args->mUseDeepSeekFp8,\n (int32_t)tile_tokens_dim, this->use_shuffled_weight,\n this->weight_layout);\n } else {\n moe_runner = std::make_unique<RunnerType>(\n this->mDtypeAct, this->mDtypeWeights, args->mUseDeepSeekFp8, (int32_t)tile_tokens_dim,\n this->activation_type, this->use_shuffled_weight, this->weight_layout);\n }\n\n if (moe_tactic == -1) {\n moe_tactic = moe_runner->getDefaultValidConfigIndex(\n args->top_k, args->hidden_size, args->intermediate_size, args->local_num_experts,\n args->num_tokens);\n }\n auto valid_cfgs =\n moe_runner->getValidConfigIndices(args->top_k, args->hidden_size, args->intermediate_size,\n args->local_num_experts, args->num_tokens);\n auto valid_it = std::find(valid_cfgs.begin(), valid_cfgs.end(), moe_tactic);\n FLASHINFER_CHECK(valid_it != valid_cfgs.end(), \"Invalid MoE tactic \", moe_tactic,\n \" for tile_N=\", tile_tokens_dim, \". Number of valid tactics for this tile is \",\n valid_cfgs.size(),\n \". This often indicates a stale or mismatched autotuner cache entry.\");\n this->moe_tactic = moe_tactic;\n\n auto workspace_sizes = moe_runner->getWorkspaceSizeInBytes(*args, moe_tactic);\n workspace_fc1 = alloc_tensor({std::get<0>(workspace_sizes)}, dl_int8, hidden_states.device());\n workspace_fc2 = alloc_tensor({std::get<1>(workspace_sizes)}, dl_int8, hidden_states.device());\n workspace.bmm1_workspace = workspace_fc1.data_ptr();\n workspace.bmm2_workspace = workspace_fc2.data_ptr();\n }\n\n public:\n virtual void check_routing() const = 0;\n virtual void prepare_routing() = 0;\n virtual void check_moe() const = 0;\n virtual void prepare_moe(int64_t& moe_tactic) = 0;\n\n // Main entry point for all the executions.\n // Do initializations prior to calling this as the initializations are different for bf16, fp8 and\n // fp4. The executions are non-blocking by default.\n virtual Array<Tensor> run(int64_t moe_tactic, bool enable_pdl = true,\n bool use_routing_scales_on_input = false,\n bool use_deep_seek_fp8 = false) {\n check_routing();\n prepare_routing();\n\n // Execute routing\n tensorrt_llm::kernels::trtllmgen_moe::Routing::Runner routing_runner(tile_tokens_dim);\n cudaStream_t routing_stream = get_stream(hidden_states.device());\n\n routing_runner.run(\n args->routing_logits, args->routing_bias, args->num_tokens, args->num_experts, args->top_k,\n args->n_group, args->topk_group, args->local_expert_offset, args->local_num_experts,\n args->routed_scaling_factor, workspace.routing_expert_indexes,\n static_cast<int*>(expert_count_histogram.data_ptr()),\n static_cast<int*>(total_num_padded_tokens.data_ptr()),\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr()),\n nullptr /*permuted_idx_to_expanded_idx.data_ptr()*/,\n static_cast<int*>(permuted_idx_to_token_idx.data_ptr()), workspace.expert_weights,\n static_cast<int*>(num_tokens_per_expert.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr()),\n static_cast<int*>(num_non_exiting_ctas.data_ptr()), args->mDtypeElt, mRoutingBiasDtype,\n use_routing_scales_on_input, use_deep_seek_fp8,\n static_cast<RoutingMethodType>(routing_method_type), routing_stream);\n\n check_moe();\n prepare_moe(moe_tactic);\n\n cudaStream_t moe_stream = get_stream(hidden_states.device());\n moe_runner->run(*args, workspace, hidden_states.device().device_id, moe_stream, moe_tactic,\n enable_pdl);\n\n if (args->do_finalize) {\n return {output};\n }\n return {gemm2_output, FusedMoeLauncher::expert_weights, expanded_idx_to_permuted_idx};\n }\n};\n\nvoid FusedMoeLauncher::init_common(\n std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, ActivationType activation_type) {\n // Check devicearchitecture: Blackwell (SM 10.x) required\n auto device = hidden_states.device().device_id;\n int major = 0, minor = 0;\n cudaDeviceGetAttribute(&major, cudaDevAttrComputeCapabilityMajor, device);\n cudaDeviceGetAttribute(&minor, cudaDevAttrComputeCapabilityMinor, device);\n TVM_FFI_ICHECK(major == 10 || major == 12)\n << \"MoE kernel requires SM 10.x or SM 12.x architecture. Current device has SM \" << major\n << minor;\n this->device_version = std::make_tuple(major, minor);\n\n args->routing_logits = routing_logits.has_value() ? routing_logits.value().data_ptr() : nullptr;\n args->routing_bias = routing_bias.has_value() ? routing_bias.value().data_ptr() : nullptr;\n args->hidden_states = hidden_states.data_ptr();\n args->gemm1_weights = gemm1_weights.data_ptr();\n args->gemm2_weights = gemm2_weights.data_ptr();\n\n this->args = std::move(args);\n this->tile_tokens_dim = tile_tokens_dim;\n this->routing_method_type = routing_method_type;\n this->use_shuffled_weight = use_shuffled_weight;\n TVM_FFI_ICHECK(0 <= weight_layout && weight_layout <= 2)\n << \"the value of weight_layout is not recognized\";\n this->weight_layout = static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout);\n this->activation_type = activation_type;\n this->intermediate_size_factor = isGatedActivation(activation_type) ? 2 : 1;\n}\n\nclass Bf16MoeLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 5> mSupportedTileNums = {8, 16, 32, 64, 128};\n\n Bf16MoeLauncher(Optional<TensorView> const& routing_logits,\n Optional<TensorView> const& routing_bias, TensorView const& expert_indices,\n TensorView const& expert_weights, TensorView const& hidden_states,\n TensorView const& gemm1_weights, TensorView const& gemm2_weights)\n : FusedMoeLauncher(routing_logits, routing_bias, hidden_states, gemm1_weights,\n Optional<TensorView>(), Optional<TensorView>(), gemm2_weights,\n Optional<TensorView>()),\n expert_indices(expert_indices),\n expert_weights(expert_weights) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout) {\n constexpr ActivationType activation_type =\n ActivationType::Swiglu; // not exposed in api for now\n\n // Do base class init and perform common checks\n FusedMoeLauncher::init_common(std::move(args), tile_tokens_dim, routing_method_type,\n use_shuffled_weight, weight_layout, activation_type);\n }\n\n void check_routing() const override {\n FusedMoeLauncher::check_routing_common();\n if (expert_indices.ndim() == 2 && expert_indices.size(0) > 0) {\n // Pre-computed routing: expert_indices is a packed tensor\n // Format: (expert_id << 16) | (weight_bf16.view(int16))\n TVM_FFI_ICHECK_EQ(expert_indices.ndim(), 2) << \"expert_indices must be 2D.\";\n TVM_FFI_ICHECK_EQ(expert_indices.size(0), hidden_states.size(0))\n << \"expert_indices and hidden_states must have same number of tokens.\";\n TVM_FFI_ICHECK_EQ(expert_indices.size(1), args->top_k)\n << \"expert_indices dim1 must match top_k.\";\n TVM_FFI_ICHECK_EQ(expert_indices.dtype(), dl_int32) << \"expert_indices must be int32.\";\n }\n\n // TODO n_group, topk_group validation?\n }\n\n void prepare_routing() override {\n FusedMoeLauncher::prepare_routing_common();\n\n args->mDtypeElt = btg::Dtype::Bfloat16;\n args->mUseDeepSeekFp8 = false;\n\n // Set expert weights dtype based on routing bias\n auto const routing_bias_dtype =\n routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool has_precomputed_indices = expert_indices.ndim() == 2 && expert_indices.size(0) > 0;\n if (has_precomputed_indices) {\n // Use expert_indices directly\n workspace.routing_expert_indexes =\n static_cast<int*>(const_cast<void*>(expert_indices.data_ptr()));\n }\n bool has_precomputed_weights = expert_weights.ndim() == 2 && expert_weights.size(0) > 0;\n if (has_precomputed_weights) {\n workspace.expert_weights = const_cast<void*>(expert_weights.data_ptr());\n } else {\n FusedMoeLauncher::expert_weights =\n alloc_tensor({args->num_tokens, args->top_k}, dl_bfloat16, hidden_states.device());\n workspace.expert_weights = FusedMoeLauncher::expert_weights.data_ptr();\n }\n }\n\n void check_moe() const override {\n FusedMoeLauncher::check_moe_common();\n\n TVM_FFI_ICHECK(weight_layout == batchedGemm::gemm::MatrixLayout::BlockMajorK)\n << \"BF16 Moe: weight_layout must be BlockMajorK\";\n check_weights_shape(\"gemm1\");\n check_weights_shape(\"gemm2\");\n\n TVM_FFI_ICHECK_EQ(args->intermediate_size % 128, 0)\n << \"the second dimension of weights must be a multiple of 128.\";\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n int32_t max_num_padded_tokens = workspace.total_max_padded_tokens;\n gemm1_output = alloc_tensor({max_num_padded_tokens, args->intermediate_size}, dl_bfloat16,\n hidden_states.device());\n activation_output = alloc_tensor({max_num_padded_tokens, args->intermediate_size}, dl_bfloat16,\n hidden_states.device());\n gemm2_output = alloc_tensor({max_num_padded_tokens, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n workspace.hidden_states_scale_linear = nullptr;\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = nullptr;\n workspace.activation_output = activation_output.data_ptr();\n workspace.activation_output_scale = nullptr;\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n\n if (args->output == nullptr) {\n output =\n alloc_tensor({args->num_tokens, args->hidden_size}, dl_bfloat16, hidden_states.device());\n args->output = output.data_ptr();\n }\n args->output_scale = nullptr;\n }\n\n static Array<Array<int64_t>> getValidConfigs(int64_t top_k, int64_t hidden_size,\n int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens, int64_t act_type,\n bool use_shuffled_weight, int64_t weight_layout) {\n Array<Array<int64_t>> valid_configs;\n\n std::vector<int32_t> supported_tile_nums(mSupportedTileNums.begin(), mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n auto moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n btg::Dtype::Bfloat16, // dtype_act\n btg::Dtype::Bfloat16, // dtype_weights\n false, // useDeepSeekFp8\n tile_N, static_cast<ActivationType>(act_type), use_shuffled_weight,\n static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout));\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n\n private:\n TensorView expert_weights;\n TensorView expert_indices;\n};\n\nclass Fp8PerTensorLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 5> mSupportedTileNums = {8, 16, 32, 64, 128};\n\n // Constructor that passes TensorView parameters to base constructor\n Fp8PerTensorLauncher(TensorView const& routing_logits, Optional<TensorView> const& routing_bias,\n TensorView const& hidden_states, TensorView const& gemm1_weights,\n TensorView const& output1_scales_scalar,\n TensorView const& output1_scales_gate_scalar,\n TensorView const& gemm2_weights, TensorView const& output2_scales_scalar)\n : FusedMoeLauncher(Optional<TensorView>(routing_logits), routing_bias, hidden_states,\n gemm1_weights, Optional<TensorView>(output1_scales_scalar),\n Optional<TensorView>(output1_scales_gate_scalar), gemm2_weights,\n Optional<TensorView>(output2_scales_scalar)),\n use_routing_scales_on_input(false) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, bool use_routing_scales_on_input_param,\n ActivationType activation_type) {\n this->use_routing_scales_on_input = use_routing_scales_on_input_param;\n\n auto dtype = hidden_states.dtype();\n if (dtype == dl_float16) {\n mDtypeAct = btg::Dtype::Fp16;\n } else if (dtype == dl_bfloat16) {\n mDtypeAct = btg::Dtype::Bfloat16;\n } else if (dtype == dl_float8_e4m3fn) {\n mDtypeAct = btg::Dtype::E4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for FP8 MoE.\";\n }\n mDtypeWeights = btg::Dtype::E4m3;\n\n FusedMoeLauncher::init_common(std::move(args), tile_tokens_dim, routing_method_type,\n use_shuffled_weight, weight_layout, activation_type);\n }\n\n void check_routing() const override { FusedMoeLauncher::check_routing_common(); }\n\n void prepare_routing() override {\n FusedMoeLauncher::prepare_routing_common();\n\n auto dtype = hidden_states.dtype();\n if (dtype == dl_float16) {\n args->mDtypeElt = btg::Dtype::Fp16;\n } else if (dtype == dl_bfloat16) {\n args->mDtypeElt = btg::Dtype::Bfloat16;\n } else if (dtype == dl_float8_e4m3fn) {\n args->mDtypeElt = btg::Dtype::E4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for MoE.\";\n }\n\n args->mDtypeOut = btg::Dtype::Bfloat16;\n args->mUseDeepSeekFp8 = false;\n\n auto const routing_bias_dtype =\n routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n\n expert_weights =\n alloc_tensor({args->num_tokens, args->top_k}, dl_bfloat16, hidden_states.device());\n\n workspace.expert_weights = expert_weights.data_ptr();\n if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::Llama4) {\n workspace.token_scales = expert_weights.data_ptr(); // Consumed by permuteGemm1 kernel\n }\n }\n\n void check_moe() const override {\n FusedMoeLauncher::check_moe_common();\n\n TVM_FFI_ICHECK(output1_scales_scalar.has_value())\n << \"output1_scales_scalar is required for FP8 MoE\";\n TVM_FFI_ICHECK_EQ(output1_scales_scalar.value().dtype(), dl_float32)\n << \"output1_scales_scalar must be float.\";\n TVM_FFI_ICHECK_EQ(output1_scales_scalar.value().ndim(), 1)\n << \"output1_scales_scalar must be 1D.\";\n TVM_FFI_ICHECK_EQ(output1_scales_scalar.value().size(0), args->local_num_experts)\n << \"output1_scales_scalar has incorrect dim 0.\";\n\n TVM_FFI_ICHECK(output1_scales_gate_scalar.has_value())\n << \"output1_scales_gate_scalar is required for FP8 MoE\";\n TVM_FFI_ICHECK_EQ(output1_scales_gate_scalar.value().dtype(), dl_float32)\n << \"output1_scales_gate_scalar must be float.\";\n TVM_FFI_ICHECK_EQ(output1_scales_gate_scalar.value().ndim(), 1)\n << \"output1_scales_gate_scalar must be 1D.\";\n TVM_FFI_ICHECK_EQ(output1_scales_gate_scalar.value().size(0), args->local_num_experts)\n << \"output1_scales_gate_scalar has incorrect dim 0.\";\n\n TVM_FFI_ICHECK(output2_scales_scalar.has_value())\n << \"output2_scales_scalar is required for FP8 MoE\";\n TVM_FFI_ICHECK_EQ(output2_scales_scalar.value().dtype(), dl_float32)\n << \"output2_scales_scalar must be float.\";\n TVM_FFI_ICHECK_EQ(output2_scales_scalar.value().ndim(), 1)\n << \"output2_scales_scalar must be 1D.\";\n TVM_FFI_ICHECK_EQ(output2_scales_scalar.value().size(0), args->local_num_experts)\n << \"output2_scales_scalar has incorrect dim 0.\";\n\n TVM_FFI_ICHECK(hidden_states.dtype() == dl_float8_e4m3fn ||\n hidden_states.dtype() == dl_float16 || hidden_states.dtype() == dl_bfloat16)\n << \"FP8 MoE: hidden_states must be float8_e4m3fn, float16, or bfloat16.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 MoE: gemm1_weights must be float8_e4m3fn.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 MoE: gemm2_weights must be float8_e4m3fn.\";\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n int32_t max_num_padded_tokens_gemm1 = workspace.total_max_padded_tokens + args->num_experts;\n int32_t max_num_padded_tokens_gemm2 = workspace.total_max_padded_tokens;\n\n gemm1_output = alloc_tensor({max_num_padded_tokens_gemm1, 2 * args->intermediate_size},\n dl_uint8, hidden_states.device());\n gemm1_output_scale =\n alloc_tensor({2 * args->intermediate_size / 128, max_num_padded_tokens_gemm1}, dl_float32,\n hidden_states.device());\n\n activation_output = alloc_tensor({max_num_padded_tokens_gemm1, args->intermediate_size},\n dl_uint8, hidden_states.device());\n activation_output_scale =\n alloc_tensor({args->intermediate_size / 128, max_num_padded_tokens_gemm1}, dl_float32,\n hidden_states.device());\n\n gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n workspace.hidden_states_scale_linear = nullptr;\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = static_cast<float*>(gemm1_output_scale.data_ptr());\n workspace.activation_output = activation_output.data_ptr();\n workspace.activation_output_scale = static_cast<float*>(activation_output_scale.data_ptr());\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n\n if (args->output == nullptr) {\n output =\n alloc_tensor({args->num_tokens, args->hidden_size}, dl_bfloat16, hidden_states.device());\n args->output = output.data_ptr();\n }\n args->output_scale = nullptr;\n\n // Set scale pointers\n TVM_FFI_ICHECK(output1_scales_scalar.has_value());\n TVM_FFI_ICHECK(output1_scales_gate_scalar.has_value());\n TVM_FFI_ICHECK(output2_scales_scalar.has_value());\n\n args->output1_scales_scalar = static_cast<float*>(output1_scales_scalar.value().data_ptr());\n args->output1_scales_gate_scalar =\n static_cast<float*>(output1_scales_gate_scalar.value().data_ptr());\n args->output2_scales_scalar = static_cast<float*>(output2_scales_scalar.value().data_ptr());\n }\n\n private:\n bool use_routing_scales_on_input;\n Tensor gemm1_output_scale;\n Tensor activation_output_scale;\n\n public:\n static Array<Array<int64_t>> getValidConfigs(int64_t top_k, int64_t hidden_size,\n int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens, int64_t act_type,\n bool use_shuffled_weight, int64_t weight_layout,\n btg::Dtype dtype_act, btg::Dtype dtype_weights) {\n Array<Array<int64_t>> valid_configs;\n\n std::vector<int32_t> supported_tile_nums(mSupportedTileNums.begin(), mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n auto moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n dtype_act, dtype_weights,\n false, // useDeepSeekFp8\n tile_N, static_cast<ActivationType>(act_type), use_shuffled_weight,\n static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout));\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n};\n\nclass Fp8BlockScaleLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 5> mBaseSupportedTileNums = {8, 16, 32, 64, 128};\n\n static std::vector<int32_t> getSupportedTileNums(Fp8QuantizationType quantization_type) {\n std::vector<int32_t> tiles(mBaseSupportedTileNums.begin(), mBaseSupportedTileNums.end());\n if (quantization_type == Fp8QuantizationType::MxFp8) {\n tiles.push_back(256);\n }\n return tiles;\n }\n\n Fp8BlockScaleLauncher(Optional<TensorView> const& routing_logits,\n Optional<TensorView> const& routing_bias, TensorView const& hidden_states,\n TensorView const& hidden_states_scale, TensorView const& gemm1_weights,\n TensorView const& gemm1_weights_scale, TensorView const& gemm2_weights,\n TensorView const& gemm2_weights_scale, TensorView const& expert_indices,\n TensorView const& expert_weights, Fp8QuantizationType quantization_type)\n : FusedMoeLauncher(routing_logits, routing_bias, hidden_states, gemm1_weights,\n Optional<TensorView>(), Optional<TensorView>(), gemm2_weights,\n Optional<TensorView>()),\n hidden_states_scale(hidden_states_scale),\n gemm1_weights_scale(gemm1_weights_scale),\n gemm2_weights_scale(gemm2_weights_scale),\n expert_indices(expert_indices),\n expert_weights(expert_weights),\n quantization_type(quantization_type) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, ActivationType activation_type) {\n if (quantization_type == Fp8QuantizationType::MxFp8) {\n mDtypeAct = btg::Dtype::MxE4m3;\n mDtypeWeights = btg::Dtype::MxE4m3;\n } else {\n mDtypeAct = btg::Dtype::E4m3;\n mDtypeWeights = btg::Dtype::E4m3;\n }\n\n auto dtype = hidden_states.dtype();\n if (dtype == dl_float16) {\n args->mDtypeElt = btg::Dtype::Fp16;\n } else if (dtype == dl_bfloat16) {\n args->mDtypeElt = btg::Dtype::Bfloat16;\n } else if (dtype == dl_float8_e4m3fn) {\n args->mDtypeElt = btg::Dtype::E4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for MoE.\";\n }\n\n // Output is always bfloat16 for FP8 block scale\n args->mDtypeOut = btg::Dtype::Bfloat16;\n\n FusedMoeLauncher::init_common(std::move(args), tile_tokens_dim, routing_method_type,\n use_shuffled_weight, weight_layout, activation_type);\n }\n\n void check_routing() const override {\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n if (expert_indices.ndim() == 2 && expert_indices.size(0) > 0) {\n // Pre-computed routing: expert_indices is a packed tensor\n // Format: (expert_id << 16) | (weight_bf16.view(int16))\n TVM_FFI_ICHECK_EQ(expert_indices.ndim(), 2) << \"expert_indices must be 2D.\";\n TVM_FFI_ICHECK_EQ(expert_indices.size(0), hidden_states.size(0))\n << \"expert_indices and hidden_states must have same number of tokens.\";\n TVM_FFI_ICHECK_EQ(expert_indices.size(1), args->top_k)\n << \"expert_indices dim1 must match top_k.\";\n TVM_FFI_ICHECK_EQ(expert_indices.dtype(), dl_int32) << \"expert_indices must be int32.\";\n }\n\n FusedMoeLauncher::check_routing_common();\n\n if (static_cast<RoutingMethodType>(routing_method_type) != RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK(args->n_group <= 1)\n << \"Current routing kernel (no groups) only supports n_group <= 1\";\n TVM_FFI_ICHECK(args->topk_group <= 1)\n << \"Current routing kernel (no groups) only supports topk_group <= 1\";\n }\n\n if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK(args->n_group != 0) << \"n_group should not be zero for DeepSeekV3 routing\";\n TVM_FFI_ICHECK(args->topk_group != 0) << \"if n_group is given, topk_group must be given\";\n TVM_FFI_ICHECK_EQ(args->num_experts % args->n_group, 0)\n << \"num_experts must be divisible by n_group\";\n // DeepSeekV3 routing supports top_k up to:\n // - 8 when num_experts <= 384 (NumKimiK2Experts)\n // - 22 when num_experts > 384 (NumNemotronExperts path)\n // Keep this in sync with LAUNCH_ROUTING_DEEPSEEK in trtllm_fused_moe_routing_deepseek.cu.\n constexpr int32_t kNumKimiK2Experts = 384; // same as in trtllm_fused_moe_routing_deepseek.cu\n int32_t max_supported_top_k = args->num_experts <= kNumKimiK2Experts ? 8 : 22;\n TVM_FFI_ICHECK(args->top_k <= max_supported_top_k && args->top_k > 0)\n << \"Current routing kernel (with groups) only supports top_k<=\" << max_supported_top_k\n << \" && top_k>0 for num_experts=\" << args->num_experts << \".\";\n TVM_FFI_ICHECK(args->topk_group <= 4 && args->topk_group > 0)\n << \"Current routing kernel only (with groups) supports topk_group<=4 && topk_group > 0.\";\n TVM_FFI_ICHECK_LE(args->topk_group, args->n_group)\n << \"n_group must not be smaller than topk_group.\";\n TVM_FFI_ICHECK_LT(args->top_k, (args->topk_group * args->num_experts / args->n_group))\n << \"top_k must be less than total number of experts in selected groups\";\n } else if (static_cast<RoutingMethodType>(routing_method_type) ==\n RoutingMethodType::Renormalize ||\n static_cast<RoutingMethodType>(routing_method_type) ==\n RoutingMethodType::RenormalizeNaive) {\n TVM_FFI_ICHECK(args->top_k <= 32 && args->top_k > 0)\n << \"Current routing kernel (no groups, renormalize) only supports top_k<=10 && top_k>0.\";\n } else if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::Llama4) {\n TVM_FFI_ICHECK_EQ(args->top_k, 1)\n << \"Current routing kernel (no groups, Llama4) only supports top_k=1.\";\n }\n\n TVM_FFI_ICHECK_EQ(args->num_experts % 4, 0)\n << \"Routing kernel expects that num_experts must be divisible by 4\";\n TVM_FFI_ICHECK_GT(args->num_experts, args->top_k) << \"num_experts must be greater than top_k\";\n TVM_FFI_ICHECK_LE(args->local_num_experts + args->local_expert_offset, args->num_experts)\n << \"num_experts must be greater or equal to local_num_experts + local_expert_offset\";\n }\n\n void prepare_routing() override {\n FusedMoeLauncher::prepare_routing_common();\n\n auto dtype = hidden_states.dtype();\n if (dtype == dl_float16) {\n args->mDtypeElt = btg::Dtype::Fp16;\n } else if (dtype == dl_bfloat16) {\n args->mDtypeElt = btg::Dtype::Bfloat16;\n } else if (dtype == dl_float8_e4m3fn) {\n args->mDtypeElt = btg::Dtype::E4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for MoE.\";\n }\n\n args->mUseDeepSeekFp8 = quantization_type == Fp8QuantizationType::DeepSeekFp8;\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool has_precomputed_indices = expert_indices.ndim() == 2 && expert_indices.size(0) > 0;\n if (has_precomputed_indices) {\n // Use expert_indices directly\n workspace.routing_expert_indexes =\n static_cast<int*>(const_cast<void*>(expert_indices.data_ptr()));\n } else {\n // Use routing_logits directly\n args->routing_logits = static_cast<float*>(routing_logits.value().data_ptr());\n }\n // Set expert weights dtype based on routing bias\n auto const routing_bias_dtype =\n routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool has_precomputed_weights = expert_weights.ndim() == 2 && expert_weights.size(0) > 0;\n if (!has_precomputed_weights) {\n // Allocate expert_weights buffer for routing output\n FusedMoeLauncher::expert_weights =\n alloc_tensor({args->num_tokens, args->top_k}, dl_bfloat16, hidden_states.device());\n workspace.expert_weights = FusedMoeLauncher::expert_weights.data_ptr();\n } else {\n workspace.expert_weights = const_cast<void*>(expert_weights.data_ptr());\n }\n }\n\n void check_moe() const override {\n FusedMoeLauncher::check_moe_common();\n\n TVM_FFI_ICHECK_EQ(hidden_states.dtype(), dl_float8_e4m3fn) << \"hidden_states must be fp8.\";\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(hidden_states_scale.dtype(), dl_float32)\n << \"hidden_states_scale must be float.\";\n TVM_FFI_ICHECK_EQ(hidden_states_scale.ndim(), 2) << \"hidden_states_scale must be 2D.\";\n TVM_FFI_ICHECK_EQ(hidden_states_scale.size(0), hidden_states.size(1) / 128)\n << \"hidden_states_scale dim0 must match hidden_states dim1 / 128.\";\n TVM_FFI_ICHECK_EQ(hidden_states_scale.size(1), args->num_tokens)\n << \"hidden_states_scale dim1 must match num_tokens.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_CHECK(weight_layout == batchedGemm::gemm::MatrixLayout::MajorK,\n \"weight_layout must be MajorK for MxFp8.\");\n TVM_FFI_ICHECK_EQ(hidden_states_scale.dtype(), dl_uint8);\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_float8_e4m3fn) << \"gemm1_weights must be fp8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_float8_e4m3fn) << \"gemm2_weights must be fp8.\";\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_float32)\n << \"gemm1_weights_scale must be float.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.ndim(), 3) << \"gemm1_weights_scale must be 3D.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.size(0), args->local_num_experts)\n << \"gemm1_weights_scale has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(args->intermediate_size % 128, 0)\n << \"intermediate_size must be a multiple of 128.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.size(1),\n intermediate_size_factor * args->intermediate_size / 128)\n << \"gemm1_weights_scale has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.size(2), args->hidden_size / 128)\n << \"gemm1_weights_scale has incorrect shape.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_uint8)\n << \"gemm1_weights_scale must be uint8.\";\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_float32)\n << \"gemm2_weights_scale must be float.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.ndim(), 3) << \"gemm2_weights_scale must be 3D.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.size(0), args->local_num_experts)\n << \"gemm2_weights_scale has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.size(1), args->hidden_size / 128)\n << \"gemm2_weights_scale has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.size(2), args->intermediate_size / 128)\n << \"gemm2_weights_scale has incorrect shape.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_uint8)\n << \"gemm2_weights_scale must be uint8.\";\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n\n check_weights_shape(\"gemm1\");\n check_weights_shape(\"gemm2\");\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(args->intermediate_size % 128, 0)\n << \"intermediate_size must be a multiple of 128.\";\n }\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n // Calculate max_num_padded_tokens for gemm1 and gemm2 using maybeGetMinTokenCount\n int32_t max_num_padded_tokens_gemm1 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->intermediate_size,\n btg::dtypeGetNumBits(args->mDtypeElt));\n int32_t max_num_padded_tokens_gemm2 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->hidden_size,\n btg::dtypeGetNumBits(args->mDtypeOut));\n\n gemm1_output = alloc_tensor(\n {max_num_padded_tokens_gemm1, intermediate_size_factor * args->intermediate_size}, dl_uint8,\n hidden_states.device());\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n gemm1_output_scale = alloc_tensor({intermediate_size_factor * args->intermediate_size / 128,\n workspace.total_max_padded_tokens},\n dl_float32, hidden_states.device());\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n // MxFP8 fuses the activation so no need for intermediate_size_factor\n int64_t sf_size = tensorrt_llm::computeSwizzledLayoutSFSize(max_num_padded_tokens_gemm1,\n args->intermediate_size / 32);\n gemm1_output_scale = alloc_tensor({sf_size}, dl_uint8, hidden_states.device());\n }\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n activation_output = alloc_tensor({max_num_padded_tokens_gemm1, args->intermediate_size},\n dl_uint8, hidden_states.device());\n activation_output_scale =\n alloc_tensor({args->intermediate_size / 128, max_num_padded_tokens_gemm1}, dl_float32,\n hidden_states.device());\n }\n\n gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n workspace.hidden_states_scale_linear = nullptr;\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = static_cast<float*>(gemm1_output_scale.data_ptr());\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n workspace.activation_output = activation_output.data_ptr();\n workspace.activation_output_scale = static_cast<float*>(activation_output_scale.data_ptr());\n }\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n\n if (args->output == nullptr) {\n output =\n alloc_tensor({args->num_tokens, args->hidden_size}, dl_bfloat16, hidden_states.device());\n args->output = output.data_ptr();\n }\n args->output_scale = nullptr;\n\n args->hidden_states_scale = static_cast<float*>(hidden_states_scale.data_ptr());\n args->gemm1_weights_scale = static_cast<float*>(gemm1_weights_scale.data_ptr());\n args->gemm2_weights_scale = static_cast<float*>(gemm2_weights_scale.data_ptr());\n }\n\n private:\n TensorView hidden_states_scale;\n TensorView gemm1_weights_scale;\n TensorView gemm2_weights_scale;\n Tensor gemm1_output_scale;\n Tensor activation_output_scale;\n TensorView expert_indices;\n TensorView expert_weights;\n Fp8QuantizationType quantization_type;\n\n public:\n // Override to handle pre-computed routing\n Array<Tensor> run(int64_t moe_tactic, bool enable_pdl = true,\n bool use_routing_scales_on_input = false,\n bool use_deep_seek_fp8 = false) override {\n check_routing();\n prepare_routing();\n\n cudaStream_t routing_stream = get_stream(hidden_states.device());\n tensorrt_llm::kernels::trtllmgen_moe::Routing::Runner routing_runner(tile_tokens_dim);\n\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool use_precomputed = expert_indices.ndim() == 2 && expert_indices.size(0) > 0;\n // When using pre-computed routing, pass nullptr as routing_logits to tell the\n // routing runner to use the pre-computed expert indices from workspace.routing_expert_indexes\n routing_runner.run(\n use_precomputed ? nullptr : args->routing_logits, args->routing_bias, args->num_tokens,\n args->num_experts, args->top_k, args->n_group, args->topk_group, args->local_expert_offset,\n args->local_num_experts, args->routed_scaling_factor, workspace.routing_expert_indexes,\n static_cast<int*>(expert_count_histogram.data_ptr()),\n static_cast<int*>(total_num_padded_tokens.data_ptr()),\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr()),\n nullptr /*permuted_idx_to_expanded_idx.data_ptr()*/,\n static_cast<int*>(permuted_idx_to_token_idx.data_ptr()), workspace.expert_weights,\n static_cast<int*>(num_tokens_per_expert.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr()),\n static_cast<int*>(num_non_exiting_ctas.data_ptr()), args->mDtypeElt, mRoutingBiasDtype,\n use_routing_scales_on_input, use_deep_seek_fp8,\n static_cast<RoutingMethodType>(routing_method_type), routing_stream);\n\n check_moe();\n prepare_moe(moe_tactic);\n\n cudaStream_t moe_stream = get_stream(hidden_states.device());\n moe_runner->run(*args, workspace, hidden_states.device().device_id, moe_stream, moe_tactic,\n enable_pdl);\n\n if (args->do_finalize) {\n return {output};\n }\n return {gemm2_output, FusedMoeLauncher::expert_weights, expanded_idx_to_permuted_idx};\n }\n\n static Array<Array<int64_t>> getValidConfigs(\n int64_t top_k, int64_t hidden_size, int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens, bool use_shuffled_weight, int64_t weight_layout, btg::Dtype dtype_act,\n btg::Dtype dtype_weights, Fp8QuantizationType quantization_type, int64_t act_type) {\n Array<Array<int64_t>> valid_configs;\n auto activation_type = validateAndCastActivationType(act_type);\n\n auto supported_tile_nums = getSupportedTileNums(quantization_type);\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner> moe_runner;\n // Keep getValidConfigs constructor path aligned with runtime prepare_moe_common().\n // This branch is for DeepSeek FP8 (E4m3 activations + E4m3 weights).\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8 && dtype_act == btg::Dtype::E4m3 &&\n dtype_weights == btg::Dtype::E4m3) {\n TVM_FFI_ICHECK(static_cast<int>(activation_type) ==\n static_cast<int>(ActivationType::Swiglu))\n << \"DeepSeekFp8 only supports ActivationType::Swiglu, got \"\n << static_cast<int>(activation_type) << \".\";\n moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n dtype_weights, true /* useDeepSeekFp8 */, tile_N, use_shuffled_weight,\n static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout));\n } else {\n // Under current trtllm_get_valid_moe_configs() dispatch rules, this else-path is\n // reached only by FP8 block-scale MXFP8 (dtype_act=dtype_weights=MxE4m3).\n moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n dtype_act, // dtypeAct\n dtype_weights, // dtypeWeights\n quantization_type == Fp8QuantizationType::DeepSeekFp8, // useDeepSeekFp8\n tile_N, activation_type, use_shuffled_weight,\n static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout));\n }\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n};\n\nclass MxInt4BlockScaleLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 5> mSupportedTileNums = {8, 16, 32, 64, 128};\n\n MxInt4BlockScaleLauncher(TensorView const& routing_logits,\n Optional<TensorView> const& routing_bias,\n TensorView const& hidden_states, TensorView const& gemm1_weights,\n TensorView const& gemm1_weights_scale,\n Optional<TensorView> const& gemm1_alpha,\n Optional<TensorView> const& gemm1_beta,\n Optional<TensorView> const& gemm1_clamp_limit,\n TensorView const& gemm2_weights, TensorView const& gemm2_weights_scale)\n : FusedMoeLauncher(Optional<TensorView>(routing_logits), routing_bias, hidden_states,\n gemm1_weights, Optional<TensorView>(), Optional<TensorView>(),\n gemm2_weights, Optional<TensorView>()),\n gemm1_weights_scale(gemm1_weights_scale),\n gemm2_weights_scale(gemm2_weights_scale) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type) {\n // currently only support mxint4 x bf16\n auto dtype = hidden_states.dtype();\n if (dtype == dl_bfloat16) {\n args->mDtypeElt = btg::Dtype::Bfloat16;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for MoE.\";\n }\n args->mDtypeOut = btg::Dtype::Bfloat16;\n\n mDtypeAct = btg::Dtype::Bfloat16;\n mDtypeWeights = btg::Dtype::MxInt4;\n\n FusedMoeLauncher::init_common(\n std::move(args), tile_tokens_dim, routing_method_type,\n /*use_shuffled_weight=*/true,\n static_cast<int64_t>(batchedGemm::gemm::MatrixLayout::BlockMajorK), ActivationType::Swiglu);\n }\n\n void check_routing() const override { FusedMoeLauncher::check_routing_common(); }\n\n void prepare_routing() override {\n FusedMoeLauncher::prepare_routing_common();\n\n args->mDtypeElt = mDtypeAct;\n args->mUseDeepSeekFp8 = false;\n // Set expert weights dtype based on routing bias\n auto const routing_bias_dtype =\n routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n\n expert_weights =\n alloc_tensor({args->num_tokens, args->top_k}, dl_bfloat16, hidden_states.device());\n\n workspace.expert_weights = expert_weights.data_ptr();\n }\n\n void check_moe() const override {\n TVM_FFI_ICHECK(mDtypeAct == btg::Dtype::Bfloat16)\n << \"Only Bfloat16 is supported by MxInt4 block scale MoE\";\n\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_uint8) << \"gemm1_weights must be uint8.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_bfloat16)\n << \"gemm1_weights_scale must be bf16.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_uint8) << \"gemm2_weights must be uint8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_bfloat16)\n << \"gemm2_weights_scale must be bf16.\";\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n args->hidden_states = hidden_states.data_ptr();\n args->hidden_states_scale = nullptr;\n args->gemm1_weights = gemm1_weights.data_ptr();\n args->gemm1_weights_scale = gemm1_weights_scale.data_ptr();\n args->gemm1_alpha =\n gemm1_alpha.has_value() ? static_cast<float*>(gemm1_alpha.value().data_ptr()) : nullptr;\n args->gemm1_beta =\n gemm1_beta.has_value() ? static_cast<float*>(gemm1_beta.value().data_ptr()) : nullptr;\n args->gemm1_clamp_limit = gemm1_clamp_limit.has_value()\n ? static_cast<float*>(gemm1_clamp_limit.value().data_ptr())\n : nullptr;\n args->gemm2_weights = gemm2_weights.data_ptr();\n args->gemm2_weights_scale = gemm2_weights_scale.data_ptr();\n args->output1_scales_scalar = nullptr;\n args->output1_scales_gate_scalar = nullptr;\n args->output2_scales_scalar = nullptr;\n\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n max_num_padded_tokens_gemm1 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->intermediate_size,\n btg::dtypeGetNumBits(mDtypeAct));\n max_num_padded_tokens_gemm2 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->hidden_size,\n btg::dtypeGetNumBits(btg::Dtype::Bfloat16)); // Output is always BF16\n\n auto const gemm1_output_hidden = args->intermediate_size;\n gemm1_output = alloc_tensor({max_num_padded_tokens_gemm1, gemm1_output_hidden}, dl_bfloat16,\n hidden_states.device());\n\n // Allocate gemm2_output\n gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n // Setup workspace pointers\n workspace.hidden_states_scale_linear = nullptr; // MxInt4 doesn't use linear scale\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = nullptr;\n // Note: activation_output and activation_output_scale are set by the base class\n // prepare_moe_common() when gated activation is used\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n }\n\n private:\n TensorView gemm1_weights_scale;\n Optional<TensorView> gemm1_alpha;\n Optional<TensorView> gemm1_beta;\n Optional<TensorView> gemm1_clamp_limit;\n TensorView gemm2_weights_scale;\n int32_t max_num_padded_tokens_gemm1{};\n int32_t max_num_padded_tokens_gemm2{};\n\n public:\n static Array<Array<int64_t>> getValidConfigs(int64_t top_k, int64_t hidden_size,\n int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens) {\n Array<Array<int64_t>> valid_configs;\n\n std::vector<int32_t> tile_sizes(mSupportedTileNums.begin(), mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(tile_sizes, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n auto moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n btg::Dtype::Bfloat16, btg::Dtype::MxInt4,\n false, // useDeepSeekFp8\n tile_N, ActivationType::Swiglu,\n /*useShuffledMatrix*/ true, batchedGemm::gemm::MatrixLayout::BlockMajorK);\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n};\n\nclass FP4BlockScaleLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 4> mBaseSupportedTileNums = {8, 16, 32, 64};\n\n static std::vector<int32_t> getSupportedTileNums(btg::Dtype dtype_act) {\n std::vector<int32_t> tiles(mBaseSupportedTileNums.begin(), mBaseSupportedTileNums.end());\n if (dtype_act != btg::Dtype::Bfloat16) {\n tiles.push_back(128);\n tiles.push_back(256);\n }\n return tiles;\n }\n\n FP4BlockScaleLauncher(\n Optional<TensorView> const& routing_logits, Optional<TensorView> const& routing_bias,\n TensorView const& hidden_states, Optional<TensorView> const& hidden_states_scale,\n TensorView const& gemm1_weights, TensorView const& gemm1_weights_scale,\n Optional<TensorView> const& gemm1_bias, Optional<TensorView> const& gemm1_alpha,\n Optional<TensorView> const& gemm1_beta, Optional<TensorView> const& gemm1_clamp_limit,\n TensorView const& gemm2_weights, TensorView const& gemm2_weights_scale,\n Optional<TensorView> const& gemm2_bias, Optional<TensorView> const& output1_scales_scalar,\n Optional<TensorView> const& output1_scales_gate_scalar,\n Optional<TensorView> const& output2_scales_scalar, TensorView const& expert_indices,\n TensorView const& expert_weights)\n : FusedMoeLauncher(routing_logits, routing_bias, hidden_states, gemm1_weights,\n output1_scales_scalar, output1_scales_gate_scalar, gemm2_weights,\n output2_scales_scalar),\n hidden_states_scale(hidden_states_scale),\n gemm1_weights_scale(gemm1_weights_scale),\n gemm1_bias(gemm1_bias),\n gemm1_alpha(gemm1_alpha),\n gemm1_beta(gemm1_beta),\n gemm1_clamp_limit(gemm1_clamp_limit),\n gemm2_weights_scale(gemm2_weights_scale),\n gemm2_bias(gemm2_bias),\n expert_indices(expert_indices),\n expert_weights(expert_weights) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, ActivationType activation_type, btg::Dtype dtype_act,\n btg::Dtype dtype_weights) {\n // Set data types\n args->mDtypeElt = dtype_act;\n args->mDtypeOut = btg::Dtype::Bfloat16; // Output is always BF16 for FP4\n args->mUseDeepSeekFp8 = false; // FP4 doesn't use DeepSeek FP8\n\n mDtypeAct = dtype_act;\n mDtypeWeights = dtype_weights;\n\n FusedMoeLauncher::init_common(std::move(args), tile_tokens_dim, routing_method_type,\n use_shuffled_weight, weight_layout, activation_type);\n }\n\n void check_routing() const override {\n // First call base class common routing checks\n FusedMoeLauncher::check_routing_common();\n }\n\n void prepare_routing() override {\n num_tokens_per_expert = alloc_tensor({args->num_experts}, dl_int32, hidden_states.device());\n int32_t max_num_padded_tokens =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::getMaxPermutedPaddedCount(\n args->num_tokens, args->top_k, args->num_experts, tile_tokens_dim);\n\n total_num_padded_tokens = alloc_tensor({1}, dl_int32, hidden_states.device());\n expanded_idx_to_permuted_idx =\n alloc_tensor({args->num_tokens * args->top_k}, dl_int32, hidden_states.device());\n permuted_idx_to_token_idx =\n alloc_tensor({max_num_padded_tokens}, dl_int32, hidden_states.device());\n\n int64_t const size_of_expert_count_histogram = std::max(args->num_experts * 2, 256 * 2);\n expert_count_histogram =\n alloc_tensor({size_of_expert_count_histogram}, dl_int32, hidden_states.device());\n\n int32_t max_num_ctas = tensorrt_llm::kernels::trtllmgen_moe::Routing::getMaxNumCtasInBatchDim(\n args->num_tokens, args->top_k, args->num_experts, tile_tokens_dim);\n cta_idx_xy_to_batch_idx = alloc_tensor({max_num_ctas}, dl_int32, hidden_states.device());\n cta_idx_xy_to_mn_limit = alloc_tensor({max_num_ctas}, dl_int32, hidden_states.device());\n num_non_exiting_ctas = alloc_tensor({1}, dl_int32, hidden_states.device());\n\n workspace.total_num_padded_tokens = static_cast<int*>(total_num_padded_tokens.data_ptr());\n workspace.total_max_padded_tokens = max_num_padded_tokens;\n workspace.ProjUpTileN = tile_tokens_dim;\n workspace.routing_expert_indexes =\n static_cast<int*>(const_cast<void*>(expert_indices.data_ptr()));\n workspace.expert_weights = const_cast<void*>(expert_weights.data_ptr());\n workspace.permuted_idx_size = static_cast<int*>(total_num_padded_tokens.data_ptr());\n workspace.expanded_idx_to_permuted_idx =\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr());\n workspace.permuted_idx_to_token_idx = static_cast<int*>(permuted_idx_to_token_idx.data_ptr());\n workspace.cta_idx_xy_to_batch_idx = static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr());\n workspace.cta_idx_xy_to_mn_limit = static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr());\n workspace.num_non_exiting_ctas = static_cast<int*>(num_non_exiting_ctas.data_ptr());\n\n args->mDtypeElt = mDtypeAct;\n auto routing_bias_dtype = routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n }\n\n void check_moe() const override {\n TVM_FFI_ICHECK(mDtypeAct == btg::Dtype::E2m1 || mDtypeAct == btg::Dtype::Bfloat16 ||\n mDtypeAct == btg::Dtype::E4m3 || mDtypeAct == btg::Dtype::MxE4m3)\n << \"Only E2m1, Bfloat16, MxE4m3 and E4m3 are supported by Fp4 block scale MoE\";\n\n if (mDtypeAct == btg::Dtype::E2m1) {\n TVM_FFI_ICHECK(mDtypeWeights == btg::Dtype::E2m1)\n << \"Only E2m1 and MxE2m1 are supported by block scale MoE with E2m1 activation\";\n TVM_FFI_ICHECK(hidden_states_scale.has_value())\n << \"hidden_states_scale is required for E2m1 activation\";\n TVM_FFI_ICHECK(output1_scales_scalar.has_value())\n << \"output1_scales_scalar is required for E2m1 activation\";\n TVM_FFI_ICHECK(output1_scales_gate_scalar.has_value())\n << \"output1_scales_gate_scalar is required for E2m1 activation\";\n TVM_FFI_ICHECK(output2_scales_scalar.has_value())\n << \"output2_scales_scalar is required for E2m1 activation\";\n } else if (mDtypeAct == btg::Dtype::Bfloat16 || mDtypeAct == btg::Dtype::E4m3 ||\n mDtypeAct == btg::Dtype::MxE4m3) {\n TVM_FFI_ICHECK(mDtypeWeights == btg::Dtype::MxE2m1)\n << \"Only MxE2m1 weights are supported by block scale MoE with Bfloat16, E4m3 or \"\n \"MxE4m3 activation\";\n }\n\n if (mDtypeAct == btg::Dtype::E4m3) {\n TVM_FFI_ICHECK(output1_scales_scalar.has_value())\n << \"output1_scales_scalar is required for E4m3 activation\";\n TVM_FFI_ICHECK(output1_scales_gate_scalar.has_value())\n << \"output1_scales_gate_scalar is required for E4m3 activation\";\n TVM_FFI_ICHECK(output2_scales_scalar.has_value())\n << \"output2_scales_scalar is required for E4m3 activation\";\n }\n\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_uint8) << \"gemm1_weights must be byte.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_float8_e4m3fn)\n << \"gemm1_weights_scale must be fp8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_uint8) << \"gemm2_weights must be byte.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_float8_e4m3fn)\n << \"gemm2_weights_scale must be fp8.\";\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n args->hidden_states = hidden_states.data_ptr();\n args->hidden_states_scale =\n hidden_states_scale.has_value() ? hidden_states_scale.value().data_ptr() : nullptr;\n args->gemm1_weights = gemm1_weights.data_ptr();\n args->gemm1_weights_scale = gemm1_weights_scale.data_ptr();\n args->gemm1_bias =\n gemm1_bias.has_value() ? static_cast<float*>(gemm1_bias.value().data_ptr()) : nullptr;\n args->gemm1_alpha =\n gemm1_alpha.has_value() ? static_cast<float*>(gemm1_alpha.value().data_ptr()) : nullptr;\n args->gemm1_beta =\n gemm1_beta.has_value() ? static_cast<float*>(gemm1_beta.value().data_ptr()) : nullptr;\n args->gemm1_clamp_limit = gemm1_clamp_limit.has_value()\n ? static_cast<float*>(gemm1_clamp_limit.value().data_ptr())\n : nullptr;\n args->gemm2_weights = gemm2_weights.data_ptr();\n args->gemm2_weights_scale = gemm2_weights_scale.data_ptr();\n args->gemm2_bias =\n gemm2_bias.has_value() ? static_cast<float*>(gemm2_bias.value().data_ptr()) : nullptr;\n args->output1_scales_scalar =\n output1_scales_scalar.has_value()\n ? static_cast<float*>(output1_scales_scalar.value().data_ptr())\n : nullptr;\n args->output1_scales_gate_scalar =\n output1_scales_gate_scalar.has_value()\n ? static_cast<float*>(output1_scales_gate_scalar.value().data_ptr())\n : nullptr;\n args->output2_scales_scalar =\n output2_scales_scalar.has_value()\n ? static_cast<float*>(output2_scales_scalar.value().data_ptr())\n : nullptr;\n\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n auto const sf_vec_size = mDtypeWeights == btg::Dtype::MxE2m1 ? 32 : 16;\n\n max_num_padded_tokens_gemm1 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->intermediate_size,\n btg::dtypeGetNumBits(mDtypeAct));\n max_num_padded_tokens_gemm2 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->hidden_size,\n btg::dtypeGetNumBits(btg::Dtype::Bfloat16)); // Output is always BF16\n\n auto const gemm1_output_hidden =\n mDtypeAct == btg::Dtype::E2m1 ? args->intermediate_size / 2 : args->intermediate_size;\n gemm1_output = alloc_tensor({max_num_padded_tokens_gemm1, gemm1_output_hidden},\n mDtypeAct == btg::Dtype::Bfloat16 ? dl_bfloat16 : dl_uint8,\n hidden_states.device());\n\n if (mDtypeAct == btg::Dtype::E2m1 || mDtypeAct == btg::Dtype::MxE4m3) {\n int64_t sf_size = tensorrt_llm::computeSwizzledLayoutSFSize(\n max_num_padded_tokens_gemm1, args->intermediate_size / sf_vec_size);\n gemm1_output_scale = alloc_tensor({sf_size}, dl_uint8, hidden_states.device());\n }\n\n // Allocate gemm2_output\n gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n // Setup workspace pointers\n workspace.hidden_states_scale_linear = nullptr; // FP4 doesn't use linear scale\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = gemm1_output_scale.has_value()\n ? static_cast<float*>(gemm1_output_scale.value().data_ptr())\n : nullptr;\n // Note: activation_output and activation_output_scale are set by the base class\n // prepare_moe_common() when gated activation is used\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n }\n\n private:\n Optional<TensorView> hidden_states_scale;\n TensorView gemm1_weights_scale;\n Optional<TensorView> gemm1_bias;\n Optional<TensorView> gemm1_alpha;\n Optional<TensorView> gemm1_beta;\n Optional<TensorView> gemm1_clamp_limit;\n TensorView gemm2_weights_scale;\n Optional<TensorView> gemm2_bias;\n int32_t max_num_padded_tokens_gemm1{};\n int32_t max_num_padded_tokens_gemm2{};\n Optional<Tensor> gemm1_output_scale;\n TensorView expert_indices;\n TensorView expert_weights;\n\n public:\n Array<Tensor> run(int64_t moe_tactic, bool enable_pdl = true,\n bool use_routing_scales_on_input = false,\n bool use_deep_seek_fp8 = false) override {\n check_routing();\n prepare_routing();\n\n // Execute routing\n tensorrt_llm::kernels::trtllmgen_moe::Routing::Runner routing_runner(tile_tokens_dim);\n cudaStream_t routing_stream = get_stream(hidden_states.device());\n\n routing_runner.run(\n args->routing_logits, args->routing_bias, args->num_tokens, args->num_experts, args->top_k,\n args->n_group, args->topk_group, args->local_expert_offset, args->local_num_experts,\n args->routed_scaling_factor, static_cast<int*>(expert_indices.data_ptr()),\n static_cast<int*>(expert_count_histogram.data_ptr()),\n static_cast<int*>(total_num_padded_tokens.data_ptr()),\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr()),\n nullptr /*permuted_idx_to_expanded_idx.data_ptr()*/,\n static_cast<int*>(permuted_idx_to_token_idx.data_ptr()), expert_weights.data_ptr(),\n static_cast<int*>(num_tokens_per_expert.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr()),\n static_cast<int*>(num_non_exiting_ctas.data_ptr()), args->mDtypeElt, mRoutingBiasDtype,\n use_routing_scales_on_input, use_deep_seek_fp8,\n static_cast<RoutingMethodType>(routing_method_type), routing_stream);\n\n check_moe();\n prepare_moe(moe_tactic);\n\n cudaStream_t moe_stream = get_stream(hidden_states.device());\n moe_runner->run(*args, workspace, hidden_states.device().device_id, moe_stream, moe_tactic,\n enable_pdl);\n\n // Match original FP4 behavior for return values\n if (args->do_finalize) {\n return {output};\n }\n return {gemm2_output, FusedMoeLauncher::expert_weights, expanded_idx_to_permuted_idx};\n }\n\n static Array<Array<int64_t>> getValidConfigs(int64_t top_k, int64_t hidden_size,\n int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens, int64_t act_type,\n btg::Dtype dtype_act, btg::Dtype dtype_weights) {\n Array<Array<int64_t>> valid_configs;\n\n std::vector<int32_t> tile_sizes = getSupportedTileNums(dtype_act);\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(tile_sizes, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n auto moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n dtype_act, dtype_weights,\n false, // useDeepSeekFp8\n tile_N, static_cast<ActivationType>(act_type),\n /*useShuffledMatrix*/ true); // FP4 uses shuffled weights\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n};\n\nArray<Tensor> trtllm_bf16_moe(Optional<TensorView> const& routing_logits,\n Optional<TensorView> const& routing_bias,\n TensorView const& expert_indices, TensorView const& expert_weights,\n TensorView const& hidden_states, TensorView const& gemm1_weights,\n TensorView const& gemm2_weights, TensorView output,\n int64_t num_experts, int64_t top_k, Optional<int64_t> n_group,\n Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts,\n Optional<double> routed_scaling_factor, int64_t routing_method_type,\n bool use_shuffled_weight, int64_t weight_layout, bool do_finalize,\n bool enable_pdl, Array<int64_t> moe_tactic) {\n // Just some basic type validation first and leave more checks to the launcher\n if (routing_logits.has_value()) {\n TVM_FFI_ICHECK(routing_logits.value().dtype() == dl_float32 ||\n routing_logits.value().dtype() == dl_bfloat16)\n << \"BF16 MoE: routing_logits must be bfloat16 or float.\";\n }\n TVM_FFI_ICHECK_EQ(hidden_states.dtype(), dl_bfloat16)\n << \"BF16 MoE: hidden_states must be bfloat16.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_bfloat16)\n << \"BF16 MoE: gemm1_weights must be bfloat16.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_bfloat16)\n << \"BF16 MoE: gemm2_weights must be bfloat16.\";\n\n auto const num_tokens = hidden_states.size(0);\n auto const hidden_size = hidden_states.size(1);\n\n // Calculate supported tile sizes\n std::vector<int32_t> mSupportedTileN(Bf16MoeLauncher::mSupportedTileNums.begin(),\n Bf16MoeLauncher::mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(mSupportedTileN, num_tokens, top_k, local_num_experts);\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<Bf16MoeLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : selected_tile_nums) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n args->hidden_size = hidden_size;\n args->hidden_size_output = args->hidden_size;\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<Bf16MoeLauncher>(routing_logits, routing_bias, expert_indices,\n expert_weights, hidden_states, gemm1_weights,\n gemm2_weights);\n launcher->init(std::move(args), curr_tile_N, routing_method_type, use_shuffled_weight,\n weight_layout);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n // Extract tile_N and config from moe_tactic\n int64_t tile_N = moe_tactic[0];\n int64_t config = moe_tactic[1];\n\n // Handle default case\n if (tile_N == -1 || config == -1) {\n tile_N = *selected_tile_nums.begin();\n }\n\n // Get the launcher for the selected tile_N\n auto& selected_launcher = launchers_map.at(tile_N);\n\n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl);\n}\n\nArray<Tensor> trtllm_fp8_per_tensor_scale_moe(\n TensorView routing_logits, Optional<TensorView> routing_bias, TensorView hidden_states,\n TensorView gemm1_weights, TensorView output1_scales_scalar,\n TensorView output1_scales_gate_scalar, TensorView gemm2_weights,\n TensorView output2_scales_scalar, TensorView output, int64_t num_experts, int64_t top_k,\n Optional<int64_t> n_group, Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts, Optional<double> routed_scaling_factor,\n bool use_routing_scales_on_input, int64_t routing_method_type, bool do_finalize,\n bool enable_pdl, Array<int64_t> config_index, int64_t activation_type) {\n // Basic type validation\n auto dtype = hidden_states.dtype();\n auto activation = static_cast<ActivationType>(activation_type);\n if (use_routing_scales_on_input) {\n TVM_FFI_ICHECK_EQ(routing_logits.dtype(), dl_bfloat16) << \"routing_logits must be bfloat16.\";\n } else if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK_EQ(routing_logits.dtype(), dl_float32) << \"routing_logits must be float.\";\n } else {\n TVM_FFI_ICHECK_EQ(routing_logits.dtype(), dl_bfloat16) << \"routing_logits must be bfloat16.\";\n }\n TVM_FFI_ICHECK(dtype == dl_float8_e4m3fn || dtype == dl_float16 || dtype == dl_bfloat16)\n << \"FP8 MoE: hidden_states must be float8_e4m3fn, float16, or bfloat16.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 MoE: gemm1_weights must be float8_e4m3fn.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 MoE: gemm2_weights must be float8_e4m3fn.\";\n TVM_FFI_ICHECK_EQ(output1_scales_scalar.dtype(), dl_float32)\n << \"FP8 MoE: output1_scales_scalar must be float32.\";\n TVM_FFI_ICHECK_EQ(output1_scales_gate_scalar.dtype(), dl_float32)\n << \"FP8 MoE: output1_scales_gate_scalar must be float32.\";\n TVM_FFI_ICHECK_EQ(output2_scales_scalar.dtype(), dl_float32)\n << \"FP8 MoE: output2_scales_scalar must be float32.\";\n\n auto const num_tokens = hidden_states.size(0);\n auto const hidden_size = hidden_states.size(1);\n\n // Use default values that match the original function behavior\n bool use_shuffled_weight = true; // Original uses /*useShuffledMatrix*/ true\n int64_t weight_layout = 0; // Default to MajorK\n\n // Calculate supported tile sizes\n std::vector<int32_t> mSupportedTileN(Fp8PerTensorLauncher::mSupportedTileNums.begin(),\n Fp8PerTensorLauncher::mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(mSupportedTileN, num_tokens, top_k, local_num_experts);\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<Fp8PerTensorLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : selected_tile_nums) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n args->hidden_size = hidden_size;\n args->hidden_size_output = args->hidden_size;\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<Fp8PerTensorLauncher>(\n routing_logits, routing_bias, hidden_states, gemm1_weights, output1_scales_scalar,\n output1_scales_gate_scalar, gemm2_weights, output2_scales_scalar);\n launcher->init(std::move(args), curr_tile_N, routing_method_type, use_shuffled_weight,\n weight_layout, use_routing_scales_on_input, activation);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n // Extract tile_N and config from config_index\n int64_t tile_N = config_index[0];\n int64_t config = config_index[1];\n\n // Handle default case\n if (tile_N == -1 || config == -1) {\n tile_N = *selected_tile_nums.begin();\n }\n\n // Get the launcher for the selected tile_N\n auto& selected_launcher = launchers_map.at(tile_N);\n\n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl, use_routing_scales_on_input);\n}\n\nArray<Tensor> trtllm_fp8_block_scale_moe(\n Optional<TensorView> routing_logits, TensorView expert_indices, TensorView expert_weights,\n Optional<TensorView> routing_bias, TensorView hidden_states, TensorView hidden_states_scale,\n TensorView gemm1_weights, TensorView gemm1_weights_scale, TensorView gemm2_weights,\n TensorView gemm2_weights_scale, TensorView output, int64_t num_experts, int64_t top_k,\n Optional<int64_t> n_group, Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts, Optional<double> routed_scaling_factor,\n int64_t routing_method_type, bool use_shuffled_weight, int64_t weight_layout, bool do_finalize,\n bool enable_pdl, Array<int64_t> config_index, Fp8QuantizationType quantization_type,\n int64_t act_type) {\n auto activation_type = validateAndCastActivationType(act_type);\n // DeepSeekFp8 currently uses a TRTLLM runner that hardwires Swiglu activation semantics.\n // Fail for any other activation to avoid silently running incorrect activation behavior.\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8 &&\n activation_type != ActivationType::Swiglu) {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"DeepSeekFp8 only supports ActivationType::Swiglu in this runner path. \"\n << \"Received activation_type=\" << static_cast<int>(activation_type);\n }\n\n // Basic type validation\n auto dtype = hidden_states.dtype();\n\n // Either routing_logits or expert_indices must be provided\n // expert_indices is a packed tensor: (expert_id << 16) | (weight_bf16.view(int16))\n bool use_routing_logits = routing_logits.has_value();\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool use_precomputed_routing = expert_indices.ndim() == 2 && expert_indices.size(0) > 0;\n\n TVM_FFI_ICHECK(use_routing_logits || use_precomputed_routing)\n << \"Either routing_logits or expert_indices must be provided.\";\n\n if (use_routing_logits) {\n if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK_EQ(routing_logits.value().dtype(), dl_float32)\n << \"routing_logits must be float.\";\n } else {\n TVM_FFI_ICHECK_EQ(routing_logits.value().dtype(), dl_bfloat16)\n << \"routing_logits must be bfloat16.\";\n }\n }\n TVM_FFI_ICHECK(dtype == dl_float16 || dtype == dl_bfloat16 || dtype == dl_float8_e4m3fn)\n << \"FP8 block scale MoE: hidden_states must be fp16, bf16, or fp8.\";\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(hidden_states_scale.dtype(), dl_float32)\n << \"FP8 block scale MoE: hidden_states_scale must be float32.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK_EQ(hidden_states_scale.dtype(), dl_uint8)\n << \"FP8 block scale MoE: hidden_states_scale must be uint8.\";\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 block scale MoE: gemm1_weights must be fp8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 block scale MoE: gemm2_weights must be fp8.\";\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_float32)\n << \"FP8 block scale MoE: gemm1_weights_scale must be float32.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_float32)\n << \"FP8 block scale MoE: gemm2_weights_scale must be float32.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_uint8)\n << \"FP8 block scale MoE: gemm1_weights_scale must be uint8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_uint8)\n << \"FP8 block scale MoE: gemm2_weights_scale must be uint8.\";\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n\n if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK(use_shuffled_weight) << \"use_shuffled_weight must be true for MxFp8.\";\n TVM_FFI_ICHECK(weight_layout == 0) << \"weight_layout must be 0 for MxFp8.\";\n }\n\n auto const num_tokens = hidden_states.size(0);\n auto const hidden_size = hidden_states.size(1);\n\n auto supported_tile_nums = Fp8BlockScaleLauncher::getSupportedTileNums(quantization_type);\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(supported_tile_nums, num_tokens, top_k, local_num_experts);\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<Fp8BlockScaleLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : selected_tile_nums) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n args->hidden_size = hidden_size;\n args->hidden_size_output = args->hidden_size;\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<Fp8BlockScaleLauncher>(\n routing_logits, routing_bias, hidden_states, hidden_states_scale, gemm1_weights,\n gemm1_weights_scale, gemm2_weights, gemm2_weights_scale, expert_indices, expert_weights,\n quantization_type);\n launcher->init(std::move(args), curr_tile_N, routing_method_type, use_shuffled_weight,\n weight_layout, activation_type);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n // Extract tile_N and config from config_index\n int64_t tile_N = config_index[0];\n int64_t config = config_index[1];\n\n // Handle default case\n if (tile_N == -1 || config == -1) {\n tile_N = *selected_tile_nums.begin();\n }\n\n // Get the launcher for the selected tile_N\n auto& selected_launcher = launchers_map.at(tile_N);\n\n // Run the launcher with DeepSeek FP8 enabled - it will create its own runner internally\n return selected_launcher->run(\n config, enable_pdl, false /* use_routing_scales_on_input */,\n quantization_type == Fp8QuantizationType::DeepSeekFp8 /* use_deep_seek_fp8 */);\n}\n\nArray<Tensor> trtllm_fp4_block_scale_moe(\n Optional<TensorView> routing_logits, TensorView expert_indices, TensorView expert_weights,\n Optional<TensorView> routing_bias, TensorView hidden_states,\n Optional<TensorView> hidden_states_scale, TensorView gemm1_weights,\n TensorView gemm1_weights_scale, Optional<TensorView> gemm1_bias,\n Optional<TensorView> gemm1_alpha, Optional<TensorView> gemm1_beta,\n Optional<TensorView> gemm1_clamp_limit, TensorView gemm2_weights,\n TensorView gemm2_weights_scale, Optional<TensorView> gemm2_bias,\n Optional<TensorView> output1_scales_scalar, Optional<TensorView> output1_scales_gate_scalar,\n Optional<TensorView> output2_scales_scalar, int64_t num_experts, int64_t top_k,\n Optional<int64_t> n_group, Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts, Optional<double> routed_scaling_factor,\n int64_t routing_method_type, bool do_finalize, bool enable_pdl, int64_t act_type,\n TensorView output, Array<int64_t> config_index) {\n // Determine data types based on input format\n int const num_tokens = hidden_states.size(0);\n int hidden_size = hidden_states.size(1);\n if (hidden_states.dtype() == dl_uint8) hidden_size *= 2;\n\n int hidden_states_scale_vec_size = -1;\n if (hidden_states_scale.has_value()) {\n hidden_states_scale_vec_size = (num_tokens * hidden_size) / hidden_states_scale.value().numel();\n }\n int64_t intermediate_size_factor =\n isGatedActivation(static_cast<ActivationType>(act_type)) ? 2 : 1;\n int weight_scale_vec_size =\n (local_num_experts * intermediate_size * intermediate_size_factor * hidden_size) /\n gemm1_weights_scale.numel();\n\n TVM_FFI_ICHECK(weight_scale_vec_size == 16 || weight_scale_vec_size == 32)\n << \"unsupported weight_scale_vec_size.\";\n auto mDtypeWeights = weight_scale_vec_size == 16 ? btg::Dtype::E2m1 : btg::Dtype::MxE2m1;\n\n if (routing_logits.has_value()) {\n TVM_FFI_ICHECK(routing_logits.value().dtype() == dl_float32 ||\n routing_logits.value().dtype() == dl_bfloat16)\n << \"routing_logits must be float or bfloat16.\";\n TVM_FFI_ICHECK_EQ(routing_logits.value().ndim(), 2) << \"routing_logits must be 2D.\";\n TVM_FFI_ICHECK_EQ(routing_logits.value().size(1), num_experts)\n << \"routing_logits has incorrect shape.\";\n if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK_EQ(routing_logits.value().dtype(), dl_float32)\n << \"routing_logits must be float.\";\n }\n }\n if (routing_bias.has_value()) {\n TVM_FFI_ICHECK(routing_bias.value().dtype() == dl_bfloat16 ||\n routing_bias.value().dtype() == dl_float32)\n << \"routing_bias must be bfloat16 or float.\";\n\n TVM_FFI_ICHECK_EQ(routing_bias.value().ndim(), 1) << \"routing_bias must be 1D.\";\n TVM_FFI_ICHECK_EQ(routing_bias.value().size(0), num_experts)\n << \"routing_bias has incorrect shape.\";\n }\n\n // Determine activation type\n TVM_FFI_ICHECK(gemm1_weights.dtype() == dl_uint8 && gemm2_weights.dtype() == dl_uint8)\n << \"weights must be fp4 packed in uint8.\";\n TVM_FFI_ICHECK(hidden_states.dtype() == dl_uint8 || hidden_states.dtype() == dl_bfloat16 ||\n hidden_states.dtype() == dl_float8_e4m3fn)\n << \"hidden_states must be bf16, fp8 or uint8 (packed fp4).\";\n\n auto mDtypeAct = btg::Dtype::Bfloat16;\n if (hidden_states.dtype() == dl_uint8) {\n TVM_FFI_ICHECK(hidden_states_scale.has_value() &&\n hidden_states_scale.value().dtype() == dl_float8_e4m3fn)\n << \"hidden_states_scale must be provided for fp4 activation.\";\n if (hidden_states_scale_vec_size == 16) {\n mDtypeAct = btg::Dtype::E2m1;\n } else if (hidden_states_scale_vec_size == 32) {\n mDtypeAct = btg::Dtype::MxE2m1;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported hidden state scale shape.\";\n }\n } else if (hidden_states.dtype() == dl_float8_e4m3fn) {\n if (hidden_states_scale.has_value()) {\n if (hidden_states_scale_vec_size == 32) {\n mDtypeAct = btg::Dtype::MxE4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported hidden state scale shape.\";\n }\n } else {\n mDtypeAct = btg::Dtype::E4m3;\n }\n }\n\n // Determine supported tile sizes\n std::vector<int32_t> mSupportedTileN = FP4BlockScaleLauncher::getSupportedTileNums(mDtypeAct);\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(mSupportedTileN, num_tokens, top_k, local_num_experts);\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<FP4BlockScaleLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : selected_tile_nums) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n // For E2m1, hidden_size is already multiplied by 2 above, so use it directly\n args->hidden_size = hidden_size;\n args->hidden_size_output = output.size(1);\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<FP4BlockScaleLauncher>(\n routing_logits, routing_bias, hidden_states, hidden_states_scale, gemm1_weights,\n gemm1_weights_scale, gemm1_bias, gemm1_alpha, gemm1_beta, gemm1_clamp_limit, gemm2_weights,\n gemm2_weights_scale, gemm2_bias, output1_scales_scalar, output1_scales_gate_scalar,\n output2_scales_scalar, expert_indices, expert_weights);\n launcher->init(std::move(args), curr_tile_N, routing_method_type, /*use_shuffled_weight=*/true,\n /*weight_layout=*/0, static_cast<ActivationType>(act_type), mDtypeAct,\n mDtypeWeights);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n // Extract tile_N and config from config_index\n int64_t tile_N = config_index[0];\n int64_t config = config_index[1];\n\n // Handle default case\n if (tile_N == -1 || config == -1) {\n tile_N = *selected_tile_nums.begin();\n config = -1; // Let the runner choose default\n }\n\n // Get the launcher for the selected tile_N\n auto& selected_launcher = launchers_map.at(tile_N);\n\n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl);\n}\n\nArray<Tensor> trtllm_mxint4_block_scale_moe(\n TensorView routing_logits, Optional<TensorView> routing_bias, TensorView hidden_states,\n TensorView gemm1_weights, TensorView gemm1_weights_scale, Optional<TensorView> gemm1_alpha,\n Optional<TensorView> gemm1_beta, Optional<TensorView> gemm1_clamp_limit,\n TensorView gemm2_weights, TensorView gemm2_weights_scale, int64_t num_experts, int64_t top_k,\n Optional<int64_t> n_group, Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts, Optional<double> routed_scaling_factor,\n int64_t routing_method_type, bool do_finalize, bool enable_pdl, TensorView output,\n Array<int64_t> config_index) {\n // Determine data types based on input format\n int const num_tokens = hidden_states.size(0);\n int hidden_size = hidden_states.size(1);\n // Just some basic type validation first and leave more checks to the launcher\n\n int weight_scale_vec_size =\n (local_num_experts * intermediate_size * 2 * hidden_size) / gemm1_weights_scale.numel();\n\n TVM_FFI_ICHECK(weight_scale_vec_size == 32) << \"unsupported weight_scale_vec_size.\";\n\n TVM_FFI_ICHECK(routing_logits.dtype() == dl_float32 || routing_logits.dtype() == dl_bfloat16)\n << \"routing_logits must be float or bfloat16.\";\n TVM_FFI_ICHECK_EQ(routing_logits.ndim(), 2) << \"routing_logits must be 2D.\";\n TVM_FFI_ICHECK_EQ(routing_logits.size(1), num_experts) << \"routing_logits has incorrect shape.\";\n if (routing_bias.has_value()) {\n TVM_FFI_ICHECK(routing_bias.value().dtype() == dl_bfloat16) << \"routing_bias must be bfloat16.\";\n TVM_FFI_ICHECK_EQ(routing_bias.value().ndim(), 1) << \"routing_bias must be 1D.\";\n TVM_FFI_ICHECK_EQ(routing_bias.value().size(0), num_experts)\n << \"routing_bias has incorrect shape.\";\n }\n\n // Determine activation type\n TVM_FFI_ICHECK(gemm1_weights.dtype() == dl_uint8 && gemm2_weights.dtype() == dl_uint8)\n << \"weights must be int4 packed in uint8.\";\n TVM_FFI_ICHECK(hidden_states.dtype() == dl_bfloat16) << \"hidden_states must be bf16.\";\n\n // Determine supported tile sizes\n std::vector<int32_t> mSupportedTileN(MxInt4BlockScaleLauncher::mSupportedTileNums.begin(),\n MxInt4BlockScaleLauncher::mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(mSupportedTileN, num_tokens, top_k, local_num_experts);\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<MxInt4BlockScaleLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : selected_tile_nums) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n // For E2m1, hidden_size is already multiplied by 2 above, so use it directly\n args->hidden_size = hidden_size;\n args->hidden_size_output = args->hidden_size;\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<MxInt4BlockScaleLauncher>(\n routing_logits, routing_bias, hidden_states, gemm1_weights, gemm1_weights_scale,\n gemm1_alpha, gemm1_beta, gemm1_clamp_limit, gemm2_weights, gemm2_weights_scale);\n launcher->init(std::move(args), curr_tile_N, routing_method_type);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n // Extract tile_N and config from config_index\n int64_t tile_N = config_index[0];\n int64_t config = config_index[1];\n\n // Handle default case\n if (tile_N == -1 || config == -1) {\n tile_N = *selected_tile_nums.begin();\n config = -1; // Let the runner choose default\n }\n\n // Get the launcher for the selected tile_N\n auto& selected_launcher = launchers_map.at(tile_N);\n\n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl);\n}\n\nArray<Array<int64_t>> trtllm_get_valid_moe_configs(\n int64_t const dtype_act_, int64_t const dtype_weights_, Fp8QuantizationType quantization_type,\n int64_t const top_k, int64_t const hidden_size, int64_t const intermediate_size,\n int64_t const num_local_experts, int64_t const act_type, bool const use_shuffled_weight,\n int64_t const weight_layout, int64_t const num_tokens) {\n auto activation_type = validateAndCastActivationType(act_type);\n auto dtype_act = static_cast<btg::Dtype>(dtype_act_);\n auto dtype_weights = static_cast<btg::Dtype>(dtype_weights_);\n\n if (dtype_act == btg::Dtype::Bfloat16 && dtype_weights == btg::Dtype::MxInt4) {\n // MxInt4 MoE\n return MxInt4BlockScaleLauncher::getValidConfigs(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n }\n if (dtype_act == btg::Dtype::Bfloat16 && dtype_weights == btg::Dtype::Bfloat16) {\n // BF16 MoE\n return Bf16MoeLauncher::getValidConfigs(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens, act_type,\n use_shuffled_weight, weight_layout);\n\n } else if (quantization_type == Fp8QuantizationType::DeepSeekFp8 &&\n dtype_act == btg::Dtype::E4m3 && dtype_weights == btg::Dtype::E4m3) {\n if (activation_type != ActivationType::Swiglu) {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"DeepSeekFp8 only supports ActivationType::Swiglu, \"\n << \"got act_type=\" << act_type << \".\";\n }\n // FP8 block scale (DeepSeek)\n return Fp8BlockScaleLauncher::getValidConfigs(\n top_k, hidden_size, intermediate_size, num_local_experts, num_tokens, use_shuffled_weight,\n weight_layout, dtype_act, dtype_weights, quantization_type, act_type);\n } else if (quantization_type == Fp8QuantizationType::MxFp8 && dtype_act == btg::Dtype::MxE4m3 &&\n dtype_weights == btg::Dtype::MxE4m3) {\n // FP8 block scale (MxFp8)\n return Fp8BlockScaleLauncher::getValidConfigs(\n top_k, hidden_size, intermediate_size, num_local_experts, num_tokens, use_shuffled_weight,\n weight_layout, dtype_act, dtype_weights, quantization_type, act_type);\n } else if ((quantization_type == Fp8QuantizationType::PerTensorFp8 ||\n quantization_type == Fp8QuantizationType::NoneFp8) &&\n dtype_weights == btg::Dtype::E4m3) {\n // FP8 per-tensor scale. NoneFp8 is kept for backward compatibility.\n if (!isGatedActivation(activation_type)) {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"FP8 per-tensor currently supports gated activations only, \"\n << \"got act_type=\" << act_type << \".\";\n }\n return Fp8PerTensorLauncher::getValidConfigs(\n top_k, hidden_size, intermediate_size, num_local_experts, num_tokens, act_type,\n use_shuffled_weight, weight_layout, dtype_act, dtype_weights);\n } else if (dtype_weights == btg::Dtype::E2m1 || dtype_weights == btg::Dtype::MxE2m1) {\n // FP4 block scale\n return FP4BlockScaleLauncher::getValidConfigs(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens, act_type,\n dtype_act, dtype_weights);\n }\n\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"Unsupported data type combination for getValidConfigs: \"\n << \"dtype_act=\" << static_cast<int>(dtype_act)\n << \", dtype_weights=\" << static_cast<int>(dtype_weights)\n << \", quantization_type=\" << fp8QuantizationTypeToString(quantization_type);\n\n // Unreachable code - added to suppress compiler warning\n return Array<Array<int64_t>>();\n}\n\nnamespace trtllm_cubin_loader {\n#include <flashinfer/cubin_loader.h>\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_bf16_moe, trtllm_bf16_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_fp8_per_tensor_scale_moe, trtllm_fp8_per_tensor_scale_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_fp8_block_scale_moe, trtllm_fp8_block_scale_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_fp4_block_scale_moe, trtllm_fp4_block_scale_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_mxint4_block_scale_moe, trtllm_mxint4_block_scale_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_get_valid_moe_configs, trtllm_get_valid_moe_configs);\n\n} // namespace flashinfer\n"},"after_code":{"kind":"string","value":"/*\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <cuda_runtime.h>\n#include <flashinfer/exception.h>\n#include <nvrtc.h>\n\n#include <algorithm>\n#include <cmath>\n#include <cstring>\n#include <iomanip>\n#include <iostream>\n#include <set>\n#include <unordered_map>\n#include <vector>\n\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/GemmGatedActOptions.h\"\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/trtllm/gen/DtypeDecl.h\"\n#include \"flashinfer/trtllm/fused_moe/DevKernel.h\"\n#include \"flashinfer/trtllm/fused_moe/RoutingKernel.h\"\n#include \"flashinfer/trtllm/fused_moe/runner.h\"\n#include \"nv_internal/tensorrt_llm/kernels/quantization.h\"\n#include \"nv_internal/tensorrt_llm/thop/utils.h\"\n#include \"tvm_ffi_utils.h\"\n\nnamespace flashinfer {\n\nnamespace btg = batchedGemm::trtllm::gen;\nusing tensorrt_llm::kernels::trtllmgen_moe::MoE::ActivationType;\nusing tensorrt_llm::kernels::trtllmgen_moe::Routing::RoutingMethodType;\nusing tvm::ffi::Array;\nusing tvm::ffi::Optional;\n\nenum class Fp8QuantizationType {\n NoneFp8,\n DeepSeekFp8,\n MxFp8,\n PerTensorFp8,\n};\n\ninline std::string fp8QuantizationTypeToString(Fp8QuantizationType quantization_type) {\n switch (quantization_type) {\n default:\n case Fp8QuantizationType::NoneFp8:\n return \"NoneFp8\";\n case Fp8QuantizationType::DeepSeekFp8:\n return \"DeepSeekFp8\";\n case Fp8QuantizationType::MxFp8:\n return \"MxFp8\";\n case Fp8QuantizationType::PerTensorFp8:\n return \"PerTensorFp8\";\n }\n}\n\ninline ActivationType validateAndCastActivationType(int64_t act_type) {\n TVM_FFI_ICHECK(act_type >= 0 && act_type < static_cast<int64_t>(ActivationType::InvalidType))\n << \"Invalid activation type: \" << act_type;\n return static_cast<ActivationType>(act_type);\n}\n\n// Utility function to compute the next power of two\ninline int32_t nextPowerOfTwo(float value) {\n int32_t n = static_cast<int32_t>(std::ceil(value));\n if (n <= 1) return 1;\n\n // If n is already a power of 2, return it\n if ((n & (n - 1)) == 0) return n;\n\n // Find the next power of 2\n n--;\n n |= n >> 1;\n n |= n >> 2;\n n |= n >> 4;\n n |= n >> 8;\n n |= n >> 16;\n n++;\n\n return n;\n}\n\nstd::set<int32_t> computeSelectedTileN(std::vector<int32_t> const& supported_tile_nums,\n int64_t const num_tokens, int64_t const top_k,\n int64_t const num_local_experts) {\n TVM_FFI_ICHECK(!supported_tile_nums.empty()) << \"supported_tile_nums must not be empty.\";\n float const avg_tokens_per_expert = static_cast<float>(num_tokens * top_k) / num_local_experts;\n // NOTE: This differs from Python AutoTuner bucketing:\n // - AutoTuner maps raw num_tokens with last_positive_power_of_2 (round-down).\n // - Here we map derived avg_tokens_per_expert and use nextPowerOfTwo (round-up).\n // Because they round different quantities in different directions, cache bucket and runtime\n // tile candidates can diverge; launcher-side tactic resolution handles that mismatch.\n // assume supported_tile_nums is sorted\n int32_t tile_tokens_dim = std::clamp(nextPowerOfTwo(avg_tokens_per_expert),\n supported_tile_nums.front(), supported_tile_nums.back());\n auto it = std::find(supported_tile_nums.begin(), supported_tile_nums.end(), tile_tokens_dim);\n FLASHINFER_CHECK(\n it != supported_tile_nums.end(), \"computeSelectedTileN expected exact tile \", tile_tokens_dim,\n \" in supported_tile_nums (size=\", supported_tile_nums.size(),\n \"). Please keep supported_tile_nums as a dense power-of-2 ladder for this launcher.\");\n\n // Candidate tile set centered on the heuristic tile.\n // This function returns nearby candidates (not a single final tile):\n // center, +1, +2, and -1 neighbors when available.\n // Final tile choice is made later (autotuner-provided tile if valid, otherwise fallback policy).\n std::set<int32_t> selected_tile_nums;\n selected_tile_nums.insert(tile_tokens_dim);\n if (std::next(it) != supported_tile_nums.end()) {\n selected_tile_nums.insert(*std::next(it));\n if (std::next(std::next(it)) != supported_tile_nums.end()) {\n selected_tile_nums.insert(*std::next(std::next(it)));\n }\n }\n if (it != supported_tile_nums.begin()) {\n selected_tile_nums.insert(*std::prev(it));\n }\n\n return selected_tile_nums;\n}\n\nint64_t selectDefaultTileN(std::vector<int32_t> const& supported_tile_nums,\n int64_t const num_tokens, int64_t const top_k,\n int64_t const num_local_experts) {\n auto selected = computeSelectedTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n TVM_FFI_ICHECK(!selected.empty()) << \"No selected tile_N candidates for current MoE input.\";\n return *selected.begin();\n}\n\n// Resolve the (tile_N, config) pair passed from Python side, applying fallback logic\n// when tile_N is -1.\nstd::pair<int64_t, int64_t> resolveMoeTileAndConfig(Array<int64_t> const& config_index,\n std::vector<int32_t> const& supported_tile_nums,\n int64_t const num_tokens, int64_t const top_k,\n int64_t const num_local_experts) {\n // Python side convention: tactic is [tile_N, config]\n TVM_FFI_ICHECK(config_index.size() == 2)\n << \"Invalid tactic, expected to be [tile_N, config], but got array of size \"\n << config_index.size();\n const int64_t tile_N = config_index[0];\n const int64_t config = config_index[1];\n\n if (tile_N == -1 || config == -1) {\n // Use fallback tactic\n auto const default_tile_N =\n selectDefaultTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n return {default_tile_N, -1};\n }\n\n return {tile_N, config};\n}\n\nclass FusedMoeLauncher {\n protected:\n Optional<TensorView> routing_logits;\n Optional<TensorView> routing_bias;\n TensorView hidden_states;\n TensorView gemm1_weights;\n Optional<TensorView> output1_scales_scalar;\n Optional<TensorView> output1_scales_gate_scalar;\n TensorView gemm2_weights;\n Optional<TensorView> output2_scales_scalar;\n\n int64_t tile_tokens_dim{};\n int64_t routing_method_type{};\n bool use_shuffled_weight{};\n batchedGemm::gemm::MatrixLayout weight_layout{batchedGemm::gemm::MatrixLayout::MajorK};\n\n std::tuple<int, int> device_version;\n std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs> args;\n tensorrt_llm::kernels::trtllmgen_moe::MoE::MoEWorkspace workspace;\n\n btg::Dtype mDtypeAct{btg::Dtype::Bfloat16};\n btg::Dtype mDtypeWeights{btg::Dtype::Bfloat16};\n btg::Dtype mRoutingBiasDtype{\n btg::Dtype::Bfloat16}; // Dtype for expert weights in routing, based on routing bias\n ActivationType activation_type{ActivationType::Swiglu};\n\n int64_t intermediate_size_factor{2};\n\n public:\n // Constructor that initializes all TensorView members\n FusedMoeLauncher(const Optional<TensorView>& routing_logits,\n const Optional<TensorView>& routing_bias, const TensorView& hidden_states,\n const TensorView& gemm1_weights,\n const Optional<TensorView>& output1_scales_scalar,\n const Optional<TensorView>& output1_scales_gate_scalar,\n const TensorView& gemm2_weights,\n const Optional<TensorView>& output2_scales_scalar)\n : routing_logits(routing_logits),\n routing_bias(routing_bias),\n hidden_states(hidden_states),\n gemm1_weights(gemm1_weights),\n output1_scales_scalar(output1_scales_scalar),\n output1_scales_gate_scalar(output1_scales_gate_scalar),\n gemm2_weights(gemm2_weights),\n output2_scales_scalar(output2_scales_scalar),\n tile_tokens_dim{},\n routing_method_type{},\n use_shuffled_weight{},\n weight_layout{batchedGemm::gemm::MatrixLayout::MajorK},\n mDtypeAct{btg::Dtype::Bfloat16},\n mDtypeWeights{btg::Dtype::Bfloat16},\n activation_type{ActivationType::Swiglu},\n intermediate_size_factor{2} {}\n\n protected:\n // Initialize common data necessary for later.\n // May throw exception from TVM_FFI_ICHECK.\n void init_common(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, ActivationType activation_type);\n\n // Routing logits [num_tokens, num_experts]\n void check_routing_logits_shape() const {\n if (routing_logits.has_value()) {\n TVM_FFI_ICHECK_EQ(routing_logits.value().ndim(), 2) << \"routing_logits must be 2D.\";\n TVM_FFI_ICHECK_EQ(routing_logits.value().size(0), hidden_states.size(0))\n << \"routing_logits and hidden_states must have the same number of tokens.\";\n TVM_FFI_ICHECK_EQ(routing_logits.value().size(1), args->num_experts)\n << \"routing_logits dim1 must match num_experts.\";\n }\n }\n\n // Routing bias [num_experts]\n void check_routing_bias_shape() const {\n if (routing_bias.has_value()) {\n TVM_FFI_ICHECK_EQ(routing_bias.value().ndim(), 1) << \"routing_bias must be 1D.\";\n TVM_FFI_ICHECK_EQ(routing_bias.value().size(0), args->num_experts)\n << \"routing_bias has incorrect shape.\";\n }\n }\n\n // Hidden states [num_tokens, hidden_size]\n void check_hidden_states_shape() const {\n TVM_FFI_ICHECK_EQ(hidden_states.ndim(), 2) << \"hidden_states must be 2D.\";\n TVM_FFI_ICHECK_EQ(hidden_states.size(1), args->intermediate_size)\n << \"hidden_states has incorrect shape.\";\n }\n\n // GEMM1 or GEMM2 weights [num_experts, M, K] or [num_experts, K/block_k, M, block_k]\n void check_weights_shape(std::string which_weights) const {\n TensorView weights = (which_weights == \"gemm1\") ? gemm1_weights : gemm2_weights;\n if (which_weights != \"gemm1\" && which_weights != \"gemm2\") {\n TVM_FFI_LOG_AND_THROW(InternalError) << \"Internal error: which_weights = \" << which_weights;\n }\n\n int64_t Mn = 0, K = 0;\n if (weight_layout == batchedGemm::gemm::MatrixLayout::MajorK) {\n // MajorK [num_experts, M, K]\n Mn = weights.size(1);\n K = weights.size(2);\n } else if (weight_layout == batchedGemm::gemm::MatrixLayout::BlockMajorK) {\n // BlockMajorK [num_experts, K/block_k, M, block_k]\n Mn = weights.size(2);\n int64_t block_k = weights.size(3);\n K = weights.size(1) * block_k;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"Unsupported weight_layout: \" << (int)weight_layout;\n }\n if (which_weights == \"gemm1\") {\n // Gated MoE activations (e.g. Swiglu/Geglu) pack gate+up projections in GEMM1,\n // so Mn = 2 * intermediate_size and must be even.\n if (intermediate_size_factor == 2) {\n TVM_FFI_ICHECK_EQ(Mn % 2, 0) << which_weights << \" weights Mn dimension must be even.\";\n }\n // Non-gated activations (e.g. Relu2) use a single projection in GEMM1,\n // so Mn = intermediate_size. This check covers both gated and non-gated cases.\n TVM_FFI_ICHECK_EQ(args->intermediate_size * intermediate_size_factor, Mn)\n << \"intermediate_size has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(K, hidden_states.size(1))\n << which_weights << \" weights K dimension must be equal to hidden_size.\";\n } else if (which_weights == \"gemm2\") {\n // GEMM2 always consumes the post-activation hidden of size intermediate_size.\n TVM_FFI_ICHECK_EQ(K, args->intermediate_size)\n << which_weights << \" weights K dimension must be equal to intermediate_size.\";\n }\n }\n\n void check_routing_common() const {\n TVM_FFI_ICHECK(args->top_k > 0 && args->top_k <= args->num_experts)\n << \"top_k must be between 1 and num_experts\";\n TVM_FFI_ICHECK(args->local_num_experts > 0 && args->local_num_experts <= args->num_experts)\n << \"local_num_experts must be between 1 and num_experts\";\n TVM_FFI_ICHECK(args->local_expert_offset >= 0 &&\n args->local_expert_offset + args->local_num_experts <= args->num_experts)\n << \"expert offset and count must be within valid range\";\n\n check_routing_logits_shape();\n\n if (routing_bias.has_value()) {\n check_routing_bias_shape();\n }\n }\n\n // Routing phase workspace tensors (allocated in prepare_routing() or prepare_routing_common())\n Tensor num_tokens_per_expert;\n Tensor total_num_padded_tokens;\n Tensor expanded_idx_to_permuted_idx;\n Tensor permuted_idx_to_token_idx;\n Tensor expert_weights;\n Tensor expert_indexes;\n Tensor expert_count_histogram;\n Tensor cta_idx_xy_to_batch_idx;\n Tensor cta_idx_xy_to_mn_limit;\n Tensor num_non_exiting_ctas;\n\n void prepare_routing_common() {\n // Allocate routing phase workspace tensors\n num_tokens_per_expert = alloc_tensor({args->num_experts}, dl_int32, hidden_states.device());\n int32_t max_num_padded_tokens =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::getMaxPermutedPaddedCount(\n args->num_tokens, args->top_k, args->num_experts, tile_tokens_dim);\n\n total_num_padded_tokens = alloc_tensor({1}, dl_int32, hidden_states.device());\n\n expanded_idx_to_permuted_idx =\n alloc_tensor({args->num_tokens * args->top_k}, dl_int32, hidden_states.device());\n\n permuted_idx_to_token_idx =\n alloc_tensor({max_num_padded_tokens}, dl_int32, hidden_states.device());\n\n expert_indexes =\n alloc_tensor({args->num_tokens, args->top_k}, dl_int32, hidden_states.device());\n\n // expert_weights allocation should be done by derived class since data type could vary\n\n int64_t const size_of_expert_count_histogram = std::max(args->num_experts * 2, 256 * 2);\n expert_count_histogram = alloc_tensor({size_of_expert_count_histogram},\n dl_int32, // 256 is the max number of threads per block\n // and max number of experts\n hidden_states.device());\n\n int32_t max_num_ctas = tensorrt_llm::kernels::trtllmgen_moe::Routing::getMaxNumCtasInBatchDim(\n args->num_tokens, args->top_k, args->num_experts, tile_tokens_dim);\n\n cta_idx_xy_to_batch_idx = alloc_tensor({max_num_ctas}, dl_int32, hidden_states.device());\n\n cta_idx_xy_to_mn_limit = alloc_tensor({max_num_ctas}, dl_int32, hidden_states.device());\n\n num_non_exiting_ctas = alloc_tensor({1}, dl_int32, hidden_states.device());\n\n workspace.total_num_padded_tokens = static_cast<int*>(total_num_padded_tokens.data_ptr());\n workspace.total_max_padded_tokens = max_num_padded_tokens;\n workspace.ProjUpTileN = tile_tokens_dim;\n workspace.routing_expert_indexes = static_cast<int*>(expert_indexes.data_ptr());\n workspace.permuted_idx_size = static_cast<int*>(total_num_padded_tokens.data_ptr());\n workspace.expanded_idx_to_permuted_idx =\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr());\n workspace.permuted_idx_to_token_idx = static_cast<int*>(permuted_idx_to_token_idx.data_ptr());\n // workspace.expert_weights will be set by derived class after expert_weights allocation\n workspace.cta_idx_xy_to_batch_idx = static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr());\n workspace.cta_idx_xy_to_mn_limit = static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr());\n workspace.num_non_exiting_ctas = static_cast<int*>(num_non_exiting_ctas.data_ptr());\n }\n\n void check_moe_common() const {\n // Hidden states [num_tokens, hidden_size]\n TVM_FFI_ICHECK_EQ(hidden_states.ndim(), 2) << \"hidden_states must be 2D.\";\n }\n\n // MoE computation phase workspace tensors (allocated in prepare_moe() or prepare_moe_common())\n Tensor gemm1_output;\n Tensor activation_output;\n Tensor gemm2_output;\n Tensor workspace_fc1;\n Tensor workspace_fc2;\n Tensor output;\n int64_t moe_tactic{-1};\n std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner> moe_runner;\n\n void prepare_moe_common(int64_t& moe_tactic) {\n using RunnerType = tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner;\n // For FP8 block-scale (E4m3 activations, E4m3 weights) with DeepSeek FP8, use the\n // weights-only Runner constructor to match the original kernel path and numerics.\n if (this->mDtypeAct == btg::Dtype::E4m3 && this->mDtypeWeights == btg::Dtype::E4m3 &&\n args->mUseDeepSeekFp8) {\n moe_runner = std::make_unique<RunnerType>(this->mDtypeWeights, args->mUseDeepSeekFp8,\n (int32_t)tile_tokens_dim, this->use_shuffled_weight,\n this->weight_layout);\n } else {\n moe_runner = std::make_unique<RunnerType>(\n this->mDtypeAct, this->mDtypeWeights, args->mUseDeepSeekFp8, (int32_t)tile_tokens_dim,\n this->activation_type, this->use_shuffled_weight, this->weight_layout);\n }\n\n if (moe_tactic == -1) {\n moe_tactic = moe_runner->getDefaultValidConfigIndex(\n args->top_k, args->hidden_size, args->intermediate_size, args->local_num_experts,\n args->num_tokens);\n }\n auto valid_cfgs =\n moe_runner->getValidConfigIndices(args->top_k, args->hidden_size, args->intermediate_size,\n args->local_num_experts, args->num_tokens);\n auto valid_it = std::find(valid_cfgs.begin(), valid_cfgs.end(), moe_tactic);\n FLASHINFER_CHECK(valid_it != valid_cfgs.end(), \"Invalid MoE tactic \", moe_tactic,\n \" for tile_N=\", tile_tokens_dim, \". Number of valid tactics for this tile is \",\n valid_cfgs.size(),\n \". This often indicates a stale or mismatched autotuner cache entry.\");\n this->moe_tactic = moe_tactic;\n\n auto workspace_sizes = moe_runner->getWorkspaceSizeInBytes(*args, moe_tactic);\n workspace_fc1 = alloc_tensor({std::get<0>(workspace_sizes)}, dl_int8, hidden_states.device());\n workspace_fc2 = alloc_tensor({std::get<1>(workspace_sizes)}, dl_int8, hidden_states.device());\n workspace.bmm1_workspace = workspace_fc1.data_ptr();\n workspace.bmm2_workspace = workspace_fc2.data_ptr();\n }\n\n public:\n virtual void check_routing() const = 0;\n virtual void prepare_routing() = 0;\n virtual void check_moe() const = 0;\n virtual void prepare_moe(int64_t& moe_tactic) = 0;\n\n // Main entry point for all the executions.\n // Do initializations prior to calling this as the initializations are different for bf16, fp8 and\n // fp4. The executions are non-blocking by default.\n virtual Array<Tensor> run(int64_t moe_tactic, bool enable_pdl = true,\n bool use_routing_scales_on_input = false,\n bool use_deep_seek_fp8 = false) {\n check_routing();\n prepare_routing();\n\n // Execute routing\n tensorrt_llm::kernels::trtllmgen_moe::Routing::Runner routing_runner(tile_tokens_dim);\n cudaStream_t routing_stream = get_stream(hidden_states.device());\n\n routing_runner.run(\n args->routing_logits, args->routing_bias, args->num_tokens, args->num_experts, args->top_k,\n args->n_group, args->topk_group, args->local_expert_offset, args->local_num_experts,\n args->routed_scaling_factor, workspace.routing_expert_indexes,\n static_cast<int*>(expert_count_histogram.data_ptr()),\n static_cast<int*>(total_num_padded_tokens.data_ptr()),\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr()),\n nullptr /*permuted_idx_to_expanded_idx.data_ptr()*/,\n static_cast<int*>(permuted_idx_to_token_idx.data_ptr()), workspace.expert_weights,\n static_cast<int*>(num_tokens_per_expert.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr()),\n static_cast<int*>(num_non_exiting_ctas.data_ptr()), args->mDtypeElt, mRoutingBiasDtype,\n use_routing_scales_on_input, use_deep_seek_fp8,\n static_cast<RoutingMethodType>(routing_method_type), routing_stream);\n\n check_moe();\n prepare_moe(moe_tactic);\n\n cudaStream_t moe_stream = get_stream(hidden_states.device());\n moe_runner->run(*args, workspace, hidden_states.device().device_id, moe_stream, moe_tactic,\n enable_pdl);\n\n if (args->do_finalize) {\n return {output};\n }\n return {gemm2_output, FusedMoeLauncher::expert_weights, expanded_idx_to_permuted_idx};\n }\n};\n\nvoid FusedMoeLauncher::init_common(\n std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, ActivationType activation_type) {\n // Check devicearchitecture: Blackwell (SM 10.x) required\n auto device = hidden_states.device().device_id;\n int major = 0, minor = 0;\n cudaDeviceGetAttribute(&major, cudaDevAttrComputeCapabilityMajor, device);\n cudaDeviceGetAttribute(&minor, cudaDevAttrComputeCapabilityMinor, device);\n TVM_FFI_ICHECK(major == 10 || major == 12)\n << \"MoE kernel requires SM 10.x or SM 12.x architecture. Current device has SM \" << major\n << minor;\n this->device_version = std::make_tuple(major, minor);\n\n args->routing_logits = routing_logits.has_value() ? routing_logits.value().data_ptr() : nullptr;\n args->routing_bias = routing_bias.has_value() ? routing_bias.value().data_ptr() : nullptr;\n args->hidden_states = hidden_states.data_ptr();\n args->gemm1_weights = gemm1_weights.data_ptr();\n args->gemm2_weights = gemm2_weights.data_ptr();\n\n this->args = std::move(args);\n this->tile_tokens_dim = tile_tokens_dim;\n this->routing_method_type = routing_method_type;\n this->use_shuffled_weight = use_shuffled_weight;\n TVM_FFI_ICHECK(0 <= weight_layout && weight_layout <= 2)\n << \"the value of weight_layout is not recognized\";\n this->weight_layout = static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout);\n this->activation_type = activation_type;\n this->intermediate_size_factor = isGatedActivation(activation_type) ? 2 : 1;\n}\n\nclass Bf16MoeLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 5> mSupportedTileNums = {8, 16, 32, 64, 128};\n\n Bf16MoeLauncher(Optional<TensorView> const& routing_logits,\n Optional<TensorView> const& routing_bias, TensorView const& expert_indices,\n TensorView const& expert_weights, TensorView const& hidden_states,\n TensorView const& gemm1_weights, TensorView const& gemm2_weights)\n : FusedMoeLauncher(routing_logits, routing_bias, hidden_states, gemm1_weights,\n Optional<TensorView>(), Optional<TensorView>(), gemm2_weights,\n Optional<TensorView>()),\n expert_indices(expert_indices),\n expert_weights(expert_weights) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout) {\n constexpr ActivationType activation_type =\n ActivationType::Swiglu; // not exposed in api for now\n\n // Do base class init and perform common checks\n FusedMoeLauncher::init_common(std::move(args), tile_tokens_dim, routing_method_type,\n use_shuffled_weight, weight_layout, activation_type);\n }\n\n void check_routing() const override {\n FusedMoeLauncher::check_routing_common();\n if (expert_indices.ndim() == 2 && expert_indices.size(0) > 0) {\n // Pre-computed routing: expert_indices is a packed tensor\n // Format: (expert_id << 16) | (weight_bf16.view(int16))\n TVM_FFI_ICHECK_EQ(expert_indices.ndim(), 2) << \"expert_indices must be 2D.\";\n TVM_FFI_ICHECK_EQ(expert_indices.size(0), hidden_states.size(0))\n << \"expert_indices and hidden_states must have same number of tokens.\";\n TVM_FFI_ICHECK_EQ(expert_indices.size(1), args->top_k)\n << \"expert_indices dim1 must match top_k.\";\n TVM_FFI_ICHECK_EQ(expert_indices.dtype(), dl_int32) << \"expert_indices must be int32.\";\n }\n\n // TODO n_group, topk_group validation?\n }\n\n void prepare_routing() override {\n FusedMoeLauncher::prepare_routing_common();\n\n args->mDtypeElt = btg::Dtype::Bfloat16;\n args->mUseDeepSeekFp8 = false;\n\n // Set expert weights dtype based on routing bias\n auto const routing_bias_dtype =\n routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool has_precomputed_indices = expert_indices.ndim() == 2 && expert_indices.size(0) > 0;\n if (has_precomputed_indices) {\n // Use expert_indices directly\n workspace.routing_expert_indexes =\n static_cast<int*>(const_cast<void*>(expert_indices.data_ptr()));\n }\n bool has_precomputed_weights = expert_weights.ndim() == 2 && expert_weights.size(0) > 0;\n if (has_precomputed_weights) {\n workspace.expert_weights = const_cast<void*>(expert_weights.data_ptr());\n } else {\n FusedMoeLauncher::expert_weights =\n alloc_tensor({args->num_tokens, args->top_k}, dl_bfloat16, hidden_states.device());\n workspace.expert_weights = FusedMoeLauncher::expert_weights.data_ptr();\n }\n }\n\n void check_moe() const override {\n FusedMoeLauncher::check_moe_common();\n\n TVM_FFI_ICHECK(weight_layout == batchedGemm::gemm::MatrixLayout::BlockMajorK)\n << \"BF16 Moe: weight_layout must be BlockMajorK\";\n check_weights_shape(\"gemm1\");\n check_weights_shape(\"gemm2\");\n\n TVM_FFI_ICHECK_EQ(args->intermediate_size % 128, 0)\n << \"the second dimension of weights must be a multiple of 128.\";\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n int32_t max_num_padded_tokens = workspace.total_max_padded_tokens;\n gemm1_output = alloc_tensor({max_num_padded_tokens, args->intermediate_size}, dl_bfloat16,\n hidden_states.device());\n activation_output = alloc_tensor({max_num_padded_tokens, args->intermediate_size}, dl_bfloat16,\n hidden_states.device());\n gemm2_output = alloc_tensor({max_num_padded_tokens, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n workspace.hidden_states_scale_linear = nullptr;\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = nullptr;\n workspace.activation_output = activation_output.data_ptr();\n workspace.activation_output_scale = nullptr;\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n\n if (args->output == nullptr) {\n output =\n alloc_tensor({args->num_tokens, args->hidden_size}, dl_bfloat16, hidden_states.device());\n args->output = output.data_ptr();\n }\n args->output_scale = nullptr;\n }\n\n static Array<Array<int64_t>> getValidConfigs(int64_t top_k, int64_t hidden_size,\n int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens, int64_t act_type,\n bool use_shuffled_weight, int64_t weight_layout) {\n Array<Array<int64_t>> valid_configs;\n\n std::vector<int32_t> supported_tile_nums(mSupportedTileNums.begin(), mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n auto moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n btg::Dtype::Bfloat16, // dtype_act\n btg::Dtype::Bfloat16, // dtype_weights\n false, // useDeepSeekFp8\n tile_N, static_cast<ActivationType>(act_type), use_shuffled_weight,\n static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout));\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n\n private:\n TensorView expert_weights;\n TensorView expert_indices;\n};\n\nclass Fp8PerTensorLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 5> mSupportedTileNums = {8, 16, 32, 64, 128};\n\n // Constructor that passes TensorView parameters to base constructor\n Fp8PerTensorLauncher(TensorView const& routing_logits, Optional<TensorView> const& routing_bias,\n TensorView const& hidden_states, TensorView const& gemm1_weights,\n TensorView const& output1_scales_scalar,\n TensorView const& output1_scales_gate_scalar,\n TensorView const& gemm2_weights, TensorView const& output2_scales_scalar)\n : FusedMoeLauncher(Optional<TensorView>(routing_logits), routing_bias, hidden_states,\n gemm1_weights, Optional<TensorView>(output1_scales_scalar),\n Optional<TensorView>(output1_scales_gate_scalar), gemm2_weights,\n Optional<TensorView>(output2_scales_scalar)),\n use_routing_scales_on_input(false) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, bool use_routing_scales_on_input_param,\n ActivationType activation_type) {\n this->use_routing_scales_on_input = use_routing_scales_on_input_param;\n\n auto dtype = hidden_states.dtype();\n if (dtype == dl_float16) {\n mDtypeAct = btg::Dtype::Fp16;\n } else if (dtype == dl_bfloat16) {\n mDtypeAct = btg::Dtype::Bfloat16;\n } else if (dtype == dl_float8_e4m3fn) {\n mDtypeAct = btg::Dtype::E4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for FP8 MoE.\";\n }\n mDtypeWeights = btg::Dtype::E4m3;\n\n FusedMoeLauncher::init_common(std::move(args), tile_tokens_dim, routing_method_type,\n use_shuffled_weight, weight_layout, activation_type);\n }\n\n void check_routing() const override { FusedMoeLauncher::check_routing_common(); }\n\n void prepare_routing() override {\n FusedMoeLauncher::prepare_routing_common();\n\n auto dtype = hidden_states.dtype();\n if (dtype == dl_float16) {\n args->mDtypeElt = btg::Dtype::Fp16;\n } else if (dtype == dl_bfloat16) {\n args->mDtypeElt = btg::Dtype::Bfloat16;\n } else if (dtype == dl_float8_e4m3fn) {\n args->mDtypeElt = btg::Dtype::E4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for MoE.\";\n }\n\n args->mDtypeOut = btg::Dtype::Bfloat16;\n args->mUseDeepSeekFp8 = false;\n\n auto const routing_bias_dtype =\n routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n\n expert_weights =\n alloc_tensor({args->num_tokens, args->top_k}, dl_bfloat16, hidden_states.device());\n\n workspace.expert_weights = expert_weights.data_ptr();\n if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::Llama4) {\n workspace.token_scales = expert_weights.data_ptr(); // Consumed by permuteGemm1 kernel\n }\n }\n\n void check_moe() const override {\n FusedMoeLauncher::check_moe_common();\n\n TVM_FFI_ICHECK(output1_scales_scalar.has_value())\n << \"output1_scales_scalar is required for FP8 MoE\";\n TVM_FFI_ICHECK_EQ(output1_scales_scalar.value().dtype(), dl_float32)\n << \"output1_scales_scalar must be float.\";\n TVM_FFI_ICHECK_EQ(output1_scales_scalar.value().ndim(), 1)\n << \"output1_scales_scalar must be 1D.\";\n TVM_FFI_ICHECK_EQ(output1_scales_scalar.value().size(0), args->local_num_experts)\n << \"output1_scales_scalar has incorrect dim 0.\";\n\n TVM_FFI_ICHECK(output1_scales_gate_scalar.has_value())\n << \"output1_scales_gate_scalar is required for FP8 MoE\";\n TVM_FFI_ICHECK_EQ(output1_scales_gate_scalar.value().dtype(), dl_float32)\n << \"output1_scales_gate_scalar must be float.\";\n TVM_FFI_ICHECK_EQ(output1_scales_gate_scalar.value().ndim(), 1)\n << \"output1_scales_gate_scalar must be 1D.\";\n TVM_FFI_ICHECK_EQ(output1_scales_gate_scalar.value().size(0), args->local_num_experts)\n << \"output1_scales_gate_scalar has incorrect dim 0.\";\n\n TVM_FFI_ICHECK(output2_scales_scalar.has_value())\n << \"output2_scales_scalar is required for FP8 MoE\";\n TVM_FFI_ICHECK_EQ(output2_scales_scalar.value().dtype(), dl_float32)\n << \"output2_scales_scalar must be float.\";\n TVM_FFI_ICHECK_EQ(output2_scales_scalar.value().ndim(), 1)\n << \"output2_scales_scalar must be 1D.\";\n TVM_FFI_ICHECK_EQ(output2_scales_scalar.value().size(0), args->local_num_experts)\n << \"output2_scales_scalar has incorrect dim 0.\";\n\n TVM_FFI_ICHECK(hidden_states.dtype() == dl_float8_e4m3fn ||\n hidden_states.dtype() == dl_float16 || hidden_states.dtype() == dl_bfloat16)\n << \"FP8 MoE: hidden_states must be float8_e4m3fn, float16, or bfloat16.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 MoE: gemm1_weights must be float8_e4m3fn.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 MoE: gemm2_weights must be float8_e4m3fn.\";\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n int32_t max_num_padded_tokens_gemm1 = workspace.total_max_padded_tokens + args->num_experts;\n int32_t max_num_padded_tokens_gemm2 = workspace.total_max_padded_tokens;\n\n gemm1_output = alloc_tensor({max_num_padded_tokens_gemm1, 2 * args->intermediate_size},\n dl_uint8, hidden_states.device());\n gemm1_output_scale =\n alloc_tensor({2 * args->intermediate_size / 128, max_num_padded_tokens_gemm1}, dl_float32,\n hidden_states.device());\n\n activation_output = alloc_tensor({max_num_padded_tokens_gemm1, args->intermediate_size},\n dl_uint8, hidden_states.device());\n activation_output_scale =\n alloc_tensor({args->intermediate_size / 128, max_num_padded_tokens_gemm1}, dl_float32,\n hidden_states.device());\n\n gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n workspace.hidden_states_scale_linear = nullptr;\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = static_cast<float*>(gemm1_output_scale.data_ptr());\n workspace.activation_output = activation_output.data_ptr();\n workspace.activation_output_scale = static_cast<float*>(activation_output_scale.data_ptr());\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n\n if (args->output == nullptr) {\n output =\n alloc_tensor({args->num_tokens, args->hidden_size}, dl_bfloat16, hidden_states.device());\n args->output = output.data_ptr();\n }\n args->output_scale = nullptr;\n\n // Set scale pointers\n TVM_FFI_ICHECK(output1_scales_scalar.has_value());\n TVM_FFI_ICHECK(output1_scales_gate_scalar.has_value());\n TVM_FFI_ICHECK(output2_scales_scalar.has_value());\n\n args->output1_scales_scalar = static_cast<float*>(output1_scales_scalar.value().data_ptr());\n args->output1_scales_gate_scalar =\n static_cast<float*>(output1_scales_gate_scalar.value().data_ptr());\n args->output2_scales_scalar = static_cast<float*>(output2_scales_scalar.value().data_ptr());\n }\n\n private:\n bool use_routing_scales_on_input;\n Tensor gemm1_output_scale;\n Tensor activation_output_scale;\n\n public:\n static Array<Array<int64_t>> getValidConfigs(int64_t top_k, int64_t hidden_size,\n int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens, int64_t act_type,\n bool use_shuffled_weight, int64_t weight_layout,\n btg::Dtype dtype_act, btg::Dtype dtype_weights) {\n Array<Array<int64_t>> valid_configs;\n\n std::vector<int32_t> supported_tile_nums(mSupportedTileNums.begin(), mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n auto moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n dtype_act, dtype_weights,\n false, // useDeepSeekFp8\n tile_N, static_cast<ActivationType>(act_type), use_shuffled_weight,\n static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout));\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n};\n\nclass Fp8BlockScaleLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 5> mBaseSupportedTileNums = {8, 16, 32, 64, 128};\n\n static std::vector<int32_t> getSupportedTileNums(Fp8QuantizationType quantization_type) {\n std::vector<int32_t> tiles(mBaseSupportedTileNums.begin(), mBaseSupportedTileNums.end());\n if (quantization_type == Fp8QuantizationType::MxFp8) {\n tiles.push_back(256);\n }\n return tiles;\n }\n\n Fp8BlockScaleLauncher(Optional<TensorView> const& routing_logits,\n Optional<TensorView> const& routing_bias, TensorView const& hidden_states,\n TensorView const& hidden_states_scale, TensorView const& gemm1_weights,\n TensorView const& gemm1_weights_scale, TensorView const& gemm2_weights,\n TensorView const& gemm2_weights_scale, TensorView const& expert_indices,\n TensorView const& expert_weights, Fp8QuantizationType quantization_type)\n : FusedMoeLauncher(routing_logits, routing_bias, hidden_states, gemm1_weights,\n Optional<TensorView>(), Optional<TensorView>(), gemm2_weights,\n Optional<TensorView>()),\n hidden_states_scale(hidden_states_scale),\n gemm1_weights_scale(gemm1_weights_scale),\n gemm2_weights_scale(gemm2_weights_scale),\n expert_indices(expert_indices),\n expert_weights(expert_weights),\n quantization_type(quantization_type) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, ActivationType activation_type) {\n if (quantization_type == Fp8QuantizationType::MxFp8) {\n mDtypeAct = btg::Dtype::MxE4m3;\n mDtypeWeights = btg::Dtype::MxE4m3;\n } else {\n mDtypeAct = btg::Dtype::E4m3;\n mDtypeWeights = btg::Dtype::E4m3;\n }\n\n auto dtype = hidden_states.dtype();\n if (dtype == dl_float16) {\n args->mDtypeElt = btg::Dtype::Fp16;\n } else if (dtype == dl_bfloat16) {\n args->mDtypeElt = btg::Dtype::Bfloat16;\n } else if (dtype == dl_float8_e4m3fn) {\n args->mDtypeElt = btg::Dtype::E4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for MoE.\";\n }\n\n // Output is always bfloat16 for FP8 block scale\n args->mDtypeOut = btg::Dtype::Bfloat16;\n\n FusedMoeLauncher::init_common(std::move(args), tile_tokens_dim, routing_method_type,\n use_shuffled_weight, weight_layout, activation_type);\n }\n\n void check_routing() const override {\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n if (expert_indices.ndim() == 2 && expert_indices.size(0) > 0) {\n // Pre-computed routing: expert_indices is a packed tensor\n // Format: (expert_id << 16) | (weight_bf16.view(int16))\n TVM_FFI_ICHECK_EQ(expert_indices.ndim(), 2) << \"expert_indices must be 2D.\";\n TVM_FFI_ICHECK_EQ(expert_indices.size(0), hidden_states.size(0))\n << \"expert_indices and hidden_states must have same number of tokens.\";\n TVM_FFI_ICHECK_EQ(expert_indices.size(1), args->top_k)\n << \"expert_indices dim1 must match top_k.\";\n TVM_FFI_ICHECK_EQ(expert_indices.dtype(), dl_int32) << \"expert_indices must be int32.\";\n }\n\n FusedMoeLauncher::check_routing_common();\n\n if (static_cast<RoutingMethodType>(routing_method_type) != RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK(args->n_group <= 1)\n << \"Current routing kernel (no groups) only supports n_group <= 1\";\n TVM_FFI_ICHECK(args->topk_group <= 1)\n << \"Current routing kernel (no groups) only supports topk_group <= 1\";\n }\n\n if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK(args->n_group != 0) << \"n_group should not be zero for DeepSeekV3 routing\";\n TVM_FFI_ICHECK(args->topk_group != 0) << \"if n_group is given, topk_group must be given\";\n TVM_FFI_ICHECK_EQ(args->num_experts % args->n_group, 0)\n << \"num_experts must be divisible by n_group\";\n // DeepSeekV3 routing supports top_k up to:\n // - 8 when num_experts <= 384 (NumKimiK2Experts)\n // - 22 when num_experts > 384 (NumNemotronExperts path)\n // Keep this in sync with LAUNCH_ROUTING_DEEPSEEK in trtllm_fused_moe_routing_deepseek.cu.\n constexpr int32_t kNumKimiK2Experts = 384; // same as in trtllm_fused_moe_routing_deepseek.cu\n int32_t max_supported_top_k = args->num_experts <= kNumKimiK2Experts ? 8 : 22;\n TVM_FFI_ICHECK(args->top_k <= max_supported_top_k && args->top_k > 0)\n << \"Current routing kernel (with groups) only supports top_k<=\" << max_supported_top_k\n << \" && top_k>0 for num_experts=\" << args->num_experts << \".\";\n TVM_FFI_ICHECK(args->topk_group <= 4 && args->topk_group > 0)\n << \"Current routing kernel only (with groups) supports topk_group<=4 && topk_group > 0.\";\n TVM_FFI_ICHECK_LE(args->topk_group, args->n_group)\n << \"n_group must not be smaller than topk_group.\";\n TVM_FFI_ICHECK_LT(args->top_k, (args->topk_group * args->num_experts / args->n_group))\n << \"top_k must be less than total number of experts in selected groups\";\n } else if (static_cast<RoutingMethodType>(routing_method_type) ==\n RoutingMethodType::Renormalize ||\n static_cast<RoutingMethodType>(routing_method_type) ==\n RoutingMethodType::RenormalizeNaive) {\n TVM_FFI_ICHECK(args->top_k <= 32 && args->top_k > 0)\n << \"Current routing kernel (no groups, renormalize) only supports top_k<=10 && top_k>0.\";\n } else if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::Llama4) {\n TVM_FFI_ICHECK_EQ(args->top_k, 1)\n << \"Current routing kernel (no groups, Llama4) only supports top_k=1.\";\n }\n\n TVM_FFI_ICHECK_EQ(args->num_experts % 4, 0)\n << \"Routing kernel expects that num_experts must be divisible by 4\";\n TVM_FFI_ICHECK_GT(args->num_experts, args->top_k) << \"num_experts must be greater than top_k\";\n TVM_FFI_ICHECK_LE(args->local_num_experts + args->local_expert_offset, args->num_experts)\n << \"num_experts must be greater or equal to local_num_experts + local_expert_offset\";\n }\n\n void prepare_routing() override {\n FusedMoeLauncher::prepare_routing_common();\n\n auto dtype = hidden_states.dtype();\n if (dtype == dl_float16) {\n args->mDtypeElt = btg::Dtype::Fp16;\n } else if (dtype == dl_bfloat16) {\n args->mDtypeElt = btg::Dtype::Bfloat16;\n } else if (dtype == dl_float8_e4m3fn) {\n args->mDtypeElt = btg::Dtype::E4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for MoE.\";\n }\n\n args->mUseDeepSeekFp8 = quantization_type == Fp8QuantizationType::DeepSeekFp8;\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool has_precomputed_indices = expert_indices.ndim() == 2 && expert_indices.size(0) > 0;\n if (has_precomputed_indices) {\n // Use expert_indices directly\n workspace.routing_expert_indexes =\n static_cast<int*>(const_cast<void*>(expert_indices.data_ptr()));\n } else {\n // Use routing_logits directly\n args->routing_logits = static_cast<float*>(routing_logits.value().data_ptr());\n }\n // Set expert weights dtype based on routing bias\n auto const routing_bias_dtype =\n routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool has_precomputed_weights = expert_weights.ndim() == 2 && expert_weights.size(0) > 0;\n if (!has_precomputed_weights) {\n // Allocate expert_weights buffer for routing output\n FusedMoeLauncher::expert_weights =\n alloc_tensor({args->num_tokens, args->top_k}, dl_bfloat16, hidden_states.device());\n workspace.expert_weights = FusedMoeLauncher::expert_weights.data_ptr();\n } else {\n workspace.expert_weights = const_cast<void*>(expert_weights.data_ptr());\n }\n }\n\n void check_moe() const override {\n FusedMoeLauncher::check_moe_common();\n\n TVM_FFI_ICHECK_EQ(hidden_states.dtype(), dl_float8_e4m3fn) << \"hidden_states must be fp8.\";\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(hidden_states_scale.dtype(), dl_float32)\n << \"hidden_states_scale must be float.\";\n TVM_FFI_ICHECK_EQ(hidden_states_scale.ndim(), 2) << \"hidden_states_scale must be 2D.\";\n TVM_FFI_ICHECK_EQ(hidden_states_scale.size(0), hidden_states.size(1) / 128)\n << \"hidden_states_scale dim0 must match hidden_states dim1 / 128.\";\n TVM_FFI_ICHECK_EQ(hidden_states_scale.size(1), args->num_tokens)\n << \"hidden_states_scale dim1 must match num_tokens.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_CHECK(weight_layout == batchedGemm::gemm::MatrixLayout::MajorK,\n \"weight_layout must be MajorK for MxFp8.\");\n TVM_FFI_ICHECK_EQ(hidden_states_scale.dtype(), dl_uint8);\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_float8_e4m3fn) << \"gemm1_weights must be fp8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_float8_e4m3fn) << \"gemm2_weights must be fp8.\";\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_float32)\n << \"gemm1_weights_scale must be float.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.ndim(), 3) << \"gemm1_weights_scale must be 3D.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.size(0), args->local_num_experts)\n << \"gemm1_weights_scale has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(args->intermediate_size % 128, 0)\n << \"intermediate_size must be a multiple of 128.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.size(1),\n intermediate_size_factor * args->intermediate_size / 128)\n << \"gemm1_weights_scale has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.size(2), args->hidden_size / 128)\n << \"gemm1_weights_scale has incorrect shape.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_uint8)\n << \"gemm1_weights_scale must be uint8.\";\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_float32)\n << \"gemm2_weights_scale must be float.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.ndim(), 3) << \"gemm2_weights_scale must be 3D.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.size(0), args->local_num_experts)\n << \"gemm2_weights_scale has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.size(1), args->hidden_size / 128)\n << \"gemm2_weights_scale has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.size(2), args->intermediate_size / 128)\n << \"gemm2_weights_scale has incorrect shape.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_uint8)\n << \"gemm2_weights_scale must be uint8.\";\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n\n check_weights_shape(\"gemm1\");\n check_weights_shape(\"gemm2\");\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(args->intermediate_size % 128, 0)\n << \"intermediate_size must be a multiple of 128.\";\n }\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n // Calculate max_num_padded_tokens for gemm1 and gemm2 using maybeGetMinTokenCount\n int32_t max_num_padded_tokens_gemm1 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->intermediate_size,\n btg::dtypeGetNumBits(args->mDtypeElt));\n int32_t max_num_padded_tokens_gemm2 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->hidden_size,\n btg::dtypeGetNumBits(args->mDtypeOut));\n\n gemm1_output = alloc_tensor(\n {max_num_padded_tokens_gemm1, intermediate_size_factor * args->intermediate_size}, dl_uint8,\n hidden_states.device());\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n gemm1_output_scale = alloc_tensor({intermediate_size_factor * args->intermediate_size / 128,\n workspace.total_max_padded_tokens},\n dl_float32, hidden_states.device());\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n // MxFP8 fuses the activation so no need for intermediate_size_factor\n int64_t sf_size = tensorrt_llm::computeSwizzledLayoutSFSize(max_num_padded_tokens_gemm1,\n args->intermediate_size / 32);\n gemm1_output_scale = alloc_tensor({sf_size}, dl_uint8, hidden_states.device());\n }\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n activation_output = alloc_tensor({max_num_padded_tokens_gemm1, args->intermediate_size},\n dl_uint8, hidden_states.device());\n activation_output_scale =\n alloc_tensor({args->intermediate_size / 128, max_num_padded_tokens_gemm1}, dl_float32,\n hidden_states.device());\n }\n\n gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n workspace.hidden_states_scale_linear = nullptr;\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = static_cast<float*>(gemm1_output_scale.data_ptr());\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n workspace.activation_output = activation_output.data_ptr();\n workspace.activation_output_scale = static_cast<float*>(activation_output_scale.data_ptr());\n }\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n\n if (args->output == nullptr) {\n output =\n alloc_tensor({args->num_tokens, args->hidden_size}, dl_bfloat16, hidden_states.device());\n args->output = output.data_ptr();\n }\n args->output_scale = nullptr;\n\n args->hidden_states_scale = static_cast<float*>(hidden_states_scale.data_ptr());\n args->gemm1_weights_scale = static_cast<float*>(gemm1_weights_scale.data_ptr());\n args->gemm2_weights_scale = static_cast<float*>(gemm2_weights_scale.data_ptr());\n }\n\n private:\n TensorView hidden_states_scale;\n TensorView gemm1_weights_scale;\n TensorView gemm2_weights_scale;\n Tensor gemm1_output_scale;\n Tensor activation_output_scale;\n TensorView expert_indices;\n TensorView expert_weights;\n Fp8QuantizationType quantization_type;\n\n public:\n // Override to handle pre-computed routing\n Array<Tensor> run(int64_t moe_tactic, bool enable_pdl = true,\n bool use_routing_scales_on_input = false,\n bool use_deep_seek_fp8 = false) override {\n check_routing();\n prepare_routing();\n\n cudaStream_t routing_stream = get_stream(hidden_states.device());\n tensorrt_llm::kernels::trtllmgen_moe::Routing::Runner routing_runner(tile_tokens_dim);\n\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool use_precomputed = expert_indices.ndim() == 2 && expert_indices.size(0) > 0;\n // When using pre-computed routing, pass nullptr as routing_logits to tell the\n // routing runner to use the pre-computed expert indices from workspace.routing_expert_indexes\n routing_runner.run(\n use_precomputed ? nullptr : args->routing_logits, args->routing_bias, args->num_tokens,\n args->num_experts, args->top_k, args->n_group, args->topk_group, args->local_expert_offset,\n args->local_num_experts, args->routed_scaling_factor, workspace.routing_expert_indexes,\n static_cast<int*>(expert_count_histogram.data_ptr()),\n static_cast<int*>(total_num_padded_tokens.data_ptr()),\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr()),\n nullptr /*permuted_idx_to_expanded_idx.data_ptr()*/,\n static_cast<int*>(permuted_idx_to_token_idx.data_ptr()), workspace.expert_weights,\n static_cast<int*>(num_tokens_per_expert.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr()),\n static_cast<int*>(num_non_exiting_ctas.data_ptr()), args->mDtypeElt, mRoutingBiasDtype,\n use_routing_scales_on_input, use_deep_seek_fp8,\n static_cast<RoutingMethodType>(routing_method_type), routing_stream);\n\n check_moe();\n prepare_moe(moe_tactic);\n\n cudaStream_t moe_stream = get_stream(hidden_states.device());\n moe_runner->run(*args, workspace, hidden_states.device().device_id, moe_stream, moe_tactic,\n enable_pdl);\n\n if (args->do_finalize) {\n return {output};\n }\n return {gemm2_output, FusedMoeLauncher::expert_weights, expanded_idx_to_permuted_idx};\n }\n\n static Array<Array<int64_t>> getValidConfigs(\n int64_t top_k, int64_t hidden_size, int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens, bool use_shuffled_weight, int64_t weight_layout, btg::Dtype dtype_act,\n btg::Dtype dtype_weights, Fp8QuantizationType quantization_type, int64_t act_type) {\n Array<Array<int64_t>> valid_configs;\n auto activation_type = validateAndCastActivationType(act_type);\n\n auto supported_tile_nums = getSupportedTileNums(quantization_type);\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner> moe_runner;\n // Keep getValidConfigs constructor path aligned with runtime prepare_moe_common().\n // This branch is for DeepSeek FP8 (E4m3 activations + E4m3 weights).\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8 && dtype_act == btg::Dtype::E4m3 &&\n dtype_weights == btg::Dtype::E4m3) {\n TVM_FFI_ICHECK(static_cast<int>(activation_type) ==\n static_cast<int>(ActivationType::Swiglu))\n << \"DeepSeekFp8 only supports ActivationType::Swiglu, got \"\n << static_cast<int>(activation_type) << \".\";\n moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n dtype_weights, true /* useDeepSeekFp8 */, tile_N, use_shuffled_weight,\n static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout));\n } else {\n // Under current trtllm_get_valid_moe_configs() dispatch rules, this else-path is\n // reached only by FP8 block-scale MXFP8 (dtype_act=dtype_weights=MxE4m3).\n moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n dtype_act, // dtypeAct\n dtype_weights, // dtypeWeights\n quantization_type == Fp8QuantizationType::DeepSeekFp8, // useDeepSeekFp8\n tile_N, activation_type, use_shuffled_weight,\n static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout));\n }\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n};\n\nclass MxInt4BlockScaleLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 5> mSupportedTileNums = {8, 16, 32, 64, 128};\n\n MxInt4BlockScaleLauncher(TensorView const& routing_logits,\n Optional<TensorView> const& routing_bias,\n TensorView const& hidden_states, TensorView const& gemm1_weights,\n TensorView const& gemm1_weights_scale,\n Optional<TensorView> const& gemm1_alpha,\n Optional<TensorView> const& gemm1_beta,\n Optional<TensorView> const& gemm1_clamp_limit,\n TensorView const& gemm2_weights, TensorView const& gemm2_weights_scale)\n : FusedMoeLauncher(Optional<TensorView>(routing_logits), routing_bias, hidden_states,\n gemm1_weights, Optional<TensorView>(), Optional<TensorView>(),\n gemm2_weights, Optional<TensorView>()),\n gemm1_weights_scale(gemm1_weights_scale),\n gemm2_weights_scale(gemm2_weights_scale) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type) {\n // currently only support mxint4 x bf16\n auto dtype = hidden_states.dtype();\n if (dtype == dl_bfloat16) {\n args->mDtypeElt = btg::Dtype::Bfloat16;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for MoE.\";\n }\n args->mDtypeOut = btg::Dtype::Bfloat16;\n\n mDtypeAct = btg::Dtype::Bfloat16;\n mDtypeWeights = btg::Dtype::MxInt4;\n\n FusedMoeLauncher::init_common(\n std::move(args), tile_tokens_dim, routing_method_type,\n /*use_shuffled_weight=*/true,\n static_cast<int64_t>(batchedGemm::gemm::MatrixLayout::BlockMajorK), ActivationType::Swiglu);\n }\n\n void check_routing() const override { FusedMoeLauncher::check_routing_common(); }\n\n void prepare_routing() override {\n FusedMoeLauncher::prepare_routing_common();\n\n args->mDtypeElt = mDtypeAct;\n args->mUseDeepSeekFp8 = false;\n // Set expert weights dtype based on routing bias\n auto const routing_bias_dtype =\n routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n\n expert_weights =\n alloc_tensor({args->num_tokens, args->top_k}, dl_bfloat16, hidden_states.device());\n\n workspace.expert_weights = expert_weights.data_ptr();\n }\n\n void check_moe() const override {\n TVM_FFI_ICHECK(mDtypeAct == btg::Dtype::Bfloat16)\n << \"Only Bfloat16 is supported by MxInt4 block scale MoE\";\n\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_uint8) << \"gemm1_weights must be uint8.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_bfloat16)\n << \"gemm1_weights_scale must be bf16.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_uint8) << \"gemm2_weights must be uint8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_bfloat16)\n << \"gemm2_weights_scale must be bf16.\";\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n args->hidden_states = hidden_states.data_ptr();\n args->hidden_states_scale = nullptr;\n args->gemm1_weights = gemm1_weights.data_ptr();\n args->gemm1_weights_scale = gemm1_weights_scale.data_ptr();\n args->gemm1_alpha =\n gemm1_alpha.has_value() ? static_cast<float*>(gemm1_alpha.value().data_ptr()) : nullptr;\n args->gemm1_beta =\n gemm1_beta.has_value() ? static_cast<float*>(gemm1_beta.value().data_ptr()) : nullptr;\n args->gemm1_clamp_limit = gemm1_clamp_limit.has_value()\n ? static_cast<float*>(gemm1_clamp_limit.value().data_ptr())\n : nullptr;\n args->gemm2_weights = gemm2_weights.data_ptr();\n args->gemm2_weights_scale = gemm2_weights_scale.data_ptr();\n args->output1_scales_scalar = nullptr;\n args->output1_scales_gate_scalar = nullptr;\n args->output2_scales_scalar = nullptr;\n\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n max_num_padded_tokens_gemm1 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->intermediate_size,\n btg::dtypeGetNumBits(mDtypeAct));\n max_num_padded_tokens_gemm2 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->hidden_size,\n btg::dtypeGetNumBits(btg::Dtype::Bfloat16)); // Output is always BF16\n\n auto const gemm1_output_hidden = args->intermediate_size;\n gemm1_output = alloc_tensor({max_num_padded_tokens_gemm1, gemm1_output_hidden}, dl_bfloat16,\n hidden_states.device());\n\n // Allocate gemm2_output\n gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n // Setup workspace pointers\n workspace.hidden_states_scale_linear = nullptr; // MxInt4 doesn't use linear scale\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = nullptr;\n // Note: activation_output and activation_output_scale are set by the base class\n // prepare_moe_common() when gated activation is used\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n }\n\n private:\n TensorView gemm1_weights_scale;\n Optional<TensorView> gemm1_alpha;\n Optional<TensorView> gemm1_beta;\n Optional<TensorView> gemm1_clamp_limit;\n TensorView gemm2_weights_scale;\n int32_t max_num_padded_tokens_gemm1{};\n int32_t max_num_padded_tokens_gemm2{};\n\n public:\n static Array<Array<int64_t>> getValidConfigs(int64_t top_k, int64_t hidden_size,\n int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens) {\n Array<Array<int64_t>> valid_configs;\n\n std::vector<int32_t> tile_sizes(mSupportedTileNums.begin(), mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(tile_sizes, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n auto moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n btg::Dtype::Bfloat16, btg::Dtype::MxInt4,\n false, // useDeepSeekFp8\n tile_N, ActivationType::Swiglu,\n /*useShuffledMatrix*/ true, batchedGemm::gemm::MatrixLayout::BlockMajorK);\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n};\n\nclass FP4BlockScaleLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 4> mBaseSupportedTileNums = {8, 16, 32, 64};\n\n static std::vector<int32_t> getSupportedTileNums(btg::Dtype dtype_act) {\n std::vector<int32_t> tiles(mBaseSupportedTileNums.begin(), mBaseSupportedTileNums.end());\n if (dtype_act != btg::Dtype::Bfloat16) {\n tiles.push_back(128);\n tiles.push_back(256);\n }\n return tiles;\n }\n\n FP4BlockScaleLauncher(\n Optional<TensorView> const& routing_logits, Optional<TensorView> const& routing_bias,\n TensorView const& hidden_states, Optional<TensorView> const& hidden_states_scale,\n TensorView const& gemm1_weights, TensorView const& gemm1_weights_scale,\n Optional<TensorView> const& gemm1_bias, Optional<TensorView> const& gemm1_alpha,\n Optional<TensorView> const& gemm1_beta, Optional<TensorView> const& gemm1_clamp_limit,\n TensorView const& gemm2_weights, TensorView const& gemm2_weights_scale,\n Optional<TensorView> const& gemm2_bias, Optional<TensorView> const& output1_scales_scalar,\n Optional<TensorView> const& output1_scales_gate_scalar,\n Optional<TensorView> const& output2_scales_scalar, TensorView const& expert_indices,\n TensorView const& expert_weights)\n : FusedMoeLauncher(routing_logits, routing_bias, hidden_states, gemm1_weights,\n output1_scales_scalar, output1_scales_gate_scalar, gemm2_weights,\n output2_scales_scalar),\n hidden_states_scale(hidden_states_scale),\n gemm1_weights_scale(gemm1_weights_scale),\n gemm1_bias(gemm1_bias),\n gemm1_alpha(gemm1_alpha),\n gemm1_beta(gemm1_beta),\n gemm1_clamp_limit(gemm1_clamp_limit),\n gemm2_weights_scale(gemm2_weights_scale),\n gemm2_bias(gemm2_bias),\n expert_indices(expert_indices),\n expert_weights(expert_weights) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, ActivationType activation_type, btg::Dtype dtype_act,\n btg::Dtype dtype_weights) {\n // Set data types\n args->mDtypeElt = dtype_act;\n args->mDtypeOut = btg::Dtype::Bfloat16; // Output is always BF16 for FP4\n args->mUseDeepSeekFp8 = false; // FP4 doesn't use DeepSeek FP8\n\n mDtypeAct = dtype_act;\n mDtypeWeights = dtype_weights;\n\n FusedMoeLauncher::init_common(std::move(args), tile_tokens_dim, routing_method_type,\n use_shuffled_weight, weight_layout, activation_type);\n }\n\n void check_routing() const override {\n // First call base class common routing checks\n FusedMoeLauncher::check_routing_common();\n }\n\n void prepare_routing() override {\n num_tokens_per_expert = alloc_tensor({args->num_experts}, dl_int32, hidden_states.device());\n int32_t max_num_padded_tokens =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::getMaxPermutedPaddedCount(\n args->num_tokens, args->top_k, args->num_experts, tile_tokens_dim);\n\n total_num_padded_tokens = alloc_tensor({1}, dl_int32, hidden_states.device());\n expanded_idx_to_permuted_idx =\n alloc_tensor({args->num_tokens * args->top_k}, dl_int32, hidden_states.device());\n permuted_idx_to_token_idx =\n alloc_tensor({max_num_padded_tokens}, dl_int32, hidden_states.device());\n\n int64_t const size_of_expert_count_histogram = std::max(args->num_experts * 2, 256 * 2);\n expert_count_histogram =\n alloc_tensor({size_of_expert_count_histogram}, dl_int32, hidden_states.device());\n\n int32_t max_num_ctas = tensorrt_llm::kernels::trtllmgen_moe::Routing::getMaxNumCtasInBatchDim(\n args->num_tokens, args->top_k, args->num_experts, tile_tokens_dim);\n cta_idx_xy_to_batch_idx = alloc_tensor({max_num_ctas}, dl_int32, hidden_states.device());\n cta_idx_xy_to_mn_limit = alloc_tensor({max_num_ctas}, dl_int32, hidden_states.device());\n num_non_exiting_ctas = alloc_tensor({1}, dl_int32, hidden_states.device());\n\n workspace.total_num_padded_tokens = static_cast<int*>(total_num_padded_tokens.data_ptr());\n workspace.total_max_padded_tokens = max_num_padded_tokens;\n workspace.ProjUpTileN = tile_tokens_dim;\n workspace.routing_expert_indexes =\n static_cast<int*>(const_cast<void*>(expert_indices.data_ptr()));\n workspace.expert_weights = const_cast<void*>(expert_weights.data_ptr());\n workspace.permuted_idx_size = static_cast<int*>(total_num_padded_tokens.data_ptr());\n workspace.expanded_idx_to_permuted_idx =\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr());\n workspace.permuted_idx_to_token_idx = static_cast<int*>(permuted_idx_to_token_idx.data_ptr());\n workspace.cta_idx_xy_to_batch_idx = static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr());\n workspace.cta_idx_xy_to_mn_limit = static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr());\n workspace.num_non_exiting_ctas = static_cast<int*>(num_non_exiting_ctas.data_ptr());\n\n args->mDtypeElt = mDtypeAct;\n auto routing_bias_dtype = routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n }\n\n void check_moe() const override {\n TVM_FFI_ICHECK(mDtypeAct == btg::Dtype::E2m1 || mDtypeAct == btg::Dtype::Bfloat16 ||\n mDtypeAct == btg::Dtype::E4m3 || mDtypeAct == btg::Dtype::MxE4m3)\n << \"Only E2m1, Bfloat16, MxE4m3 and E4m3 are supported by Fp4 block scale MoE\";\n\n if (mDtypeAct == btg::Dtype::E2m1) {\n TVM_FFI_ICHECK(mDtypeWeights == btg::Dtype::E2m1)\n << \"Only E2m1 and MxE2m1 are supported by block scale MoE with E2m1 activation\";\n TVM_FFI_ICHECK(hidden_states_scale.has_value())\n << \"hidden_states_scale is required for E2m1 activation\";\n TVM_FFI_ICHECK(output1_scales_scalar.has_value())\n << \"output1_scales_scalar is required for E2m1 activation\";\n TVM_FFI_ICHECK(output1_scales_gate_scalar.has_value())\n << \"output1_scales_gate_scalar is required for E2m1 activation\";\n TVM_FFI_ICHECK(output2_scales_scalar.has_value())\n << \"output2_scales_scalar is required for E2m1 activation\";\n } else if (mDtypeAct == btg::Dtype::Bfloat16 || mDtypeAct == btg::Dtype::E4m3 ||\n mDtypeAct == btg::Dtype::MxE4m3) {\n TVM_FFI_ICHECK(mDtypeWeights == btg::Dtype::MxE2m1)\n << \"Only MxE2m1 weights are supported by block scale MoE with Bfloat16, E4m3 or \"\n \"MxE4m3 activation\";\n }\n\n if (mDtypeAct == btg::Dtype::E4m3) {\n TVM_FFI_ICHECK(output1_scales_scalar.has_value())\n << \"output1_scales_scalar is required for E4m3 activation\";\n TVM_FFI_ICHECK(output1_scales_gate_scalar.has_value())\n << \"output1_scales_gate_scalar is required for E4m3 activation\";\n TVM_FFI_ICHECK(output2_scales_scalar.has_value())\n << \"output2_scales_scalar is required for E4m3 activation\";\n }\n\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_uint8) << \"gemm1_weights must be byte.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_float8_e4m3fn)\n << \"gemm1_weights_scale must be fp8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_uint8) << \"gemm2_weights must be byte.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_float8_e4m3fn)\n << \"gemm2_weights_scale must be fp8.\";\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n args->hidden_states = hidden_states.data_ptr();\n args->hidden_states_scale =\n hidden_states_scale.has_value() ? hidden_states_scale.value().data_ptr() : nullptr;\n args->gemm1_weights = gemm1_weights.data_ptr();\n args->gemm1_weights_scale = gemm1_weights_scale.data_ptr();\n args->gemm1_bias =\n gemm1_bias.has_value() ? static_cast<float*>(gemm1_bias.value().data_ptr()) : nullptr;\n args->gemm1_alpha =\n gemm1_alpha.has_value() ? static_cast<float*>(gemm1_alpha.value().data_ptr()) : nullptr;\n args->gemm1_beta =\n gemm1_beta.has_value() ? static_cast<float*>(gemm1_beta.value().data_ptr()) : nullptr;\n args->gemm1_clamp_limit = gemm1_clamp_limit.has_value()\n ? static_cast<float*>(gemm1_clamp_limit.value().data_ptr())\n : nullptr;\n args->gemm2_weights = gemm2_weights.data_ptr();\n args->gemm2_weights_scale = gemm2_weights_scale.data_ptr();\n args->gemm2_bias =\n gemm2_bias.has_value() ? static_cast<float*>(gemm2_bias.value().data_ptr()) : nullptr;\n args->output1_scales_scalar =\n output1_scales_scalar.has_value()\n ? static_cast<float*>(output1_scales_scalar.value().data_ptr())\n : nullptr;\n args->output1_scales_gate_scalar =\n output1_scales_gate_scalar.has_value()\n ? static_cast<float*>(output1_scales_gate_scalar.value().data_ptr())\n : nullptr;\n args->output2_scales_scalar =\n output2_scales_scalar.has_value()\n ? static_cast<float*>(output2_scales_scalar.value().data_ptr())\n : nullptr;\n\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n auto const sf_vec_size = mDtypeWeights == btg::Dtype::MxE2m1 ? 32 : 16;\n\n max_num_padded_tokens_gemm1 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->intermediate_size,\n btg::dtypeGetNumBits(mDtypeAct));\n max_num_padded_tokens_gemm2 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->hidden_size,\n btg::dtypeGetNumBits(btg::Dtype::Bfloat16)); // Output is always BF16\n\n auto const gemm1_output_hidden =\n mDtypeAct == btg::Dtype::E2m1 ? args->intermediate_size / 2 : args->intermediate_size;\n gemm1_output = alloc_tensor({max_num_padded_tokens_gemm1, gemm1_output_hidden},\n mDtypeAct == btg::Dtype::Bfloat16 ? dl_bfloat16 : dl_uint8,\n hidden_states.device());\n\n if (mDtypeAct == btg::Dtype::E2m1 || mDtypeAct == btg::Dtype::MxE4m3) {\n int64_t sf_size = tensorrt_llm::computeSwizzledLayoutSFSize(\n max_num_padded_tokens_gemm1, args->intermediate_size / sf_vec_size);\n gemm1_output_scale = alloc_tensor({sf_size}, dl_uint8, hidden_states.device());\n }\n\n // Allocate gemm2_output\n gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n // Setup workspace pointers\n workspace.hidden_states_scale_linear = nullptr; // FP4 doesn't use linear scale\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = gemm1_output_scale.has_value()\n ? static_cast<float*>(gemm1_output_scale.value().data_ptr())\n : nullptr;\n // Note: activation_output and activation_output_scale are set by the base class\n // prepare_moe_common() when gated activation is used\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n }\n\n private:\n Optional<TensorView> hidden_states_scale;\n TensorView gemm1_weights_scale;\n Optional<TensorView> gemm1_bias;\n Optional<TensorView> gemm1_alpha;\n Optional<TensorView> gemm1_beta;\n Optional<TensorView> gemm1_clamp_limit;\n TensorView gemm2_weights_scale;\n Optional<TensorView> gemm2_bias;\n int32_t max_num_padded_tokens_gemm1{};\n int32_t max_num_padded_tokens_gemm2{};\n Optional<Tensor> gemm1_output_scale;\n TensorView expert_indices;\n TensorView expert_weights;\n\n public:\n Array<Tensor> run(int64_t moe_tactic, bool enable_pdl = true,\n bool use_routing_scales_on_input = false,\n bool use_deep_seek_fp8 = false) override {\n check_routing();\n prepare_routing();\n\n // Execute routing\n tensorrt_llm::kernels::trtllmgen_moe::Routing::Runner routing_runner(tile_tokens_dim);\n cudaStream_t routing_stream = get_stream(hidden_states.device());\n\n routing_runner.run(\n args->routing_logits, args->routing_bias, args->num_tokens, args->num_experts, args->top_k,\n args->n_group, args->topk_group, args->local_expert_offset, args->local_num_experts,\n args->routed_scaling_factor, static_cast<int*>(expert_indices.data_ptr()),\n static_cast<int*>(expert_count_histogram.data_ptr()),\n static_cast<int*>(total_num_padded_tokens.data_ptr()),\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr()),\n nullptr /*permuted_idx_to_expanded_idx.data_ptr()*/,\n static_cast<int*>(permuted_idx_to_token_idx.data_ptr()), expert_weights.data_ptr(),\n static_cast<int*>(num_tokens_per_expert.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr()),\n static_cast<int*>(num_non_exiting_ctas.data_ptr()), args->mDtypeElt, mRoutingBiasDtype,\n use_routing_scales_on_input, use_deep_seek_fp8,\n static_cast<RoutingMethodType>(routing_method_type), routing_stream);\n\n check_moe();\n prepare_moe(moe_tactic);\n\n cudaStream_t moe_stream = get_stream(hidden_states.device());\n moe_runner->run(*args, workspace, hidden_states.device().device_id, moe_stream, moe_tactic,\n enable_pdl);\n\n // Match original FP4 behavior for return values\n if (args->do_finalize) {\n return {output};\n }\n return {gemm2_output, FusedMoeLauncher::expert_weights, expanded_idx_to_permuted_idx};\n }\n\n static Array<Array<int64_t>> getValidConfigs(int64_t top_k, int64_t hidden_size,\n int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens, int64_t act_type,\n btg::Dtype dtype_act, btg::Dtype dtype_weights) {\n Array<Array<int64_t>> valid_configs;\n\n std::vector<int32_t> tile_sizes = getSupportedTileNums(dtype_act);\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(tile_sizes, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n auto moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n dtype_act, dtype_weights,\n false, // useDeepSeekFp8\n tile_N, static_cast<ActivationType>(act_type),\n /*useShuffledMatrix*/ true); // FP4 uses shuffled weights\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n};\n\nArray<Tensor> trtllm_bf16_moe(Optional<TensorView> const& routing_logits,\n Optional<TensorView> const& routing_bias,\n TensorView const& expert_indices, TensorView const& expert_weights,\n TensorView const& hidden_states, TensorView const& gemm1_weights,\n TensorView const& gemm2_weights, TensorView output,\n int64_t num_experts, int64_t top_k, Optional<int64_t> n_group,\n Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts,\n Optional<double> routed_scaling_factor, int64_t routing_method_type,\n bool use_shuffled_weight, int64_t weight_layout, bool do_finalize,\n bool enable_pdl, Array<int64_t> moe_tactic) {\n // Just some basic type validation first and leave more checks to the launcher\n if (routing_logits.has_value()) {\n TVM_FFI_ICHECK(routing_logits.value().dtype() == dl_float32 ||\n routing_logits.value().dtype() == dl_bfloat16)\n << \"BF16 MoE: routing_logits must be bfloat16 or float.\";\n }\n TVM_FFI_ICHECK_EQ(hidden_states.dtype(), dl_bfloat16)\n << \"BF16 MoE: hidden_states must be bfloat16.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_bfloat16)\n << \"BF16 MoE: gemm1_weights must be bfloat16.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_bfloat16)\n << \"BF16 MoE: gemm2_weights must be bfloat16.\";\n\n auto const num_tokens = hidden_states.size(0);\n auto const hidden_size = hidden_states.size(1);\n\n // Calculate supported tile sizes\n std::vector<int32_t> mSupportedTileN(Bf16MoeLauncher::mSupportedTileNums.begin(),\n Bf16MoeLauncher::mSupportedTileNums.end());\n // Build launchers for ALL supported tiles (not just the computeSelectedTileN subset)\n // so that autotuner-cached tactics always find their tile_N in the map.\n // Launcher creation is cheap (no GPU allocation until run()), so this is safe.\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<Bf16MoeLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : mSupportedTileN) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n args->hidden_size = hidden_size;\n args->hidden_size_output = args->hidden_size;\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<Bf16MoeLauncher>(routing_logits, routing_bias, expert_indices,\n expert_weights, hidden_states, gemm1_weights,\n gemm2_weights);\n launcher->init(std::move(args), curr_tile_N, routing_method_type, use_shuffled_weight,\n weight_layout);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n auto const [tile_N, config] =\n resolveMoeTileAndConfig(moe_tactic, mSupportedTileN, num_tokens, top_k, local_num_experts);\n\n // Get the launcher for the selected tile_N\n auto launcher_it = launchers_map.find(static_cast<int32_t>(tile_N));\n FLASHINFER_CHECK(launcher_it != launchers_map.end(),\n \"Internal error: missing BF16 MoE launcher for tile_N=\", tile_N);\n auto& selected_launcher = launcher_it->second;\n\n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl);\n}\n\nArray<Tensor> trtllm_fp8_per_tensor_scale_moe(\n TensorView routing_logits, Optional<TensorView> routing_bias, TensorView hidden_states,\n TensorView gemm1_weights, TensorView output1_scales_scalar,\n TensorView output1_scales_gate_scalar, TensorView gemm2_weights,\n TensorView output2_scales_scalar, TensorView output, int64_t num_experts, int64_t top_k,\n Optional<int64_t> n_group, Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts, Optional<double> routed_scaling_factor,\n bool use_routing_scales_on_input, int64_t routing_method_type, bool do_finalize,\n bool enable_pdl, Array<int64_t> config_index, int64_t activation_type) {\n // Basic type validation\n auto dtype = hidden_states.dtype();\n auto activation = static_cast<ActivationType>(activation_type);\n if (use_routing_scales_on_input) {\n TVM_FFI_ICHECK_EQ(routing_logits.dtype(), dl_bfloat16) << \"routing_logits must be bfloat16.\";\n } else if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK_EQ(routing_logits.dtype(), dl_float32) << \"routing_logits must be float.\";\n } else {\n TVM_FFI_ICHECK_EQ(routing_logits.dtype(), dl_bfloat16) << \"routing_logits must be bfloat16.\";\n }\n TVM_FFI_ICHECK(dtype == dl_float8_e4m3fn || dtype == dl_float16 || dtype == dl_bfloat16)\n << \"FP8 MoE: hidden_states must be float8_e4m3fn, float16, or bfloat16.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 MoE: gemm1_weights must be float8_e4m3fn.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 MoE: gemm2_weights must be float8_e4m3fn.\";\n TVM_FFI_ICHECK_EQ(output1_scales_scalar.dtype(), dl_float32)\n << \"FP8 MoE: output1_scales_scalar must be float32.\";\n TVM_FFI_ICHECK_EQ(output1_scales_gate_scalar.dtype(), dl_float32)\n << \"FP8 MoE: output1_scales_gate_scalar must be float32.\";\n TVM_FFI_ICHECK_EQ(output2_scales_scalar.dtype(), dl_float32)\n << \"FP8 MoE: output2_scales_scalar must be float32.\";\n\n auto const num_tokens = hidden_states.size(0);\n auto const hidden_size = hidden_states.size(1);\n\n // Use default values that match the original function behavior\n bool use_shuffled_weight = true; // Original uses /*useShuffledMatrix*/ true\n int64_t weight_layout = 0; // Default to MajorK\n\n // Calculate supported tile sizes\n std::vector<int32_t> mSupportedTileN(Fp8PerTensorLauncher::mSupportedTileNums.begin(),\n Fp8PerTensorLauncher::mSupportedTileNums.end());\n // Build launchers for ALL supported tiles so autotuner-cached tactics always find their tile_N.\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<Fp8PerTensorLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : mSupportedTileN) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n args->hidden_size = hidden_size;\n args->hidden_size_output = args->hidden_size;\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<Fp8PerTensorLauncher>(\n routing_logits, routing_bias, hidden_states, gemm1_weights, output1_scales_scalar,\n output1_scales_gate_scalar, gemm2_weights, output2_scales_scalar);\n launcher->init(std::move(args), curr_tile_N, routing_method_type, use_shuffled_weight,\n weight_layout, use_routing_scales_on_input, activation);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n auto const [tile_N, config] =\n resolveMoeTileAndConfig(config_index, mSupportedTileN, num_tokens, top_k, local_num_experts);\n\n // Get the launcher for the selected tile_N\n auto launcher_it = launchers_map.find(static_cast<int32_t>(tile_N));\n FLASHINFER_CHECK(launcher_it != launchers_map.end(),\n \"Internal error: missing FP8 per-tensor MoE launcher for tile_N=\", tile_N);\n auto& selected_launcher = launcher_it->second;\n\n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl, use_routing_scales_on_input);\n}\n\nArray<Tensor> trtllm_fp8_block_scale_moe(\n Optional<TensorView> routing_logits, TensorView expert_indices, TensorView expert_weights,\n Optional<TensorView> routing_bias, TensorView hidden_states, TensorView hidden_states_scale,\n TensorView gemm1_weights, TensorView gemm1_weights_scale, TensorView gemm2_weights,\n TensorView gemm2_weights_scale, TensorView output, int64_t num_experts, int64_t top_k,\n Optional<int64_t> n_group, Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts, Optional<double> routed_scaling_factor,\n int64_t routing_method_type, bool use_shuffled_weight, int64_t weight_layout, bool do_finalize,\n bool enable_pdl, Array<int64_t> config_index, Fp8QuantizationType quantization_type,\n int64_t act_type) {\n auto activation_type = validateAndCastActivationType(act_type);\n // DeepSeekFp8 currently uses a TRTLLM runner that hardwires Swiglu activation semantics.\n // Fail for any other activation to avoid silently running incorrect activation behavior.\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8 &&\n activation_type != ActivationType::Swiglu) {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"DeepSeekFp8 only supports ActivationType::Swiglu in this runner path. \"\n << \"Received activation_type=\" << static_cast<int>(activation_type);\n }\n\n // Basic type validation\n auto dtype = hidden_states.dtype();\n\n // Either routing_logits or expert_indices must be provided\n // expert_indices is a packed tensor: (expert_id << 16) | (weight_bf16.view(int16))\n bool use_routing_logits = routing_logits.has_value();\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool use_precomputed_routing = expert_indices.ndim() == 2 && expert_indices.size(0) > 0;\n\n TVM_FFI_ICHECK(use_routing_logits || use_precomputed_routing)\n << \"Either routing_logits or expert_indices must be provided.\";\n\n if (use_routing_logits) {\n if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK_EQ(routing_logits.value().dtype(), dl_float32)\n << \"routing_logits must be float.\";\n } else {\n TVM_FFI_ICHECK_EQ(routing_logits.value().dtype(), dl_bfloat16)\n << \"routing_logits must be bfloat16.\";\n }\n }\n TVM_FFI_ICHECK(dtype == dl_float16 || dtype == dl_bfloat16 || dtype == dl_float8_e4m3fn)\n << \"FP8 block scale MoE: hidden_states must be fp16, bf16, or fp8.\";\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(hidden_states_scale.dtype(), dl_float32)\n << \"FP8 block scale MoE: hidden_states_scale must be float32.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK_EQ(hidden_states_scale.dtype(), dl_uint8)\n << \"FP8 block scale MoE: hidden_states_scale must be uint8.\";\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 block scale MoE: gemm1_weights must be fp8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 block scale MoE: gemm2_weights must be fp8.\";\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_float32)\n << \"FP8 block scale MoE: gemm1_weights_scale must be float32.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_float32)\n << \"FP8 block scale MoE: gemm2_weights_scale must be float32.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_uint8)\n << \"FP8 block scale MoE: gemm1_weights_scale must be uint8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_uint8)\n << \"FP8 block scale MoE: gemm2_weights_scale must be uint8.\";\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n\n if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK(use_shuffled_weight) << \"use_shuffled_weight must be true for MxFp8.\";\n TVM_FFI_ICHECK(weight_layout == 0) << \"weight_layout must be 0 for MxFp8.\";\n }\n\n auto const num_tokens = hidden_states.size(0);\n auto const hidden_size = hidden_states.size(1);\n\n auto supported_tile_nums = Fp8BlockScaleLauncher::getSupportedTileNums(quantization_type);\n // Build launchers for ALL supported tiles so autotuner-cached tactics always find their tile_N.\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<Fp8BlockScaleLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : supported_tile_nums) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n args->hidden_size = hidden_size;\n args->hidden_size_output = args->hidden_size;\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<Fp8BlockScaleLauncher>(\n routing_logits, routing_bias, hidden_states, hidden_states_scale, gemm1_weights,\n gemm1_weights_scale, gemm2_weights, gemm2_weights_scale, expert_indices, expert_weights,\n quantization_type);\n launcher->init(std::move(args), curr_tile_N, routing_method_type, use_shuffled_weight,\n weight_layout, activation_type);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n auto const [tile_N, config] = resolveMoeTileAndConfig(config_index, supported_tile_nums,\n num_tokens, top_k, local_num_experts);\n\n // Get the launcher for the selected tile_N\n auto launcher_it = launchers_map.find(static_cast<int32_t>(tile_N));\n FLASHINFER_CHECK(launcher_it != launchers_map.end(),\n \"Internal error: missing FP8 block-scale MoE launcher for tile_N=\", tile_N);\n auto& selected_launcher = launcher_it->second;\n\n // Run the launcher with DeepSeek FP8 enabled - it will create its own runner internally\n return selected_launcher->run(\n config, enable_pdl, false /* use_routing_scales_on_input */,\n quantization_type == Fp8QuantizationType::DeepSeekFp8 /* use_deep_seek_fp8 */);\n}\n\nArray<Tensor> trtllm_fp4_block_scale_moe(\n Optional<TensorView> routing_logits, TensorView expert_indices, TensorView expert_weights,\n Optional<TensorView> routing_bias, TensorView hidden_states,\n Optional<TensorView> hidden_states_scale, TensorView gemm1_weights,\n TensorView gemm1_weights_scale, Optional<TensorView> gemm1_bias,\n Optional<TensorView> gemm1_alpha, Optional<TensorView> gemm1_beta,\n Optional<TensorView> gemm1_clamp_limit, TensorView gemm2_weights,\n TensorView gemm2_weights_scale, Optional<TensorView> gemm2_bias,\n Optional<TensorView> output1_scales_scalar, Optional<TensorView> output1_scales_gate_scalar,\n Optional<TensorView> output2_scales_scalar, int64_t num_experts, int64_t top_k,\n Optional<int64_t> n_group, Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts, Optional<double> routed_scaling_factor,\n int64_t routing_method_type, bool do_finalize, bool enable_pdl, int64_t act_type,\n TensorView output, Array<int64_t> config_index) {\n // Determine data types based on input format\n int const num_tokens = hidden_states.size(0);\n int hidden_size = hidden_states.size(1);\n if (hidden_states.dtype() == dl_uint8) hidden_size *= 2;\n\n int hidden_states_scale_vec_size = -1;\n if (hidden_states_scale.has_value()) {\n hidden_states_scale_vec_size = (num_tokens * hidden_size) / hidden_states_scale.value().numel();\n }\n int64_t intermediate_size_factor =\n isGatedActivation(static_cast<ActivationType>(act_type)) ? 2 : 1;\n int weight_scale_vec_size =\n (local_num_experts * intermediate_size * intermediate_size_factor * hidden_size) /\n gemm1_weights_scale.numel();\n\n TVM_FFI_ICHECK(weight_scale_vec_size == 16 || weight_scale_vec_size == 32)\n << \"unsupported weight_scale_vec_size.\";\n auto mDtypeWeights = weight_scale_vec_size == 16 ? btg::Dtype::E2m1 : btg::Dtype::MxE2m1;\n\n if (routing_logits.has_value()) {\n TVM_FFI_ICHECK(routing_logits.value().dtype() == dl_float32 ||\n routing_logits.value().dtype() == dl_bfloat16)\n << \"routing_logits must be float or bfloat16.\";\n TVM_FFI_ICHECK_EQ(routing_logits.value().ndim(), 2) << \"routing_logits must be 2D.\";\n TVM_FFI_ICHECK_EQ(routing_logits.value().size(1), num_experts)\n << \"routing_logits has incorrect shape.\";\n if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK_EQ(routing_logits.value().dtype(), dl_float32)\n << \"routing_logits must be float.\";\n }\n }\n if (routing_bias.has_value()) {\n TVM_FFI_ICHECK(routing_bias.value().dtype() == dl_bfloat16 ||\n routing_bias.value().dtype() == dl_float32)\n << \"routing_bias must be bfloat16 or float.\";\n\n TVM_FFI_ICHECK_EQ(routing_bias.value().ndim(), 1) << \"routing_bias must be 1D.\";\n TVM_FFI_ICHECK_EQ(routing_bias.value().size(0), num_experts)\n << \"routing_bias has incorrect shape.\";\n }\n\n // Determine activation type\n TVM_FFI_ICHECK(gemm1_weights.dtype() == dl_uint8 && gemm2_weights.dtype() == dl_uint8)\n << \"weights must be fp4 packed in uint8.\";\n TVM_FFI_ICHECK(hidden_states.dtype() == dl_uint8 || hidden_states.dtype() == dl_bfloat16 ||\n hidden_states.dtype() == dl_float8_e4m3fn)\n << \"hidden_states must be bf16, fp8 or uint8 (packed fp4).\";\n\n auto mDtypeAct = btg::Dtype::Bfloat16;\n if (hidden_states.dtype() == dl_uint8) {\n TVM_FFI_ICHECK(hidden_states_scale.has_value() &&\n hidden_states_scale.value().dtype() == dl_float8_e4m3fn)\n << \"hidden_states_scale must be provided for fp4 activation.\";\n if (hidden_states_scale_vec_size == 16) {\n mDtypeAct = btg::Dtype::E2m1;\n } else if (hidden_states_scale_vec_size == 32) {\n mDtypeAct = btg::Dtype::MxE2m1;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported hidden state scale shape.\";\n }\n } else if (hidden_states.dtype() == dl_float8_e4m3fn) {\n if (hidden_states_scale.has_value()) {\n if (hidden_states_scale_vec_size == 32) {\n mDtypeAct = btg::Dtype::MxE4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported hidden state scale shape.\";\n }\n } else {\n mDtypeAct = btg::Dtype::E4m3;\n }\n }\n\n // Determine supported tile sizes\n std::vector<int32_t> mSupportedTileN = FP4BlockScaleLauncher::getSupportedTileNums(mDtypeAct);\n // Build launchers for ALL supported tiles so autotuner-cached tactics always find their tile_N.\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<FP4BlockScaleLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : mSupportedTileN) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n // For E2m1, hidden_size is already multiplied by 2 above, so use it directly\n args->hidden_size = hidden_size;\n args->hidden_size_output = output.size(1);\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<FP4BlockScaleLauncher>(\n routing_logits, routing_bias, hidden_states, hidden_states_scale, gemm1_weights,\n gemm1_weights_scale, gemm1_bias, gemm1_alpha, gemm1_beta, gemm1_clamp_limit, gemm2_weights,\n gemm2_weights_scale, gemm2_bias, output1_scales_scalar, output1_scales_gate_scalar,\n output2_scales_scalar, expert_indices, expert_weights);\n launcher->init(std::move(args), curr_tile_N, routing_method_type, /*use_shuffled_weight=*/true,\n /*weight_layout=*/0, static_cast<ActivationType>(act_type), mDtypeAct,\n mDtypeWeights);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n auto const [tile_N, config] =\n resolveMoeTileAndConfig(config_index, mSupportedTileN, num_tokens, top_k, local_num_experts);\n\n // Get the launcher for the selected tile_N\n auto launcher_it = launchers_map.find(static_cast<int32_t>(tile_N));\n FLASHINFER_CHECK(launcher_it != launchers_map.end(),\n \"Internal error: missing FP4 block-scale MoE launcher for tile_N=\", tile_N);\n auto& selected_launcher = launcher_it->second;\n\n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl);\n}\n\nArray<Tensor> trtllm_mxint4_block_scale_moe(\n TensorView routing_logits, Optional<TensorView> routing_bias, TensorView hidden_states,\n TensorView gemm1_weights, TensorView gemm1_weights_scale, Optional<TensorView> gemm1_alpha,\n Optional<TensorView> gemm1_beta, Optional<TensorView> gemm1_clamp_limit,\n TensorView gemm2_weights, TensorView gemm2_weights_scale, int64_t num_experts, int64_t top_k,\n Optional<int64_t> n_group, Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts, Optional<double> routed_scaling_factor,\n int64_t routing_method_type, bool do_finalize, bool enable_pdl, TensorView output,\n Array<int64_t> config_index) {\n // Determine data types based on input format\n int const num_tokens = hidden_states.size(0);\n int hidden_size = hidden_states.size(1);\n // Just some basic type validation first and leave more checks to the launcher\n\n int weight_scale_vec_size =\n (local_num_experts * intermediate_size * 2 * hidden_size) / gemm1_weights_scale.numel();\n\n TVM_FFI_ICHECK(weight_scale_vec_size == 32) << \"unsupported weight_scale_vec_size.\";\n\n TVM_FFI_ICHECK(routing_logits.dtype() == dl_float32 || routing_logits.dtype() == dl_bfloat16)\n << \"routing_logits must be float or bfloat16.\";\n TVM_FFI_ICHECK_EQ(routing_logits.ndim(), 2) << \"routing_logits must be 2D.\";\n TVM_FFI_ICHECK_EQ(routing_logits.size(1), num_experts) << \"routing_logits has incorrect shape.\";\n if (routing_bias.has_value()) {\n TVM_FFI_ICHECK(routing_bias.value().dtype() == dl_bfloat16) << \"routing_bias must be bfloat16.\";\n TVM_FFI_ICHECK_EQ(routing_bias.value().ndim(), 1) << \"routing_bias must be 1D.\";\n TVM_FFI_ICHECK_EQ(routing_bias.value().size(0), num_experts)\n << \"routing_bias has incorrect shape.\";\n }\n\n // Determine activation type\n TVM_FFI_ICHECK(gemm1_weights.dtype() == dl_uint8 && gemm2_weights.dtype() == dl_uint8)\n << \"weights must be int4 packed in uint8.\";\n TVM_FFI_ICHECK(hidden_states.dtype() == dl_bfloat16) << \"hidden_states must be bf16.\";\n\n // Determine supported tile sizes\n std::vector<int32_t> mSupportedTileN(MxInt4BlockScaleLauncher::mSupportedTileNums.begin(),\n MxInt4BlockScaleLauncher::mSupportedTileNums.end());\n // Build launchers for ALL supported tiles so autotuner-cached tactics always find their tile_N.\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<MxInt4BlockScaleLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : mSupportedTileN) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n // For E2m1, hidden_size is already multiplied by 2 above, so use it directly\n args->hidden_size = hidden_size;\n args->hidden_size_output = args->hidden_size;\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<MxInt4BlockScaleLauncher>(\n routing_logits, routing_bias, hidden_states, gemm1_weights, gemm1_weights_scale,\n gemm1_alpha, gemm1_beta, gemm1_clamp_limit, gemm2_weights, gemm2_weights_scale);\n launcher->init(std::move(args), curr_tile_N, routing_method_type);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n auto const [tile_N, config] =\n resolveMoeTileAndConfig(config_index, mSupportedTileN, num_tokens, top_k, local_num_experts);\n\n // Get the launcher for the selected tile_N\n auto launcher_it = launchers_map.find(static_cast<int32_t>(tile_N));\n FLASHINFER_CHECK(launcher_it != launchers_map.end(),\n \"Internal error: missing MXINT4 block-scale MoE launcher for tile_N=\", tile_N);\n auto& selected_launcher = launcher_it->second;\n\n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl);\n}\n\nArray<Array<int64_t>> trtllm_get_valid_moe_configs(\n int64_t const dtype_act_, int64_t const dtype_weights_, Fp8QuantizationType quantization_type,\n int64_t const top_k, int64_t const hidden_size, int64_t const intermediate_size,\n int64_t const num_local_experts, int64_t const act_type, bool const use_shuffled_weight,\n int64_t const weight_layout, int64_t const num_tokens) {\n auto activation_type = validateAndCastActivationType(act_type);\n auto dtype_act = static_cast<btg::Dtype>(dtype_act_);\n auto dtype_weights = static_cast<btg::Dtype>(dtype_weights_);\n\n if (dtype_act == btg::Dtype::Bfloat16 && dtype_weights == btg::Dtype::MxInt4) {\n // MxInt4 MoE\n return MxInt4BlockScaleLauncher::getValidConfigs(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n }\n if (dtype_act == btg::Dtype::Bfloat16 && dtype_weights == btg::Dtype::Bfloat16) {\n // BF16 MoE\n return Bf16MoeLauncher::getValidConfigs(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens, act_type,\n use_shuffled_weight, weight_layout);\n\n } else if (quantization_type == Fp8QuantizationType::DeepSeekFp8 &&\n dtype_act == btg::Dtype::E4m3 && dtype_weights == btg::Dtype::E4m3) {\n if (activation_type != ActivationType::Swiglu) {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"DeepSeekFp8 only supports ActivationType::Swiglu, \"\n << \"got act_type=\" << act_type << \".\";\n }\n // FP8 block scale (DeepSeek)\n return Fp8BlockScaleLauncher::getValidConfigs(\n top_k, hidden_size, intermediate_size, num_local_experts, num_tokens, use_shuffled_weight,\n weight_layout, dtype_act, dtype_weights, quantization_type, act_type);\n } else if (quantization_type == Fp8QuantizationType::MxFp8 && dtype_act == btg::Dtype::MxE4m3 &&\n dtype_weights == btg::Dtype::MxE4m3) {\n // FP8 block scale (MxFp8)\n return Fp8BlockScaleLauncher::getValidConfigs(\n top_k, hidden_size, intermediate_size, num_local_experts, num_tokens, use_shuffled_weight,\n weight_layout, dtype_act, dtype_weights, quantization_type, act_type);\n } else if ((quantization_type == Fp8QuantizationType::PerTensorFp8 ||\n quantization_type == Fp8QuantizationType::NoneFp8) &&\n dtype_weights == btg::Dtype::E4m3) {\n // FP8 per-tensor scale. NoneFp8 is kept for backward compatibility.\n if (!isGatedActivation(activation_type)) {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"FP8 per-tensor currently supports gated activations only, \"\n << \"got act_type=\" << act_type << \".\";\n }\n return Fp8PerTensorLauncher::getValidConfigs(\n top_k, hidden_size, intermediate_size, num_local_experts, num_tokens, act_type,\n use_shuffled_weight, weight_layout, dtype_act, dtype_weights);\n } else if (dtype_weights == btg::Dtype::E2m1 || dtype_weights == btg::Dtype::MxE2m1) {\n // FP4 block scale\n return FP4BlockScaleLauncher::getValidConfigs(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens, act_type,\n dtype_act, dtype_weights);\n }\n\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"Unsupported data type combination for getValidConfigs: \"\n << \"dtype_act=\" << static_cast<int>(dtype_act)\n << \", dtype_weights=\" << static_cast<int>(dtype_weights)\n << \", quantization_type=\" << fp8QuantizationTypeToString(quantization_type);\n\n // Unreachable code - added to suppress compiler warning\n return Array<Array<int64_t>>();\n}\n\nnamespace trtllm_cubin_loader {\n#include <flashinfer/cubin_loader.h>\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_bf16_moe, trtllm_bf16_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_fp8_per_tensor_scale_moe, trtllm_fp8_per_tensor_scale_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_fp8_block_scale_moe, trtllm_fp8_block_scale_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_fp4_block_scale_moe, trtllm_fp4_block_scale_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_mxint4_block_scale_moe, trtllm_mxint4_block_scale_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_get_valid_moe_configs, trtllm_get_valid_moe_configs);\n\n} // namespace flashinfer\n"},"diff":{"kind":"string","value":"--- csrc/trtllm_fused_moe_kernel_launcher.cu\n+++ csrc/trtllm_fused_moe_kernel_launcher.cu\n@@ -91,12 +91,26 @@\n std::set<int32_t> computeSelectedTileN(std::vector<int32_t> const& supported_tile_nums,\n int64_t const num_tokens, int64_t const top_k,\n int64_t const num_local_experts) {\n+ TVM_FFI_ICHECK(!supported_tile_nums.empty()) << \"supported_tile_nums must not be empty.\";\n float const avg_tokens_per_expert = static_cast<float>(num_tokens * top_k) / num_local_experts;\n+ // NOTE: This differs from Python AutoTuner bucketing:\n+ // - AutoTuner maps raw num_tokens with last_positive_power_of_2 (round-down).\n+ // - Here we map derived avg_tokens_per_expert and use nextPowerOfTwo (round-up).\n+ // Because they round different quantities in different directions, cache bucket and runtime\n+ // tile candidates can diverge; launcher-side tactic resolution handles that mismatch.\n // assume supported_tile_nums is sorted\n int32_t tile_tokens_dim = std::clamp(nextPowerOfTwo(avg_tokens_per_expert),\n supported_tile_nums.front(), supported_tile_nums.back());\n auto it = std::find(supported_tile_nums.begin(), supported_tile_nums.end(), tile_tokens_dim);\n-\n+ FLASHINFER_CHECK(\n+ it != supported_tile_nums.end(), \"computeSelectedTileN expected exact tile \", tile_tokens_dim,\n+ \" in supported_tile_nums (size=\", supported_tile_nums.size(),\n+ \"). Please keep supported_tile_nums as a dense power-of-2 ladder for this launcher.\");\n+\n+ // Candidate tile set centered on the heuristic tile.\n+ // This function returns nearby candidates (not a single final tile):\n+ // center, +1, +2, and -1 neighbors when available.\n+ // Final tile choice is made later (autotuner-provided tile if valid, otherwise fallback policy).\n std::set<int32_t> selected_tile_nums;\n selected_tile_nums.insert(tile_tokens_dim);\n if (std::next(it) != supported_tile_nums.end()) {\n@@ -110,6 +124,37 @@\n }\n \n return selected_tile_nums;\n+}\n+\n+int64_t selectDefaultTileN(std::vector<int32_t> const& supported_tile_nums,\n+ int64_t const num_tokens, int64_t const top_k,\n+ int64_t const num_local_experts) {\n+ auto selected = computeSelectedTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n+ TVM_FFI_ICHECK(!selected.empty()) << \"No selected tile_N candidates for current MoE input.\";\n+ return *selected.begin();\n+}\n+\n+// Resolve the (tile_N, config) pair passed from Python side, applying fallback logic\n+// when tile_N is -1.\n+std::pair<int64_t, int64_t> resolveMoeTileAndConfig(Array<int64_t> const& config_index,\n+ std::vector<int32_t> const& supported_tile_nums,\n+ int64_t const num_tokens, int64_t const top_k,\n+ int64_t const num_local_experts) {\n+ // Python side convention: tactic is [tile_N, config]\n+ TVM_FFI_ICHECK(config_index.size() == 2)\n+ << \"Invalid tactic, expected to be [tile_N, config], but got array of size \"\n+ << config_index.size();\n+ const int64_t tile_N = config_index[0];\n+ const int64_t config = config_index[1];\n+\n+ if (tile_N == -1 || config == -1) {\n+ // Use fallback tactic\n+ auto const default_tile_N =\n+ selectDefaultTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n+ return {default_tile_N, -1};\n+ }\n+\n+ return {tile_N, config};\n }\n \n class FusedMoeLauncher {\n@@ -1656,13 +1701,14 @@\n // Calculate supported tile sizes\n std::vector<int32_t> mSupportedTileN(Bf16MoeLauncher::mSupportedTileNums.begin(),\n Bf16MoeLauncher::mSupportedTileNums.end());\n- std::set<int32_t> selected_tile_nums =\n- computeSelectedTileN(mSupportedTileN, num_tokens, top_k, local_num_experts);\n+ // Build launchers for ALL supported tiles (not just the computeSelectedTileN subset)\n+ // so that autotuner-cached tactics always find their tile_N in the map.\n+ // Launcher creation is cheap (no GPU allocation until run()), so this is safe.\n \n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<Bf16MoeLauncher>> launchers_map;\n \n- for (int32_t curr_tile_N : selected_tile_nums) {\n+ for (int32_t curr_tile_N : mSupportedTileN) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n@@ -1690,17 +1736,14 @@\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n \n- // Extract tile_N and config from moe_tactic\n- int64_t tile_N = moe_tactic[0];\n- int64_t config = moe_tactic[1];\n-\n- // Handle default case\n- if (tile_N == -1 || config == -1) {\n- tile_N = *selected_tile_nums.begin();\n- }\n+ auto const [tile_N, config] =\n+ resolveMoeTileAndConfig(moe_tactic, mSupportedTileN, num_tokens, top_k, local_num_experts);\n \n // Get the launcher for the selected tile_N\n- auto& selected_launcher = launchers_map.at(tile_N);\n+ auto launcher_it = launchers_map.find(static_cast<int32_t>(tile_N));\n+ FLASHINFER_CHECK(launcher_it != launchers_map.end(),\n+ \"Internal error: missing BF16 MoE launcher for tile_N=\", tile_N);\n+ auto& selected_launcher = launcher_it->second;\n \n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl);\n@@ -1748,13 +1791,12 @@\n // Calculate supported tile sizes\n std::vector<int32_t> mSupportedTileN(Fp8PerTensorLauncher::mSupportedTileNums.begin(),\n Fp8PerTensorLauncher::mSupportedTileNums.end());\n- std::set<int32_t> selected_tile_nums =\n- computeSelectedTileN(mSupportedTileN, num_tokens, top_k, local_num_experts);\n+ // Build launchers for ALL supported tiles so autotuner-cached tactics always find their tile_N.\n \n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<Fp8PerTensorLauncher>> launchers_map;\n \n- for (int32_t curr_tile_N : selected_tile_nums) {\n+ for (int32_t curr_tile_N : mSupportedTileN) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n@@ -1782,17 +1824,14 @@\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n \n- // Extract tile_N and config from config_index\n- int64_t tile_N = config_index[0];\n- int64_t config = config_index[1];\n-\n- // Handle default case\n- if (tile_N == -1 || config == -1) {\n- tile_N = *selected_tile_nums.begin();\n- }\n+ auto const [tile_N, config] =\n+ resolveMoeTileAndConfig(config_index, mSupportedTileN, num_tokens, top_k, local_num_experts);\n \n // Get the launcher for the selected tile_N\n- auto& selected_launcher = launchers_map.at(tile_N);\n+ auto launcher_it = launchers_map.find(static_cast<int32_t>(tile_N));\n+ FLASHINFER_CHECK(launcher_it != launchers_map.end(),\n+ \"Internal error: missing FP8 per-tensor MoE launcher for tile_N=\", tile_N);\n+ auto& selected_launcher = launcher_it->second;\n \n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl, use_routing_scales_on_input);\n@@ -1879,13 +1918,12 @@\n auto const hidden_size = hidden_states.size(1);\n \n auto supported_tile_nums = Fp8BlockScaleLauncher::getSupportedTileNums(quantization_type);\n- std::set<int32_t> selected_tile_nums =\n- computeSelectedTileN(supported_tile_nums, num_tokens, top_k, local_num_experts);\n+ // Build launchers for ALL supported tiles so autotuner-cached tactics always find their tile_N.\n \n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<Fp8BlockScaleLauncher>> launchers_map;\n \n- for (int32_t curr_tile_N : selected_tile_nums) {\n+ for (int32_t curr_tile_N : supported_tile_nums) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n@@ -1914,17 +1952,14 @@\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n \n- // Extract tile_N and config from config_index\n- int64_t tile_N = config_index[0];\n- int64_t config = config_index[1];\n-\n- // Handle default case\n- if (tile_N == -1 || config == -1) {\n- tile_N = *selected_tile_nums.begin();\n- }\n+ auto const [tile_N, config] = resolveMoeTileAndConfig(config_index, supported_tile_nums,\n+ num_tokens, top_k, local_num_experts);\n \n // Get the launcher for the selected tile_N\n- auto& selected_launcher = launchers_map.at(tile_N);\n+ auto launcher_it = launchers_map.find(static_cast<int32_t>(tile_N));\n+ FLASHINFER_CHECK(launcher_it != launchers_map.end(),\n+ \"Internal error: missing FP8 block-scale MoE launcher for tile_N=\", tile_N);\n+ auto& selected_launcher = launcher_it->second;\n \n // Run the launcher with DeepSeek FP8 enabled - it will create its own runner internally\n return selected_launcher->run(\n@@ -2020,13 +2055,12 @@\n \n // Determine supported tile sizes\n std::vector<int32_t> mSupportedTileN = FP4BlockScaleLauncher::getSupportedTileNums(mDtypeAct);\n- std::set<int32_t> selected_tile_nums =\n- computeSelectedTileN(mSupportedTileN, num_tokens, top_k, local_num_experts);\n+ // Build launchers for ALL supported tiles so autotuner-cached tactics always find their tile_N.\n \n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<FP4BlockScaleLauncher>> launchers_map;\n \n- for (int32_t curr_tile_N : selected_tile_nums) {\n+ for (int32_t curr_tile_N : mSupportedTileN) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n@@ -2058,18 +2092,14 @@\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n \n- // Extract tile_N and config from config_index\n- int64_t tile_N = config_index[0];\n- int64_t config = config_index[1];\n-\n- // Handle default case\n- if (tile_N == -1 || config == -1) {\n- tile_N = *selected_tile_nums.begin();\n- config = -1; // Let the runner choose default\n- }\n+ auto const [tile_N, config] =\n+ resolveMoeTileAndConfig(config_index, mSupportedTileN, num_tokens, top_k, local_num_experts);\n \n // Get the launcher for the selected tile_N\n- auto& selected_launcher = launchers_map.at(tile_N);\n+ auto launcher_it = launchers_map.find(static_cast<int32_t>(tile_N));\n+ FLASHINFER_CHECK(launcher_it != launchers_map.end(),\n+ \"Internal error: missing FP4 block-scale MoE launcher for tile_N=\", tile_N);\n+ auto& selected_launcher = launcher_it->second;\n \n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl);\n@@ -2113,13 +2143,12 @@\n // Determine supported tile sizes\n std::vector<int32_t> mSupportedTileN(MxInt4BlockScaleLauncher::mSupportedTileNums.begin(),\n MxInt4BlockScaleLauncher::mSupportedTileNums.end());\n- std::set<int32_t> selected_tile_nums =\n- computeSelectedTileN(mSupportedTileN, num_tokens, top_k, local_num_experts);\n+ // Build launchers for ALL supported tiles so autotuner-cached tactics always find their tile_N.\n \n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<MxInt4BlockScaleLauncher>> launchers_map;\n \n- for (int32_t curr_tile_N : selected_tile_nums) {\n+ for (int32_t curr_tile_N : mSupportedTileN) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n@@ -2147,18 +2176,14 @@\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n \n- // Extract tile_N and config from config_index\n- int64_t tile_N = config_index[0];\n- int64_t config = config_index[1];\n-\n- // Handle default case\n- if (tile_N == -1 || config == -1) {\n- tile_N = *selected_tile_nums.begin();\n- config = -1; // Let the runner choose default\n- }\n+ auto const [tile_N, config] =\n+ resolveMoeTileAndConfig(config_index, mSupportedTileN, num_tokens, top_k, local_num_experts);\n \n // Get the launcher for the selected tile_N\n- auto& selected_launcher = launchers_map.at(tile_N);\n+ auto launcher_it = launchers_map.find(static_cast<int32_t>(tile_N));\n+ FLASHINFER_CHECK(launcher_it != launchers_map.end(),\n+ \"Internal error: missing MXINT4 block-scale MoE launcher for tile_N=\", tile_N);\n+ auto& selected_launcher = launcher_it->second;\n \n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl);"},"lines_added":{"kind":"number","value":88,"string":"88"},"lines_removed":{"kind":"number","value":63,"string":"63"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":["nemotron"],"string":"[\n \"nemotron\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["SM100"],"string":"[\n \"SM100\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/trtllm_fused_moe_kernel_launcher.cu).\n\nGoal: fix: Autotuner _find_nearest_profile non-power-of-2 num_tokens, create launchers for all supported tileN in trtllm fused MoE\nTarget hardware: SM100\nTarget models: nemotron\n\nCurrent file:\n```cuda\n/*\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <cuda_runtime.h>\n#include <flashinfer/exception.h>\n#include <nvrtc.h>\n\n#include <algorithm>\n#include <cmath>\n#include <cstring>\n#include <iomanip>\n#include <iostream>\n#include <set>\n#include <unordered_map>\n#include <vector>\n\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/GemmGatedActOptions.h\"\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/trtllm/gen/DtypeDecl.h\"\n#include \"flashinfer/trtllm/fused_moe/DevKernel.h\"\n#include \"flashinfer/trtllm/fused_moe/RoutingKernel.h\"\n#include \"flashinfer/trtllm/fused_moe/runner.h\"\n#include \"nv_internal/tensorrt_llm/kernels/quantization.h\"\n#include \"nv_internal/tensorrt_llm/thop/utils.h\"\n#include \"tvm_ffi_utils.h\"\n\nnamespace flashinfer {\n\nnamespace btg = batchedGemm::trtllm::gen;\nusing tensorrt_llm::kernels::trtllmgen_moe::MoE::ActivationType;\nusing tensorrt_llm::kernels::trtllmgen_moe::Routing::RoutingMethodType;\nusing tvm::ffi::Array;\nusing tvm::ffi::Optional;\n\nenum class Fp8QuantizationType {\n NoneFp8,\n DeepSeekFp8,\n MxFp8,\n PerTensorFp8,\n};\n\ninline std::string fp8QuantizationTypeToString(Fp8QuantizationType quantization_type) {\n switch (quantization_type) {\n default:\n case Fp8QuantizationType::NoneFp8:\n return \"NoneFp8\";\n case Fp8QuantizationType::DeepSeekFp8:\n return \"DeepSeekFp8\";\n case Fp8QuantizationType::MxFp8:\n return \"MxFp8\";\n case Fp8QuantizationType::PerTensorFp8:\n return \"PerTensorFp8\";\n }\n}\n\ninline ActivationType validateAndCastActivationType(int64_t act_type) {\n TVM_FFI_ICHECK(act_type >= 0 && act_type < static_cast<int64_t>(ActivationType::InvalidType))\n << \"Invalid activation type: \" << act_type;\n return static_cast<ActivationType>(act_type);\n}\n\n// Utility function to compute the next power of two\ninline int32_t nextPowerOfTwo(float value) {\n int32_t n = static_cast<int32_t>(std::ceil(value));\n if (n <= 1) return 1;\n\n // If n is already a power of 2, return it\n if ((n & (n - 1)) == 0) return n;\n\n // Find the next power of 2\n n--;\n n |= n >> 1;\n n |= n >> 2;\n n |= n >> 4;\n n |= n >> 8;\n n |= n >> 16;\n n++;\n\n return n;\n}\n\nstd::set<int32_t> computeSelectedTileN(std::vector<int32_t> const& supported_tile_nums,\n int64_t const num_tokens, int64_t const top_k,\n int64_t const num_local_experts) {\n float const avg_tokens_per_expert = static_cast<float>(num_tokens * top_k) / num_local_experts;\n // assume supported_tile_nums is sorted\n int32_t tile_tokens_dim = std::clamp(nextPowerOfTwo(avg_tokens_per_expert),\n supported_tile_nums.front(), supported_tile_nums.back());\n auto it = std::find(supported_tile_nums.begin(), supported_tile_nums.end(), tile_tokens_dim);\n\n std::set<int32_t> selected_tile_nums;\n selected_tile_nums.insert(tile_tokens_dim);\n if (std::next(it) != supported_tile_nums.end()) {\n selected_tile_nums.insert(*std::next(it));\n if (std::next(std::next(it)) != supported_tile_nums.end()) {\n selected_tile_nums.insert(*std::next(std::next(it)));\n }\n }\n if (it != supported_tile_nums.begin()) {\n selected_tile_nums.insert(*std::prev(it));\n }\n\n return selected_tile_nums;\n}\n\nclass FusedMoeLauncher {\n protected:\n Optional<TensorView> routing_logits;\n Optional<TensorView> routing_bias;\n TensorView hidden_states;\n TensorView gemm1_weights;\n Optional<TensorView> output1_scales_scalar;\n Optional<TensorView> output1_scales_gate_scalar;\n TensorView gemm2_weights;\n Optional<TensorView> output2_scales_scalar;\n\n int64_t tile_tokens_dim{};\n int64_t routing_method_type{};\n bool use_shuffled_weight{};\n batchedGemm::gemm::MatrixLayout weight_layout{batchedGemm::gemm::MatrixLayout::MajorK};\n\n std::tuple<int, int> device_version;\n std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs> args;\n tensorrt_llm::kernels::trtllmgen_moe::MoE::MoEWorkspace workspace;\n\n btg::Dtype mDtypeAct{btg::Dtype::Bfloat16};\n btg::Dtype mDtypeWeights{btg::Dtype::Bfloat16};\n btg::Dtype mRoutingBiasDtype{\n btg::Dtype::Bfloat16}; // Dtype for expert weights in routing, based on routing bias\n ActivationType activation_type{ActivationType::Swiglu};\n\n int64_t intermediate_size_factor{2};\n\n public:\n // Constructor that initializes all TensorView members\n FusedMoeLauncher(const Optional<TensorView>& routing_logits,\n const Optional<TensorView>& routing_bias, const TensorView& hidden_states,\n const TensorView& gemm1_weights,\n const Optional<TensorView>& output1_scales_scalar,\n const Optional<TensorView>& output1_scales_gate_scalar,\n const TensorView& gemm2_weights,\n const Optional<TensorView>& output2_scales_scalar)\n : routing_logits(routing_logits),\n routing_bias(routing_bias),\n hidden_states(hidden_states),\n gemm1_weights(gemm1_weights),\n output1_scales_scalar(output1_scales_scalar),\n output1_scales_gate_scalar(output1_scales_gate_scalar),\n gemm2_weights(gemm2_weights),\n output2_scales_scalar(output2_scales_scalar),\n tile_tokens_dim{},\n routing_method_type{},\n use_shuffled_weight{},\n weight_layout{batchedGemm::gemm::MatrixLayout::MajorK},\n mDtypeAct{btg::Dtype::Bfloat16},\n mDtypeWeights{btg::Dtype::Bfloat16},\n activation_type{ActivationType::Swiglu},\n intermediate_size_factor{2} {}\n\n protected:\n // Initialize common data necessary for later.\n // May throw exception from TVM_FFI_ICHECK.\n void init_common(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, ActivationType activation_type);\n\n // Routing logits [num_tokens, num_experts]\n void check_routing_logits_shape() const {\n if (routing_logits.has_value()) {\n TVM_FFI_ICHECK_EQ(routing_logits.value().ndim(), 2) << \"routing_logits must be 2D.\";\n TVM_FFI_ICHECK_EQ(routing_logits.value().size(0), hidden_states.size(0))\n << \"routing_logits and hidden_states must have the same number of tokens.\";\n TVM_FFI_ICHECK_EQ(routing_logits.value().size(1), args->num_experts)\n << \"routing_logits dim1 must match num_experts.\";\n }\n }\n\n // Routing bias [num_experts]\n void check_routing_bias_shape() const {\n if (routing_bias.has_value()) {\n TVM_FFI_ICHECK_EQ(routing_bias.value().ndim(), 1) << \"routing_bias must be 1D.\";\n TVM_FFI_ICHECK_EQ(routing_bias.value().size(0), args->num_experts)\n << \"routing_bias has incorrect shape.\";\n }\n }\n\n // Hidden states [num_tokens, hidden_size]\n void check_hidden_states_shape() const {\n TVM_FFI_ICHECK_EQ(hidden_states.ndim(), 2) << \"hidden_states must be 2D.\";\n TVM_FFI_ICHECK_EQ(hidden_states.size(1), args->intermediate_size)\n << \"hidden_states has incorrect shape.\";\n }\n\n // GEMM1 or GEMM2 weights [num_experts, M, K] or [num_experts, K/block_k, M, block_k]\n void check_weights_shape(std::string which_weights) const {\n TensorView weights = (which_weights == \"gemm1\") ? gemm1_weights : gemm2_weights;\n if (which_weights != \"gemm1\" && which_weights != \"gemm2\") {\n TVM_FFI_LOG_AND_THROW(InternalError) << \"Internal error: which_weights = \" << which_weights;\n }\n\n int64_t Mn = 0, K = 0;\n if (weight_layout == batchedGemm::gemm::MatrixLayout::MajorK) {\n // MajorK [num_experts, M, K]\n Mn = weights.size(1);\n K = weights.size(2);\n } else if (weight_layout == batchedGemm::gemm::MatrixLayout::BlockMajorK) {\n // BlockMajorK [num_experts, K/block_k, M, block_k]\n Mn = weights.size(2);\n int64_t block_k = weights.size(3);\n K = weights.size(1) * block_k;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"Unsupported weight_layout: \" << (int)weight_layout;\n }\n if (which_weights == \"gemm1\") {\n // Gated MoE activations (e.g. Swiglu/Geglu) pack gate+up projections in GEMM1,\n // so Mn = 2 * intermediate_size and must be even.\n if (intermediate_size_factor == 2) {\n TVM_FFI_ICHECK_EQ(Mn % 2, 0) << which_weights << \" weights Mn dimension must be even.\";\n }\n // Non-gated activations (e.g. Relu2) use a single projection in GEMM1,\n // so Mn = intermediate_size. This check covers both gated and non-gated cases.\n TVM_FFI_ICHECK_EQ(args->intermediate_size * intermediate_size_factor, Mn)\n << \"intermediate_size has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(K, hidden_states.size(1))\n << which_weights << \" weights K dimension must be equal to hidden_size.\";\n } else if (which_weights == \"gemm2\") {\n // GEMM2 always consumes the post-activation hidden of size intermediate_size.\n TVM_FFI_ICHECK_EQ(K, args->intermediate_size)\n << which_weights << \" weights K dimension must be equal to intermediate_size.\";\n }\n }\n\n void check_routing_common() const {\n TVM_FFI_ICHECK(args->top_k > 0 && args->top_k <= args->num_experts)\n << \"top_k must be between 1 and num_experts\";\n TVM_FFI_ICHECK(args->local_num_experts > 0 && args->local_num_experts <= args->num_experts)\n << \"local_num_experts must be between 1 and num_experts\";\n TVM_FFI_ICHECK(args->local_expert_offset >= 0 &&\n args->local_expert_offset + args->local_num_experts <= args->num_experts)\n << \"expert offset and count must be within valid range\";\n\n check_routing_logits_shape();\n\n if (routing_bias.has_value()) {\n check_routing_bias_shape();\n }\n }\n\n // Routing phase workspace tensors (allocated in prepare_routing() or prepare_routing_common())\n Tensor num_tokens_per_expert;\n Tensor total_num_padded_tokens;\n Tensor expanded_idx_to_permuted_idx;\n Tensor permuted_idx_to_token_idx;\n Tensor expert_weights;\n Tensor expert_indexes;\n Tensor expert_count_histogram;\n Tensor cta_idx_xy_to_batch_idx;\n Tensor cta_idx_xy_to_mn_limit;\n Tensor num_non_exiting_ctas;\n\n void prepare_routing_common() {\n // Allocate routing phase workspace tensors\n num_tokens_per_expert = alloc_tensor({args->num_experts}, dl_int32, hidden_states.device());\n int32_t max_num_padded_tokens =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::getMaxPermutedPaddedCount(\n args->num_tokens, args->top_k, args->num_experts, tile_tokens_dim);\n\n total_num_padded_tokens = alloc_tensor({1}, dl_int32, hidden_states.device());\n\n expanded_idx_to_permuted_idx =\n alloc_tensor({args->num_tokens * args->top_k}, dl_int32, hidden_states.device());\n\n permuted_idx_to_token_idx =\n alloc_tensor({max_num_padded_tokens}, dl_int32, hidden_states.device());\n\n expert_indexes =\n alloc_tensor({args->num_tokens, args->top_k}, dl_int32, hidden_states.device());\n\n // expert_weights allocation should be done by derived class since data type could vary\n\n int64_t const size_of_expert_count_histogram = std::max(args->num_experts * 2, 256 * 2);\n expert_count_histogram = alloc_tensor({size_of_expert_count_histogram},\n dl_int32, // 256 is the max number of threads per block\n // and max number of experts\n hidden_states.device());\n\n int32_t max_num_ctas = tensorrt_llm::kernels::trtllmgen_moe::Routing::getMaxNumCtasInBatchDim(\n args->num_tokens, args->top_k, args->num_experts, tile_tokens_dim);\n\n cta_idx_xy_to_batch_idx = alloc_tensor({max_num_ctas}, dl_int32, hidden_states.device());\n\n cta_idx_xy_to_mn_limit = alloc_tensor({max_num_ctas}, dl_int32, hidden_states.device());\n\n num_non_exiting_ctas = alloc_tensor({1}, dl_int32, hidden_states.device());\n\n workspace.total_num_padded_tokens = static_cast<int*>(total_num_padded_tokens.data_ptr());\n workspace.total_max_padded_tokens = max_num_padded_tokens;\n workspace.ProjUpTileN = tile_tokens_dim;\n workspace.routing_expert_indexes = static_cast<int*>(expert_indexes.data_ptr());\n workspace.permuted_idx_size = static_cast<int*>(total_num_padded_tokens.data_ptr());\n workspace.expanded_idx_to_permuted_idx =\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr());\n workspace.permuted_idx_to_token_idx = static_cast<int*>(permuted_idx_to_token_idx.data_ptr());\n // workspace.expert_weights will be set by derived class after expert_weights allocation\n workspace.cta_idx_xy_to_batch_idx = static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr());\n workspace.cta_idx_xy_to_mn_limit = static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr());\n workspace.num_non_exiting_ctas = static_cast<int*>(num_non_exiting_ctas.data_ptr());\n }\n\n void check_moe_common() const {\n // Hidden states [num_tokens, hidden_size]\n TVM_FFI_ICHECK_EQ(hidden_states.ndim(), 2) << \"hidden_states must be 2D.\";\n }\n\n // MoE computation phase workspace tensors (allocated in prepare_moe() or prepare_moe_common())\n Tensor gemm1_output;\n Tensor activation_output;\n Tensor gemm2_output;\n Tensor workspace_fc1;\n Tensor workspace_fc2;\n Tensor output;\n int64_t moe_tactic{-1};\n std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner> moe_runner;\n\n void prepare_moe_common(int64_t& moe_tactic) {\n using RunnerType = tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner;\n // For FP8 block-scale (E4m3 activations, E4m3 weights) with DeepSeek FP8, use the\n // weights-only Runner constructor to match the original kernel path and numerics.\n if (this->mDtypeAct == btg::Dtype::E4m3 && this->mDtypeWeights == btg::Dtype::E4m3 &&\n args->mUseDeepSeekFp8) {\n moe_runner = std::make_unique<RunnerType>(this->mDtypeWeights, args->mUseDeepSeekFp8,\n (int32_t)tile_tokens_dim, this->use_shuffled_weight,\n this->weight_layout);\n } else {\n moe_runner = std::make_unique<RunnerType>(\n this->mDtypeAct, this->mDtypeWeights, args->mUseDeepSeekFp8, (int32_t)tile_tokens_dim,\n this->activation_type, this->use_shuffled_weight, this->weight_layout);\n }\n\n if (moe_tactic == -1) {\n moe_tactic = moe_runner->getDefaultValidConfigIndex(\n args->top_k, args->hidden_size, args->intermediate_size, args->local_num_experts,\n args->num_tokens);\n }\n auto valid_cfgs =\n moe_runner->getValidConfigIndices(args->top_k, args->hidden_size, args->intermediate_size,\n args->local_num_experts, args->num_tokens);\n auto valid_it = std::find(valid_cfgs.begin(), valid_cfgs.end(), moe_tactic);\n FLASHINFER_CHECK(valid_it != valid_cfgs.end(), \"Invalid MoE tactic \", moe_tactic,\n \" for tile_N=\", tile_tokens_dim, \". Number of valid tactics for this tile is \",\n valid_cfgs.size(),\n \". This often indicates a stale or mismatched autotuner cache entry.\");\n this->moe_tactic = moe_tactic;\n\n auto workspace_sizes = moe_runner->getWorkspaceSizeInBytes(*args, moe_tactic);\n workspace_fc1 = alloc_tensor({std::get<0>(workspace_sizes)}, dl_int8, hidden_states.device());\n workspace_fc2 = alloc_tensor({std::get<1>(workspace_sizes)}, dl_int8, hidden_states.device());\n workspace.bmm1_workspace = workspace_fc1.data_ptr();\n workspace.bmm2_workspace = workspace_fc2.data_ptr();\n }\n\n public:\n virtual void check_routing() const = 0;\n virtual void prepare_routing() = 0;\n virtual void check_moe() const = 0;\n virtual void prepare_moe(int64_t& moe_tactic) = 0;\n\n // Main entry point for all the executions.\n // Do initializations prior to calling this as the initializations are different for bf16, fp8 and\n // fp4. The executions are non-blocking by default.\n virtual Array<Tensor> run(int64_t moe_tactic, bool enable_pdl = true,\n bool use_routing_scales_on_input = false,\n bool use_deep_seek_fp8 = false) {\n check_routing();\n prepare_routing();\n\n // Execute routing\n tensorrt_llm::kernels::trtllmgen_moe::Routing::Runner routing_runner(tile_tokens_dim);\n cudaStream_t routing_stream = get_stream(hidden_states.device());\n\n routing_runner.run(\n args->routing_logits, args->routing_bias, args->num_tokens, args->num_experts, args->top_k,\n args->n_group, args->topk_group, args->local_expert_offset, args->local_num_experts,\n args->routed_scaling_factor, workspace.routing_expert_indexes,\n static_cast<int*>(expert_count_histogram.data_ptr()),\n static_cast<int*>(total_num_padded_tokens.data_ptr()),\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr()),\n nullptr /*permuted_idx_to_expanded_idx.data_ptr()*/,\n static_cast<int*>(permuted_idx_to_token_idx.data_ptr()), workspace.expert_weights,\n static_cast<int*>(num_tokens_per_expert.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr()),\n static_cast<int*>(num_non_exiting_ctas.data_ptr()), args->mDtypeElt, mRoutingBiasDtype,\n use_routing_scales_on_input, use_deep_seek_fp8,\n static_cast<RoutingMethodType>(routing_method_type), routing_stream);\n\n check_moe();\n prepare_moe(moe_tactic);\n\n cudaStream_t moe_stream = get_stream(hidden_states.device());\n moe_runner->run(*args, workspace, hidden_states.device().device_id, moe_stream, moe_tactic,\n enable_pdl);\n\n if (args->do_finalize) {\n return {output};\n }\n return {gemm2_output, FusedMoeLauncher::expert_weights, expanded_idx_to_permuted_idx};\n }\n};\n\nvoid FusedMoeLauncher::init_common(\n std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, ActivationType activation_type) {\n // Check devicearchitecture: Blackwell (SM 10.x) required\n auto device = hidden_states.device().device_id;\n int major = 0, minor = 0;\n cudaDeviceGetAttribute(&major, cudaDevAttrComputeCapabilityMajor, device);\n cudaDeviceGetAttribute(&minor, cudaDevAttrComputeCapabilityMinor, device);\n TVM_FFI_ICHECK(major == 10 || major == 12)\n << \"MoE kernel requires SM 10.x or SM 12.x architecture. Current device has SM \" << major\n << minor;\n this->device_version = std::make_tuple(major, minor);\n\n args->routing_logits = routing_logits.has_value() ? routing_logits.value().data_ptr() : nullptr;\n args->routing_bias = routing_bias.has_value() ? routing_bias.value().data_ptr() : nullptr;\n args->hidden_states = hidden_states.data_ptr();\n args->gemm1_weights = gemm1_weights.data_ptr();\n args->gemm2_weights = gemm2_weights.data_ptr();\n\n this->args = std::move(args);\n this->tile_tokens_dim = tile_tokens_dim;\n this->routing_method_type = routing_method_type;\n this->use_shuffled_weight = use_shuffled_weight;\n TVM_FFI_ICHECK(0 <= weight_layout && weight_layout <= 2)\n << \"the value of weight_layout is not recognized\";\n this->weight_layout = static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout);\n this->activation_type = activation_type;\n this->intermediate_size_factor = isGatedActivation(activation_type) ? 2 : 1;\n}\n\nclass Bf16MoeLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 5> mSupportedTileNums = {8, 16, 32, 64, 128};\n\n Bf16MoeLauncher(Optional<TensorView> const& routing_logits,\n Optional<TensorView> const& routing_bias, TensorView const& expert_indices,\n TensorView const& expert_weights, TensorView const& hidden_states,\n TensorView const& gemm1_weights, TensorView const& gemm2_weights)\n : FusedMoeLauncher(routing_logits, routing_bias, hidden_states, gemm1_weights,\n Optional<TensorView>(), Optional<TensorView>(), gemm2_weights,\n Optional<TensorView>()),\n expert_indices(expert_indices),\n expert_weights(expert_weights) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout) {\n constexpr ActivationType activation_type =\n ActivationType::Swiglu; // not exposed in api for now\n\n // Do base class init and perform common checks\n FusedMoeLauncher::init_common(std::move(args), tile_tokens_dim, routing_method_type,\n use_shuffled_weight, weight_layout, activation_type);\n }\n\n void check_routing() const override {\n FusedMoeLauncher::check_routing_common();\n if (expert_indices.ndim() == 2 && expert_indices.size(0) > 0) {\n // Pre-computed routing: expert_indices is a packed tensor\n // Format: (expert_id << 16) | (weight_bf16.view(int16))\n TVM_FFI_ICHECK_EQ(expert_indices.ndim(), 2) << \"expert_indices must be 2D.\";\n TVM_FFI_ICHECK_EQ(expert_indices.size(0), hidden_states.size(0))\n << \"expert_indices and hidden_states must have same number of tokens.\";\n TVM_FFI_ICHECK_EQ(expert_indices.size(1), args->top_k)\n << \"expert_indices dim1 must match top_k.\";\n TVM_FFI_ICHECK_EQ(expert_indices.dtype(), dl_int32) << \"expert_indices must be int32.\";\n }\n\n // TODO n_group, topk_group validation?\n }\n\n void prepare_routing() override {\n FusedMoeLauncher::prepare_routing_common();\n\n args->mDtypeElt = btg::Dtype::Bfloat16;\n args->mUseDeepSeekFp8 = false;\n\n // Set expert weights dtype based on routing bias\n auto const routing_bias_dtype =\n routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool has_precomputed_indices = expert_indices.ndim() == 2 && expert_indices.size(0) > 0;\n if (has_precomputed_indices) {\n // Use expert_indices directly\n workspace.routing_expert_indexes =\n static_cast<int*>(const_cast<void*>(expert_indices.data_ptr()));\n }\n bool has_precomputed_weights = expert_weights.ndim() == 2 && expert_weights.size(0) > 0;\n if (has_precomputed_weights) {\n workspace.expert_weights = const_cast<void*>(expert_weights.data_ptr());\n } else {\n FusedMoeLauncher::expert_weights =\n alloc_tensor({args->num_tokens, args->top_k}, dl_bfloat16, hidden_states.device());\n workspace.expert_weights = FusedMoeLauncher::expert_weights.data_ptr();\n }\n }\n\n void check_moe() const override {\n FusedMoeLauncher::check_moe_common();\n\n TVM_FFI_ICHECK(weight_layout == batchedGemm::gemm::MatrixLayout::BlockMajorK)\n << \"BF16 Moe: weight_layout must be BlockMajorK\";\n check_weights_shape(\"gemm1\");\n check_weights_shape(\"gemm2\");\n\n TVM_FFI_ICHECK_EQ(args->intermediate_size % 128, 0)\n << \"the second dimension of weights must be a multiple of 128.\";\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n int32_t max_num_padded_tokens = workspace.total_max_padded_tokens;\n gemm1_output = alloc_tensor({max_num_padded_tokens, args->intermediate_size}, dl_bfloat16,\n hidden_states.device());\n activation_output = alloc_tensor({max_num_padded_tokens, args->intermediate_size}, dl_bfloat16,\n hidden_states.device());\n gemm2_output = alloc_tensor({max_num_padded_tokens, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n workspace.hidden_states_scale_linear = nullptr;\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = nullptr;\n workspace.activation_output = activation_output.data_ptr();\n workspace.activation_output_scale = nullptr;\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n\n if (args->output == nullptr) {\n output =\n alloc_tensor({args->num_tokens, args->hidden_size}, dl_bfloat16, hidden_states.device());\n args->output = output.data_ptr();\n }\n args->output_scale = nullptr;\n }\n\n static Array<Array<int64_t>> getValidConfigs(int64_t top_k, int64_t hidden_size,\n int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens, int64_t act_type,\n bool use_shuffled_weight, int64_t weight_layout) {\n Array<Array<int64_t>> valid_configs;\n\n std::vector<int32_t> supported_tile_nums(mSupportedTileNums.begin(), mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n auto moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n btg::Dtype::Bfloat16, // dtype_act\n btg::Dtype::Bfloat16, // dtype_weights\n false, // useDeepSeekFp8\n tile_N, static_cast<ActivationType>(act_type), use_shuffled_weight,\n static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout));\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n\n private:\n TensorView expert_weights;\n TensorView expert_indices;\n};\n\nclass Fp8PerTensorLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 5> mSupportedTileNums = {8, 16, 32, 64, 128};\n\n // Constructor that passes TensorView parameters to base constructor\n Fp8PerTensorLauncher(TensorView const& routing_logits, Optional<TensorView> const& routing_bias,\n TensorView const& hidden_states, TensorView const& gemm1_weights,\n TensorView const& output1_scales_scalar,\n TensorView const& output1_scales_gate_scalar,\n TensorView const& gemm2_weights, TensorView const& output2_scales_scalar)\n : FusedMoeLauncher(Optional<TensorView>(routing_logits), routing_bias, hidden_states,\n gemm1_weights, Optional<TensorView>(output1_scales_scalar),\n Optional<TensorView>(output1_scales_gate_scalar), gemm2_weights,\n Optional<TensorView>(output2_scales_scalar)),\n use_routing_scales_on_input(false) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, bool use_routing_scales_on_input_param,\n ActivationType activation_type) {\n this->use_routing_scales_on_input = use_routing_scales_on_input_param;\n\n auto dtype = hidden_states.dtype();\n if (dtype == dl_float16) {\n mDtypeAct = btg::Dtype::Fp16;\n } else if (dtype == dl_bfloat16) {\n mDtypeAct = btg::Dtype::Bfloat16;\n } else if (dtype == dl_float8_e4m3fn) {\n mDtypeAct = btg::Dtype::E4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for FP8 MoE.\";\n }\n mDtypeWeights = btg::Dtype::E4m3;\n\n FusedMoeLauncher::init_common(std::move(args), tile_tokens_dim, routing_method_type,\n use_shuffled_weight, weight_layout, activation_type);\n }\n\n void check_routing() const override { FusedMoeLauncher::check_routing_common(); }\n\n void prepare_routing() override {\n FusedMoeLauncher::prepare_routing_common();\n\n auto dtype = hidden_states.dtype();\n if (dtype == dl_float16) {\n args->mDtypeElt = btg::Dtype::Fp16;\n } else if (dtype == dl_bfloat16) {\n args->mDtypeElt = btg::Dtype::Bfloat16;\n } else if (dtype == dl_float8_e4m3fn) {\n args->mDtypeElt = btg::Dtype::E4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for MoE.\";\n }\n\n args->mDtypeOut = btg::Dtype::Bfloat16;\n args->mUseDeepSeekFp8 = false;\n\n auto const routing_bias_dtype =\n routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n\n expert_weights =\n alloc_tensor({args->num_tokens, args->top_k}, dl_bfloat16, hidden_states.device());\n\n workspace.expert_weights = expert_weights.data_ptr();\n if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::Llama4) {\n workspace.token_scales = expert_weights.data_ptr(); // Consumed by permuteGemm1 kernel\n }\n }\n\n void check_moe() const override {\n FusedMoeLauncher::check_moe_common();\n\n TVM_FFI_ICHECK(output1_scales_scalar.has_value())\n << \"output1_scales_scalar is required for FP8 MoE\";\n TVM_FFI_ICHECK_EQ(output1_scales_scalar.value().dtype(), dl_float32)\n << \"output1_scales_scalar must be float.\";\n TVM_FFI_ICHECK_EQ(output1_scales_scalar.value().ndim(), 1)\n << \"output1_scales_scalar must be 1D.\";\n TVM_FFI_ICHECK_EQ(output1_scales_scalar.value().size(0), args->local_num_experts)\n << \"output1_scales_scalar has incorrect dim 0.\";\n\n TVM_FFI_ICHECK(output1_scales_gate_scalar.has_value())\n << \"output1_scales_gate_scalar is required for FP8 MoE\";\n TVM_FFI_ICHECK_EQ(output1_scales_gate_scalar.value().dtype(), dl_float32)\n << \"output1_scales_gate_scalar must be float.\";\n TVM_FFI_ICHECK_EQ(output1_scales_gate_scalar.value().ndim(), 1)\n << \"output1_scales_gate_scalar must be 1D.\";\n TVM_FFI_ICHECK_EQ(output1_scales_gate_scalar.value().size(0), args->local_num_experts)\n << \"output1_scales_gate_scalar has incorrect dim 0.\";\n\n TVM_FFI_ICHECK(output2_scales_scalar.has_value())\n << \"output2_scales_scalar is required for FP8 MoE\";\n TVM_FFI_ICHECK_EQ(output2_scales_scalar.value().dtype(), dl_float32)\n << \"output2_scales_scalar must be float.\";\n TVM_FFI_ICHECK_EQ(output2_scales_scalar.value().ndim(), 1)\n << \"output2_scales_scalar must be 1D.\";\n TVM_FFI_ICHECK_EQ(output2_scales_scalar.value().size(0), args->local_num_experts)\n << \"output2_scales_scalar has incorrect dim 0.\";\n\n TVM_FFI_ICHECK(hidden_states.dtype() == dl_float8_e4m3fn ||\n hidden_states.dtype() == dl_float16 || hidden_states.dtype() == dl_bfloat16)\n << \"FP8 MoE: hidden_states must be float8_e4m3fn, float16, or bfloat16.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 MoE: gemm1_weights must be float8_e4m3fn.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 MoE: gemm2_weights must be float8_e4m3fn.\";\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n int32_t max_num_padded_tokens_gemm1 = workspace.total_max_padded_tokens + args->num_experts;\n int32_t max_num_padded_tokens_gemm2 = workspace.total_max_padded_tokens;\n\n gemm1_output = alloc_tensor({max_num_padded_tokens_gemm1, 2 * args->intermediate_size},\n dl_uint8, hidden_states.device());\n gemm1_output_scale =\n alloc_tensor({2 * args->intermediate_size / 128, max_num_padded_tokens_gemm1}, dl_float32,\n hidden_states.device());\n\n activation_output = alloc_tensor({max_num_padded_tokens_gemm1, args->intermediate_size},\n dl_uint8, hidden_states.device());\n activation_output_scale =\n alloc_tensor({args->intermediate_size / 128, max_num_padded_tokens_gemm1}, dl_float32,\n hidden_states.device());\n\n gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n workspace.hidden_states_scale_linear = nullptr;\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = static_cast<float*>(gemm1_output_scale.data_ptr());\n workspace.activation_output = activation_output.data_ptr();\n workspace.activation_output_scale = static_cast<float*>(activation_output_scale.data_ptr());\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n\n if (args->output == nullptr) {\n output =\n alloc_tensor({args->num_tokens, args->hidden_size}, dl_bfloat16, hidden_states.device());\n args->output = output.data_ptr();\n }\n args->output_scale = nullptr;\n\n // Set scale pointers\n TVM_FFI_ICHECK(output1_scales_scalar.has_value());\n TVM_FFI_ICHECK(output1_scales_gate_scalar.has_value());\n TVM_FFI_ICHECK(output2_scales_scalar.has_value());\n\n args->output1_scales_scalar = static_cast<float*>(output1_scales_scalar.value().data_ptr());\n args->output1_scales_gate_scalar =\n static_cast<float*>(output1_scales_gate_scalar.value().data_ptr());\n args->output2_scales_scalar = static_cast<float*>(output2_scales_scalar.value().data_ptr());\n }\n\n private:\n bool use_routing_scales_on_input;\n Tensor gemm1_output_scale;\n Tensor activation_output_scale;\n\n public:\n static Array<Array<int64_t>> getValidConfigs(int64_t top_k, int64_t hidden_size,\n int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens, int64_t act_type,\n bool use_shuffled_weight, int64_t weight_layout,\n btg::Dtype dtype_act, btg::Dtype dtype_weights) {\n Array<Array<int64_t>> valid_configs;\n\n std::vector<int32_t> supported_tile_nums(mSupportedTileNums.begin(), mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n auto moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n dtype_act, dtype_weights,\n false, // useDeepSeekFp8\n tile_N, static_cast<ActivationType>(act_type), use_shuffled_weight,\n static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout));\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n};\n\nclass Fp8BlockScaleLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 5> mBaseSupportedTileNums = {8, 16, 32, 64, 128};\n\n static std::vector<int32_t> getSupportedTileNums(Fp8QuantizationType quantization_type) {\n std::vector<int32_t> tiles(mBaseSupportedTileNums.begin(), mBaseSupportedTileNums.end());\n if (quantization_type == Fp8QuantizationType::MxFp8) {\n tiles.push_back(256);\n }\n return tiles;\n }\n\n Fp8BlockScaleLauncher(Optional<TensorView> const& routing_logits,\n Optional<TensorView> const& routing_bias, TensorView const& hidden_states,\n TensorView const& hidden_states_scale, TensorView const& gemm1_weights,\n TensorView const& gemm1_weights_scale, TensorView const& gemm2_weights,\n TensorView const& gemm2_weights_scale, TensorView const& expert_indices,\n TensorView const& expert_weights, Fp8QuantizationType quantization_type)\n : FusedMoeLauncher(routing_logits, routing_bias, hidden_states, gemm1_weights,\n Optional<TensorView>(), Optional<TensorView>(), gemm2_weights,\n Optional<TensorView>()),\n hidden_states_scale(hidden_states_scale),\n gemm1_weights_scale(gemm1_weights_scale),\n gemm2_weights_scale(gemm2_weights_scale),\n expert_indices(expert_indices),\n expert_weights(expert_weights),\n quantization_type(quantization_type) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, ActivationType activation_type) {\n if (quantization_type == Fp8QuantizationType::MxFp8) {\n mDtypeAct = btg::Dtype::MxE4m3;\n mDtypeWeights = btg::Dtype::MxE4m3;\n } else {\n mDtypeAct = btg::Dtype::E4m3;\n mDtypeWeights = btg::Dtype::E4m3;\n }\n\n auto dtype = hidden_states.dtype();\n if (dtype == dl_float16) {\n args->mDtypeElt = btg::Dtype::Fp16;\n } else if (dtype == dl_bfloat16) {\n args->mDtypeElt = btg::Dtype::Bfloat16;\n } else if (dtype == dl_float8_e4m3fn) {\n args->mDtypeElt = btg::Dtype::E4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for MoE.\";\n }\n\n // Output is always bfloat16 for FP8 block scale\n args->mDtypeOut = btg::Dtype::Bfloat16;\n\n FusedMoeLauncher::init_common(std::move(args), tile_tokens_dim, routing_method_type,\n use_shuffled_weight, weight_layout, activation_type);\n }\n\n void check_routing() const override {\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n if (expert_indices.ndim() == 2 && expert_indices.size(0) > 0) {\n // Pre-computed routing: expert_indices is a packed tensor\n // Format: (expert_id << 16) | (weight_bf16.view(int16))\n TVM_FFI_ICHECK_EQ(expert_indices.ndim(), 2) << \"expert_indices must be 2D.\";\n TVM_FFI_ICHECK_EQ(expert_indices.size(0), hidden_states.size(0))\n << \"expert_indices and hidden_states must have same number of tokens.\";\n TVM_FFI_ICHECK_EQ(expert_indices.size(1), args->top_k)\n << \"expert_indices dim1 must match top_k.\";\n TVM_FFI_ICHECK_EQ(expert_indices.dtype(), dl_int32) << \"expert_indices must be int32.\";\n }\n\n FusedMoeLauncher::check_routing_common();\n\n if (static_cast<RoutingMethodType>(routing_method_type) != RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK(args->n_group <= 1)\n << \"Current routing kernel (no groups) only supports n_group <= 1\";\n TVM_FFI_ICHECK(args->topk_group <= 1)\n << \"Current routing kernel (no groups) only supports topk_group <= 1\";\n }\n\n if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK(args->n_group != 0) << \"n_group should not be zero for DeepSeekV3 routing\";\n TVM_FFI_ICHECK(args->topk_group != 0) << \"if n_group is given, topk_group must be given\";\n TVM_FFI_ICHECK_EQ(args->num_experts % args->n_group, 0)\n << \"num_experts must be divisible by n_group\";\n // DeepSeekV3 routing supports top_k up to:\n // - 8 when num_experts <= 384 (NumKimiK2Experts)\n // - 22 when num_experts > 384 (NumNemotronExperts path)\n // Keep this in sync with LAUNCH_ROUTING_DEEPSEEK in trtllm_fused_moe_routing_deepseek.cu.\n constexpr int32_t kNumKimiK2Experts = 384; // same as in trtllm_fused_moe_routing_deepseek.cu\n int32_t max_supported_top_k = args->num_experts <= kNumKimiK2Experts ? 8 : 22;\n TVM_FFI_ICHECK(args->top_k <= max_supported_top_k && args->top_k > 0)\n << \"Current routing kernel (with groups) only supports top_k<=\" << max_supported_top_k\n << \" && top_k>0 for num_experts=\" << args->num_experts << \".\";\n TVM_FFI_ICHECK(args->topk_group <= 4 && args->topk_group > 0)\n << \"Current routing kernel only (with groups) supports topk_group<=4 && topk_group > 0.\";\n TVM_FFI_ICHECK_LE(args->topk_group, args->n_group)\n << \"n_group must not be smaller than topk_group.\";\n TVM_FFI_ICHECK_LT(args->top_k, (args->topk_group * args->num_experts / args->n_group))\n << \"top_k must be less than total number of experts in selected groups\";\n } else if (static_cast<RoutingMethodType>(routing_method_type) ==\n RoutingMethodType::Renormalize ||\n static_cast<RoutingMethodType>(routing_method_type) ==\n RoutingMethodType::RenormalizeNaive) {\n TVM_FFI_ICHECK(args->top_k <= 32 && args->top_k > 0)\n << \"Current routing kernel (no groups, renormalize) only supports top_k<=10 && top_k>0.\";\n } else if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::Llama4) {\n TVM_FFI_ICHECK_EQ(args->top_k, 1)\n << \"Current routing kernel (no groups, Llama4) only supports top_k=1.\";\n }\n\n TVM_FFI_ICHECK_EQ(args->num_experts % 4, 0)\n << \"Routing kernel expects that num_experts must be divisible by 4\";\n TVM_FFI_ICHECK_GT(args->num_experts, args->top_k) << \"num_experts must be greater than top_k\";\n TVM_FFI_ICHECK_LE(args->local_num_experts + args->local_expert_offset, args->num_experts)\n << \"num_experts must be greater or equal to local_num_experts + local_expert_offset\";\n }\n\n void prepare_routing() override {\n FusedMoeLauncher::prepare_routing_common();\n\n auto dtype = hidden_states.dtype();\n if (dtype == dl_float16) {\n args->mDtypeElt = btg::Dtype::Fp16;\n } else if (dtype == dl_bfloat16) {\n args->mDtypeElt = btg::Dtype::Bfloat16;\n } else if (dtype == dl_float8_e4m3fn) {\n args->mDtypeElt = btg::Dtype::E4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for MoE.\";\n }\n\n args->mUseDeepSeekFp8 = quantization_type == Fp8QuantizationType::DeepSeekFp8;\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool has_precomputed_indices = expert_indices.ndim() == 2 && expert_indices.size(0) > 0;\n if (has_precomputed_indices) {\n // Use expert_indices directly\n workspace.routing_expert_indexes =\n static_cast<int*>(const_cast<void*>(expert_indices.data_ptr()));\n } else {\n // Use routing_logits directly\n args->routing_logits = static_cast<float*>(routing_logits.value().data_ptr());\n }\n // Set expert weights dtype based on routing bias\n auto const routing_bias_dtype =\n routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool has_precomputed_weights = expert_weights.ndim() == 2 && expert_weights.size(0) > 0;\n if (!has_precomputed_weights) {\n // Allocate expert_weights buffer for routing output\n FusedMoeLauncher::expert_weights =\n alloc_tensor({args->num_tokens, args->top_k}, dl_bfloat16, hidden_states.device());\n workspace.expert_weights = FusedMoeLauncher::expert_weights.data_ptr();\n } else {\n workspace.expert_weights = const_cast<void*>(expert_weights.data_ptr());\n }\n }\n\n void check_moe() const override {\n FusedMoeLauncher::check_moe_common();\n\n TVM_FFI_ICHECK_EQ(hidden_states.dtype(), dl_float8_e4m3fn) << \"hidden_states must be fp8.\";\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(hidden_states_scale.dtype(), dl_float32)\n << \"hidden_states_scale must be float.\";\n TVM_FFI_ICHECK_EQ(hidden_states_scale.ndim(), 2) << \"hidden_states_scale must be 2D.\";\n TVM_FFI_ICHECK_EQ(hidden_states_scale.size(0), hidden_states.size(1) / 128)\n << \"hidden_states_scale dim0 must match hidden_states dim1 / 128.\";\n TVM_FFI_ICHECK_EQ(hidden_states_scale.size(1), args->num_tokens)\n << \"hidden_states_scale dim1 must match num_tokens.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_CHECK(weight_layout == batchedGemm::gemm::MatrixLayout::MajorK,\n \"weight_layout must be MajorK for MxFp8.\");\n TVM_FFI_ICHECK_EQ(hidden_states_scale.dtype(), dl_uint8);\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_float8_e4m3fn) << \"gemm1_weights must be fp8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_float8_e4m3fn) << \"gemm2_weights must be fp8.\";\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_float32)\n << \"gemm1_weights_scale must be float.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.ndim(), 3) << \"gemm1_weights_scale must be 3D.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.size(0), args->local_num_experts)\n << \"gemm1_weights_scale has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(args->intermediate_size % 128, 0)\n << \"intermediate_size must be a multiple of 128.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.size(1),\n intermediate_size_factor * args->intermediate_size / 128)\n << \"gemm1_weights_scale has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.size(2), args->hidden_size / 128)\n << \"gemm1_weights_scale has incorrect shape.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_uint8)\n << \"gemm1_weights_scale must be uint8.\";\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_float32)\n << \"gemm2_weights_scale must be float.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.ndim(), 3) << \"gemm2_weights_scale must be 3D.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.size(0), args->local_num_experts)\n << \"gemm2_weights_scale has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.size(1), args->hidden_size / 128)\n << \"gemm2_weights_scale has incorrect shape.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.size(2), args->intermediate_size / 128)\n << \"gemm2_weights_scale has incorrect shape.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_uint8)\n << \"gemm2_weights_scale must be uint8.\";\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n\n check_weights_shape(\"gemm1\");\n check_weights_shape(\"gemm2\");\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(args->intermediate_size % 128, 0)\n << \"intermediate_size must be a multiple of 128.\";\n }\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n // Calculate max_num_padded_tokens for gemm1 and gemm2 using maybeGetMinTokenCount\n int32_t max_num_padded_tokens_gemm1 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->intermediate_size,\n btg::dtypeGetNumBits(args->mDtypeElt));\n int32_t max_num_padded_tokens_gemm2 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->hidden_size,\n btg::dtypeGetNumBits(args->mDtypeOut));\n\n gemm1_output = alloc_tensor(\n {max_num_padded_tokens_gemm1, intermediate_size_factor * args->intermediate_size}, dl_uint8,\n hidden_states.device());\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n gemm1_output_scale = alloc_tensor({intermediate_size_factor * args->intermediate_size / 128,\n workspace.total_max_padded_tokens},\n dl_float32, hidden_states.device());\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n // MxFP8 fuses the activation so no need for intermediate_size_factor\n int64_t sf_size = tensorrt_llm::computeSwizzledLayoutSFSize(max_num_padded_tokens_gemm1,\n args->intermediate_size / 32);\n gemm1_output_scale = alloc_tensor({sf_size}, dl_uint8, hidden_states.device());\n }\n\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n activation_output = alloc_tensor({max_num_padded_tokens_gemm1, args->intermediate_size},\n dl_uint8, hidden_states.device());\n activation_output_scale =\n alloc_tensor({args->intermediate_size / 128, max_num_padded_tokens_gemm1}, dl_float32,\n hidden_states.device());\n }\n\n gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n workspace.hidden_states_scale_linear = nullptr;\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = static_cast<float*>(gemm1_output_scale.data_ptr());\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n workspace.activation_output = activation_output.data_ptr();\n workspace.activation_output_scale = static_cast<float*>(activation_output_scale.data_ptr());\n }\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n\n if (args->output == nullptr) {\n output =\n alloc_tensor({args->num_tokens, args->hidden_size}, dl_bfloat16, hidden_states.device());\n args->output = output.data_ptr();\n }\n args->output_scale = nullptr;\n\n args->hidden_states_scale = static_cast<float*>(hidden_states_scale.data_ptr());\n args->gemm1_weights_scale = static_cast<float*>(gemm1_weights_scale.data_ptr());\n args->gemm2_weights_scale = static_cast<float*>(gemm2_weights_scale.data_ptr());\n }\n\n private:\n TensorView hidden_states_scale;\n TensorView gemm1_weights_scale;\n TensorView gemm2_weights_scale;\n Tensor gemm1_output_scale;\n Tensor activation_output_scale;\n TensorView expert_indices;\n TensorView expert_weights;\n Fp8QuantizationType quantization_type;\n\n public:\n // Override to handle pre-computed routing\n Array<Tensor> run(int64_t moe_tactic, bool enable_pdl = true,\n bool use_routing_scales_on_input = false,\n bool use_deep_seek_fp8 = false) override {\n check_routing();\n prepare_routing();\n\n cudaStream_t routing_stream = get_stream(hidden_states.device());\n tensorrt_llm::kernels::trtllmgen_moe::Routing::Runner routing_runner(tile_tokens_dim);\n\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool use_precomputed = expert_indices.ndim() == 2 && expert_indices.size(0) > 0;\n // When using pre-computed routing, pass nullptr as routing_logits to tell the\n // routing runner to use the pre-computed expert indices from workspace.routing_expert_indexes\n routing_runner.run(\n use_precomputed ? nullptr : args->routing_logits, args->routing_bias, args->num_tokens,\n args->num_experts, args->top_k, args->n_group, args->topk_group, args->local_expert_offset,\n args->local_num_experts, args->routed_scaling_factor, workspace.routing_expert_indexes,\n static_cast<int*>(expert_count_histogram.data_ptr()),\n static_cast<int*>(total_num_padded_tokens.data_ptr()),\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr()),\n nullptr /*permuted_idx_to_expanded_idx.data_ptr()*/,\n static_cast<int*>(permuted_idx_to_token_idx.data_ptr()), workspace.expert_weights,\n static_cast<int*>(num_tokens_per_expert.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr()),\n static_cast<int*>(num_non_exiting_ctas.data_ptr()), args->mDtypeElt, mRoutingBiasDtype,\n use_routing_scales_on_input, use_deep_seek_fp8,\n static_cast<RoutingMethodType>(routing_method_type), routing_stream);\n\n check_moe();\n prepare_moe(moe_tactic);\n\n cudaStream_t moe_stream = get_stream(hidden_states.device());\n moe_runner->run(*args, workspace, hidden_states.device().device_id, moe_stream, moe_tactic,\n enable_pdl);\n\n if (args->do_finalize) {\n return {output};\n }\n return {gemm2_output, FusedMoeLauncher::expert_weights, expanded_idx_to_permuted_idx};\n }\n\n static Array<Array<int64_t>> getValidConfigs(\n int64_t top_k, int64_t hidden_size, int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens, bool use_shuffled_weight, int64_t weight_layout, btg::Dtype dtype_act,\n btg::Dtype dtype_weights, Fp8QuantizationType quantization_type, int64_t act_type) {\n Array<Array<int64_t>> valid_configs;\n auto activation_type = validateAndCastActivationType(act_type);\n\n auto supported_tile_nums = getSupportedTileNums(quantization_type);\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(supported_tile_nums, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner> moe_runner;\n // Keep getValidConfigs constructor path aligned with runtime prepare_moe_common().\n // This branch is for DeepSeek FP8 (E4m3 activations + E4m3 weights).\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8 && dtype_act == btg::Dtype::E4m3 &&\n dtype_weights == btg::Dtype::E4m3) {\n TVM_FFI_ICHECK(static_cast<int>(activation_type) ==\n static_cast<int>(ActivationType::Swiglu))\n << \"DeepSeekFp8 only supports ActivationType::Swiglu, got \"\n << static_cast<int>(activation_type) << \".\";\n moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n dtype_weights, true /* useDeepSeekFp8 */, tile_N, use_shuffled_weight,\n static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout));\n } else {\n // Under current trtllm_get_valid_moe_configs() dispatch rules, this else-path is\n // reached only by FP8 block-scale MXFP8 (dtype_act=dtype_weights=MxE4m3).\n moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n dtype_act, // dtypeAct\n dtype_weights, // dtypeWeights\n quantization_type == Fp8QuantizationType::DeepSeekFp8, // useDeepSeekFp8\n tile_N, activation_type, use_shuffled_weight,\n static_cast<batchedGemm::gemm::MatrixLayout>(weight_layout));\n }\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n};\n\nclass MxInt4BlockScaleLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 5> mSupportedTileNums = {8, 16, 32, 64, 128};\n\n MxInt4BlockScaleLauncher(TensorView const& routing_logits,\n Optional<TensorView> const& routing_bias,\n TensorView const& hidden_states, TensorView const& gemm1_weights,\n TensorView const& gemm1_weights_scale,\n Optional<TensorView> const& gemm1_alpha,\n Optional<TensorView> const& gemm1_beta,\n Optional<TensorView> const& gemm1_clamp_limit,\n TensorView const& gemm2_weights, TensorView const& gemm2_weights_scale)\n : FusedMoeLauncher(Optional<TensorView>(routing_logits), routing_bias, hidden_states,\n gemm1_weights, Optional<TensorView>(), Optional<TensorView>(),\n gemm2_weights, Optional<TensorView>()),\n gemm1_weights_scale(gemm1_weights_scale),\n gemm2_weights_scale(gemm2_weights_scale) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type) {\n // currently only support mxint4 x bf16\n auto dtype = hidden_states.dtype();\n if (dtype == dl_bfloat16) {\n args->mDtypeElt = btg::Dtype::Bfloat16;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input dtype for MoE.\";\n }\n args->mDtypeOut = btg::Dtype::Bfloat16;\n\n mDtypeAct = btg::Dtype::Bfloat16;\n mDtypeWeights = btg::Dtype::MxInt4;\n\n FusedMoeLauncher::init_common(\n std::move(args), tile_tokens_dim, routing_method_type,\n /*use_shuffled_weight=*/true,\n static_cast<int64_t>(batchedGemm::gemm::MatrixLayout::BlockMajorK), ActivationType::Swiglu);\n }\n\n void check_routing() const override { FusedMoeLauncher::check_routing_common(); }\n\n void prepare_routing() override {\n FusedMoeLauncher::prepare_routing_common();\n\n args->mDtypeElt = mDtypeAct;\n args->mUseDeepSeekFp8 = false;\n // Set expert weights dtype based on routing bias\n auto const routing_bias_dtype =\n routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n\n expert_weights =\n alloc_tensor({args->num_tokens, args->top_k}, dl_bfloat16, hidden_states.device());\n\n workspace.expert_weights = expert_weights.data_ptr();\n }\n\n void check_moe() const override {\n TVM_FFI_ICHECK(mDtypeAct == btg::Dtype::Bfloat16)\n << \"Only Bfloat16 is supported by MxInt4 block scale MoE\";\n\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_uint8) << \"gemm1_weights must be uint8.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_bfloat16)\n << \"gemm1_weights_scale must be bf16.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_uint8) << \"gemm2_weights must be uint8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_bfloat16)\n << \"gemm2_weights_scale must be bf16.\";\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n args->hidden_states = hidden_states.data_ptr();\n args->hidden_states_scale = nullptr;\n args->gemm1_weights = gemm1_weights.data_ptr();\n args->gemm1_weights_scale = gemm1_weights_scale.data_ptr();\n args->gemm1_alpha =\n gemm1_alpha.has_value() ? static_cast<float*>(gemm1_alpha.value().data_ptr()) : nullptr;\n args->gemm1_beta =\n gemm1_beta.has_value() ? static_cast<float*>(gemm1_beta.value().data_ptr()) : nullptr;\n args->gemm1_clamp_limit = gemm1_clamp_limit.has_value()\n ? static_cast<float*>(gemm1_clamp_limit.value().data_ptr())\n : nullptr;\n args->gemm2_weights = gemm2_weights.data_ptr();\n args->gemm2_weights_scale = gemm2_weights_scale.data_ptr();\n args->output1_scales_scalar = nullptr;\n args->output1_scales_gate_scalar = nullptr;\n args->output2_scales_scalar = nullptr;\n\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n max_num_padded_tokens_gemm1 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->intermediate_size,\n btg::dtypeGetNumBits(mDtypeAct));\n max_num_padded_tokens_gemm2 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->hidden_size,\n btg::dtypeGetNumBits(btg::Dtype::Bfloat16)); // Output is always BF16\n\n auto const gemm1_output_hidden = args->intermediate_size;\n gemm1_output = alloc_tensor({max_num_padded_tokens_gemm1, gemm1_output_hidden}, dl_bfloat16,\n hidden_states.device());\n\n // Allocate gemm2_output\n gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n // Setup workspace pointers\n workspace.hidden_states_scale_linear = nullptr; // MxInt4 doesn't use linear scale\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = nullptr;\n // Note: activation_output and activation_output_scale are set by the base class\n // prepare_moe_common() when gated activation is used\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n }\n\n private:\n TensorView gemm1_weights_scale;\n Optional<TensorView> gemm1_alpha;\n Optional<TensorView> gemm1_beta;\n Optional<TensorView> gemm1_clamp_limit;\n TensorView gemm2_weights_scale;\n int32_t max_num_padded_tokens_gemm1{};\n int32_t max_num_padded_tokens_gemm2{};\n\n public:\n static Array<Array<int64_t>> getValidConfigs(int64_t top_k, int64_t hidden_size,\n int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens) {\n Array<Array<int64_t>> valid_configs;\n\n std::vector<int32_t> tile_sizes(mSupportedTileNums.begin(), mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(tile_sizes, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n auto moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n btg::Dtype::Bfloat16, btg::Dtype::MxInt4,\n false, // useDeepSeekFp8\n tile_N, ActivationType::Swiglu,\n /*useShuffledMatrix*/ true, batchedGemm::gemm::MatrixLayout::BlockMajorK);\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n};\n\nclass FP4BlockScaleLauncher : public FusedMoeLauncher {\n public:\n static constexpr std::array<int32_t, 4> mBaseSupportedTileNums = {8, 16, 32, 64};\n\n static std::vector<int32_t> getSupportedTileNums(btg::Dtype dtype_act) {\n std::vector<int32_t> tiles(mBaseSupportedTileNums.begin(), mBaseSupportedTileNums.end());\n if (dtype_act != btg::Dtype::Bfloat16) {\n tiles.push_back(128);\n tiles.push_back(256);\n }\n return tiles;\n }\n\n FP4BlockScaleLauncher(\n Optional<TensorView> const& routing_logits, Optional<TensorView> const& routing_bias,\n TensorView const& hidden_states, Optional<TensorView> const& hidden_states_scale,\n TensorView const& gemm1_weights, TensorView const& gemm1_weights_scale,\n Optional<TensorView> const& gemm1_bias, Optional<TensorView> const& gemm1_alpha,\n Optional<TensorView> const& gemm1_beta, Optional<TensorView> const& gemm1_clamp_limit,\n TensorView const& gemm2_weights, TensorView const& gemm2_weights_scale,\n Optional<TensorView> const& gemm2_bias, Optional<TensorView> const& output1_scales_scalar,\n Optional<TensorView> const& output1_scales_gate_scalar,\n Optional<TensorView> const& output2_scales_scalar, TensorView const& expert_indices,\n TensorView const& expert_weights)\n : FusedMoeLauncher(routing_logits, routing_bias, hidden_states, gemm1_weights,\n output1_scales_scalar, output1_scales_gate_scalar, gemm2_weights,\n output2_scales_scalar),\n hidden_states_scale(hidden_states_scale),\n gemm1_weights_scale(gemm1_weights_scale),\n gemm1_bias(gemm1_bias),\n gemm1_alpha(gemm1_alpha),\n gemm1_beta(gemm1_beta),\n gemm1_clamp_limit(gemm1_clamp_limit),\n gemm2_weights_scale(gemm2_weights_scale),\n gemm2_bias(gemm2_bias),\n expert_indices(expert_indices),\n expert_weights(expert_weights) {}\n\n void init(std::unique_ptr<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>&& args,\n int64_t tile_tokens_dim, int64_t routing_method_type, bool use_shuffled_weight,\n int64_t weight_layout, ActivationType activation_type, btg::Dtype dtype_act,\n btg::Dtype dtype_weights) {\n // Set data types\n args->mDtypeElt = dtype_act;\n args->mDtypeOut = btg::Dtype::Bfloat16; // Output is always BF16 for FP4\n args->mUseDeepSeekFp8 = false; // FP4 doesn't use DeepSeek FP8\n\n mDtypeAct = dtype_act;\n mDtypeWeights = dtype_weights;\n\n FusedMoeLauncher::init_common(std::move(args), tile_tokens_dim, routing_method_type,\n use_shuffled_weight, weight_layout, activation_type);\n }\n\n void check_routing() const override {\n // First call base class common routing checks\n FusedMoeLauncher::check_routing_common();\n }\n\n void prepare_routing() override {\n num_tokens_per_expert = alloc_tensor({args->num_experts}, dl_int32, hidden_states.device());\n int32_t max_num_padded_tokens =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::getMaxPermutedPaddedCount(\n args->num_tokens, args->top_k, args->num_experts, tile_tokens_dim);\n\n total_num_padded_tokens = alloc_tensor({1}, dl_int32, hidden_states.device());\n expanded_idx_to_permuted_idx =\n alloc_tensor({args->num_tokens * args->top_k}, dl_int32, hidden_states.device());\n permuted_idx_to_token_idx =\n alloc_tensor({max_num_padded_tokens}, dl_int32, hidden_states.device());\n\n int64_t const size_of_expert_count_histogram = std::max(args->num_experts * 2, 256 * 2);\n expert_count_histogram =\n alloc_tensor({size_of_expert_count_histogram}, dl_int32, hidden_states.device());\n\n int32_t max_num_ctas = tensorrt_llm::kernels::trtllmgen_moe::Routing::getMaxNumCtasInBatchDim(\n args->num_tokens, args->top_k, args->num_experts, tile_tokens_dim);\n cta_idx_xy_to_batch_idx = alloc_tensor({max_num_ctas}, dl_int32, hidden_states.device());\n cta_idx_xy_to_mn_limit = alloc_tensor({max_num_ctas}, dl_int32, hidden_states.device());\n num_non_exiting_ctas = alloc_tensor({1}, dl_int32, hidden_states.device());\n\n workspace.total_num_padded_tokens = static_cast<int*>(total_num_padded_tokens.data_ptr());\n workspace.total_max_padded_tokens = max_num_padded_tokens;\n workspace.ProjUpTileN = tile_tokens_dim;\n workspace.routing_expert_indexes =\n static_cast<int*>(const_cast<void*>(expert_indices.data_ptr()));\n workspace.expert_weights = const_cast<void*>(expert_weights.data_ptr());\n workspace.permuted_idx_size = static_cast<int*>(total_num_padded_tokens.data_ptr());\n workspace.expanded_idx_to_permuted_idx =\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr());\n workspace.permuted_idx_to_token_idx = static_cast<int*>(permuted_idx_to_token_idx.data_ptr());\n workspace.cta_idx_xy_to_batch_idx = static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr());\n workspace.cta_idx_xy_to_mn_limit = static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr());\n workspace.num_non_exiting_ctas = static_cast<int*>(num_non_exiting_ctas.data_ptr());\n\n args->mDtypeElt = mDtypeAct;\n auto routing_bias_dtype = routing_bias.has_value() ? routing_bias.value().dtype() : dl_bfloat16;\n mRoutingBiasDtype = routing_bias_dtype == dl_bfloat16 ? btg::Dtype::Bfloat16 : btg::Dtype::Fp32;\n }\n\n void check_moe() const override {\n TVM_FFI_ICHECK(mDtypeAct == btg::Dtype::E2m1 || mDtypeAct == btg::Dtype::Bfloat16 ||\n mDtypeAct == btg::Dtype::E4m3 || mDtypeAct == btg::Dtype::MxE4m3)\n << \"Only E2m1, Bfloat16, MxE4m3 and E4m3 are supported by Fp4 block scale MoE\";\n\n if (mDtypeAct == btg::Dtype::E2m1) {\n TVM_FFI_ICHECK(mDtypeWeights == btg::Dtype::E2m1)\n << \"Only E2m1 and MxE2m1 are supported by block scale MoE with E2m1 activation\";\n TVM_FFI_ICHECK(hidden_states_scale.has_value())\n << \"hidden_states_scale is required for E2m1 activation\";\n TVM_FFI_ICHECK(output1_scales_scalar.has_value())\n << \"output1_scales_scalar is required for E2m1 activation\";\n TVM_FFI_ICHECK(output1_scales_gate_scalar.has_value())\n << \"output1_scales_gate_scalar is required for E2m1 activation\";\n TVM_FFI_ICHECK(output2_scales_scalar.has_value())\n << \"output2_scales_scalar is required for E2m1 activation\";\n } else if (mDtypeAct == btg::Dtype::Bfloat16 || mDtypeAct == btg::Dtype::E4m3 ||\n mDtypeAct == btg::Dtype::MxE4m3) {\n TVM_FFI_ICHECK(mDtypeWeights == btg::Dtype::MxE2m1)\n << \"Only MxE2m1 weights are supported by block scale MoE with Bfloat16, E4m3 or \"\n \"MxE4m3 activation\";\n }\n\n if (mDtypeAct == btg::Dtype::E4m3) {\n TVM_FFI_ICHECK(output1_scales_scalar.has_value())\n << \"output1_scales_scalar is required for E4m3 activation\";\n TVM_FFI_ICHECK(output1_scales_gate_scalar.has_value())\n << \"output1_scales_gate_scalar is required for E4m3 activation\";\n TVM_FFI_ICHECK(output2_scales_scalar.has_value())\n << \"output2_scales_scalar is required for E4m3 activation\";\n }\n\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_uint8) << \"gemm1_weights must be byte.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_float8_e4m3fn)\n << \"gemm1_weights_scale must be fp8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_uint8) << \"gemm2_weights must be byte.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_float8_e4m3fn)\n << \"gemm2_weights_scale must be fp8.\";\n }\n\n void prepare_moe(int64_t& moe_tactic) override {\n args->hidden_states = hidden_states.data_ptr();\n args->hidden_states_scale =\n hidden_states_scale.has_value() ? hidden_states_scale.value().data_ptr() : nullptr;\n args->gemm1_weights = gemm1_weights.data_ptr();\n args->gemm1_weights_scale = gemm1_weights_scale.data_ptr();\n args->gemm1_bias =\n gemm1_bias.has_value() ? static_cast<float*>(gemm1_bias.value().data_ptr()) : nullptr;\n args->gemm1_alpha =\n gemm1_alpha.has_value() ? static_cast<float*>(gemm1_alpha.value().data_ptr()) : nullptr;\n args->gemm1_beta =\n gemm1_beta.has_value() ? static_cast<float*>(gemm1_beta.value().data_ptr()) : nullptr;\n args->gemm1_clamp_limit = gemm1_clamp_limit.has_value()\n ? static_cast<float*>(gemm1_clamp_limit.value().data_ptr())\n : nullptr;\n args->gemm2_weights = gemm2_weights.data_ptr();\n args->gemm2_weights_scale = gemm2_weights_scale.data_ptr();\n args->gemm2_bias =\n gemm2_bias.has_value() ? static_cast<float*>(gemm2_bias.value().data_ptr()) : nullptr;\n args->output1_scales_scalar =\n output1_scales_scalar.has_value()\n ? static_cast<float*>(output1_scales_scalar.value().data_ptr())\n : nullptr;\n args->output1_scales_gate_scalar =\n output1_scales_gate_scalar.has_value()\n ? static_cast<float*>(output1_scales_gate_scalar.value().data_ptr())\n : nullptr;\n args->output2_scales_scalar =\n output2_scales_scalar.has_value()\n ? static_cast<float*>(output2_scales_scalar.value().data_ptr())\n : nullptr;\n\n FusedMoeLauncher::prepare_moe_common(moe_tactic);\n\n auto const sf_vec_size = mDtypeWeights == btg::Dtype::MxE2m1 ? 32 : 16;\n\n max_num_padded_tokens_gemm1 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->intermediate_size,\n btg::dtypeGetNumBits(mDtypeAct));\n max_num_padded_tokens_gemm2 =\n tensorrt_llm::kernels::trtllmgen_moe::Routing::maybeGetMinTokenCount(\n workspace.total_max_padded_tokens, args->hidden_size,\n btg::dtypeGetNumBits(btg::Dtype::Bfloat16)); // Output is always BF16\n\n auto const gemm1_output_hidden =\n mDtypeAct == btg::Dtype::E2m1 ? args->intermediate_size / 2 : args->intermediate_size;\n gemm1_output = alloc_tensor({max_num_padded_tokens_gemm1, gemm1_output_hidden},\n mDtypeAct == btg::Dtype::Bfloat16 ? dl_bfloat16 : dl_uint8,\n hidden_states.device());\n\n if (mDtypeAct == btg::Dtype::E2m1 || mDtypeAct == btg::Dtype::MxE4m3) {\n int64_t sf_size = tensorrt_llm::computeSwizzledLayoutSFSize(\n max_num_padded_tokens_gemm1, args->intermediate_size / sf_vec_size);\n gemm1_output_scale = alloc_tensor({sf_size}, dl_uint8, hidden_states.device());\n }\n\n // Allocate gemm2_output\n gemm2_output = alloc_tensor({max_num_padded_tokens_gemm2, args->hidden_size}, dl_bfloat16,\n hidden_states.device());\n\n // Setup workspace pointers\n workspace.hidden_states_scale_linear = nullptr; // FP4 doesn't use linear scale\n workspace.gemm1_output = gemm1_output.data_ptr();\n workspace.gemm1_output_scale = gemm1_output_scale.has_value()\n ? static_cast<float*>(gemm1_output_scale.value().data_ptr())\n : nullptr;\n // Note: activation_output and activation_output_scale are set by the base class\n // prepare_moe_common() when gated activation is used\n workspace.gemm2_output = gemm2_output.data_ptr();\n workspace.gemm2_output_scale = nullptr;\n }\n\n private:\n Optional<TensorView> hidden_states_scale;\n TensorView gemm1_weights_scale;\n Optional<TensorView> gemm1_bias;\n Optional<TensorView> gemm1_alpha;\n Optional<TensorView> gemm1_beta;\n Optional<TensorView> gemm1_clamp_limit;\n TensorView gemm2_weights_scale;\n Optional<TensorView> gemm2_bias;\n int32_t max_num_padded_tokens_gemm1{};\n int32_t max_num_padded_tokens_gemm2{};\n Optional<Tensor> gemm1_output_scale;\n TensorView expert_indices;\n TensorView expert_weights;\n\n public:\n Array<Tensor> run(int64_t moe_tactic, bool enable_pdl = true,\n bool use_routing_scales_on_input = false,\n bool use_deep_seek_fp8 = false) override {\n check_routing();\n prepare_routing();\n\n // Execute routing\n tensorrt_llm::kernels::trtllmgen_moe::Routing::Runner routing_runner(tile_tokens_dim);\n cudaStream_t routing_stream = get_stream(hidden_states.device());\n\n routing_runner.run(\n args->routing_logits, args->routing_bias, args->num_tokens, args->num_experts, args->top_k,\n args->n_group, args->topk_group, args->local_expert_offset, args->local_num_experts,\n args->routed_scaling_factor, static_cast<int*>(expert_indices.data_ptr()),\n static_cast<int*>(expert_count_histogram.data_ptr()),\n static_cast<int*>(total_num_padded_tokens.data_ptr()),\n static_cast<int*>(expanded_idx_to_permuted_idx.data_ptr()),\n nullptr /*permuted_idx_to_expanded_idx.data_ptr()*/,\n static_cast<int*>(permuted_idx_to_token_idx.data_ptr()), expert_weights.data_ptr(),\n static_cast<int*>(num_tokens_per_expert.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_batch_idx.data_ptr()),\n static_cast<int*>(cta_idx_xy_to_mn_limit.data_ptr()),\n static_cast<int*>(num_non_exiting_ctas.data_ptr()), args->mDtypeElt, mRoutingBiasDtype,\n use_routing_scales_on_input, use_deep_seek_fp8,\n static_cast<RoutingMethodType>(routing_method_type), routing_stream);\n\n check_moe();\n prepare_moe(moe_tactic);\n\n cudaStream_t moe_stream = get_stream(hidden_states.device());\n moe_runner->run(*args, workspace, hidden_states.device().device_id, moe_stream, moe_tactic,\n enable_pdl);\n\n // Match original FP4 behavior for return values\n if (args->do_finalize) {\n return {output};\n }\n return {gemm2_output, FusedMoeLauncher::expert_weights, expanded_idx_to_permuted_idx};\n }\n\n static Array<Array<int64_t>> getValidConfigs(int64_t top_k, int64_t hidden_size,\n int64_t intermediate_size, int64_t num_local_experts,\n int64_t num_tokens, int64_t act_type,\n btg::Dtype dtype_act, btg::Dtype dtype_weights) {\n Array<Array<int64_t>> valid_configs;\n\n std::vector<int32_t> tile_sizes = getSupportedTileNums(dtype_act);\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(tile_sizes, num_tokens, top_k, num_local_experts);\n\n for (int32_t tile_N : selected_tile_nums) {\n auto moe_runner = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::Runner>(\n dtype_act, dtype_weights,\n false, // useDeepSeekFp8\n tile_N, static_cast<ActivationType>(act_type),\n /*useShuffledMatrix*/ true); // FP4 uses shuffled weights\n\n auto cfgs = moe_runner->getValidConfigIndices(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n\n for (auto cfg : cfgs) {\n valid_configs.push_back({tile_N, cfg});\n }\n }\n\n return valid_configs;\n }\n};\n\nArray<Tensor> trtllm_bf16_moe(Optional<TensorView> const& routing_logits,\n Optional<TensorView> const& routing_bias,\n TensorView const& expert_indices, TensorView const& expert_weights,\n TensorView const& hidden_states, TensorView const& gemm1_weights,\n TensorView const& gemm2_weights, TensorView output,\n int64_t num_experts, int64_t top_k, Optional<int64_t> n_group,\n Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts,\n Optional<double> routed_scaling_factor, int64_t routing_method_type,\n bool use_shuffled_weight, int64_t weight_layout, bool do_finalize,\n bool enable_pdl, Array<int64_t> moe_tactic) {\n // Just some basic type validation first and leave more checks to the launcher\n if (routing_logits.has_value()) {\n TVM_FFI_ICHECK(routing_logits.value().dtype() == dl_float32 ||\n routing_logits.value().dtype() == dl_bfloat16)\n << \"BF16 MoE: routing_logits must be bfloat16 or float.\";\n }\n TVM_FFI_ICHECK_EQ(hidden_states.dtype(), dl_bfloat16)\n << \"BF16 MoE: hidden_states must be bfloat16.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_bfloat16)\n << \"BF16 MoE: gemm1_weights must be bfloat16.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_bfloat16)\n << \"BF16 MoE: gemm2_weights must be bfloat16.\";\n\n auto const num_tokens = hidden_states.size(0);\n auto const hidden_size = hidden_states.size(1);\n\n // Calculate supported tile sizes\n std::vector<int32_t> mSupportedTileN(Bf16MoeLauncher::mSupportedTileNums.begin(),\n Bf16MoeLauncher::mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(mSupportedTileN, num_tokens, top_k, local_num_experts);\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<Bf16MoeLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : selected_tile_nums) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n args->hidden_size = hidden_size;\n args->hidden_size_output = args->hidden_size;\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<Bf16MoeLauncher>(routing_logits, routing_bias, expert_indices,\n expert_weights, hidden_states, gemm1_weights,\n gemm2_weights);\n launcher->init(std::move(args), curr_tile_N, routing_method_type, use_shuffled_weight,\n weight_layout);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n // Extract tile_N and config from moe_tactic\n int64_t tile_N = moe_tactic[0];\n int64_t config = moe_tactic[1];\n\n // Handle default case\n if (tile_N == -1 || config == -1) {\n tile_N = *selected_tile_nums.begin();\n }\n\n // Get the launcher for the selected tile_N\n auto& selected_launcher = launchers_map.at(tile_N);\n\n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl);\n}\n\nArray<Tensor> trtllm_fp8_per_tensor_scale_moe(\n TensorView routing_logits, Optional<TensorView> routing_bias, TensorView hidden_states,\n TensorView gemm1_weights, TensorView output1_scales_scalar,\n TensorView output1_scales_gate_scalar, TensorView gemm2_weights,\n TensorView output2_scales_scalar, TensorView output, int64_t num_experts, int64_t top_k,\n Optional<int64_t> n_group, Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts, Optional<double> routed_scaling_factor,\n bool use_routing_scales_on_input, int64_t routing_method_type, bool do_finalize,\n bool enable_pdl, Array<int64_t> config_index, int64_t activation_type) {\n // Basic type validation\n auto dtype = hidden_states.dtype();\n auto activation = static_cast<ActivationType>(activation_type);\n if (use_routing_scales_on_input) {\n TVM_FFI_ICHECK_EQ(routing_logits.dtype(), dl_bfloat16) << \"routing_logits must be bfloat16.\";\n } else if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK_EQ(routing_logits.dtype(), dl_float32) << \"routing_logits must be float.\";\n } else {\n TVM_FFI_ICHECK_EQ(routing_logits.dtype(), dl_bfloat16) << \"routing_logits must be bfloat16.\";\n }\n TVM_FFI_ICHECK(dtype == dl_float8_e4m3fn || dtype == dl_float16 || dtype == dl_bfloat16)\n << \"FP8 MoE: hidden_states must be float8_e4m3fn, float16, or bfloat16.\";\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 MoE: gemm1_weights must be float8_e4m3fn.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 MoE: gemm2_weights must be float8_e4m3fn.\";\n TVM_FFI_ICHECK_EQ(output1_scales_scalar.dtype(), dl_float32)\n << \"FP8 MoE: output1_scales_scalar must be float32.\";\n TVM_FFI_ICHECK_EQ(output1_scales_gate_scalar.dtype(), dl_float32)\n << \"FP8 MoE: output1_scales_gate_scalar must be float32.\";\n TVM_FFI_ICHECK_EQ(output2_scales_scalar.dtype(), dl_float32)\n << \"FP8 MoE: output2_scales_scalar must be float32.\";\n\n auto const num_tokens = hidden_states.size(0);\n auto const hidden_size = hidden_states.size(1);\n\n // Use default values that match the original function behavior\n bool use_shuffled_weight = true; // Original uses /*useShuffledMatrix*/ true\n int64_t weight_layout = 0; // Default to MajorK\n\n // Calculate supported tile sizes\n std::vector<int32_t> mSupportedTileN(Fp8PerTensorLauncher::mSupportedTileNums.begin(),\n Fp8PerTensorLauncher::mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(mSupportedTileN, num_tokens, top_k, local_num_experts);\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<Fp8PerTensorLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : selected_tile_nums) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n args->hidden_size = hidden_size;\n args->hidden_size_output = args->hidden_size;\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<Fp8PerTensorLauncher>(\n routing_logits, routing_bias, hidden_states, gemm1_weights, output1_scales_scalar,\n output1_scales_gate_scalar, gemm2_weights, output2_scales_scalar);\n launcher->init(std::move(args), curr_tile_N, routing_method_type, use_shuffled_weight,\n weight_layout, use_routing_scales_on_input, activation);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n // Extract tile_N and config from config_index\n int64_t tile_N = config_index[0];\n int64_t config = config_index[1];\n\n // Handle default case\n if (tile_N == -1 || config == -1) {\n tile_N = *selected_tile_nums.begin();\n }\n\n // Get the launcher for the selected tile_N\n auto& selected_launcher = launchers_map.at(tile_N);\n\n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl, use_routing_scales_on_input);\n}\n\nArray<Tensor> trtllm_fp8_block_scale_moe(\n Optional<TensorView> routing_logits, TensorView expert_indices, TensorView expert_weights,\n Optional<TensorView> routing_bias, TensorView hidden_states, TensorView hidden_states_scale,\n TensorView gemm1_weights, TensorView gemm1_weights_scale, TensorView gemm2_weights,\n TensorView gemm2_weights_scale, TensorView output, int64_t num_experts, int64_t top_k,\n Optional<int64_t> n_group, Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts, Optional<double> routed_scaling_factor,\n int64_t routing_method_type, bool use_shuffled_weight, int64_t weight_layout, bool do_finalize,\n bool enable_pdl, Array<int64_t> config_index, Fp8QuantizationType quantization_type,\n int64_t act_type) {\n auto activation_type = validateAndCastActivationType(act_type);\n // DeepSeekFp8 currently uses a TRTLLM runner that hardwires Swiglu activation semantics.\n // Fail for any other activation to avoid silently running incorrect activation behavior.\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8 &&\n activation_type != ActivationType::Swiglu) {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"DeepSeekFp8 only supports ActivationType::Swiglu in this runner path. \"\n << \"Received activation_type=\" << static_cast<int>(activation_type);\n }\n\n // Basic type validation\n auto dtype = hidden_states.dtype();\n\n // Either routing_logits or expert_indices must be provided\n // expert_indices is a packed tensor: (expert_id << 16) | (weight_bf16.view(int16))\n bool use_routing_logits = routing_logits.has_value();\n // Check ndim==2 and size>0 because empty placeholder tensors may have non-null data_ptr\n bool use_precomputed_routing = expert_indices.ndim() == 2 && expert_indices.size(0) > 0;\n\n TVM_FFI_ICHECK(use_routing_logits || use_precomputed_routing)\n << \"Either routing_logits or expert_indices must be provided.\";\n\n if (use_routing_logits) {\n if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK_EQ(routing_logits.value().dtype(), dl_float32)\n << \"routing_logits must be float.\";\n } else {\n TVM_FFI_ICHECK_EQ(routing_logits.value().dtype(), dl_bfloat16)\n << \"routing_logits must be bfloat16.\";\n }\n }\n TVM_FFI_ICHECK(dtype == dl_float16 || dtype == dl_bfloat16 || dtype == dl_float8_e4m3fn)\n << \"FP8 block scale MoE: hidden_states must be fp16, bf16, or fp8.\";\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(hidden_states_scale.dtype(), dl_float32)\n << \"FP8 block scale MoE: hidden_states_scale must be float32.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK_EQ(hidden_states_scale.dtype(), dl_uint8)\n << \"FP8 block scale MoE: hidden_states_scale must be uint8.\";\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n TVM_FFI_ICHECK_EQ(gemm1_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 block scale MoE: gemm1_weights must be fp8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights.dtype(), dl_float8_e4m3fn)\n << \"FP8 block scale MoE: gemm2_weights must be fp8.\";\n if (quantization_type == Fp8QuantizationType::DeepSeekFp8) {\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_float32)\n << \"FP8 block scale MoE: gemm1_weights_scale must be float32.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_float32)\n << \"FP8 block scale MoE: gemm2_weights_scale must be float32.\";\n } else if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK_EQ(gemm1_weights_scale.dtype(), dl_uint8)\n << \"FP8 block scale MoE: gemm1_weights_scale must be uint8.\";\n TVM_FFI_ICHECK_EQ(gemm2_weights_scale.dtype(), dl_uint8)\n << \"FP8 block scale MoE: gemm2_weights_scale must be uint8.\";\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"trtllm_fp8_block_scale_moe only supports DeepSeekFp8 or MxFp8.\";\n }\n\n if (quantization_type == Fp8QuantizationType::MxFp8) {\n TVM_FFI_ICHECK(use_shuffled_weight) << \"use_shuffled_weight must be true for MxFp8.\";\n TVM_FFI_ICHECK(weight_layout == 0) << \"weight_layout must be 0 for MxFp8.\";\n }\n\n auto const num_tokens = hidden_states.size(0);\n auto const hidden_size = hidden_states.size(1);\n\n auto supported_tile_nums = Fp8BlockScaleLauncher::getSupportedTileNums(quantization_type);\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(supported_tile_nums, num_tokens, top_k, local_num_experts);\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<Fp8BlockScaleLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : selected_tile_nums) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n args->hidden_size = hidden_size;\n args->hidden_size_output = args->hidden_size;\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<Fp8BlockScaleLauncher>(\n routing_logits, routing_bias, hidden_states, hidden_states_scale, gemm1_weights,\n gemm1_weights_scale, gemm2_weights, gemm2_weights_scale, expert_indices, expert_weights,\n quantization_type);\n launcher->init(std::move(args), curr_tile_N, routing_method_type, use_shuffled_weight,\n weight_layout, activation_type);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n // Extract tile_N and config from config_index\n int64_t tile_N = config_index[0];\n int64_t config = config_index[1];\n\n // Handle default case\n if (tile_N == -1 || config == -1) {\n tile_N = *selected_tile_nums.begin();\n }\n\n // Get the launcher for the selected tile_N\n auto& selected_launcher = launchers_map.at(tile_N);\n\n // Run the launcher with DeepSeek FP8 enabled - it will create its own runner internally\n return selected_launcher->run(\n config, enable_pdl, false /* use_routing_scales_on_input */,\n quantization_type == Fp8QuantizationType::DeepSeekFp8 /* use_deep_seek_fp8 */);\n}\n\nArray<Tensor> trtllm_fp4_block_scale_moe(\n Optional<TensorView> routing_logits, TensorView expert_indices, TensorView expert_weights,\n Optional<TensorView> routing_bias, TensorView hidden_states,\n Optional<TensorView> hidden_states_scale, TensorView gemm1_weights,\n TensorView gemm1_weights_scale, Optional<TensorView> gemm1_bias,\n Optional<TensorView> gemm1_alpha, Optional<TensorView> gemm1_beta,\n Optional<TensorView> gemm1_clamp_limit, TensorView gemm2_weights,\n TensorView gemm2_weights_scale, Optional<TensorView> gemm2_bias,\n Optional<TensorView> output1_scales_scalar, Optional<TensorView> output1_scales_gate_scalar,\n Optional<TensorView> output2_scales_scalar, int64_t num_experts, int64_t top_k,\n Optional<int64_t> n_group, Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts, Optional<double> routed_scaling_factor,\n int64_t routing_method_type, bool do_finalize, bool enable_pdl, int64_t act_type,\n TensorView output, Array<int64_t> config_index) {\n // Determine data types based on input format\n int const num_tokens = hidden_states.size(0);\n int hidden_size = hidden_states.size(1);\n if (hidden_states.dtype() == dl_uint8) hidden_size *= 2;\n\n int hidden_states_scale_vec_size = -1;\n if (hidden_states_scale.has_value()) {\n hidden_states_scale_vec_size = (num_tokens * hidden_size) / hidden_states_scale.value().numel();\n }\n int64_t intermediate_size_factor =\n isGatedActivation(static_cast<ActivationType>(act_type)) ? 2 : 1;\n int weight_scale_vec_size =\n (local_num_experts * intermediate_size * intermediate_size_factor * hidden_size) /\n gemm1_weights_scale.numel();\n\n TVM_FFI_ICHECK(weight_scale_vec_size == 16 || weight_scale_vec_size == 32)\n << \"unsupported weight_scale_vec_size.\";\n auto mDtypeWeights = weight_scale_vec_size == 16 ? btg::Dtype::E2m1 : btg::Dtype::MxE2m1;\n\n if (routing_logits.has_value()) {\n TVM_FFI_ICHECK(routing_logits.value().dtype() == dl_float32 ||\n routing_logits.value().dtype() == dl_bfloat16)\n << \"routing_logits must be float or bfloat16.\";\n TVM_FFI_ICHECK_EQ(routing_logits.value().ndim(), 2) << \"routing_logits must be 2D.\";\n TVM_FFI_ICHECK_EQ(routing_logits.value().size(1), num_experts)\n << \"routing_logits has incorrect shape.\";\n if (static_cast<RoutingMethodType>(routing_method_type) == RoutingMethodType::DeepSeekV3) {\n TVM_FFI_ICHECK_EQ(routing_logits.value().dtype(), dl_float32)\n << \"routing_logits must be float.\";\n }\n }\n if (routing_bias.has_value()) {\n TVM_FFI_ICHECK(routing_bias.value().dtype() == dl_bfloat16 ||\n routing_bias.value().dtype() == dl_float32)\n << \"routing_bias must be bfloat16 or float.\";\n\n TVM_FFI_ICHECK_EQ(routing_bias.value().ndim(), 1) << \"routing_bias must be 1D.\";\n TVM_FFI_ICHECK_EQ(routing_bias.value().size(0), num_experts)\n << \"routing_bias has incorrect shape.\";\n }\n\n // Determine activation type\n TVM_FFI_ICHECK(gemm1_weights.dtype() == dl_uint8 && gemm2_weights.dtype() == dl_uint8)\n << \"weights must be fp4 packed in uint8.\";\n TVM_FFI_ICHECK(hidden_states.dtype() == dl_uint8 || hidden_states.dtype() == dl_bfloat16 ||\n hidden_states.dtype() == dl_float8_e4m3fn)\n << \"hidden_states must be bf16, fp8 or uint8 (packed fp4).\";\n\n auto mDtypeAct = btg::Dtype::Bfloat16;\n if (hidden_states.dtype() == dl_uint8) {\n TVM_FFI_ICHECK(hidden_states_scale.has_value() &&\n hidden_states_scale.value().dtype() == dl_float8_e4m3fn)\n << \"hidden_states_scale must be provided for fp4 activation.\";\n if (hidden_states_scale_vec_size == 16) {\n mDtypeAct = btg::Dtype::E2m1;\n } else if (hidden_states_scale_vec_size == 32) {\n mDtypeAct = btg::Dtype::MxE2m1;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported hidden state scale shape.\";\n }\n } else if (hidden_states.dtype() == dl_float8_e4m3fn) {\n if (hidden_states_scale.has_value()) {\n if (hidden_states_scale_vec_size == 32) {\n mDtypeAct = btg::Dtype::MxE4m3;\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported hidden state scale shape.\";\n }\n } else {\n mDtypeAct = btg::Dtype::E4m3;\n }\n }\n\n // Determine supported tile sizes\n std::vector<int32_t> mSupportedTileN = FP4BlockScaleLauncher::getSupportedTileNums(mDtypeAct);\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(mSupportedTileN, num_tokens, top_k, local_num_experts);\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<FP4BlockScaleLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : selected_tile_nums) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n // For E2m1, hidden_size is already multiplied by 2 above, so use it directly\n args->hidden_size = hidden_size;\n args->hidden_size_output = output.size(1);\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<FP4BlockScaleLauncher>(\n routing_logits, routing_bias, hidden_states, hidden_states_scale, gemm1_weights,\n gemm1_weights_scale, gemm1_bias, gemm1_alpha, gemm1_beta, gemm1_clamp_limit, gemm2_weights,\n gemm2_weights_scale, gemm2_bias, output1_scales_scalar, output1_scales_gate_scalar,\n output2_scales_scalar, expert_indices, expert_weights);\n launcher->init(std::move(args), curr_tile_N, routing_method_type, /*use_shuffled_weight=*/true,\n /*weight_layout=*/0, static_cast<ActivationType>(act_type), mDtypeAct,\n mDtypeWeights);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n // Extract tile_N and config from config_index\n int64_t tile_N = config_index[0];\n int64_t config = config_index[1];\n\n // Handle default case\n if (tile_N == -1 || config == -1) {\n tile_N = *selected_tile_nums.begin();\n config = -1; // Let the runner choose default\n }\n\n // Get the launcher for the selected tile_N\n auto& selected_launcher = launchers_map.at(tile_N);\n\n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl);\n}\n\nArray<Tensor> trtllm_mxint4_block_scale_moe(\n TensorView routing_logits, Optional<TensorView> routing_bias, TensorView hidden_states,\n TensorView gemm1_weights, TensorView gemm1_weights_scale, Optional<TensorView> gemm1_alpha,\n Optional<TensorView> gemm1_beta, Optional<TensorView> gemm1_clamp_limit,\n TensorView gemm2_weights, TensorView gemm2_weights_scale, int64_t num_experts, int64_t top_k,\n Optional<int64_t> n_group, Optional<int64_t> topk_group, int64_t intermediate_size,\n int64_t local_expert_offset, int64_t local_num_experts, Optional<double> routed_scaling_factor,\n int64_t routing_method_type, bool do_finalize, bool enable_pdl, TensorView output,\n Array<int64_t> config_index) {\n // Determine data types based on input format\n int const num_tokens = hidden_states.size(0);\n int hidden_size = hidden_states.size(1);\n // Just some basic type validation first and leave more checks to the launcher\n\n int weight_scale_vec_size =\n (local_num_experts * intermediate_size * 2 * hidden_size) / gemm1_weights_scale.numel();\n\n TVM_FFI_ICHECK(weight_scale_vec_size == 32) << \"unsupported weight_scale_vec_size.\";\n\n TVM_FFI_ICHECK(routing_logits.dtype() == dl_float32 || routing_logits.dtype() == dl_bfloat16)\n << \"routing_logits must be float or bfloat16.\";\n TVM_FFI_ICHECK_EQ(routing_logits.ndim(), 2) << \"routing_logits must be 2D.\";\n TVM_FFI_ICHECK_EQ(routing_logits.size(1), num_experts) << \"routing_logits has incorrect shape.\";\n if (routing_bias.has_value()) {\n TVM_FFI_ICHECK(routing_bias.value().dtype() == dl_bfloat16) << \"routing_bias must be bfloat16.\";\n TVM_FFI_ICHECK_EQ(routing_bias.value().ndim(), 1) << \"routing_bias must be 1D.\";\n TVM_FFI_ICHECK_EQ(routing_bias.value().size(0), num_experts)\n << \"routing_bias has incorrect shape.\";\n }\n\n // Determine activation type\n TVM_FFI_ICHECK(gemm1_weights.dtype() == dl_uint8 && gemm2_weights.dtype() == dl_uint8)\n << \"weights must be int4 packed in uint8.\";\n TVM_FFI_ICHECK(hidden_states.dtype() == dl_bfloat16) << \"hidden_states must be bf16.\";\n\n // Determine supported tile sizes\n std::vector<int32_t> mSupportedTileN(MxInt4BlockScaleLauncher::mSupportedTileNums.begin(),\n MxInt4BlockScaleLauncher::mSupportedTileNums.end());\n std::set<int32_t> selected_tile_nums =\n computeSelectedTileN(mSupportedTileN, num_tokens, top_k, local_num_experts);\n\n // Create a map of launchers for each tile size\n std::unordered_map<int32_t, std::unique_ptr<MxInt4BlockScaleLauncher>> launchers_map;\n\n for (int32_t curr_tile_N : selected_tile_nums) {\n // Create MoE arguments for this launcher\n auto args = std::make_unique<tensorrt_llm::kernels::trtllmgen_moe::MoE::MoERunnerArgs>();\n args->num_tokens = num_tokens;\n args->num_experts = num_experts;\n // For E2m1, hidden_size is already multiplied by 2 above, so use it directly\n args->hidden_size = hidden_size;\n args->hidden_size_output = args->hidden_size;\n args->top_k = top_k;\n args->n_group = n_group.value_or(0);\n args->topk_group = topk_group.value_or(0);\n args->local_expert_offset = local_expert_offset;\n args->local_num_experts = local_num_experts;\n args->intermediate_size = intermediate_size;\n args->routed_scaling_factor = routed_scaling_factor.value_or(1.0);\n args->do_finalize = do_finalize;\n args->output = output.data_ptr();\n args->output_scale = nullptr;\n\n // Create and initialize launcher for this tile size\n auto launcher = std::make_unique<MxInt4BlockScaleLauncher>(\n routing_logits, routing_bias, hidden_states, gemm1_weights, gemm1_weights_scale,\n gemm1_alpha, gemm1_beta, gemm1_clamp_limit, gemm2_weights, gemm2_weights_scale);\n launcher->init(std::move(args), curr_tile_N, routing_method_type);\n\n launchers_map[curr_tile_N] = std::move(launcher);\n }\n\n // Extract tile_N and config from config_index\n int64_t tile_N = config_index[0];\n int64_t config = config_index[1];\n\n // Handle default case\n if (tile_N == -1 || config == -1) {\n tile_N = *selected_tile_nums.begin();\n config = -1; // Let the runner choose default\n }\n\n // Get the launcher for the selected tile_N\n auto& selected_launcher = launchers_map.at(tile_N);\n\n // Run the launcher - it will create its own runner internally\n return selected_launcher->run(config, enable_pdl);\n}\n\nArray<Array<int64_t>> trtllm_get_valid_moe_configs(\n int64_t const dtype_act_, int64_t const dtype_weights_, Fp8QuantizationType quantization_type,\n int64_t const top_k, int64_t const hidden_size, int64_t const intermediate_size,\n int64_t const num_local_experts, int64_t const act_type, bool const use_shuffled_weight,\n int64_t const weight_layout, int64_t const num_tokens) {\n auto activation_type = validateAndCastActivationType(act_type);\n auto dtype_act = static_cast<btg::Dtype>(dtype_act_);\n auto dtype_weights = static_cast<btg::Dtype>(dtype_weights_);\n\n if (dtype_act == btg::Dtype::Bfloat16 && dtype_weights == btg::Dtype::MxInt4) {\n // MxInt4 MoE\n return MxInt4BlockScaleLauncher::getValidConfigs(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens);\n }\n if (dtype_act == btg::Dtype::Bfloat16 && dtype_weights == btg::Dtype::Bfloat16) {\n // BF16 MoE\n return Bf16MoeLauncher::getValidConfigs(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens, act_type,\n use_shuffled_weight, weight_layout);\n\n } else if (quantization_type == Fp8QuantizationType::DeepSeekFp8 &&\n dtype_act == btg::Dtype::E4m3 && dtype_weights == btg::Dtype::E4m3) {\n if (activation_type != ActivationType::Swiglu) {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"DeepSeekFp8 only supports ActivationType::Swiglu, \"\n << \"got act_type=\" << act_type << \".\";\n }\n // FP8 block scale (DeepSeek)\n return Fp8BlockScaleLauncher::getValidConfigs(\n top_k, hidden_size, intermediate_size, num_local_experts, num_tokens, use_shuffled_weight,\n weight_layout, dtype_act, dtype_weights, quantization_type, act_type);\n } else if (quantization_type == Fp8QuantizationType::MxFp8 && dtype_act == btg::Dtype::MxE4m3 &&\n dtype_weights == btg::Dtype::MxE4m3) {\n // FP8 block scale (MxFp8)\n return Fp8BlockScaleLauncher::getValidConfigs(\n top_k, hidden_size, intermediate_size, num_local_experts, num_tokens, use_shuffled_weight,\n weight_layout, dtype_act, dtype_weights, quantization_type, act_type);\n } else if ((quantization_type == Fp8QuantizationType::PerTensorFp8 ||\n quantization_type == Fp8QuantizationType::NoneFp8) &&\n dtype_weights == btg::Dtype::E4m3) {\n // FP8 per-tensor scale. NoneFp8 is kept for backward compatibility.\n if (!isGatedActivation(activation_type)) {\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"FP8 per-tensor currently supports gated activations only, \"\n << \"got act_type=\" << act_type << \".\";\n }\n return Fp8PerTensorLauncher::getValidConfigs(\n top_k, hidden_size, intermediate_size, num_local_experts, num_tokens, act_type,\n use_shuffled_weight, weight_layout, dtype_act, dtype_weights);\n } else if (dtype_weights == btg::Dtype::E2m1 || dtype_weights == btg::Dtype::MxE2m1) {\n // FP4 block scale\n return FP4BlockScaleLauncher::getValidConfigs(top_k, hidden_size, intermediate_size,\n num_local_experts, num_tokens, act_type,\n dtype_act, dtype_weights);\n }\n\n TVM_FFI_LOG_AND_THROW(NotImplementedError)\n << \"Unsupported data type combination for getValidConfigs: \"\n << \"dtype_act=\" << static_cast<int>(dtype_act)\n << \", dtype_weights=\" << static_cast<int>(dtype_weights)\n << \", quantization_type=\" << fp8QuantizationTypeToString(quantization_type);\n\n // Unreachable code - added to suppress compiler warning\n return Array<Array<int64_t>>();\n}\n\nnamespace trtllm_cubin_loader {\n#include <flashinfer/cubin_loader.h>\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_bf16_moe, trtllm_bf16_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_fp8_per_tensor_scale_moe, trtllm_fp8_per_tensor_scale_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_fp8_block_scale_moe, trtllm_fp8_block_scale_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_fp4_block_scale_moe, trtllm_fp4_block_scale_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_mxint4_block_scale_moe, trtllm_mxint4_block_scale_moe);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_get_valid_moe_configs, trtllm_get_valid_moe_configs);\n\n} // namespace flashinfer\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nIt fixes two autotuner related bugs:\n1. Revert back the autotuner fix that was reverted in https://github.com/flashinfer-ai/flashinfer/pull/2697\n2. Fix the issue that https://github.com/flashinfer-ai/flashinfer/pull/2697 revealed, which is trtllm fused MoE kernel launcher crash when it receives tileN that is supported but filtered out by `computeSelectedTileN`, by creating kernel launchers for all supported tileN values.\n\nThis PR continues the work in https://github.com/flashinfer-ai/flashinfer/pull/2695 by @danisereb to revert bugfix 1 and to fix bug 2.\n\nMore technical details:\n### Bug 1:\nWhen given num_tokens that isn't a power-of-2, the autotuner (python side) fails to find its appropriate entry in the autotuner cache, so it falls back to passing default, which means passing `[-1, -1]` as the `(tileN, tactic)` to the CPP.\nIt was fixed in [this PR](https://github.com/flashinfer-ai/flashinfer/pull/2617/changes#diff-1964ab957d8185d04b0d5f0cb02d0c7c0a3260ac0a6c573167af6875ab0b0e87L729-L734) but soon after merge, it was reverted [here](https://github.com/flashinfer-ai/flashinfer/pull/2697), as it exposed the next bug.\n\n### Bug 2 (exposed after fixing bug 1):\nCrash in fused MoE kernel launcher on forward pass on some values of num_tokens. The crash is at `launchers_map.at(tile_N)` in `trtllm_fused_moe_kernel_launcher.cu`. It happens because:\nThe python side of the autotuner profiles num_tokens that are power of 2, and each such value represents the range until the next power of 2.\ne.g.: The profile for the range `[2048, 4095]` is done on num_tokens=2048.\n\n`computeSelectedTileN` function in `trtllm_fused_moe_kernel_launcher.cu` reduces the set of supported tileN values (to reduce the autotuner's search space), by choosing specific values from the supported tileN sorted list, the values are: `roundUpToPowerOfTwo(num_tokens * topK / numExperts)`, its previous one, and its next 2 values (max value is 256). So values in the same range can get different sets of tileN values.\nFor example, on Nemotron 3 Super NVFP4:\n- `num_tokens=2048` -> `2048*22/512 = 88`, which rounds up to 128, so the tileN set is `(64, 128, 256)`\n- `num_tokens=3003` -> `3003*22/512 = 129.03`, which rounds up to 256, so the tileN set is `(128, 256)`\nIn case `tileN=64` was found to be the fastest on `num_tokens=2048` for range `[2048, 4095]`, when given `num_tokens=3003`, the python side would pass `[64, someTactic]` to the CPP, but for `num_tokens=3003`, there's no launcher for `tileN=64` as `computeSelectedTileN` filtered it out.\n\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n * Stricter MoE tile validation and ensured all supported tiles are available at launch to avoid missing kernel configurations.\n * Autotuner mapping for linked dynamic dimensions now yields consistent cached bucket values.\n\n* **Tests**\n * Added SM100 MoE autotuner integration tests (including invalid-cached-tactic checks).\n * Re-enabled and expanded autotuner unit tests and added a test utility to reset the autotuner.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1175,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"f7322d91610cf20b30f1c60422fb038dcc3858d5"},"date":{"kind":"string","value":"2026-03-17T15:08:21-07:00"},"pr_number":{"kind":"number","value":2777,"string":"2,777"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2777"},"title":{"kind":"string","value":"perf: Performance tune cute dsl RMSNorm variants (#2777)"},"message":{"kind":"string","value":"perf: Performance tune cute dsl RMSNorm variants (#2777)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n<!-- What does this PR do? Briefly describe the changes and why they’re\nneeded. -->\n\nRewrites all CuTe-DSL RMSNorm kernel variants (`rmsnorm`,\n`gemma_rmsnorm`, `fused_add_rmsnorm`, `gemma_fused_add_rmsnorm`,\n`rmsnorm_quant`, `fused_add_rmsnorm_quant`, `qk_rmsnorm`,\n`gemma_qk_rmsnorm`)\n\n**Key changes:**\n* Multi-row blocks with async global-to-shared copy (cpasync): Each\nthread block processes multiple rows, improving wave utilization and\nhiding memory latency. Falls back to synchronous copies when alignment\nor shared memory constraints prevent async usage.\n* Cluster reduction on SM90+: For large hidden sizes (H > max single-CTA\ncapacity), the workload is split across a CTA cluster that reduces\npartial sums via shared memory, avoiding the need for a single CTA to\nhandle the full row.\n* Vectorized FP8 convert+store PTX intrinsics\n`cvt.rn.satfinite.e4m3x2.f32`, dramatically improving quantization\nkernel throughput.\n* Occupancy-aware shared memory management\n* Non-contiguous tensor support without performance loss: Uses dual-path\ncompilation — a compact kernel for contiguous inputs (optimal codegen)\nand a strided kernel for non-contiguous inputs (symbolic row strides).\nRuntime dispatch via is_contiguous() ensures zero overhead for the\ncommon contiguous case.\n\n\n\n<details>\n<summary>Click to see B200 performance comparison data (Peak 8\nTB/s)</summary>\n\n**RMSNorm**\n\nBefore:\n<img width=\"1905\" height=\"1680\"\nalt=\"before_rmsnorm_bfloat16_NVIDIA_B200\"\nsrc=\"https://github.com/user-attachments/assets/15582140-f6df-4794-a4b4-2cc19d252dbb\"\n/>\nAfter\n<img width=\"1905\" height=\"1680\"\nalt=\"after_heatmap_rmsnorm_bfloat16_NVIDIA_B200\"\nsrc=\"https://github.com/user-attachments/assets/0d306806-36d2-4576-a6c2-9f4629f277f8\"\n/>\n\n**QK RMSNorm**\n\nBefore:\n<img width=\"1905\" height=\"1680\"\nalt=\"before_qk_rmsnorm_bfloat16_NVIDIA_B200\"\nsrc=\"https://github.com/user-attachments/assets/71540b32-1df7-4772-94a7-b6b8c71080ee\"\n/>\nAfter:\n<img width=\"1905\" height=\"1680\"\nalt=\"after_qk_rmsnorm_bfloat16_NVIDIA_B200\"\nsrc=\"https://github.com/user-attachments/assets/04e95f62-73fe-43f4-b1a1-95eff234e379\"\n/>\n\n**Add + RMSNorm + FP8 Quantize**\n\nBefore:\n<img width=\"1905\" height=\"1680\"\nalt=\"before_fused_add_rmsnorm_quant_bfloat16_NVIDIA_B200\"\nsrc=\"https://github.com/user-attachments/assets/7bdda617-2d20-4a05-b7fd-2e9e489acba7\"\n/>\nAfter:\n<img width=\"1905\" height=\"1680\"\nalt=\"after_fused_add_rmsnorm_quant_bfloat16_NVIDIA_B200\"\nsrc=\"https://github.com/user-attachments/assets/663fb2a5-45cf-4fab-a74b-dc338d7d8bd0\"\n/>\n\n</details>\n\n<details>\n<summary>Click to see H200 performance comparison data (Peak 4.8\nTB/s)</summary>\n\n**RMSNorm**\n\nBefore:\n<img width=\"1905\" height=\"1680\"\nalt=\"before_rmsnorm_bfloat16_NVIDIA_H200\"\nsrc=\"https://github.com/user-attachments/assets/42f63c06-8f6f-4ada-b6fd-e19de4ee32cc\"\n/>\n\nAfter:\n<img width=\"1905\" height=\"1680\" alt=\"after_rmsnorm_bfloat16_NVIDIA_H200\"\nsrc=\"https://github.com/user-attachments/assets/ae30fc58-159e-43b6-b108-850bf1711cad\"\n/>\n\n**RMSNorm + FP8 Quantize**\n\nBefore:\n<img width=\"1905\" height=\"1680\"\nalt=\"before_rmsnorm_quant_bfloat16_NVIDIA_H200\"\nsrc=\"https://github.com/user-attachments/assets/52469123-6a5f-459a-ae0b-586a11370ac9\"\n/>\nAfter:\n<img width=\"1905\" height=\"1680\"\nalt=\"after_rmsnorm_quant_bfloat16_NVIDIA_H200\"\nsrc=\"https://github.com/user-attachments/assets/4a229d4a-10ea-4d89-985f-c0378c6554d4\"\n/>\n\n\n**Add + RMSNorm + FP8 Quantize**\n\nBefore:\n<img width=\"1905\" height=\"1680\"\nalt=\"before_fused_add_rmsnorm_quant_bfloat16_NVIDIA_H200\"\nsrc=\"https://github.com/user-attachments/assets/78ac50aa-ae6a-4ea6-a585-0b326279e96b\"\n/>\nAfter:\n<img width=\"1905\" height=\"1680\"\nalt=\"after_fused_add_rmsnorm_quant_bfloat16_NVIDIA_H200\"\nsrc=\"https://github.com/user-attachments/assets/8268ffb8-0ee0-49b7-9353-8d0151002329\"\n/>\n\n</details>\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n#2396 \n\n#2771 \n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* SM-version aware kernels and cluster-based tiling for multi-CTA\nexecution\n * Contiguity-aware selection for compact vs. strided tensor paths\n * Hardware-accelerated FP8/E4M3 conversion and packed storage routines\n* New exposed utilities for device SM queries and cluster-backed\nreductions\n\n* **Improvements**\n* Async copy paths, expanded shared-memory and cluster-reduction support\n* Per-cluster memory/tiling estimation and improved multi-cluster\nreduction handling\n* Public APIs now accept an optional SM-version hint and infer/preserve\ncontiguity\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"flashinfer/norm/utils.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nShared CuTe DSL Utilities for Norm Kernels\n==========================================\n\nCommon utilities used by all norm kernels:\n- Constants for vectorization and FP8 quantization\n- PTX intrinsics for fast reciprocal and FP8 conversion\n- Warp and block reduction utilities\n- Predicate helpers for bounds checking\n- Layout configuration helpers\n- Type conversion utilities\n\"\"\"\n\nimport math\nimport operator\nfrom typing import Callable\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Int64\nfrom cutlass.cutlass_dsl import T, dsl_user_op\nfrom cutlass._mlir.dialects import llvm\n\nfrom ..cute_dsl.utils import get_cutlass_dtype, get_num_sm\n\n\n# =============================================================================\n# Constants\n# =============================================================================\n\nFLOAT8_E4M3_MAX = 448.0 # Maximum value representable in FP8 E4M3\nCOPY_BITS = 128 # 128-bit vectorized loads\n\n\n# =============================================================================\n# PTX Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef rcp_approx_ftz(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Fast reciprocal using PTX rcp.approx.ftz.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"rcp.approx.ftz.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef cvt_and_store_f32_to_e4m3_hw(val: Float32, addr: Int64, *, loc=None, ip=None):\n \"\"\"Convert float32 to E4M3 and store single byte — hardware path (sm_89+).\n\n Uses the cvt.rn.satfinite.e4m3x2.f32 PTX instruction for maximum performance.\n \"\"\"\n llvm.inline_asm(\n None,\n [Float32(val).ir_value(loc=loc, ip=ip), Int64(addr).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .f32 zero;\n mov.f32 zero, 0f00000000;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, zero, $0;\n st.global.b8 [$1], fp8_pair;\n }\n \"\"\",\n \"f,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef cvt_and_store_f32_to_e4m3_sw(val: Float32, addr: Int64, *, loc=None, ip=None):\n \"\"\"Convert float32 to E4M3 and store single byte — software path (all architectures).\n\n Uses integer bit manipulation mirroring NVIDIA's __nv_cvt_float_to_fp8 from cuda_fp8.hpp.\n The caller must clamp the value to [-448, 448] before calling this function.\n\n E4M3 format: 1 sign bit, 4 exponent bits (bias=7), 3 mantissa bits.\n Conversion strategy (operates on f32 bit representation):\n - Normal range (f32 biased exp >= 121): direct exponent/mantissa extraction with RNE\n - Denormal range (f32 biased exp in [118..120]): shift mantissa with implicit bit, RNE\n - Underflow (abs <= 2^-10): flush to zero (2^-10 is the RNE midpoint to min denorm)\n \"\"\"\n llvm.inline_asm(\n None,\n [Float32(val).ir_value(loc=loc, ip=ip), Int64(addr).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 fbits, sign8, abs_bits, f32_exp, f32_mant;\n .reg .b32 e4m3_exp, e4m3_mant, norm_raw;\n .reg .b32 rbit, sticky, odd_bit, radj;\n .reg .b32 shift, dmant4, denorm_raw;\n .reg .b32 dr_bit, dsticky, dadj;\n .reg .b32 e4m3_raw, tmp, tmp2;\n .reg .pred p_zero, p_denorm;\n\n // Bitcast float to int and extract sign/exponent/mantissa\n mov.b32 fbits, $0;\n shr.u32 sign8, fbits, 24;\n and.b32 sign8, sign8, 128;\n and.b32 abs_bits, fbits, 0x7FFFFFFF;\n shr.u32 f32_exp, abs_bits, 23;\n and.b32 f32_mant, abs_bits, 0x007FFFFF;\n\n // === Normal path (f32 biased exp >= 121, i.e. e4m3 exp >= 1) ===\n sub.u32 e4m3_exp, f32_exp, 120;\n shr.u32 e4m3_mant, f32_mant, 20;\n shl.b32 norm_raw, e4m3_exp, 3;\n or.b32 norm_raw, norm_raw, e4m3_mant;\n\n // Round-to-nearest-even: round up if round_bit AND (sticky OR odd)\n shr.u32 rbit, f32_mant, 19;\n and.b32 rbit, rbit, 1;\n and.b32 sticky, f32_mant, 0x0007FFFF;\n and.b32 odd_bit, e4m3_mant, 1;\n or.b32 tmp, sticky, odd_bit;\n min.u32 tmp, tmp, 1;\n and.b32 radj, tmp, rbit;\n add.u32 norm_raw, norm_raw, radj;\n min.u32 norm_raw, norm_raw, 126;\n\n // === Denormal path (f32 biased exp in {118,119,120}) ===\n sub.u32 shift, 121, f32_exp;\n shr.u32 tmp, f32_mant, 20;\n or.b32 dmant4, tmp, 8;\n shr.u32 denorm_raw, dmant4, shift;\n\n // RNE rounding for denormals\n sub.u32 tmp, shift, 1;\n shr.u32 dr_bit, dmant4, tmp;\n and.b32 dr_bit, dr_bit, 1;\n shl.b32 tmp2, 1, tmp;\n sub.u32 tmp2, tmp2, 1;\n and.b32 dsticky, dmant4, tmp2;\n and.b32 tmp, f32_mant, 0x000FFFFF;\n or.b32 dsticky, dsticky, tmp;\n and.b32 odd_bit, denorm_raw, 1;\n or.b32 tmp, dsticky, odd_bit;\n min.u32 tmp, tmp, 1;\n and.b32 dadj, tmp, dr_bit;\n add.u32 denorm_raw, denorm_raw, dadj;\n\n // Select between normal/denormal, then apply zero flush\n setp.le.u32 p_denorm, f32_exp, 120;\n selp.u32 e4m3_raw, denorm_raw, norm_raw, p_denorm;\n setp.le.u32 p_zero, abs_bits, 0x3A800000;\n selp.u32 e4m3_raw, 0, e4m3_raw, p_zero;\n\n // Apply sign and store single byte\n or.b32 e4m3_raw, e4m3_raw, sign8;\n st.global.b8 [$1], e4m3_raw;\n }\n \"\"\",\n \"f,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\ndef has_hw_fp8_cvt(device: torch.device = None) -> bool:\n \"\"\"Check if the device supports hardware FP8 conversion (sm_89+).\"\"\"\n if device is None:\n device = torch.device(\"cuda\", torch.cuda.current_device())\n major, minor = torch.cuda.get_device_capability(device)\n return major > 8 or (major == 8 and minor >= 9)\n\n\n@dsl_user_op\ndef get_ptr_as_int64(tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None) -> Int64:\n \"\"\"Get the memory address of tensor[offset] as Int64.\"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n ptr_int = llvm.ptrtoint(T.i64(), elem_ptr.llvm_ptr, loc=loc, ip=ip)\n return Int64(ptr_int)\n\n\n# =============================================================================\n# Warp and Block Reduction Utilities\n# =============================================================================\n\n\n@cute.jit\ndef warp_reduce(val, op, width: cutlass.Constexpr[int] = 32):\n \"\"\"Reduce across threads in a warp using butterfly shuffle.\"\"\"\n if cutlass.const_expr(isinstance(val, cute.TensorSSA)):\n res = cute.make_rmem_tensor(val.shape, val.dtype)\n res.store(val)\n for i in cutlass.range_constexpr(cute.size(val.shape)):\n res[i] = warp_reduce(res[i], op, width)\n return res.load()\n else:\n for i in cutlass.range_constexpr(int(math.log2(width))):\n val = op(val, cute.arch.shuffle_sync_bfly(val, offset=1 << i))\n return val\n\n\n@cute.jit\ndef block_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n init_val: Float32,\n) -> Float32:\n \"\"\"Block reduction across multiple warps using shared memory.\"\"\"\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n num_warps = cute.size(reduction_buffer.shape)\n\n if lane_idx == 0:\n reduction_buffer[warp_idx] = val\n cute.arch.barrier()\n\n block_reduce_val = init_val\n if lane_idx < num_warps:\n block_reduce_val = reduction_buffer[lane_idx]\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef row_reduce_sum(\n x: cute.TensorSSA,\n threads_per_row: cutlass.Constexpr[int],\n reduction_buffer: cute.Tensor,\n) -> Float32:\n \"\"\"Row reduction for sum operation.\"\"\"\n local_val = x.reduce(\n cute.ReductionOp.ADD, init_val=Float32(0.0), reduction_profile=0\n )\n\n warp_width = min(threads_per_row, 32)\n warp_val = warp_reduce(local_val, operator.add, width=warp_width)\n\n warps_per_row = max(threads_per_row // 32, 1)\n\n if cutlass.const_expr(warps_per_row > 1):\n return block_reduce(warp_val, operator.add, reduction_buffer, Float32(0.0))\n else:\n return warp_val\n\n\n# =============================================================================\n# Predicate Utility\n# =============================================================================\n\n\n@cute.jit\ndef predicate_k(tXcX: cute.Tensor, limit: int) -> cute.Tensor:\n \"\"\"Create predicate tensor for bounds checking (2D tensors).\"\"\"\n tXpX = cute.make_rmem_tensor(\n cute.make_layout(\n (\n cute.size(tXcX, mode=[0, 1]),\n cute.size(tXcX, mode=[1]),\n cute.size(tXcX, mode=[2]),\n ),\n stride=(cute.size(tXcX, mode=[2]), 0, 1),\n ),\n cutlass.Boolean,\n )\n for rest_v in cutlass.range_constexpr(tXpX.shape[0]):\n for rest_k in cutlass.range_constexpr(tXpX.shape[2]):\n tXpX[rest_v, 0, rest_k] = cute.elem_less(\n tXcX[(0, rest_v), 0, rest_k][1], limit\n )\n return tXpX\n\n\n@cute.jit\ndef predicate_k_3d(tXcX: cute.Tensor, limit: int) -> cute.Tensor:\n \"\"\"Create predicate tensor for bounds checking (3D tensors).\n\n For 3D tensors after local_tile, the last coordinate [2] is the head_dim dimension.\n \"\"\"\n tXpX = cute.make_rmem_tensor(\n cute.make_layout(\n (\n cute.size(tXcX, mode=[0, 1]),\n cute.size(tXcX, mode=[1]),\n cute.size(tXcX, mode=[2]),\n ),\n stride=(cute.size(tXcX, mode=[2]), 0, 1),\n ),\n cutlass.Boolean,\n )\n for rest_v in cutlass.range_constexpr(tXpX.shape[0]):\n for rest_k in cutlass.range_constexpr(tXpX.shape[2]):\n # For 3D tensor, coordinate[2] is the head_dim index\n tXpX[rest_v, 0, rest_k] = cute.elem_less(\n tXcX[(0, rest_v), 0, rest_k][2], limit\n )\n return tXpX\n\n\n# =============================================================================\n# Helper Functions for Kernel Configuration\n# =============================================================================\n\n\ndef compute_optimal_vec_size(H: int, max_vec_size: int) -> int:\n \"\"\"Compute vec_size that maximizes warp utilization.\n\n For small hidden sizes, using max vec_size may result in fewer than 32 threads,\n wasting warp resources. This function finds the largest vec_size that:\n 1. Divides H evenly\n 2. Results in at least 32 threads (one full warp)\n\n Examples:\n - H=128, max=8: vec_size=8 gives 16 threads, vec_size=4 gives 32 threads -> return 4\n - H=4096, max=8: vec_size=8 gives 512 threads -> return 8\n - H=111, max=8: no vec_size divides evenly with >=32 threads, use gcd -> return 1\n \"\"\"\n # Try vec_sizes from largest to smallest\n for vec_size in [\n max_vec_size,\n max_vec_size // 2,\n max_vec_size // 4,\n max_vec_size // 8,\n ]:\n if vec_size < 1:\n continue\n if H % vec_size != 0:\n continue\n threads_needed = H // vec_size\n if threads_needed >= 32:\n return vec_size\n # Fallback: use gcd for correctness (handles odd sizes like 111)\n return math.gcd(max_vec_size, H)\n\n\ndef compute_threads_per_row(H: int, vec_size: int) -> int:\n \"\"\"Compute optimal threads per row based on hidden size.\"\"\"\n threads_needed = (H + vec_size - 1) // vec_size\n # Round up to power of 2, capped at 1024\n threads = 32\n while threads < threads_needed and threads < 1024:\n threads *= 2\n return min(threads, 1024)\n\n\ndef make_tv_layout(threads_per_row: int, vec_size: int, num_vec_blocks: int) -> tuple:\n \"\"\"Create Thread-Value layout for coalesced vectorized memory access.\n\n This layout distributes work across threads where each thread handles\n vec_size consecutive elements, and threads are arranged for coalesced access.\n\n Args:\n threads_per_row: Number of threads processing one row\n vec_size: Number of elements each thread processes per vector load\n num_vec_blocks: Number of vector blocks per row\n\n Returns:\n Tuple of (shape, stride) for creating cute.Layout\n \"\"\"\n shape = (\n (threads_per_row, 1),\n (vec_size, num_vec_blocks),\n )\n stride = (\n (vec_size, 1),\n (1, vec_size * threads_per_row),\n )\n return shape, stride\n\n\n# =============================================================================\n# Type Conversion Utilities\n# =============================================================================\n\n\n# Module-level dict to avoid recreation on each call\n_TORCH_DTYPE_TO_STR_MAP = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n torch.float32: \"float32\",\n torch.float8_e4m3fn: \"float8_e4m3fn\",\n}\n\n\ndef _torch_dtype_to_str(dtype: torch.dtype) -> str:\n return _TORCH_DTYPE_TO_STR_MAP[dtype]\n\n\n# Re-export utilities from cute_dsl.utils for convenience\n__all__ = [\n # Constants\n \"FLOAT8_E4M3_MAX\",\n \"COPY_BITS\",\n # PTX intrinsics\n \"rcp_approx_ftz\",\n \"cvt_and_store_f32_to_e4m3_hw\",\n \"cvt_and_store_f32_to_e4m3_sw\",\n \"has_hw_fp8_cvt\",\n \"get_ptr_as_int64\",\n # Reduction utilities\n \"warp_reduce\",\n \"block_reduce\",\n \"row_reduce_sum\",\n # Predicate utilities\n \"predicate_k\",\n \"predicate_k_3d\",\n # Configuration helpers\n \"compute_optimal_vec_size\",\n \"compute_threads_per_row\",\n \"make_tv_layout\",\n # Type utilities\n \"_torch_dtype_to_str\",\n # Re-exports from cute_dsl.utils\n \"get_cutlass_dtype\",\n \"get_num_sm\",\n]\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nShared CuTe DSL Utilities for Norm Kernels\n==========================================\n\nCommon utilities used by all norm kernels:\n- Constants for vectorization and FP8 quantization\n- PTX intrinsics for fast reciprocal and FP8 conversion\n- Warp and block reduction utilities\n- Predicate helpers for bounds checking\n- Layout configuration helpers\n- Type conversion utilities\n\"\"\"\n\nimport functools\nimport math\nimport operator\nfrom typing import Callable\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Int64\nfrom cutlass.cutlass_dsl import T, dsl_user_op\nfrom cutlass._mlir.dialects import llvm\n\nfrom ..cute_dsl.utils import get_cutlass_dtype, get_num_sm\n\n\n# =============================================================================\n# Constants\n# =============================================================================\n\nFLOAT8_E4M3_MAX = 448.0 # Maximum value representable in FP8 E4M3\nCOPY_BITS = 128 # 128-bit vectorized loads\n\n\n# =============================================================================\n# PTX Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef rcp_approx_ftz(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Fast reciprocal using PTX rcp.approx.ftz.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"rcp.approx.ftz.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef cvt_and_store_f32_to_e4m3_hw(val: Float32, addr: Int64, *, loc=None, ip=None):\n \"\"\"Convert float32 to E4M3 and store single byte — hardware path (sm_89+).\n\n Uses the cvt.rn.satfinite.e4m3x2.f32 PTX instruction for maximum performance.\n \"\"\"\n llvm.inline_asm(\n None,\n [Float32(val).ir_value(loc=loc, ip=ip), Int64(addr).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .f32 zero;\n mov.f32 zero, 0f00000000;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, zero, $0;\n st.global.b8 [$1], fp8_pair;\n }\n \"\"\",\n \"f,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef cvt_and_store_f32_to_e4m3_sw(val: Float32, addr: Int64, *, loc=None, ip=None):\n \"\"\"Convert float32 to E4M3 and store single byte — software path (all architectures).\n\n Uses integer bit manipulation mirroring NVIDIA's __nv_cvt_float_to_fp8 from cuda_fp8.hpp.\n The caller must clamp the value to [-448, 448] before calling this function.\n\n E4M3 format: 1 sign bit, 4 exponent bits (bias=7), 3 mantissa bits.\n Conversion strategy (operates on f32 bit representation):\n - Normal range (f32 biased exp >= 121): direct exponent/mantissa extraction with RNE\n - Denormal range (f32 biased exp in [118..120]): shift mantissa with implicit bit, RNE\n - Underflow (abs <= 2^-10): flush to zero (2^-10 is the RNE midpoint to min denorm)\n \"\"\"\n llvm.inline_asm(\n None,\n [Float32(val).ir_value(loc=loc, ip=ip), Int64(addr).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 fbits, sign8, abs_bits, f32_exp, f32_mant;\n .reg .b32 e4m3_exp, e4m3_mant, norm_raw;\n .reg .b32 rbit, sticky, odd_bit, radj;\n .reg .b32 shift, dmant4, denorm_raw;\n .reg .b32 dr_bit, dsticky, dadj;\n .reg .b32 e4m3_raw, tmp, tmp2;\n .reg .pred p_zero, p_denorm;\n\n // Bitcast float to int and extract sign/exponent/mantissa\n mov.b32 fbits, $0;\n shr.u32 sign8, fbits, 24;\n and.b32 sign8, sign8, 128;\n and.b32 abs_bits, fbits, 0x7FFFFFFF;\n shr.u32 f32_exp, abs_bits, 23;\n and.b32 f32_mant, abs_bits, 0x007FFFFF;\n\n // === Normal path (f32 biased exp >= 121, i.e. e4m3 exp >= 1) ===\n sub.u32 e4m3_exp, f32_exp, 120;\n shr.u32 e4m3_mant, f32_mant, 20;\n shl.b32 norm_raw, e4m3_exp, 3;\n or.b32 norm_raw, norm_raw, e4m3_mant;\n\n // Round-to-nearest-even: round up if round_bit AND (sticky OR odd)\n shr.u32 rbit, f32_mant, 19;\n and.b32 rbit, rbit, 1;\n and.b32 sticky, f32_mant, 0x0007FFFF;\n and.b32 odd_bit, e4m3_mant, 1;\n or.b32 tmp, sticky, odd_bit;\n min.u32 tmp, tmp, 1;\n and.b32 radj, tmp, rbit;\n add.u32 norm_raw, norm_raw, radj;\n min.u32 norm_raw, norm_raw, 126;\n\n // === Denormal path (f32 biased exp in {118,119,120}) ===\n sub.u32 shift, 121, f32_exp;\n shr.u32 tmp, f32_mant, 20;\n or.b32 dmant4, tmp, 8;\n shr.u32 denorm_raw, dmant4, shift;\n\n // RNE rounding for denormals\n sub.u32 tmp, shift, 1;\n shr.u32 dr_bit, dmant4, tmp;\n and.b32 dr_bit, dr_bit, 1;\n shl.b32 tmp2, 1, tmp;\n sub.u32 tmp2, tmp2, 1;\n and.b32 dsticky, dmant4, tmp2;\n and.b32 tmp, f32_mant, 0x000FFFFF;\n or.b32 dsticky, dsticky, tmp;\n and.b32 odd_bit, denorm_raw, 1;\n or.b32 tmp, dsticky, odd_bit;\n min.u32 tmp, tmp, 1;\n and.b32 dadj, tmp, dr_bit;\n add.u32 denorm_raw, denorm_raw, dadj;\n\n // Select between normal/denormal, then apply zero flush\n setp.le.u32 p_denorm, f32_exp, 120;\n selp.u32 e4m3_raw, denorm_raw, norm_raw, p_denorm;\n setp.le.u32 p_zero, abs_bits, 0x3A800000;\n selp.u32 e4m3_raw, 0, e4m3_raw, p_zero;\n\n // Apply sign and store single byte\n or.b32 e4m3_raw, e4m3_raw, sign8;\n st.global.b8 [$1], e4m3_raw;\n }\n \"\"\",\n \"f,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef cvt_and_store_8xf32_to_e4m3_hw(\n v0: Float32,\n v1: Float32,\n v2: Float32,\n v3: Float32,\n v4: Float32,\n v5: Float32,\n v6: Float32,\n v7: Float32,\n addr: Int64,\n *,\n loc=None,\n ip=None,\n):\n \"\"\"Convert 8 float32 values to E4M3 and store as one 64-bit global store (sm_89+).\n\n Uses cvt.rn.satfinite.e4m3x2.f32 to convert pairs, then packs into two b32\n words and issues a single st.global.v2.b32. ~4x fewer instructions and ~8x\n fewer store transactions compared to 8 scalar st.global.b8 calls.\n \"\"\"\n llvm.inline_asm(\n None,\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n Float32(v2).ir_value(loc=loc, ip=ip),\n Float32(v3).ir_value(loc=loc, ip=ip),\n Float32(v4).ir_value(loc=loc, ip=ip),\n Float32(v5).ir_value(loc=loc, ip=ip),\n Float32(v6).ir_value(loc=loc, ip=ip),\n Float32(v7).ir_value(loc=loc, ip=ip),\n Int64(addr).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 p01, p23, p45, p67;\n .reg .b32 lo, hi;\n cvt.rn.satfinite.e4m3x2.f32 p01, $1, $0;\n cvt.rn.satfinite.e4m3x2.f32 p23, $3, $2;\n cvt.rn.satfinite.e4m3x2.f32 p45, $5, $4;\n cvt.rn.satfinite.e4m3x2.f32 p67, $7, $6;\n mov.b32 lo, {p01, p23};\n mov.b32 hi, {p45, p67};\n st.global.v2.b32 [$8], {lo, hi};\n }\n \"\"\",\n \"f,f,f,f,f,f,f,f,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef cvt_and_store_4xf32_to_e4m3_hw(\n v0: Float32,\n v1: Float32,\n v2: Float32,\n v3: Float32,\n addr: Int64,\n *,\n loc=None,\n ip=None,\n):\n \"\"\"Convert 4 float32 values to E4M3 and store as one 32-bit global store (sm_89+).\"\"\"\n llvm.inline_asm(\n None,\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n Float32(v2).ir_value(loc=loc, ip=ip),\n Float32(v3).ir_value(loc=loc, ip=ip),\n Int64(addr).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 p01, p23;\n .reg .b32 packed;\n cvt.rn.satfinite.e4m3x2.f32 p01, $1, $0;\n cvt.rn.satfinite.e4m3x2.f32 p23, $3, $2;\n mov.b32 packed, {p01, p23};\n st.global.b32 [$4], packed;\n }\n \"\"\",\n \"f,f,f,f,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef cvt_and_store_2xf32_to_e4m3_hw(\n v0: Float32, v1: Float32, addr: Int64, *, loc=None, ip=None\n):\n \"\"\"Convert 2 float32 values to E4M3 and store as one 16-bit global store (sm_89+).\"\"\"\n llvm.inline_asm(\n None,\n [\n Float32(v0).ir_value(loc=loc, ip=ip),\n Float32(v1).ir_value(loc=loc, ip=ip),\n Int64(addr).ir_value(loc=loc, ip=ip),\n ],\n \"\"\"\n {\n .reg .b16 packed;\n cvt.rn.satfinite.e4m3x2.f32 packed, $1, $0;\n st.global.b16 [$2], packed;\n }\n \"\"\",\n \"f,f,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\ndef has_hw_fp8_cvt(device: torch.device = None) -> bool:\n \"\"\"Check if the device supports hardware FP8 conversion (sm_89+).\"\"\"\n if device is None:\n device = torch.device(\"cuda\", torch.cuda.current_device())\n major, minor = torch.cuda.get_device_capability(device)\n return major > 8 or (major == 8 and minor >= 9)\n\n\n@functools.lru_cache(maxsize=16)\ndef get_sm_version(device=None) -> int:\n \"\"\"Get the SM version of a CUDA device (e.g., 100 for SM100).\"\"\"\n if not torch.cuda.is_available():\n return 80\n if device is None:\n device = torch.cuda.current_device()\n props = torch.cuda.get_device_properties(device)\n return props.major * 10 + props.minor\n\n\n@dsl_user_op\ndef get_ptr_as_int64(tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None) -> Int64:\n \"\"\"Get the memory address of tensor[offset] as Int64.\"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n ptr_int = llvm.ptrtoint(T.i64(), elem_ptr.llvm_ptr, loc=loc, ip=ip)\n return Int64(ptr_int)\n\n\n# =============================================================================\n# PTX Intrinsics - Cluster Operations (SM90+)\n# =============================================================================\n\n\n@dsl_user_op\ndef set_block_rank(\n smem_ptr: cute.Pointer, peer_cta_rank_in_cluster: Int32, *, loc=None, ip=None\n) -> Int32:\n \"\"\"Map smem pointer to address at another CTA rank in the cluster.\"\"\"\n smem_ptr_i32 = smem_ptr.toint(loc=loc, ip=ip).ir_value()\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [smem_ptr_i32, peer_cta_rank_in_cluster.ir_value()],\n \"mapa.shared::cluster.u32 $0, $1, $2;\",\n \"=r,r,r\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef store_shared_remote(\n val: Float32,\n smem_ptr: cute.Pointer,\n mbar_ptr: cute.Pointer,\n peer_cta_rank_in_cluster: Int32,\n *,\n loc=None,\n ip=None,\n) -> None:\n \"\"\"Store Float32 value to shared memory on a remote CTA in the cluster.\"\"\"\n remote_smem_ptr_i32 = set_block_rank(\n smem_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n ).ir_value()\n remote_mbar_ptr_i32 = set_block_rank(\n mbar_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n ).ir_value()\n llvm.inline_asm(\n None,\n [remote_smem_ptr_i32, val.ir_value(loc=loc, ip=ip), remote_mbar_ptr_i32],\n \"st.async.shared::cluster.mbarrier::complete_tx::bytes.f32 [$0], $1, [$2];\",\n \"r,f,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef elem_pointer(x: cute.Tensor, coord, *, loc=None, ip=None) -> cute.Pointer:\n \"\"\"Get pointer to element at coordinate in tensor.\"\"\"\n return x.iterator + cute.crd2idx(coord, x.layout, loc=loc, ip=ip)\n\n\n# =============================================================================\n# Warp and Block Reduction Utilities\n# =============================================================================\n\n\n@cute.jit\ndef warp_reduce(val, op, width: cutlass.Constexpr[int] = 32):\n \"\"\"Reduce across threads in a warp using butterfly shuffle.\"\"\"\n if cutlass.const_expr(isinstance(val, cute.TensorSSA)):\n res = cute.make_rmem_tensor(val.shape, val.dtype)\n res.store(val)\n for i in cutlass.range_constexpr(cute.size(val.shape)):\n res[i] = warp_reduce(res[i], op, width)\n return res.load()\n else:\n for i in cutlass.range_constexpr(int(math.log2(width))):\n val = op(val, cute.arch.shuffle_sync_bfly(val, offset=1 << i))\n return val\n\n\n@cute.jit\ndef block_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n init_val: Float32,\n) -> Float32:\n \"\"\"Block reduction across multiple warps using shared memory.\"\"\"\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n num_warps = cute.size(reduction_buffer.shape)\n\n if lane_idx == 0:\n reduction_buffer[warp_idx] = val\n cute.arch.barrier()\n\n block_reduce_val = init_val\n if lane_idx < num_warps:\n block_reduce_val = reduction_buffer[lane_idx]\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef row_reduce_sum(\n x: cute.TensorSSA,\n threads_per_row: cutlass.Constexpr[int],\n reduction_buffer: cute.Tensor,\n) -> Float32:\n \"\"\"Row reduction for sum operation.\"\"\"\n local_val = x.reduce(\n cute.ReductionOp.ADD, init_val=Float32(0.0), reduction_profile=0\n )\n\n warp_width = min(threads_per_row, 32)\n warp_val = warp_reduce(local_val, operator.add, width=warp_width)\n\n warps_per_row = max(threads_per_row // 32, 1)\n\n if cutlass.const_expr(warps_per_row > 1):\n return block_reduce(warp_val, operator.add, reduction_buffer, Float32(0.0))\n else:\n return warp_val\n\n\n@cute.jit\ndef block_reduce_multirow(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n init_val: Float32,\n) -> Float32:\n \"\"\"Block reduction with 2D buffer (rows_per_block, warps_per_row).\n\n Each warp writes its partial sum to the row it belongs to, then\n lane 0..warps_per_row-1 read back and do a final warp reduction.\n \"\"\"\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n warps_per_row = cute.size(reduction_buffer.shape[1])\n row_idx = warp_idx // warps_per_row\n col_idx = warp_idx % warps_per_row\n\n if lane_idx == 0:\n reduction_buffer[row_idx, col_idx] = val\n cute.arch.barrier()\n\n block_reduce_val = init_val\n if lane_idx < warps_per_row:\n block_reduce_val = reduction_buffer[row_idx, lane_idx]\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef cluster_reduce_multirow(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n mbar_ptr,\n cluster_n: cutlass.Constexpr[int],\n init_val: Float32,\n) -> Float32:\n \"\"\"Cluster reduction across multiple CTAs using mbarrier.\n\n reduction_buffer has shape (rows_per_block, (warps_per_row, cluster_n)).\n Each warp sends its partial result to all CTAs in the cluster via\n st.async.shared::cluster, then every CTA reduces the collected values.\n \"\"\"\n cta_rank_in_cluster = cute.arch.block_idx_in_cluster()\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n\n rows_per_block = reduction_buffer.shape[0]\n warps_per_row = reduction_buffer.shape[1][0]\n\n row_idx = warp_idx // warps_per_row\n col_idx = warp_idx % warps_per_row\n\n if warp_idx == 0:\n with cute.arch.elect_one():\n num_warps = rows_per_block * warps_per_row\n expected_bytes = num_warps * cluster_n * 4\n cute.arch.mbarrier_arrive_and_expect_tx(mbar_ptr, expected_bytes)\n\n if lane_idx < cluster_n:\n store_shared_remote(\n val,\n elem_pointer(reduction_buffer, (row_idx, (col_idx, cta_rank_in_cluster))),\n mbar_ptr,\n peer_cta_rank_in_cluster=lane_idx,\n )\n\n cute.arch.mbarrier_wait(mbar_ptr, phase=0)\n\n num_total = warps_per_row * cluster_n\n num_iter = cute.ceil_div(num_total, 32)\n\n block_reduce_val = init_val\n for i in cutlass.range_constexpr(num_iter):\n idx = lane_idx + i * 32\n if idx < num_total:\n block_reduce_val = op(block_reduce_val, reduction_buffer[row_idx, idx])\n\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef row_reduce_sum_multirow(\n x: cute.TensorSSA,\n threads_per_row: cutlass.Constexpr[int],\n reduction_buffer: cute.Tensor,\n mbar_ptr,\n cluster_n: cutlass.Constexpr[int],\n) -> Float32:\n \"\"\"Row reduction for sum with optional cluster support.\n\n When cluster_n == 1, uses block-level reduction with 2D buffer\n (rows_per_block, warps_per_row). When cluster_n > 1, uses cross-CTA\n cluster reduction with hierarchical buffer\n (rows_per_block, (warps_per_row, cluster_n)).\n \"\"\"\n local_val = x.reduce(\n cute.ReductionOp.ADD, init_val=Float32(0.0), reduction_profile=0\n )\n\n warp_width = min(threads_per_row, 32)\n warp_val = warp_reduce(local_val, operator.add, width=warp_width)\n\n warps_per_row = max(threads_per_row // 32, 1)\n\n if cutlass.const_expr(warps_per_row > 1 or cluster_n > 1):\n if cutlass.const_expr(cluster_n == 1):\n return block_reduce_multirow(\n warp_val, operator.add, reduction_buffer, Float32(0.0)\n )\n else:\n return cluster_reduce_multirow(\n warp_val,\n operator.add,\n reduction_buffer,\n mbar_ptr,\n cluster_n,\n Float32(0.0),\n )\n else:\n return warp_val\n\n\n# =============================================================================\n# Predicate Utility\n# =============================================================================\n\n\n@cute.jit\ndef predicate_k(tXcX: cute.Tensor, limit: int) -> cute.Tensor:\n \"\"\"Create predicate tensor for bounds checking (2D tensors).\"\"\"\n tXpX = cute.make_rmem_tensor(\n cute.make_layout(\n (\n cute.size(tXcX, mode=[0, 1]),\n cute.size(tXcX, mode=[1]),\n cute.size(tXcX, mode=[2]),\n ),\n stride=(cute.size(tXcX, mode=[2]), 0, 1),\n ),\n cutlass.Boolean,\n )\n for rest_v in cutlass.range_constexpr(tXpX.shape[0]):\n for rest_k in cutlass.range_constexpr(tXpX.shape[2]):\n tXpX[rest_v, 0, rest_k] = cute.elem_less(\n tXcX[(0, rest_v), 0, rest_k][1], limit\n )\n return tXpX\n\n\n@cute.jit\ndef predicate_k_3d(tXcX: cute.Tensor, limit: int) -> cute.Tensor:\n \"\"\"Create predicate tensor for bounds checking (3D tensors).\n\n For 3D tensors after local_tile, the last coordinate [2] is the head_dim dimension.\n \"\"\"\n tXpX = cute.make_rmem_tensor(\n cute.make_layout(\n (\n cute.size(tXcX, mode=[0, 1]),\n cute.size(tXcX, mode=[1]),\n cute.size(tXcX, mode=[2]),\n ),\n stride=(cute.size(tXcX, mode=[2]), 0, 1),\n ),\n cutlass.Boolean,\n )\n for rest_v in cutlass.range_constexpr(tXpX.shape[0]):\n for rest_k in cutlass.range_constexpr(tXpX.shape[2]):\n # For 3D tensor, coordinate[2] is the head_dim index\n tXpX[rest_v, 0, rest_k] = cute.elem_less(\n tXcX[(0, rest_v), 0, rest_k][2], limit\n )\n return tXpX\n\n\n# =============================================================================\n# Helper Functions for Kernel Configuration\n# =============================================================================\n\n\ndef compute_optimal_vec_size(H: int, max_vec_size: int) -> int:\n \"\"\"Compute vec_size that maximizes warp utilization.\n\n For small hidden sizes, using max vec_size may result in fewer than 32 threads,\n wasting warp resources. This function finds the largest vec_size that:\n 1. Divides H evenly\n 2. Results in at least 32 threads (one full warp)\n\n Examples:\n - H=128, max=8: vec_size=8 gives 16 threads, vec_size=4 gives 32 threads -> return 4\n - H=4096, max=8: vec_size=8 gives 512 threads -> return 8\n - H=111, max=8: no vec_size divides evenly with >=32 threads, use gcd -> return 1\n \"\"\"\n # Try vec_sizes from largest to smallest\n for vec_size in [\n max_vec_size,\n max_vec_size // 2,\n max_vec_size // 4,\n max_vec_size // 8,\n ]:\n if vec_size < 1:\n continue\n if H % vec_size != 0:\n continue\n threads_needed = H // vec_size\n if threads_needed >= 32:\n return vec_size\n # Fallback: use gcd for correctness (handles odd sizes like 111)\n return math.gcd(max_vec_size, H)\n\n\ndef compute_threads_per_row(H: int, vec_size: int) -> int:\n \"\"\"Compute optimal threads per row based on hidden size.\"\"\"\n threads_needed = (H + vec_size - 1) // vec_size\n # Round up to power of 2, capped at 1024\n threads = 32\n while threads < threads_needed and threads < 1024:\n threads *= 2\n return min(threads, 1024)\n\n\ndef make_tv_layout(threads_per_row: int, vec_size: int, num_vec_blocks: int) -> tuple:\n \"\"\"Create Thread-Value layout for coalesced vectorized memory access.\n\n This layout distributes work across threads where each thread handles\n vec_size consecutive elements, and threads are arranged for coalesced access.\n\n Args:\n threads_per_row: Number of threads processing one row\n vec_size: Number of elements each thread processes per vector load\n num_vec_blocks: Number of vector blocks per row\n\n Returns:\n Tuple of (shape, stride) for creating cute.Layout\n \"\"\"\n shape = (\n (threads_per_row, 1),\n (vec_size, num_vec_blocks),\n )\n stride = (\n (vec_size, 1),\n (1, vec_size * threads_per_row),\n )\n return shape, stride\n\n\n# =============================================================================\n# Type Conversion Utilities\n# =============================================================================\n\n\n# Module-level dict to avoid recreation on each call\n_TORCH_DTYPE_TO_STR_MAP = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n torch.float32: \"float32\",\n torch.float8_e4m3fn: \"float8_e4m3fn\",\n}\n\n\ndef _torch_dtype_to_str(dtype: torch.dtype) -> str:\n return _TORCH_DTYPE_TO_STR_MAP[dtype]\n\n\n# Re-export utilities from cute_dsl.utils for convenience\n__all__ = [\n # Constants\n \"FLOAT8_E4M3_MAX\",\n \"COPY_BITS\",\n # PTX intrinsics\n \"rcp_approx_ftz\",\n \"cvt_and_store_f32_to_e4m3_hw\",\n \"cvt_and_store_f32_to_e4m3_sw\",\n \"cvt_and_store_8xf32_to_e4m3_hw\",\n \"cvt_and_store_4xf32_to_e4m3_hw\",\n \"cvt_and_store_2xf32_to_e4m3_hw\",\n \"has_hw_fp8_cvt\",\n \"get_ptr_as_int64\",\n # PTX intrinsics - Cluster operations\n \"set_block_rank\",\n \"store_shared_remote\",\n \"elem_pointer\",\n # Device utilities\n \"get_sm_version\",\n # Reduction utilities\n \"warp_reduce\",\n \"block_reduce\",\n \"row_reduce_sum\",\n \"block_reduce_multirow\",\n \"cluster_reduce_multirow\",\n \"row_reduce_sum_multirow\",\n # Predicate utilities\n \"predicate_k\",\n \"predicate_k_3d\",\n # Configuration helpers\n \"compute_optimal_vec_size\",\n \"compute_threads_per_row\",\n \"make_tv_layout\",\n # Type utilities\n \"_torch_dtype_to_str\",\n # Re-exports from cute_dsl.utils\n \"get_cutlass_dtype\",\n \"get_num_sm\",\n]\n"},"diff":{"kind":"string","value":"--- flashinfer/norm/utils.py\n+++ flashinfer/norm/utils.py\n@@ -25,6 +25,7 @@\n - Type conversion utilities\n \"\"\"\n \n+import functools\n import math\n import operator\n from typing import Callable\n@@ -183,6 +184,124 @@\n )\n \n \n+@dsl_user_op\n+def cvt_and_store_8xf32_to_e4m3_hw(\n+ v0: Float32,\n+ v1: Float32,\n+ v2: Float32,\n+ v3: Float32,\n+ v4: Float32,\n+ v5: Float32,\n+ v6: Float32,\n+ v7: Float32,\n+ addr: Int64,\n+ *,\n+ loc=None,\n+ ip=None,\n+):\n+ \"\"\"Convert 8 float32 values to E4M3 and store as one 64-bit global store (sm_89+).\n+\n+ Uses cvt.rn.satfinite.e4m3x2.f32 to convert pairs, then packs into two b32\n+ words and issues a single st.global.v2.b32. ~4x fewer instructions and ~8x\n+ fewer store transactions compared to 8 scalar st.global.b8 calls.\n+ \"\"\"\n+ llvm.inline_asm(\n+ None,\n+ [\n+ Float32(v0).ir_value(loc=loc, ip=ip),\n+ Float32(v1).ir_value(loc=loc, ip=ip),\n+ Float32(v2).ir_value(loc=loc, ip=ip),\n+ Float32(v3).ir_value(loc=loc, ip=ip),\n+ Float32(v4).ir_value(loc=loc, ip=ip),\n+ Float32(v5).ir_value(loc=loc, ip=ip),\n+ Float32(v6).ir_value(loc=loc, ip=ip),\n+ Float32(v7).ir_value(loc=loc, ip=ip),\n+ Int64(addr).ir_value(loc=loc, ip=ip),\n+ ],\n+ \"\"\"\n+ {\n+ .reg .b16 p01, p23, p45, p67;\n+ .reg .b32 lo, hi;\n+ cvt.rn.satfinite.e4m3x2.f32 p01, $1, $0;\n+ cvt.rn.satfinite.e4m3x2.f32 p23, $3, $2;\n+ cvt.rn.satfinite.e4m3x2.f32 p45, $5, $4;\n+ cvt.rn.satfinite.e4m3x2.f32 p67, $7, $6;\n+ mov.b32 lo, {p01, p23};\n+ mov.b32 hi, {p45, p67};\n+ st.global.v2.b32 [$8], {lo, hi};\n+ }\n+ \"\"\",\n+ \"f,f,f,f,f,f,f,f,l\",\n+ has_side_effects=True,\n+ is_align_stack=False,\n+ asm_dialect=llvm.AsmDialect.AD_ATT,\n+ )\n+\n+\n+@dsl_user_op\n+def cvt_and_store_4xf32_to_e4m3_hw(\n+ v0: Float32,\n+ v1: Float32,\n+ v2: Float32,\n+ v3: Float32,\n+ addr: Int64,\n+ *,\n+ loc=None,\n+ ip=None,\n+):\n+ \"\"\"Convert 4 float32 values to E4M3 and store as one 32-bit global store (sm_89+).\"\"\"\n+ llvm.inline_asm(\n+ None,\n+ [\n+ Float32(v0).ir_value(loc=loc, ip=ip),\n+ Float32(v1).ir_value(loc=loc, ip=ip),\n+ Float32(v2).ir_value(loc=loc, ip=ip),\n+ Float32(v3).ir_value(loc=loc, ip=ip),\n+ Int64(addr).ir_value(loc=loc, ip=ip),\n+ ],\n+ \"\"\"\n+ {\n+ .reg .b16 p01, p23;\n+ .reg .b32 packed;\n+ cvt.rn.satfinite.e4m3x2.f32 p01, $1, $0;\n+ cvt.rn.satfinite.e4m3x2.f32 p23, $3, $2;\n+ mov.b32 packed, {p01, p23};\n+ st.global.b32 [$4], packed;\n+ }\n+ \"\"\",\n+ \"f,f,f,f,l\",\n+ has_side_effects=True,\n+ is_align_stack=False,\n+ asm_dialect=llvm.AsmDialect.AD_ATT,\n+ )\n+\n+\n+@dsl_user_op\n+def cvt_and_store_2xf32_to_e4m3_hw(\n+ v0: Float32, v1: Float32, addr: Int64, *, loc=None, ip=None\n+):\n+ \"\"\"Convert 2 float32 values to E4M3 and store as one 16-bit global store (sm_89+).\"\"\"\n+ llvm.inline_asm(\n+ None,\n+ [\n+ Float32(v0).ir_value(loc=loc, ip=ip),\n+ Float32(v1).ir_value(loc=loc, ip=ip),\n+ Int64(addr).ir_value(loc=loc, ip=ip),\n+ ],\n+ \"\"\"\n+ {\n+ .reg .b16 packed;\n+ cvt.rn.satfinite.e4m3x2.f32 packed, $1, $0;\n+ st.global.b16 [$2], packed;\n+ }\n+ \"\"\",\n+ \"f,f,l\",\n+ has_side_effects=True,\n+ is_align_stack=False,\n+ asm_dialect=llvm.AsmDialect.AD_ATT,\n+ )\n+\n+\n def has_hw_fp8_cvt(device: torch.device = None) -> bool:\n \"\"\"Check if the device supports hardware FP8 conversion (sm_89+).\"\"\"\n if device is None:\n@@ -191,12 +310,81 @@\n return major > 8 or (major == 8 and minor >= 9)\n \n \n+@functools.lru_cache(maxsize=16)\n+def get_sm_version(device=None) -> int:\n+ \"\"\"Get the SM version of a CUDA device (e.g., 100 for SM100).\"\"\"\n+ if not torch.cuda.is_available():\n+ return 80\n+ if device is None:\n+ device = torch.cuda.current_device()\n+ props = torch.cuda.get_device_properties(device)\n+ return props.major * 10 + props.minor\n+\n+\n @dsl_user_op\n def get_ptr_as_int64(tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None) -> Int64:\n \"\"\"Get the memory address of tensor[offset] as Int64.\"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n ptr_int = llvm.ptrtoint(T.i64(), elem_ptr.llvm_ptr, loc=loc, ip=ip)\n return Int64(ptr_int)\n+\n+\n+# =============================================================================\n+# PTX Intrinsics - Cluster Operations (SM90+)\n+# =============================================================================\n+\n+\n+@dsl_user_op\n+def set_block_rank(\n+ smem_ptr: cute.Pointer, peer_cta_rank_in_cluster: Int32, *, loc=None, ip=None\n+) -> Int32:\n+ \"\"\"Map smem pointer to address at another CTA rank in the cluster.\"\"\"\n+ smem_ptr_i32 = smem_ptr.toint(loc=loc, ip=ip).ir_value()\n+ return Int32(\n+ llvm.inline_asm(\n+ T.i32(),\n+ [smem_ptr_i32, peer_cta_rank_in_cluster.ir_value()],\n+ \"mapa.shared::cluster.u32 $0, $1, $2;\",\n+ \"=r,r,r\",\n+ has_side_effects=False,\n+ is_align_stack=False,\n+ asm_dialect=llvm.AsmDialect.AD_ATT,\n+ )\n+ )\n+\n+\n+@dsl_user_op\n+def store_shared_remote(\n+ val: Float32,\n+ smem_ptr: cute.Pointer,\n+ mbar_ptr: cute.Pointer,\n+ peer_cta_rank_in_cluster: Int32,\n+ *,\n+ loc=None,\n+ ip=None,\n+) -> None:\n+ \"\"\"Store Float32 value to shared memory on a remote CTA in the cluster.\"\"\"\n+ remote_smem_ptr_i32 = set_block_rank(\n+ smem_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n+ ).ir_value()\n+ remote_mbar_ptr_i32 = set_block_rank(\n+ mbar_ptr, peer_cta_rank_in_cluster, loc=loc, ip=ip\n+ ).ir_value()\n+ llvm.inline_asm(\n+ None,\n+ [remote_smem_ptr_i32, val.ir_value(loc=loc, ip=ip), remote_mbar_ptr_i32],\n+ \"st.async.shared::cluster.mbarrier::complete_tx::bytes.f32 [$0], $1, [$2];\",\n+ \"r,f,r\",\n+ has_side_effects=True,\n+ is_align_stack=False,\n+ asm_dialect=llvm.AsmDialect.AD_ATT,\n+ )\n+\n+\n+@dsl_user_op\n+def elem_pointer(x: cute.Tensor, coord, *, loc=None, ip=None) -> cute.Pointer:\n+ \"\"\"Get pointer to element at coordinate in tensor.\"\"\"\n+ return x.iterator + cute.crd2idx(coord, x.layout, loc=loc, ip=ip)\n \n \n # =============================================================================\n@@ -259,6 +447,129 @@\n \n if cutlass.const_expr(warps_per_row > 1):\n return block_reduce(warp_val, operator.add, reduction_buffer, Float32(0.0))\n+ else:\n+ return warp_val\n+\n+\n+@cute.jit\n+def block_reduce_multirow(\n+ val: Float32,\n+ op: Callable,\n+ reduction_buffer: cute.Tensor,\n+ init_val: Float32,\n+) -> Float32:\n+ \"\"\"Block reduction with 2D buffer (rows_per_block, warps_per_row).\n+\n+ Each warp writes its partial sum to the row it belongs to, then\n+ lane 0..warps_per_row-1 read back and do a final warp reduction.\n+ \"\"\"\n+ lane_idx = cute.arch.lane_idx()\n+ warp_idx = cute.arch.warp_idx()\n+ warps_per_row = cute.size(reduction_buffer.shape[1])\n+ row_idx = warp_idx // warps_per_row\n+ col_idx = warp_idx % warps_per_row\n+\n+ if lane_idx == 0:\n+ reduction_buffer[row_idx, col_idx] = val\n+ cute.arch.barrier()\n+\n+ block_reduce_val = init_val\n+ if lane_idx < warps_per_row:\n+ block_reduce_val = reduction_buffer[row_idx, lane_idx]\n+ return warp_reduce(block_reduce_val, op)\n+\n+\n+@cute.jit\n+def cluster_reduce_multirow(\n+ val: Float32,\n+ op: Callable,\n+ reduction_buffer: cute.Tensor,\n+ mbar_ptr,\n+ cluster_n: cutlass.Constexpr[int],\n+ init_val: Float32,\n+) -> Float32:\n+ \"\"\"Cluster reduction across multiple CTAs using mbarrier.\n+\n+ reduction_buffer has shape (rows_per_block, (warps_per_row, cluster_n)).\n+ Each warp sends its partial result to all CTAs in the cluster via\n+ st.async.shared::cluster, then every CTA reduces the collected values.\n+ \"\"\"\n+ cta_rank_in_cluster = cute.arch.block_idx_in_cluster()\n+ lane_idx = cute.arch.lane_idx()\n+ warp_idx = cute.arch.warp_idx()\n+\n+ rows_per_block = reduction_buffer.shape[0]\n+ warps_per_row = reduction_buffer.shape[1][0]\n+\n+ row_idx = warp_idx // warps_per_row\n+ col_idx = warp_idx % warps_per_row\n+\n+ if warp_idx == 0:\n+ with cute.arch.elect_one():\n+ num_warps = rows_per_block * warps_per_row\n+ expected_bytes = num_warps * cluster_n * 4\n+ cute.arch.mbarrier_arrive_and_expect_tx(mbar_ptr, expected_bytes)\n+\n+ if lane_idx < cluster_n:\n+ store_shared_remote(\n+ val,\n+ elem_pointer(reduction_buffer, (row_idx, (col_idx, cta_rank_in_cluster))),\n+ mbar_ptr,\n+ peer_cta_rank_in_cluster=lane_idx,\n+ )\n+\n+ cute.arch.mbarrier_wait(mbar_ptr, phase=0)\n+\n+ num_total = warps_per_row * cluster_n\n+ num_iter = cute.ceil_div(num_total, 32)\n+\n+ block_reduce_val = init_val\n+ for i in cutlass.range_constexpr(num_iter):\n+ idx = lane_idx + i * 32\n+ if idx < num_total:\n+ block_reduce_val = op(block_reduce_val, reduction_buffer[row_idx, idx])\n+\n+ return warp_reduce(block_reduce_val, op)\n+\n+\n+@cute.jit\n+def row_reduce_sum_multirow(\n+ x: cute.TensorSSA,\n+ threads_per_row: cutlass.Constexpr[int],\n+ reduction_buffer: cute.Tensor,\n+ mbar_ptr,\n+ cluster_n: cutlass.Constexpr[int],\n+) -> Float32:\n+ \"\"\"Row reduction for sum with optional cluster support.\n+\n+ When cluster_n == 1, uses block-level reduction with 2D buffer\n+ (rows_per_block, warps_per_row). When cluster_n > 1, uses cross-CTA\n+ cluster reduction with hierarchical buffer\n+ (rows_per_block, (warps_per_row, cluster_n)).\n+ \"\"\"\n+ local_val = x.reduce(\n+ cute.ReductionOp.ADD, init_val=Float32(0.0), reduction_profile=0\n+ )\n+\n+ warp_width = min(threads_per_row, 32)\n+ warp_val = warp_reduce(local_val, operator.add, width=warp_width)\n+\n+ warps_per_row = max(threads_per_row // 32, 1)\n+\n+ if cutlass.const_expr(warps_per_row > 1 or cluster_n > 1):\n+ if cutlass.const_expr(cluster_n == 1):\n+ return block_reduce_multirow(\n+ warp_val, operator.add, reduction_buffer, Float32(0.0)\n+ )\n+ else:\n+ return cluster_reduce_multirow(\n+ warp_val,\n+ operator.add,\n+ reduction_buffer,\n+ mbar_ptr,\n+ cluster_n,\n+ Float32(0.0),\n+ )\n else:\n return warp_val\n \n@@ -414,12 +725,24 @@\n \"rcp_approx_ftz\",\n \"cvt_and_store_f32_to_e4m3_hw\",\n \"cvt_and_store_f32_to_e4m3_sw\",\n+ \"cvt_and_store_8xf32_to_e4m3_hw\",\n+ \"cvt_and_store_4xf32_to_e4m3_hw\",\n+ \"cvt_and_store_2xf32_to_e4m3_hw\",\n \"has_hw_fp8_cvt\",\n \"get_ptr_as_int64\",\n+ # PTX intrinsics - Cluster operations\n+ \"set_block_rank\",\n+ \"store_shared_remote\",\n+ \"elem_pointer\",\n+ # Device utilities\n+ \"get_sm_version\",\n # Reduction utilities\n \"warp_reduce\",\n \"block_reduce\",\n \"row_reduce_sum\",\n+ \"block_reduce_multirow\",\n+ \"cluster_reduce_multirow\",\n+ \"row_reduce_sum_multirow\",\n # Predicate utilities\n \"predicate_k\",\n \"predicate_k_3d\","},"lines_added":{"kind":"number","value":323,"string":"323"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":3,"string":"3"},"models_mentioned":{"kind":"list like","value":["gemma"],"string":"[\n \"gemma\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200","H200","SM90"],"string":"[\n \"B200\",\n \"H200\",\n \"SM90\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/norm/utils.py).\n\nGoal: perf: Performance tune cute dsl RMSNorm variants\nTarget hardware: B200, H200, SM90\nTarget models: gemma\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\nShared CuTe DSL Utilities for Norm Kernels\n==========================================\n\nCommon utilities used by all norm kernels:\n- Constants for vectorization and FP8 quantization\n- PTX intrinsics for fast reciprocal and FP8 conversion\n- Warp and block reduction utilities\n- Predicate helpers for bounds checking\n- Layout configuration helpers\n- Type conversion utilities\n\"\"\"\n\nimport math\nimport operator\nfrom typing import Callable\n\nimport cutlass\nimport cutlass.cute as cute\nimport torch\nfrom cutlass import Float32, Int32, Int64\nfrom cutlass.cutlass_dsl import T, dsl_user_op\nfrom cutlass._mlir.dialects import llvm\n\nfrom ..cute_dsl.utils import get_cutlass_dtype, get_num_sm\n\n\n# =============================================================================\n# Constants\n# =============================================================================\n\nFLOAT8_E4M3_MAX = 448.0 # Maximum value representable in FP8 E4M3\nCOPY_BITS = 128 # 128-bit vectorized loads\n\n\n# =============================================================================\n# PTX Intrinsics\n# =============================================================================\n\n\n@dsl_user_op\ndef rcp_approx_ftz(a: Float32, *, loc=None, ip=None) -> Float32:\n \"\"\"Fast reciprocal using PTX rcp.approx.ftz.f32.\"\"\"\n return Float32(\n llvm.inline_asm(\n T.f32(),\n [Float32(a).ir_value(loc=loc, ip=ip)],\n \"rcp.approx.ftz.f32 $0, $1;\",\n \"=f,f\",\n has_side_effects=False,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\n@dsl_user_op\ndef cvt_and_store_f32_to_e4m3_hw(val: Float32, addr: Int64, *, loc=None, ip=None):\n \"\"\"Convert float32 to E4M3 and store single byte — hardware path (sm_89+).\n\n Uses the cvt.rn.satfinite.e4m3x2.f32 PTX instruction for maximum performance.\n \"\"\"\n llvm.inline_asm(\n None,\n [Float32(val).ir_value(loc=loc, ip=ip), Int64(addr).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b16 fp8_pair;\n .reg .f32 zero;\n mov.f32 zero, 0f00000000;\n cvt.rn.satfinite.e4m3x2.f32 fp8_pair, zero, $0;\n st.global.b8 [$1], fp8_pair;\n }\n \"\"\",\n \"f,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\n@dsl_user_op\ndef cvt_and_store_f32_to_e4m3_sw(val: Float32, addr: Int64, *, loc=None, ip=None):\n \"\"\"Convert float32 to E4M3 and store single byte — software path (all architectures).\n\n Uses integer bit manipulation mirroring NVIDIA's __nv_cvt_float_to_fp8 from cuda_fp8.hpp.\n The caller must clamp the value to [-448, 448] before calling this function.\n\n E4M3 format: 1 sign bit, 4 exponent bits (bias=7), 3 mantissa bits.\n Conversion strategy (operates on f32 bit representation):\n - Normal range (f32 biased exp >= 121): direct exponent/mantissa extraction with RNE\n - Denormal range (f32 biased exp in [118..120]): shift mantissa with implicit bit, RNE\n - Underflow (abs <= 2^-10): flush to zero (2^-10 is the RNE midpoint to min denorm)\n \"\"\"\n llvm.inline_asm(\n None,\n [Float32(val).ir_value(loc=loc, ip=ip), Int64(addr).ir_value(loc=loc, ip=ip)],\n \"\"\"\n {\n .reg .b32 fbits, sign8, abs_bits, f32_exp, f32_mant;\n .reg .b32 e4m3_exp, e4m3_mant, norm_raw;\n .reg .b32 rbit, sticky, odd_bit, radj;\n .reg .b32 shift, dmant4, denorm_raw;\n .reg .b32 dr_bit, dsticky, dadj;\n .reg .b32 e4m3_raw, tmp, tmp2;\n .reg .pred p_zero, p_denorm;\n\n // Bitcast float to int and extract sign/exponent/mantissa\n mov.b32 fbits, $0;\n shr.u32 sign8, fbits, 24;\n and.b32 sign8, sign8, 128;\n and.b32 abs_bits, fbits, 0x7FFFFFFF;\n shr.u32 f32_exp, abs_bits, 23;\n and.b32 f32_mant, abs_bits, 0x007FFFFF;\n\n // === Normal path (f32 biased exp >= 121, i.e. e4m3 exp >= 1) ===\n sub.u32 e4m3_exp, f32_exp, 120;\n shr.u32 e4m3_mant, f32_mant, 20;\n shl.b32 norm_raw, e4m3_exp, 3;\n or.b32 norm_raw, norm_raw, e4m3_mant;\n\n // Round-to-nearest-even: round up if round_bit AND (sticky OR odd)\n shr.u32 rbit, f32_mant, 19;\n and.b32 rbit, rbit, 1;\n and.b32 sticky, f32_mant, 0x0007FFFF;\n and.b32 odd_bit, e4m3_mant, 1;\n or.b32 tmp, sticky, odd_bit;\n min.u32 tmp, tmp, 1;\n and.b32 radj, tmp, rbit;\n add.u32 norm_raw, norm_raw, radj;\n min.u32 norm_raw, norm_raw, 126;\n\n // === Denormal path (f32 biased exp in {118,119,120}) ===\n sub.u32 shift, 121, f32_exp;\n shr.u32 tmp, f32_mant, 20;\n or.b32 dmant4, tmp, 8;\n shr.u32 denorm_raw, dmant4, shift;\n\n // RNE rounding for denormals\n sub.u32 tmp, shift, 1;\n shr.u32 dr_bit, dmant4, tmp;\n and.b32 dr_bit, dr_bit, 1;\n shl.b32 tmp2, 1, tmp;\n sub.u32 tmp2, tmp2, 1;\n and.b32 dsticky, dmant4, tmp2;\n and.b32 tmp, f32_mant, 0x000FFFFF;\n or.b32 dsticky, dsticky, tmp;\n and.b32 odd_bit, denorm_raw, 1;\n or.b32 tmp, dsticky, odd_bit;\n min.u32 tmp, tmp, 1;\n and.b32 dadj, tmp, dr_bit;\n add.u32 denorm_raw, denorm_raw, dadj;\n\n // Select between normal/denormal, then apply zero flush\n setp.le.u32 p_denorm, f32_exp, 120;\n selp.u32 e4m3_raw, denorm_raw, norm_raw, p_denorm;\n setp.le.u32 p_zero, abs_bits, 0x3A800000;\n selp.u32 e4m3_raw, 0, e4m3_raw, p_zero;\n\n // Apply sign and store single byte\n or.b32 e4m3_raw, e4m3_raw, sign8;\n st.global.b8 [$1], e4m3_raw;\n }\n \"\"\",\n \"f,l\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n\n\ndef has_hw_fp8_cvt(device: torch.device = None) -> bool:\n \"\"\"Check if the device supports hardware FP8 conversion (sm_89+).\"\"\"\n if device is None:\n device = torch.device(\"cuda\", torch.cuda.current_device())\n major, minor = torch.cuda.get_device_capability(device)\n return major > 8 or (major == 8 and minor >= 9)\n\n\n@dsl_user_op\ndef get_ptr_as_int64(tensor: cute.Tensor, offset: Int32, *, loc=None, ip=None) -> Int64:\n \"\"\"Get the memory address of tensor[offset] as Int64.\"\"\"\n elem_ptr = tensor.iterator + Int32(offset)\n ptr_int = llvm.ptrtoint(T.i64(), elem_ptr.llvm_ptr, loc=loc, ip=ip)\n return Int64(ptr_int)\n\n\n# =============================================================================\n# Warp and Block Reduction Utilities\n# =============================================================================\n\n\n@cute.jit\ndef warp_reduce(val, op, width: cutlass.Constexpr[int] = 32):\n \"\"\"Reduce across threads in a warp using butterfly shuffle.\"\"\"\n if cutlass.const_expr(isinstance(val, cute.TensorSSA)):\n res = cute.make_rmem_tensor(val.shape, val.dtype)\n res.store(val)\n for i in cutlass.range_constexpr(cute.size(val.shape)):\n res[i] = warp_reduce(res[i], op, width)\n return res.load()\n else:\n for i in cutlass.range_constexpr(int(math.log2(width))):\n val = op(val, cute.arch.shuffle_sync_bfly(val, offset=1 << i))\n return val\n\n\n@cute.jit\ndef block_reduce(\n val: Float32,\n op: Callable,\n reduction_buffer: cute.Tensor,\n init_val: Float32,\n) -> Float32:\n \"\"\"Block reduction across multiple warps using shared memory.\"\"\"\n lane_idx = cute.arch.lane_idx()\n warp_idx = cute.arch.warp_idx()\n num_warps = cute.size(reduction_buffer.shape)\n\n if lane_idx == 0:\n reduction_buffer[warp_idx] = val\n cute.arch.barrier()\n\n block_reduce_val = init_val\n if lane_idx < num_warps:\n block_reduce_val = reduction_buffer[lane_idx]\n return warp_reduce(block_reduce_val, op)\n\n\n@cute.jit\ndef row_reduce_sum(\n x: cute.TensorSSA,\n threads_per_row: cutlass.Constexpr[int],\n reduction_buffer: cute.Tensor,\n) -> Float32:\n \"\"\"Row reduction for sum operation.\"\"\"\n local_val = x.reduce(\n cute.ReductionOp.ADD, init_val=Float32(0.0), reduction_profile=0\n )\n\n warp_width = min(threads_per_row, 32)\n warp_val = warp_reduce(local_val, operator.add, width=warp_width)\n\n warps_per_row = max(threads_per_row // 32, 1)\n\n if cutlass.const_expr(warps_per_row > 1):\n return block_reduce(warp_val, operator.add, reduction_buffer, Float32(0.0))\n else:\n return warp_val\n\n\n# =============================================================================\n# Predicate Utility\n# =============================================================================\n\n\n@cute.jit\ndef predicate_k(tXcX: cute.Tensor, limit: int) -> cute.Tensor:\n \"\"\"Create predicate tensor for bounds checking (2D tensors).\"\"\"\n tXpX = cute.make_rmem_tensor(\n cute.make_layout(\n (\n cute.size(tXcX, mode=[0, 1]),\n cute.size(tXcX, mode=[1]),\n cute.size(tXcX, mode=[2]),\n ),\n stride=(cute.size(tXcX, mode=[2]), 0, 1),\n ),\n cutlass.Boolean,\n )\n for rest_v in cutlass.range_constexpr(tXpX.shape[0]):\n for rest_k in cutlass.range_constexpr(tXpX.shape[2]):\n tXpX[rest_v, 0, rest_k] = cute.elem_less(\n tXcX[(0, rest_v), 0, rest_k][1], limit\n )\n return tXpX\n\n\n@cute.jit\ndef predicate_k_3d(tXcX: cute.Tensor, limit: int) -> cute.Tensor:\n \"\"\"Create predicate tensor for bounds checking (3D tensors).\n\n For 3D tensors after local_tile, the last coordinate [2] is the head_dim dimension.\n \"\"\"\n tXpX = cute.make_rmem_tensor(\n cute.make_layout(\n (\n cute.size(tXcX, mode=[0, 1]),\n cute.size(tXcX, mode=[1]),\n cute.size(tXcX, mode=[2]),\n ),\n stride=(cute.size(tXcX, mode=[2]), 0, 1),\n ),\n cutlass.Boolean,\n )\n for rest_v in cutlass.range_constexpr(tXpX.shape[0]):\n for rest_k in cutlass.range_constexpr(tXpX.shape[2]):\n # For 3D tensor, coordinate[2] is the head_dim index\n tXpX[rest_v, 0, rest_k] = cute.elem_less(\n tXcX[(0, rest_v), 0, rest_k][2], limit\n )\n return tXpX\n\n\n# =============================================================================\n# Helper Functions for Kernel Configuration\n# =============================================================================\n\n\ndef compute_optimal_vec_size(H: int, max_vec_size: int) -> int:\n \"\"\"Compute vec_size that maximizes warp utilization.\n\n For small hidden sizes, using max vec_size may result in fewer than 32 threads,\n wasting warp resources. This function finds the largest vec_size that:\n 1. Divides H evenly\n 2. Results in at least 32 threads (one full warp)\n\n Examples:\n - H=128, max=8: vec_size=8 gives 16 threads, vec_size=4 gives 32 threads -> return 4\n - H=4096, max=8: vec_size=8 gives 512 threads -> return 8\n - H=111, max=8: no vec_size divides evenly with >=32 threads, use gcd -> return 1\n \"\"\"\n # Try vec_sizes from largest to smallest\n for vec_size in [\n max_vec_size,\n max_vec_size // 2,\n max_vec_size // 4,\n max_vec_size // 8,\n ]:\n if vec_size < 1:\n continue\n if H % vec_size != 0:\n continue\n threads_needed = H // vec_size\n if threads_needed >= 32:\n return vec_size\n # Fallback: use gcd for correctness (handles odd sizes like 111)\n return math.gcd(max_vec_size, H)\n\n\ndef compute_threads_per_row(H: int, vec_size: int) -> int:\n \"\"\"Compute optimal threads per row based on hidden size.\"\"\"\n threads_needed = (H + vec_size - 1) // vec_size\n # Round up to power of 2, capped at 1024\n threads = 32\n while threads < threads_needed and threads < 1024:\n threads *= 2\n return min(threads, 1024)\n\n\ndef make_tv_layout(threads_per_row: int, vec_size: int, num_vec_blocks: int) -> tuple:\n \"\"\"Create Thread-Value layout for coalesced vectorized memory access.\n\n This layout distributes work across threads where each thread handles\n vec_size consecutive elements, and threads are arranged for coalesced access.\n\n Args:\n threads_per_row: Number of threads processing one row\n vec_size: Number of elements each thread processes per vector load\n num_vec_blocks: Number of vector blocks per row\n\n Returns:\n Tuple of (shape, stride) for creating cute.Layout\n \"\"\"\n shape = (\n (threads_per_row, 1),\n (vec_size, num_vec_blocks),\n )\n stride = (\n (vec_size, 1),\n (1, vec_size * threads_per_row),\n )\n return shape, stride\n\n\n# =============================================================================\n# Type Conversion Utilities\n# =============================================================================\n\n\n# Module-level dict to avoid recreation on each call\n_TORCH_DTYPE_TO_STR_MAP = {\n torch.float16: \"float16\",\n torch.bfloat16: \"bfloat16\",\n torch.float32: \"float32\",\n torch.float8_e4m3fn: \"float8_e4m3fn\",\n}\n\n\ndef _torch_dtype_to_str(dtype: torch.dtype) -> str:\n return _TORCH_DTYPE_TO_STR_MAP[dtype]\n\n\n# Re-export utilities from cute_dsl.utils for convenience\n__all__ = [\n # Constants\n \"FLOAT8_E4M3_MAX\",\n \"COPY_BITS\",\n # PTX intrinsics\n \"rcp_approx_ftz\",\n \"cvt_and_store_f32_to_e4m3_hw\",\n \"cvt_and_store_f32_to_e4m3_sw\",\n \"has_hw_fp8_cvt\",\n \"get_ptr_as_int64\",\n # Reduction utilities\n \"warp_reduce\",\n \"block_reduce\",\n \"row_reduce_sum\",\n # Predicate utilities\n \"predicate_k\",\n \"predicate_k_3d\",\n # Configuration helpers\n \"compute_optimal_vec_size\",\n \"compute_threads_per_row\",\n \"make_tv_layout\",\n # Type utilities\n \"_torch_dtype_to_str\",\n # Re-exports from cute_dsl.utils\n \"get_cutlass_dtype\",\n \"get_num_sm\",\n]\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->\n\nRewrites all CuTe-DSL RMSNorm kernel variants (`rmsnorm`, `gemma_rmsnorm`, `fused_add_rmsnorm`, `gemma_fused_add_rmsnorm`, `rmsnorm_quant`, `fused_add_rmsnorm_quant`, `qk_rmsnorm`, `gemma_qk_rmsnorm`)\n\n**Key changes:**\n* Multi-row blocks with async global-to-shared copy (cpasync): Each thread block processes multiple rows, improving wave utilization and hiding memory latency. Falls back to synchronous copies when alignment or shared memory constraints prevent async usage.\n* Cluster reduction on SM90+: For large hidden sizes (H > max single-CTA capacity), the workload is split across a CTA cluster that reduces partial sums via shared memory, avoiding the need for a single CTA to handle the full row.\n* Vectorized FP8 convert+store PTX intrinsics `cvt.rn.satfinite.e4m3x2.f32`, dramatically improving quantization kernel throughput.\n* Occupancy-aware shared memory management\n* Non-contiguous tensor support without performance loss: Uses dual-path compilation — a compact kernel for contiguous inputs (optimal codegen) and a strided kernel for non-contiguous inputs (symbolic row strides). Runtime dispatch via is_contiguous() ensures zero overhead for the common contiguous case.\n\n\n\n<details>\n <summary>Click to see B200 performance comparison data (Peak 8 TB/s)</summary>\n\n**RMSNorm**\n\nBefore:\n<img width=\"1905\" height=\"1680\" alt=\"before_rmsnorm_bfloat16_NVIDIA_B200\" src=\"https://github.com/user-attachments/assets/15582140-f6df-4794-a4b4-2cc19d252dbb\" />\nAfter\n<img width=\"1905\" height=\"1680\" alt=\"after_heatmap_rmsnorm_bfloat16_NVIDIA_B200\" src=\"https://github.com/user-attachments/assets/0d306806-36d2-4576-a6c2-9f4629f277f8\" />\n\n**QK RMSNorm**\n\nBefore:\n<img width=\"1905\" height=\"1680\" alt=\"before_qk_rmsnorm_bfloat16_NVIDIA_B200\" src=\"https://github.com/user-attachments/assets/71540b32-1df7-4772-94a7-b6b8c71080ee\" />\nAfter:\n<img width=\"1905\" height=\"1680\" alt=\"after_qk_rmsnorm_bfloat16_NVIDIA_B200\" src=\"https://github.com/user-attachments/assets/04e95f62-73fe-43f4-b1a1-95eff234e379\" />\n\n**Add + RMSNorm + FP8 Quantize**\n\nBefore:\n<img width=\"1905\" height=\"1680\" alt=\"before_fused_add_rmsnorm_quant_bfloat16_NVIDIA_B200\" src=\"https://github.com/user-attachments/assets/7bdda617-2d20-4a05-b7fd-2e9e489acba7\" />\nAfter:\n<img width=\"1905\" height=\"1680\" alt=\"after_fused_add_rmsnorm_quant_bfloat16_NVIDIA_B200\" src=\"https://github.com/user-attachments/assets/663fb2a5-45cf-4fab-a74b-dc338d7d8bd0\" />\n\n</details>\n\n<details>\n <summary>Click to see H200 performance comparison data (Peak 4.8 TB/s)</summary>\n\n**RMSNorm**\n\nBefore:\n<img width=\"1905\" height=\"1680\" alt=\"before_rmsnorm_bfloat16_NVIDIA_H200\" src=\"https://github.com/user-attachments/assets/42f63c06-8f6f-4ada-b6fd-e19de4ee32cc\" />\n\nAfter:\n<img width=\"1905\" height=\"1680\" alt=\"after_rmsnorm_bfloat16_NVIDIA_H200\" src=\"https://github.com/user-attachments/assets/ae30fc58-159e-43b6-b108-850bf1711cad\" />\n\n**RMSNorm + FP8 Quantize**\n\nBefore:\n<img width=\"1905\" height=\"1680\" alt=\"before_rmsnorm_quant_bfloat16_NVIDIA_H200\" src=\"https://github.com/user-attachments/assets/52469123-6a5f-459a-ae0b-586a11370ac9\" />\nAfter:\n<img width=\"1905\" height=\"1680\" alt=\"after_rmsnorm_quant_bfloat16_NVIDIA_H200\" src=\"https://github.com/user-attachments/assets/4a229d4a-10ea-4d89-985f-c0378c6554d4\" />\n\n\n**Add + RMSNorm + FP8 Quantize**\n\nBefore:\n<img width=\"1905\" height=\"1680\" alt=\"before_fused_add_rmsnorm_quant_bfloat16_NVIDIA_H200\" src=\"https://github.com/user-attachments/assets/78ac50aa-ae6a-4ea6-a585-0b326279e96b\" />\nAfter:\n<img width=\"1905\" height=\"1680\" alt=\"after_fused_add_rmsnorm_quant_bfloat16_NVIDIA_H200\" src=\"https://github.com/user-attachments/assets/8268ffb8-0ee0-49b7-9353-8d0151002329\" />\n\n</details>\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n#2396 \n\n#2771 \n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * SM-version aware kernels and cluster-based tiling for multi-CTA execution\n * Contiguity-aware selection for compact vs. strided tensor paths\n * Hardware-accelerated FP8/E4M3 conversion and packed storage routines\n * New exposed utilities for device SM queries and cluster-backed reductions\n\n* **Improvements**\n * Async copy paths, expanded shared-memory and cluster-reduction support\n * Per-cluster memory/tiling estimation and improved multi-cluster reduction handling\n * Public APIs now accept an optional SM-version hint and infer/preserve contiguity\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1176,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"4f422f5b4783d73041d9dda8fecc6a17c9d21603"},"date":{"kind":"string","value":"2026-03-03T11:18:05+02:00"},"pr_number":{"kind":"number","value":2667,"string":"2,667"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2667"},"title":{"kind":"string","value":"perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act (#2667)"},"message":{"kind":"string","value":"perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act (#2667)\n\n## 📌 Description\n\nUpdates the trtllm-gen batched GEMM kernel hashes and\n`include/flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export` directory\nfor:\n* Faster batched GEMM kernels\n* Additional NVFP4 tile dims kernels\n* Additional MXFP8 with Relu^2 non-gated activation kernels\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **Chores**\n* Updated an internal batched matrix‑multiplication interface (call\nsignature changed).\n* Refreshed native artifact references and checksums for GPU-accelerated\ncomponents.\n* No end-user behavioral changes expected; these are internal\ncompatibility and maintenance updates.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nSigned-off-by: amitz-nv <203509407+amitz-nv@users.noreply.github.com>\nCo-authored-by: jimmzhou <jimmzhou@nvidia.com>\nCo-authored-by: Jimmy Zhou <79552142+jimmyzho@users.noreply.github.com>\nCo-authored-by: Alex Yang <aleozlx@gmail.com>\nCo-authored-by: Zihao Ye <zihaoye.cs@gmail.com>"},"path":{"kind":"string","value":"csrc/trtllm_batched_gemm_runner.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cstring>\n#include <vector>\n\n#include \"flashinfer/trtllm/batched_gemm/KernelRunner.h\"\n// #include \"tensorrt_llm/common/assert.h\"\n#include \"flashinfer/exception.h\"\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/BatchedGemmInterface.h\"\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/Enums.h\"\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/trtllm/gen/DtypeDecl.h\"\n#include \"flashinfer/trtllm/common.h\"\n#include \"tensorrt_llm/common/cudaUtils.h\"\n#include \"tensorrt_llm/common/envUtils.h\"\n\nnamespace tensorrt_llm {\nnamespace kernels {\n\nusing namespace batchedGemm::batchedGemm;\nusing namespace batchedGemm::gemm;\nusing namespace batchedGemm::trtllm::gen;\n\nstatic BatchedGemmInterface::ModuleCache globalTrtllmGenBatchedGemmModuleCache;\n\nstd::vector<int64_t> prioritizePredefinedConfigs(\n int m, int n, int k, std::vector<int64_t> const& sortedIndices,\n batchedGemm::batchedGemm::BatchedGemmConfig const* configs) {\n // Function to bubble up the pre-determined config.\n auto bubbleUpConfig = [&configs](std::vector<int64_t> const& sortedIndices,\n auto&& pred) -> std::vector<int64_t> {\n std::vector<int64_t> prioritizedIndices_;\n // Copy matching configs to new vector\n std::copy_if(sortedIndices.begin(), sortedIndices.end(),\n std::back_inserter(prioritizedIndices_), [&configs, &pred](int idx) {\n BatchedGemmConfig const& config = configs[idx];\n return (pred(config));\n });\n // Copy the rest of the configs to new vector, if not already copied\n std::copy_if(sortedIndices.begin(), sortedIndices.end(),\n std::back_inserter(prioritizedIndices_), [&prioritizedIndices_](int idx) {\n return std::find(prioritizedIndices_.begin(), prioritizedIndices_.end(), idx) ==\n prioritizedIndices_.end();\n });\n return prioritizedIndices_;\n };\n\n // Init empty vector\n std::vector<int64_t> prioritizedIndices;\n\n //\n // Dummy\n //\n\n if (n /* out_dim */ == 0 && k /* in_dim */ == 0) {\n auto pred = [](BatchedGemmConfig const& config) {\n BatchedGemmOptions const& options = config.mOptions;\n return options.mNumStages == 4 && options.mNumStagesMma == 2 && options.mTileK == 256 &&\n options.mTileScheduler == TileScheduler::Persistent;\n };\n prioritizedIndices = bubbleUpConfig(sortedIndices, pred);\n }\n //\n // Fall back\n //\n else {\n prioritizedIndices = sortedIndices;\n }\n\n return prioritizedIndices;\n}\n\nTrtllmGenBatchedGemmRunner::TrtllmGenBatchedGemmRunner(\n TrtllmGenBatchedGemmRunnerOptions const& options_)\n : mOptions(options_) {\n // Select a GEMM kernel config to use\n auto const bmm = BatchedGemmInterface();\n auto const configs = bmm.getBatchedGemmConfigs();\n\n mPassingConfigIndices.clear();\n\n for (size_t i = 0; i < bmm.getNumBatchedGemmConfigs(); ++i) {\n auto const options = configs[i].mOptions;\n auto const tileSize = mOptions.transposeMmaOutput ? options.mTileN : options.mTileM;\n // When we include low-latency kernels we can set transposeMmaOutput via constructor\n if (options.mDtypeA == mOptions.dtypeA && options.mDtypeB == mOptions.dtypeB &&\n options.mDtypeC == mOptions.dtypeC && options.mUseDeepSeekFp8 == mOptions.deepSeekFp8 &&\n options.mTransposeMmaOutput == mOptions.transposeMmaOutput &&\n (!doesRouteImplUseNoRoute(options.mRouteImpl)) == mOptions.routeAct &&\n options.mFusedAct == mOptions.fusedAct && options.mIsStaticBatch == mOptions.staticBatch &&\n tileSize == mOptions.tileSize && options.mUseShuffledMatrix == mOptions.useShuffledMatrix &&\n options.mLayoutA == mOptions.weightLayout) {\n if (options.mFusedAct) {\n if (options.mActType != static_cast<batchedGemm::gemmGatedAct::ActType>(mOptions.actType)) {\n continue;\n }\n }\n if ((int64_t)options.mEltwiseActType != (int64_t)mOptions.eltwiseActType) {\n continue;\n }\n\n if (mOptions.transposeMmaOutput && options.mEpilogueTileM == mOptions.epilogueTileM) {\n mPassingConfigIndices.push_back(i);\n }\n }\n }\n\n std::ostringstream error_msg;\n error_msg << \"No kernel found for the given options: \"\n << \"mDtypeA: \" << tg::dtypeToString(mOptions.dtypeA)\n << \", mDtypeB: \" << tg::dtypeToString(mOptions.dtypeB)\n << \", mDtypeC: \" << tg::dtypeToString(mOptions.dtypeC)\n << \", mUseDeepSeekFp8: \" << mOptions.deepSeekFp8\n << \", mActType: \" << (int64_t)mOptions.actType\n << \", mEltwiseActType: \" << (int64_t)mOptions.eltwiseActType\n << \", mTransposeMmaOutput: \" << mOptions.transposeMmaOutput\n << \", mRouteAct: \" << mOptions.routeAct << \", mFusedAct: \" << mOptions.fusedAct\n << \", mIsStaticBatch: \" << mOptions.staticBatch << \", mTileSize: \" << mOptions.tileSize;\n FLASHINFER_CHECK(!mPassingConfigIndices.empty(), error_msg.str());\n}\n\nsize_t TrtllmGenBatchedGemmRunner::getWorkspaceSizeInBytes(\n int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,\n int32_t numBatches, int32_t maxNumCtasInBatchDim, int32_t configIndex) const {\n BatchedGemmData gemmData{};\n gemmData.mProblemDimensions.mNumBatches = numBatches;\n gemmData.mProblemDimensions.mNumTokens = numTokens;\n gemmData.mProblemDimensions.mBatchM = !mOptions.transposeMmaOutput;\n gemmData.mProblemDimensions.mBatchedM =\n mOptions.transposeMmaOutput ? std::vector<int32_t>{} : batchedTokens;\n gemmData.mProblemDimensions.mBatchedN =\n mOptions.transposeMmaOutput ? batchedTokens : std::vector<int32_t>{};\n gemmData.mProblemDimensions.mM = mOptions.transposeMmaOutput ? n : m;\n gemmData.mProblemDimensions.mN = mOptions.transposeMmaOutput ? m : n;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;\n\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n\n auto bmm = BatchedGemmInterface();\n\n auto const configs = bmm.getBatchedGemmConfigs();\n\n auto const& config = configs[configIndex];\n\n return bmm.getWorkspaceSizeInBytes(config, gemmData);\n}\n\nvoid TrtllmGenBatchedGemmRunner::run(\n int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,\n int32_t numBatches, int32_t maxNumCtasInBatchDim, void const* a, void const* sfA, void const* b,\n void const* sfB, void const* perTokensSfA, void const* perTokensSfB, float const* scaleC,\n float const* scaleGateC, float const* ptrBias, float const* ptrAlpha, float const* ptrBeta,\n float const* ptrClampLimit, void* c, void* outSfC, int32_t const* routeMap,\n int32_t const* totalNumPaddedTokens, int32_t const* ctaIdxXyToBatchIdx,\n int32_t const* ctaIdxXyToMnLimit, int32_t const* numNonExitingCtas, void* workspace,\n CUstream stream, int device, int32_t configIndex, bool enable_pdl) {\n auto bmm = BatchedGemmInterface();\n\n BatchedGemmData gemmData{};\n\n auto const configs = bmm.getBatchedGemmConfigs();\n\n auto const& config = configs[configIndex];\n // printf(\"running config %d: %s\\n\", configIndex, config.mFunctionName);\n\n FLASHINFER_CHECK(numBatches > 0, \"Batched GEMM requires numBatches > 0\");\n if (!mOptions.staticBatch) {\n FLASHINFER_CHECK(totalNumPaddedTokens,\n \"Batched GEMM with dynamic batching requires totalNumPaddedTokens\");\n FLASHINFER_CHECK(ctaIdxXyToBatchIdx,\n \"Batched GEMM with dynamic batching requires ctaIdxXyToBatchIdx\");\n FLASHINFER_CHECK(ctaIdxXyToMnLimit,\n \"Batched GEMM with dynamic batching requires ctaIdxXyToMnLimit\");\n FLASHINFER_CHECK(numNonExitingCtas,\n \"Batched GEMM with dynamic batching requires numNonExitingCtas\");\n }\n\n if (!mOptions.staticBatch && numTokens != 0) {\n FLASHINFER_CHECK(maxNumCtasInBatchDim > 0,\n \"Batched GEMM with dynamic batching requires maxNumCtasInBatchDim > 0\");\n }\n\n if (mOptions.routeAct) {\n FLASHINFER_CHECK(routeMap, \"Batched GEMM with routeAct requires routeMap\");\n FLASHINFER_CHECK(numTokens > 0, \"Batched GEMM with routeAct requires numTokens > 0\");\n }\n\n // Dims\n gemmData.mProblemDimensions.mNumBatches = numBatches;\n gemmData.mProblemDimensions.mNumTokens = numTokens;\n gemmData.mProblemDimensions.mBatchM = !mOptions.transposeMmaOutput;\n gemmData.mProblemDimensions.mBatchedM =\n mOptions.transposeMmaOutput ? std::vector<int32_t>{} : batchedTokens;\n gemmData.mProblemDimensions.mBatchedN =\n mOptions.transposeMmaOutput ? batchedTokens : std::vector<int32_t>{};\n gemmData.mProblemDimensions.mM = mOptions.transposeMmaOutput ? n : m;\n gemmData.mProblemDimensions.mN = mOptions.transposeMmaOutput ? m : n;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n\n // Inputs\n gemmData.mInputBuffers.mPtrA = mOptions.transposeMmaOutput ? b : a;\n gemmData.mInputBuffers.mPtrSfA = mOptions.transposeMmaOutput ? sfB : sfA;\n gemmData.mInputBuffers.mPtrB = mOptions.transposeMmaOutput ? a : b;\n gemmData.mInputBuffers.mPtrSfB = mOptions.transposeMmaOutput ? sfA : sfB;\n gemmData.mInputBuffers.mPtrScaleC = scaleC;\n gemmData.mInputBuffers.mPtrScaleGate = scaleGateC;\n // For simplicity pass set scaleAct to scaleGateC\n gemmData.mInputBuffers.mPtrScaleAct = scaleGateC;\n gemmData.mInputBuffers.mPtrPerTokenSfA =\n mOptions.transposeMmaOutput ? perTokensSfB : perTokensSfA;\n gemmData.mInputBuffers.mPtrPerTokenSfB =\n mOptions.transposeMmaOutput ? perTokensSfA : perTokensSfB;\n gemmData.mInputBuffers.mPtrBias = ptrBias;\n gemmData.mInputBuffers.mPtrGatedActAlpha = ptrAlpha;\n gemmData.mInputBuffers.mPtrGatedActBeta = ptrBeta;\n gemmData.mInputBuffers.mPtrClampLimit = ptrClampLimit;\n\n gemmData.mInputBuffers.mPtrRouteMap = routeMap;\n\n gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;\n\n // Pointer to total number of padded tokens\n gemmData.mInputBuffers.mPtrTotalNumPaddedTokens = totalNumPaddedTokens;\n gemmData.mInputBuffers.mPtrCtaIdxXyToBatchIdx = ctaIdxXyToBatchIdx;\n gemmData.mInputBuffers.mPtrCtaIdxXyToMnLimit = ctaIdxXyToMnLimit;\n gemmData.mInputBuffers.mPtrNumNonExitingCtas = numNonExitingCtas;\n\n // Outputs\n gemmData.mOutputBuffers.mPtrC = c;\n gemmData.mOutputBuffers.mPtrSfC = outSfC;\n\n int32_t multiProcessorCount;\n cudaDeviceGetAttribute(&multiProcessorCount, cudaDevAttrMultiProcessorCount, device);\n\n // FIXME once we start using all-reduce in the epilogue of the bmm this can be moved elsewhere\n bmm.runInitBeforeWorldSync(config, gemmData, static_cast<void*>(stream));\n\n auto const err = bmm.run(config, workspace, gemmData, static_cast<void*>(stream),\n multiProcessorCount, enable_pdl, globalTrtllmGenBatchedGemmModuleCache);\n\n FLASHINFER_CHECK(err == 0,\n \"Error occurred when running GEMM!\"\n \" (numBatches: \",\n numBatches, \", GemmMNK: \", m, \" \", n, \" \", k, \", Kernel: \", config.mFunctionName,\n \")\");\n}\n\nvoid TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k,\n std::vector<int32_t> const& batchedTokens, void const* a,\n void const* sfA, void const* b, void const* sfB, void* c,\n void* outSfC, void* workspace, CUstream stream, int device,\n int32_t configIndex, bool enable_pdl) {\n // Dispatch with block scaling factors and with static batching.\n run(m, n, k, batchedTokens, /* numTokens */ 0, batchedTokens.size(), /* maxNumCtasInBatchDim */ 0,\n a, sfA, b, sfB,\n /* perTokensSfA */ nullptr, /* perTokensSfB */ nullptr,\n /* scaleC */ nullptr, /* scaleGateC */ nullptr, /* ptrBias */ nullptr, /* ptrAlpha */ nullptr,\n /* ptrBeta */ nullptr, /* ptrClampLimit */ nullptr, c, outSfC,\n /* routeMap */ nullptr, /* totalNumPaddedTokens */ nullptr,\n /* ctaIdxXyToBatchIdx */ nullptr, /* ctaIdxXyToMnLimit */ nullptr,\n /* numNonExitingCtas */ nullptr, workspace, stream, device, configIndex, enable_pdl);\n}\n\nvoid TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k,\n std::vector<int32_t> const& batchedTokens, void const* a,\n void const* sfA, void const* b, void const* sfB,\n float const* ptrBias, float const* ptrAlpha,\n float const* ptrBeta, float const* ptrClampLimit, void* c,\n void* outSfC, void* workspace, CUstream stream, int device,\n int32_t configIndex, bool enable_pdl) {\n // Dispatch with block scaling factors and with static batching.\n run(m, n, k, batchedTokens, /* numTokens */ 0, batchedTokens.size(), /* maxNumCtasInBatchDim */ 0,\n a, sfA, b, sfB,\n /* perTokensSfA */ nullptr, /* perTokensSfB */ nullptr,\n /* scaleC */ nullptr, /* scaleGateC */ nullptr, ptrBias, ptrAlpha, ptrBeta, ptrClampLimit, c,\n outSfC,\n /* routeMap */ nullptr, /* totalNumPaddedTokens */ nullptr,\n /* ctaIdxXyToBatchIdx */ nullptr, /* ctaIdxXyToMnLimit */ nullptr,\n /* numNonExitingCtas */ nullptr, workspace, stream, device, configIndex, enable_pdl);\n}\n\nvoid TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k,\n std::vector<int32_t> const& batchedTokens, void const* a,\n void const* b, float const* scaleC, float const* scaleGateC,\n void* c, void* workspace, CUstream stream, int device,\n int32_t configIndex, bool enable_pdl) {\n // Dispatch with block scaling factors and with static batching.\n run(m, n, k, batchedTokens, /* numTokens */ 0, batchedTokens.size(), /* maxNumCtasInBatchDim */ 0,\n a,\n /* sfA */ nullptr, b, /* sfB */ nullptr, /* perTokensSfA */ nullptr,\n /* perTokensSfB */ nullptr, scaleC, scaleGateC, /* ptrBias */ nullptr, /* ptrAlpha */ nullptr,\n /* ptrBeta */ nullptr, /* ptrClampLimit */ nullptr, c,\n /* outSfC */ nullptr,\n /* routeMap */ nullptr, /* totalNumPaddedTokens */ nullptr,\n /* ctaIdxXyToBatchIdx */ nullptr, /* ctaIdxXyToMnLimit */ nullptr,\n /* numNonExitingCtas */ nullptr, workspace, stream, device, configIndex, enable_pdl);\n}\n\nstd::vector<int64_t> TrtllmGenBatchedGemmRunner::getValidConfigIndices(\n int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,\n int32_t numBatches, int32_t maxNumCtasInBatchDim) const {\n auto const bmm = BatchedGemmInterface();\n auto const configs = bmm.getBatchedGemmConfigs();\n\n int32_t multiProcessorCount = tensorrt_llm::common::getMultiProcessorCount();\n\n BatchedGemmData gemmData{};\n // Dims\n gemmData.mProblemDimensions.mNumBatches = numBatches;\n gemmData.mProblemDimensions.mNumTokens = numTokens;\n gemmData.mProblemDimensions.mBatchM = !mOptions.transposeMmaOutput;\n gemmData.mProblemDimensions.mBatchedM =\n mOptions.transposeMmaOutput ? std::vector<int32_t>{} : batchedTokens;\n gemmData.mProblemDimensions.mBatchedN =\n mOptions.transposeMmaOutput ? batchedTokens : std::vector<int32_t>{};\n gemmData.mProblemDimensions.mM = mOptions.transposeMmaOutput ? n : m;\n gemmData.mProblemDimensions.mN = mOptions.transposeMmaOutput ? m : n;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;\n\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n\n auto cmpFunc = [&configs, &gemmData, &bmm, &multiProcessorCount](int64_t idx0, int64_t idx1) {\n auto const& optionsA = configs[idx0].mOptions;\n auto const& optionsB = configs[idx1].mOptions;\n int32_t sizeK = gemmData.mProblemDimensions.mK;\n\n // Tier 0: K < tileK, prefer higher efficiency.\n if (optionsA.mTileK != optionsB.mTileK) {\n // Both waste computation, prefer higher efficiency.\n if (sizeK <= optionsA.mTileK && sizeK <= optionsB.mTileK) {\n double eff_a = (double)sizeK / optionsA.mTileK;\n double eff_b = (double)sizeK / optionsB.mTileK;\n return eff_a > eff_b;\n }\n // If either can be utilized, sort by tileK.\n else {\n return optionsA.mTileK > optionsB.mTileK;\n }\n }\n\n // Tier 1: When tileK is the same, prefer unroll loop 2x for mma.\n if (optionsA.mUseUnrollLoop2xForMma != optionsB.mUseUnrollLoop2xForMma) {\n return optionsA.mUseUnrollLoop2xForMma;\n }\n\n // Tier 2+: When previous comparators are the same, prefer higher tileM.\n if (optionsA.mTileM != optionsB.mTileM) {\n return optionsA.mTileM > optionsB.mTileM;\n }\n\n // Tier 2+: When previous comparators are the same, prefer higher tileN.\n if (optionsA.mTileN != optionsB.mTileN) {\n return optionsA.mTileN > optionsB.mTileN;\n }\n\n // Tier 2+: When previous comparators are the same, and when the number of estimated CTAs is on\n // the larger side, prefer persistent tile scheduler.\n if (optionsA.mTileScheduler != optionsB.mTileScheduler) {\n auto options = bmm.getOptionsFromConfigAndData(configs[idx0], gemmData);\n auto numCtas = bmm.getNumCtas(options, gemmData.mProblemDimensions.mMaxNumCtasInTokenDim);\n if (numCtas > multiProcessorCount) {\n return optionsA.mTileScheduler == batchedGemm::gemm::TileScheduler::Persistent;\n } else {\n return optionsB.mTileScheduler == batchedGemm::gemm::TileScheduler::Persistent;\n }\n }\n\n return false;\n };\n\n // Sort configs by options.\n std::vector<int64_t> sortedIndices = mPassingConfigIndices;\n std::sort(sortedIndices.begin(), sortedIndices.end(), cmpFunc);\n\n // Special rules for corner cases, if applicable.\n std::vector<int64_t> prioritizedIndices =\n prioritizePredefinedConfigs(m, n, k, sortedIndices, configs);\n\n // Filter out invalid configs.\n std::vector<int64_t> validConfigIndices;\n for (auto const& configIndex : prioritizedIndices) {\n auto isValidConfig = bmm.isValidConfig(configs[configIndex], gemmData);\n if (isValidConfig) {\n validConfigIndices.push_back(configIndex);\n }\n }\n\n FLASHINFER_CHECK(!validConfigIndices.empty(),\n \"No valid config found for the given problem shape\");\n\n return validConfigIndices;\n}\n\nint64_t TrtllmGenBatchedGemmRunner::getDefaultValidConfigIndex(\n int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,\n int32_t numBatches, int32_t maxNumCtasInBatchDim) const {\n auto const validConfigIndices =\n getValidConfigIndices(m, n, k, batchedTokens, numTokens, numBatches, maxNumCtasInBatchDim);\n\n return validConfigIndices[0];\n}\n\nbool TrtllmGenBatchedGemmRunner::isValidConfigIndex(int32_t configIndex, int32_t m, int32_t n,\n int32_t k,\n std::vector<int32_t> const& batchedTokens,\n int32_t numTokens, int32_t numBatches,\n int32_t maxNumCtasInBatchDim) const {\n auto const bmm = BatchedGemmInterface();\n auto const configs = bmm.getBatchedGemmConfigs();\n\n BatchedGemmData gemmData{};\n // Dims\n gemmData.mProblemDimensions.mNumBatches = numBatches;\n gemmData.mProblemDimensions.mNumTokens = numTokens;\n gemmData.mProblemDimensions.mBatchM = !mOptions.transposeMmaOutput;\n gemmData.mProblemDimensions.mBatchedM =\n mOptions.transposeMmaOutput ? std::vector<int32_t>{} : batchedTokens;\n gemmData.mProblemDimensions.mBatchedN =\n mOptions.transposeMmaOutput ? batchedTokens : std::vector<int32_t>{};\n gemmData.mProblemDimensions.mM = mOptions.transposeMmaOutput ? n : m;\n gemmData.mProblemDimensions.mN = mOptions.transposeMmaOutput ? m : n;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n\n auto const& config = configs[configIndex];\n\n return bmm.isValidConfig(config, gemmData);\n}\n\n} // namespace kernels\n} // namespace tensorrt_llm\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cstring>\n#include <vector>\n\n#include \"flashinfer/trtllm/batched_gemm/KernelRunner.h\"\n// #include \"tensorrt_llm/common/assert.h\"\n#include \"flashinfer/exception.h\"\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/BatchedGemmInterface.h\"\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/Enums.h\"\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/trtllm/gen/DtypeDecl.h\"\n#include \"flashinfer/trtllm/common.h\"\n#include \"tensorrt_llm/common/cudaUtils.h\"\n#include \"tensorrt_llm/common/envUtils.h\"\n\nnamespace tensorrt_llm {\nnamespace kernels {\n\nusing namespace batchedGemm::batchedGemm;\nusing namespace batchedGemm::gemm;\nusing namespace batchedGemm::trtllm::gen;\n\nstatic BatchedGemmInterface::ModuleCache globalTrtllmGenBatchedGemmModuleCache;\n\nstd::vector<int64_t> prioritizePredefinedConfigs(\n int m, int n, int k, std::vector<int64_t> const& sortedIndices,\n batchedGemm::batchedGemm::BatchedGemmConfig const* configs) {\n // Function to bubble up the pre-determined config.\n auto bubbleUpConfig = [&configs](std::vector<int64_t> const& sortedIndices,\n auto&& pred) -> std::vector<int64_t> {\n std::vector<int64_t> prioritizedIndices_;\n // Copy matching configs to new vector\n std::copy_if(sortedIndices.begin(), sortedIndices.end(),\n std::back_inserter(prioritizedIndices_), [&configs, &pred](int idx) {\n BatchedGemmConfig const& config = configs[idx];\n return (pred(config));\n });\n // Copy the rest of the configs to new vector, if not already copied\n std::copy_if(sortedIndices.begin(), sortedIndices.end(),\n std::back_inserter(prioritizedIndices_), [&prioritizedIndices_](int idx) {\n return std::find(prioritizedIndices_.begin(), prioritizedIndices_.end(), idx) ==\n prioritizedIndices_.end();\n });\n return prioritizedIndices_;\n };\n\n // Init empty vector\n std::vector<int64_t> prioritizedIndices;\n\n //\n // Dummy\n //\n\n if (n /* out_dim */ == 0 && k /* in_dim */ == 0) {\n auto pred = [](BatchedGemmConfig const& config) {\n BatchedGemmOptions const& options = config.mOptions;\n return options.mNumStages == 4 && options.mNumStagesMma == 2 && options.mTileK == 256 &&\n options.mTileScheduler == TileScheduler::Persistent;\n };\n prioritizedIndices = bubbleUpConfig(sortedIndices, pred);\n }\n //\n // Fall back\n //\n else {\n prioritizedIndices = sortedIndices;\n }\n\n return prioritizedIndices;\n}\n\nTrtllmGenBatchedGemmRunner::TrtllmGenBatchedGemmRunner(\n TrtllmGenBatchedGemmRunnerOptions const& options_)\n : mOptions(options_) {\n // Select a GEMM kernel config to use\n auto const bmm = BatchedGemmInterface();\n auto const configs = bmm.getBatchedGemmConfigs();\n\n mPassingConfigIndices.clear();\n\n for (size_t i = 0; i < bmm.getNumBatchedGemmConfigs(); ++i) {\n auto const options = configs[i].mOptions;\n auto const tileSize = mOptions.transposeMmaOutput ? options.mTileN : options.mTileM;\n // When we include low-latency kernels we can set transposeMmaOutput via constructor\n if (options.mDtypeA == mOptions.dtypeA && options.mDtypeB == mOptions.dtypeB &&\n options.mDtypeC == mOptions.dtypeC && options.mUseDeepSeekFp8 == mOptions.deepSeekFp8 &&\n options.mTransposeMmaOutput == mOptions.transposeMmaOutput &&\n (!doesRouteImplUseNoRoute(options.mRouteImpl)) == mOptions.routeAct &&\n options.mFusedAct == mOptions.fusedAct && options.mIsStaticBatch == mOptions.staticBatch &&\n tileSize == mOptions.tileSize && options.mUseShuffledMatrix == mOptions.useShuffledMatrix &&\n options.mLayoutA == mOptions.weightLayout) {\n if (options.mFusedAct) {\n if (options.mActType != static_cast<batchedGemm::gemmGatedAct::ActType>(mOptions.actType)) {\n continue;\n }\n }\n if ((int64_t)options.mEltwiseActType != (int64_t)mOptions.eltwiseActType) {\n continue;\n }\n\n if (mOptions.transposeMmaOutput && options.mEpilogueTileM == mOptions.epilogueTileM) {\n mPassingConfigIndices.push_back(i);\n }\n }\n }\n\n std::ostringstream error_msg;\n error_msg << \"No kernel found for the given options: \"\n << \"mDtypeA: \" << tg::dtypeToString(mOptions.dtypeA)\n << \", mDtypeB: \" << tg::dtypeToString(mOptions.dtypeB)\n << \", mDtypeC: \" << tg::dtypeToString(mOptions.dtypeC)\n << \", mUseDeepSeekFp8: \" << mOptions.deepSeekFp8\n << \", mActType: \" << (int64_t)mOptions.actType\n << \", mEltwiseActType: \" << (int64_t)mOptions.eltwiseActType\n << \", mTransposeMmaOutput: \" << mOptions.transposeMmaOutput\n << \", mRouteAct: \" << mOptions.routeAct << \", mFusedAct: \" << mOptions.fusedAct\n << \", mIsStaticBatch: \" << mOptions.staticBatch << \", mTileSize: \" << mOptions.tileSize;\n FLASHINFER_CHECK(!mPassingConfigIndices.empty(), error_msg.str());\n}\n\nsize_t TrtllmGenBatchedGemmRunner::getWorkspaceSizeInBytes(\n int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,\n int32_t numBatches, int32_t maxNumCtasInBatchDim, int32_t configIndex) const {\n BatchedGemmData gemmData{};\n gemmData.mProblemDimensions.mNumBatches = numBatches;\n gemmData.mProblemDimensions.mNumTokens = numTokens;\n gemmData.mProblemDimensions.mBatchM = !mOptions.transposeMmaOutput;\n gemmData.mProblemDimensions.mBatchedM =\n mOptions.transposeMmaOutput ? std::vector<int32_t>{} : batchedTokens;\n gemmData.mProblemDimensions.mBatchedN =\n mOptions.transposeMmaOutput ? batchedTokens : std::vector<int32_t>{};\n gemmData.mProblemDimensions.mM = mOptions.transposeMmaOutput ? n : m;\n gemmData.mProblemDimensions.mN = mOptions.transposeMmaOutput ? m : n;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;\n\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n\n auto bmm = BatchedGemmInterface();\n\n auto const configs = bmm.getBatchedGemmConfigs();\n\n auto const& config = configs[configIndex];\n\n return bmm.getWorkspaceSizeInBytes(config, gemmData);\n}\n\nvoid TrtllmGenBatchedGemmRunner::run(\n int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,\n int32_t numBatches, int32_t maxNumCtasInBatchDim, void const* a, void const* sfA, void const* b,\n void const* sfB, void const* perTokensSfA, void const* perTokensSfB, float const* scaleC,\n float const* scaleGateC, float const* ptrBias, float const* ptrAlpha, float const* ptrBeta,\n float const* ptrClampLimit, void* c, void* outSfC, int32_t const* routeMap,\n int32_t const* totalNumPaddedTokens, int32_t const* ctaIdxXyToBatchIdx,\n int32_t const* ctaIdxXyToMnLimit, int32_t const* numNonExitingCtas, void* workspace,\n CUstream stream, int device, int32_t configIndex, bool enable_pdl) {\n auto bmm = BatchedGemmInterface();\n\n BatchedGemmData gemmData{};\n\n auto const configs = bmm.getBatchedGemmConfigs();\n\n auto const& config = configs[configIndex];\n // printf(\"running config %d: %s\\n\", configIndex, config.mFunctionName);\n\n FLASHINFER_CHECK(numBatches > 0, \"Batched GEMM requires numBatches > 0\");\n if (!mOptions.staticBatch) {\n FLASHINFER_CHECK(totalNumPaddedTokens,\n \"Batched GEMM with dynamic batching requires totalNumPaddedTokens\");\n FLASHINFER_CHECK(ctaIdxXyToBatchIdx,\n \"Batched GEMM with dynamic batching requires ctaIdxXyToBatchIdx\");\n FLASHINFER_CHECK(ctaIdxXyToMnLimit,\n \"Batched GEMM with dynamic batching requires ctaIdxXyToMnLimit\");\n FLASHINFER_CHECK(numNonExitingCtas,\n \"Batched GEMM with dynamic batching requires numNonExitingCtas\");\n }\n\n if (!mOptions.staticBatch && numTokens != 0) {\n FLASHINFER_CHECK(maxNumCtasInBatchDim > 0,\n \"Batched GEMM with dynamic batching requires maxNumCtasInBatchDim > 0\");\n }\n\n if (mOptions.routeAct) {\n FLASHINFER_CHECK(routeMap, \"Batched GEMM with routeAct requires routeMap\");\n FLASHINFER_CHECK(numTokens > 0, \"Batched GEMM with routeAct requires numTokens > 0\");\n }\n\n // Dims\n gemmData.mProblemDimensions.mNumBatches = numBatches;\n gemmData.mProblemDimensions.mNumTokens = numTokens;\n gemmData.mProblemDimensions.mBatchM = !mOptions.transposeMmaOutput;\n gemmData.mProblemDimensions.mBatchedM =\n mOptions.transposeMmaOutput ? std::vector<int32_t>{} : batchedTokens;\n gemmData.mProblemDimensions.mBatchedN =\n mOptions.transposeMmaOutput ? batchedTokens : std::vector<int32_t>{};\n gemmData.mProblemDimensions.mM = mOptions.transposeMmaOutput ? n : m;\n gemmData.mProblemDimensions.mN = mOptions.transposeMmaOutput ? m : n;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n\n // Inputs\n gemmData.mInputBuffers.mPtrA = mOptions.transposeMmaOutput ? b : a;\n gemmData.mInputBuffers.mPtrSfA = mOptions.transposeMmaOutput ? sfB : sfA;\n gemmData.mInputBuffers.mPtrB = mOptions.transposeMmaOutput ? a : b;\n gemmData.mInputBuffers.mPtrSfB = mOptions.transposeMmaOutput ? sfA : sfB;\n gemmData.mInputBuffers.mPtrScaleC = scaleC;\n gemmData.mInputBuffers.mPtrScaleGate = scaleGateC;\n // For simplicity pass set scaleAct to scaleGateC\n gemmData.mInputBuffers.mPtrScaleAct = scaleGateC;\n gemmData.mInputBuffers.mPtrPerTokenSfA =\n mOptions.transposeMmaOutput ? perTokensSfB : perTokensSfA;\n gemmData.mInputBuffers.mPtrPerTokenSfB =\n mOptions.transposeMmaOutput ? perTokensSfA : perTokensSfB;\n gemmData.mInputBuffers.mPtrBias = ptrBias;\n gemmData.mInputBuffers.mPtrGatedActAlpha = ptrAlpha;\n gemmData.mInputBuffers.mPtrGatedActBeta = ptrBeta;\n gemmData.mInputBuffers.mPtrClampLimit = ptrClampLimit;\n\n gemmData.mInputBuffers.mPtrRouteMap = routeMap;\n\n gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;\n\n // Pointer to total number of padded tokens\n gemmData.mInputBuffers.mPtrTotalNumPaddedTokens = totalNumPaddedTokens;\n gemmData.mInputBuffers.mPtrCtaIdxXyToBatchIdx = ctaIdxXyToBatchIdx;\n gemmData.mInputBuffers.mPtrCtaIdxXyToMnLimit = ctaIdxXyToMnLimit;\n gemmData.mInputBuffers.mPtrNumNonExitingCtas = numNonExitingCtas;\n\n // Outputs\n gemmData.mOutputBuffers.mPtrC = c;\n gemmData.mOutputBuffers.mPtrSfC = outSfC;\n\n int32_t multiProcessorCount;\n cudaDeviceGetAttribute(&multiProcessorCount, cudaDevAttrMultiProcessorCount, device);\n\n // FIXME once we start using all-reduce in the epilogue of the bmm this can be moved elsewhere\n bmm.runInitBeforeWorldSync(config, gemmData, static_cast<void*>(stream));\n\n auto const err =\n bmm.run(config, workspace, gemmData, static_cast<void*>(stream), multiProcessorCount,\n enable_pdl, /*pinnedHostBuffer=*/nullptr, globalTrtllmGenBatchedGemmModuleCache);\n\n FLASHINFER_CHECK(err == 0,\n \"Error occurred when running GEMM!\"\n \" (numBatches: \",\n numBatches, \", GemmMNK: \", m, \" \", n, \" \", k, \", Kernel: \", config.mFunctionName,\n \")\");\n}\n\nvoid TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k,\n std::vector<int32_t> const& batchedTokens, void const* a,\n void const* sfA, void const* b, void const* sfB, void* c,\n void* outSfC, void* workspace, CUstream stream, int device,\n int32_t configIndex, bool enable_pdl) {\n // Dispatch with block scaling factors and with static batching.\n run(m, n, k, batchedTokens, /* numTokens */ 0, batchedTokens.size(), /* maxNumCtasInBatchDim */ 0,\n a, sfA, b, sfB,\n /* perTokensSfA */ nullptr, /* perTokensSfB */ nullptr,\n /* scaleC */ nullptr, /* scaleGateC */ nullptr, /* ptrBias */ nullptr, /* ptrAlpha */ nullptr,\n /* ptrBeta */ nullptr, /* ptrClampLimit */ nullptr, c, outSfC,\n /* routeMap */ nullptr, /* totalNumPaddedTokens */ nullptr,\n /* ctaIdxXyToBatchIdx */ nullptr, /* ctaIdxXyToMnLimit */ nullptr,\n /* numNonExitingCtas */ nullptr, workspace, stream, device, configIndex, enable_pdl);\n}\n\nvoid TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k,\n std::vector<int32_t> const& batchedTokens, void const* a,\n void const* sfA, void const* b, void const* sfB,\n float const* ptrBias, float const* ptrAlpha,\n float const* ptrBeta, float const* ptrClampLimit, void* c,\n void* outSfC, void* workspace, CUstream stream, int device,\n int32_t configIndex, bool enable_pdl) {\n // Dispatch with block scaling factors and with static batching.\n run(m, n, k, batchedTokens, /* numTokens */ 0, batchedTokens.size(), /* maxNumCtasInBatchDim */ 0,\n a, sfA, b, sfB,\n /* perTokensSfA */ nullptr, /* perTokensSfB */ nullptr,\n /* scaleC */ nullptr, /* scaleGateC */ nullptr, ptrBias, ptrAlpha, ptrBeta, ptrClampLimit, c,\n outSfC,\n /* routeMap */ nullptr, /* totalNumPaddedTokens */ nullptr,\n /* ctaIdxXyToBatchIdx */ nullptr, /* ctaIdxXyToMnLimit */ nullptr,\n /* numNonExitingCtas */ nullptr, workspace, stream, device, configIndex, enable_pdl);\n}\n\nvoid TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k,\n std::vector<int32_t> const& batchedTokens, void const* a,\n void const* b, float const* scaleC, float const* scaleGateC,\n void* c, void* workspace, CUstream stream, int device,\n int32_t configIndex, bool enable_pdl) {\n // Dispatch with block scaling factors and with static batching.\n run(m, n, k, batchedTokens, /* numTokens */ 0, batchedTokens.size(), /* maxNumCtasInBatchDim */ 0,\n a,\n /* sfA */ nullptr, b, /* sfB */ nullptr, /* perTokensSfA */ nullptr,\n /* perTokensSfB */ nullptr, scaleC, scaleGateC, /* ptrBias */ nullptr, /* ptrAlpha */ nullptr,\n /* ptrBeta */ nullptr, /* ptrClampLimit */ nullptr, c,\n /* outSfC */ nullptr,\n /* routeMap */ nullptr, /* totalNumPaddedTokens */ nullptr,\n /* ctaIdxXyToBatchIdx */ nullptr, /* ctaIdxXyToMnLimit */ nullptr,\n /* numNonExitingCtas */ nullptr, workspace, stream, device, configIndex, enable_pdl);\n}\n\nstd::vector<int64_t> TrtllmGenBatchedGemmRunner::getValidConfigIndices(\n int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,\n int32_t numBatches, int32_t maxNumCtasInBatchDim) const {\n auto const bmm = BatchedGemmInterface();\n auto const configs = bmm.getBatchedGemmConfigs();\n\n int32_t multiProcessorCount = tensorrt_llm::common::getMultiProcessorCount();\n\n BatchedGemmData gemmData{};\n // Dims\n gemmData.mProblemDimensions.mNumBatches = numBatches;\n gemmData.mProblemDimensions.mNumTokens = numTokens;\n gemmData.mProblemDimensions.mBatchM = !mOptions.transposeMmaOutput;\n gemmData.mProblemDimensions.mBatchedM =\n mOptions.transposeMmaOutput ? std::vector<int32_t>{} : batchedTokens;\n gemmData.mProblemDimensions.mBatchedN =\n mOptions.transposeMmaOutput ? batchedTokens : std::vector<int32_t>{};\n gemmData.mProblemDimensions.mM = mOptions.transposeMmaOutput ? n : m;\n gemmData.mProblemDimensions.mN = mOptions.transposeMmaOutput ? m : n;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;\n\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n\n auto cmpFunc = [&configs, &gemmData, &bmm, &multiProcessorCount](int64_t idx0, int64_t idx1) {\n auto const& optionsA = configs[idx0].mOptions;\n auto const& optionsB = configs[idx1].mOptions;\n int32_t sizeK = gemmData.mProblemDimensions.mK;\n\n // Tier 0: K < tileK, prefer higher efficiency.\n if (optionsA.mTileK != optionsB.mTileK) {\n // Both waste computation, prefer higher efficiency.\n if (sizeK <= optionsA.mTileK && sizeK <= optionsB.mTileK) {\n double eff_a = (double)sizeK / optionsA.mTileK;\n double eff_b = (double)sizeK / optionsB.mTileK;\n return eff_a > eff_b;\n }\n // If either can be utilized, sort by tileK.\n else {\n return optionsA.mTileK > optionsB.mTileK;\n }\n }\n\n // Tier 1: When tileK is the same, prefer unroll loop 2x for mma.\n if (optionsA.mUseUnrollLoop2xForMma != optionsB.mUseUnrollLoop2xForMma) {\n return optionsA.mUseUnrollLoop2xForMma;\n }\n\n // Tier 2+: When previous comparators are the same, prefer higher tileM.\n if (optionsA.mTileM != optionsB.mTileM) {\n return optionsA.mTileM > optionsB.mTileM;\n }\n\n // Tier 2+: When previous comparators are the same, prefer higher tileN.\n if (optionsA.mTileN != optionsB.mTileN) {\n return optionsA.mTileN > optionsB.mTileN;\n }\n\n // Tier 2+: When previous comparators are the same, and when the number of estimated CTAs is on\n // the larger side, prefer persistent tile scheduler.\n if (optionsA.mTileScheduler != optionsB.mTileScheduler) {\n auto options = bmm.getOptionsFromConfigAndData(configs[idx0], gemmData);\n auto numCtas = bmm.getNumCtas(options, gemmData.mProblemDimensions.mMaxNumCtasInTokenDim);\n if (numCtas > multiProcessorCount) {\n return optionsA.mTileScheduler == batchedGemm::gemm::TileScheduler::Persistent;\n } else {\n return optionsB.mTileScheduler == batchedGemm::gemm::TileScheduler::Persistent;\n }\n }\n\n return false;\n };\n\n // Sort configs by options.\n std::vector<int64_t> sortedIndices = mPassingConfigIndices;\n std::sort(sortedIndices.begin(), sortedIndices.end(), cmpFunc);\n\n // Special rules for corner cases, if applicable.\n std::vector<int64_t> prioritizedIndices =\n prioritizePredefinedConfigs(m, n, k, sortedIndices, configs);\n\n // Filter out invalid configs.\n std::vector<int64_t> validConfigIndices;\n for (auto const& configIndex : prioritizedIndices) {\n auto isValidConfig = bmm.isValidConfig(configs[configIndex], gemmData);\n if (isValidConfig) {\n validConfigIndices.push_back(configIndex);\n }\n }\n\n FLASHINFER_CHECK(!validConfigIndices.empty(),\n \"No valid config found for the given problem shape\");\n\n return validConfigIndices;\n}\n\nint64_t TrtllmGenBatchedGemmRunner::getDefaultValidConfigIndex(\n int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,\n int32_t numBatches, int32_t maxNumCtasInBatchDim) const {\n auto const validConfigIndices =\n getValidConfigIndices(m, n, k, batchedTokens, numTokens, numBatches, maxNumCtasInBatchDim);\n\n return validConfigIndices[0];\n}\n\nbool TrtllmGenBatchedGemmRunner::isValidConfigIndex(int32_t configIndex, int32_t m, int32_t n,\n int32_t k,\n std::vector<int32_t> const& batchedTokens,\n int32_t numTokens, int32_t numBatches,\n int32_t maxNumCtasInBatchDim) const {\n auto const bmm = BatchedGemmInterface();\n auto const configs = bmm.getBatchedGemmConfigs();\n\n BatchedGemmData gemmData{};\n // Dims\n gemmData.mProblemDimensions.mNumBatches = numBatches;\n gemmData.mProblemDimensions.mNumTokens = numTokens;\n gemmData.mProblemDimensions.mBatchM = !mOptions.transposeMmaOutput;\n gemmData.mProblemDimensions.mBatchedM =\n mOptions.transposeMmaOutput ? std::vector<int32_t>{} : batchedTokens;\n gemmData.mProblemDimensions.mBatchedN =\n mOptions.transposeMmaOutput ? batchedTokens : std::vector<int32_t>{};\n gemmData.mProblemDimensions.mM = mOptions.transposeMmaOutput ? n : m;\n gemmData.mProblemDimensions.mN = mOptions.transposeMmaOutput ? m : n;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n\n auto const& config = configs[configIndex];\n\n return bmm.isValidConfig(config, gemmData);\n}\n\n} // namespace kernels\n} // namespace tensorrt_llm\n"},"diff":{"kind":"string","value":"--- csrc/trtllm_batched_gemm_runner.cu\n+++ csrc/trtllm_batched_gemm_runner.cu\n@@ -258,8 +258,9 @@\n // FIXME once we start using all-reduce in the epilogue of the bmm this can be moved elsewhere\n bmm.runInitBeforeWorldSync(config, gemmData, static_cast<void*>(stream));\n \n- auto const err = bmm.run(config, workspace, gemmData, static_cast<void*>(stream),\n- multiProcessorCount, enable_pdl, globalTrtllmGenBatchedGemmModuleCache);\n+ auto const err =\n+ bmm.run(config, workspace, gemmData, static_cast<void*>(stream), multiProcessorCount,\n+ enable_pdl, /*pinnedHostBuffer=*/nullptr, globalTrtllmGenBatchedGemmModuleCache);\n \n FLASHINFER_CHECK(err == 0,\n \"Error occurred when running GEMM!\""},"lines_added":{"kind":"number","value":3,"string":"3"},"lines_removed":{"kind":"number","value":2,"string":"2"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/trtllm_batched_gemm_runner.cu).\n\nGoal: perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cstring>\n#include <vector>\n\n#include \"flashinfer/trtllm/batched_gemm/KernelRunner.h\"\n// #include \"tensorrt_llm/common/assert.h\"\n#include \"flashinfer/exception.h\"\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/BatchedGemmInterface.h\"\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/Enums.h\"\n#include \"flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export/trtllm/gen/DtypeDecl.h\"\n#include \"flashinfer/trtllm/common.h\"\n#include \"tensorrt_llm/common/cudaUtils.h\"\n#include \"tensorrt_llm/common/envUtils.h\"\n\nnamespace tensorrt_llm {\nnamespace kernels {\n\nusing namespace batchedGemm::batchedGemm;\nusing namespace batchedGemm::gemm;\nusing namespace batchedGemm::trtllm::gen;\n\nstatic BatchedGemmInterface::ModuleCache globalTrtllmGenBatchedGemmModuleCache;\n\nstd::vector<int64_t> prioritizePredefinedConfigs(\n int m, int n, int k, std::vector<int64_t> const& sortedIndices,\n batchedGemm::batchedGemm::BatchedGemmConfig const* configs) {\n // Function to bubble up the pre-determined config.\n auto bubbleUpConfig = [&configs](std::vector<int64_t> const& sortedIndices,\n auto&& pred) -> std::vector<int64_t> {\n std::vector<int64_t> prioritizedIndices_;\n // Copy matching configs to new vector\n std::copy_if(sortedIndices.begin(), sortedIndices.end(),\n std::back_inserter(prioritizedIndices_), [&configs, &pred](int idx) {\n BatchedGemmConfig const& config = configs[idx];\n return (pred(config));\n });\n // Copy the rest of the configs to new vector, if not already copied\n std::copy_if(sortedIndices.begin(), sortedIndices.end(),\n std::back_inserter(prioritizedIndices_), [&prioritizedIndices_](int idx) {\n return std::find(prioritizedIndices_.begin(), prioritizedIndices_.end(), idx) ==\n prioritizedIndices_.end();\n });\n return prioritizedIndices_;\n };\n\n // Init empty vector\n std::vector<int64_t> prioritizedIndices;\n\n //\n // Dummy\n //\n\n if (n /* out_dim */ == 0 && k /* in_dim */ == 0) {\n auto pred = [](BatchedGemmConfig const& config) {\n BatchedGemmOptions const& options = config.mOptions;\n return options.mNumStages == 4 && options.mNumStagesMma == 2 && options.mTileK == 256 &&\n options.mTileScheduler == TileScheduler::Persistent;\n };\n prioritizedIndices = bubbleUpConfig(sortedIndices, pred);\n }\n //\n // Fall back\n //\n else {\n prioritizedIndices = sortedIndices;\n }\n\n return prioritizedIndices;\n}\n\nTrtllmGenBatchedGemmRunner::TrtllmGenBatchedGemmRunner(\n TrtllmGenBatchedGemmRunnerOptions const& options_)\n : mOptions(options_) {\n // Select a GEMM kernel config to use\n auto const bmm = BatchedGemmInterface();\n auto const configs = bmm.getBatchedGemmConfigs();\n\n mPassingConfigIndices.clear();\n\n for (size_t i = 0; i < bmm.getNumBatchedGemmConfigs(); ++i) {\n auto const options = configs[i].mOptions;\n auto const tileSize = mOptions.transposeMmaOutput ? options.mTileN : options.mTileM;\n // When we include low-latency kernels we can set transposeMmaOutput via constructor\n if (options.mDtypeA == mOptions.dtypeA && options.mDtypeB == mOptions.dtypeB &&\n options.mDtypeC == mOptions.dtypeC && options.mUseDeepSeekFp8 == mOptions.deepSeekFp8 &&\n options.mTransposeMmaOutput == mOptions.transposeMmaOutput &&\n (!doesRouteImplUseNoRoute(options.mRouteImpl)) == mOptions.routeAct &&\n options.mFusedAct == mOptions.fusedAct && options.mIsStaticBatch == mOptions.staticBatch &&\n tileSize == mOptions.tileSize && options.mUseShuffledMatrix == mOptions.useShuffledMatrix &&\n options.mLayoutA == mOptions.weightLayout) {\n if (options.mFusedAct) {\n if (options.mActType != static_cast<batchedGemm::gemmGatedAct::ActType>(mOptions.actType)) {\n continue;\n }\n }\n if ((int64_t)options.mEltwiseActType != (int64_t)mOptions.eltwiseActType) {\n continue;\n }\n\n if (mOptions.transposeMmaOutput && options.mEpilogueTileM == mOptions.epilogueTileM) {\n mPassingConfigIndices.push_back(i);\n }\n }\n }\n\n std::ostringstream error_msg;\n error_msg << \"No kernel found for the given options: \"\n << \"mDtypeA: \" << tg::dtypeToString(mOptions.dtypeA)\n << \", mDtypeB: \" << tg::dtypeToString(mOptions.dtypeB)\n << \", mDtypeC: \" << tg::dtypeToString(mOptions.dtypeC)\n << \", mUseDeepSeekFp8: \" << mOptions.deepSeekFp8\n << \", mActType: \" << (int64_t)mOptions.actType\n << \", mEltwiseActType: \" << (int64_t)mOptions.eltwiseActType\n << \", mTransposeMmaOutput: \" << mOptions.transposeMmaOutput\n << \", mRouteAct: \" << mOptions.routeAct << \", mFusedAct: \" << mOptions.fusedAct\n << \", mIsStaticBatch: \" << mOptions.staticBatch << \", mTileSize: \" << mOptions.tileSize;\n FLASHINFER_CHECK(!mPassingConfigIndices.empty(), error_msg.str());\n}\n\nsize_t TrtllmGenBatchedGemmRunner::getWorkspaceSizeInBytes(\n int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,\n int32_t numBatches, int32_t maxNumCtasInBatchDim, int32_t configIndex) const {\n BatchedGemmData gemmData{};\n gemmData.mProblemDimensions.mNumBatches = numBatches;\n gemmData.mProblemDimensions.mNumTokens = numTokens;\n gemmData.mProblemDimensions.mBatchM = !mOptions.transposeMmaOutput;\n gemmData.mProblemDimensions.mBatchedM =\n mOptions.transposeMmaOutput ? std::vector<int32_t>{} : batchedTokens;\n gemmData.mProblemDimensions.mBatchedN =\n mOptions.transposeMmaOutput ? batchedTokens : std::vector<int32_t>{};\n gemmData.mProblemDimensions.mM = mOptions.transposeMmaOutput ? n : m;\n gemmData.mProblemDimensions.mN = mOptions.transposeMmaOutput ? m : n;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;\n\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n\n auto bmm = BatchedGemmInterface();\n\n auto const configs = bmm.getBatchedGemmConfigs();\n\n auto const& config = configs[configIndex];\n\n return bmm.getWorkspaceSizeInBytes(config, gemmData);\n}\n\nvoid TrtllmGenBatchedGemmRunner::run(\n int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,\n int32_t numBatches, int32_t maxNumCtasInBatchDim, void const* a, void const* sfA, void const* b,\n void const* sfB, void const* perTokensSfA, void const* perTokensSfB, float const* scaleC,\n float const* scaleGateC, float const* ptrBias, float const* ptrAlpha, float const* ptrBeta,\n float const* ptrClampLimit, void* c, void* outSfC, int32_t const* routeMap,\n int32_t const* totalNumPaddedTokens, int32_t const* ctaIdxXyToBatchIdx,\n int32_t const* ctaIdxXyToMnLimit, int32_t const* numNonExitingCtas, void* workspace,\n CUstream stream, int device, int32_t configIndex, bool enable_pdl) {\n auto bmm = BatchedGemmInterface();\n\n BatchedGemmData gemmData{};\n\n auto const configs = bmm.getBatchedGemmConfigs();\n\n auto const& config = configs[configIndex];\n // printf(\"running config %d: %s\\n\", configIndex, config.mFunctionName);\n\n FLASHINFER_CHECK(numBatches > 0, \"Batched GEMM requires numBatches > 0\");\n if (!mOptions.staticBatch) {\n FLASHINFER_CHECK(totalNumPaddedTokens,\n \"Batched GEMM with dynamic batching requires totalNumPaddedTokens\");\n FLASHINFER_CHECK(ctaIdxXyToBatchIdx,\n \"Batched GEMM with dynamic batching requires ctaIdxXyToBatchIdx\");\n FLASHINFER_CHECK(ctaIdxXyToMnLimit,\n \"Batched GEMM with dynamic batching requires ctaIdxXyToMnLimit\");\n FLASHINFER_CHECK(numNonExitingCtas,\n \"Batched GEMM with dynamic batching requires numNonExitingCtas\");\n }\n\n if (!mOptions.staticBatch && numTokens != 0) {\n FLASHINFER_CHECK(maxNumCtasInBatchDim > 0,\n \"Batched GEMM with dynamic batching requires maxNumCtasInBatchDim > 0\");\n }\n\n if (mOptions.routeAct) {\n FLASHINFER_CHECK(routeMap, \"Batched GEMM with routeAct requires routeMap\");\n FLASHINFER_CHECK(numTokens > 0, \"Batched GEMM with routeAct requires numTokens > 0\");\n }\n\n // Dims\n gemmData.mProblemDimensions.mNumBatches = numBatches;\n gemmData.mProblemDimensions.mNumTokens = numTokens;\n gemmData.mProblemDimensions.mBatchM = !mOptions.transposeMmaOutput;\n gemmData.mProblemDimensions.mBatchedM =\n mOptions.transposeMmaOutput ? std::vector<int32_t>{} : batchedTokens;\n gemmData.mProblemDimensions.mBatchedN =\n mOptions.transposeMmaOutput ? batchedTokens : std::vector<int32_t>{};\n gemmData.mProblemDimensions.mM = mOptions.transposeMmaOutput ? n : m;\n gemmData.mProblemDimensions.mN = mOptions.transposeMmaOutput ? m : n;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n\n // Inputs\n gemmData.mInputBuffers.mPtrA = mOptions.transposeMmaOutput ? b : a;\n gemmData.mInputBuffers.mPtrSfA = mOptions.transposeMmaOutput ? sfB : sfA;\n gemmData.mInputBuffers.mPtrB = mOptions.transposeMmaOutput ? a : b;\n gemmData.mInputBuffers.mPtrSfB = mOptions.transposeMmaOutput ? sfA : sfB;\n gemmData.mInputBuffers.mPtrScaleC = scaleC;\n gemmData.mInputBuffers.mPtrScaleGate = scaleGateC;\n // For simplicity pass set scaleAct to scaleGateC\n gemmData.mInputBuffers.mPtrScaleAct = scaleGateC;\n gemmData.mInputBuffers.mPtrPerTokenSfA =\n mOptions.transposeMmaOutput ? perTokensSfB : perTokensSfA;\n gemmData.mInputBuffers.mPtrPerTokenSfB =\n mOptions.transposeMmaOutput ? perTokensSfA : perTokensSfB;\n gemmData.mInputBuffers.mPtrBias = ptrBias;\n gemmData.mInputBuffers.mPtrGatedActAlpha = ptrAlpha;\n gemmData.mInputBuffers.mPtrGatedActBeta = ptrBeta;\n gemmData.mInputBuffers.mPtrClampLimit = ptrClampLimit;\n\n gemmData.mInputBuffers.mPtrRouteMap = routeMap;\n\n gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;\n\n // Pointer to total number of padded tokens\n gemmData.mInputBuffers.mPtrTotalNumPaddedTokens = totalNumPaddedTokens;\n gemmData.mInputBuffers.mPtrCtaIdxXyToBatchIdx = ctaIdxXyToBatchIdx;\n gemmData.mInputBuffers.mPtrCtaIdxXyToMnLimit = ctaIdxXyToMnLimit;\n gemmData.mInputBuffers.mPtrNumNonExitingCtas = numNonExitingCtas;\n\n // Outputs\n gemmData.mOutputBuffers.mPtrC = c;\n gemmData.mOutputBuffers.mPtrSfC = outSfC;\n\n int32_t multiProcessorCount;\n cudaDeviceGetAttribute(&multiProcessorCount, cudaDevAttrMultiProcessorCount, device);\n\n // FIXME once we start using all-reduce in the epilogue of the bmm this can be moved elsewhere\n bmm.runInitBeforeWorldSync(config, gemmData, static_cast<void*>(stream));\n\n auto const err = bmm.run(config, workspace, gemmData, static_cast<void*>(stream),\n multiProcessorCount, enable_pdl, globalTrtllmGenBatchedGemmModuleCache);\n\n FLASHINFER_CHECK(err == 0,\n \"Error occurred when running GEMM!\"\n \" (numBatches: \",\n numBatches, \", GemmMNK: \", m, \" \", n, \" \", k, \", Kernel: \", config.mFunctionName,\n \")\");\n}\n\nvoid TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k,\n std::vector<int32_t> const& batchedTokens, void const* a,\n void const* sfA, void const* b, void const* sfB, void* c,\n void* outSfC, void* workspace, CUstream stream, int device,\n int32_t configIndex, bool enable_pdl) {\n // Dispatch with block scaling factors and with static batching.\n run(m, n, k, batchedTokens, /* numTokens */ 0, batchedTokens.size(), /* maxNumCtasInBatchDim */ 0,\n a, sfA, b, sfB,\n /* perTokensSfA */ nullptr, /* perTokensSfB */ nullptr,\n /* scaleC */ nullptr, /* scaleGateC */ nullptr, /* ptrBias */ nullptr, /* ptrAlpha */ nullptr,\n /* ptrBeta */ nullptr, /* ptrClampLimit */ nullptr, c, outSfC,\n /* routeMap */ nullptr, /* totalNumPaddedTokens */ nullptr,\n /* ctaIdxXyToBatchIdx */ nullptr, /* ctaIdxXyToMnLimit */ nullptr,\n /* numNonExitingCtas */ nullptr, workspace, stream, device, configIndex, enable_pdl);\n}\n\nvoid TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k,\n std::vector<int32_t> const& batchedTokens, void const* a,\n void const* sfA, void const* b, void const* sfB,\n float const* ptrBias, float const* ptrAlpha,\n float const* ptrBeta, float const* ptrClampLimit, void* c,\n void* outSfC, void* workspace, CUstream stream, int device,\n int32_t configIndex, bool enable_pdl) {\n // Dispatch with block scaling factors and with static batching.\n run(m, n, k, batchedTokens, /* numTokens */ 0, batchedTokens.size(), /* maxNumCtasInBatchDim */ 0,\n a, sfA, b, sfB,\n /* perTokensSfA */ nullptr, /* perTokensSfB */ nullptr,\n /* scaleC */ nullptr, /* scaleGateC */ nullptr, ptrBias, ptrAlpha, ptrBeta, ptrClampLimit, c,\n outSfC,\n /* routeMap */ nullptr, /* totalNumPaddedTokens */ nullptr,\n /* ctaIdxXyToBatchIdx */ nullptr, /* ctaIdxXyToMnLimit */ nullptr,\n /* numNonExitingCtas */ nullptr, workspace, stream, device, configIndex, enable_pdl);\n}\n\nvoid TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k,\n std::vector<int32_t> const& batchedTokens, void const* a,\n void const* b, float const* scaleC, float const* scaleGateC,\n void* c, void* workspace, CUstream stream, int device,\n int32_t configIndex, bool enable_pdl) {\n // Dispatch with block scaling factors and with static batching.\n run(m, n, k, batchedTokens, /* numTokens */ 0, batchedTokens.size(), /* maxNumCtasInBatchDim */ 0,\n a,\n /* sfA */ nullptr, b, /* sfB */ nullptr, /* perTokensSfA */ nullptr,\n /* perTokensSfB */ nullptr, scaleC, scaleGateC, /* ptrBias */ nullptr, /* ptrAlpha */ nullptr,\n /* ptrBeta */ nullptr, /* ptrClampLimit */ nullptr, c,\n /* outSfC */ nullptr,\n /* routeMap */ nullptr, /* totalNumPaddedTokens */ nullptr,\n /* ctaIdxXyToBatchIdx */ nullptr, /* ctaIdxXyToMnLimit */ nullptr,\n /* numNonExitingCtas */ nullptr, workspace, stream, device, configIndex, enable_pdl);\n}\n\nstd::vector<int64_t> TrtllmGenBatchedGemmRunner::getValidConfigIndices(\n int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,\n int32_t numBatches, int32_t maxNumCtasInBatchDim) const {\n auto const bmm = BatchedGemmInterface();\n auto const configs = bmm.getBatchedGemmConfigs();\n\n int32_t multiProcessorCount = tensorrt_llm::common::getMultiProcessorCount();\n\n BatchedGemmData gemmData{};\n // Dims\n gemmData.mProblemDimensions.mNumBatches = numBatches;\n gemmData.mProblemDimensions.mNumTokens = numTokens;\n gemmData.mProblemDimensions.mBatchM = !mOptions.transposeMmaOutput;\n gemmData.mProblemDimensions.mBatchedM =\n mOptions.transposeMmaOutput ? std::vector<int32_t>{} : batchedTokens;\n gemmData.mProblemDimensions.mBatchedN =\n mOptions.transposeMmaOutput ? batchedTokens : std::vector<int32_t>{};\n gemmData.mProblemDimensions.mM = mOptions.transposeMmaOutput ? n : m;\n gemmData.mProblemDimensions.mN = mOptions.transposeMmaOutput ? m : n;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;\n\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n\n auto cmpFunc = [&configs, &gemmData, &bmm, &multiProcessorCount](int64_t idx0, int64_t idx1) {\n auto const& optionsA = configs[idx0].mOptions;\n auto const& optionsB = configs[idx1].mOptions;\n int32_t sizeK = gemmData.mProblemDimensions.mK;\n\n // Tier 0: K < tileK, prefer higher efficiency.\n if (optionsA.mTileK != optionsB.mTileK) {\n // Both waste computation, prefer higher efficiency.\n if (sizeK <= optionsA.mTileK && sizeK <= optionsB.mTileK) {\n double eff_a = (double)sizeK / optionsA.mTileK;\n double eff_b = (double)sizeK / optionsB.mTileK;\n return eff_a > eff_b;\n }\n // If either can be utilized, sort by tileK.\n else {\n return optionsA.mTileK > optionsB.mTileK;\n }\n }\n\n // Tier 1: When tileK is the same, prefer unroll loop 2x for mma.\n if (optionsA.mUseUnrollLoop2xForMma != optionsB.mUseUnrollLoop2xForMma) {\n return optionsA.mUseUnrollLoop2xForMma;\n }\n\n // Tier 2+: When previous comparators are the same, prefer higher tileM.\n if (optionsA.mTileM != optionsB.mTileM) {\n return optionsA.mTileM > optionsB.mTileM;\n }\n\n // Tier 2+: When previous comparators are the same, prefer higher tileN.\n if (optionsA.mTileN != optionsB.mTileN) {\n return optionsA.mTileN > optionsB.mTileN;\n }\n\n // Tier 2+: When previous comparators are the same, and when the number of estimated CTAs is on\n // the larger side, prefer persistent tile scheduler.\n if (optionsA.mTileScheduler != optionsB.mTileScheduler) {\n auto options = bmm.getOptionsFromConfigAndData(configs[idx0], gemmData);\n auto numCtas = bmm.getNumCtas(options, gemmData.mProblemDimensions.mMaxNumCtasInTokenDim);\n if (numCtas > multiProcessorCount) {\n return optionsA.mTileScheduler == batchedGemm::gemm::TileScheduler::Persistent;\n } else {\n return optionsB.mTileScheduler == batchedGemm::gemm::TileScheduler::Persistent;\n }\n }\n\n return false;\n };\n\n // Sort configs by options.\n std::vector<int64_t> sortedIndices = mPassingConfigIndices;\n std::sort(sortedIndices.begin(), sortedIndices.end(), cmpFunc);\n\n // Special rules for corner cases, if applicable.\n std::vector<int64_t> prioritizedIndices =\n prioritizePredefinedConfigs(m, n, k, sortedIndices, configs);\n\n // Filter out invalid configs.\n std::vector<int64_t> validConfigIndices;\n for (auto const& configIndex : prioritizedIndices) {\n auto isValidConfig = bmm.isValidConfig(configs[configIndex], gemmData);\n if (isValidConfig) {\n validConfigIndices.push_back(configIndex);\n }\n }\n\n FLASHINFER_CHECK(!validConfigIndices.empty(),\n \"No valid config found for the given problem shape\");\n\n return validConfigIndices;\n}\n\nint64_t TrtllmGenBatchedGemmRunner::getDefaultValidConfigIndex(\n int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,\n int32_t numBatches, int32_t maxNumCtasInBatchDim) const {\n auto const validConfigIndices =\n getValidConfigIndices(m, n, k, batchedTokens, numTokens, numBatches, maxNumCtasInBatchDim);\n\n return validConfigIndices[0];\n}\n\nbool TrtllmGenBatchedGemmRunner::isValidConfigIndex(int32_t configIndex, int32_t m, int32_t n,\n int32_t k,\n std::vector<int32_t> const& batchedTokens,\n int32_t numTokens, int32_t numBatches,\n int32_t maxNumCtasInBatchDim) const {\n auto const bmm = BatchedGemmInterface();\n auto const configs = bmm.getBatchedGemmConfigs();\n\n BatchedGemmData gemmData{};\n // Dims\n gemmData.mProblemDimensions.mNumBatches = numBatches;\n gemmData.mProblemDimensions.mNumTokens = numTokens;\n gemmData.mProblemDimensions.mBatchM = !mOptions.transposeMmaOutput;\n gemmData.mProblemDimensions.mBatchedM =\n mOptions.transposeMmaOutput ? std::vector<int32_t>{} : batchedTokens;\n gemmData.mProblemDimensions.mBatchedN =\n mOptions.transposeMmaOutput ? batchedTokens : std::vector<int32_t>{};\n gemmData.mProblemDimensions.mM = mOptions.transposeMmaOutput ? n : m;\n gemmData.mProblemDimensions.mN = mOptions.transposeMmaOutput ? m : n;\n gemmData.mProblemDimensions.mK = k;\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n gemmData.mProblemDimensions.mRank = 0;\n gemmData.mProblemDimensions.mWorldSize = 1;\n gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;\n gemmData.mProblemDimensions.mValidM = gemmData.mProblemDimensions.mM;\n gemmData.mProblemDimensions.mValidN = gemmData.mProblemDimensions.mN;\n gemmData.mProblemDimensions.mValidK = gemmData.mProblemDimensions.mK;\n\n auto const& config = configs[configIndex];\n\n return bmm.isValidConfig(config, gemmData);\n}\n\n} // namespace kernels\n} // namespace tensorrt_llm\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## 📌 Description\n\nUpdates the trtllm-gen batched GEMM kernel hashes and `include/flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export` directory for:\n* Faster batched GEMM kernels\n* Additional NVFP4 tile dims kernels\n* Additional MXFP8 with Relu^2 non-gated activation kernels\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Chores**\n * Updated an internal batched matrix‑multiplication interface (call signature changed).\n * Refreshed native artifact references and checksums for GPU-accelerated components.\n * No end-user behavioral changes expected; these are internal compatibility and maintenance updates.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1177,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"1589ebb405b437dab5a3b0ca3b77097da0959071"},"date":{"kind":"string","value":"2026-02-26T11:08:00-08:00"},"pr_number":{"kind":"number","value":2588,"string":"2,588"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2588"},"title":{"kind":"string","value":"Perf: Optimize GDN decode pretranspose kernel for all batch sizes (#2588)"},"message":{"kind":"string","value":"Perf: Optimize GDN decode pretranspose kernel for all batch sizes (#2588)\n\nTwo optimizations:\n\n1. Early gate reads: Move gate GMEM reads (r_A_log, r_a, r_dt_bias, r_b)\nto immediately before the barrier, hiding memory latency during sync.\n\n2. Always use 8-CTA architecture: Remove batch size conditional that\nswitched to big_batch (1 CTA) for B > 32. The 8-CTA small_batch kernel\nperforms better for ALL batch sizes.\n\nBenchmark results (1000 iters, warmup=10, q_heads=16, k_heads=16,\nv_heads=32, head_size=128, bfloat16, qk_l2norm=ON):\n\n| Batch | Before (us) | After (us) | Improvement |\n|-------|-------------|------------|-------------|\n| 1 | 3.74 | 3.74 | ~same |\n| 2 | 4.22 | 4.22 | ~same |\n| 4 | 5.38 | 5.38 | ~same |\n| 8 | 7.68 | 7.65 | ~same |\n| 16 | 12.90 | 12.90 | ~same |\n| 32 | 23.04 | 23.04 | ~same |\n| 64 | 51.57 | 42.56 | ~17% |\n| 128 | 92.13 | 81.31 | ~12% |\n| 256 | 170.18 | 158.98 | ~7% |\n| 512 | 334.21 | 314.05 | ~6% |\n\nCorrectness verified on all batch sizes (1, 2, 4, 8, 16, 32, 64, 128,\n256, 512).\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n<!-- What does this PR do? Briefly describe the changes and why they’re\nneeded. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [ ] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **Refactor**\n* Optimized GPU kernel memory management sequences in decoding\noperations with improved synchronization and data loading patterns\n* Consolidated kernel execution logic by unifying batch-size handling,\nremoving conditional branching for more consistent performance\n* Enhanced thread-level resource efficiency through refined writeback\noperations in the decoding pipeline\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\nSigned-off-by: Amey Naik <212485788+ameynaik-hub@users.noreply.github.com>\nCo-authored-by: Claude Opus 4.5 <noreply@anthropic.com>"},"path":{"kind":"string","value":"flashinfer/gdn_decode.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\n\"\"\"\nGated Delta Rule Decode Kernel - Single Token Generation\n\nThis file implements a fused CUDA kernel using CUTLASS CuTe DSL for executing\nSigmoid Gating Delta Rule updates during decode phase. Key features:\n\nArchitecture Design:\n- Uses TMA (Tensor Memory Accelerator) for efficient Global Memory → Shared Memory transfers\n- Employs 2-stage pipeline to overlap loading and computation, hiding memory latency\n- Each block uses 128 threads (4 warps), with each warp processing one matrix row\n- Tile size: 8x128 (TILE_V x TILE_K)\n\nComputation Flow:\n1. Warp 0 handles TMA prefetch, loading data from GMEM to SMEM\n2. All warps compute in parallel: softplus, L2 normalization, delta rule updates\n3. Each warp processes one row of data, completing h_new = g*h + k*(beta*(v - h@k))\n4. Uses warp-level shuffle for efficient reduction operations\n5. Results are vectorized and written back to Global Memory\n\nPerformance Optimizations:\n- Vectorized memory access: each thread processes vec_size=4 elements (128-bit aligned)\n- Warp-level collective operations: shuffle-based reduction\n- Pipeline overlap: load stage N+1 while computing stage N\n\"\"\"\n\nimport functools\nfrom typing import Optional, Tuple\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass.cute.nvgpu import cpasync\nfrom cutlass.cute.runtime import from_dlpack\nimport cuda.bindings.driver as cuda\n\ntry:\n from .api_logging import flashinfer_api\n\n _FLASHINFER_AVAILABLE = True\nexcept ImportError:\n _FLASHINFER_AVAILABLE = False\n\n # Fallback decorator for standalone usage\n def flashinfer_api(func): # type: ignore[misc]\n return func\n\n\n# GDN decode K-last bf16 state kernel (T=1..4, bf16 state, K-last layout) - optional backend\ntry:\n from .gdn_kernels.gdn_decode_bf16_state import (\n gated_delta_rule as _gated_delta_rule_gdn_decode_klast_bf16_state,\n )\n\n _GDN_DECODE_KLAST_BF16_STATE_AVAILABLE = True\nexcept ImportError:\n _GDN_DECODE_KLAST_BF16_STATE_AVAILABLE = False\n _gated_delta_rule_gdn_decode_klast_bf16_state = None\n\n\n# ============================================================================\n# Global configuration for PRETRANSPOSE version ([B*HV, V, K])\n# ============================================================================\nTILE_V = 8\nTILE_K = 128\nNUM_STAGES = 2\nNUM_THREADS = 128 # 4 warps\nNUM_BLOCKS_PER_STATE = 8\n\n# ============================================================================\n# Global configuration for NONTRANSPOSE version ([pool, HV, K, V])\n# ============================================================================\nTILE_K_NT = 128\nTILE_V_NT = 32\nTILE_V_PADDED_NT = 36\nTILE_V_SMALL_NT = 16\nTILE_V_SMALL_PADDED_NT = 20\nNUM_STAGES_NT = 2\nNUM_THREADS_NT = 128\nNUM_BLOCKS_PER_STATE_SMALL_NT = 8\nNUM_THREADS_LARGE_NT = 256\nNUM_WARPS_LARGE_NT = 8\nV_PER_WARP_NT = 4\nROWS_PER_ITER_NT = 8\nNUM_K_ITERS_NT = TILE_K_NT // ROWS_PER_ITER_NT\nSMALL_BATCH_THRESHOLD_NT = 32\n\n# ============================================================================\n# Global configuration for MTP (Multiple Token Processing) version\n# ============================================================================\n# Dynamic kernel selection based on batch size:\n# - Small batch (B <= threshold): Use smaller TILE_V for more parallelism\n# Optimal TILE_V depends on batch size (empirically determined):\n# B=1-2: TILE_V=4 (more blocks, better parallelism for tiny batches)\n# B=4: TILE_V=8 (intermediate parallelism)\n# B=8: TILE_V=16 (balance between parallelism and efficiency)\n# B>=16: TILE_V=32 (fewer blocks, better efficiency for large batches)\n\nTILE_K_MTP = 128 # Full K dimension (shared across all configs)\nNUM_THREADS_MTP = 128 # 4 warps (shared across all configs)\n\n\ndef get_vec_size_mtp(batch_size: int, seq_len: int = 1) -> int:\n \"\"\"Select vec_size for MTP kernel.\n\n Always use vec_size=4 (32 threads per group = full warp, 4 groups per block).\n Full warp shuffle is more efficient and achieves >= 1.0x speedup vs Triton.\n \"\"\"\n return 4\n\n\ndef get_tile_v_mtp(batch_size: int, seq_len: int = 1) -> int:\n \"\"\"Select optimal TILE_V for MTP kernel based on batch size and sequence length.\n\n With vec_size=4, num_groups=4, rows_per_group = tile_v / 4.\n Tuned via grid search for optimal performance.\n \"\"\"\n if batch_size <= 2:\n return 4 # Small batch needs max parallelism\n elif batch_size <= 4:\n return 8\n elif batch_size <= 8:\n return 16\n elif batch_size <= 16:\n return 32\n else:\n return 64\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n cute.arch.barrier()\n\n # Get current batch\n gSrc_batch = h0_source[(batch_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (batch_idx, None, 0))\n\n # V 方向分 tiles\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n start_v_tiles = batch_inner * num_v_tiles_per_block\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles_per_block)\n for v_tiles in range(start_v_tiles, start_v_tiles + prefetch_count):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n end_v_tiles = start_v_tiles + num_v_tiles_per_block\n for v_tiles in range(start_v_tiles, end_v_tiles):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < end_v_tiles:\n next_stage = (next_v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n gDst_tile = cute.local_tile(\n gDst, (1, 1, vec_size, 1), (0, row + row_offset, lane_id, v_tiles)\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n if tidx >= start_v_tiles * TILE_V and tidx < end_v_tiles * TILE_V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n cute.arch.barrier()\n\n # Get current batch\n gSrc_batch = h0_source[(batch_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (batch_idx, None, 0))\n\n # V 方向分 tiles\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles)\n for v_tiles in range(prefetch_count):\n stage = v_tiles % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n for v_tiles in range(num_v_tiles):\n stage = v_tiles % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < num_v_tiles:\n next_stage = next_v_tiles % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n gDst_tile = cute.local_tile(\n gDst, (1, 1, vec_size, 1), (0, row + row_offset, lane_id, v_tiles)\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n \"\"\"Launch original pipelined kernel for small batch pretranspose.\"\"\"\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * batch_size * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n ).launch(\n grid=(batch_size * NUM_BLOCKS_PER_STATE, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * batch_size * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # print(f\"Batched CP.ASYNC Load + Store (bypass L1 cache)\")\n # print(f\" {batch_size} batches x {v_dim}x{k_dim} matrices\")\n # print(f\" Tile: {TILE_V}x{TILE_K}, {num_v_tiles} tiles/batch\")\n # print(f\" Threads: {NUM_THREADS} ({NUM_THREADS // 32} warps), vec_size: {vec_size}\")\n # print(f\" Total: {total_data_mb:.1f} MB\\n\")\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# FlashInfer API Layer\n# ============================================================================\n\n\n@functools.cache\ndef _get_compiled_decode_kernel(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled kernel for given configuration (pretranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\n@functools.cache\ndef _get_compiled_decode_kernel_nontranspose(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled kernel for given configuration (nontranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\n@flashinfer_api\ndef gated_delta_rule_decode_pretranspose(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n state: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Gated Delta Rule Decode kernel for single-token generation.\n\n This implements the decode phase of gated delta rule linear attention,\n processing one token at a time and updating the recurrent state.\n\n Args:\n q (torch.Tensor):\n Current query of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n k (torch.Tensor):\n Current key of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n v (torch.Tensor):\n Current value of shape ``[B, 1, HV, V]``. Must be float16/bfloat16.\n state (torch.Tensor):\n Current state of shape ``[B, HV, V, K]`` (v-major / K-last layout).\n Float32: legacy kernel (T=1 only). Bfloat16: gdn_decode_klast_bf16_state backend\n when T in 1..4 and K=V=128. Will be updated in-place.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``. Must be float32.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``. Must be bfloat16 or float32.\n b (torch.Tensor):\n Update gate (beta) input of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n scale (Optional[float]):\n Scale factor for queries. If None, defaults to ``1 / sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, 1, HV, V]``.\n If None, will be allocated automatically.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, 1, HV, V]``\n - state: Updated state tensor of shape ``[B, HV, V, K]``\n\n Note:\n - Requires SM90 (Hopper) architecture\n - State is updated in-place\n - State layout is v-major (K-last): [B, HV, V, K]. When state is bfloat16\n and T in 1..4 with K=V=128, the gdn_decode_klast_bf16_state kernel is used.\n - Legacy path (float32 state, T=1): K and V must be multiples of 4.\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n _, _, HV, V = v.shape\n\n # Validate state shape (Qwen-style K-last: [B, HV, V, K])\n assert state.shape == (B, HV, V, K), (\n f\"Expected state shape [B={B}, HV={HV}, V={V}, K={K}], got {state.shape}\"\n )\n\n # Backend: gdn_decode_klast_bf16_state when bf16 state, T<=4, K-last layout, K=V=128\n use_gdn_decode_klast_bf16_state = (\n _GDN_DECODE_KLAST_BF16_STATE_AVAILABLE\n and state.dtype == torch.bfloat16\n and T in (1, 2, 3, 4)\n and K == 128\n and V == 128\n )\n if use_gdn_decode_klast_bf16_state:\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n scale_val = K**-0.5 if scale is None else scale\n out = _gated_delta_rule_gdn_decode_klast_bf16_state(\n A_log=A_log,\n a=a,\n dt_bias=dt_bias,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n q=q,\n k=k,\n v=v,\n b=b,\n initial_state_source=state,\n use_qk_l2norm_in_kernel=use_qk_l2norm,\n scale=scale_val,\n )\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n if output is not None:\n output.copy_(out)\n else:\n output = out\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n return output, state\n\n # Legacy path: T=1 only, float32 state\n assert T == 1, f\"Decode only supports T=1, got T={T}\"\n assert state.dtype == torch.float32, f\"state must be float32, got {state.dtype}\"\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n assert V % TILE_V == 0, (\n f\"V must be divisible by {TILE_V} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n # Note: kernel outputs bfloat16, we'll convert to q.dtype if needed\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # Convert state from [B, HV, V, K] to [B*HV, V, K] for kernel\n h0_source = state.reshape(B * HV, V, K)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel(*cache_key)\n\n # Get or create h0_indices and cu_seqlens (cached per config)\n if \"h0_indices\" not in cache or cache[\"h0_indices\"].device != q.device:\n cache[\"h0_indices\"] = torch.zeros(B, dtype=torch.int32, device=q.device)\n cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n h0_indices = cache[\"h0_indices\"]\n cu_seqlens = cache[\"cu_seqlens\"]\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Choose kernel based on batch size\n if B <= 32:\n run_func = run_gdn_decode_kernel_small_batch_pretranspose\n else:\n run_func = run_gdn_decode_kernel_big_batch_pretranspose\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n h0_source_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n B=B,\n T=T,\n H=H,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n cache[\"compiled\"](\n h0_source, A_log, a, dt_bias, q, k, v, b, output, h0_indices, cu_seqlens, stream\n )\n\n # Copy state back only if state was not contiguous\n # (if contiguous, reshape returns a view and kernel updated state in-place)\n if not state.is_contiguous():\n state.copy_(h0_source.reshape(B, HV, V, K))\n\n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, state\n\n\n# ============================================================================\n# NONTRANSPOSE Version Kernels - K-major layout [pool, HV, K, V]\n# ============================================================================\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_nontranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n num_v_tiles: cutlass.Constexpr[int],\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n use_qk_l2norm: cutlass.Constexpr[bool],\n):\n \"\"\"Small batch kernel for (N, 1, ...) format with K-major state layout.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n in_warp_tid = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n\n NUM_WARPS_SMALL = 4\n V_PER_WARP_SMALL = TILE_V_SMALL_NT // NUM_WARPS_SMALL\n ROWS_PER_ITER_SMALL = 32 // V_PER_WARP_SMALL\n NUM_K_ITERS_SMALL = TILE_K_NT // ROWS_PER_ITER_SMALL\n\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE_SMALL_NT\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE_SMALL_NT\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE_SMALL_NT\n start_v_tile = batch_inner * num_v_tiles_per_block\n\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n pool_idx = h0_indices[i_n]\n\n if pool_idx >= 0:\n k_local = in_warp_tid // V_PER_WARP_SMALL\n v_local = in_warp_tid % V_PER_WARP_SMALL\n v_base = warp_idx * V_PER_WARP_SMALL\n v_idx = v_base + v_local\n\n smem = cutlass.utils.SmemAllocator()\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n smem_o_layout = cute.make_layout((TILE_V_SMALL_NT,), stride=(1,))\n smem_o = smem.allocate_tensor(cutlass.Float32, smem_o_layout, 128)\n smem_k_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n smem_q_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n sK = smem.allocate_tensor(cutlass.Float32, smem_k_layout, 128)\n sQ = smem.allocate_tensor(cutlass.Float32, smem_q_layout, 128)\n\n if tidx < TILE_K_NT:\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n\n # Compute flat index for flattened state [B*HV, K, V]\n flat_idx = pool_idx * HV + i_hv\n gSrc_batch = h0_source[(flat_idx, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_SMALL_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n prefetch_count = cutlass.min(NUM_STAGES_NT - 1, num_v_tiles_per_block)\n for v_tile_offset in range(prefetch_count):\n v_tile = start_v_tile + v_tile_offset\n stage = v_tile_offset % NUM_STAGES_NT\n gSrc_tile = gSrc[(None, None, v_tile)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_a = cutlass.Float32(a[i_n, 0, i_hv])\n r_b = cutlass.Float32(b[i_n, 0, i_hv])\n\n r_g = 0.0\n r_beta = 0.0\n if in_warp_tid == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n cute.arch.barrier()\n\n if use_qk_l2norm:\n sum_q_partial = 0.0\n sum_k_partial = 0.0\n if tidx < TILE_K_NT:\n q_val = sQ[tidx]\n k_val = sK[tidx]\n sum_q_partial = q_val * q_val\n sum_k_partial = k_val * k_val\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q_partial += cute.arch.shuffle_sync_bfly(\n sum_q_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k_partial += cute.arch.shuffle_sync_bfly(\n sum_k_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n if in_warp_tid == 0:\n smem_o[warp_idx] = sum_q_partial\n smem_o[warp_idx + 4] = sum_k_partial\n cute.arch.barrier()\n\n inv_norm_q = 0.0\n inv_norm_k = 0.0\n if warp_idx == 0:\n local_sum_q = 0.0\n local_sum_k = 0.0\n if in_warp_tid < NUM_WARPS_SMALL:\n local_sum_q = smem_o[in_warp_tid]\n local_sum_k = smem_o[in_warp_tid + 4]\n for offset in [2, 1]:\n local_sum_q += cute.arch.shuffle_sync_bfly(\n local_sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n local_sum_k += cute.arch.shuffle_sync_bfly(\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n smem_o[0] = cute.rsqrt(local_sum_q + 1e-6, fastmath=True)\n smem_o[1] = cute.rsqrt(local_sum_k + 1e-6, fastmath=True)\n cute.arch.barrier()\n\n inv_norm_q = smem_o[0]\n inv_norm_k = smem_o[1]\n\n if tidx < TILE_K_NT:\n sK[tidx] = sK[tidx] * inv_norm_k\n sQ[tidx] = sQ[tidx] * scale * inv_norm_q\n cute.arch.barrier()\n else:\n if tidx < TILE_K_NT:\n sQ[tidx] = sQ[tidx] * scale\n cute.arch.barrier()\n\n for v_tile_offset in range(num_v_tiles_per_block):\n v_tile = start_v_tile + v_tile_offset\n stage = v_tile_offset % NUM_STAGES_NT\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n next_v_tile_offset = v_tile_offset + prefetch_count\n if next_v_tile_offset < num_v_tiles_per_block:\n next_v_tile = start_v_tile + next_v_tile_offset\n next_stage = next_v_tile_offset % NUM_STAGES_NT\n gSrc_next = gSrc[(None, None, next_v_tile)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n v_global = v_tile * TILE_V_SMALL_NT + v_idx\n r_v = cutlass.Float32(v[i_n, 0, i_hv, v_global])\n\n sum_hk = 0.0\n for k_iter in range(NUM_K_ITERS_SMALL, unroll=16): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_SMALL\n k_idx = k_base + k_local\n h_val = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n sum_hk += h_val * r_k_val\n\n for offset in [4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk,\n offset=offset * V_PER_WARP_SMALL,\n mask=-1,\n mask_and_clamp=31,\n )\n\n v_new = (r_v - sum_hk) * r_beta\n v_new = cute.arch.shuffle_sync(v_new, v_local)\n\n sum_hq = 0.0\n for k_iter in range(NUM_K_ITERS_SMALL, unroll=16): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_SMALL\n k_idx = k_base + k_local\n h_old = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n r_q_val = sQ[k_idx]\n h_new = h_old + r_k_val * v_new\n sData[(k_idx, v_idx, stage)] = h_new\n sum_hq += h_new * r_q_val\n\n for offset in [4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq,\n offset=offset * V_PER_WARP_SMALL,\n mask=-1,\n mask_and_clamp=31,\n )\n\n if k_local == 0:\n v_global_out = v_tile * TILE_V_SMALL_NT + v_idx\n o[(i_n, 0, i_hv, v_global_out)] = cutlass.BFloat16(sum_hq)\n\n cute.arch.barrier()\n\n for k_iter in cutlass.range_constexpr(NUM_K_ITERS_SMALL):\n flat_tid = tidx + k_iter * 128\n k_write = flat_tid // TILE_V_SMALL_NT\n v_write = flat_tid % TILE_V_SMALL_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_SMALL_NT + v_write\n # Use flat index for flattened state [B*HV, K, V]\n h0_source[(flat_idx, k_write, v_global_write)] = h_val\n\n cute.arch.barrier()\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_nontranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n num_v_tiles: cutlass.Constexpr[int],\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n use_qk_l2norm: cutlass.Constexpr[bool],\n):\n \"\"\"Large batch kernel for (N, 1, ...) format with K-major state layout.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n in_warp_tid = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n pool_idx = h0_indices[i_n]\n\n if pool_idx >= 0:\n k_local = in_warp_tid // V_PER_WARP_NT\n v_local = in_warp_tid % V_PER_WARP_NT\n v_base = warp_idx * V_PER_WARP_NT\n v_idx = v_base + v_local\n\n smem = cutlass.utils.SmemAllocator()\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n smem_o_layout = cute.make_layout((TILE_V_NT,), stride=(1,))\n smem_o = smem.allocate_tensor(cutlass.Float32, smem_o_layout, 128)\n smem_k_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n smem_q_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n sK = smem.allocate_tensor(cutlass.Float32, smem_k_layout, 128)\n sQ = smem.allocate_tensor(cutlass.Float32, smem_q_layout, 128)\n\n if tidx < TILE_K_NT:\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n\n # Compute flat index for flattened state [B*HV, K, V]\n flat_idx = pool_idx * HV + i_hv\n gSrc_batch = h0_source[(flat_idx, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n prefetch_count = cutlass.min(NUM_STAGES_NT - 1, num_v_tiles)\n for v_tile in range(prefetch_count):\n stage = v_tile % NUM_STAGES_NT\n gSrc_tile = gSrc[(None, None, v_tile)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_a = cutlass.Float32(a[i_n, 0, i_hv])\n r_b = cutlass.Float32(b[i_n, 0, i_hv])\n\n r_g = 0.0\n r_beta = 0.0\n if in_warp_tid == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n cute.arch.barrier()\n\n if use_qk_l2norm:\n sum_q_partial = 0.0\n sum_k_partial = 0.0\n if tidx < TILE_K_NT:\n q_val = sQ[tidx]\n k_val = sK[tidx]\n sum_q_partial = q_val * q_val\n sum_k_partial = k_val * k_val\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q_partial += cute.arch.shuffle_sync_bfly(\n sum_q_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k_partial += cute.arch.shuffle_sync_bfly(\n sum_k_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n if in_warp_tid == 0:\n smem_o[warp_idx] = sum_q_partial\n smem_o[warp_idx + 8] = sum_k_partial\n cute.arch.barrier()\n\n inv_norm_q = 0.0\n inv_norm_k = 0.0\n if warp_idx == 0:\n local_sum_q = 0.0\n local_sum_k = 0.0\n if in_warp_tid < NUM_WARPS_LARGE_NT:\n local_sum_q = smem_o[in_warp_tid]\n local_sum_k = smem_o[in_warp_tid + 8]\n for offset in [4, 2, 1]:\n local_sum_q += cute.arch.shuffle_sync_bfly(\n local_sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n local_sum_k += cute.arch.shuffle_sync_bfly(\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n smem_o[0] = cute.rsqrt(local_sum_q + 1e-6, fastmath=True)\n smem_o[1] = cute.rsqrt(local_sum_k + 1e-6, fastmath=True)\n cute.arch.barrier()\n\n inv_norm_q = smem_o[0]\n inv_norm_k = smem_o[1]\n\n if tidx < TILE_K_NT:\n sK[tidx] = sK[tidx] * inv_norm_k\n sQ[tidx] = sQ[tidx] * scale * inv_norm_q\n cute.arch.barrier()\n else:\n if tidx < TILE_K_NT:\n sQ[tidx] = sQ[tidx] * scale\n cute.arch.barrier()\n\n for v_tile in range(num_v_tiles):\n stage = v_tile % NUM_STAGES_NT\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n next_v_tile = v_tile + prefetch_count\n if next_v_tile < num_v_tiles:\n next_stage = next_v_tile % NUM_STAGES_NT\n gSrc_next = gSrc[(None, None, next_v_tile)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n v_global = v_tile * TILE_V_NT + v_idx\n r_v = cutlass.Float32(v[i_n, 0, i_hv, v_global])\n\n sum_hk = 0.0\n for k_iter in range(NUM_K_ITERS_NT, unroll=8): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_NT\n k_idx = k_base + k_local\n h_val = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n sum_hk += h_val * r_k_val\n\n for offset in [4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset * V_PER_WARP_NT, mask=-1, mask_and_clamp=31\n )\n\n v_new = (r_v - sum_hk) * r_beta\n v_new = cute.arch.shuffle_sync(v_new, v_local)\n\n sum_hq = 0.0\n for k_iter in range(NUM_K_ITERS_NT, unroll=8): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_NT\n k_idx = k_base + k_local\n h_old = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n r_q_val = sQ[k_idx]\n h_new = h_old + r_k_val * v_new\n sData[(k_idx, v_idx, stage)] = h_new\n sum_hq += h_new * r_q_val\n\n for offset in [4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset * V_PER_WARP_NT, mask=-1, mask_and_clamp=31\n )\n\n if k_local == 0:\n v_global_out = v_tile * TILE_V_NT + v_idx\n o[(i_n, 0, i_hv, v_global_out)] = cutlass.BFloat16(sum_hq)\n\n cute.arch.barrier()\n\n for k_iter in cutlass.range_constexpr(NUM_K_ITERS_NT):\n flat_tid = tidx + k_iter * 256\n k_write = flat_tid // TILE_V_NT\n v_write = flat_tid % TILE_V_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_NT + v_write\n # Use flat index for flattened state [B*HV, K, V]\n h0_source[(flat_idx, k_write, v_global_write)] = h_val\n\n cute.arch.barrier()\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_nontranspose(\n cu_seqlens: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n h0_source: cute.Tensor,\n h0_indices: cute.Tensor,\n o: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source is flattened to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n batch_hv_dim, k_dim, v_dim = h0_source.layout.shape\n h0_indices.layout.shape[0]\n batch_size = batch_hv_dim # batch_hv_dim = B * HV\n\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n num_v_tiles_small = cute.ceil_div(v_dim, TILE_V_SMALL_NT)\n smem_layout_small = cute.make_layout(\n (TILE_K_NT, TILE_V_SMALL_NT, NUM_STAGES_NT),\n stride=(TILE_V_SMALL_PADDED_NT, 1, TILE_K_NT * TILE_V_SMALL_PADDED_NT),\n )\n thread_layout_small = cute.make_layout((32, 4), stride=(4, 1))\n val_layout_small = cute.make_layout((1, 4))\n tiled_copy_load_small = cute.make_tiled_copy_tv(\n copy_atom, thread_layout_small, val_layout_small\n )\n smem_bytes_small = (\n 4 * TILE_K_NT * TILE_V_SMALL_PADDED_NT * NUM_STAGES_NT\n + 4 * TILE_V_SMALL_NT\n + 4 * TILE_K_NT * 2\n + 64\n )\n\n gdn_decode_kernel_small_batch_nontranspose(\n tiled_copy_load_small,\n h0_source,\n smem_layout_small,\n num_v_tiles_small,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n o,\n h0_indices,\n softplus_beta,\n softplus_threshold,\n scale,\n H,\n HV,\n use_qk_l2norm,\n ).launch(\n grid=(batch_size * NUM_BLOCKS_PER_STATE_SMALL_NT, 1, 1),\n block=[NUM_THREADS_NT, 1, 1],\n smem=smem_bytes_small,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_nontranspose(\n cu_seqlens: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n h0_source: cute.Tensor,\n h0_indices: cute.Tensor,\n o: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source is flattened to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n batch_hv_dim, k_dim, v_dim = h0_source.layout.shape\n h0_indices.layout.shape[0]\n batch_size = batch_hv_dim # batch_hv_dim = B * HV\n\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n num_v_tiles = cute.ceil_div(v_dim, TILE_V_NT)\n base_smem_layout = cute.make_layout(\n (TILE_K_NT, TILE_V_NT, NUM_STAGES_NT),\n stride=(TILE_V_PADDED_NT, 1, TILE_K_NT * TILE_V_PADDED_NT),\n )\n thread_layout = cute.make_layout((32, 8), stride=(8, 1))\n val_layout = cute.make_layout((1, 4))\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n smem_bytes = (\n 4 * TILE_K_NT * TILE_V_PADDED_NT * NUM_STAGES_NT\n + 4 * TILE_V_NT\n + 4 * TILE_K_NT * 2\n + 64\n )\n\n gdn_decode_kernel_big_batch_nontranspose(\n tiled_copy_load,\n h0_source,\n base_smem_layout,\n num_v_tiles,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n o,\n h0_indices,\n softplus_beta,\n softplus_threshold,\n scale,\n H,\n HV,\n use_qk_l2norm,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS_LARGE_NT, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# FlashInfer API Layer - NONTRANSPOSE Version (Recommended)\n# ============================================================================\n\n\n@flashinfer_api\ndef gated_delta_rule_decode(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n state: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Gated Delta Rule Decode kernel (K-major layout, no transpose needed).\n\n This implements the decode phase of gated delta rule linear attention,\n processing one token at a time and updating the recurrent state.\n This version uses K-major state layout [B, HV, K, V] which is more natural\n and doesn't require transposition.\n\n Args:\n q (torch.Tensor):\n Current query of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n k (torch.Tensor):\n Current key of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n v (torch.Tensor):\n Current value of shape ``[B, 1, HV, V]``. Must be float16/bfloat16.\n state (torch.Tensor):\n Current state of shape ``[B, HV, K, V]`` (k-major layout).\n Must be float32. Will be updated in-place.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``. Must be float32.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``. Must be bfloat16 or float32.\n b (torch.Tensor):\n Update gate (beta) input of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n scale (Optional[float]):\n Scale factor for queries. If None, defaults to ``1 / sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, 1, HV, V]``.\n If None, will be allocated automatically.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, 1, HV, V]``\n - state: Updated state tensor of shape ``[B, HV, K, V]``\n\n Note:\n - Requires SM90 (Hopper) architecture\n - State is updated in-place\n - K and V must be multiples of 4 for vectorized loads\n - State layout is k-major: [B, HV, K, V] (no transpose needed)\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n assert T == 1, f\"Decode only supports T=1, got T={T}\"\n _, _, HV, V = v.shape\n\n # Validate state shape\n assert state.shape == (B, HV, K, V), (\n f\"Expected state shape [B={B}, HV={HV}, K={K}, V={V}], got {state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n # V must be divisible by tile size to prevent out-of-bounds access\n # For small batch: TILE_V_SMALL_NT=16, for large batch: TILE_V_NT=32\n # Use the more restrictive constraint (32) to cover both cases\n assert V % TILE_V_NT == 0, (\n f\"V must be divisible by {TILE_V_NT} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert state.dtype == torch.float32, f\"state must be float32, got {state.dtype}\"\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # State is in K-major layout [B, HV, K, V]\n # Flatten to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n # This avoids alignment issues when B=1 (zero strides cause alignment failures)\n state_contiguous = state.contiguous()\n h0_source = state_contiguous.view(B * HV, K, V)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel_nontranspose(*cache_key)\n\n # Get or create h0_indices and cu_seqlens (cached per config)\n if \"h0_indices\" not in cache or cache[\"h0_indices\"].device != q.device:\n cache[\"h0_indices\"] = torch.arange(B, dtype=torch.int32, device=q.device)\n cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n h0_indices = cache[\"h0_indices\"]\n cu_seqlens = cache[\"cu_seqlens\"]\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Choose kernel based on batch size\n use_small_batch = B < SMALL_BATCH_THRESHOLD_NT\n\n if use_small_batch:\n run_func = run_gdn_decode_kernel_small_batch_nontranspose\n else:\n run_func = run_gdn_decode_kernel_big_batch_nontranspose\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n cu_seqlens_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n a_tensor,\n b_tensor,\n A_log_tensor,\n dt_bias_tensor,\n h0_source_tensor,\n h0_indices_tensor,\n o_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n B=B,\n T=T,\n H=H,\n HV=HV,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n compiled(\n cu_seqlens,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n h0_source,\n h0_indices,\n output,\n stream,\n )\n\n # Copy state back only if state was not contiguous\n # (if contiguous, state_contiguous is state itself, so kernel updated state in-place)\n if state_contiguous.data_ptr() != state.data_ptr():\n state.copy_(state_contiguous)\n\n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, state\n\n\n# ============================================================================\n# MTP (Multiple Token Processing) Kernel - for T > 1 (verify mode)\n# ============================================================================\n\n\n@cute.kernel\ndef gdn_verify_kernel_mtp(\n h0_source: cute.Tensor, # [pool_size * HV, V, K] - initial state pool (K-last)\n intermediate_states: cute.Tensor, # [pool_size * T * HV, V, K] - intermediate state cache\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n tile_v: cutlass.Constexpr[int], # TILE_V - configurable for batch size\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n disable_state_update: cutlass.Constexpr[bool],\n cache_intermediate_states: cutlass.Constexpr[bool],\n):\n \"\"\"\n Parallel MTP kernel - each block handles one [TILE_V, TILE_K] tile.\n\n Grid: (B * HV * num_v_tiles, 1, 1)\n Each block:\n - Loads its v_tile of state into registers\n - Processes all T time steps with state in registers\n - Writes output and optionally updates state\n\n This matches Triton's parallelization strategy for better small-batch performance.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n\n # Compute thread grouping based on vec_size:\n # vec_size=8: 16 threads per group (half-warp), 8 groups per block\n # vec_size=4: 32 threads per group (full warp), 4 groups per block\n threads_per_group: cutlass.Constexpr[int] = K // vec_size # 16 or 32\n groups_per_warp: cutlass.Constexpr[int] = 32 // threads_per_group # 2 or 1\n num_groups: cutlass.Constexpr[int] = 4 * groups_per_warp # 8 or 4\n\n # Lane position within group and group index\n lane_in_group = lane_id % threads_per_group\n group_in_warp = lane_id // threads_per_group\n group_idx = warp_idx * groups_per_warp + group_in_warp\n\n batch_idx, _, _ = cute.arch.block_idx()\n\n # Decode block index: (i_n, i_hv, i_v) from batch_idx\n i_v = batch_idx % num_v_tiles\n tmp = batch_idx // num_v_tiles\n i_hv = tmp % HV\n i_n = tmp // HV\n i_h = i_hv // (HV // H)\n\n # Get initial state index for this batch\n cache_idx = h0_indices[i_n]\n\n # Load A_log and dt_bias once (they don't vary with time)\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n\n # Allocate shared memory for pre-computed values (broadcast to all warps)\n smem = cutlass.utils.SmemAllocator()\n sQ = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sK = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sG = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n sBeta = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n\n # Register arrays for computation\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Only process valid batch entries (cache_idx >= 0)\n if cache_idx >= 0:\n # Compute k_start once (used for shared memory writes)\n k_start = lane_in_group * vec_size\n\n # Pre-compute q, k, g, beta for ALL time steps ONCE (shared across warps)\n for i_t in cutlass.range_constexpr(T):\n # Load q, k into BF16 registers using autovec_copy (coalesced)\n q_tile = cute.local_tile(\n q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_in_group)\n )\n k_tile = cute.local_tile(\n k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_in_group)\n )\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32 for computation\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Apply L2 normalization to q, k (with scale fused for q)\n if cutlass.const_expr(use_qk_l2norm):\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n\n # Warp-level reduction (32 threads per group with vec_size=4)\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Fuse scale into q's normalization factor\n inv_norm_q_scaled = cute.rsqrt(sum_q + 1e-6, fastmath=True) * scale\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q_scaled\n r_k[i] = r_k[i] * inv_norm_k\n else:\n # No L2 norm, just apply scale to q\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # Store to shared memory (only first group writes) - contiguous layout\n if tidx < threads_per_group:\n for i in cutlass.range_constexpr(vec_size):\n sQ[(i_t, k_start + i)] = r_q[i]\n sK[(i_t, k_start + i)] = r_k[i]\n\n # Compute g, beta - all lanes compute (redundant but no divergence)\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n\n # Branchless softplus\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n softplus_val = (cutlass.Float32(1.0) / softplus_beta) * cute.log(\n cutlass.Float32(1.0) + exp_beta_x, fastmath=True\n )\n use_softplus = (\n cutlass.Float32(1.0)\n if beta_x <= softplus_threshold\n else cutlass.Float32(0.0)\n )\n softplus_x = (\n use_softplus * softplus_val + (cutlass.Float32(1.0) - use_softplus) * x\n )\n\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n r_beta = cutlass.Float32(1.0) / (\n cutlass.Float32(1.0) + cute.exp(-r_b, fastmath=True)\n )\n r_g = cute.exp(r_g_value, fastmath=True)\n\n # Only thread 0 stores to shared memory\n if tidx == 0:\n sG[i_t] = r_g\n sBeta[i_t] = r_beta\n\n cute.arch.barrier()\n\n # Each group handles tile_v/num_groups V rows\n rows_per_group: cutlass.Constexpr[int] = tile_v // num_groups\n for row_in_group in cutlass.range_constexpr(rows_per_group):\n v_idx = i_v * tile_v + group_idx * rows_per_group + row_in_group\n\n if v_idx < V:\n # Load h[v_idx, :] into registers using 3D local_tile + autovec_copy\n flat_state_idx = cache_idx * HV + i_hv\n h_tile = cute.local_tile(\n h0_source, (1, 1, vec_size), (flat_state_idx, v_idx, lane_in_group)\n )\n cute.autovec_copy(h_tile, r_h)\n\n # Process all T time steps with h in registers\n for i_t in cutlass.range_constexpr(T):\n # Load pre-computed q, k from shared memory using 2D local_tile\n sQ_tile = cute.local_tile(sQ, (1, vec_size), (i_t, lane_in_group))\n sK_tile = cute.local_tile(sK, (1, vec_size), (i_t, lane_in_group))\n cute.autovec_copy(sQ_tile, r_q)\n cute.autovec_copy(sK_tile, r_k)\n\n r_g = sG[i_t]\n r_beta = sBeta[i_t]\n\n # Step 1: Apply decay to h\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n\n # Step 2: Compute sum_hk = h @ k (group reduction)\n sum_hk = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_hk += r_h[i] * r_k[i]\n\n # Warp-level reduction\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Step 3: Load v for this v_idx and time step, apply delta rule\n r_v = cutlass.Float32(v[i_n, i_t, i_hv, v_idx])\n v_new = (r_v - sum_hk) * r_beta\n\n # Step 4: Update h: h += k * v_new\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n\n # Cache intermediate state if needed using 3D local_tile + autovec_copy\n if cutlass.const_expr(cache_intermediate_states):\n flat_idx = i_n * T * HV + i_t * HV + i_hv\n inter_tile = cute.local_tile(\n intermediate_states,\n (1, 1, vec_size),\n (flat_idx, v_idx, lane_in_group),\n )\n cute.autovec_copy(r_h, inter_tile)\n\n # Step 5: Compute output: sum_hq = h @ q (group reduction)\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_hq += r_h[i] * r_q[i]\n\n # Warp-level reduction\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Write output (only lane 0 of each group)\n if lane_in_group == 0:\n o[(i_n, i_t, i_hv, v_idx)] = cutlass.BFloat16(sum_hq)\n\n # Write final state back (if not disabled) using 3D local_tile + autovec_copy\n if cutlass.const_expr(not disable_state_update):\n h_tile_out = cute.local_tile(\n h0_source,\n (1, 1, vec_size),\n (flat_state_idx, v_idx, lane_in_group),\n )\n cute.autovec_copy(r_h, h_tile_out)\n\n\n@cute.jit\ndef run_gdn_verify_kernel_mtp(\n h0_source: cute.Tensor,\n intermediate_states: cute.Tensor,\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n tile_v: cutlass.Constexpr[int], # TILE_V - configurable for batch size\n vec_size: cutlass.Constexpr[int], # 4 for full warp, 8 for half-warp\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n disable_state_update: cutlass.Constexpr[bool],\n cache_intermediate_states: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n _, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n num_v_tiles = cute.ceil_div(v_dim, tile_v)\n\n # Grid: (B * HV * num_v_tiles, 1, 1) - parallelize across V dimension\n grid_size = B * HV * num_v_tiles\n\n # Shared memory for pre-computed q, k, g, beta\n smem_bytes = (\n 4 * T * (k_dim + 8) # sQ\n + 4 * T * (k_dim + 8) # sK\n + 4 * T # sG\n + 4 * T # sBeta\n + 128 # alignment\n )\n\n gdn_verify_kernel_mtp(\n h0_source,\n intermediate_states,\n vec_size,\n num_v_tiles,\n tile_v,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n disable_state_update,\n cache_intermediate_states,\n ).launch(\n grid=(grid_size, 1, 1),\n block=[NUM_THREADS_MTP, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@functools.cache\ndef _get_compiled_mtp_kernel(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n pool_size: int,\n cache_steps: int,\n disable_state_update: bool,\n cache_intermediate_states: bool,\n scale: float,\n use_qk_l2norm: bool,\n tile_v: int, # TILE_V - configurable for batch size\n vec_size: int, # 4 for full warp, 8 for half-warp\n):\n \"\"\"Cache compiled MTP kernel for given configuration.\"\"\"\n return {}\n\n\n@flashinfer_api\ndef gated_delta_rule_mtp(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n initial_state: torch.Tensor,\n initial_state_indices: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n intermediate_states_buffer: Optional[torch.Tensor] = None,\n disable_state_update: bool = True,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n \"\"\"\n Gated Delta Rule MTP Kernel (Multiple Token Processing).\n\n This function processes multiple tokens (T > 1) in sequence, typically used for\n speculative decoding verification. It supports intermediate state caching for\n potential rollback scenarios.\n\n Args:\n q (torch.Tensor):\n Query tensor of shape ``[B, T, H, K]``.\n k (torch.Tensor):\n Key tensor of shape ``[B, T, H, K]``.\n v (torch.Tensor):\n Value tensor of shape ``[B, T, HV, V]``.\n initial_state (torch.Tensor):\n Initial state tensor of shape ``[pool_size, HV, V, K]`` (K-last layout).\n initial_state_indices (torch.Tensor):\n Indices mapping each batch to its initial state, shape ``[B]``.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, T, HV]``.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``.\n b (torch.Tensor):\n Update gate input of shape ``[B, T, HV]``.\n scale (Optional[float]):\n Scaling factor for queries. If None, uses ``1/sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, T, HV, V]``.\n intermediate_states_buffer (Optional[torch.Tensor]):\n Buffer for caching intermediate states, shape ``[pool_size, T, HV, V, K]``.\n If None, intermediate states are not cached.\n disable_state_update (bool):\n If True, the initial state is not updated. Default: ``True``.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, T, HV, V]``\n - initial_state: Updated state tensor (unchanged if disable_state_update=True)\n\n Note:\n - Requires SM90 (Hopper) architecture\n - Supports T > 1 (multiple token processing)\n - State layout is K-last: [pool_size, HV, V, K]\n - Optimized for speculative decoding verification scenarios\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n _, _, HV, V = v.shape\n pool_size = initial_state.shape[0]\n\n # Dynamic TILE_V and vec_size selection based on batch size and sequence length\n tile_v = get_tile_v_mtp(B, T)\n vec_size = get_vec_size_mtp(B, T)\n\n # Validate state shape\n assert initial_state.shape == (pool_size, HV, V, K), (\n f\"Expected initial_state shape [pool_size={pool_size}, HV={HV}, V={V}, K={K}], got {initial_state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n assert V % tile_v == 0, (\n f\"V must be divisible by {tile_v} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert initial_state.dtype == torch.float32, (\n f\"initial_state must be float32, got {initial_state.dtype}\"\n )\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # Reshape initial_state from [pool_size, HV, V, K] to [pool_size * HV, V, K]\n h0_source = initial_state.to(torch.float32).reshape(pool_size * HV, V, K)\n\n # Handle intermediate states\n cache_intermediate_states = intermediate_states_buffer is not None\n if cache_intermediate_states:\n buffer_size = intermediate_states_buffer.shape[0]\n cache_steps = intermediate_states_buffer.shape[1]\n\n # Validate buffer length matches query sequence length\n assert cache_steps >= T, (\n f\"intermediate_states_buffer second dimension (cache_steps={cache_steps}) must be at least T={T} to prevent out-of-bounds indexing\"\n )\n\n intermediate_states = (\n intermediate_states_buffer.to(torch.float32)\n .reshape(buffer_size * cache_steps * HV, V, K)\n .contiguous()\n )\n else:\n cache_steps = T\n intermediate_states = torch.zeros(1, 1, 1, dtype=torch.float32, device=q.device)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (\n B,\n T,\n H,\n HV,\n K,\n V,\n pool_size,\n cache_steps,\n disable_state_update,\n cache_intermediate_states,\n scale,\n use_qk_l2norm,\n tile_v,\n vec_size,\n )\n cache = _get_compiled_mtp_kernel(*cache_key)\n\n # Get or create cu_seqlens (cached per config)\n if \"cu_seqlens\" not in cache or cache[\"cu_seqlens\"].device != q.device:\n cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n cu_seqlens = cache[\"cu_seqlens\"]\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n intermediate_states_tensor = from_dlpack(intermediate_states, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(initial_state_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_gdn_verify_kernel_mtp,\n h0_source_tensor,\n intermediate_states_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n B=B,\n T=T,\n H=H,\n K=K,\n V=V,\n tile_v=tile_v,\n vec_size=vec_size,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n disable_state_update=disable_state_update,\n cache_intermediate_states=cache_intermediate_states,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n compiled(\n h0_source,\n intermediate_states,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n output,\n initial_state_indices,\n cu_seqlens,\n stream,\n )\n\n # Copy state back if needed (no sync needed - PyTorch handles stream ordering)\n # Only copy if state update is enabled AND initial_state was not contiguous\n # (if contiguous, reshape returns a view and kernel updated state in-place)\n if not disable_state_update and not initial_state.is_contiguous():\n initial_state.copy_(h0_source.reshape(pool_size, HV, V, K))\n\n # Convert output to target dtype if needed\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, initial_state\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\n\"\"\"\nGated Delta Rule Decode Kernel - Single Token Generation\n\nThis file implements a fused CUDA kernel using CUTLASS CuTe DSL for executing\nSigmoid Gating Delta Rule updates during decode phase. Key features:\n\nArchitecture Design:\n- Uses TMA (Tensor Memory Accelerator) for efficient Global Memory → Shared Memory transfers\n- Employs 2-stage pipeline to overlap loading and computation, hiding memory latency\n- Each block uses 128 threads (4 warps), with each warp processing one matrix row\n- Tile size: 8x128 (TILE_V x TILE_K)\n\nComputation Flow:\n1. Warp 0 handles TMA prefetch, loading data from GMEM to SMEM\n2. All warps compute in parallel: softplus, L2 normalization, delta rule updates\n3. Each warp processes one row of data, completing h_new = g*h + k*(beta*(v - h@k))\n4. Uses warp-level shuffle for efficient reduction operations\n5. Results are vectorized and written back to Global Memory\n\nPerformance Optimizations:\n- Vectorized memory access: each thread processes vec_size=4 elements (128-bit aligned)\n- Warp-level collective operations: shuffle-based reduction\n- Pipeline overlap: load stage N+1 while computing stage N\n\"\"\"\n\nimport functools\nfrom typing import Optional, Tuple\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass.cute.nvgpu import cpasync\nfrom cutlass.cute.runtime import from_dlpack\nimport cuda.bindings.driver as cuda\n\ntry:\n from .api_logging import flashinfer_api\n\n _FLASHINFER_AVAILABLE = True\nexcept ImportError:\n _FLASHINFER_AVAILABLE = False\n\n # Fallback decorator for standalone usage\n def flashinfer_api(func): # type: ignore[misc]\n return func\n\n\n# GDN decode K-last bf16 state kernel (T=1..4, bf16 state, K-last layout) - optional backend\ntry:\n from .gdn_kernels.gdn_decode_bf16_state import (\n gated_delta_rule as _gated_delta_rule_gdn_decode_klast_bf16_state,\n )\n\n _GDN_DECODE_KLAST_BF16_STATE_AVAILABLE = True\nexcept ImportError:\n _GDN_DECODE_KLAST_BF16_STATE_AVAILABLE = False\n _gated_delta_rule_gdn_decode_klast_bf16_state = None\n\n\n# ============================================================================\n# Global configuration for PRETRANSPOSE version ([B*HV, V, K])\n# ============================================================================\nTILE_V = 8\nTILE_K = 128\nNUM_STAGES = 2\nNUM_THREADS = 128 # 4 warps\nNUM_BLOCKS_PER_STATE = 8\n\n# ============================================================================\n# Global configuration for NONTRANSPOSE version ([pool, HV, K, V])\n# ============================================================================\nTILE_K_NT = 128\nTILE_V_NT = 32\nTILE_V_PADDED_NT = 36\nTILE_V_SMALL_NT = 16\nTILE_V_SMALL_PADDED_NT = 20\nNUM_STAGES_NT = 2\nNUM_THREADS_NT = 128\nNUM_BLOCKS_PER_STATE_SMALL_NT = 8\nNUM_THREADS_LARGE_NT = 256\nNUM_WARPS_LARGE_NT = 8\nV_PER_WARP_NT = 4\nROWS_PER_ITER_NT = 8\nNUM_K_ITERS_NT = TILE_K_NT // ROWS_PER_ITER_NT\nSMALL_BATCH_THRESHOLD_NT = 32\n\n# ============================================================================\n# Global configuration for MTP (Multiple Token Processing) version\n# ============================================================================\n# Dynamic kernel selection based on batch size:\n# - Small batch (B <= threshold): Use smaller TILE_V for more parallelism\n# Optimal TILE_V depends on batch size (empirically determined):\n# B=1-2: TILE_V=4 (more blocks, better parallelism for tiny batches)\n# B=4: TILE_V=8 (intermediate parallelism)\n# B=8: TILE_V=16 (balance between parallelism and efficiency)\n# B>=16: TILE_V=32 (fewer blocks, better efficiency for large batches)\n\nTILE_K_MTP = 128 # Full K dimension (shared across all configs)\nNUM_THREADS_MTP = 128 # 4 warps (shared across all configs)\n\n\ndef get_vec_size_mtp(batch_size: int, seq_len: int = 1) -> int:\n \"\"\"Select vec_size for MTP kernel.\n\n Always use vec_size=4 (32 threads per group = full warp, 4 groups per block).\n Full warp shuffle is more efficient and achieves >= 1.0x speedup vs Triton.\n \"\"\"\n return 4\n\n\ndef get_tile_v_mtp(batch_size: int, seq_len: int = 1) -> int:\n \"\"\"Select optimal TILE_V for MTP kernel based on batch size and sequence length.\n\n With vec_size=4, num_groups=4, rows_per_group = tile_v / 4.\n Tuned via grid search for optimal performance.\n \"\"\"\n if batch_size <= 2:\n return 4 # Small batch needs max parallelism\n elif batch_size <= 4:\n return 8\n elif batch_size <= 8:\n return 16\n elif batch_size <= 16:\n return 32\n else:\n return 64\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n # Read gate values from GMEM EARLY (before barrier, latency hidden during sync)\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n cute.arch.barrier()\n\n # Get current batch\n gSrc_batch = h0_source[(batch_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (batch_idx, None, 0))\n\n # V 方向分 tiles\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n start_v_tiles = batch_inner * num_v_tiles_per_block\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles_per_block)\n for v_tiles in range(start_v_tiles, start_v_tiles + prefetch_count):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n end_v_tiles = start_v_tiles + num_v_tiles_per_block\n for v_tiles in range(start_v_tiles, end_v_tiles):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < end_v_tiles:\n next_stage = (next_v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n gDst_tile = cute.local_tile(\n gDst, (1, 1, vec_size, 1), (0, row + row_offset, lane_id, v_tiles)\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n if tidx >= start_v_tiles * TILE_V and tidx < end_v_tiles * TILE_V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n cute.arch.barrier()\n\n # Get current batch\n gSrc_batch = h0_source[(batch_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (batch_idx, None, 0))\n\n # V 方向分 tiles\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles)\n for v_tiles in range(prefetch_count):\n stage = v_tiles % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n for v_tiles in range(num_v_tiles):\n stage = v_tiles % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < num_v_tiles:\n next_stage = next_v_tiles % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n gDst_tile = cute.local_tile(\n gDst, (1, 1, vec_size, 1), (0, row + row_offset, lane_id, v_tiles)\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n \"\"\"Launch original pipelined kernel for small batch pretranspose.\"\"\"\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * batch_size * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n ).launch(\n grid=(batch_size * NUM_BLOCKS_PER_STATE, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * batch_size * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # print(f\"Batched CP.ASYNC Load + Store (bypass L1 cache)\")\n # print(f\" {batch_size} batches x {v_dim}x{k_dim} matrices\")\n # print(f\" Tile: {TILE_V}x{TILE_K}, {num_v_tiles} tiles/batch\")\n # print(f\" Threads: {NUM_THREADS} ({NUM_THREADS // 32} warps), vec_size: {vec_size}\")\n # print(f\" Total: {total_data_mb:.1f} MB\\n\")\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# FlashInfer API Layer\n# ============================================================================\n\n\n@functools.cache\ndef _get_compiled_decode_kernel(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled kernel for given configuration (pretranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\n@functools.cache\ndef _get_compiled_decode_kernel_nontranspose(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled kernel for given configuration (nontranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\n@flashinfer_api\ndef gated_delta_rule_decode_pretranspose(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n state: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Gated Delta Rule Decode kernel for single-token generation.\n\n This implements the decode phase of gated delta rule linear attention,\n processing one token at a time and updating the recurrent state.\n\n Args:\n q (torch.Tensor):\n Current query of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n k (torch.Tensor):\n Current key of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n v (torch.Tensor):\n Current value of shape ``[B, 1, HV, V]``. Must be float16/bfloat16.\n state (torch.Tensor):\n Current state of shape ``[B, HV, V, K]`` (v-major / K-last layout).\n Float32: legacy kernel (T=1 only). Bfloat16: gdn_decode_klast_bf16_state backend\n when T in 1..4 and K=V=128. Will be updated in-place.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``. Must be float32.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``. Must be bfloat16 or float32.\n b (torch.Tensor):\n Update gate (beta) input of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n scale (Optional[float]):\n Scale factor for queries. If None, defaults to ``1 / sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, 1, HV, V]``.\n If None, will be allocated automatically.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, 1, HV, V]``\n - state: Updated state tensor of shape ``[B, HV, V, K]``\n\n Note:\n - Requires SM90 (Hopper) architecture\n - State is updated in-place\n - State layout is v-major (K-last): [B, HV, V, K]. When state is bfloat16\n and T in 1..4 with K=V=128, the gdn_decode_klast_bf16_state kernel is used.\n - Legacy path (float32 state, T=1): K and V must be multiples of 4.\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n _, _, HV, V = v.shape\n\n # Validate state shape (Qwen-style K-last: [B, HV, V, K])\n assert state.shape == (B, HV, V, K), (\n f\"Expected state shape [B={B}, HV={HV}, V={V}, K={K}], got {state.shape}\"\n )\n\n # Backend: gdn_decode_klast_bf16_state when bf16 state, T<=4, K-last layout, K=V=128\n use_gdn_decode_klast_bf16_state = (\n _GDN_DECODE_KLAST_BF16_STATE_AVAILABLE\n and state.dtype == torch.bfloat16\n and T in (1, 2, 3, 4)\n and K == 128\n and V == 128\n )\n if use_gdn_decode_klast_bf16_state:\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n scale_val = K**-0.5 if scale is None else scale\n out = _gated_delta_rule_gdn_decode_klast_bf16_state(\n A_log=A_log,\n a=a,\n dt_bias=dt_bias,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n q=q,\n k=k,\n v=v,\n b=b,\n initial_state_source=state,\n use_qk_l2norm_in_kernel=use_qk_l2norm,\n scale=scale_val,\n )\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n if output is not None:\n output.copy_(out)\n else:\n output = out\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n return output, state\n\n # Legacy path: T=1 only, float32 state\n assert T == 1, f\"Decode only supports T=1, got T={T}\"\n assert state.dtype == torch.float32, f\"state must be float32, got {state.dtype}\"\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n assert V % TILE_V == 0, (\n f\"V must be divisible by {TILE_V} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n # Note: kernel outputs bfloat16, we'll convert to q.dtype if needed\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # Convert state from [B, HV, V, K] to [B*HV, V, K] for kernel\n h0_source = state.reshape(B * HV, V, K)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel(*cache_key)\n\n # Get or create h0_indices and cu_seqlens (cached per config)\n if \"h0_indices\" not in cache or cache[\"h0_indices\"].device != q.device:\n cache[\"h0_indices\"] = torch.zeros(B, dtype=torch.int32, device=q.device)\n cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n h0_indices = cache[\"h0_indices\"]\n cu_seqlens = cache[\"cu_seqlens\"]\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Always use 8-CTA architecture (benchmarks show it's better for all batch sizes)\n run_func = run_gdn_decode_kernel_small_batch_pretranspose\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n h0_source_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n B=B,\n T=T,\n H=H,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n cache[\"compiled\"](\n h0_source, A_log, a, dt_bias, q, k, v, b, output, h0_indices, cu_seqlens, stream\n )\n\n # Copy state back only if state was not contiguous\n # (if contiguous, reshape returns a view and kernel updated state in-place)\n if not state.is_contiguous():\n state.copy_(h0_source.reshape(B, HV, V, K))\n\n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, state\n\n\n# ============================================================================\n# NONTRANSPOSE Version Kernels - K-major layout [pool, HV, K, V]\n# ============================================================================\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_nontranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n num_v_tiles: cutlass.Constexpr[int],\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n use_qk_l2norm: cutlass.Constexpr[bool],\n):\n \"\"\"Small batch kernel for (N, 1, ...) format with K-major state layout.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n in_warp_tid = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n\n NUM_WARPS_SMALL = 4\n V_PER_WARP_SMALL = TILE_V_SMALL_NT // NUM_WARPS_SMALL\n ROWS_PER_ITER_SMALL = 32 // V_PER_WARP_SMALL\n NUM_K_ITERS_SMALL = TILE_K_NT // ROWS_PER_ITER_SMALL\n\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE_SMALL_NT\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE_SMALL_NT\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE_SMALL_NT\n start_v_tile = batch_inner * num_v_tiles_per_block\n\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n pool_idx = h0_indices[i_n]\n\n if pool_idx >= 0:\n k_local = in_warp_tid // V_PER_WARP_SMALL\n v_local = in_warp_tid % V_PER_WARP_SMALL\n v_base = warp_idx * V_PER_WARP_SMALL\n v_idx = v_base + v_local\n\n smem = cutlass.utils.SmemAllocator()\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n smem_o_layout = cute.make_layout((TILE_V_SMALL_NT,), stride=(1,))\n smem_o = smem.allocate_tensor(cutlass.Float32, smem_o_layout, 128)\n smem_k_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n smem_q_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n sK = smem.allocate_tensor(cutlass.Float32, smem_k_layout, 128)\n sQ = smem.allocate_tensor(cutlass.Float32, smem_q_layout, 128)\n\n if tidx < TILE_K_NT:\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n\n # Compute flat index for flattened state [B*HV, K, V]\n flat_idx = pool_idx * HV + i_hv\n gSrc_batch = h0_source[(flat_idx, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_SMALL_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n prefetch_count = cutlass.min(NUM_STAGES_NT - 1, num_v_tiles_per_block)\n for v_tile_offset in range(prefetch_count):\n v_tile = start_v_tile + v_tile_offset\n stage = v_tile_offset % NUM_STAGES_NT\n gSrc_tile = gSrc[(None, None, v_tile)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_a = cutlass.Float32(a[i_n, 0, i_hv])\n r_b = cutlass.Float32(b[i_n, 0, i_hv])\n\n r_g = 0.0\n r_beta = 0.0\n if in_warp_tid == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n cute.arch.barrier()\n\n if use_qk_l2norm:\n sum_q_partial = 0.0\n sum_k_partial = 0.0\n if tidx < TILE_K_NT:\n q_val = sQ[tidx]\n k_val = sK[tidx]\n sum_q_partial = q_val * q_val\n sum_k_partial = k_val * k_val\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q_partial += cute.arch.shuffle_sync_bfly(\n sum_q_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k_partial += cute.arch.shuffle_sync_bfly(\n sum_k_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n if in_warp_tid == 0:\n smem_o[warp_idx] = sum_q_partial\n smem_o[warp_idx + 4] = sum_k_partial\n cute.arch.barrier()\n\n inv_norm_q = 0.0\n inv_norm_k = 0.0\n if warp_idx == 0:\n local_sum_q = 0.0\n local_sum_k = 0.0\n if in_warp_tid < NUM_WARPS_SMALL:\n local_sum_q = smem_o[in_warp_tid]\n local_sum_k = smem_o[in_warp_tid + 4]\n for offset in [2, 1]:\n local_sum_q += cute.arch.shuffle_sync_bfly(\n local_sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n local_sum_k += cute.arch.shuffle_sync_bfly(\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n smem_o[0] = cute.rsqrt(local_sum_q + 1e-6, fastmath=True)\n smem_o[1] = cute.rsqrt(local_sum_k + 1e-6, fastmath=True)\n cute.arch.barrier()\n\n inv_norm_q = smem_o[0]\n inv_norm_k = smem_o[1]\n\n if tidx < TILE_K_NT:\n sK[tidx] = sK[tidx] * inv_norm_k\n sQ[tidx] = sQ[tidx] * scale * inv_norm_q\n cute.arch.barrier()\n else:\n if tidx < TILE_K_NT:\n sQ[tidx] = sQ[tidx] * scale\n cute.arch.barrier()\n\n for v_tile_offset in range(num_v_tiles_per_block):\n v_tile = start_v_tile + v_tile_offset\n stage = v_tile_offset % NUM_STAGES_NT\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n next_v_tile_offset = v_tile_offset + prefetch_count\n if next_v_tile_offset < num_v_tiles_per_block:\n next_v_tile = start_v_tile + next_v_tile_offset\n next_stage = next_v_tile_offset % NUM_STAGES_NT\n gSrc_next = gSrc[(None, None, next_v_tile)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n v_global = v_tile * TILE_V_SMALL_NT + v_idx\n r_v = cutlass.Float32(v[i_n, 0, i_hv, v_global])\n\n sum_hk = 0.0\n for k_iter in range(NUM_K_ITERS_SMALL, unroll=16): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_SMALL\n k_idx = k_base + k_local\n h_val = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n sum_hk += h_val * r_k_val\n\n for offset in [4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk,\n offset=offset * V_PER_WARP_SMALL,\n mask=-1,\n mask_and_clamp=31,\n )\n\n v_new = (r_v - sum_hk) * r_beta\n v_new = cute.arch.shuffle_sync(v_new, v_local)\n\n sum_hq = 0.0\n for k_iter in range(NUM_K_ITERS_SMALL, unroll=16): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_SMALL\n k_idx = k_base + k_local\n h_old = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n r_q_val = sQ[k_idx]\n h_new = h_old + r_k_val * v_new\n sData[(k_idx, v_idx, stage)] = h_new\n sum_hq += h_new * r_q_val\n\n for offset in [4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq,\n offset=offset * V_PER_WARP_SMALL,\n mask=-1,\n mask_and_clamp=31,\n )\n\n if k_local == 0:\n v_global_out = v_tile * TILE_V_SMALL_NT + v_idx\n o[(i_n, 0, i_hv, v_global_out)] = cutlass.BFloat16(sum_hq)\n\n cute.arch.barrier()\n\n for k_iter in cutlass.range_constexpr(NUM_K_ITERS_SMALL):\n flat_tid = tidx + k_iter * 128\n k_write = flat_tid // TILE_V_SMALL_NT\n v_write = flat_tid % TILE_V_SMALL_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_SMALL_NT + v_write\n # Use flat index for flattened state [B*HV, K, V]\n h0_source[(flat_idx, k_write, v_global_write)] = h_val\n\n cute.arch.barrier()\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_nontranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n num_v_tiles: cutlass.Constexpr[int],\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n use_qk_l2norm: cutlass.Constexpr[bool],\n):\n \"\"\"Large batch kernel for (N, 1, ...) format with K-major state layout.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n in_warp_tid = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n pool_idx = h0_indices[i_n]\n\n if pool_idx >= 0:\n k_local = in_warp_tid // V_PER_WARP_NT\n v_local = in_warp_tid % V_PER_WARP_NT\n v_base = warp_idx * V_PER_WARP_NT\n v_idx = v_base + v_local\n\n smem = cutlass.utils.SmemAllocator()\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n smem_o_layout = cute.make_layout((TILE_V_NT,), stride=(1,))\n smem_o = smem.allocate_tensor(cutlass.Float32, smem_o_layout, 128)\n smem_k_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n smem_q_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n sK = smem.allocate_tensor(cutlass.Float32, smem_k_layout, 128)\n sQ = smem.allocate_tensor(cutlass.Float32, smem_q_layout, 128)\n\n if tidx < TILE_K_NT:\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n\n # Compute flat index for flattened state [B*HV, K, V]\n flat_idx = pool_idx * HV + i_hv\n gSrc_batch = h0_source[(flat_idx, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n prefetch_count = cutlass.min(NUM_STAGES_NT - 1, num_v_tiles)\n for v_tile in range(prefetch_count):\n stage = v_tile % NUM_STAGES_NT\n gSrc_tile = gSrc[(None, None, v_tile)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_a = cutlass.Float32(a[i_n, 0, i_hv])\n r_b = cutlass.Float32(b[i_n, 0, i_hv])\n\n r_g = 0.0\n r_beta = 0.0\n if in_warp_tid == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n cute.arch.barrier()\n\n if use_qk_l2norm:\n sum_q_partial = 0.0\n sum_k_partial = 0.0\n if tidx < TILE_K_NT:\n q_val = sQ[tidx]\n k_val = sK[tidx]\n sum_q_partial = q_val * q_val\n sum_k_partial = k_val * k_val\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q_partial += cute.arch.shuffle_sync_bfly(\n sum_q_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k_partial += cute.arch.shuffle_sync_bfly(\n sum_k_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n if in_warp_tid == 0:\n smem_o[warp_idx] = sum_q_partial\n smem_o[warp_idx + 8] = sum_k_partial\n cute.arch.barrier()\n\n inv_norm_q = 0.0\n inv_norm_k = 0.0\n if warp_idx == 0:\n local_sum_q = 0.0\n local_sum_k = 0.0\n if in_warp_tid < NUM_WARPS_LARGE_NT:\n local_sum_q = smem_o[in_warp_tid]\n local_sum_k = smem_o[in_warp_tid + 8]\n for offset in [4, 2, 1]:\n local_sum_q += cute.arch.shuffle_sync_bfly(\n local_sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n local_sum_k += cute.arch.shuffle_sync_bfly(\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n smem_o[0] = cute.rsqrt(local_sum_q + 1e-6, fastmath=True)\n smem_o[1] = cute.rsqrt(local_sum_k + 1e-6, fastmath=True)\n cute.arch.barrier()\n\n inv_norm_q = smem_o[0]\n inv_norm_k = smem_o[1]\n\n if tidx < TILE_K_NT:\n sK[tidx] = sK[tidx] * inv_norm_k\n sQ[tidx] = sQ[tidx] * scale * inv_norm_q\n cute.arch.barrier()\n else:\n if tidx < TILE_K_NT:\n sQ[tidx] = sQ[tidx] * scale\n cute.arch.barrier()\n\n for v_tile in range(num_v_tiles):\n stage = v_tile % NUM_STAGES_NT\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n next_v_tile = v_tile + prefetch_count\n if next_v_tile < num_v_tiles:\n next_stage = next_v_tile % NUM_STAGES_NT\n gSrc_next = gSrc[(None, None, next_v_tile)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n v_global = v_tile * TILE_V_NT + v_idx\n r_v = cutlass.Float32(v[i_n, 0, i_hv, v_global])\n\n sum_hk = 0.0\n for k_iter in range(NUM_K_ITERS_NT, unroll=8): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_NT\n k_idx = k_base + k_local\n h_val = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n sum_hk += h_val * r_k_val\n\n for offset in [4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset * V_PER_WARP_NT, mask=-1, mask_and_clamp=31\n )\n\n v_new = (r_v - sum_hk) * r_beta\n v_new = cute.arch.shuffle_sync(v_new, v_local)\n\n sum_hq = 0.0\n for k_iter in range(NUM_K_ITERS_NT, unroll=8): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_NT\n k_idx = k_base + k_local\n h_old = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n r_q_val = sQ[k_idx]\n h_new = h_old + r_k_val * v_new\n sData[(k_idx, v_idx, stage)] = h_new\n sum_hq += h_new * r_q_val\n\n for offset in [4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset * V_PER_WARP_NT, mask=-1, mask_and_clamp=31\n )\n\n if k_local == 0:\n v_global_out = v_tile * TILE_V_NT + v_idx\n o[(i_n, 0, i_hv, v_global_out)] = cutlass.BFloat16(sum_hq)\n\n cute.arch.barrier()\n\n for k_iter in cutlass.range_constexpr(NUM_K_ITERS_NT):\n flat_tid = tidx + k_iter * 256\n k_write = flat_tid // TILE_V_NT\n v_write = flat_tid % TILE_V_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_NT + v_write\n # Use flat index for flattened state [B*HV, K, V]\n h0_source[(flat_idx, k_write, v_global_write)] = h_val\n\n cute.arch.barrier()\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_nontranspose(\n cu_seqlens: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n h0_source: cute.Tensor,\n h0_indices: cute.Tensor,\n o: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source is flattened to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n batch_hv_dim, k_dim, v_dim = h0_source.layout.shape\n h0_indices.layout.shape[0]\n batch_size = batch_hv_dim # batch_hv_dim = B * HV\n\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n num_v_tiles_small = cute.ceil_div(v_dim, TILE_V_SMALL_NT)\n smem_layout_small = cute.make_layout(\n (TILE_K_NT, TILE_V_SMALL_NT, NUM_STAGES_NT),\n stride=(TILE_V_SMALL_PADDED_NT, 1, TILE_K_NT * TILE_V_SMALL_PADDED_NT),\n )\n thread_layout_small = cute.make_layout((32, 4), stride=(4, 1))\n val_layout_small = cute.make_layout((1, 4))\n tiled_copy_load_small = cute.make_tiled_copy_tv(\n copy_atom, thread_layout_small, val_layout_small\n )\n smem_bytes_small = (\n 4 * TILE_K_NT * TILE_V_SMALL_PADDED_NT * NUM_STAGES_NT\n + 4 * TILE_V_SMALL_NT\n + 4 * TILE_K_NT * 2\n + 64\n )\n\n gdn_decode_kernel_small_batch_nontranspose(\n tiled_copy_load_small,\n h0_source,\n smem_layout_small,\n num_v_tiles_small,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n o,\n h0_indices,\n softplus_beta,\n softplus_threshold,\n scale,\n H,\n HV,\n use_qk_l2norm,\n ).launch(\n grid=(batch_size * NUM_BLOCKS_PER_STATE_SMALL_NT, 1, 1),\n block=[NUM_THREADS_NT, 1, 1],\n smem=smem_bytes_small,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_nontranspose(\n cu_seqlens: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n h0_source: cute.Tensor,\n h0_indices: cute.Tensor,\n o: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source is flattened to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n batch_hv_dim, k_dim, v_dim = h0_source.layout.shape\n h0_indices.layout.shape[0]\n batch_size = batch_hv_dim # batch_hv_dim = B * HV\n\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n num_v_tiles = cute.ceil_div(v_dim, TILE_V_NT)\n base_smem_layout = cute.make_layout(\n (TILE_K_NT, TILE_V_NT, NUM_STAGES_NT),\n stride=(TILE_V_PADDED_NT, 1, TILE_K_NT * TILE_V_PADDED_NT),\n )\n thread_layout = cute.make_layout((32, 8), stride=(8, 1))\n val_layout = cute.make_layout((1, 4))\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n smem_bytes = (\n 4 * TILE_K_NT * TILE_V_PADDED_NT * NUM_STAGES_NT\n + 4 * TILE_V_NT\n + 4 * TILE_K_NT * 2\n + 64\n )\n\n gdn_decode_kernel_big_batch_nontranspose(\n tiled_copy_load,\n h0_source,\n base_smem_layout,\n num_v_tiles,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n o,\n h0_indices,\n softplus_beta,\n softplus_threshold,\n scale,\n H,\n HV,\n use_qk_l2norm,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS_LARGE_NT, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# FlashInfer API Layer - NONTRANSPOSE Version (Recommended)\n# ============================================================================\n\n\n@flashinfer_api\ndef gated_delta_rule_decode(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n state: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Gated Delta Rule Decode kernel (K-major layout, no transpose needed).\n\n This implements the decode phase of gated delta rule linear attention,\n processing one token at a time and updating the recurrent state.\n This version uses K-major state layout [B, HV, K, V] which is more natural\n and doesn't require transposition.\n\n Args:\n q (torch.Tensor):\n Current query of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n k (torch.Tensor):\n Current key of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n v (torch.Tensor):\n Current value of shape ``[B, 1, HV, V]``. Must be float16/bfloat16.\n state (torch.Tensor):\n Current state of shape ``[B, HV, K, V]`` (k-major layout).\n Must be float32. Will be updated in-place.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``. Must be float32.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``. Must be bfloat16 or float32.\n b (torch.Tensor):\n Update gate (beta) input of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n scale (Optional[float]):\n Scale factor for queries. If None, defaults to ``1 / sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, 1, HV, V]``.\n If None, will be allocated automatically.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, 1, HV, V]``\n - state: Updated state tensor of shape ``[B, HV, K, V]``\n\n Note:\n - Requires SM90 (Hopper) architecture\n - State is updated in-place\n - K and V must be multiples of 4 for vectorized loads\n - State layout is k-major: [B, HV, K, V] (no transpose needed)\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n assert T == 1, f\"Decode only supports T=1, got T={T}\"\n _, _, HV, V = v.shape\n\n # Validate state shape\n assert state.shape == (B, HV, K, V), (\n f\"Expected state shape [B={B}, HV={HV}, K={K}, V={V}], got {state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n # V must be divisible by tile size to prevent out-of-bounds access\n # For small batch: TILE_V_SMALL_NT=16, for large batch: TILE_V_NT=32\n # Use the more restrictive constraint (32) to cover both cases\n assert V % TILE_V_NT == 0, (\n f\"V must be divisible by {TILE_V_NT} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert state.dtype == torch.float32, f\"state must be float32, got {state.dtype}\"\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # State is in K-major layout [B, HV, K, V]\n # Flatten to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n # This avoids alignment issues when B=1 (zero strides cause alignment failures)\n state_contiguous = state.contiguous()\n h0_source = state_contiguous.view(B * HV, K, V)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel_nontranspose(*cache_key)\n\n # Get or create h0_indices and cu_seqlens (cached per config)\n if \"h0_indices\" not in cache or cache[\"h0_indices\"].device != q.device:\n cache[\"h0_indices\"] = torch.arange(B, dtype=torch.int32, device=q.device)\n cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n h0_indices = cache[\"h0_indices\"]\n cu_seqlens = cache[\"cu_seqlens\"]\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Choose kernel based on batch size\n use_small_batch = B < SMALL_BATCH_THRESHOLD_NT\n\n if use_small_batch:\n run_func = run_gdn_decode_kernel_small_batch_nontranspose\n else:\n run_func = run_gdn_decode_kernel_big_batch_nontranspose\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n cu_seqlens_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n a_tensor,\n b_tensor,\n A_log_tensor,\n dt_bias_tensor,\n h0_source_tensor,\n h0_indices_tensor,\n o_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n B=B,\n T=T,\n H=H,\n HV=HV,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n compiled(\n cu_seqlens,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n h0_source,\n h0_indices,\n output,\n stream,\n )\n\n # Copy state back only if state was not contiguous\n # (if contiguous, state_contiguous is state itself, so kernel updated state in-place)\n if state_contiguous.data_ptr() != state.data_ptr():\n state.copy_(state_contiguous)\n\n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, state\n\n\n# ============================================================================\n# MTP (Multiple Token Processing) Kernel - for T > 1 (verify mode)\n# ============================================================================\n\n\n@cute.kernel\ndef gdn_verify_kernel_mtp(\n h0_source: cute.Tensor, # [pool_size * HV, V, K] - initial state pool (K-last)\n intermediate_states: cute.Tensor, # [pool_size * T * HV, V, K] - intermediate state cache\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n tile_v: cutlass.Constexpr[int], # TILE_V - configurable for batch size\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n disable_state_update: cutlass.Constexpr[bool],\n cache_intermediate_states: cutlass.Constexpr[bool],\n):\n \"\"\"\n Parallel MTP kernel - each block handles one [TILE_V, TILE_K] tile.\n\n Grid: (B * HV * num_v_tiles, 1, 1)\n Each block:\n - Loads its v_tile of state into registers\n - Processes all T time steps with state in registers\n - Writes output and optionally updates state\n\n This matches Triton's parallelization strategy for better small-batch performance.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n\n # Compute thread grouping based on vec_size:\n # vec_size=8: 16 threads per group (half-warp), 8 groups per block\n # vec_size=4: 32 threads per group (full warp), 4 groups per block\n threads_per_group: cutlass.Constexpr[int] = K // vec_size # 16 or 32\n groups_per_warp: cutlass.Constexpr[int] = 32 // threads_per_group # 2 or 1\n num_groups: cutlass.Constexpr[int] = 4 * groups_per_warp # 8 or 4\n\n # Lane position within group and group index\n lane_in_group = lane_id % threads_per_group\n group_in_warp = lane_id // threads_per_group\n group_idx = warp_idx * groups_per_warp + group_in_warp\n\n batch_idx, _, _ = cute.arch.block_idx()\n\n # Decode block index: (i_n, i_hv, i_v) from batch_idx\n i_v = batch_idx % num_v_tiles\n tmp = batch_idx // num_v_tiles\n i_hv = tmp % HV\n i_n = tmp // HV\n i_h = i_hv // (HV // H)\n\n # Get initial state index for this batch\n cache_idx = h0_indices[i_n]\n\n # Load A_log and dt_bias once (they don't vary with time)\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n\n # Allocate shared memory for pre-computed values (broadcast to all warps)\n smem = cutlass.utils.SmemAllocator()\n sQ = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sK = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sG = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n sBeta = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n\n # Register arrays for computation\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Only process valid batch entries (cache_idx >= 0)\n if cache_idx >= 0:\n # Compute k_start once (used for shared memory writes)\n k_start = lane_in_group * vec_size\n\n # Pre-compute q, k, g, beta for ALL time steps ONCE (shared across warps)\n for i_t in cutlass.range_constexpr(T):\n # Load q, k into BF16 registers using autovec_copy (coalesced)\n q_tile = cute.local_tile(\n q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_in_group)\n )\n k_tile = cute.local_tile(\n k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_in_group)\n )\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32 for computation\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Apply L2 normalization to q, k (with scale fused for q)\n if cutlass.const_expr(use_qk_l2norm):\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n\n # Warp-level reduction (32 threads per group with vec_size=4)\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Fuse scale into q's normalization factor\n inv_norm_q_scaled = cute.rsqrt(sum_q + 1e-6, fastmath=True) * scale\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q_scaled\n r_k[i] = r_k[i] * inv_norm_k\n else:\n # No L2 norm, just apply scale to q\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # Store to shared memory (only first group writes) - contiguous layout\n if tidx < threads_per_group:\n for i in cutlass.range_constexpr(vec_size):\n sQ[(i_t, k_start + i)] = r_q[i]\n sK[(i_t, k_start + i)] = r_k[i]\n\n # Compute g, beta - all lanes compute (redundant but no divergence)\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n\n # Branchless softplus\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n softplus_val = (cutlass.Float32(1.0) / softplus_beta) * cute.log(\n cutlass.Float32(1.0) + exp_beta_x, fastmath=True\n )\n use_softplus = (\n cutlass.Float32(1.0)\n if beta_x <= softplus_threshold\n else cutlass.Float32(0.0)\n )\n softplus_x = (\n use_softplus * softplus_val + (cutlass.Float32(1.0) - use_softplus) * x\n )\n\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n r_beta = cutlass.Float32(1.0) / (\n cutlass.Float32(1.0) + cute.exp(-r_b, fastmath=True)\n )\n r_g = cute.exp(r_g_value, fastmath=True)\n\n # Only thread 0 stores to shared memory\n if tidx == 0:\n sG[i_t] = r_g\n sBeta[i_t] = r_beta\n\n cute.arch.barrier()\n\n # Each group handles tile_v/num_groups V rows\n rows_per_group: cutlass.Constexpr[int] = tile_v // num_groups\n for row_in_group in cutlass.range_constexpr(rows_per_group):\n v_idx = i_v * tile_v + group_idx * rows_per_group + row_in_group\n\n if v_idx < V:\n # Load h[v_idx, :] into registers using 3D local_tile + autovec_copy\n flat_state_idx = cache_idx * HV + i_hv\n h_tile = cute.local_tile(\n h0_source, (1, 1, vec_size), (flat_state_idx, v_idx, lane_in_group)\n )\n cute.autovec_copy(h_tile, r_h)\n\n # Process all T time steps with h in registers\n for i_t in cutlass.range_constexpr(T):\n # Load pre-computed q, k from shared memory using 2D local_tile\n sQ_tile = cute.local_tile(sQ, (1, vec_size), (i_t, lane_in_group))\n sK_tile = cute.local_tile(sK, (1, vec_size), (i_t, lane_in_group))\n cute.autovec_copy(sQ_tile, r_q)\n cute.autovec_copy(sK_tile, r_k)\n\n r_g = sG[i_t]\n r_beta = sBeta[i_t]\n\n # Step 1: Apply decay to h\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n\n # Step 2: Compute sum_hk = h @ k (group reduction)\n sum_hk = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_hk += r_h[i] * r_k[i]\n\n # Warp-level reduction\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Step 3: Load v for this v_idx and time step, apply delta rule\n r_v = cutlass.Float32(v[i_n, i_t, i_hv, v_idx])\n v_new = (r_v - sum_hk) * r_beta\n\n # Step 4: Update h: h += k * v_new\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n\n # Cache intermediate state if needed using 3D local_tile + autovec_copy\n if cutlass.const_expr(cache_intermediate_states):\n flat_idx = i_n * T * HV + i_t * HV + i_hv\n inter_tile = cute.local_tile(\n intermediate_states,\n (1, 1, vec_size),\n (flat_idx, v_idx, lane_in_group),\n )\n cute.autovec_copy(r_h, inter_tile)\n\n # Step 5: Compute output: sum_hq = h @ q (group reduction)\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_hq += r_h[i] * r_q[i]\n\n # Warp-level reduction\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Write output (only lane 0 of each group)\n if lane_in_group == 0:\n o[(i_n, i_t, i_hv, v_idx)] = cutlass.BFloat16(sum_hq)\n\n # Write final state back (if not disabled) using 3D local_tile + autovec_copy\n if cutlass.const_expr(not disable_state_update):\n h_tile_out = cute.local_tile(\n h0_source,\n (1, 1, vec_size),\n (flat_state_idx, v_idx, lane_in_group),\n )\n cute.autovec_copy(r_h, h_tile_out)\n\n\n@cute.jit\ndef run_gdn_verify_kernel_mtp(\n h0_source: cute.Tensor,\n intermediate_states: cute.Tensor,\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n tile_v: cutlass.Constexpr[int], # TILE_V - configurable for batch size\n vec_size: cutlass.Constexpr[int], # 4 for full warp, 8 for half-warp\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n disable_state_update: cutlass.Constexpr[bool],\n cache_intermediate_states: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n _, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n num_v_tiles = cute.ceil_div(v_dim, tile_v)\n\n # Grid: (B * HV * num_v_tiles, 1, 1) - parallelize across V dimension\n grid_size = B * HV * num_v_tiles\n\n # Shared memory for pre-computed q, k, g, beta\n smem_bytes = (\n 4 * T * (k_dim + 8) # sQ\n + 4 * T * (k_dim + 8) # sK\n + 4 * T # sG\n + 4 * T # sBeta\n + 128 # alignment\n )\n\n gdn_verify_kernel_mtp(\n h0_source,\n intermediate_states,\n vec_size,\n num_v_tiles,\n tile_v,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n disable_state_update,\n cache_intermediate_states,\n ).launch(\n grid=(grid_size, 1, 1),\n block=[NUM_THREADS_MTP, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@functools.cache\ndef _get_compiled_mtp_kernel(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n pool_size: int,\n cache_steps: int,\n disable_state_update: bool,\n cache_intermediate_states: bool,\n scale: float,\n use_qk_l2norm: bool,\n tile_v: int, # TILE_V - configurable for batch size\n vec_size: int, # 4 for full warp, 8 for half-warp\n):\n \"\"\"Cache compiled MTP kernel for given configuration.\"\"\"\n return {}\n\n\n@flashinfer_api\ndef gated_delta_rule_mtp(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n initial_state: torch.Tensor,\n initial_state_indices: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n intermediate_states_buffer: Optional[torch.Tensor] = None,\n disable_state_update: bool = True,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n \"\"\"\n Gated Delta Rule MTP Kernel (Multiple Token Processing).\n\n This function processes multiple tokens (T > 1) in sequence, typically used for\n speculative decoding verification. It supports intermediate state caching for\n potential rollback scenarios.\n\n Args:\n q (torch.Tensor):\n Query tensor of shape ``[B, T, H, K]``.\n k (torch.Tensor):\n Key tensor of shape ``[B, T, H, K]``.\n v (torch.Tensor):\n Value tensor of shape ``[B, T, HV, V]``.\n initial_state (torch.Tensor):\n Initial state tensor of shape ``[pool_size, HV, V, K]`` (K-last layout).\n initial_state_indices (torch.Tensor):\n Indices mapping each batch to its initial state, shape ``[B]``.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, T, HV]``.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``.\n b (torch.Tensor):\n Update gate input of shape ``[B, T, HV]``.\n scale (Optional[float]):\n Scaling factor for queries. If None, uses ``1/sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, T, HV, V]``.\n intermediate_states_buffer (Optional[torch.Tensor]):\n Buffer for caching intermediate states, shape ``[pool_size, T, HV, V, K]``.\n If None, intermediate states are not cached.\n disable_state_update (bool):\n If True, the initial state is not updated. Default: ``True``.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, T, HV, V]``\n - initial_state: Updated state tensor (unchanged if disable_state_update=True)\n\n Note:\n - Requires SM90 (Hopper) architecture\n - Supports T > 1 (multiple token processing)\n - State layout is K-last: [pool_size, HV, V, K]\n - Optimized for speculative decoding verification scenarios\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n _, _, HV, V = v.shape\n pool_size = initial_state.shape[0]\n\n # Dynamic TILE_V and vec_size selection based on batch size and sequence length\n tile_v = get_tile_v_mtp(B, T)\n vec_size = get_vec_size_mtp(B, T)\n\n # Validate state shape\n assert initial_state.shape == (pool_size, HV, V, K), (\n f\"Expected initial_state shape [pool_size={pool_size}, HV={HV}, V={V}, K={K}], got {initial_state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n assert V % tile_v == 0, (\n f\"V must be divisible by {tile_v} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert initial_state.dtype == torch.float32, (\n f\"initial_state must be float32, got {initial_state.dtype}\"\n )\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # Reshape initial_state from [pool_size, HV, V, K] to [pool_size * HV, V, K]\n h0_source = initial_state.to(torch.float32).reshape(pool_size * HV, V, K)\n\n # Handle intermediate states\n cache_intermediate_states = intermediate_states_buffer is not None\n if cache_intermediate_states:\n buffer_size = intermediate_states_buffer.shape[0]\n cache_steps = intermediate_states_buffer.shape[1]\n\n # Validate buffer length matches query sequence length\n assert cache_steps >= T, (\n f\"intermediate_states_buffer second dimension (cache_steps={cache_steps}) must be at least T={T} to prevent out-of-bounds indexing\"\n )\n\n intermediate_states = (\n intermediate_states_buffer.to(torch.float32)\n .reshape(buffer_size * cache_steps * HV, V, K)\n .contiguous()\n )\n else:\n cache_steps = T\n intermediate_states = torch.zeros(1, 1, 1, dtype=torch.float32, device=q.device)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (\n B,\n T,\n H,\n HV,\n K,\n V,\n pool_size,\n cache_steps,\n disable_state_update,\n cache_intermediate_states,\n scale,\n use_qk_l2norm,\n tile_v,\n vec_size,\n )\n cache = _get_compiled_mtp_kernel(*cache_key)\n\n # Get or create cu_seqlens (cached per config)\n if \"cu_seqlens\" not in cache or cache[\"cu_seqlens\"].device != q.device:\n cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n cu_seqlens = cache[\"cu_seqlens\"]\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n intermediate_states_tensor = from_dlpack(intermediate_states, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(initial_state_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_gdn_verify_kernel_mtp,\n h0_source_tensor,\n intermediate_states_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n B=B,\n T=T,\n H=H,\n K=K,\n V=V,\n tile_v=tile_v,\n vec_size=vec_size,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n disable_state_update=disable_state_update,\n cache_intermediate_states=cache_intermediate_states,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n compiled(\n h0_source,\n intermediate_states,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n output,\n initial_state_indices,\n cu_seqlens,\n stream,\n )\n\n # Copy state back if needed (no sync needed - PyTorch handles stream ordering)\n # Only copy if state update is enabled AND initial_state was not contiguous\n # (if contiguous, reshape returns a view and kernel updated state in-place)\n if not disable_state_update and not initial_state.is_contiguous():\n initial_state.copy_(h0_source.reshape(pool_size, HV, V, K))\n\n # Convert output to target dtype if needed\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, initial_state\n"},"diff":{"kind":"string","value":"--- flashinfer/gdn_decode.py\n+++ flashinfer/gdn_decode.py\n@@ -186,47 +186,48 @@\n i_h = i_hv // (HV // H)\n i_t = 0\n \n+ smem = cutlass.utils.SmemAllocator()\n+\n+ # ===================================================================\n+ # Allocate shared memory (using passed-in layout)\n+ # ===================================================================\n+ sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n+\n+ # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n+ sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n+\n+ # Allocate shared memory for v values (size K, to reduce register usage)\n+ sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n+\n+ r_k = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n+ )\n+ r_q = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n+ )\n+ # r_v moved to shared memory (sV)\n+ r_h = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n+ )\n+ # BF16 register tensors for vectorized q, k, v loading\n+ r_q_bf16 = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n+ )\n+ r_k_bf16 = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n+ )\n+ r_v_bf16 = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n+ )\n+\n+ # Compute k_start for contiguous access pattern\n+ k_start = lane_id * vec_size\n+\n+ # Read gate values from GMEM EARLY (before barrier, latency hidden during sync)\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n-\n- smem = cutlass.utils.SmemAllocator()\n-\n- # ===================================================================\n- # Allocate shared memory (using passed-in layout)\n- # ===================================================================\n- sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n-\n- # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n- sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n-\n- # Allocate shared memory for v values (size K, to reduce register usage)\n- sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n-\n- r_k = cute.make_rmem_tensor(\n- cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n- )\n- r_q = cute.make_rmem_tensor(\n- cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n- )\n- # r_v moved to shared memory (sV)\n- r_h = cute.make_rmem_tensor(\n- cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n- )\n- # BF16 register tensors for vectorized q, k, v loading\n- r_q_bf16 = cute.make_rmem_tensor(\n- cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n- )\n- r_k_bf16 = cute.make_rmem_tensor(\n- cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n- )\n- r_v_bf16 = cute.make_rmem_tensor(\n- cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n- )\n-\n- # Compute k_start for contiguous access pattern\n- k_start = lane_id * vec_size\n \n cute.arch.barrier()\n \n@@ -1102,11 +1103,8 @@\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n \n- # Choose kernel based on batch size\n- if B <= 32:\n- run_func = run_gdn_decode_kernel_small_batch_pretranspose\n- else:\n- run_func = run_gdn_decode_kernel_big_batch_pretranspose\n+ # Always use 8-CTA architecture (benchmarks show it's better for all batch sizes)\n+ run_func = run_gdn_decode_kernel_small_batch_pretranspose\n \n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile("},"lines_added":{"kind":"number","value":40,"string":"40"},"lines_removed":{"kind":"number","value":42,"string":"42"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_decode.py).\n\nGoal: Perf: Optimize GDN decode pretranspose kernel for all batch sizes\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\n\"\"\"\nGated Delta Rule Decode Kernel - Single Token Generation\n\nThis file implements a fused CUDA kernel using CUTLASS CuTe DSL for executing\nSigmoid Gating Delta Rule updates during decode phase. Key features:\n\nArchitecture Design:\n- Uses TMA (Tensor Memory Accelerator) for efficient Global Memory → Shared Memory transfers\n- Employs 2-stage pipeline to overlap loading and computation, hiding memory latency\n- Each block uses 128 threads (4 warps), with each warp processing one matrix row\n- Tile size: 8x128 (TILE_V x TILE_K)\n\nComputation Flow:\n1. Warp 0 handles TMA prefetch, loading data from GMEM to SMEM\n2. All warps compute in parallel: softplus, L2 normalization, delta rule updates\n3. Each warp processes one row of data, completing h_new = g*h + k*(beta*(v - h@k))\n4. Uses warp-level shuffle for efficient reduction operations\n5. Results are vectorized and written back to Global Memory\n\nPerformance Optimizations:\n- Vectorized memory access: each thread processes vec_size=4 elements (128-bit aligned)\n- Warp-level collective operations: shuffle-based reduction\n- Pipeline overlap: load stage N+1 while computing stage N\n\"\"\"\n\nimport functools\nfrom typing import Optional, Tuple\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass.cute.nvgpu import cpasync\nfrom cutlass.cute.runtime import from_dlpack\nimport cuda.bindings.driver as cuda\n\ntry:\n from .api_logging import flashinfer_api\n\n _FLASHINFER_AVAILABLE = True\nexcept ImportError:\n _FLASHINFER_AVAILABLE = False\n\n # Fallback decorator for standalone usage\n def flashinfer_api(func): # type: ignore[misc]\n return func\n\n\n# GDN decode K-last bf16 state kernel (T=1..4, bf16 state, K-last layout) - optional backend\ntry:\n from .gdn_kernels.gdn_decode_bf16_state import (\n gated_delta_rule as _gated_delta_rule_gdn_decode_klast_bf16_state,\n )\n\n _GDN_DECODE_KLAST_BF16_STATE_AVAILABLE = True\nexcept ImportError:\n _GDN_DECODE_KLAST_BF16_STATE_AVAILABLE = False\n _gated_delta_rule_gdn_decode_klast_bf16_state = None\n\n\n# ============================================================================\n# Global configuration for PRETRANSPOSE version ([B*HV, V, K])\n# ============================================================================\nTILE_V = 8\nTILE_K = 128\nNUM_STAGES = 2\nNUM_THREADS = 128 # 4 warps\nNUM_BLOCKS_PER_STATE = 8\n\n# ============================================================================\n# Global configuration for NONTRANSPOSE version ([pool, HV, K, V])\n# ============================================================================\nTILE_K_NT = 128\nTILE_V_NT = 32\nTILE_V_PADDED_NT = 36\nTILE_V_SMALL_NT = 16\nTILE_V_SMALL_PADDED_NT = 20\nNUM_STAGES_NT = 2\nNUM_THREADS_NT = 128\nNUM_BLOCKS_PER_STATE_SMALL_NT = 8\nNUM_THREADS_LARGE_NT = 256\nNUM_WARPS_LARGE_NT = 8\nV_PER_WARP_NT = 4\nROWS_PER_ITER_NT = 8\nNUM_K_ITERS_NT = TILE_K_NT // ROWS_PER_ITER_NT\nSMALL_BATCH_THRESHOLD_NT = 32\n\n# ============================================================================\n# Global configuration for MTP (Multiple Token Processing) version\n# ============================================================================\n# Dynamic kernel selection based on batch size:\n# - Small batch (B <= threshold): Use smaller TILE_V for more parallelism\n# Optimal TILE_V depends on batch size (empirically determined):\n# B=1-2: TILE_V=4 (more blocks, better parallelism for tiny batches)\n# B=4: TILE_V=8 (intermediate parallelism)\n# B=8: TILE_V=16 (balance between parallelism and efficiency)\n# B>=16: TILE_V=32 (fewer blocks, better efficiency for large batches)\n\nTILE_K_MTP = 128 # Full K dimension (shared across all configs)\nNUM_THREADS_MTP = 128 # 4 warps (shared across all configs)\n\n\ndef get_vec_size_mtp(batch_size: int, seq_len: int = 1) -> int:\n \"\"\"Select vec_size for MTP kernel.\n\n Always use vec_size=4 (32 threads per group = full warp, 4 groups per block).\n Full warp shuffle is more efficient and achieves >= 1.0x speedup vs Triton.\n \"\"\"\n return 4\n\n\ndef get_tile_v_mtp(batch_size: int, seq_len: int = 1) -> int:\n \"\"\"Select optimal TILE_V for MTP kernel based on batch size and sequence length.\n\n With vec_size=4, num_groups=4, rows_per_group = tile_v / 4.\n Tuned via grid search for optimal performance.\n \"\"\"\n if batch_size <= 2:\n return 4 # Small batch needs max parallelism\n elif batch_size <= 4:\n return 8\n elif batch_size <= 8:\n return 16\n elif batch_size <= 16:\n return 32\n else:\n return 64\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n cute.arch.barrier()\n\n # Get current batch\n gSrc_batch = h0_source[(batch_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (batch_idx, None, 0))\n\n # V 方向分 tiles\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n start_v_tiles = batch_inner * num_v_tiles_per_block\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles_per_block)\n for v_tiles in range(start_v_tiles, start_v_tiles + prefetch_count):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n end_v_tiles = start_v_tiles + num_v_tiles_per_block\n for v_tiles in range(start_v_tiles, end_v_tiles):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < end_v_tiles:\n next_stage = (next_v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n gDst_tile = cute.local_tile(\n gDst, (1, 1, vec_size, 1), (0, row + row_offset, lane_id, v_tiles)\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n if tidx >= start_v_tiles * TILE_V and tidx < end_v_tiles * TILE_V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n cute.arch.barrier()\n\n # Get current batch\n gSrc_batch = h0_source[(batch_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (batch_idx, None, 0))\n\n # V 方向分 tiles\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles)\n for v_tiles in range(prefetch_count):\n stage = v_tiles % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n for v_tiles in range(num_v_tiles):\n stage = v_tiles % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < num_v_tiles:\n next_stage = next_v_tiles % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n gDst_tile = cute.local_tile(\n gDst, (1, 1, vec_size, 1), (0, row + row_offset, lane_id, v_tiles)\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n \"\"\"Launch original pipelined kernel for small batch pretranspose.\"\"\"\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * batch_size * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n ).launch(\n grid=(batch_size * NUM_BLOCKS_PER_STATE, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * batch_size * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # print(f\"Batched CP.ASYNC Load + Store (bypass L1 cache)\")\n # print(f\" {batch_size} batches x {v_dim}x{k_dim} matrices\")\n # print(f\" Tile: {TILE_V}x{TILE_K}, {num_v_tiles} tiles/batch\")\n # print(f\" Threads: {NUM_THREADS} ({NUM_THREADS // 32} warps), vec_size: {vec_size}\")\n # print(f\" Total: {total_data_mb:.1f} MB\\n\")\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# FlashInfer API Layer\n# ============================================================================\n\n\n@functools.cache\ndef _get_compiled_decode_kernel(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled kernel for given configuration (pretranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\n@functools.cache\ndef _get_compiled_decode_kernel_nontranspose(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled kernel for given configuration (nontranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\n@flashinfer_api\ndef gated_delta_rule_decode_pretranspose(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n state: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Gated Delta Rule Decode kernel for single-token generation.\n\n This implements the decode phase of gated delta rule linear attention,\n processing one token at a time and updating the recurrent state.\n\n Args:\n q (torch.Tensor):\n Current query of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n k (torch.Tensor):\n Current key of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n v (torch.Tensor):\n Current value of shape ``[B, 1, HV, V]``. Must be float16/bfloat16.\n state (torch.Tensor):\n Current state of shape ``[B, HV, V, K]`` (v-major / K-last layout).\n Float32: legacy kernel (T=1 only). Bfloat16: gdn_decode_klast_bf16_state backend\n when T in 1..4 and K=V=128. Will be updated in-place.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``. Must be float32.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``. Must be bfloat16 or float32.\n b (torch.Tensor):\n Update gate (beta) input of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n scale (Optional[float]):\n Scale factor for queries. If None, defaults to ``1 / sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, 1, HV, V]``.\n If None, will be allocated automatically.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, 1, HV, V]``\n - state: Updated state tensor of shape ``[B, HV, V, K]``\n\n Note:\n - Requires SM90 (Hopper) architecture\n - State is updated in-place\n - State layout is v-major (K-last): [B, HV, V, K]. When state is bfloat16\n and T in 1..4 with K=V=128, the gdn_decode_klast_bf16_state kernel is used.\n - Legacy path (float32 state, T=1): K and V must be multiples of 4.\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n _, _, HV, V = v.shape\n\n # Validate state shape (Qwen-style K-last: [B, HV, V, K])\n assert state.shape == (B, HV, V, K), (\n f\"Expected state shape [B={B}, HV={HV}, V={V}, K={K}], got {state.shape}\"\n )\n\n # Backend: gdn_decode_klast_bf16_state when bf16 state, T<=4, K-last layout, K=V=128\n use_gdn_decode_klast_bf16_state = (\n _GDN_DECODE_KLAST_BF16_STATE_AVAILABLE\n and state.dtype == torch.bfloat16\n and T in (1, 2, 3, 4)\n and K == 128\n and V == 128\n )\n if use_gdn_decode_klast_bf16_state:\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n scale_val = K**-0.5 if scale is None else scale\n out = _gated_delta_rule_gdn_decode_klast_bf16_state(\n A_log=A_log,\n a=a,\n dt_bias=dt_bias,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n q=q,\n k=k,\n v=v,\n b=b,\n initial_state_source=state,\n use_qk_l2norm_in_kernel=use_qk_l2norm,\n scale=scale_val,\n )\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n if output is not None:\n output.copy_(out)\n else:\n output = out\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n return output, state\n\n # Legacy path: T=1 only, float32 state\n assert T == 1, f\"Decode only supports T=1, got T={T}\"\n assert state.dtype == torch.float32, f\"state must be float32, got {state.dtype}\"\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n assert V % TILE_V == 0, (\n f\"V must be divisible by {TILE_V} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n # Note: kernel outputs bfloat16, we'll convert to q.dtype if needed\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # Convert state from [B, HV, V, K] to [B*HV, V, K] for kernel\n h0_source = state.reshape(B * HV, V, K)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel(*cache_key)\n\n # Get or create h0_indices and cu_seqlens (cached per config)\n if \"h0_indices\" not in cache or cache[\"h0_indices\"].device != q.device:\n cache[\"h0_indices\"] = torch.zeros(B, dtype=torch.int32, device=q.device)\n cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n h0_indices = cache[\"h0_indices\"]\n cu_seqlens = cache[\"cu_seqlens\"]\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Choose kernel based on batch size\n if B <= 32:\n run_func = run_gdn_decode_kernel_small_batch_pretranspose\n else:\n run_func = run_gdn_decode_kernel_big_batch_pretranspose\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n h0_source_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n B=B,\n T=T,\n H=H,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n cache[\"compiled\"](\n h0_source, A_log, a, dt_bias, q, k, v, b, output, h0_indices, cu_seqlens, stream\n )\n\n # Copy state back only if state was not contiguous\n # (if contiguous, reshape returns a view and kernel updated state in-place)\n if not state.is_contiguous():\n state.copy_(h0_source.reshape(B, HV, V, K))\n\n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, state\n\n\n# ============================================================================\n# NONTRANSPOSE Version Kernels - K-major layout [pool, HV, K, V]\n# ============================================================================\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_nontranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n num_v_tiles: cutlass.Constexpr[int],\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n use_qk_l2norm: cutlass.Constexpr[bool],\n):\n \"\"\"Small batch kernel for (N, 1, ...) format with K-major state layout.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n in_warp_tid = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n\n NUM_WARPS_SMALL = 4\n V_PER_WARP_SMALL = TILE_V_SMALL_NT // NUM_WARPS_SMALL\n ROWS_PER_ITER_SMALL = 32 // V_PER_WARP_SMALL\n NUM_K_ITERS_SMALL = TILE_K_NT // ROWS_PER_ITER_SMALL\n\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE_SMALL_NT\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE_SMALL_NT\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE_SMALL_NT\n start_v_tile = batch_inner * num_v_tiles_per_block\n\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n pool_idx = h0_indices[i_n]\n\n if pool_idx >= 0:\n k_local = in_warp_tid // V_PER_WARP_SMALL\n v_local = in_warp_tid % V_PER_WARP_SMALL\n v_base = warp_idx * V_PER_WARP_SMALL\n v_idx = v_base + v_local\n\n smem = cutlass.utils.SmemAllocator()\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n smem_o_layout = cute.make_layout((TILE_V_SMALL_NT,), stride=(1,))\n smem_o = smem.allocate_tensor(cutlass.Float32, smem_o_layout, 128)\n smem_k_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n smem_q_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n sK = smem.allocate_tensor(cutlass.Float32, smem_k_layout, 128)\n sQ = smem.allocate_tensor(cutlass.Float32, smem_q_layout, 128)\n\n if tidx < TILE_K_NT:\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n\n # Compute flat index for flattened state [B*HV, K, V]\n flat_idx = pool_idx * HV + i_hv\n gSrc_batch = h0_source[(flat_idx, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_SMALL_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n prefetch_count = cutlass.min(NUM_STAGES_NT - 1, num_v_tiles_per_block)\n for v_tile_offset in range(prefetch_count):\n v_tile = start_v_tile + v_tile_offset\n stage = v_tile_offset % NUM_STAGES_NT\n gSrc_tile = gSrc[(None, None, v_tile)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_a = cutlass.Float32(a[i_n, 0, i_hv])\n r_b = cutlass.Float32(b[i_n, 0, i_hv])\n\n r_g = 0.0\n r_beta = 0.0\n if in_warp_tid == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n cute.arch.barrier()\n\n if use_qk_l2norm:\n sum_q_partial = 0.0\n sum_k_partial = 0.0\n if tidx < TILE_K_NT:\n q_val = sQ[tidx]\n k_val = sK[tidx]\n sum_q_partial = q_val * q_val\n sum_k_partial = k_val * k_val\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q_partial += cute.arch.shuffle_sync_bfly(\n sum_q_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k_partial += cute.arch.shuffle_sync_bfly(\n sum_k_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n if in_warp_tid == 0:\n smem_o[warp_idx] = sum_q_partial\n smem_o[warp_idx + 4] = sum_k_partial\n cute.arch.barrier()\n\n inv_norm_q = 0.0\n inv_norm_k = 0.0\n if warp_idx == 0:\n local_sum_q = 0.0\n local_sum_k = 0.0\n if in_warp_tid < NUM_WARPS_SMALL:\n local_sum_q = smem_o[in_warp_tid]\n local_sum_k = smem_o[in_warp_tid + 4]\n for offset in [2, 1]:\n local_sum_q += cute.arch.shuffle_sync_bfly(\n local_sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n local_sum_k += cute.arch.shuffle_sync_bfly(\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n smem_o[0] = cute.rsqrt(local_sum_q + 1e-6, fastmath=True)\n smem_o[1] = cute.rsqrt(local_sum_k + 1e-6, fastmath=True)\n cute.arch.barrier()\n\n inv_norm_q = smem_o[0]\n inv_norm_k = smem_o[1]\n\n if tidx < TILE_K_NT:\n sK[tidx] = sK[tidx] * inv_norm_k\n sQ[tidx] = sQ[tidx] * scale * inv_norm_q\n cute.arch.barrier()\n else:\n if tidx < TILE_K_NT:\n sQ[tidx] = sQ[tidx] * scale\n cute.arch.barrier()\n\n for v_tile_offset in range(num_v_tiles_per_block):\n v_tile = start_v_tile + v_tile_offset\n stage = v_tile_offset % NUM_STAGES_NT\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n next_v_tile_offset = v_tile_offset + prefetch_count\n if next_v_tile_offset < num_v_tiles_per_block:\n next_v_tile = start_v_tile + next_v_tile_offset\n next_stage = next_v_tile_offset % NUM_STAGES_NT\n gSrc_next = gSrc[(None, None, next_v_tile)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n v_global = v_tile * TILE_V_SMALL_NT + v_idx\n r_v = cutlass.Float32(v[i_n, 0, i_hv, v_global])\n\n sum_hk = 0.0\n for k_iter in range(NUM_K_ITERS_SMALL, unroll=16): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_SMALL\n k_idx = k_base + k_local\n h_val = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n sum_hk += h_val * r_k_val\n\n for offset in [4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk,\n offset=offset * V_PER_WARP_SMALL,\n mask=-1,\n mask_and_clamp=31,\n )\n\n v_new = (r_v - sum_hk) * r_beta\n v_new = cute.arch.shuffle_sync(v_new, v_local)\n\n sum_hq = 0.0\n for k_iter in range(NUM_K_ITERS_SMALL, unroll=16): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_SMALL\n k_idx = k_base + k_local\n h_old = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n r_q_val = sQ[k_idx]\n h_new = h_old + r_k_val * v_new\n sData[(k_idx, v_idx, stage)] = h_new\n sum_hq += h_new * r_q_val\n\n for offset in [4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq,\n offset=offset * V_PER_WARP_SMALL,\n mask=-1,\n mask_and_clamp=31,\n )\n\n if k_local == 0:\n v_global_out = v_tile * TILE_V_SMALL_NT + v_idx\n o[(i_n, 0, i_hv, v_global_out)] = cutlass.BFloat16(sum_hq)\n\n cute.arch.barrier()\n\n for k_iter in cutlass.range_constexpr(NUM_K_ITERS_SMALL):\n flat_tid = tidx + k_iter * 128\n k_write = flat_tid // TILE_V_SMALL_NT\n v_write = flat_tid % TILE_V_SMALL_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_SMALL_NT + v_write\n # Use flat index for flattened state [B*HV, K, V]\n h0_source[(flat_idx, k_write, v_global_write)] = h_val\n\n cute.arch.barrier()\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_nontranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n num_v_tiles: cutlass.Constexpr[int],\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n use_qk_l2norm: cutlass.Constexpr[bool],\n):\n \"\"\"Large batch kernel for (N, 1, ...) format with K-major state layout.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n in_warp_tid = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n pool_idx = h0_indices[i_n]\n\n if pool_idx >= 0:\n k_local = in_warp_tid // V_PER_WARP_NT\n v_local = in_warp_tid % V_PER_WARP_NT\n v_base = warp_idx * V_PER_WARP_NT\n v_idx = v_base + v_local\n\n smem = cutlass.utils.SmemAllocator()\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n smem_o_layout = cute.make_layout((TILE_V_NT,), stride=(1,))\n smem_o = smem.allocate_tensor(cutlass.Float32, smem_o_layout, 128)\n smem_k_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n smem_q_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n sK = smem.allocate_tensor(cutlass.Float32, smem_k_layout, 128)\n sQ = smem.allocate_tensor(cutlass.Float32, smem_q_layout, 128)\n\n if tidx < TILE_K_NT:\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n\n # Compute flat index for flattened state [B*HV, K, V]\n flat_idx = pool_idx * HV + i_hv\n gSrc_batch = h0_source[(flat_idx, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n prefetch_count = cutlass.min(NUM_STAGES_NT - 1, num_v_tiles)\n for v_tile in range(prefetch_count):\n stage = v_tile % NUM_STAGES_NT\n gSrc_tile = gSrc[(None, None, v_tile)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_a = cutlass.Float32(a[i_n, 0, i_hv])\n r_b = cutlass.Float32(b[i_n, 0, i_hv])\n\n r_g = 0.0\n r_beta = 0.0\n if in_warp_tid == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n cute.arch.barrier()\n\n if use_qk_l2norm:\n sum_q_partial = 0.0\n sum_k_partial = 0.0\n if tidx < TILE_K_NT:\n q_val = sQ[tidx]\n k_val = sK[tidx]\n sum_q_partial = q_val * q_val\n sum_k_partial = k_val * k_val\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q_partial += cute.arch.shuffle_sync_bfly(\n sum_q_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k_partial += cute.arch.shuffle_sync_bfly(\n sum_k_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n if in_warp_tid == 0:\n smem_o[warp_idx] = sum_q_partial\n smem_o[warp_idx + 8] = sum_k_partial\n cute.arch.barrier()\n\n inv_norm_q = 0.0\n inv_norm_k = 0.0\n if warp_idx == 0:\n local_sum_q = 0.0\n local_sum_k = 0.0\n if in_warp_tid < NUM_WARPS_LARGE_NT:\n local_sum_q = smem_o[in_warp_tid]\n local_sum_k = smem_o[in_warp_tid + 8]\n for offset in [4, 2, 1]:\n local_sum_q += cute.arch.shuffle_sync_bfly(\n local_sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n local_sum_k += cute.arch.shuffle_sync_bfly(\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n smem_o[0] = cute.rsqrt(local_sum_q + 1e-6, fastmath=True)\n smem_o[1] = cute.rsqrt(local_sum_k + 1e-6, fastmath=True)\n cute.arch.barrier()\n\n inv_norm_q = smem_o[0]\n inv_norm_k = smem_o[1]\n\n if tidx < TILE_K_NT:\n sK[tidx] = sK[tidx] * inv_norm_k\n sQ[tidx] = sQ[tidx] * scale * inv_norm_q\n cute.arch.barrier()\n else:\n if tidx < TILE_K_NT:\n sQ[tidx] = sQ[tidx] * scale\n cute.arch.barrier()\n\n for v_tile in range(num_v_tiles):\n stage = v_tile % NUM_STAGES_NT\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n next_v_tile = v_tile + prefetch_count\n if next_v_tile < num_v_tiles:\n next_stage = next_v_tile % NUM_STAGES_NT\n gSrc_next = gSrc[(None, None, next_v_tile)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n v_global = v_tile * TILE_V_NT + v_idx\n r_v = cutlass.Float32(v[i_n, 0, i_hv, v_global])\n\n sum_hk = 0.0\n for k_iter in range(NUM_K_ITERS_NT, unroll=8): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_NT\n k_idx = k_base + k_local\n h_val = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n sum_hk += h_val * r_k_val\n\n for offset in [4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset * V_PER_WARP_NT, mask=-1, mask_and_clamp=31\n )\n\n v_new = (r_v - sum_hk) * r_beta\n v_new = cute.arch.shuffle_sync(v_new, v_local)\n\n sum_hq = 0.0\n for k_iter in range(NUM_K_ITERS_NT, unroll=8): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_NT\n k_idx = k_base + k_local\n h_old = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n r_q_val = sQ[k_idx]\n h_new = h_old + r_k_val * v_new\n sData[(k_idx, v_idx, stage)] = h_new\n sum_hq += h_new * r_q_val\n\n for offset in [4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset * V_PER_WARP_NT, mask=-1, mask_and_clamp=31\n )\n\n if k_local == 0:\n v_global_out = v_tile * TILE_V_NT + v_idx\n o[(i_n, 0, i_hv, v_global_out)] = cutlass.BFloat16(sum_hq)\n\n cute.arch.barrier()\n\n for k_iter in cutlass.range_constexpr(NUM_K_ITERS_NT):\n flat_tid = tidx + k_iter * 256\n k_write = flat_tid // TILE_V_NT\n v_write = flat_tid % TILE_V_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_NT + v_write\n # Use flat index for flattened state [B*HV, K, V]\n h0_source[(flat_idx, k_write, v_global_write)] = h_val\n\n cute.arch.barrier()\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_nontranspose(\n cu_seqlens: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n h0_source: cute.Tensor,\n h0_indices: cute.Tensor,\n o: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source is flattened to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n batch_hv_dim, k_dim, v_dim = h0_source.layout.shape\n h0_indices.layout.shape[0]\n batch_size = batch_hv_dim # batch_hv_dim = B * HV\n\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n num_v_tiles_small = cute.ceil_div(v_dim, TILE_V_SMALL_NT)\n smem_layout_small = cute.make_layout(\n (TILE_K_NT, TILE_V_SMALL_NT, NUM_STAGES_NT),\n stride=(TILE_V_SMALL_PADDED_NT, 1, TILE_K_NT * TILE_V_SMALL_PADDED_NT),\n )\n thread_layout_small = cute.make_layout((32, 4), stride=(4, 1))\n val_layout_small = cute.make_layout((1, 4))\n tiled_copy_load_small = cute.make_tiled_copy_tv(\n copy_atom, thread_layout_small, val_layout_small\n )\n smem_bytes_small = (\n 4 * TILE_K_NT * TILE_V_SMALL_PADDED_NT * NUM_STAGES_NT\n + 4 * TILE_V_SMALL_NT\n + 4 * TILE_K_NT * 2\n + 64\n )\n\n gdn_decode_kernel_small_batch_nontranspose(\n tiled_copy_load_small,\n h0_source,\n smem_layout_small,\n num_v_tiles_small,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n o,\n h0_indices,\n softplus_beta,\n softplus_threshold,\n scale,\n H,\n HV,\n use_qk_l2norm,\n ).launch(\n grid=(batch_size * NUM_BLOCKS_PER_STATE_SMALL_NT, 1, 1),\n block=[NUM_THREADS_NT, 1, 1],\n smem=smem_bytes_small,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_nontranspose(\n cu_seqlens: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n h0_source: cute.Tensor,\n h0_indices: cute.Tensor,\n o: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source is flattened to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n batch_hv_dim, k_dim, v_dim = h0_source.layout.shape\n h0_indices.layout.shape[0]\n batch_size = batch_hv_dim # batch_hv_dim = B * HV\n\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n num_v_tiles = cute.ceil_div(v_dim, TILE_V_NT)\n base_smem_layout = cute.make_layout(\n (TILE_K_NT, TILE_V_NT, NUM_STAGES_NT),\n stride=(TILE_V_PADDED_NT, 1, TILE_K_NT * TILE_V_PADDED_NT),\n )\n thread_layout = cute.make_layout((32, 8), stride=(8, 1))\n val_layout = cute.make_layout((1, 4))\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n smem_bytes = (\n 4 * TILE_K_NT * TILE_V_PADDED_NT * NUM_STAGES_NT\n + 4 * TILE_V_NT\n + 4 * TILE_K_NT * 2\n + 64\n )\n\n gdn_decode_kernel_big_batch_nontranspose(\n tiled_copy_load,\n h0_source,\n base_smem_layout,\n num_v_tiles,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n o,\n h0_indices,\n softplus_beta,\n softplus_threshold,\n scale,\n H,\n HV,\n use_qk_l2norm,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS_LARGE_NT, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# FlashInfer API Layer - NONTRANSPOSE Version (Recommended)\n# ============================================================================\n\n\n@flashinfer_api\ndef gated_delta_rule_decode(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n state: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Gated Delta Rule Decode kernel (K-major layout, no transpose needed).\n\n This implements the decode phase of gated delta rule linear attention,\n processing one token at a time and updating the recurrent state.\n This version uses K-major state layout [B, HV, K, V] which is more natural\n and doesn't require transposition.\n\n Args:\n q (torch.Tensor):\n Current query of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n k (torch.Tensor):\n Current key of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n v (torch.Tensor):\n Current value of shape ``[B, 1, HV, V]``. Must be float16/bfloat16.\n state (torch.Tensor):\n Current state of shape ``[B, HV, K, V]`` (k-major layout).\n Must be float32. Will be updated in-place.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``. Must be float32.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``. Must be bfloat16 or float32.\n b (torch.Tensor):\n Update gate (beta) input of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n scale (Optional[float]):\n Scale factor for queries. If None, defaults to ``1 / sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, 1, HV, V]``.\n If None, will be allocated automatically.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, 1, HV, V]``\n - state: Updated state tensor of shape ``[B, HV, K, V]``\n\n Note:\n - Requires SM90 (Hopper) architecture\n - State is updated in-place\n - K and V must be multiples of 4 for vectorized loads\n - State layout is k-major: [B, HV, K, V] (no transpose needed)\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n assert T == 1, f\"Decode only supports T=1, got T={T}\"\n _, _, HV, V = v.shape\n\n # Validate state shape\n assert state.shape == (B, HV, K, V), (\n f\"Expected state shape [B={B}, HV={HV}, K={K}, V={V}], got {state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n # V must be divisible by tile size to prevent out-of-bounds access\n # For small batch: TILE_V_SMALL_NT=16, for large batch: TILE_V_NT=32\n # Use the more restrictive constraint (32) to cover both cases\n assert V % TILE_V_NT == 0, (\n f\"V must be divisible by {TILE_V_NT} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert state.dtype == torch.float32, f\"state must be float32, got {state.dtype}\"\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # State is in K-major layout [B, HV, K, V]\n # Flatten to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n # This avoids alignment issues when B=1 (zero strides cause alignment failures)\n state_contiguous = state.contiguous()\n h0_source = state_contiguous.view(B * HV, K, V)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel_nontranspose(*cache_key)\n\n # Get or create h0_indices and cu_seqlens (cached per config)\n if \"h0_indices\" not in cache or cache[\"h0_indices\"].device != q.device:\n cache[\"h0_indices\"] = torch.arange(B, dtype=torch.int32, device=q.device)\n cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n h0_indices = cache[\"h0_indices\"]\n cu_seqlens = cache[\"cu_seqlens\"]\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Choose kernel based on batch size\n use_small_batch = B < SMALL_BATCH_THRESHOLD_NT\n\n if use_small_batch:\n run_func = run_gdn_decode_kernel_small_batch_nontranspose\n else:\n run_func = run_gdn_decode_kernel_big_batch_nontranspose\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n cu_seqlens_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n a_tensor,\n b_tensor,\n A_log_tensor,\n dt_bias_tensor,\n h0_source_tensor,\n h0_indices_tensor,\n o_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n B=B,\n T=T,\n H=H,\n HV=HV,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n compiled(\n cu_seqlens,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n h0_source,\n h0_indices,\n output,\n stream,\n )\n\n # Copy state back only if state was not contiguous\n # (if contiguous, state_contiguous is state itself, so kernel updated state in-place)\n if state_contiguous.data_ptr() != state.data_ptr():\n state.copy_(state_contiguous)\n\n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, state\n\n\n# ============================================================================\n# MTP (Multiple Token Processing) Kernel - for T > 1 (verify mode)\n# ============================================================================\n\n\n@cute.kernel\ndef gdn_verify_kernel_mtp(\n h0_source: cute.Tensor, # [pool_size * HV, V, K] - initial state pool (K-last)\n intermediate_states: cute.Tensor, # [pool_size * T * HV, V, K] - intermediate state cache\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n tile_v: cutlass.Constexpr[int], # TILE_V - configurable for batch size\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n disable_state_update: cutlass.Constexpr[bool],\n cache_intermediate_states: cutlass.Constexpr[bool],\n):\n \"\"\"\n Parallel MTP kernel - each block handles one [TILE_V, TILE_K] tile.\n\n Grid: (B * HV * num_v_tiles, 1, 1)\n Each block:\n - Loads its v_tile of state into registers\n - Processes all T time steps with state in registers\n - Writes output and optionally updates state\n\n This matches Triton's parallelization strategy for better small-batch performance.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n\n # Compute thread grouping based on vec_size:\n # vec_size=8: 16 threads per group (half-warp), 8 groups per block\n # vec_size=4: 32 threads per group (full warp), 4 groups per block\n threads_per_group: cutlass.Constexpr[int] = K // vec_size # 16 or 32\n groups_per_warp: cutlass.Constexpr[int] = 32 // threads_per_group # 2 or 1\n num_groups: cutlass.Constexpr[int] = 4 * groups_per_warp # 8 or 4\n\n # Lane position within group and group index\n lane_in_group = lane_id % threads_per_group\n group_in_warp = lane_id // threads_per_group\n group_idx = warp_idx * groups_per_warp + group_in_warp\n\n batch_idx, _, _ = cute.arch.block_idx()\n\n # Decode block index: (i_n, i_hv, i_v) from batch_idx\n i_v = batch_idx % num_v_tiles\n tmp = batch_idx // num_v_tiles\n i_hv = tmp % HV\n i_n = tmp // HV\n i_h = i_hv // (HV // H)\n\n # Get initial state index for this batch\n cache_idx = h0_indices[i_n]\n\n # Load A_log and dt_bias once (they don't vary with time)\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n\n # Allocate shared memory for pre-computed values (broadcast to all warps)\n smem = cutlass.utils.SmemAllocator()\n sQ = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sK = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sG = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n sBeta = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n\n # Register arrays for computation\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Only process valid batch entries (cache_idx >= 0)\n if cache_idx >= 0:\n # Compute k_start once (used for shared memory writes)\n k_start = lane_in_group * vec_size\n\n # Pre-compute q, k, g, beta for ALL time steps ONCE (shared across warps)\n for i_t in cutlass.range_constexpr(T):\n # Load q, k into BF16 registers using autovec_copy (coalesced)\n q_tile = cute.local_tile(\n q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_in_group)\n )\n k_tile = cute.local_tile(\n k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_in_group)\n )\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32 for computation\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Apply L2 normalization to q, k (with scale fused for q)\n if cutlass.const_expr(use_qk_l2norm):\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n\n # Warp-level reduction (32 threads per group with vec_size=4)\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Fuse scale into q's normalization factor\n inv_norm_q_scaled = cute.rsqrt(sum_q + 1e-6, fastmath=True) * scale\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q_scaled\n r_k[i] = r_k[i] * inv_norm_k\n else:\n # No L2 norm, just apply scale to q\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # Store to shared memory (only first group writes) - contiguous layout\n if tidx < threads_per_group:\n for i in cutlass.range_constexpr(vec_size):\n sQ[(i_t, k_start + i)] = r_q[i]\n sK[(i_t, k_start + i)] = r_k[i]\n\n # Compute g, beta - all lanes compute (redundant but no divergence)\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n\n # Branchless softplus\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n softplus_val = (cutlass.Float32(1.0) / softplus_beta) * cute.log(\n cutlass.Float32(1.0) + exp_beta_x, fastmath=True\n )\n use_softplus = (\n cutlass.Float32(1.0)\n if beta_x <= softplus_threshold\n else cutlass.Float32(0.0)\n )\n softplus_x = (\n use_softplus * softplus_val + (cutlass.Float32(1.0) - use_softplus) * x\n )\n\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n r_beta = cutlass.Float32(1.0) / (\n cutlass.Float32(1.0) + cute.exp(-r_b, fastmath=True)\n )\n r_g = cute.exp(r_g_value, fastmath=True)\n\n # Only thread 0 stores to shared memory\n if tidx == 0:\n sG[i_t] = r_g\n sBeta[i_t] = r_beta\n\n cute.arch.barrier()\n\n # Each group handles tile_v/num_groups V rows\n rows_per_group: cutlass.Constexpr[int] = tile_v // num_groups\n for row_in_group in cutlass.range_constexpr(rows_per_group):\n v_idx = i_v * tile_v + group_idx * rows_per_group + row_in_group\n\n if v_idx < V:\n # Load h[v_idx, :] into registers using 3D local_tile + autovec_copy\n flat_state_idx = cache_idx * HV + i_hv\n h_tile = cute.local_tile(\n h0_source, (1, 1, vec_size), (flat_state_idx, v_idx, lane_in_group)\n )\n cute.autovec_copy(h_tile, r_h)\n\n # Process all T time steps with h in registers\n for i_t in cutlass.range_constexpr(T):\n # Load pre-computed q, k from shared memory using 2D local_tile\n sQ_tile = cute.local_tile(sQ, (1, vec_size), (i_t, lane_in_group))\n sK_tile = cute.local_tile(sK, (1, vec_size), (i_t, lane_in_group))\n cute.autovec_copy(sQ_tile, r_q)\n cute.autovec_copy(sK_tile, r_k)\n\n r_g = sG[i_t]\n r_beta = sBeta[i_t]\n\n # Step 1: Apply decay to h\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n\n # Step 2: Compute sum_hk = h @ k (group reduction)\n sum_hk = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_hk += r_h[i] * r_k[i]\n\n # Warp-level reduction\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Step 3: Load v for this v_idx and time step, apply delta rule\n r_v = cutlass.Float32(v[i_n, i_t, i_hv, v_idx])\n v_new = (r_v - sum_hk) * r_beta\n\n # Step 4: Update h: h += k * v_new\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n\n # Cache intermediate state if needed using 3D local_tile + autovec_copy\n if cutlass.const_expr(cache_intermediate_states):\n flat_idx = i_n * T * HV + i_t * HV + i_hv\n inter_tile = cute.local_tile(\n intermediate_states,\n (1, 1, vec_size),\n (flat_idx, v_idx, lane_in_group),\n )\n cute.autovec_copy(r_h, inter_tile)\n\n # Step 5: Compute output: sum_hq = h @ q (group reduction)\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_hq += r_h[i] * r_q[i]\n\n # Warp-level reduction\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Write output (only lane 0 of each group)\n if lane_in_group == 0:\n o[(i_n, i_t, i_hv, v_idx)] = cutlass.BFloat16(sum_hq)\n\n # Write final state back (if not disabled) using 3D local_tile + autovec_copy\n if cutlass.const_expr(not disable_state_update):\n h_tile_out = cute.local_tile(\n h0_source,\n (1, 1, vec_size),\n (flat_state_idx, v_idx, lane_in_group),\n )\n cute.autovec_copy(r_h, h_tile_out)\n\n\n@cute.jit\ndef run_gdn_verify_kernel_mtp(\n h0_source: cute.Tensor,\n intermediate_states: cute.Tensor,\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n tile_v: cutlass.Constexpr[int], # TILE_V - configurable for batch size\n vec_size: cutlass.Constexpr[int], # 4 for full warp, 8 for half-warp\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n disable_state_update: cutlass.Constexpr[bool],\n cache_intermediate_states: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n _, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n num_v_tiles = cute.ceil_div(v_dim, tile_v)\n\n # Grid: (B * HV * num_v_tiles, 1, 1) - parallelize across V dimension\n grid_size = B * HV * num_v_tiles\n\n # Shared memory for pre-computed q, k, g, beta\n smem_bytes = (\n 4 * T * (k_dim + 8) # sQ\n + 4 * T * (k_dim + 8) # sK\n + 4 * T # sG\n + 4 * T # sBeta\n + 128 # alignment\n )\n\n gdn_verify_kernel_mtp(\n h0_source,\n intermediate_states,\n vec_size,\n num_v_tiles,\n tile_v,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n disable_state_update,\n cache_intermediate_states,\n ).launch(\n grid=(grid_size, 1, 1),\n block=[NUM_THREADS_MTP, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@functools.cache\ndef _get_compiled_mtp_kernel(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n pool_size: int,\n cache_steps: int,\n disable_state_update: bool,\n cache_intermediate_states: bool,\n scale: float,\n use_qk_l2norm: bool,\n tile_v: int, # TILE_V - configurable for batch size\n vec_size: int, # 4 for full warp, 8 for half-warp\n):\n \"\"\"Cache compiled MTP kernel for given configuration.\"\"\"\n return {}\n\n\n@flashinfer_api\ndef gated_delta_rule_mtp(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n initial_state: torch.Tensor,\n initial_state_indices: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n intermediate_states_buffer: Optional[torch.Tensor] = None,\n disable_state_update: bool = True,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n \"\"\"\n Gated Delta Rule MTP Kernel (Multiple Token Processing).\n\n This function processes multiple tokens (T > 1) in sequence, typically used for\n speculative decoding verification. It supports intermediate state caching for\n potential rollback scenarios.\n\n Args:\n q (torch.Tensor):\n Query tensor of shape ``[B, T, H, K]``.\n k (torch.Tensor):\n Key tensor of shape ``[B, T, H, K]``.\n v (torch.Tensor):\n Value tensor of shape ``[B, T, HV, V]``.\n initial_state (torch.Tensor):\n Initial state tensor of shape ``[pool_size, HV, V, K]`` (K-last layout).\n initial_state_indices (torch.Tensor):\n Indices mapping each batch to its initial state, shape ``[B]``.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, T, HV]``.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``.\n b (torch.Tensor):\n Update gate input of shape ``[B, T, HV]``.\n scale (Optional[float]):\n Scaling factor for queries. If None, uses ``1/sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, T, HV, V]``.\n intermediate_states_buffer (Optional[torch.Tensor]):\n Buffer for caching intermediate states, shape ``[pool_size, T, HV, V, K]``.\n If None, intermediate states are not cached.\n disable_state_update (bool):\n If True, the initial state is not updated. Default: ``True``.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, T, HV, V]``\n - initial_state: Updated state tensor (unchanged if disable_state_update=True)\n\n Note:\n - Requires SM90 (Hopper) architecture\n - Supports T > 1 (multiple token processing)\n - State layout is K-last: [pool_size, HV, V, K]\n - Optimized for speculative decoding verification scenarios\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n _, _, HV, V = v.shape\n pool_size = initial_state.shape[0]\n\n # Dynamic TILE_V and vec_size selection based on batch size and sequence length\n tile_v = get_tile_v_mtp(B, T)\n vec_size = get_vec_size_mtp(B, T)\n\n # Validate state shape\n assert initial_state.shape == (pool_size, HV, V, K), (\n f\"Expected initial_state shape [pool_size={pool_size}, HV={HV}, V={V}, K={K}], got {initial_state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n assert V % tile_v == 0, (\n f\"V must be divisible by {tile_v} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert initial_state.dtype == torch.float32, (\n f\"initial_state must be float32, got {initial_state.dtype}\"\n )\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # Reshape initial_state from [pool_size, HV, V, K] to [pool_size * HV, V, K]\n h0_source = initial_state.to(torch.float32).reshape(pool_size * HV, V, K)\n\n # Handle intermediate states\n cache_intermediate_states = intermediate_states_buffer is not None\n if cache_intermediate_states:\n buffer_size = intermediate_states_buffer.shape[0]\n cache_steps = intermediate_states_buffer.shape[1]\n\n # Validate buffer length matches query sequence length\n assert cache_steps >= T, (\n f\"intermediate_states_buffer second dimension (cache_steps={cache_steps}) must be at least T={T} to prevent out-of-bounds indexing\"\n )\n\n intermediate_states = (\n intermediate_states_buffer.to(torch.float32)\n .reshape(buffer_size * cache_steps * HV, V, K)\n .contiguous()\n )\n else:\n cache_steps = T\n intermediate_states = torch.zeros(1, 1, 1, dtype=torch.float32, device=q.device)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (\n B,\n T,\n H,\n HV,\n K,\n V,\n pool_size,\n cache_steps,\n disable_state_update,\n cache_intermediate_states,\n scale,\n use_qk_l2norm,\n tile_v,\n vec_size,\n )\n cache = _get_compiled_mtp_kernel(*cache_key)\n\n # Get or create cu_seqlens (cached per config)\n if \"cu_seqlens\" not in cache or cache[\"cu_seqlens\"].device != q.device:\n cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n cu_seqlens = cache[\"cu_seqlens\"]\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n intermediate_states_tensor = from_dlpack(intermediate_states, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(initial_state_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_gdn_verify_kernel_mtp,\n h0_source_tensor,\n intermediate_states_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n B=B,\n T=T,\n H=H,\n K=K,\n V=V,\n tile_v=tile_v,\n vec_size=vec_size,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n disable_state_update=disable_state_update,\n cache_intermediate_states=cache_intermediate_states,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n compiled(\n h0_source,\n intermediate_states,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n output,\n initial_state_indices,\n cu_seqlens,\n stream,\n )\n\n # Copy state back if needed (no sync needed - PyTorch handles stream ordering)\n # Only copy if state update is enabled AND initial_state was not contiguous\n # (if contiguous, reshape returns a view and kernel updated state in-place)\n if not disable_state_update and not initial_state.is_contiguous():\n initial_state.copy_(h0_source.reshape(pool_size, HV, V, K))\n\n # Convert output to target dtype if needed\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, initial_state\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"Two optimizations:\n\n1. Early gate reads: Move gate GMEM reads (r_A_log, r_a, r_dt_bias, r_b) to immediately before the barrier, hiding memory latency during sync.\n\n2. Always use 8-CTA architecture: Remove batch size conditional that switched to big_batch (1 CTA) for B > 32. The 8-CTA small_batch kernel performs better for ALL batch sizes.\n\nBenchmark results (1000 iters, warmup=10, q_heads=16, k_heads=16, v_heads=32, head_size=128, bfloat16, qk_l2norm=ON):\n\n| Batch | Before (us) | After (us) | Improvement | |-------|-------------|------------|-------------|\n| 1 | 3.74 | 3.74 | ~same |\n| 2 | 4.22 | 4.22 | ~same |\n| 4 | 5.38 | 5.38 | ~same |\n| 8 | 7.68 | 7.65 | ~same |\n| 16 | 12.90 | 12.90 | ~same |\n| 32 | 23.04 | 23.04 | ~same |\n| 64 | 51.57 | 42.56 | ~17% |\n| 128 | 92.13 | 81.31 | ~12% |\n| 256 | 170.18 | 158.98 | ~7% |\n| 512 | 334.21 | 314.05 | ~6% |\n\nCorrectness verified on all batch sizes (1, 2, 4, 8, 16, 32, 64, 128, 256, 512).\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\n<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [ ] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **Refactor**\n * Optimized GPU kernel memory management sequences in decoding operations with improved synchronization and data loading patterns\n * Consolidated kernel execution logic by unifying batch-size handling, removing conditional branching for more consistent performance\n * Enhanced thread-level resource efficiency through refined writeback operations in the decoding pipeline\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 3.74, \"optimized\": 3.74, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128\", \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 4.22, \"optimized\": 4.22, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128\", \"batch_size\": 4, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 5.38, \"optimized\": 5.38, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 7.68, \"optimized\": 7.65, \"stated_speedup\": null, \"speedup\": 1.0039}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 12.9, \"optimized\": 12.9, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 23.04, \"optimized\": 23.04, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 51.57, \"optimized\": 42.56, \"stated_speedup\": 1.17, \"speedup\": 1.2117}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128\", \"batch_size\": 128, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 92.13, \"optimized\": 81.31, \"stated_speedup\": 1.12, \"speedup\": 1.1331}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128\", \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 170.18, \"optimized\": 158.98, \"stated_speedup\": 1.07, \"speedup\": 1.0704}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128\", \"batch_size\": 512, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 334.21, \"optimized\": 314.05, \"stated_speedup\": 1.06, \"speedup\": 1.0642}]"},"kernel_speedup":{"kind":"number","value":1.0019,"string":"1.0019"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1178,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"58128d1218979256e7fd487473758dd906f6f853"},"date":{"kind":"string","value":"2026-02-24T01:30:22+09:00"},"pr_number":{"kind":"number","value":2609,"string":"2,609"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2609"},"title":{"kind":"string","value":"docs: resolve TODO by documenting log2f vs logf performance rationale in sampling (#2609)"},"message":{"kind":"string","value":"docs: resolve TODO by documenting log2f vs logf performance rationale in sampling (#2609)\n\n## Summary\nResolved the TODO comment in `sampling.cuh` regarding `log2f` vs `logf`\nperformance comparison.\n\n## Changes\n- Removed `// TODO: compare the speed of log2 and log`\n- Added documentation explaining why `log2f` is preferred:\n - `log2f` maps to a single PTX `LG2` instruction on NVIDIA GPUs\n- `logf` internally computes `log2f * ln(2)`, requiring an extra\nmultiply\n- Current approach (3 ops) is more efficient than the `logf` alternative\n(4 ops)\n- Fixed `#pragma unroll` indentation to match surrounding code style\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n\n## Summary by CodeRabbit\n\n* **Chores**\n* Minor code improvements and formatting adjustments to internal\nsampling implementation.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"include/flashinfer/sampling.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_SAMPLING_CUH_\n#define FLASHINFER_SAMPLING_CUH_\n\n#include <cuda.h>\n#include <curand.h>\n#include <curand_kernel.h>\n#include <curand_philox4x32_x.h>\n\n#include <cstdlib>\n#include <cstring>\n#include <cub/cub.cuh>\n#include <cuda/functional>\n#include <cuda/std/functional>\n#include <cuda/std/limits>\n#include <limits>\n#include <numeric>\n#include <tuple>\n\n#include \"allocator.h\"\n#include \"math.cuh\"\n#include \"topk.cuh\"\n#include \"utils.cuh\"\n#include \"vec_dtypes.cuh\"\n\n// Define reduction operators based on CUDA version\n// CUDA 13 (12.9+) deprecated cub::Max/Min in favor of cuda::maximum/minimum\n#if CUDA_VERSION >= 12090\nusing MaxReduceOp = cuda::maximum<>;\nusing MinReduceOp = cuda::minimum<>;\n#else\nusing MaxReduceOp = cub::Max;\nusing MinReduceOp = cub::Min;\n#endif\n\nnamespace flashinfer {\n\nnamespace sampling {\n\nusing namespace cub;\n\n#define DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, ...) \\\n if (deterministic) { \\\n constexpr bool DETERMINISTIC = true; \\\n __VA_ARGS__ \\\n } else { \\\n constexpr bool DETERMINISTIC = false; \\\n __VA_ARGS__ \\\n }\n\n#define DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, ...) \\\n if (compute_capacity.first >= 8) { \\\n constexpr uint32_t BLOCK_THREADS = 1024; \\\n __VA_ARGS__ \\\n } else { \\\n constexpr uint32_t BLOCK_THREADS = 512; \\\n __VA_ARGS__ \\\n }\n\n#define DISPATCH_SOFTMAX_CACHE_INPUT(cache_input, CACHE_INPUT, ...) \\\n if (cache_input) { \\\n constexpr bool CACHE_INPUT = true; \\\n __VA_ARGS__ \\\n } else { \\\n constexpr bool CACHE_INPUT = false; \\\n __VA_ARGS__ \\\n }\n\nconstexpr BlockScanAlgorithm SCAN_ALGO = BLOCK_SCAN_WARP_SCANS;\nconstexpr BlockReduceAlgorithm REDUCE_ALGO = BLOCK_REDUCE_WARP_REDUCTIONS;\n\n#if (__CUDACC_VER_MAJOR__ * 10000 + __CUDACC_VER_MINOR__ * 100 >= 120100)\n#define FLASHINFER_CUB_SUBTRACTLEFT_DEFINED\n#endif\n\ntemplate <typename T>\nstruct ValueCount {\n T value;\n int count;\n\n __device__ ValueCount operator+(const ValueCount& other) const {\n return {value + other.value, count + other.count};\n }\n __device__ ValueCount& operator+=(const ValueCount& other) {\n value += other.value;\n count += other.count;\n return *this;\n }\n};\n\nstruct BoolDiffOp {\n __device__ __forceinline__ bool operator()(const bool& lhs, const bool& rhs) const {\n return lhs != rhs;\n }\n};\n\nstruct Float2SoftmaxReduceOp {\n __device__ __forceinline__ float2 operator()(const float2& a, const float2& b) const {\n if (isinf(a.x)) return b;\n if (isinf(b.x)) return a;\n\n float new_max = max(a.x, b.x);\n float new_denom = a.y * __expf(a.x - new_max) + b.y * __expf(b.x - new_max);\n return make_float2(new_max, new_denom);\n }\n};\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM>\nstruct SamplingTempStorage {\n union {\n float deterministic_scan[BLOCK_THREADS / 32];\n typename BlockScan<float, BLOCK_THREADS, SCAN_ALGORITHM>::TempStorage scan;\n typename BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage reduce;\n typename BlockReduce<int, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage reduce_int;\n typename BlockReduce<ValueCount<float>, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage\n reduce_value_count;\n typename BlockAdjacentDifference<bool, BLOCK_THREADS>::TempStorage adj_diff;\n } block_prim;\n struct {\n int32_t sampled_id;\n int32_t last_valid_id;\n float max_val;\n union {\n float value;\n ValueCount<float> pair;\n } block_aggregate;\n };\n};\n\ntemplate <uint32_t BLOCK_THREADS>\nstruct OnlineSoftmaxTempStorage {\n union {\n typename cub::BlockReduce<float, BLOCK_THREADS>::TempStorage reduce;\n typename cub::BlockReduce<float2, BLOCK_THREADS>::TempStorage reduce_pair;\n } block_prim;\n\n struct {\n float max_val;\n float denominator;\n } shared_state;\n};\n\nstruct PartialSoftmaxResult {\n float max_val;\n float denominator;\n};\n\n/*!\n * \\brief Deterministic inclusive scan implementation, use Belloch scan algorithm.\n * \\note This implementation is slower than the cub::BlockScan, but it is deterministic.\n */\ntemplate <uint32_t VEC_SIZE, uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM>\n__device__ __forceinline__ void DeterministicInclusiveSum(\n const float* in_data, float* out_data,\n SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>* temp_storage) {\n float* smem_prefix_sum = temp_storage->block_prim.deterministic_scan;\n float thread_data[VEC_SIZE];\n float thread_sum = 0;\n#pragma unroll\n for (uint32_t i = 0; i < VEC_SIZE; ++i) {\n thread_sum += in_data[i];\n thread_data[i] = thread_sum;\n }\n\n float thread_exclusive_prefix_sum = thread_sum;\n\n#pragma unroll\n for (uint32_t offset = 1; offset < 32; offset *= 2) {\n float tmp = __shfl_up_sync(0xffffffff, thread_exclusive_prefix_sum, offset);\n if ((threadIdx.x + 1) % (offset * 2) == 0) {\n thread_exclusive_prefix_sum += tmp;\n }\n }\n\n float warp_sum = __shfl_sync(0xffffffff, thread_exclusive_prefix_sum, threadIdx.x | 0xffffffff);\n if (threadIdx.x % 32 == 31) {\n thread_exclusive_prefix_sum = 0;\n }\n\n#pragma unroll\n for (uint32_t offset = 16; offset >= 1; offset /= 2) {\n float tmp = __shfl_xor_sync(0xffffffff, thread_exclusive_prefix_sum, offset);\n if ((threadIdx.x + 1) % (offset * 2) == 0) {\n thread_exclusive_prefix_sum = tmp + thread_exclusive_prefix_sum;\n }\n if ((threadIdx.x + 1) % (offset * 2) == offset) {\n thread_exclusive_prefix_sum = tmp;\n }\n }\n\n smem_prefix_sum[threadIdx.x / 32] = warp_sum;\n __syncthreads();\n\n if (threadIdx.x < 32) {\n float warp_exclusive_prefix_sum =\n (threadIdx.x < BLOCK_THREADS / 32) ? smem_prefix_sum[threadIdx.x] : 0;\n\n#pragma unroll\n for (uint32_t offset = 1; offset < 32; offset *= 2) {\n float tmp = __shfl_up_sync(0xffffffff, warp_exclusive_prefix_sum, offset);\n if ((threadIdx.x + 1) % (offset * 2) == 0) {\n warp_exclusive_prefix_sum += tmp;\n }\n }\n\n if (threadIdx.x % 32 == 31) {\n warp_exclusive_prefix_sum = 0;\n }\n\n#pragma unroll\n for (uint32_t offset = 16; offset >= 1; offset /= 2) {\n float tmp = __shfl_xor_sync(0xffffffff, warp_exclusive_prefix_sum, offset);\n if ((threadIdx.x + 1) % (offset * 2) == 0) {\n warp_exclusive_prefix_sum = tmp + warp_exclusive_prefix_sum;\n }\n if ((threadIdx.x + 1) % (offset * 2) == offset) {\n warp_exclusive_prefix_sum = tmp;\n }\n }\n if (threadIdx.x < BLOCK_THREADS / 32) {\n smem_prefix_sum[threadIdx.x] = warp_exclusive_prefix_sum;\n }\n }\n __syncthreads();\n\n#pragma unroll\n for (uint32_t i = 0; i < VEC_SIZE; ++i) {\n out_data[i] = smem_prefix_sum[threadIdx.x / 32] + thread_exclusive_prefix_sum + thread_data[i];\n }\n}\n\ntemplate <uint32_t VEC_SIZE, uint32_t BLOCK_THREADS, BlockReduceAlgorithm REDUCE_ALGORITHM,\n typename TempStorage>\n__device__ __forceinline__ float GetMaxValue(float* in_data, uint32_t row_idx, uint32_t d,\n TempStorage& temp_storage) {\n const uint32_t tx = threadIdx.x;\n vec_t<float, VEC_SIZE> in_data_vec;\n\n // Thread-local max accumulation (deferred reduction)\n float thread_max = 0.0f;\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n in_data_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n in_data_vec.cast_load(in_data + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n thread_max = max(thread_max, static_cast<float>(in_data_vec[j]));\n }\n }\n\n // Single block reduction after loop completes\n float max_val =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Reduce(thread_max, MaxReduceOp{});\n if (tx == 0) {\n temp_storage.max_val = max_val;\n }\n __syncthreads();\n return temp_storage.max_val;\n}\n\ntemplate <uint32_t BLOCK_THREADS, uint32_t VEC_SIZE, typename DType, bool CACHE_INPUT>\n__global__ void OnlineSoftmaxFusedKernel(DType* logits, DType* output, DType* temperature_arr,\n DType temperature_val, uint32_t d) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n float temperature = temperature_arr == nullptr ? temperature_val : temperature_arr[bx];\n const float inv_temp = (temperature == 0.f) ? 0.f : 1.f / temperature;\n\n using TempStorage = OnlineSoftmaxTempStorage<BLOCK_THREADS>;\n extern __shared__ __align__(alignof(TempStorage)) uint8_t smem[];\n auto& temp_storage = reinterpret_cast<TempStorage&>(smem);\n\n DType* smem_vec_base = nullptr;\n if constexpr (CACHE_INPUT) {\n constexpr size_t vec_alignment = alignof(vec_t<DType, VEC_SIZE>);\n size_t aligned_offset = round_up(sizeof(TempStorage), vec_alignment);\n smem_vec_base = reinterpret_cast<DType*>(smem + aligned_offset);\n }\n\n vec_t<DType, VEC_SIZE> logits_vec;\n\n float running_max = -cuda::std::numeric_limits<float>::infinity();\n float running_denominator = 0.0f;\n float threadlocal_running_denominator = 0.0f;\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n // Pass 1: Compute running max and denominator\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n logits_vec.fill(-cuda::std::numeric_limits<DType>::infinity());\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.cast_load(logits + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n logits_vec[j] *= inv_temp;\n }\n\n if constexpr (CACHE_INPUT) {\n logits_vec.store(smem_vec_base + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n }\n\n float thread_max = -cuda::std::numeric_limits<float>::infinity();\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n thread_max = max(thread_max, logits_vec[j]);\n }\n float block_max = cub::BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Reduce(thread_max, MaxReduceOp{});\n\n if (tx == 0) {\n temp_storage.shared_state.max_val = block_max;\n }\n __syncthreads();\n block_max = temp_storage.shared_state.max_val;\n // if block_max is -inf, then this block contains all -inf values, so we can skip updating\n if (!isinf(block_max)) {\n float threadlocal_sum = 0.0f;\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n threadlocal_sum += __expf(logits_vec[j] - block_max);\n }\n float new_max = max(running_max, block_max);\n threadlocal_running_denominator =\n threadlocal_running_denominator * __expf(running_max - new_max) +\n threadlocal_sum * __expf(block_max - new_max);\n running_max = new_max;\n }\n }\n\n running_denominator = cub::BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_running_denominator);\n if (tx == 0) {\n temp_storage.shared_state.denominator = running_denominator;\n }\n __syncthreads();\n running_denominator = temp_storage.shared_state.denominator;\n\n const float final_max = running_max;\n const float inv_denominator = 1.0f / running_denominator;\n\n // Pass 2: Normalize in place\n vec_t<DType, VEC_SIZE> prob_vec;\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n if constexpr (CACHE_INPUT) {\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.load(smem_vec_base + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n } else {\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.cast_load(logits + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n logits_vec[j] *= inv_temp;\n }\n }\n }\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n float p = __expf(static_cast<float>(logits_vec[j]) - final_max) * inv_denominator;\n prob_vec[j] = static_cast<DType>(p);\n }\n\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n prob_vec.cast_store(output + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n }\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\ntemplate <uint32_t BLOCK_THREADS, uint32_t VEC_SIZE, typename DType>\n__global__ void OnlineSoftmaxMapKernel(DType* logits, PartialSoftmaxResult* partial_results,\n DType* temperature_arr, float temperature_val, uint32_t d,\n uint32_t num_slices) {\n const uint32_t bx = blockIdx.x;\n const uint32_t by = blockIdx.y; // slice index\n const uint32_t tx = threadIdx.x;\n float temperature = temperature_arr == nullptr ? temperature_val : temperature_arr[bx];\n const float inv_temp = (temperature == 0.f) ? 0.f : 1.f / temperature;\n\n const uint32_t vec_alignment_elems = alignof(vec_t<DType, VEC_SIZE>) / sizeof(DType);\n const uint32_t slice_stride = round_up(ceil_div(d, num_slices), vec_alignment_elems);\n const uint32_t slice_start = by * slice_stride;\n const uint32_t slice_size = min((by + 1) * slice_stride, d) - slice_start;\n\n if (slice_start >= d) return;\n\n using TempStorage = OnlineSoftmaxTempStorage<BLOCK_THREADS>;\n extern __shared__ __align__(alignof(TempStorage)) uint8_t smem[];\n auto& temp_storage = reinterpret_cast<TempStorage&>(smem);\n\n vec_t<DType, VEC_SIZE> logits_vec;\n float running_max = -cuda::std::numeric_limits<float>::infinity();\n float running_denominator = 0.0f;\n float threadlocal_running_denominator = 0.0f;\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(slice_size, BLOCK_THREADS * VEC_SIZE); ++i) {\n logits_vec.fill(-cuda::std::numeric_limits<DType>::infinity());\n\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < slice_size) {\n logits_vec.cast_load(logits + bx * d + slice_start + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n float thread_max = -cuda::std::numeric_limits<float>::infinity();\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n logits_vec[j] *= inv_temp;\n thread_max = max(thread_max, logits_vec[j]);\n }\n\n float block_max = cub::BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Reduce(thread_max, MaxReduceOp{});\n\n if (tx == 0) {\n temp_storage.shared_state.max_val = block_max;\n }\n __syncthreads();\n block_max = temp_storage.shared_state.max_val;\n\n // if block_max is -inf, then this block contains all -inf values, so we can skip updating\n if (!isinf(block_max)) {\n float threadlocal_sum = 0.0f;\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n threadlocal_sum += __expf(logits_vec[j] - block_max);\n }\n float new_max = max(running_max, block_max);\n threadlocal_running_denominator =\n threadlocal_running_denominator * __expf(running_max - new_max) +\n threadlocal_sum * __expf(block_max - new_max);\n running_max = new_max;\n }\n }\n\n running_denominator = cub::BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_running_denominator);\n if (tx == 0) {\n temp_storage.shared_state.denominator = running_denominator;\n }\n __syncthreads();\n running_denominator = temp_storage.shared_state.denominator;\n\n if (tx == 0) {\n partial_results[bx * num_slices + by] = {running_max, running_denominator};\n }\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\ntemplate <uint32_t BLOCK_THREADS, uint32_t VEC_SIZE, typename DType>\n__global__ void OnlineSoftmaxReduceKernel(DType* logits, DType* output,\n PartialSoftmaxResult* partial_results,\n DType* temperature_arr, float temperature_val, uint32_t d,\n uint32_t num_slices) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x;\n float temperature = temperature_arr == nullptr ? temperature_val : temperature_arr[bx];\n const float inv_temp = (temperature == 0.f) ? 0.f : 1.f / temperature;\n\n // Reduce slice results\n using TempStorage = OnlineSoftmaxTempStorage<BLOCK_THREADS>;\n extern __shared__ __align__(alignof(TempStorage)) uint8_t smem[];\n auto& temp_storage = reinterpret_cast<TempStorage&>(smem);\n\n const Float2SoftmaxReduceOp reduce_op;\n\n float2 thread_aggregate = make_float2(-cuda::std::numeric_limits<float>::infinity(), 0.0f);\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n for (uint32_t i = tx; i < num_slices; i += BLOCK_THREADS) {\n PartialSoftmaxResult partial = partial_results[bx * num_slices + i];\n float2 partial_pair = make_float2(partial.max_val, partial.denominator);\n thread_aggregate = reduce_op(thread_aggregate, partial_pair);\n }\n\n float2 block_result = cub::BlockReduce<float2, BLOCK_THREADS>(temp_storage.block_prim.reduce_pair)\n .Reduce(thread_aggregate, reduce_op);\n\n if (tx == 0) {\n temp_storage.shared_state.max_val = block_result.x;\n temp_storage.shared_state.denominator = block_result.y;\n }\n __syncthreads();\n\n block_result =\n make_float2(temp_storage.shared_state.max_val, temp_storage.shared_state.denominator);\n\n const float final_max = temp_storage.shared_state.max_val;\n const float inv_denominator = 1.0f / temp_storage.shared_state.denominator;\n\n // Apply normalization\n vec_t<DType, VEC_SIZE> logits_vec;\n vec_t<DType, VEC_SIZE> prob_vec;\n\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n logits_vec.fill(-cuda::std::numeric_limits<DType>::infinity());\n\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.cast_load(logits + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n logits_vec[j] *= inv_temp;\n float p = __expf(static_cast<float>(logits_vec[j]) - final_max) * inv_denominator;\n prob_vec[j] = static_cast<DType>(p);\n }\n\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n prob_vec.cast_store(output + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n }\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\ntemplate <uint32_t VEC_SIZE, uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, bool DETERMINISTIC, typename Predicate>\n__device__ __forceinline__ void DeviceSamplingFromProb(\n uint32_t i, uint32_t d, Predicate pred, float u, vec_t<float, VEC_SIZE> prob_vec,\n float& aggregate,\n SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>* temp_storage) {\n const uint32_t tx = threadIdx.x;\n float prob_greater_than_threshold[VEC_SIZE];\n float inclusive_cdf[VEC_SIZE];\n bool greater_than_u[VEC_SIZE], valid[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n prob_greater_than_threshold[j] = pred(prob_vec[j]) ? prob_vec[j] : 0;\n valid[j] = pred(prob_vec[j]) && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d;\n }\n float aggregate_local =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage->block_prim.reduce)\n .template Sum<VEC_SIZE>(prob_greater_than_threshold);\n if (tx == 0) {\n temp_storage->block_aggregate.value = aggregate_local;\n }\n __syncthreads();\n aggregate_local = temp_storage->block_aggregate.value;\n\n if (aggregate + aggregate_local > u) {\n if constexpr (DETERMINISTIC) {\n DeterministicInclusiveSum<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>(\n prob_greater_than_threshold, inclusive_cdf, temp_storage);\n } else {\n BlockScan<float, BLOCK_THREADS, SCAN_ALGORITHM>(temp_storage->block_prim.scan)\n .template InclusiveSum<VEC_SIZE>(prob_greater_than_threshold, inclusive_cdf);\n\n __syncthreads();\n }\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n greater_than_u[j] = (inclusive_cdf[j] + aggregate > u) && valid[j];\n }\n\n bool greater_than_u_diff[VEC_SIZE];\n#ifdef FLASHINFER_CUB_SUBTRACTLEFT_DEFINED\n BlockAdjacentDifference<bool, BLOCK_THREADS>(temp_storage->block_prim.adj_diff)\n .SubtractLeft<VEC_SIZE>(greater_than_u, greater_than_u_diff, BoolDiffOp());\n#else\n BlockAdjacentDifference<bool, BLOCK_THREADS>(temp_storage->block_prim.adj_diff)\n .template FlagHeads<VEC_SIZE>(greater_than_u_diff, greater_than_u, BoolDiffOp(), 0);\n#endif\n __syncthreads();\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n if (greater_than_u_diff[j]) {\n atomicMin(&(temp_storage->sampled_id), (i * BLOCK_THREADS + tx) * VEC_SIZE + j);\n }\n }\n __syncthreads();\n }\n\n // update the last valid index\n int valid_index[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n if (valid[j]) {\n valid_index[j] = (i * BLOCK_THREADS + tx) * VEC_SIZE + j;\n } else {\n valid_index[j] = -1;\n }\n }\n int max_valid_index =\n BlockReduce<int, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage->block_prim.reduce_int)\n .Reduce(valid_index, MaxReduceOp{});\n if (tx == 0 && max_valid_index != -1) {\n temp_storage->last_valid_id = max_valid_index;\n }\n __syncthreads();\n aggregate += aggregate_local;\n}\n\ntemplate <typename DType, typename IdType>\nstruct DataAndIndex {\n DType data;\n IdType index;\n\n __device__ DataAndIndex operator+(const DataAndIndex& other) const {\n if (data > other.data) {\n return {data, index};\n } else {\n return {other.data, other.index};\n }\n }\n __device__ DataAndIndex& operator+=(const DataAndIndex& other) {\n if (data > other.data) {\n return *this;\n } else {\n data = other.data;\n index = other.index;\n return *this;\n }\n }\n};\n\ntemplate <typename DType, uint32_t VEC_SIZE>\n__device__ __forceinline__ vec_t<DType, VEC_SIZE> GenerateGumbelNoise(uint64_t philox_seed,\n uint64_t philox_offset,\n uint64_t subsequence) {\n curandStatePhilox4_32_10_t state;\n vec_t<float, VEC_SIZE> noise;\n constexpr float kSCALE = 1.0f - cuda::std::numeric_limits<float>::epsilon();\n constexpr float kLOG2 = 0.6931471806f;\n auto uniform2gumbel = [](float x) {\n // NB: cuRAND returns strictly positive normal floating point numbers, up to\n // and including 1.0. kSCALE is used to exclude 1.0, s.t.\n // 1.18e-38 <= x * kSCALE <= 1.0f - epsilon\n // => -4.47 <= -log(-log(...)) <= 15.9\n return -kLOG2 * log2f(-log2f((x * kSCALE)));\n };\n// TODO: compare the speed of log2 and log\n#pragma unroll\n for (uint32_t i = 0; i + 4 <= VEC_SIZE; i += 4) {\n curand_init(philox_seed, subsequence + i, philox_offset, &state);\n float4 noise_vec = curand_uniform4(&state);\n noise[i] = uniform2gumbel(noise_vec.x);\n noise[i + 1] = uniform2gumbel(noise_vec.y);\n noise[i + 2] = uniform2gumbel(noise_vec.z);\n noise[i + 3] = uniform2gumbel(noise_vec.w);\n }\n if constexpr (VEC_SIZE % 4 != 0) {\n curand_init(philox_seed, subsequence + VEC_SIZE / 4 * 4, philox_offset, &state);\n float4 noise_vec = curand_uniform4(&state);\n if constexpr (VEC_SIZE % 4 == 1) {\n noise[VEC_SIZE - 1] = uniform2gumbel(noise_vec.x);\n } else if constexpr (VEC_SIZE % 4 == 2) {\n noise[VEC_SIZE - 2] = uniform2gumbel(noise_vec.x);\n noise[VEC_SIZE - 1] = uniform2gumbel(noise_vec.y);\n } else if constexpr (VEC_SIZE % 4 == 3) {\n noise[VEC_SIZE - 3] = uniform2gumbel(noise_vec.x);\n noise[VEC_SIZE - 2] = uniform2gumbel(noise_vec.y);\n noise[VEC_SIZE - 1] = uniform2gumbel(noise_vec.z);\n }\n }\n\n if constexpr (std::is_same_v<DType, float>) {\n return noise;\n } else {\n vec_t<DType, VEC_SIZE> ret;\n#pragma unroll\n for (uint32_t i = 0; i < VEC_SIZE; ++i) {\n ret[i] = static_cast<DType>(noise[i]);\n }\n return ret;\n }\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void SamplingFromLogitsKernel(DType* logits, IdType* output, IdType* indices, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n using SharedMem = typename BlockReduce<DataAndIndex<DType, IdType>, BLOCK_THREADS,\n REDUCE_ALGORITHM>::TempStorage;\n extern __shared__ __align__(alignof(SharedMem)) uint8_t smem_sampling_logit[];\n auto& temp_storage = reinterpret_cast<SharedMem&>(smem_sampling_logit);\n\n vec_t<DType, VEC_SIZE> logits_vec;\n DataAndIndex<DType, IdType> max_data = {-cuda::std::numeric_limits<DType>::infinity(), 0};\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n logits_vec.fill(-cuda::std::numeric_limits<DType>::infinity());\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.cast_load(logits + row_idx * d + i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n\n vec_t<DType, VEC_SIZE> gumbel_noise = GenerateGumbelNoise<DType, VEC_SIZE>(\n philox_seed, philox_offset,\n static_cast<uint64_t>(bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE));\n DataAndIndex<DType, IdType> cur_data[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n cur_data[j].data = (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d\n ? logits_vec[j] + gumbel_noise[j]\n : -cuda::std::numeric_limits<DType>::infinity();\n cur_data[j].index = (i * BLOCK_THREADS + tx) * VEC_SIZE + j;\n }\n\n max_data +=\n BlockReduce<DataAndIndex<DType, IdType>, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage)\n .template Sum<VEC_SIZE>(cur_data);\n }\n if (tx == 0) {\n output[bx] = max_data.index;\n }\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void SamplingFromProbKernel(DType* probs, IdType* output, IdType* indices, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val, uint64_t* offset_arr,\n uint64_t offset_val) {\n curandStatePhilox4_32_10_t state;\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n temp_storage.sampled_id = d;\n __syncthreads();\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate(0);\n float u = curand_uniform(&state);\n\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [](float x) { return x > 0; }, u, probs_vec, aggregate, &temp_storage);\n if (float(aggregate) > u) {\n break;\n }\n }\n int sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n output[bx] = sampled_id;\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void TopKSamplingFromProbKernel(DType* probs, IdType* output, IdType* indices,\n IdType* top_k_arr, uint32_t top_k_val, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t batch_size = gridDim.x;\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curandStatePhilox4_32_10_t state;\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t k = top_k_arr == nullptr ? top_k_val : top_k_arr[bx];\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate;\n float q = 1;\n double low = 0, high = 1.f;\n int sampled_id;\n int round = 0;\n do {\n round += 1;\n temp_storage.sampled_id = d;\n __syncthreads();\n float u = curand_uniform(&state) * q;\n aggregate = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x > low; }, u, probs_vec, aggregate, &temp_storage);\n if (aggregate > u) {\n break;\n }\n }\n __syncthreads();\n sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n double pivot_0 = probs[row_idx * d + sampled_id];\n double pivot_1 = (pivot_0 + high) / 2;\n\n ValueCount<float> aggregate_gt_pivot_0{0, 0}, aggregate_gt_pivot_1{0, 0};\n ValueCount<float> threadlocal_gt_pivot_0{0, 0}, threadlocal_gt_pivot_1{0, 0};\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n ValueCount<float> probs_gt_pivot_0[VEC_SIZE], probs_gt_pivot_1[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot_0[j] = {\n (probs_vec[j] > pivot_0) ? probs_vec[j] : 0,\n (probs_vec[j] > pivot_0 && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d)};\n probs_gt_pivot_1[j] = {\n (probs_vec[j] > pivot_1) ? probs_vec[j] : 0,\n (probs_vec[j] > pivot_1 && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d)};\n threadlocal_gt_pivot_0 += probs_gt_pivot_0[j];\n threadlocal_gt_pivot_1 += probs_gt_pivot_1[j];\n }\n }\n aggregate_gt_pivot_0 += BlockReduce<ValueCount<float>, BLOCK_THREADS, REDUCE_ALGORITHM>(\n temp_storage.block_prim.reduce_value_count)\n .Sum(threadlocal_gt_pivot_0);\n if (tx == 0) {\n temp_storage.block_aggregate.pair = aggregate_gt_pivot_0;\n }\n __syncthreads();\n aggregate_gt_pivot_0 = temp_storage.block_aggregate.pair;\n\n aggregate_gt_pivot_1 += BlockReduce<ValueCount<float>, BLOCK_THREADS, REDUCE_ALGORITHM>(\n temp_storage.block_prim.reduce_value_count)\n .Sum(threadlocal_gt_pivot_1);\n if (tx == 0) {\n temp_storage.block_aggregate.pair = aggregate_gt_pivot_1;\n }\n __syncthreads();\n aggregate_gt_pivot_1 = temp_storage.block_aggregate.pair;\n if (aggregate_gt_pivot_0.count < k) {\n // case 1: pivot_0 accepted\n break;\n }\n if (aggregate_gt_pivot_1.count < k) {\n // case 2: pivot_0 rejected, pivot_1 accepted\n low = pivot_0;\n high = pivot_1;\n q = aggregate_gt_pivot_0.value;\n } else {\n // case 3: pivot_0 rejected, pivot_1 rejected\n low = pivot_1;\n q = aggregate_gt_pivot_1.value;\n }\n } while (low < high);\n __syncthreads();\n if (tx == 0) {\n output[bx] = sampled_id;\n }\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void TopPSamplingFromProbKernel(DType* probs, IdType* output, IdType* indices,\n float* top_p_arr, float top_p_val, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t batch_size = gridDim.x;\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curandStatePhilox4_32_10_t state;\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n float top_p = (top_p_arr == nullptr) ? top_p_val : top_p_arr[row_idx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate;\n float q = 1;\n double low = 0, high = 1.f;\n int sampled_id;\n do {\n temp_storage.sampled_id = d;\n __syncthreads();\n float u = curand_uniform(&state) * q;\n aggregate = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x > low; }, u, probs_vec, aggregate, &temp_storage);\n if (aggregate > u) {\n break;\n }\n }\n __syncthreads();\n sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n double pivot_0 = probs[row_idx * d + sampled_id];\n double pivot_1 = (pivot_0 + high) / 2;\n\n float aggregate_gt_pivot_0 = 0, aggregate_gt_pivot_1 = 0;\n float threadlocal_aggregate_gt_pivot_0 = 0;\n float threadlocal_aggregate_gt_pivot_1 = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n float probs_gt_pivot_0[VEC_SIZE], probs_gt_pivot_1[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot_0[j] = (probs_vec[j] > pivot_0) ? probs_vec[j] : 0;\n probs_gt_pivot_1[j] = (probs_vec[j] > pivot_1) ? probs_vec[j] : 0;\n threadlocal_aggregate_gt_pivot_0 += probs_gt_pivot_0[j];\n threadlocal_aggregate_gt_pivot_1 += probs_gt_pivot_1[j];\n }\n }\n aggregate_gt_pivot_0 += BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot_0);\n if (tx == 0) {\n temp_storage.block_aggregate.value = aggregate_gt_pivot_0;\n }\n __syncthreads();\n aggregate_gt_pivot_0 = temp_storage.block_aggregate.value;\n\n aggregate_gt_pivot_1 += BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot_1);\n if (tx == 0) {\n temp_storage.block_aggregate.value = aggregate_gt_pivot_1;\n }\n __syncthreads();\n aggregate_gt_pivot_1 = temp_storage.block_aggregate.value;\n\n if (aggregate_gt_pivot_0 < top_p) {\n // case 1: pivot_0 accepted\n break;\n }\n if (aggregate_gt_pivot_1 < top_p) {\n // case 2: pivot_0 rejected, pivot_1 accepted\n low = pivot_0;\n high = pivot_1;\n q = aggregate_gt_pivot_0;\n } else {\n // case 3: pivot_0 rejected, pivot_1 rejected\n low = pivot_1;\n q = aggregate_gt_pivot_1;\n }\n } while (low < high);\n __syncthreads();\n if (tx == 0) {\n output[bx] = sampled_id;\n }\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void MinPSamplingFromProbKernel(DType* probs, float* min_p_arr, IdType* output,\n IdType* indices, float min_p_val, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n float p = (min_p_arr == nullptr) ? min_p_val : min_p_arr[bx];\n curandStatePhilox4_32_10_t state;\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n float max_val = GetMaxValue<VEC_SIZE, BLOCK_THREADS, REDUCE_ALGORITHM,\n SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>>(\n probs, row_idx, d, temp_storage);\n float pivot = max_val * p;\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate_gt_pivot = 0;\n float threadlocal_aggregate_gt_pivot = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n float probs_gt_pivot[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot[j] = (probs_vec[j] >= pivot) ? probs_vec[j] : 0;\n threadlocal_aggregate_gt_pivot += probs_gt_pivot[j];\n }\n }\n\n aggregate_gt_pivot += BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot);\n if (tx == 0) {\n temp_storage.block_aggregate.value = aggregate_gt_pivot;\n }\n __syncthreads();\n\n float aggregate = 0;\n float q = temp_storage.block_aggregate.value;\n\n int sampled_id;\n temp_storage.sampled_id = d;\n __syncthreads();\n float u = curand_uniform(&state) * q;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x >= pivot; }, u, probs_vec, aggregate, &temp_storage);\n if (aggregate > u) {\n break;\n }\n }\n sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n output[bx] = sampled_id;\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void TopKTopPSamplingFromProbKernel(DType* probs, IdType* top_k_arr, float* top_p_arr,\n IdType* output, IdType* indices, IdType top_k_val,\n float top_p_val, uint32_t d, uint64_t* seed_arr,\n uint64_t seed_val, uint64_t* offset_arr,\n uint64_t offset_val) {\n const uint32_t batch_size = gridDim.x;\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curandStatePhilox4_32_10_t state;\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n const uint32_t k = top_k_arr == nullptr ? top_k_val : top_k_arr[row_idx];\n const float p = top_p_arr == nullptr ? top_p_val : top_p_arr[row_idx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate;\n float q = 1;\n double low = 0, high = 1.f;\n int sampled_id;\n do {\n temp_storage.sampled_id = d;\n __syncthreads();\n float u = curand_uniform(&state) * q;\n aggregate = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x > low; }, u, probs_vec, aggregate, &temp_storage);\n if (aggregate > u) {\n break;\n }\n }\n __syncthreads();\n sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n double pivot_0 = probs[row_idx * d + sampled_id];\n double pivot_1 = (pivot_0 + high) / 2;\n\n ValueCount<float> aggregate_gt_pivot_0{0, 0}, aggregate_gt_pivot_1{0, 0};\n ValueCount<float> threadlocal_aggregate_gt_pivot_0{0, 0};\n ValueCount<float> threadlocal_aggregate_gt_pivot_1{0, 0};\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n ValueCount<float> probs_gt_pivot_0[VEC_SIZE], probs_gt_pivot_1[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot_0[j] = {\n (probs_vec[j] > pivot_0) ? probs_vec[j] : 0,\n (probs_vec[j] > pivot_0 && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d)};\n probs_gt_pivot_1[j] = {\n (probs_vec[j] > pivot_1) ? probs_vec[j] : 0,\n (probs_vec[j] > pivot_1 && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d)};\n threadlocal_aggregate_gt_pivot_0 += probs_gt_pivot_0[j];\n threadlocal_aggregate_gt_pivot_1 += probs_gt_pivot_1[j];\n }\n }\n aggregate_gt_pivot_0 +=\n BlockReduce<ValueCount<float>, BLOCK_THREADS>(temp_storage.block_prim.reduce_value_count)\n .Sum(threadlocal_aggregate_gt_pivot_0);\n if (tx == 0) {\n temp_storage.block_aggregate.pair = aggregate_gt_pivot_0;\n }\n __syncthreads();\n aggregate_gt_pivot_0 = temp_storage.block_aggregate.pair;\n\n aggregate_gt_pivot_1 +=\n BlockReduce<ValueCount<float>, BLOCK_THREADS>(temp_storage.block_prim.reduce_value_count)\n .Sum(threadlocal_aggregate_gt_pivot_1);\n if (tx == 0) {\n temp_storage.block_aggregate.pair = aggregate_gt_pivot_1;\n }\n __syncthreads();\n aggregate_gt_pivot_1 = temp_storage.block_aggregate.pair;\n if (aggregate_gt_pivot_0.count < k && aggregate_gt_pivot_0.value < p) {\n // case 1: pivot_0 accepted\n break;\n }\n if (aggregate_gt_pivot_1.count < k && aggregate_gt_pivot_1.value < p) {\n // case 2: pivot_0 rejected, pivot_1 accepted\n low = pivot_0;\n high = pivot_1;\n q = aggregate_gt_pivot_0.value;\n } else {\n // case 3: pivot_0 rejected, pivot_1 rejected\n low = pivot_1;\n q = aggregate_gt_pivot_1.value;\n }\n } while (low < high);\n __syncthreads();\n if (tx == 0) {\n output[bx] = sampled_id;\n }\n}\n\ntemplate <typename DType>\ncudaError_t OnlineSoftmax(DType* logits, DType* output, uint32_t batch_size, uint32_t d,\n DType* temperature_arr, DType temperature_val, void* workspace_buffer,\n size_t workspace_buffer_size_in_bytes, bool enable_pdl,\n cudaStream_t stream = 0) {\n constexpr uint32_t SMALL_BATCH_THRESHOLD = 128;\n constexpr uint32_t LARGE_VOCAB_THRESHOLD = 24576;\n constexpr uint32_t DEFAULT_SLICE_SIZE = 8192;\n\n const uint32_t vec_size = std::gcd(16 / sizeof(DType), d);\n auto compute_capacity = GetCudaComputeCapability();\n\n DISPATCH_COMPUTE_CAP_NUM_THREADS(\n compute_capacity, BLOCK_THREADS, {DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n if (batch_size <= SMALL_BATCH_THRESHOLD && d >= LARGE_VOCAB_THRESHOLD) {\n // Path A: Vocab-Splitting Strategy for small-batch & large-vocab\n uint32_t num_slices = ceil_div(d, DEFAULT_SLICE_SIZE);\n\n const size_t partial_buffer_size = batch_size * num_slices * sizeof(PartialSoftmaxResult);\n if (workspace_buffer_size_in_bytes < partial_buffer_size) {\n return cudaErrorInvalidValue;\n }\n\n AlignedAllocator allocator(workspace_buffer, workspace_buffer_size_in_bytes);\n auto partial_results = allocator.aligned_alloc<PartialSoftmaxResult>(\n partial_buffer_size, alignof(PartialSoftmaxResult), \"softmax_workspace\");\n\n // Phase 1: Map-Reduce across vocab slices\n dim3 phase1_nblks(batch_size, num_slices);\n dim3 phase1_nthrs(BLOCK_THREADS);\n size_t smem_size = sizeof(OnlineSoftmaxTempStorage<BLOCK_THREADS>);\n\n auto phase1_kernel = OnlineSoftmaxMapKernel<BLOCK_THREADS, VEC_SIZE, DType>;\n void* phase1_args[] = {&logits, &partial_results, &temperature_arr, &temperature_val,\n &d, &num_slices};\n\n FLASHINFER_CUDA_CALL(cudaFuncSetAttribute(\n phase1_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n if (enable_pdl) {\n cudaLaunchAttribute attribute[1];\n attribute[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attribute[0].val.programmaticStreamSerializationAllowed = 1;\n\n cudaLaunchConfig_t config;\n config.gridDim = phase1_nblks;\n config.blockDim = phase1_nthrs;\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attribute;\n config.numAttrs = 1;\n\n FLASHINFER_CUDA_CALL(cudaLaunchKernelEx(&config, phase1_kernel, logits, partial_results,\n temperature_arr, temperature_val, d,\n num_slices));\n } else {\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)phase1_kernel, phase1_nblks, phase1_nthrs,\n phase1_args, smem_size, stream));\n }\n\n // Phase 2: Final reduction and apply normalization\n dim3 phase2_nblks(batch_size);\n dim3 phase2_nthrs(BLOCK_THREADS);\n\n auto phase2_kernel = OnlineSoftmaxReduceKernel<BLOCK_THREADS, VEC_SIZE, DType>;\n void* phase2_args[] = {&logits, &output, &partial_results, &temperature_arr,\n &temperature_val, &d, &num_slices};\n\n FLASHINFER_CUDA_CALL(cudaFuncSetAttribute(\n phase2_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n if (enable_pdl) {\n cudaLaunchAttribute attribute[1];\n attribute[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attribute[0].val.programmaticStreamSerializationAllowed = 1;\n\n cudaLaunchConfig_t config;\n config.gridDim = phase2_nblks;\n config.blockDim = phase2_nthrs;\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attribute;\n config.numAttrs = 1;\n\n FLASHINFER_CUDA_CALL(cudaLaunchKernelEx(&config, phase2_kernel, logits, output,\n partial_results, temperature_arr,\n temperature_val, d, num_slices));\n } else {\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)phase2_kernel, phase2_nblks, phase2_nthrs,\n phase2_args, smem_size, stream));\n }\n } else {\n // Path B: Single-Block Strategy\n // Switch input cache\n uint32_t cache_threshold;\n if (batch_size <= 16) {\n cache_threshold = 4096;\n } else if (batch_size <= 32) {\n cache_threshold = 2048;\n } else {\n cache_threshold = 0;\n }\n const bool cache_input = d <= cache_threshold;\n\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&logits, &output, &temperature_arr, &temperature_val, &d};\n\n const size_t smem_logits_bytes = (round_up(d, VEC_SIZE) + VEC_SIZE) * sizeof(DType);\n\n uint32_t smem_size = sizeof(OnlineSoftmaxTempStorage<BLOCK_THREADS>) +\n (cache_input ? smem_logits_bytes : 0);\n\n DISPATCH_SOFTMAX_CACHE_INPUT(cache_input, CACHE_INPUT, {\n auto kernel = OnlineSoftmaxFusedKernel<BLOCK_THREADS, VEC_SIZE, DType, CACHE_INPUT>;\n FLASHINFER_CUDA_CALL(cudaFuncSetAttribute(\n kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n if (enable_pdl) {\n cudaLaunchAttribute attribute[1];\n attribute[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attribute[0].val.programmaticStreamSerializationAllowed = 1;\n\n cudaLaunchConfig_t config;\n config.gridDim = nblks;\n config.blockDim = nthrs;\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attribute;\n config.numAttrs = 1;\n\n FLASHINFER_CUDA_CALL(cudaLaunchKernelEx(&config, kernel, logits, output,\n temperature_arr, temperature_val, d));\n } else {\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n }\n });\n }\n })});\n return cudaSuccess;\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t SamplingFromLogits(T* logits, IdType* output, IdType* indices, uint32_t batch_size,\n uint32_t d, bool deterministic, uint64_t* seed_arr,\n uint64_t seed_val, uint64_t* offset_arr, uint64_t offset_val,\n cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&logits, &output, &indices, &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n const uint32_t smem_size = sizeof(\n typename BlockReduce<DataAndIndex<T, IdType>, BLOCK_THREADS, REDUCE_ALGO>::TempStorage);\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = SamplingFromLogitsKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t SamplingFromProb(T* probs, IdType* output, IdType* indices, uint32_t batch_size,\n uint32_t d, bool deterministic, uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &output, &indices, &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = SamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t TopKSamplingFromProb(T* probs, IdType* output, IdType* indices, T* top_k_arr,\n uint32_t batch_size, uint32_t top_k_val, uint32_t d,\n bool deterministic, uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val,\n cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &output, &indices, &top_k_arr, &top_k_val,\n &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = TopKSamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t TopPSamplingFromProb(T* probs, IdType* output, IdType* indices, T* top_p_arr,\n uint32_t batch_size, T top_p_val, uint32_t d, bool deterministic,\n uint64_t* seed_arr, uint64_t seed_val, uint64_t* offset_arr,\n uint64_t offset_val, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &output, &indices, &top_p_arr, &top_p_val,\n &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = TopPSamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t MinPSamplingFromProb(T* probs, T* min_p_arr, IdType* output, IdType* indices,\n uint32_t batch_size, float min_p_val, uint32_t d,\n bool deterministic, uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val,\n cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &min_p_arr, &output, &indices, &min_p_val,\n &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = MinPSamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t TopKTopPSamplingFromProb(T* probs, IdType* top_k_arr, T* top_p_arr, IdType* output,\n IdType* indices, uint32_t batch_size, IdType top_k_val,\n T top_p_val, uint32_t d, bool deterministic,\n uint64_t* seed_arr, uint64_t seed_val, uint64_t* offset_arr,\n uint64_t offset_val, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &top_k_arr, &top_p_arr, &output, &indices, &top_k_val,\n &top_p_val, &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = TopKTopPSamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO,\n VEC_SIZE, DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockReduceAlgorithm REDUCE_ALGORITHM>\nstruct RenormTempStorage {\n union {\n typename BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage reduce;\n typename BlockReduce<int, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage reduce_int;\n typename BlockReduce<ValueCount<float>, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage\n reduce_value_count;\n } block_prim;\n struct {\n float max_val;\n float min_val;\n float row_sum;\n union {\n struct {\n float values[2];\n };\n struct {\n int counts[2];\n };\n struct {\n ValueCount<float> pairs[2];\n };\n } block_aggregate;\n };\n};\n\ntemplate <uint32_t BLOCK_THREADS, BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE,\n typename DType>\n__global__ void TopPRenormProbKernel(DType* probs, DType* renormed_prob, float* top_p_arr,\n float top_p_val, uint32_t d) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n const uint32_t row_idx = bx;\n float p = top_p_arr == nullptr ? top_p_val : top_p_arr[bx];\n\n extern __shared__ __align__(alignof(RenormTempStorage<BLOCK_THREADS, REDUCE_ALGO>))\n uint8_t smem_renorm[];\n auto& temp_storage =\n reinterpret_cast<RenormTempStorage<BLOCK_THREADS, REDUCE_ALGO>&>(smem_renorm);\n vec_t<float, VEC_SIZE> probs_vec;\n\n // Fast-path: when p >= 1.0 (e.g., p == 1.0), perform simple sum and normalization\n if (p >= 1.0f) {\n // Stage A: per-thread float accumulation over assigned lanes (vectorized)\n float thread_sum = 0.0f;\n const uint32_t num_iters = ceil_div(d, BLOCK_THREADS * VEC_SIZE);\n for (uint32_t i = 0; i < num_iters; ++i) {\n probs_vec.fill(0.0f);\n const uint32_t base_idx = (i * BLOCK_THREADS + tx) * VEC_SIZE;\n if (base_idx < d) {\n probs_vec.cast_load(probs + row_idx * d + base_idx);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n const uint32_t idx = base_idx + j;\n if (idx < d) thread_sum += probs_vec[j];\n }\n }\n\n // Block reduce (float)\n float row_sum =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Sum(thread_sum);\n // Broadcast via shared\n if (tx == 0) temp_storage.row_sum = row_sum;\n __syncthreads();\n row_sum = temp_storage.row_sum;\n\n // Guard against zero sum\n const float denom = (row_sum <= 1e-8f) ? 1.0f : row_sum;\n const float normalizer = math::ptx_rcp(denom);\n\n // Stage B: normalize and store\n for (uint32_t i = 0; i < num_iters; ++i) {\n probs_vec.fill(0.0f);\n const uint32_t base_idx = (i * BLOCK_THREADS + tx) * VEC_SIZE;\n if (base_idx < d) {\n probs_vec.cast_load(probs + row_idx * d + base_idx);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n const uint32_t idx = base_idx + j;\n float v = probs_vec[j];\n probs_vec[j] = (idx < d) ? (v * normalizer) : 0.0f;\n }\n if (base_idx < d) {\n probs_vec.cast_store(renormed_prob + row_idx * d + base_idx);\n }\n }\n return; // Exit after fast-path processing\n }\n\n // Original Top-P renormalization logic\n temp_storage.max_val = 0;\n float max_val = GetMaxValue<VEC_SIZE, BLOCK_THREADS, REDUCE_ALGORITHM,\n RenormTempStorage<BLOCK_THREADS, REDUCE_ALGORITHM>>(probs, row_idx, d,\n temp_storage);\n\n double low = 0, high = max_val;\n float min_gt_low, max_le_high;\n float sum_low = 1;\n // f(x) = sum(probs[probs > x]), f(x) is non-increasing\n // min_gt_low = min{p \\in probs | p > low}, max_le_high = max{p \\in probs | p <= high}\n // loop invariant:\n // - f(low) >= p, f(high) < p\n // - f(low) > f(min_gt_low) >= f(max_le_high) == f(high)\n // stopping condition\n // - f(low) >= p, f(min_gt_low) == f(max_le_high) == f(high) < p\n do {\n double pivot_0 = (high + 2 * low) / 3;\n double pivot_1 = (2 * high + low) / 3;\n\n float aggregate_gt_pivot_0 = 0, aggregate_gt_pivot_1 = 0;\n min_gt_low = high;\n max_le_high = low;\n float threadlocal_aggregate_gt_pivot_0 = 0;\n float threadlocal_aggregate_gt_pivot_1 = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n\n float probs_gt_pivot_0[VEC_SIZE], probs_gt_pivot_1[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot_0[j] = (probs_vec[j] > pivot_0) ? probs_vec[j] : 0;\n probs_gt_pivot_1[j] = (probs_vec[j] > pivot_1) ? probs_vec[j] : 0;\n\n if (probs_vec[j] > low && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d) {\n min_gt_low = min(min_gt_low, probs_vec[j]);\n }\n if (probs_vec[j] <= high && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d) {\n max_le_high = max(max_le_high, probs_vec[j]);\n }\n threadlocal_aggregate_gt_pivot_0 += probs_gt_pivot_0[j];\n threadlocal_aggregate_gt_pivot_1 += probs_gt_pivot_1[j];\n }\n }\n aggregate_gt_pivot_0 =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot_0);\n __syncthreads();\n aggregate_gt_pivot_1 =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot_1);\n __syncthreads();\n\n min_gt_low = BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Reduce(min_gt_low, MinReduceOp{});\n __syncthreads();\n max_le_high =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Reduce(max_le_high, MaxReduceOp{});\n if (tx == 0) {\n temp_storage.block_aggregate.values[0] = aggregate_gt_pivot_0;\n temp_storage.block_aggregate.values[1] = aggregate_gt_pivot_1;\n temp_storage.min_val = min_gt_low;\n temp_storage.max_val = max_le_high;\n }\n __syncthreads();\n aggregate_gt_pivot_0 = temp_storage.block_aggregate.values[0];\n aggregate_gt_pivot_1 = temp_storage.block_aggregate.values[1];\n min_gt_low = temp_storage.min_val;\n max_le_high = temp_storage.max_val;\n\n if (aggregate_gt_pivot_1 >= p) {\n low = pivot_1;\n sum_low = aggregate_gt_pivot_1;\n } else if (aggregate_gt_pivot_0 >= p) {\n low = pivot_0;\n high = min(pivot_1, max_le_high);\n sum_low = aggregate_gt_pivot_0;\n } else {\n high = min(pivot_0, max_le_high);\n }\n } while (min_gt_low != max_le_high);\n\n float normalizer = math::ptx_rcp(max(sum_low, 1e-8));\n\n // normalize\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_vec[j] = (probs_vec[j] > low) ? probs_vec[j] * normalizer : 0;\n }\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_store(renormed_prob + row_idx * d + i * BLOCK_THREADS * VEC_SIZE +\n tx * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename DType>\ncudaError_t TopPRenormProb(DType* probs, DType* renormed_prob, float* top_p_arr,\n uint32_t batch_size, float top_p_val, uint32_t d,\n cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(DType), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(RenormTempStorage<BLOCK_THREADS, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &renormed_prob, &top_p_arr, &top_p_val, &d};\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = TopPRenormProbKernel<BLOCK_THREADS, REDUCE_ALGO, VEC_SIZE, DType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n return cudaSuccess;\n });\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void ChainSpeculativeSampling(DType* draft_probs, IdType* draft_token_ids,\n DType* target_probs, IdType* output_token_ids,\n IdType* output_accepted_token_num,\n IdType* output_emitted_draft_token_num,\n uint32_t num_speculative_tokens, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n const uint32_t row_idx = bx;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curandStatePhilox4_32_10_t curand_state;\n curand_init(philox_seed, bx, philox_offset, &curand_state);\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n uint32_t pos = num_speculative_tokens;\n for (uint32_t i = 0; i < num_speculative_tokens; ++i) {\n IdType draft_id = draft_token_ids[row_idx * num_speculative_tokens + i];\n float q = target_probs[(row_idx * (num_speculative_tokens + 1) + i) * d + draft_id],\n p = draft_probs[(row_idx * num_speculative_tokens + i) * d + draft_id];\n float u = curand_uniform(&curand_state);\n if (u * p < q) {\n // accept the draft models output\n output_token_ids[row_idx * (num_speculative_tokens + 1) + i] = draft_id;\n } else {\n pos = i;\n break;\n }\n }\n\n uint32_t emitted_token_num = pos;\n uint32_t accepted_token_num = pos;\n for (uint32_t i = pos; i < num_speculative_tokens; ++i) {\n int draft_id = draft_token_ids[row_idx * num_speculative_tokens + i];\n float q = target_probs[(row_idx * (num_speculative_tokens + 1) + i) * d + draft_id],\n p = draft_probs[(row_idx * num_speculative_tokens + i) * d + draft_id];\n float u = curand_uniform(&curand_state);\n if (u * p < q) {\n ++accepted_token_num;\n }\n }\n\n if (tx == 0) {\n output_accepted_token_num[row_idx] += accepted_token_num;\n output_emitted_draft_token_num[row_idx] += emitted_token_num;\n }\n\n // sample from relu(target_probs - draft_probs)\n float sum_relu_q_minus_p = 0;\n vec_t<float, VEC_SIZE> q_vec, p_vec;\n float relu_q_minus_p[VEC_SIZE];\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n q_vec.fill(0);\n p_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n q_vec.cast_load(target_probs + (row_idx * (num_speculative_tokens + 1) + pos) * d +\n i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n if (pos != num_speculative_tokens) {\n // there is no draft_probs for the bonus token\n p_vec.cast_load(draft_probs + (row_idx * num_speculative_tokens + pos) * d +\n i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n relu_q_minus_p[j] = max(q_vec[j] - p_vec[j], 0.0f);\n }\n sum_relu_q_minus_p +=\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Sum<VEC_SIZE>(relu_q_minus_p);\n __syncthreads();\n }\n if (tx == 0) {\n temp_storage.block_aggregate.value = sum_relu_q_minus_p;\n }\n // init the first rejected token to d\n temp_storage.sampled_id = d;\n __syncthreads();\n sum_relu_q_minus_p = temp_storage.block_aggregate.value;\n float u = curand_uniform(&curand_state) * sum_relu_q_minus_p;\n\n float aggregate_relu_q_minus_p(0);\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n q_vec.fill(0);\n p_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n q_vec.cast_load(target_probs + (row_idx * (num_speculative_tokens + 1) + pos) * d +\n i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n if (pos != num_speculative_tokens) {\n // there is no draft_probs for the bonus token\n p_vec.cast_load(draft_probs + (row_idx * num_speculative_tokens + pos) * d +\n i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n }\n\n vec_t<float, VEC_SIZE> relu_q_minus_p_vec;\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n relu_q_minus_p_vec[j] = max(q_vec[j] - p_vec[j], 0.0f);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x > 0; }, u, relu_q_minus_p_vec, aggregate_relu_q_minus_p,\n &temp_storage);\n if (aggregate_relu_q_minus_p > u) {\n break;\n }\n }\n __syncthreads();\n int sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n // set the first rejected token\n output_token_ids[row_idx * (num_speculative_tokens + 1) + pos] = sampled_id;\n // move to the next token\n pos++;\n\n // pad remaining tokens with -1\n for (; pos < num_speculative_tokens + 1; ++pos) {\n output_token_ids[row_idx * (num_speculative_tokens + 1) + pos] = -1;\n }\n}\n\ntemplate <typename DType, typename IdType>\ncudaError_t ChainSpeculativeSampling(\n DType* draft_probs, IdType* draft_token_ids, DType* target_probs, IdType* output_token_ids,\n IdType* output_accepted_token_num, IdType* output_emitted_draft_token_num, uint32_t batch_size,\n uint32_t num_speculative_tokens, uint32_t d, bool deterministic, uint64_t* seed_arr,\n uint64_t seed_val, uint64_t* offset_arr, uint64_t offset_val, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(DType), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&draft_probs,\n &draft_token_ids,\n &target_probs,\n &output_token_ids,\n &output_accepted_token_num,\n &output_emitted_draft_token_num,\n &num_speculative_tokens,\n &d,\n &seed_arr,\n &seed_val,\n &offset_arr,\n &offset_val};\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = ChainSpeculativeSampling<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, DType, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\n} // namespace sampling\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_SAMPLING_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_SAMPLING_CUH_\n#define FLASHINFER_SAMPLING_CUH_\n\n#include <cuda.h>\n#include <curand.h>\n#include <curand_kernel.h>\n#include <curand_philox4x32_x.h>\n\n#include <cstdlib>\n#include <cstring>\n#include <cub/cub.cuh>\n#include <cuda/functional>\n#include <cuda/std/functional>\n#include <cuda/std/limits>\n#include <limits>\n#include <numeric>\n#include <tuple>\n\n#include \"allocator.h\"\n#include \"math.cuh\"\n#include \"topk.cuh\"\n#include \"utils.cuh\"\n#include \"vec_dtypes.cuh\"\n\n// Define reduction operators based on CUDA version\n// CUDA 13 (12.9+) deprecated cub::Max/Min in favor of cuda::maximum/minimum\n#if CUDA_VERSION >= 12090\nusing MaxReduceOp = cuda::maximum<>;\nusing MinReduceOp = cuda::minimum<>;\n#else\nusing MaxReduceOp = cub::Max;\nusing MinReduceOp = cub::Min;\n#endif\n\nnamespace flashinfer {\n\nnamespace sampling {\n\nusing namespace cub;\n\n#define DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, ...) \\\n if (deterministic) { \\\n constexpr bool DETERMINISTIC = true; \\\n __VA_ARGS__ \\\n } else { \\\n constexpr bool DETERMINISTIC = false; \\\n __VA_ARGS__ \\\n }\n\n#define DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, ...) \\\n if (compute_capacity.first >= 8) { \\\n constexpr uint32_t BLOCK_THREADS = 1024; \\\n __VA_ARGS__ \\\n } else { \\\n constexpr uint32_t BLOCK_THREADS = 512; \\\n __VA_ARGS__ \\\n }\n\n#define DISPATCH_SOFTMAX_CACHE_INPUT(cache_input, CACHE_INPUT, ...) \\\n if (cache_input) { \\\n constexpr bool CACHE_INPUT = true; \\\n __VA_ARGS__ \\\n } else { \\\n constexpr bool CACHE_INPUT = false; \\\n __VA_ARGS__ \\\n }\n\nconstexpr BlockScanAlgorithm SCAN_ALGO = BLOCK_SCAN_WARP_SCANS;\nconstexpr BlockReduceAlgorithm REDUCE_ALGO = BLOCK_REDUCE_WARP_REDUCTIONS;\n\n#if (__CUDACC_VER_MAJOR__ * 10000 + __CUDACC_VER_MINOR__ * 100 >= 120100)\n#define FLASHINFER_CUB_SUBTRACTLEFT_DEFINED\n#endif\n\ntemplate <typename T>\nstruct ValueCount {\n T value;\n int count;\n\n __device__ ValueCount operator+(const ValueCount& other) const {\n return {value + other.value, count + other.count};\n }\n __device__ ValueCount& operator+=(const ValueCount& other) {\n value += other.value;\n count += other.count;\n return *this;\n }\n};\n\nstruct BoolDiffOp {\n __device__ __forceinline__ bool operator()(const bool& lhs, const bool& rhs) const {\n return lhs != rhs;\n }\n};\n\nstruct Float2SoftmaxReduceOp {\n __device__ __forceinline__ float2 operator()(const float2& a, const float2& b) const {\n if (isinf(a.x)) return b;\n if (isinf(b.x)) return a;\n\n float new_max = max(a.x, b.x);\n float new_denom = a.y * __expf(a.x - new_max) + b.y * __expf(b.x - new_max);\n return make_float2(new_max, new_denom);\n }\n};\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM>\nstruct SamplingTempStorage {\n union {\n float deterministic_scan[BLOCK_THREADS / 32];\n typename BlockScan<float, BLOCK_THREADS, SCAN_ALGORITHM>::TempStorage scan;\n typename BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage reduce;\n typename BlockReduce<int, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage reduce_int;\n typename BlockReduce<ValueCount<float>, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage\n reduce_value_count;\n typename BlockAdjacentDifference<bool, BLOCK_THREADS>::TempStorage adj_diff;\n } block_prim;\n struct {\n int32_t sampled_id;\n int32_t last_valid_id;\n float max_val;\n union {\n float value;\n ValueCount<float> pair;\n } block_aggregate;\n };\n};\n\ntemplate <uint32_t BLOCK_THREADS>\nstruct OnlineSoftmaxTempStorage {\n union {\n typename cub::BlockReduce<float, BLOCK_THREADS>::TempStorage reduce;\n typename cub::BlockReduce<float2, BLOCK_THREADS>::TempStorage reduce_pair;\n } block_prim;\n\n struct {\n float max_val;\n float denominator;\n } shared_state;\n};\n\nstruct PartialSoftmaxResult {\n float max_val;\n float denominator;\n};\n\n/*!\n * \\brief Deterministic inclusive scan implementation, use Belloch scan algorithm.\n * \\note This implementation is slower than the cub::BlockScan, but it is deterministic.\n */\ntemplate <uint32_t VEC_SIZE, uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM>\n__device__ __forceinline__ void DeterministicInclusiveSum(\n const float* in_data, float* out_data,\n SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>* temp_storage) {\n float* smem_prefix_sum = temp_storage->block_prim.deterministic_scan;\n float thread_data[VEC_SIZE];\n float thread_sum = 0;\n#pragma unroll\n for (uint32_t i = 0; i < VEC_SIZE; ++i) {\n thread_sum += in_data[i];\n thread_data[i] = thread_sum;\n }\n\n float thread_exclusive_prefix_sum = thread_sum;\n\n#pragma unroll\n for (uint32_t offset = 1; offset < 32; offset *= 2) {\n float tmp = __shfl_up_sync(0xffffffff, thread_exclusive_prefix_sum, offset);\n if ((threadIdx.x + 1) % (offset * 2) == 0) {\n thread_exclusive_prefix_sum += tmp;\n }\n }\n\n float warp_sum = __shfl_sync(0xffffffff, thread_exclusive_prefix_sum, threadIdx.x | 0xffffffff);\n if (threadIdx.x % 32 == 31) {\n thread_exclusive_prefix_sum = 0;\n }\n\n#pragma unroll\n for (uint32_t offset = 16; offset >= 1; offset /= 2) {\n float tmp = __shfl_xor_sync(0xffffffff, thread_exclusive_prefix_sum, offset);\n if ((threadIdx.x + 1) % (offset * 2) == 0) {\n thread_exclusive_prefix_sum = tmp + thread_exclusive_prefix_sum;\n }\n if ((threadIdx.x + 1) % (offset * 2) == offset) {\n thread_exclusive_prefix_sum = tmp;\n }\n }\n\n smem_prefix_sum[threadIdx.x / 32] = warp_sum;\n __syncthreads();\n\n if (threadIdx.x < 32) {\n float warp_exclusive_prefix_sum =\n (threadIdx.x < BLOCK_THREADS / 32) ? smem_prefix_sum[threadIdx.x] : 0;\n\n#pragma unroll\n for (uint32_t offset = 1; offset < 32; offset *= 2) {\n float tmp = __shfl_up_sync(0xffffffff, warp_exclusive_prefix_sum, offset);\n if ((threadIdx.x + 1) % (offset * 2) == 0) {\n warp_exclusive_prefix_sum += tmp;\n }\n }\n\n if (threadIdx.x % 32 == 31) {\n warp_exclusive_prefix_sum = 0;\n }\n\n#pragma unroll\n for (uint32_t offset = 16; offset >= 1; offset /= 2) {\n float tmp = __shfl_xor_sync(0xffffffff, warp_exclusive_prefix_sum, offset);\n if ((threadIdx.x + 1) % (offset * 2) == 0) {\n warp_exclusive_prefix_sum = tmp + warp_exclusive_prefix_sum;\n }\n if ((threadIdx.x + 1) % (offset * 2) == offset) {\n warp_exclusive_prefix_sum = tmp;\n }\n }\n if (threadIdx.x < BLOCK_THREADS / 32) {\n smem_prefix_sum[threadIdx.x] = warp_exclusive_prefix_sum;\n }\n }\n __syncthreads();\n\n#pragma unroll\n for (uint32_t i = 0; i < VEC_SIZE; ++i) {\n out_data[i] = smem_prefix_sum[threadIdx.x / 32] + thread_exclusive_prefix_sum + thread_data[i];\n }\n}\n\ntemplate <uint32_t VEC_SIZE, uint32_t BLOCK_THREADS, BlockReduceAlgorithm REDUCE_ALGORITHM,\n typename TempStorage>\n__device__ __forceinline__ float GetMaxValue(float* in_data, uint32_t row_idx, uint32_t d,\n TempStorage& temp_storage) {\n const uint32_t tx = threadIdx.x;\n vec_t<float, VEC_SIZE> in_data_vec;\n\n // Thread-local max accumulation (deferred reduction)\n float thread_max = 0.0f;\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n in_data_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n in_data_vec.cast_load(in_data + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n thread_max = max(thread_max, static_cast<float>(in_data_vec[j]));\n }\n }\n\n // Single block reduction after loop completes\n float max_val =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Reduce(thread_max, MaxReduceOp{});\n if (tx == 0) {\n temp_storage.max_val = max_val;\n }\n __syncthreads();\n return temp_storage.max_val;\n}\n\ntemplate <uint32_t BLOCK_THREADS, uint32_t VEC_SIZE, typename DType, bool CACHE_INPUT>\n__global__ void OnlineSoftmaxFusedKernel(DType* logits, DType* output, DType* temperature_arr,\n DType temperature_val, uint32_t d) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n float temperature = temperature_arr == nullptr ? temperature_val : temperature_arr[bx];\n const float inv_temp = (temperature == 0.f) ? 0.f : 1.f / temperature;\n\n using TempStorage = OnlineSoftmaxTempStorage<BLOCK_THREADS>;\n extern __shared__ __align__(alignof(TempStorage)) uint8_t smem[];\n auto& temp_storage = reinterpret_cast<TempStorage&>(smem);\n\n DType* smem_vec_base = nullptr;\n if constexpr (CACHE_INPUT) {\n constexpr size_t vec_alignment = alignof(vec_t<DType, VEC_SIZE>);\n size_t aligned_offset = round_up(sizeof(TempStorage), vec_alignment);\n smem_vec_base = reinterpret_cast<DType*>(smem + aligned_offset);\n }\n\n vec_t<DType, VEC_SIZE> logits_vec;\n\n float running_max = -cuda::std::numeric_limits<float>::infinity();\n float running_denominator = 0.0f;\n float threadlocal_running_denominator = 0.0f;\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n // Pass 1: Compute running max and denominator\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n logits_vec.fill(-cuda::std::numeric_limits<DType>::infinity());\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.cast_load(logits + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n logits_vec[j] *= inv_temp;\n }\n\n if constexpr (CACHE_INPUT) {\n logits_vec.store(smem_vec_base + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n }\n\n float thread_max = -cuda::std::numeric_limits<float>::infinity();\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n thread_max = max(thread_max, logits_vec[j]);\n }\n float block_max = cub::BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Reduce(thread_max, MaxReduceOp{});\n\n if (tx == 0) {\n temp_storage.shared_state.max_val = block_max;\n }\n __syncthreads();\n block_max = temp_storage.shared_state.max_val;\n // if block_max is -inf, then this block contains all -inf values, so we can skip updating\n if (!isinf(block_max)) {\n float threadlocal_sum = 0.0f;\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n threadlocal_sum += __expf(logits_vec[j] - block_max);\n }\n float new_max = max(running_max, block_max);\n threadlocal_running_denominator =\n threadlocal_running_denominator * __expf(running_max - new_max) +\n threadlocal_sum * __expf(block_max - new_max);\n running_max = new_max;\n }\n }\n\n running_denominator = cub::BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_running_denominator);\n if (tx == 0) {\n temp_storage.shared_state.denominator = running_denominator;\n }\n __syncthreads();\n running_denominator = temp_storage.shared_state.denominator;\n\n const float final_max = running_max;\n const float inv_denominator = 1.0f / running_denominator;\n\n // Pass 2: Normalize in place\n vec_t<DType, VEC_SIZE> prob_vec;\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n if constexpr (CACHE_INPUT) {\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.load(smem_vec_base + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n } else {\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.cast_load(logits + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n logits_vec[j] *= inv_temp;\n }\n }\n }\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n float p = __expf(static_cast<float>(logits_vec[j]) - final_max) * inv_denominator;\n prob_vec[j] = static_cast<DType>(p);\n }\n\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n prob_vec.cast_store(output + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n }\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\ntemplate <uint32_t BLOCK_THREADS, uint32_t VEC_SIZE, typename DType>\n__global__ void OnlineSoftmaxMapKernel(DType* logits, PartialSoftmaxResult* partial_results,\n DType* temperature_arr, float temperature_val, uint32_t d,\n uint32_t num_slices) {\n const uint32_t bx = blockIdx.x;\n const uint32_t by = blockIdx.y; // slice index\n const uint32_t tx = threadIdx.x;\n float temperature = temperature_arr == nullptr ? temperature_val : temperature_arr[bx];\n const float inv_temp = (temperature == 0.f) ? 0.f : 1.f / temperature;\n\n const uint32_t vec_alignment_elems = alignof(vec_t<DType, VEC_SIZE>) / sizeof(DType);\n const uint32_t slice_stride = round_up(ceil_div(d, num_slices), vec_alignment_elems);\n const uint32_t slice_start = by * slice_stride;\n const uint32_t slice_size = min((by + 1) * slice_stride, d) - slice_start;\n\n if (slice_start >= d) return;\n\n using TempStorage = OnlineSoftmaxTempStorage<BLOCK_THREADS>;\n extern __shared__ __align__(alignof(TempStorage)) uint8_t smem[];\n auto& temp_storage = reinterpret_cast<TempStorage&>(smem);\n\n vec_t<DType, VEC_SIZE> logits_vec;\n float running_max = -cuda::std::numeric_limits<float>::infinity();\n float running_denominator = 0.0f;\n float threadlocal_running_denominator = 0.0f;\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(slice_size, BLOCK_THREADS * VEC_SIZE); ++i) {\n logits_vec.fill(-cuda::std::numeric_limits<DType>::infinity());\n\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < slice_size) {\n logits_vec.cast_load(logits + bx * d + slice_start + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n float thread_max = -cuda::std::numeric_limits<float>::infinity();\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n logits_vec[j] *= inv_temp;\n thread_max = max(thread_max, logits_vec[j]);\n }\n\n float block_max = cub::BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Reduce(thread_max, MaxReduceOp{});\n\n if (tx == 0) {\n temp_storage.shared_state.max_val = block_max;\n }\n __syncthreads();\n block_max = temp_storage.shared_state.max_val;\n\n // if block_max is -inf, then this block contains all -inf values, so we can skip updating\n if (!isinf(block_max)) {\n float threadlocal_sum = 0.0f;\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n threadlocal_sum += __expf(logits_vec[j] - block_max);\n }\n float new_max = max(running_max, block_max);\n threadlocal_running_denominator =\n threadlocal_running_denominator * __expf(running_max - new_max) +\n threadlocal_sum * __expf(block_max - new_max);\n running_max = new_max;\n }\n }\n\n running_denominator = cub::BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_running_denominator);\n if (tx == 0) {\n temp_storage.shared_state.denominator = running_denominator;\n }\n __syncthreads();\n running_denominator = temp_storage.shared_state.denominator;\n\n if (tx == 0) {\n partial_results[bx * num_slices + by] = {running_max, running_denominator};\n }\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\ntemplate <uint32_t BLOCK_THREADS, uint32_t VEC_SIZE, typename DType>\n__global__ void OnlineSoftmaxReduceKernel(DType* logits, DType* output,\n PartialSoftmaxResult* partial_results,\n DType* temperature_arr, float temperature_val, uint32_t d,\n uint32_t num_slices) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x;\n float temperature = temperature_arr == nullptr ? temperature_val : temperature_arr[bx];\n const float inv_temp = (temperature == 0.f) ? 0.f : 1.f / temperature;\n\n // Reduce slice results\n using TempStorage = OnlineSoftmaxTempStorage<BLOCK_THREADS>;\n extern __shared__ __align__(alignof(TempStorage)) uint8_t smem[];\n auto& temp_storage = reinterpret_cast<TempStorage&>(smem);\n\n const Float2SoftmaxReduceOp reduce_op;\n\n float2 thread_aggregate = make_float2(-cuda::std::numeric_limits<float>::infinity(), 0.0f);\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n for (uint32_t i = tx; i < num_slices; i += BLOCK_THREADS) {\n PartialSoftmaxResult partial = partial_results[bx * num_slices + i];\n float2 partial_pair = make_float2(partial.max_val, partial.denominator);\n thread_aggregate = reduce_op(thread_aggregate, partial_pair);\n }\n\n float2 block_result = cub::BlockReduce<float2, BLOCK_THREADS>(temp_storage.block_prim.reduce_pair)\n .Reduce(thread_aggregate, reduce_op);\n\n if (tx == 0) {\n temp_storage.shared_state.max_val = block_result.x;\n temp_storage.shared_state.denominator = block_result.y;\n }\n __syncthreads();\n\n block_result =\n make_float2(temp_storage.shared_state.max_val, temp_storage.shared_state.denominator);\n\n const float final_max = temp_storage.shared_state.max_val;\n const float inv_denominator = 1.0f / temp_storage.shared_state.denominator;\n\n // Apply normalization\n vec_t<DType, VEC_SIZE> logits_vec;\n vec_t<DType, VEC_SIZE> prob_vec;\n\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n logits_vec.fill(-cuda::std::numeric_limits<DType>::infinity());\n\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.cast_load(logits + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n logits_vec[j] *= inv_temp;\n float p = __expf(static_cast<float>(logits_vec[j]) - final_max) * inv_denominator;\n prob_vec[j] = static_cast<DType>(p);\n }\n\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n prob_vec.cast_store(output + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n }\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\ntemplate <uint32_t VEC_SIZE, uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, bool DETERMINISTIC, typename Predicate>\n__device__ __forceinline__ void DeviceSamplingFromProb(\n uint32_t i, uint32_t d, Predicate pred, float u, vec_t<float, VEC_SIZE> prob_vec,\n float& aggregate,\n SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>* temp_storage) {\n const uint32_t tx = threadIdx.x;\n float prob_greater_than_threshold[VEC_SIZE];\n float inclusive_cdf[VEC_SIZE];\n bool greater_than_u[VEC_SIZE], valid[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n prob_greater_than_threshold[j] = pred(prob_vec[j]) ? prob_vec[j] : 0;\n valid[j] = pred(prob_vec[j]) && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d;\n }\n float aggregate_local =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage->block_prim.reduce)\n .template Sum<VEC_SIZE>(prob_greater_than_threshold);\n if (tx == 0) {\n temp_storage->block_aggregate.value = aggregate_local;\n }\n __syncthreads();\n aggregate_local = temp_storage->block_aggregate.value;\n\n if (aggregate + aggregate_local > u) {\n if constexpr (DETERMINISTIC) {\n DeterministicInclusiveSum<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>(\n prob_greater_than_threshold, inclusive_cdf, temp_storage);\n } else {\n BlockScan<float, BLOCK_THREADS, SCAN_ALGORITHM>(temp_storage->block_prim.scan)\n .template InclusiveSum<VEC_SIZE>(prob_greater_than_threshold, inclusive_cdf);\n\n __syncthreads();\n }\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n greater_than_u[j] = (inclusive_cdf[j] + aggregate > u) && valid[j];\n }\n\n bool greater_than_u_diff[VEC_SIZE];\n#ifdef FLASHINFER_CUB_SUBTRACTLEFT_DEFINED\n BlockAdjacentDifference<bool, BLOCK_THREADS>(temp_storage->block_prim.adj_diff)\n .SubtractLeft<VEC_SIZE>(greater_than_u, greater_than_u_diff, BoolDiffOp());\n#else\n BlockAdjacentDifference<bool, BLOCK_THREADS>(temp_storage->block_prim.adj_diff)\n .template FlagHeads<VEC_SIZE>(greater_than_u_diff, greater_than_u, BoolDiffOp(), 0);\n#endif\n __syncthreads();\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n if (greater_than_u_diff[j]) {\n atomicMin(&(temp_storage->sampled_id), (i * BLOCK_THREADS + tx) * VEC_SIZE + j);\n }\n }\n __syncthreads();\n }\n\n // update the last valid index\n int valid_index[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n if (valid[j]) {\n valid_index[j] = (i * BLOCK_THREADS + tx) * VEC_SIZE + j;\n } else {\n valid_index[j] = -1;\n }\n }\n int max_valid_index =\n BlockReduce<int, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage->block_prim.reduce_int)\n .Reduce(valid_index, MaxReduceOp{});\n if (tx == 0 && max_valid_index != -1) {\n temp_storage->last_valid_id = max_valid_index;\n }\n __syncthreads();\n aggregate += aggregate_local;\n}\n\ntemplate <typename DType, typename IdType>\nstruct DataAndIndex {\n DType data;\n IdType index;\n\n __device__ DataAndIndex operator+(const DataAndIndex& other) const {\n if (data > other.data) {\n return {data, index};\n } else {\n return {other.data, other.index};\n }\n }\n __device__ DataAndIndex& operator+=(const DataAndIndex& other) {\n if (data > other.data) {\n return *this;\n } else {\n data = other.data;\n index = other.index;\n return *this;\n }\n }\n};\n\ntemplate <typename DType, uint32_t VEC_SIZE>\n__device__ __forceinline__ vec_t<DType, VEC_SIZE> GenerateGumbelNoise(uint64_t philox_seed,\n uint64_t philox_offset,\n uint64_t subsequence) {\n curandStatePhilox4_32_10_t state;\n vec_t<float, VEC_SIZE> noise;\n constexpr float kSCALE = 1.0f - cuda::std::numeric_limits<float>::epsilon();\n constexpr float kLOG2 = 0.6931471806f;\n auto uniform2gumbel = [](float x) {\n // NB: cuRAND returns strictly positive normal floating point numbers, up to\n // and including 1.0. kSCALE is used to exclude 1.0, s.t.\n // 1.18e-38 <= x * kSCALE <= 1.0f - epsilon\n // => -4.47 <= -log(-log(...)) <= 15.9\n // log2f maps to a single PTX LG2 instruction on NVIDIA GPUs, while logf\n // internally computes log2f * ln(2). Using log2f with a single kLOG2\n // multiplication is more efficient (3 ops vs 4 ops).\n return -kLOG2 * log2f(-log2f((x * kSCALE)));\n };\n#pragma unroll\n for (uint32_t i = 0; i + 4 <= VEC_SIZE; i += 4) {\n curand_init(philox_seed, subsequence + i, philox_offset, &state);\n float4 noise_vec = curand_uniform4(&state);\n noise[i] = uniform2gumbel(noise_vec.x);\n noise[i + 1] = uniform2gumbel(noise_vec.y);\n noise[i + 2] = uniform2gumbel(noise_vec.z);\n noise[i + 3] = uniform2gumbel(noise_vec.w);\n }\n if constexpr (VEC_SIZE % 4 != 0) {\n curand_init(philox_seed, subsequence + VEC_SIZE / 4 * 4, philox_offset, &state);\n float4 noise_vec = curand_uniform4(&state);\n if constexpr (VEC_SIZE % 4 == 1) {\n noise[VEC_SIZE - 1] = uniform2gumbel(noise_vec.x);\n } else if constexpr (VEC_SIZE % 4 == 2) {\n noise[VEC_SIZE - 2] = uniform2gumbel(noise_vec.x);\n noise[VEC_SIZE - 1] = uniform2gumbel(noise_vec.y);\n } else if constexpr (VEC_SIZE % 4 == 3) {\n noise[VEC_SIZE - 3] = uniform2gumbel(noise_vec.x);\n noise[VEC_SIZE - 2] = uniform2gumbel(noise_vec.y);\n noise[VEC_SIZE - 1] = uniform2gumbel(noise_vec.z);\n }\n }\n\n if constexpr (std::is_same_v<DType, float>) {\n return noise;\n } else {\n vec_t<DType, VEC_SIZE> ret;\n#pragma unroll\n for (uint32_t i = 0; i < VEC_SIZE; ++i) {\n ret[i] = static_cast<DType>(noise[i]);\n }\n return ret;\n }\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void SamplingFromLogitsKernel(DType* logits, IdType* output, IdType* indices, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n using SharedMem = typename BlockReduce<DataAndIndex<DType, IdType>, BLOCK_THREADS,\n REDUCE_ALGORITHM>::TempStorage;\n extern __shared__ __align__(alignof(SharedMem)) uint8_t smem_sampling_logit[];\n auto& temp_storage = reinterpret_cast<SharedMem&>(smem_sampling_logit);\n\n vec_t<DType, VEC_SIZE> logits_vec;\n DataAndIndex<DType, IdType> max_data = {-cuda::std::numeric_limits<DType>::infinity(), 0};\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n logits_vec.fill(-cuda::std::numeric_limits<DType>::infinity());\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.cast_load(logits + row_idx * d + i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n\n vec_t<DType, VEC_SIZE> gumbel_noise = GenerateGumbelNoise<DType, VEC_SIZE>(\n philox_seed, philox_offset,\n static_cast<uint64_t>(bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE));\n DataAndIndex<DType, IdType> cur_data[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n cur_data[j].data = (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d\n ? logits_vec[j] + gumbel_noise[j]\n : -cuda::std::numeric_limits<DType>::infinity();\n cur_data[j].index = (i * BLOCK_THREADS + tx) * VEC_SIZE + j;\n }\n\n max_data +=\n BlockReduce<DataAndIndex<DType, IdType>, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage)\n .template Sum<VEC_SIZE>(cur_data);\n }\n if (tx == 0) {\n output[bx] = max_data.index;\n }\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void SamplingFromProbKernel(DType* probs, IdType* output, IdType* indices, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val, uint64_t* offset_arr,\n uint64_t offset_val) {\n curandStatePhilox4_32_10_t state;\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n temp_storage.sampled_id = d;\n __syncthreads();\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate(0);\n float u = curand_uniform(&state);\n\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [](float x) { return x > 0; }, u, probs_vec, aggregate, &temp_storage);\n if (float(aggregate) > u) {\n break;\n }\n }\n int sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n output[bx] = sampled_id;\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void TopKSamplingFromProbKernel(DType* probs, IdType* output, IdType* indices,\n IdType* top_k_arr, uint32_t top_k_val, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t batch_size = gridDim.x;\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curandStatePhilox4_32_10_t state;\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t k = top_k_arr == nullptr ? top_k_val : top_k_arr[bx];\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate;\n float q = 1;\n double low = 0, high = 1.f;\n int sampled_id;\n int round = 0;\n do {\n round += 1;\n temp_storage.sampled_id = d;\n __syncthreads();\n float u = curand_uniform(&state) * q;\n aggregate = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x > low; }, u, probs_vec, aggregate, &temp_storage);\n if (aggregate > u) {\n break;\n }\n }\n __syncthreads();\n sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n double pivot_0 = probs[row_idx * d + sampled_id];\n double pivot_1 = (pivot_0 + high) / 2;\n\n ValueCount<float> aggregate_gt_pivot_0{0, 0}, aggregate_gt_pivot_1{0, 0};\n ValueCount<float> threadlocal_gt_pivot_0{0, 0}, threadlocal_gt_pivot_1{0, 0};\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n ValueCount<float> probs_gt_pivot_0[VEC_SIZE], probs_gt_pivot_1[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot_0[j] = {\n (probs_vec[j] > pivot_0) ? probs_vec[j] : 0,\n (probs_vec[j] > pivot_0 && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d)};\n probs_gt_pivot_1[j] = {\n (probs_vec[j] > pivot_1) ? probs_vec[j] : 0,\n (probs_vec[j] > pivot_1 && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d)};\n threadlocal_gt_pivot_0 += probs_gt_pivot_0[j];\n threadlocal_gt_pivot_1 += probs_gt_pivot_1[j];\n }\n }\n aggregate_gt_pivot_0 += BlockReduce<ValueCount<float>, BLOCK_THREADS, REDUCE_ALGORITHM>(\n temp_storage.block_prim.reduce_value_count)\n .Sum(threadlocal_gt_pivot_0);\n if (tx == 0) {\n temp_storage.block_aggregate.pair = aggregate_gt_pivot_0;\n }\n __syncthreads();\n aggregate_gt_pivot_0 = temp_storage.block_aggregate.pair;\n\n aggregate_gt_pivot_1 += BlockReduce<ValueCount<float>, BLOCK_THREADS, REDUCE_ALGORITHM>(\n temp_storage.block_prim.reduce_value_count)\n .Sum(threadlocal_gt_pivot_1);\n if (tx == 0) {\n temp_storage.block_aggregate.pair = aggregate_gt_pivot_1;\n }\n __syncthreads();\n aggregate_gt_pivot_1 = temp_storage.block_aggregate.pair;\n if (aggregate_gt_pivot_0.count < k) {\n // case 1: pivot_0 accepted\n break;\n }\n if (aggregate_gt_pivot_1.count < k) {\n // case 2: pivot_0 rejected, pivot_1 accepted\n low = pivot_0;\n high = pivot_1;\n q = aggregate_gt_pivot_0.value;\n } else {\n // case 3: pivot_0 rejected, pivot_1 rejected\n low = pivot_1;\n q = aggregate_gt_pivot_1.value;\n }\n } while (low < high);\n __syncthreads();\n if (tx == 0) {\n output[bx] = sampled_id;\n }\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void TopPSamplingFromProbKernel(DType* probs, IdType* output, IdType* indices,\n float* top_p_arr, float top_p_val, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t batch_size = gridDim.x;\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curandStatePhilox4_32_10_t state;\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n float top_p = (top_p_arr == nullptr) ? top_p_val : top_p_arr[row_idx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate;\n float q = 1;\n double low = 0, high = 1.f;\n int sampled_id;\n do {\n temp_storage.sampled_id = d;\n __syncthreads();\n float u = curand_uniform(&state) * q;\n aggregate = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x > low; }, u, probs_vec, aggregate, &temp_storage);\n if (aggregate > u) {\n break;\n }\n }\n __syncthreads();\n sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n double pivot_0 = probs[row_idx * d + sampled_id];\n double pivot_1 = (pivot_0 + high) / 2;\n\n float aggregate_gt_pivot_0 = 0, aggregate_gt_pivot_1 = 0;\n float threadlocal_aggregate_gt_pivot_0 = 0;\n float threadlocal_aggregate_gt_pivot_1 = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n float probs_gt_pivot_0[VEC_SIZE], probs_gt_pivot_1[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot_0[j] = (probs_vec[j] > pivot_0) ? probs_vec[j] : 0;\n probs_gt_pivot_1[j] = (probs_vec[j] > pivot_1) ? probs_vec[j] : 0;\n threadlocal_aggregate_gt_pivot_0 += probs_gt_pivot_0[j];\n threadlocal_aggregate_gt_pivot_1 += probs_gt_pivot_1[j];\n }\n }\n aggregate_gt_pivot_0 += BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot_0);\n if (tx == 0) {\n temp_storage.block_aggregate.value = aggregate_gt_pivot_0;\n }\n __syncthreads();\n aggregate_gt_pivot_0 = temp_storage.block_aggregate.value;\n\n aggregate_gt_pivot_1 += BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot_1);\n if (tx == 0) {\n temp_storage.block_aggregate.value = aggregate_gt_pivot_1;\n }\n __syncthreads();\n aggregate_gt_pivot_1 = temp_storage.block_aggregate.value;\n\n if (aggregate_gt_pivot_0 < top_p) {\n // case 1: pivot_0 accepted\n break;\n }\n if (aggregate_gt_pivot_1 < top_p) {\n // case 2: pivot_0 rejected, pivot_1 accepted\n low = pivot_0;\n high = pivot_1;\n q = aggregate_gt_pivot_0;\n } else {\n // case 3: pivot_0 rejected, pivot_1 rejected\n low = pivot_1;\n q = aggregate_gt_pivot_1;\n }\n } while (low < high);\n __syncthreads();\n if (tx == 0) {\n output[bx] = sampled_id;\n }\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void MinPSamplingFromProbKernel(DType* probs, float* min_p_arr, IdType* output,\n IdType* indices, float min_p_val, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n float p = (min_p_arr == nullptr) ? min_p_val : min_p_arr[bx];\n curandStatePhilox4_32_10_t state;\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n float max_val = GetMaxValue<VEC_SIZE, BLOCK_THREADS, REDUCE_ALGORITHM,\n SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>>(\n probs, row_idx, d, temp_storage);\n float pivot = max_val * p;\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate_gt_pivot = 0;\n float threadlocal_aggregate_gt_pivot = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n float probs_gt_pivot[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot[j] = (probs_vec[j] >= pivot) ? probs_vec[j] : 0;\n threadlocal_aggregate_gt_pivot += probs_gt_pivot[j];\n }\n }\n\n aggregate_gt_pivot += BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot);\n if (tx == 0) {\n temp_storage.block_aggregate.value = aggregate_gt_pivot;\n }\n __syncthreads();\n\n float aggregate = 0;\n float q = temp_storage.block_aggregate.value;\n\n int sampled_id;\n temp_storage.sampled_id = d;\n __syncthreads();\n float u = curand_uniform(&state) * q;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x >= pivot; }, u, probs_vec, aggregate, &temp_storage);\n if (aggregate > u) {\n break;\n }\n }\n sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n output[bx] = sampled_id;\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void TopKTopPSamplingFromProbKernel(DType* probs, IdType* top_k_arr, float* top_p_arr,\n IdType* output, IdType* indices, IdType top_k_val,\n float top_p_val, uint32_t d, uint64_t* seed_arr,\n uint64_t seed_val, uint64_t* offset_arr,\n uint64_t offset_val) {\n const uint32_t batch_size = gridDim.x;\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curandStatePhilox4_32_10_t state;\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n const uint32_t k = top_k_arr == nullptr ? top_k_val : top_k_arr[row_idx];\n const float p = top_p_arr == nullptr ? top_p_val : top_p_arr[row_idx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate;\n float q = 1;\n double low = 0, high = 1.f;\n int sampled_id;\n do {\n temp_storage.sampled_id = d;\n __syncthreads();\n float u = curand_uniform(&state) * q;\n aggregate = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x > low; }, u, probs_vec, aggregate, &temp_storage);\n if (aggregate > u) {\n break;\n }\n }\n __syncthreads();\n sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n double pivot_0 = probs[row_idx * d + sampled_id];\n double pivot_1 = (pivot_0 + high) / 2;\n\n ValueCount<float> aggregate_gt_pivot_0{0, 0}, aggregate_gt_pivot_1{0, 0};\n ValueCount<float> threadlocal_aggregate_gt_pivot_0{0, 0};\n ValueCount<float> threadlocal_aggregate_gt_pivot_1{0, 0};\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n ValueCount<float> probs_gt_pivot_0[VEC_SIZE], probs_gt_pivot_1[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot_0[j] = {\n (probs_vec[j] > pivot_0) ? probs_vec[j] : 0,\n (probs_vec[j] > pivot_0 && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d)};\n probs_gt_pivot_1[j] = {\n (probs_vec[j] > pivot_1) ? probs_vec[j] : 0,\n (probs_vec[j] > pivot_1 && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d)};\n threadlocal_aggregate_gt_pivot_0 += probs_gt_pivot_0[j];\n threadlocal_aggregate_gt_pivot_1 += probs_gt_pivot_1[j];\n }\n }\n aggregate_gt_pivot_0 +=\n BlockReduce<ValueCount<float>, BLOCK_THREADS>(temp_storage.block_prim.reduce_value_count)\n .Sum(threadlocal_aggregate_gt_pivot_0);\n if (tx == 0) {\n temp_storage.block_aggregate.pair = aggregate_gt_pivot_0;\n }\n __syncthreads();\n aggregate_gt_pivot_0 = temp_storage.block_aggregate.pair;\n\n aggregate_gt_pivot_1 +=\n BlockReduce<ValueCount<float>, BLOCK_THREADS>(temp_storage.block_prim.reduce_value_count)\n .Sum(threadlocal_aggregate_gt_pivot_1);\n if (tx == 0) {\n temp_storage.block_aggregate.pair = aggregate_gt_pivot_1;\n }\n __syncthreads();\n aggregate_gt_pivot_1 = temp_storage.block_aggregate.pair;\n if (aggregate_gt_pivot_0.count < k && aggregate_gt_pivot_0.value < p) {\n // case 1: pivot_0 accepted\n break;\n }\n if (aggregate_gt_pivot_1.count < k && aggregate_gt_pivot_1.value < p) {\n // case 2: pivot_0 rejected, pivot_1 accepted\n low = pivot_0;\n high = pivot_1;\n q = aggregate_gt_pivot_0.value;\n } else {\n // case 3: pivot_0 rejected, pivot_1 rejected\n low = pivot_1;\n q = aggregate_gt_pivot_1.value;\n }\n } while (low < high);\n __syncthreads();\n if (tx == 0) {\n output[bx] = sampled_id;\n }\n}\n\ntemplate <typename DType>\ncudaError_t OnlineSoftmax(DType* logits, DType* output, uint32_t batch_size, uint32_t d,\n DType* temperature_arr, DType temperature_val, void* workspace_buffer,\n size_t workspace_buffer_size_in_bytes, bool enable_pdl,\n cudaStream_t stream = 0) {\n constexpr uint32_t SMALL_BATCH_THRESHOLD = 128;\n constexpr uint32_t LARGE_VOCAB_THRESHOLD = 24576;\n constexpr uint32_t DEFAULT_SLICE_SIZE = 8192;\n\n const uint32_t vec_size = std::gcd(16 / sizeof(DType), d);\n auto compute_capacity = GetCudaComputeCapability();\n\n DISPATCH_COMPUTE_CAP_NUM_THREADS(\n compute_capacity, BLOCK_THREADS, {DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n if (batch_size <= SMALL_BATCH_THRESHOLD && d >= LARGE_VOCAB_THRESHOLD) {\n // Path A: Vocab-Splitting Strategy for small-batch & large-vocab\n uint32_t num_slices = ceil_div(d, DEFAULT_SLICE_SIZE);\n\n const size_t partial_buffer_size = batch_size * num_slices * sizeof(PartialSoftmaxResult);\n if (workspace_buffer_size_in_bytes < partial_buffer_size) {\n return cudaErrorInvalidValue;\n }\n\n AlignedAllocator allocator(workspace_buffer, workspace_buffer_size_in_bytes);\n auto partial_results = allocator.aligned_alloc<PartialSoftmaxResult>(\n partial_buffer_size, alignof(PartialSoftmaxResult), \"softmax_workspace\");\n\n // Phase 1: Map-Reduce across vocab slices\n dim3 phase1_nblks(batch_size, num_slices);\n dim3 phase1_nthrs(BLOCK_THREADS);\n size_t smem_size = sizeof(OnlineSoftmaxTempStorage<BLOCK_THREADS>);\n\n auto phase1_kernel = OnlineSoftmaxMapKernel<BLOCK_THREADS, VEC_SIZE, DType>;\n void* phase1_args[] = {&logits, &partial_results, &temperature_arr, &temperature_val,\n &d, &num_slices};\n\n FLASHINFER_CUDA_CALL(cudaFuncSetAttribute(\n phase1_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n if (enable_pdl) {\n cudaLaunchAttribute attribute[1];\n attribute[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attribute[0].val.programmaticStreamSerializationAllowed = 1;\n\n cudaLaunchConfig_t config;\n config.gridDim = phase1_nblks;\n config.blockDim = phase1_nthrs;\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attribute;\n config.numAttrs = 1;\n\n FLASHINFER_CUDA_CALL(cudaLaunchKernelEx(&config, phase1_kernel, logits, partial_results,\n temperature_arr, temperature_val, d,\n num_slices));\n } else {\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)phase1_kernel, phase1_nblks, phase1_nthrs,\n phase1_args, smem_size, stream));\n }\n\n // Phase 2: Final reduction and apply normalization\n dim3 phase2_nblks(batch_size);\n dim3 phase2_nthrs(BLOCK_THREADS);\n\n auto phase2_kernel = OnlineSoftmaxReduceKernel<BLOCK_THREADS, VEC_SIZE, DType>;\n void* phase2_args[] = {&logits, &output, &partial_results, &temperature_arr,\n &temperature_val, &d, &num_slices};\n\n FLASHINFER_CUDA_CALL(cudaFuncSetAttribute(\n phase2_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n if (enable_pdl) {\n cudaLaunchAttribute attribute[1];\n attribute[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attribute[0].val.programmaticStreamSerializationAllowed = 1;\n\n cudaLaunchConfig_t config;\n config.gridDim = phase2_nblks;\n config.blockDim = phase2_nthrs;\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attribute;\n config.numAttrs = 1;\n\n FLASHINFER_CUDA_CALL(cudaLaunchKernelEx(&config, phase2_kernel, logits, output,\n partial_results, temperature_arr,\n temperature_val, d, num_slices));\n } else {\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)phase2_kernel, phase2_nblks, phase2_nthrs,\n phase2_args, smem_size, stream));\n }\n } else {\n // Path B: Single-Block Strategy\n // Switch input cache\n uint32_t cache_threshold;\n if (batch_size <= 16) {\n cache_threshold = 4096;\n } else if (batch_size <= 32) {\n cache_threshold = 2048;\n } else {\n cache_threshold = 0;\n }\n const bool cache_input = d <= cache_threshold;\n\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&logits, &output, &temperature_arr, &temperature_val, &d};\n\n const size_t smem_logits_bytes = (round_up(d, VEC_SIZE) + VEC_SIZE) * sizeof(DType);\n\n uint32_t smem_size = sizeof(OnlineSoftmaxTempStorage<BLOCK_THREADS>) +\n (cache_input ? smem_logits_bytes : 0);\n\n DISPATCH_SOFTMAX_CACHE_INPUT(cache_input, CACHE_INPUT, {\n auto kernel = OnlineSoftmaxFusedKernel<BLOCK_THREADS, VEC_SIZE, DType, CACHE_INPUT>;\n FLASHINFER_CUDA_CALL(cudaFuncSetAttribute(\n kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n if (enable_pdl) {\n cudaLaunchAttribute attribute[1];\n attribute[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attribute[0].val.programmaticStreamSerializationAllowed = 1;\n\n cudaLaunchConfig_t config;\n config.gridDim = nblks;\n config.blockDim = nthrs;\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attribute;\n config.numAttrs = 1;\n\n FLASHINFER_CUDA_CALL(cudaLaunchKernelEx(&config, kernel, logits, output,\n temperature_arr, temperature_val, d));\n } else {\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n }\n });\n }\n })});\n return cudaSuccess;\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t SamplingFromLogits(T* logits, IdType* output, IdType* indices, uint32_t batch_size,\n uint32_t d, bool deterministic, uint64_t* seed_arr,\n uint64_t seed_val, uint64_t* offset_arr, uint64_t offset_val,\n cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&logits, &output, &indices, &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n const uint32_t smem_size = sizeof(\n typename BlockReduce<DataAndIndex<T, IdType>, BLOCK_THREADS, REDUCE_ALGO>::TempStorage);\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = SamplingFromLogitsKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t SamplingFromProb(T* probs, IdType* output, IdType* indices, uint32_t batch_size,\n uint32_t d, bool deterministic, uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &output, &indices, &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = SamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t TopKSamplingFromProb(T* probs, IdType* output, IdType* indices, T* top_k_arr,\n uint32_t batch_size, uint32_t top_k_val, uint32_t d,\n bool deterministic, uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val,\n cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &output, &indices, &top_k_arr, &top_k_val,\n &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = TopKSamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t TopPSamplingFromProb(T* probs, IdType* output, IdType* indices, T* top_p_arr,\n uint32_t batch_size, T top_p_val, uint32_t d, bool deterministic,\n uint64_t* seed_arr, uint64_t seed_val, uint64_t* offset_arr,\n uint64_t offset_val, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &output, &indices, &top_p_arr, &top_p_val,\n &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = TopPSamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t MinPSamplingFromProb(T* probs, T* min_p_arr, IdType* output, IdType* indices,\n uint32_t batch_size, float min_p_val, uint32_t d,\n bool deterministic, uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val,\n cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &min_p_arr, &output, &indices, &min_p_val,\n &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = MinPSamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t TopKTopPSamplingFromProb(T* probs, IdType* top_k_arr, T* top_p_arr, IdType* output,\n IdType* indices, uint32_t batch_size, IdType top_k_val,\n T top_p_val, uint32_t d, bool deterministic,\n uint64_t* seed_arr, uint64_t seed_val, uint64_t* offset_arr,\n uint64_t offset_val, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &top_k_arr, &top_p_arr, &output, &indices, &top_k_val,\n &top_p_val, &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = TopKTopPSamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO,\n VEC_SIZE, DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockReduceAlgorithm REDUCE_ALGORITHM>\nstruct RenormTempStorage {\n union {\n typename BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage reduce;\n typename BlockReduce<int, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage reduce_int;\n typename BlockReduce<ValueCount<float>, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage\n reduce_value_count;\n } block_prim;\n struct {\n float max_val;\n float min_val;\n float row_sum;\n union {\n struct {\n float values[2];\n };\n struct {\n int counts[2];\n };\n struct {\n ValueCount<float> pairs[2];\n };\n } block_aggregate;\n };\n};\n\ntemplate <uint32_t BLOCK_THREADS, BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE,\n typename DType>\n__global__ void TopPRenormProbKernel(DType* probs, DType* renormed_prob, float* top_p_arr,\n float top_p_val, uint32_t d) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n const uint32_t row_idx = bx;\n float p = top_p_arr == nullptr ? top_p_val : top_p_arr[bx];\n\n extern __shared__ __align__(alignof(RenormTempStorage<BLOCK_THREADS, REDUCE_ALGO>))\n uint8_t smem_renorm[];\n auto& temp_storage =\n reinterpret_cast<RenormTempStorage<BLOCK_THREADS, REDUCE_ALGO>&>(smem_renorm);\n vec_t<float, VEC_SIZE> probs_vec;\n\n // Fast-path: when p >= 1.0 (e.g., p == 1.0), perform simple sum and normalization\n if (p >= 1.0f) {\n // Stage A: per-thread float accumulation over assigned lanes (vectorized)\n float thread_sum = 0.0f;\n const uint32_t num_iters = ceil_div(d, BLOCK_THREADS * VEC_SIZE);\n for (uint32_t i = 0; i < num_iters; ++i) {\n probs_vec.fill(0.0f);\n const uint32_t base_idx = (i * BLOCK_THREADS + tx) * VEC_SIZE;\n if (base_idx < d) {\n probs_vec.cast_load(probs + row_idx * d + base_idx);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n const uint32_t idx = base_idx + j;\n if (idx < d) thread_sum += probs_vec[j];\n }\n }\n\n // Block reduce (float)\n float row_sum =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Sum(thread_sum);\n // Broadcast via shared\n if (tx == 0) temp_storage.row_sum = row_sum;\n __syncthreads();\n row_sum = temp_storage.row_sum;\n\n // Guard against zero sum\n const float denom = (row_sum <= 1e-8f) ? 1.0f : row_sum;\n const float normalizer = math::ptx_rcp(denom);\n\n // Stage B: normalize and store\n for (uint32_t i = 0; i < num_iters; ++i) {\n probs_vec.fill(0.0f);\n const uint32_t base_idx = (i * BLOCK_THREADS + tx) * VEC_SIZE;\n if (base_idx < d) {\n probs_vec.cast_load(probs + row_idx * d + base_idx);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n const uint32_t idx = base_idx + j;\n float v = probs_vec[j];\n probs_vec[j] = (idx < d) ? (v * normalizer) : 0.0f;\n }\n if (base_idx < d) {\n probs_vec.cast_store(renormed_prob + row_idx * d + base_idx);\n }\n }\n return; // Exit after fast-path processing\n }\n\n // Original Top-P renormalization logic\n temp_storage.max_val = 0;\n float max_val = GetMaxValue<VEC_SIZE, BLOCK_THREADS, REDUCE_ALGORITHM,\n RenormTempStorage<BLOCK_THREADS, REDUCE_ALGORITHM>>(probs, row_idx, d,\n temp_storage);\n\n double low = 0, high = max_val;\n float min_gt_low, max_le_high;\n float sum_low = 1;\n // f(x) = sum(probs[probs > x]), f(x) is non-increasing\n // min_gt_low = min{p \\in probs | p > low}, max_le_high = max{p \\in probs | p <= high}\n // loop invariant:\n // - f(low) >= p, f(high) < p\n // - f(low) > f(min_gt_low) >= f(max_le_high) == f(high)\n // stopping condition\n // - f(low) >= p, f(min_gt_low) == f(max_le_high) == f(high) < p\n do {\n double pivot_0 = (high + 2 * low) / 3;\n double pivot_1 = (2 * high + low) / 3;\n\n float aggregate_gt_pivot_0 = 0, aggregate_gt_pivot_1 = 0;\n min_gt_low = high;\n max_le_high = low;\n float threadlocal_aggregate_gt_pivot_0 = 0;\n float threadlocal_aggregate_gt_pivot_1 = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n\n float probs_gt_pivot_0[VEC_SIZE], probs_gt_pivot_1[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot_0[j] = (probs_vec[j] > pivot_0) ? probs_vec[j] : 0;\n probs_gt_pivot_1[j] = (probs_vec[j] > pivot_1) ? probs_vec[j] : 0;\n\n if (probs_vec[j] > low && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d) {\n min_gt_low = min(min_gt_low, probs_vec[j]);\n }\n if (probs_vec[j] <= high && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d) {\n max_le_high = max(max_le_high, probs_vec[j]);\n }\n threadlocal_aggregate_gt_pivot_0 += probs_gt_pivot_0[j];\n threadlocal_aggregate_gt_pivot_1 += probs_gt_pivot_1[j];\n }\n }\n aggregate_gt_pivot_0 =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot_0);\n __syncthreads();\n aggregate_gt_pivot_1 =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot_1);\n __syncthreads();\n\n min_gt_low = BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Reduce(min_gt_low, MinReduceOp{});\n __syncthreads();\n max_le_high =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Reduce(max_le_high, MaxReduceOp{});\n if (tx == 0) {\n temp_storage.block_aggregate.values[0] = aggregate_gt_pivot_0;\n temp_storage.block_aggregate.values[1] = aggregate_gt_pivot_1;\n temp_storage.min_val = min_gt_low;\n temp_storage.max_val = max_le_high;\n }\n __syncthreads();\n aggregate_gt_pivot_0 = temp_storage.block_aggregate.values[0];\n aggregate_gt_pivot_1 = temp_storage.block_aggregate.values[1];\n min_gt_low = temp_storage.min_val;\n max_le_high = temp_storage.max_val;\n\n if (aggregate_gt_pivot_1 >= p) {\n low = pivot_1;\n sum_low = aggregate_gt_pivot_1;\n } else if (aggregate_gt_pivot_0 >= p) {\n low = pivot_0;\n high = min(pivot_1, max_le_high);\n sum_low = aggregate_gt_pivot_0;\n } else {\n high = min(pivot_0, max_le_high);\n }\n } while (min_gt_low != max_le_high);\n\n float normalizer = math::ptx_rcp(max(sum_low, 1e-8));\n\n // normalize\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_vec[j] = (probs_vec[j] > low) ? probs_vec[j] * normalizer : 0;\n }\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_store(renormed_prob + row_idx * d + i * BLOCK_THREADS * VEC_SIZE +\n tx * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename DType>\ncudaError_t TopPRenormProb(DType* probs, DType* renormed_prob, float* top_p_arr,\n uint32_t batch_size, float top_p_val, uint32_t d,\n cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(DType), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(RenormTempStorage<BLOCK_THREADS, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &renormed_prob, &top_p_arr, &top_p_val, &d};\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = TopPRenormProbKernel<BLOCK_THREADS, REDUCE_ALGO, VEC_SIZE, DType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n return cudaSuccess;\n });\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void ChainSpeculativeSampling(DType* draft_probs, IdType* draft_token_ids,\n DType* target_probs, IdType* output_token_ids,\n IdType* output_accepted_token_num,\n IdType* output_emitted_draft_token_num,\n uint32_t num_speculative_tokens, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n const uint32_t row_idx = bx;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curandStatePhilox4_32_10_t curand_state;\n curand_init(philox_seed, bx, philox_offset, &curand_state);\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n uint32_t pos = num_speculative_tokens;\n for (uint32_t i = 0; i < num_speculative_tokens; ++i) {\n IdType draft_id = draft_token_ids[row_idx * num_speculative_tokens + i];\n float q = target_probs[(row_idx * (num_speculative_tokens + 1) + i) * d + draft_id],\n p = draft_probs[(row_idx * num_speculative_tokens + i) * d + draft_id];\n float u = curand_uniform(&curand_state);\n if (u * p < q) {\n // accept the draft models output\n output_token_ids[row_idx * (num_speculative_tokens + 1) + i] = draft_id;\n } else {\n pos = i;\n break;\n }\n }\n\n uint32_t emitted_token_num = pos;\n uint32_t accepted_token_num = pos;\n for (uint32_t i = pos; i < num_speculative_tokens; ++i) {\n int draft_id = draft_token_ids[row_idx * num_speculative_tokens + i];\n float q = target_probs[(row_idx * (num_speculative_tokens + 1) + i) * d + draft_id],\n p = draft_probs[(row_idx * num_speculative_tokens + i) * d + draft_id];\n float u = curand_uniform(&curand_state);\n if (u * p < q) {\n ++accepted_token_num;\n }\n }\n\n if (tx == 0) {\n output_accepted_token_num[row_idx] += accepted_token_num;\n output_emitted_draft_token_num[row_idx] += emitted_token_num;\n }\n\n // sample from relu(target_probs - draft_probs)\n float sum_relu_q_minus_p = 0;\n vec_t<float, VEC_SIZE> q_vec, p_vec;\n float relu_q_minus_p[VEC_SIZE];\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n q_vec.fill(0);\n p_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n q_vec.cast_load(target_probs + (row_idx * (num_speculative_tokens + 1) + pos) * d +\n i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n if (pos != num_speculative_tokens) {\n // there is no draft_probs for the bonus token\n p_vec.cast_load(draft_probs + (row_idx * num_speculative_tokens + pos) * d +\n i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n relu_q_minus_p[j] = max(q_vec[j] - p_vec[j], 0.0f);\n }\n sum_relu_q_minus_p +=\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Sum<VEC_SIZE>(relu_q_minus_p);\n __syncthreads();\n }\n if (tx == 0) {\n temp_storage.block_aggregate.value = sum_relu_q_minus_p;\n }\n // init the first rejected token to d\n temp_storage.sampled_id = d;\n __syncthreads();\n sum_relu_q_minus_p = temp_storage.block_aggregate.value;\n float u = curand_uniform(&curand_state) * sum_relu_q_minus_p;\n\n float aggregate_relu_q_minus_p(0);\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n q_vec.fill(0);\n p_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n q_vec.cast_load(target_probs + (row_idx * (num_speculative_tokens + 1) + pos) * d +\n i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n if (pos != num_speculative_tokens) {\n // there is no draft_probs for the bonus token\n p_vec.cast_load(draft_probs + (row_idx * num_speculative_tokens + pos) * d +\n i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n }\n\n vec_t<float, VEC_SIZE> relu_q_minus_p_vec;\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n relu_q_minus_p_vec[j] = max(q_vec[j] - p_vec[j], 0.0f);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x > 0; }, u, relu_q_minus_p_vec, aggregate_relu_q_minus_p,\n &temp_storage);\n if (aggregate_relu_q_minus_p > u) {\n break;\n }\n }\n __syncthreads();\n int sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n // set the first rejected token\n output_token_ids[row_idx * (num_speculative_tokens + 1) + pos] = sampled_id;\n // move to the next token\n pos++;\n\n // pad remaining tokens with -1\n for (; pos < num_speculative_tokens + 1; ++pos) {\n output_token_ids[row_idx * (num_speculative_tokens + 1) + pos] = -1;\n }\n}\n\ntemplate <typename DType, typename IdType>\ncudaError_t ChainSpeculativeSampling(\n DType* draft_probs, IdType* draft_token_ids, DType* target_probs, IdType* output_token_ids,\n IdType* output_accepted_token_num, IdType* output_emitted_draft_token_num, uint32_t batch_size,\n uint32_t num_speculative_tokens, uint32_t d, bool deterministic, uint64_t* seed_arr,\n uint64_t seed_val, uint64_t* offset_arr, uint64_t offset_val, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(DType), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&draft_probs,\n &draft_token_ids,\n &target_probs,\n &output_token_ids,\n &output_accepted_token_num,\n &output_emitted_draft_token_num,\n &num_speculative_tokens,\n &d,\n &seed_arr,\n &seed_val,\n &offset_arr,\n &offset_val};\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = ChainSpeculativeSampling<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, DType, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\n} // namespace sampling\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_SAMPLING_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/sampling.cuh\n+++ include/flashinfer/sampling.cuh\n@@ -664,9 +664,11 @@\n // and including 1.0. kSCALE is used to exclude 1.0, s.t.\n // 1.18e-38 <= x * kSCALE <= 1.0f - epsilon\n // => -4.47 <= -log(-log(...)) <= 15.9\n+ // log2f maps to a single PTX LG2 instruction on NVIDIA GPUs, while logf\n+ // internally computes log2f * ln(2). Using log2f with a single kLOG2\n+ // multiplication is more efficient (3 ops vs 4 ops).\n return -kLOG2 * log2f(-log2f((x * kSCALE)));\n };\n-// TODO: compare the speed of log2 and log\n #pragma unroll\n for (uint32_t i = 0; i + 4 <= VEC_SIZE; i += 4) {\n curand_init(philox_seed, subsequence + i, philox_offset, &state);"},"lines_added":{"kind":"number","value":3,"string":"3"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/sampling.cuh).\n\nGoal: docs: resolve TODO by documenting log2f vs logf performance rationale in sampling\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_SAMPLING_CUH_\n#define FLASHINFER_SAMPLING_CUH_\n\n#include <cuda.h>\n#include <curand.h>\n#include <curand_kernel.h>\n#include <curand_philox4x32_x.h>\n\n#include <cstdlib>\n#include <cstring>\n#include <cub/cub.cuh>\n#include <cuda/functional>\n#include <cuda/std/functional>\n#include <cuda/std/limits>\n#include <limits>\n#include <numeric>\n#include <tuple>\n\n#include \"allocator.h\"\n#include \"math.cuh\"\n#include \"topk.cuh\"\n#include \"utils.cuh\"\n#include \"vec_dtypes.cuh\"\n\n// Define reduction operators based on CUDA version\n// CUDA 13 (12.9+) deprecated cub::Max/Min in favor of cuda::maximum/minimum\n#if CUDA_VERSION >= 12090\nusing MaxReduceOp = cuda::maximum<>;\nusing MinReduceOp = cuda::minimum<>;\n#else\nusing MaxReduceOp = cub::Max;\nusing MinReduceOp = cub::Min;\n#endif\n\nnamespace flashinfer {\n\nnamespace sampling {\n\nusing namespace cub;\n\n#define DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, ...) \\\n if (deterministic) { \\\n constexpr bool DETERMINISTIC = true; \\\n __VA_ARGS__ \\\n } else { \\\n constexpr bool DETERMINISTIC = false; \\\n __VA_ARGS__ \\\n }\n\n#define DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, ...) \\\n if (compute_capacity.first >= 8) { \\\n constexpr uint32_t BLOCK_THREADS = 1024; \\\n __VA_ARGS__ \\\n } else { \\\n constexpr uint32_t BLOCK_THREADS = 512; \\\n __VA_ARGS__ \\\n }\n\n#define DISPATCH_SOFTMAX_CACHE_INPUT(cache_input, CACHE_INPUT, ...) \\\n if (cache_input) { \\\n constexpr bool CACHE_INPUT = true; \\\n __VA_ARGS__ \\\n } else { \\\n constexpr bool CACHE_INPUT = false; \\\n __VA_ARGS__ \\\n }\n\nconstexpr BlockScanAlgorithm SCAN_ALGO = BLOCK_SCAN_WARP_SCANS;\nconstexpr BlockReduceAlgorithm REDUCE_ALGO = BLOCK_REDUCE_WARP_REDUCTIONS;\n\n#if (__CUDACC_VER_MAJOR__ * 10000 + __CUDACC_VER_MINOR__ * 100 >= 120100)\n#define FLASHINFER_CUB_SUBTRACTLEFT_DEFINED\n#endif\n\ntemplate <typename T>\nstruct ValueCount {\n T value;\n int count;\n\n __device__ ValueCount operator+(const ValueCount& other) const {\n return {value + other.value, count + other.count};\n }\n __device__ ValueCount& operator+=(const ValueCount& other) {\n value += other.value;\n count += other.count;\n return *this;\n }\n};\n\nstruct BoolDiffOp {\n __device__ __forceinline__ bool operator()(const bool& lhs, const bool& rhs) const {\n return lhs != rhs;\n }\n};\n\nstruct Float2SoftmaxReduceOp {\n __device__ __forceinline__ float2 operator()(const float2& a, const float2& b) const {\n if (isinf(a.x)) return b;\n if (isinf(b.x)) return a;\n\n float new_max = max(a.x, b.x);\n float new_denom = a.y * __expf(a.x - new_max) + b.y * __expf(b.x - new_max);\n return make_float2(new_max, new_denom);\n }\n};\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM>\nstruct SamplingTempStorage {\n union {\n float deterministic_scan[BLOCK_THREADS / 32];\n typename BlockScan<float, BLOCK_THREADS, SCAN_ALGORITHM>::TempStorage scan;\n typename BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage reduce;\n typename BlockReduce<int, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage reduce_int;\n typename BlockReduce<ValueCount<float>, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage\n reduce_value_count;\n typename BlockAdjacentDifference<bool, BLOCK_THREADS>::TempStorage adj_diff;\n } block_prim;\n struct {\n int32_t sampled_id;\n int32_t last_valid_id;\n float max_val;\n union {\n float value;\n ValueCount<float> pair;\n } block_aggregate;\n };\n};\n\ntemplate <uint32_t BLOCK_THREADS>\nstruct OnlineSoftmaxTempStorage {\n union {\n typename cub::BlockReduce<float, BLOCK_THREADS>::TempStorage reduce;\n typename cub::BlockReduce<float2, BLOCK_THREADS>::TempStorage reduce_pair;\n } block_prim;\n\n struct {\n float max_val;\n float denominator;\n } shared_state;\n};\n\nstruct PartialSoftmaxResult {\n float max_val;\n float denominator;\n};\n\n/*!\n * \\brief Deterministic inclusive scan implementation, use Belloch scan algorithm.\n * \\note This implementation is slower than the cub::BlockScan, but it is deterministic.\n */\ntemplate <uint32_t VEC_SIZE, uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM>\n__device__ __forceinline__ void DeterministicInclusiveSum(\n const float* in_data, float* out_data,\n SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>* temp_storage) {\n float* smem_prefix_sum = temp_storage->block_prim.deterministic_scan;\n float thread_data[VEC_SIZE];\n float thread_sum = 0;\n#pragma unroll\n for (uint32_t i = 0; i < VEC_SIZE; ++i) {\n thread_sum += in_data[i];\n thread_data[i] = thread_sum;\n }\n\n float thread_exclusive_prefix_sum = thread_sum;\n\n#pragma unroll\n for (uint32_t offset = 1; offset < 32; offset *= 2) {\n float tmp = __shfl_up_sync(0xffffffff, thread_exclusive_prefix_sum, offset);\n if ((threadIdx.x + 1) % (offset * 2) == 0) {\n thread_exclusive_prefix_sum += tmp;\n }\n }\n\n float warp_sum = __shfl_sync(0xffffffff, thread_exclusive_prefix_sum, threadIdx.x | 0xffffffff);\n if (threadIdx.x % 32 == 31) {\n thread_exclusive_prefix_sum = 0;\n }\n\n#pragma unroll\n for (uint32_t offset = 16; offset >= 1; offset /= 2) {\n float tmp = __shfl_xor_sync(0xffffffff, thread_exclusive_prefix_sum, offset);\n if ((threadIdx.x + 1) % (offset * 2) == 0) {\n thread_exclusive_prefix_sum = tmp + thread_exclusive_prefix_sum;\n }\n if ((threadIdx.x + 1) % (offset * 2) == offset) {\n thread_exclusive_prefix_sum = tmp;\n }\n }\n\n smem_prefix_sum[threadIdx.x / 32] = warp_sum;\n __syncthreads();\n\n if (threadIdx.x < 32) {\n float warp_exclusive_prefix_sum =\n (threadIdx.x < BLOCK_THREADS / 32) ? smem_prefix_sum[threadIdx.x] : 0;\n\n#pragma unroll\n for (uint32_t offset = 1; offset < 32; offset *= 2) {\n float tmp = __shfl_up_sync(0xffffffff, warp_exclusive_prefix_sum, offset);\n if ((threadIdx.x + 1) % (offset * 2) == 0) {\n warp_exclusive_prefix_sum += tmp;\n }\n }\n\n if (threadIdx.x % 32 == 31) {\n warp_exclusive_prefix_sum = 0;\n }\n\n#pragma unroll\n for (uint32_t offset = 16; offset >= 1; offset /= 2) {\n float tmp = __shfl_xor_sync(0xffffffff, warp_exclusive_prefix_sum, offset);\n if ((threadIdx.x + 1) % (offset * 2) == 0) {\n warp_exclusive_prefix_sum = tmp + warp_exclusive_prefix_sum;\n }\n if ((threadIdx.x + 1) % (offset * 2) == offset) {\n warp_exclusive_prefix_sum = tmp;\n }\n }\n if (threadIdx.x < BLOCK_THREADS / 32) {\n smem_prefix_sum[threadIdx.x] = warp_exclusive_prefix_sum;\n }\n }\n __syncthreads();\n\n#pragma unroll\n for (uint32_t i = 0; i < VEC_SIZE; ++i) {\n out_data[i] = smem_prefix_sum[threadIdx.x / 32] + thread_exclusive_prefix_sum + thread_data[i];\n }\n}\n\ntemplate <uint32_t VEC_SIZE, uint32_t BLOCK_THREADS, BlockReduceAlgorithm REDUCE_ALGORITHM,\n typename TempStorage>\n__device__ __forceinline__ float GetMaxValue(float* in_data, uint32_t row_idx, uint32_t d,\n TempStorage& temp_storage) {\n const uint32_t tx = threadIdx.x;\n vec_t<float, VEC_SIZE> in_data_vec;\n\n // Thread-local max accumulation (deferred reduction)\n float thread_max = 0.0f;\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n in_data_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n in_data_vec.cast_load(in_data + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n thread_max = max(thread_max, static_cast<float>(in_data_vec[j]));\n }\n }\n\n // Single block reduction after loop completes\n float max_val =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Reduce(thread_max, MaxReduceOp{});\n if (tx == 0) {\n temp_storage.max_val = max_val;\n }\n __syncthreads();\n return temp_storage.max_val;\n}\n\ntemplate <uint32_t BLOCK_THREADS, uint32_t VEC_SIZE, typename DType, bool CACHE_INPUT>\n__global__ void OnlineSoftmaxFusedKernel(DType* logits, DType* output, DType* temperature_arr,\n DType temperature_val, uint32_t d) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n float temperature = temperature_arr == nullptr ? temperature_val : temperature_arr[bx];\n const float inv_temp = (temperature == 0.f) ? 0.f : 1.f / temperature;\n\n using TempStorage = OnlineSoftmaxTempStorage<BLOCK_THREADS>;\n extern __shared__ __align__(alignof(TempStorage)) uint8_t smem[];\n auto& temp_storage = reinterpret_cast<TempStorage&>(smem);\n\n DType* smem_vec_base = nullptr;\n if constexpr (CACHE_INPUT) {\n constexpr size_t vec_alignment = alignof(vec_t<DType, VEC_SIZE>);\n size_t aligned_offset = round_up(sizeof(TempStorage), vec_alignment);\n smem_vec_base = reinterpret_cast<DType*>(smem + aligned_offset);\n }\n\n vec_t<DType, VEC_SIZE> logits_vec;\n\n float running_max = -cuda::std::numeric_limits<float>::infinity();\n float running_denominator = 0.0f;\n float threadlocal_running_denominator = 0.0f;\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n // Pass 1: Compute running max and denominator\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n logits_vec.fill(-cuda::std::numeric_limits<DType>::infinity());\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.cast_load(logits + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n logits_vec[j] *= inv_temp;\n }\n\n if constexpr (CACHE_INPUT) {\n logits_vec.store(smem_vec_base + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n }\n\n float thread_max = -cuda::std::numeric_limits<float>::infinity();\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n thread_max = max(thread_max, logits_vec[j]);\n }\n float block_max = cub::BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Reduce(thread_max, MaxReduceOp{});\n\n if (tx == 0) {\n temp_storage.shared_state.max_val = block_max;\n }\n __syncthreads();\n block_max = temp_storage.shared_state.max_val;\n // if block_max is -inf, then this block contains all -inf values, so we can skip updating\n if (!isinf(block_max)) {\n float threadlocal_sum = 0.0f;\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n threadlocal_sum += __expf(logits_vec[j] - block_max);\n }\n float new_max = max(running_max, block_max);\n threadlocal_running_denominator =\n threadlocal_running_denominator * __expf(running_max - new_max) +\n threadlocal_sum * __expf(block_max - new_max);\n running_max = new_max;\n }\n }\n\n running_denominator = cub::BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_running_denominator);\n if (tx == 0) {\n temp_storage.shared_state.denominator = running_denominator;\n }\n __syncthreads();\n running_denominator = temp_storage.shared_state.denominator;\n\n const float final_max = running_max;\n const float inv_denominator = 1.0f / running_denominator;\n\n // Pass 2: Normalize in place\n vec_t<DType, VEC_SIZE> prob_vec;\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n if constexpr (CACHE_INPUT) {\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.load(smem_vec_base + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n } else {\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.cast_load(logits + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n logits_vec[j] *= inv_temp;\n }\n }\n }\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n float p = __expf(static_cast<float>(logits_vec[j]) - final_max) * inv_denominator;\n prob_vec[j] = static_cast<DType>(p);\n }\n\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n prob_vec.cast_store(output + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n }\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\ntemplate <uint32_t BLOCK_THREADS, uint32_t VEC_SIZE, typename DType>\n__global__ void OnlineSoftmaxMapKernel(DType* logits, PartialSoftmaxResult* partial_results,\n DType* temperature_arr, float temperature_val, uint32_t d,\n uint32_t num_slices) {\n const uint32_t bx = blockIdx.x;\n const uint32_t by = blockIdx.y; // slice index\n const uint32_t tx = threadIdx.x;\n float temperature = temperature_arr == nullptr ? temperature_val : temperature_arr[bx];\n const float inv_temp = (temperature == 0.f) ? 0.f : 1.f / temperature;\n\n const uint32_t vec_alignment_elems = alignof(vec_t<DType, VEC_SIZE>) / sizeof(DType);\n const uint32_t slice_stride = round_up(ceil_div(d, num_slices), vec_alignment_elems);\n const uint32_t slice_start = by * slice_stride;\n const uint32_t slice_size = min((by + 1) * slice_stride, d) - slice_start;\n\n if (slice_start >= d) return;\n\n using TempStorage = OnlineSoftmaxTempStorage<BLOCK_THREADS>;\n extern __shared__ __align__(alignof(TempStorage)) uint8_t smem[];\n auto& temp_storage = reinterpret_cast<TempStorage&>(smem);\n\n vec_t<DType, VEC_SIZE> logits_vec;\n float running_max = -cuda::std::numeric_limits<float>::infinity();\n float running_denominator = 0.0f;\n float threadlocal_running_denominator = 0.0f;\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(slice_size, BLOCK_THREADS * VEC_SIZE); ++i) {\n logits_vec.fill(-cuda::std::numeric_limits<DType>::infinity());\n\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < slice_size) {\n logits_vec.cast_load(logits + bx * d + slice_start + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n float thread_max = -cuda::std::numeric_limits<float>::infinity();\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n logits_vec[j] *= inv_temp;\n thread_max = max(thread_max, logits_vec[j]);\n }\n\n float block_max = cub::BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Reduce(thread_max, MaxReduceOp{});\n\n if (tx == 0) {\n temp_storage.shared_state.max_val = block_max;\n }\n __syncthreads();\n block_max = temp_storage.shared_state.max_val;\n\n // if block_max is -inf, then this block contains all -inf values, so we can skip updating\n if (!isinf(block_max)) {\n float threadlocal_sum = 0.0f;\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n threadlocal_sum += __expf(logits_vec[j] - block_max);\n }\n float new_max = max(running_max, block_max);\n threadlocal_running_denominator =\n threadlocal_running_denominator * __expf(running_max - new_max) +\n threadlocal_sum * __expf(block_max - new_max);\n running_max = new_max;\n }\n }\n\n running_denominator = cub::BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_running_denominator);\n if (tx == 0) {\n temp_storage.shared_state.denominator = running_denominator;\n }\n __syncthreads();\n running_denominator = temp_storage.shared_state.denominator;\n\n if (tx == 0) {\n partial_results[bx * num_slices + by] = {running_max, running_denominator};\n }\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\ntemplate <uint32_t BLOCK_THREADS, uint32_t VEC_SIZE, typename DType>\n__global__ void OnlineSoftmaxReduceKernel(DType* logits, DType* output,\n PartialSoftmaxResult* partial_results,\n DType* temperature_arr, float temperature_val, uint32_t d,\n uint32_t num_slices) {\n const uint32_t bx = blockIdx.x;\n const uint32_t tx = threadIdx.x;\n float temperature = temperature_arr == nullptr ? temperature_val : temperature_arr[bx];\n const float inv_temp = (temperature == 0.f) ? 0.f : 1.f / temperature;\n\n // Reduce slice results\n using TempStorage = OnlineSoftmaxTempStorage<BLOCK_THREADS>;\n extern __shared__ __align__(alignof(TempStorage)) uint8_t smem[];\n auto& temp_storage = reinterpret_cast<TempStorage&>(smem);\n\n const Float2SoftmaxReduceOp reduce_op;\n\n float2 thread_aggregate = make_float2(-cuda::std::numeric_limits<float>::infinity(), 0.0f);\n\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n for (uint32_t i = tx; i < num_slices; i += BLOCK_THREADS) {\n PartialSoftmaxResult partial = partial_results[bx * num_slices + i];\n float2 partial_pair = make_float2(partial.max_val, partial.denominator);\n thread_aggregate = reduce_op(thread_aggregate, partial_pair);\n }\n\n float2 block_result = cub::BlockReduce<float2, BLOCK_THREADS>(temp_storage.block_prim.reduce_pair)\n .Reduce(thread_aggregate, reduce_op);\n\n if (tx == 0) {\n temp_storage.shared_state.max_val = block_result.x;\n temp_storage.shared_state.denominator = block_result.y;\n }\n __syncthreads();\n\n block_result =\n make_float2(temp_storage.shared_state.max_val, temp_storage.shared_state.denominator);\n\n const float final_max = temp_storage.shared_state.max_val;\n const float inv_denominator = 1.0f / temp_storage.shared_state.denominator;\n\n // Apply normalization\n vec_t<DType, VEC_SIZE> logits_vec;\n vec_t<DType, VEC_SIZE> prob_vec;\n\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n logits_vec.fill(-cuda::std::numeric_limits<DType>::infinity());\n\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.cast_load(logits + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n logits_vec[j] *= inv_temp;\n float p = __expf(static_cast<float>(logits_vec[j]) - final_max) * inv_denominator;\n prob_vec[j] = static_cast<DType>(p);\n }\n\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n prob_vec.cast_store(output + bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n }\n#if (__CUDACC_VER_MAJOR__ >= 12 && defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n\ntemplate <uint32_t VEC_SIZE, uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, bool DETERMINISTIC, typename Predicate>\n__device__ __forceinline__ void DeviceSamplingFromProb(\n uint32_t i, uint32_t d, Predicate pred, float u, vec_t<float, VEC_SIZE> prob_vec,\n float& aggregate,\n SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>* temp_storage) {\n const uint32_t tx = threadIdx.x;\n float prob_greater_than_threshold[VEC_SIZE];\n float inclusive_cdf[VEC_SIZE];\n bool greater_than_u[VEC_SIZE], valid[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n prob_greater_than_threshold[j] = pred(prob_vec[j]) ? prob_vec[j] : 0;\n valid[j] = pred(prob_vec[j]) && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d;\n }\n float aggregate_local =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage->block_prim.reduce)\n .template Sum<VEC_SIZE>(prob_greater_than_threshold);\n if (tx == 0) {\n temp_storage->block_aggregate.value = aggregate_local;\n }\n __syncthreads();\n aggregate_local = temp_storage->block_aggregate.value;\n\n if (aggregate + aggregate_local > u) {\n if constexpr (DETERMINISTIC) {\n DeterministicInclusiveSum<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>(\n prob_greater_than_threshold, inclusive_cdf, temp_storage);\n } else {\n BlockScan<float, BLOCK_THREADS, SCAN_ALGORITHM>(temp_storage->block_prim.scan)\n .template InclusiveSum<VEC_SIZE>(prob_greater_than_threshold, inclusive_cdf);\n\n __syncthreads();\n }\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n greater_than_u[j] = (inclusive_cdf[j] + aggregate > u) && valid[j];\n }\n\n bool greater_than_u_diff[VEC_SIZE];\n#ifdef FLASHINFER_CUB_SUBTRACTLEFT_DEFINED\n BlockAdjacentDifference<bool, BLOCK_THREADS>(temp_storage->block_prim.adj_diff)\n .SubtractLeft<VEC_SIZE>(greater_than_u, greater_than_u_diff, BoolDiffOp());\n#else\n BlockAdjacentDifference<bool, BLOCK_THREADS>(temp_storage->block_prim.adj_diff)\n .template FlagHeads<VEC_SIZE>(greater_than_u_diff, greater_than_u, BoolDiffOp(), 0);\n#endif\n __syncthreads();\n\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n if (greater_than_u_diff[j]) {\n atomicMin(&(temp_storage->sampled_id), (i * BLOCK_THREADS + tx) * VEC_SIZE + j);\n }\n }\n __syncthreads();\n }\n\n // update the last valid index\n int valid_index[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n if (valid[j]) {\n valid_index[j] = (i * BLOCK_THREADS + tx) * VEC_SIZE + j;\n } else {\n valid_index[j] = -1;\n }\n }\n int max_valid_index =\n BlockReduce<int, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage->block_prim.reduce_int)\n .Reduce(valid_index, MaxReduceOp{});\n if (tx == 0 && max_valid_index != -1) {\n temp_storage->last_valid_id = max_valid_index;\n }\n __syncthreads();\n aggregate += aggregate_local;\n}\n\ntemplate <typename DType, typename IdType>\nstruct DataAndIndex {\n DType data;\n IdType index;\n\n __device__ DataAndIndex operator+(const DataAndIndex& other) const {\n if (data > other.data) {\n return {data, index};\n } else {\n return {other.data, other.index};\n }\n }\n __device__ DataAndIndex& operator+=(const DataAndIndex& other) {\n if (data > other.data) {\n return *this;\n } else {\n data = other.data;\n index = other.index;\n return *this;\n }\n }\n};\n\ntemplate <typename DType, uint32_t VEC_SIZE>\n__device__ __forceinline__ vec_t<DType, VEC_SIZE> GenerateGumbelNoise(uint64_t philox_seed,\n uint64_t philox_offset,\n uint64_t subsequence) {\n curandStatePhilox4_32_10_t state;\n vec_t<float, VEC_SIZE> noise;\n constexpr float kSCALE = 1.0f - cuda::std::numeric_limits<float>::epsilon();\n constexpr float kLOG2 = 0.6931471806f;\n auto uniform2gumbel = [](float x) {\n // NB: cuRAND returns strictly positive normal floating point numbers, up to\n // and including 1.0. kSCALE is used to exclude 1.0, s.t.\n // 1.18e-38 <= x * kSCALE <= 1.0f - epsilon\n // => -4.47 <= -log(-log(...)) <= 15.9\n return -kLOG2 * log2f(-log2f((x * kSCALE)));\n };\n// TODO: compare the speed of log2 and log\n#pragma unroll\n for (uint32_t i = 0; i + 4 <= VEC_SIZE; i += 4) {\n curand_init(philox_seed, subsequence + i, philox_offset, &state);\n float4 noise_vec = curand_uniform4(&state);\n noise[i] = uniform2gumbel(noise_vec.x);\n noise[i + 1] = uniform2gumbel(noise_vec.y);\n noise[i + 2] = uniform2gumbel(noise_vec.z);\n noise[i + 3] = uniform2gumbel(noise_vec.w);\n }\n if constexpr (VEC_SIZE % 4 != 0) {\n curand_init(philox_seed, subsequence + VEC_SIZE / 4 * 4, philox_offset, &state);\n float4 noise_vec = curand_uniform4(&state);\n if constexpr (VEC_SIZE % 4 == 1) {\n noise[VEC_SIZE - 1] = uniform2gumbel(noise_vec.x);\n } else if constexpr (VEC_SIZE % 4 == 2) {\n noise[VEC_SIZE - 2] = uniform2gumbel(noise_vec.x);\n noise[VEC_SIZE - 1] = uniform2gumbel(noise_vec.y);\n } else if constexpr (VEC_SIZE % 4 == 3) {\n noise[VEC_SIZE - 3] = uniform2gumbel(noise_vec.x);\n noise[VEC_SIZE - 2] = uniform2gumbel(noise_vec.y);\n noise[VEC_SIZE - 1] = uniform2gumbel(noise_vec.z);\n }\n }\n\n if constexpr (std::is_same_v<DType, float>) {\n return noise;\n } else {\n vec_t<DType, VEC_SIZE> ret;\n#pragma unroll\n for (uint32_t i = 0; i < VEC_SIZE; ++i) {\n ret[i] = static_cast<DType>(noise[i]);\n }\n return ret;\n }\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void SamplingFromLogitsKernel(DType* logits, IdType* output, IdType* indices, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n using SharedMem = typename BlockReduce<DataAndIndex<DType, IdType>, BLOCK_THREADS,\n REDUCE_ALGORITHM>::TempStorage;\n extern __shared__ __align__(alignof(SharedMem)) uint8_t smem_sampling_logit[];\n auto& temp_storage = reinterpret_cast<SharedMem&>(smem_sampling_logit);\n\n vec_t<DType, VEC_SIZE> logits_vec;\n DataAndIndex<DType, IdType> max_data = {-cuda::std::numeric_limits<DType>::infinity(), 0};\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n logits_vec.fill(-cuda::std::numeric_limits<DType>::infinity());\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n logits_vec.cast_load(logits + row_idx * d + i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n\n vec_t<DType, VEC_SIZE> gumbel_noise = GenerateGumbelNoise<DType, VEC_SIZE>(\n philox_seed, philox_offset,\n static_cast<uint64_t>(bx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE));\n DataAndIndex<DType, IdType> cur_data[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n cur_data[j].data = (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d\n ? logits_vec[j] + gumbel_noise[j]\n : -cuda::std::numeric_limits<DType>::infinity();\n cur_data[j].index = (i * BLOCK_THREADS + tx) * VEC_SIZE + j;\n }\n\n max_data +=\n BlockReduce<DataAndIndex<DType, IdType>, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage)\n .template Sum<VEC_SIZE>(cur_data);\n }\n if (tx == 0) {\n output[bx] = max_data.index;\n }\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void SamplingFromProbKernel(DType* probs, IdType* output, IdType* indices, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val, uint64_t* offset_arr,\n uint64_t offset_val) {\n curandStatePhilox4_32_10_t state;\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n temp_storage.sampled_id = d;\n __syncthreads();\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate(0);\n float u = curand_uniform(&state);\n\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [](float x) { return x > 0; }, u, probs_vec, aggregate, &temp_storage);\n if (float(aggregate) > u) {\n break;\n }\n }\n int sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n output[bx] = sampled_id;\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void TopKSamplingFromProbKernel(DType* probs, IdType* output, IdType* indices,\n IdType* top_k_arr, uint32_t top_k_val, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t batch_size = gridDim.x;\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curandStatePhilox4_32_10_t state;\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t k = top_k_arr == nullptr ? top_k_val : top_k_arr[bx];\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate;\n float q = 1;\n double low = 0, high = 1.f;\n int sampled_id;\n int round = 0;\n do {\n round += 1;\n temp_storage.sampled_id = d;\n __syncthreads();\n float u = curand_uniform(&state) * q;\n aggregate = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x > low; }, u, probs_vec, aggregate, &temp_storage);\n if (aggregate > u) {\n break;\n }\n }\n __syncthreads();\n sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n double pivot_0 = probs[row_idx * d + sampled_id];\n double pivot_1 = (pivot_0 + high) / 2;\n\n ValueCount<float> aggregate_gt_pivot_0{0, 0}, aggregate_gt_pivot_1{0, 0};\n ValueCount<float> threadlocal_gt_pivot_0{0, 0}, threadlocal_gt_pivot_1{0, 0};\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n ValueCount<float> probs_gt_pivot_0[VEC_SIZE], probs_gt_pivot_1[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot_0[j] = {\n (probs_vec[j] > pivot_0) ? probs_vec[j] : 0,\n (probs_vec[j] > pivot_0 && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d)};\n probs_gt_pivot_1[j] = {\n (probs_vec[j] > pivot_1) ? probs_vec[j] : 0,\n (probs_vec[j] > pivot_1 && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d)};\n threadlocal_gt_pivot_0 += probs_gt_pivot_0[j];\n threadlocal_gt_pivot_1 += probs_gt_pivot_1[j];\n }\n }\n aggregate_gt_pivot_0 += BlockReduce<ValueCount<float>, BLOCK_THREADS, REDUCE_ALGORITHM>(\n temp_storage.block_prim.reduce_value_count)\n .Sum(threadlocal_gt_pivot_0);\n if (tx == 0) {\n temp_storage.block_aggregate.pair = aggregate_gt_pivot_0;\n }\n __syncthreads();\n aggregate_gt_pivot_0 = temp_storage.block_aggregate.pair;\n\n aggregate_gt_pivot_1 += BlockReduce<ValueCount<float>, BLOCK_THREADS, REDUCE_ALGORITHM>(\n temp_storage.block_prim.reduce_value_count)\n .Sum(threadlocal_gt_pivot_1);\n if (tx == 0) {\n temp_storage.block_aggregate.pair = aggregate_gt_pivot_1;\n }\n __syncthreads();\n aggregate_gt_pivot_1 = temp_storage.block_aggregate.pair;\n if (aggregate_gt_pivot_0.count < k) {\n // case 1: pivot_0 accepted\n break;\n }\n if (aggregate_gt_pivot_1.count < k) {\n // case 2: pivot_0 rejected, pivot_1 accepted\n low = pivot_0;\n high = pivot_1;\n q = aggregate_gt_pivot_0.value;\n } else {\n // case 3: pivot_0 rejected, pivot_1 rejected\n low = pivot_1;\n q = aggregate_gt_pivot_1.value;\n }\n } while (low < high);\n __syncthreads();\n if (tx == 0) {\n output[bx] = sampled_id;\n }\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void TopPSamplingFromProbKernel(DType* probs, IdType* output, IdType* indices,\n float* top_p_arr, float top_p_val, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t batch_size = gridDim.x;\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curandStatePhilox4_32_10_t state;\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n float top_p = (top_p_arr == nullptr) ? top_p_val : top_p_arr[row_idx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate;\n float q = 1;\n double low = 0, high = 1.f;\n int sampled_id;\n do {\n temp_storage.sampled_id = d;\n __syncthreads();\n float u = curand_uniform(&state) * q;\n aggregate = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x > low; }, u, probs_vec, aggregate, &temp_storage);\n if (aggregate > u) {\n break;\n }\n }\n __syncthreads();\n sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n double pivot_0 = probs[row_idx * d + sampled_id];\n double pivot_1 = (pivot_0 + high) / 2;\n\n float aggregate_gt_pivot_0 = 0, aggregate_gt_pivot_1 = 0;\n float threadlocal_aggregate_gt_pivot_0 = 0;\n float threadlocal_aggregate_gt_pivot_1 = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n float probs_gt_pivot_0[VEC_SIZE], probs_gt_pivot_1[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot_0[j] = (probs_vec[j] > pivot_0) ? probs_vec[j] : 0;\n probs_gt_pivot_1[j] = (probs_vec[j] > pivot_1) ? probs_vec[j] : 0;\n threadlocal_aggregate_gt_pivot_0 += probs_gt_pivot_0[j];\n threadlocal_aggregate_gt_pivot_1 += probs_gt_pivot_1[j];\n }\n }\n aggregate_gt_pivot_0 += BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot_0);\n if (tx == 0) {\n temp_storage.block_aggregate.value = aggregate_gt_pivot_0;\n }\n __syncthreads();\n aggregate_gt_pivot_0 = temp_storage.block_aggregate.value;\n\n aggregate_gt_pivot_1 += BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot_1);\n if (tx == 0) {\n temp_storage.block_aggregate.value = aggregate_gt_pivot_1;\n }\n __syncthreads();\n aggregate_gt_pivot_1 = temp_storage.block_aggregate.value;\n\n if (aggregate_gt_pivot_0 < top_p) {\n // case 1: pivot_0 accepted\n break;\n }\n if (aggregate_gt_pivot_1 < top_p) {\n // case 2: pivot_0 rejected, pivot_1 accepted\n low = pivot_0;\n high = pivot_1;\n q = aggregate_gt_pivot_0;\n } else {\n // case 3: pivot_0 rejected, pivot_1 rejected\n low = pivot_1;\n q = aggregate_gt_pivot_1;\n }\n } while (low < high);\n __syncthreads();\n if (tx == 0) {\n output[bx] = sampled_id;\n }\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void MinPSamplingFromProbKernel(DType* probs, float* min_p_arr, IdType* output,\n IdType* indices, float min_p_val, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n float p = (min_p_arr == nullptr) ? min_p_val : min_p_arr[bx];\n curandStatePhilox4_32_10_t state;\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n float max_val = GetMaxValue<VEC_SIZE, BLOCK_THREADS, REDUCE_ALGORITHM,\n SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>>(\n probs, row_idx, d, temp_storage);\n float pivot = max_val * p;\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate_gt_pivot = 0;\n float threadlocal_aggregate_gt_pivot = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n float probs_gt_pivot[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot[j] = (probs_vec[j] >= pivot) ? probs_vec[j] : 0;\n threadlocal_aggregate_gt_pivot += probs_gt_pivot[j];\n }\n }\n\n aggregate_gt_pivot += BlockReduce<float, BLOCK_THREADS>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot);\n if (tx == 0) {\n temp_storage.block_aggregate.value = aggregate_gt_pivot;\n }\n __syncthreads();\n\n float aggregate = 0;\n float q = temp_storage.block_aggregate.value;\n\n int sampled_id;\n temp_storage.sampled_id = d;\n __syncthreads();\n float u = curand_uniform(&state) * q;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x >= pivot; }, u, probs_vec, aggregate, &temp_storage);\n if (aggregate > u) {\n break;\n }\n }\n sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n output[bx] = sampled_id;\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void TopKTopPSamplingFromProbKernel(DType* probs, IdType* top_k_arr, float* top_p_arr,\n IdType* output, IdType* indices, IdType top_k_val,\n float top_p_val, uint32_t d, uint64_t* seed_arr,\n uint64_t seed_val, uint64_t* offset_arr,\n uint64_t offset_val) {\n const uint32_t batch_size = gridDim.x;\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curandStatePhilox4_32_10_t state;\n curand_init(philox_seed, bx, philox_offset, &state);\n const uint32_t row_idx = indices == nullptr ? bx : indices[bx];\n const uint32_t k = top_k_arr == nullptr ? top_k_val : top_k_arr[row_idx];\n const float p = top_p_arr == nullptr ? top_p_val : top_p_arr[row_idx];\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n vec_t<float, VEC_SIZE> probs_vec;\n float aggregate;\n float q = 1;\n double low = 0, high = 1.f;\n int sampled_id;\n do {\n temp_storage.sampled_id = d;\n __syncthreads();\n float u = curand_uniform(&state) * q;\n aggregate = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x > low; }, u, probs_vec, aggregate, &temp_storage);\n if (aggregate > u) {\n break;\n }\n }\n __syncthreads();\n sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n double pivot_0 = probs[row_idx * d + sampled_id];\n double pivot_1 = (pivot_0 + high) / 2;\n\n ValueCount<float> aggregate_gt_pivot_0{0, 0}, aggregate_gt_pivot_1{0, 0};\n ValueCount<float> threadlocal_aggregate_gt_pivot_0{0, 0};\n ValueCount<float> threadlocal_aggregate_gt_pivot_1{0, 0};\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + (i * BLOCK_THREADS + tx) * VEC_SIZE);\n }\n\n ValueCount<float> probs_gt_pivot_0[VEC_SIZE], probs_gt_pivot_1[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot_0[j] = {\n (probs_vec[j] > pivot_0) ? probs_vec[j] : 0,\n (probs_vec[j] > pivot_0 && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d)};\n probs_gt_pivot_1[j] = {\n (probs_vec[j] > pivot_1) ? probs_vec[j] : 0,\n (probs_vec[j] > pivot_1 && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d)};\n threadlocal_aggregate_gt_pivot_0 += probs_gt_pivot_0[j];\n threadlocal_aggregate_gt_pivot_1 += probs_gt_pivot_1[j];\n }\n }\n aggregate_gt_pivot_0 +=\n BlockReduce<ValueCount<float>, BLOCK_THREADS>(temp_storage.block_prim.reduce_value_count)\n .Sum(threadlocal_aggregate_gt_pivot_0);\n if (tx == 0) {\n temp_storage.block_aggregate.pair = aggregate_gt_pivot_0;\n }\n __syncthreads();\n aggregate_gt_pivot_0 = temp_storage.block_aggregate.pair;\n\n aggregate_gt_pivot_1 +=\n BlockReduce<ValueCount<float>, BLOCK_THREADS>(temp_storage.block_prim.reduce_value_count)\n .Sum(threadlocal_aggregate_gt_pivot_1);\n if (tx == 0) {\n temp_storage.block_aggregate.pair = aggregate_gt_pivot_1;\n }\n __syncthreads();\n aggregate_gt_pivot_1 = temp_storage.block_aggregate.pair;\n if (aggregate_gt_pivot_0.count < k && aggregate_gt_pivot_0.value < p) {\n // case 1: pivot_0 accepted\n break;\n }\n if (aggregate_gt_pivot_1.count < k && aggregate_gt_pivot_1.value < p) {\n // case 2: pivot_0 rejected, pivot_1 accepted\n low = pivot_0;\n high = pivot_1;\n q = aggregate_gt_pivot_0.value;\n } else {\n // case 3: pivot_0 rejected, pivot_1 rejected\n low = pivot_1;\n q = aggregate_gt_pivot_1.value;\n }\n } while (low < high);\n __syncthreads();\n if (tx == 0) {\n output[bx] = sampled_id;\n }\n}\n\ntemplate <typename DType>\ncudaError_t OnlineSoftmax(DType* logits, DType* output, uint32_t batch_size, uint32_t d,\n DType* temperature_arr, DType temperature_val, void* workspace_buffer,\n size_t workspace_buffer_size_in_bytes, bool enable_pdl,\n cudaStream_t stream = 0) {\n constexpr uint32_t SMALL_BATCH_THRESHOLD = 128;\n constexpr uint32_t LARGE_VOCAB_THRESHOLD = 24576;\n constexpr uint32_t DEFAULT_SLICE_SIZE = 8192;\n\n const uint32_t vec_size = std::gcd(16 / sizeof(DType), d);\n auto compute_capacity = GetCudaComputeCapability();\n\n DISPATCH_COMPUTE_CAP_NUM_THREADS(\n compute_capacity, BLOCK_THREADS, {DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n if (batch_size <= SMALL_BATCH_THRESHOLD && d >= LARGE_VOCAB_THRESHOLD) {\n // Path A: Vocab-Splitting Strategy for small-batch & large-vocab\n uint32_t num_slices = ceil_div(d, DEFAULT_SLICE_SIZE);\n\n const size_t partial_buffer_size = batch_size * num_slices * sizeof(PartialSoftmaxResult);\n if (workspace_buffer_size_in_bytes < partial_buffer_size) {\n return cudaErrorInvalidValue;\n }\n\n AlignedAllocator allocator(workspace_buffer, workspace_buffer_size_in_bytes);\n auto partial_results = allocator.aligned_alloc<PartialSoftmaxResult>(\n partial_buffer_size, alignof(PartialSoftmaxResult), \"softmax_workspace\");\n\n // Phase 1: Map-Reduce across vocab slices\n dim3 phase1_nblks(batch_size, num_slices);\n dim3 phase1_nthrs(BLOCK_THREADS);\n size_t smem_size = sizeof(OnlineSoftmaxTempStorage<BLOCK_THREADS>);\n\n auto phase1_kernel = OnlineSoftmaxMapKernel<BLOCK_THREADS, VEC_SIZE, DType>;\n void* phase1_args[] = {&logits, &partial_results, &temperature_arr, &temperature_val,\n &d, &num_slices};\n\n FLASHINFER_CUDA_CALL(cudaFuncSetAttribute(\n phase1_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n if (enable_pdl) {\n cudaLaunchAttribute attribute[1];\n attribute[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attribute[0].val.programmaticStreamSerializationAllowed = 1;\n\n cudaLaunchConfig_t config;\n config.gridDim = phase1_nblks;\n config.blockDim = phase1_nthrs;\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attribute;\n config.numAttrs = 1;\n\n FLASHINFER_CUDA_CALL(cudaLaunchKernelEx(&config, phase1_kernel, logits, partial_results,\n temperature_arr, temperature_val, d,\n num_slices));\n } else {\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)phase1_kernel, phase1_nblks, phase1_nthrs,\n phase1_args, smem_size, stream));\n }\n\n // Phase 2: Final reduction and apply normalization\n dim3 phase2_nblks(batch_size);\n dim3 phase2_nthrs(BLOCK_THREADS);\n\n auto phase2_kernel = OnlineSoftmaxReduceKernel<BLOCK_THREADS, VEC_SIZE, DType>;\n void* phase2_args[] = {&logits, &output, &partial_results, &temperature_arr,\n &temperature_val, &d, &num_slices};\n\n FLASHINFER_CUDA_CALL(cudaFuncSetAttribute(\n phase2_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n if (enable_pdl) {\n cudaLaunchAttribute attribute[1];\n attribute[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attribute[0].val.programmaticStreamSerializationAllowed = 1;\n\n cudaLaunchConfig_t config;\n config.gridDim = phase2_nblks;\n config.blockDim = phase2_nthrs;\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attribute;\n config.numAttrs = 1;\n\n FLASHINFER_CUDA_CALL(cudaLaunchKernelEx(&config, phase2_kernel, logits, output,\n partial_results, temperature_arr,\n temperature_val, d, num_slices));\n } else {\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)phase2_kernel, phase2_nblks, phase2_nthrs,\n phase2_args, smem_size, stream));\n }\n } else {\n // Path B: Single-Block Strategy\n // Switch input cache\n uint32_t cache_threshold;\n if (batch_size <= 16) {\n cache_threshold = 4096;\n } else if (batch_size <= 32) {\n cache_threshold = 2048;\n } else {\n cache_threshold = 0;\n }\n const bool cache_input = d <= cache_threshold;\n\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&logits, &output, &temperature_arr, &temperature_val, &d};\n\n const size_t smem_logits_bytes = (round_up(d, VEC_SIZE) + VEC_SIZE) * sizeof(DType);\n\n uint32_t smem_size = sizeof(OnlineSoftmaxTempStorage<BLOCK_THREADS>) +\n (cache_input ? smem_logits_bytes : 0);\n\n DISPATCH_SOFTMAX_CACHE_INPUT(cache_input, CACHE_INPUT, {\n auto kernel = OnlineSoftmaxFusedKernel<BLOCK_THREADS, VEC_SIZE, DType, CACHE_INPUT>;\n FLASHINFER_CUDA_CALL(cudaFuncSetAttribute(\n kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n if (enable_pdl) {\n cudaLaunchAttribute attribute[1];\n attribute[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attribute[0].val.programmaticStreamSerializationAllowed = 1;\n\n cudaLaunchConfig_t config;\n config.gridDim = nblks;\n config.blockDim = nthrs;\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n config.attrs = attribute;\n config.numAttrs = 1;\n\n FLASHINFER_CUDA_CALL(cudaLaunchKernelEx(&config, kernel, logits, output,\n temperature_arr, temperature_val, d));\n } else {\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n }\n });\n }\n })});\n return cudaSuccess;\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t SamplingFromLogits(T* logits, IdType* output, IdType* indices, uint32_t batch_size,\n uint32_t d, bool deterministic, uint64_t* seed_arr,\n uint64_t seed_val, uint64_t* offset_arr, uint64_t offset_val,\n cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&logits, &output, &indices, &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n const uint32_t smem_size = sizeof(\n typename BlockReduce<DataAndIndex<T, IdType>, BLOCK_THREADS, REDUCE_ALGO>::TempStorage);\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = SamplingFromLogitsKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t SamplingFromProb(T* probs, IdType* output, IdType* indices, uint32_t batch_size,\n uint32_t d, bool deterministic, uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &output, &indices, &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = SamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t TopKSamplingFromProb(T* probs, IdType* output, IdType* indices, T* top_k_arr,\n uint32_t batch_size, uint32_t top_k_val, uint32_t d,\n bool deterministic, uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val,\n cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &output, &indices, &top_k_arr, &top_k_val,\n &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = TopKSamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t TopPSamplingFromProb(T* probs, IdType* output, IdType* indices, T* top_p_arr,\n uint32_t batch_size, T top_p_val, uint32_t d, bool deterministic,\n uint64_t* seed_arr, uint64_t seed_val, uint64_t* offset_arr,\n uint64_t offset_val, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &output, &indices, &top_p_arr, &top_p_val,\n &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = TopPSamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t MinPSamplingFromProb(T* probs, T* min_p_arr, IdType* output, IdType* indices,\n uint32_t batch_size, float min_p_val, uint32_t d,\n bool deterministic, uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val,\n cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &min_p_arr, &output, &indices, &min_p_val,\n &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = MinPSamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <typename T, typename IdType>\ncudaError_t TopKTopPSamplingFromProb(T* probs, IdType* top_k_arr, T* top_p_arr, IdType* output,\n IdType* indices, uint32_t batch_size, IdType top_k_val,\n T top_p_val, uint32_t d, bool deterministic,\n uint64_t* seed_arr, uint64_t seed_val, uint64_t* offset_arr,\n uint64_t offset_val, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(T), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &top_k_arr, &top_p_arr, &output, &indices, &top_k_val,\n &top_p_val, &d, &seed_arr, &seed_val, &offset_arr, &offset_val};\n\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = TopKTopPSamplingFromProbKernel<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO,\n VEC_SIZE, DETERMINISTIC, T, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockReduceAlgorithm REDUCE_ALGORITHM>\nstruct RenormTempStorage {\n union {\n typename BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage reduce;\n typename BlockReduce<int, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage reduce_int;\n typename BlockReduce<ValueCount<float>, BLOCK_THREADS, REDUCE_ALGORITHM>::TempStorage\n reduce_value_count;\n } block_prim;\n struct {\n float max_val;\n float min_val;\n float row_sum;\n union {\n struct {\n float values[2];\n };\n struct {\n int counts[2];\n };\n struct {\n ValueCount<float> pairs[2];\n };\n } block_aggregate;\n };\n};\n\ntemplate <uint32_t BLOCK_THREADS, BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE,\n typename DType>\n__global__ void TopPRenormProbKernel(DType* probs, DType* renormed_prob, float* top_p_arr,\n float top_p_val, uint32_t d) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n const uint32_t row_idx = bx;\n float p = top_p_arr == nullptr ? top_p_val : top_p_arr[bx];\n\n extern __shared__ __align__(alignof(RenormTempStorage<BLOCK_THREADS, REDUCE_ALGO>))\n uint8_t smem_renorm[];\n auto& temp_storage =\n reinterpret_cast<RenormTempStorage<BLOCK_THREADS, REDUCE_ALGO>&>(smem_renorm);\n vec_t<float, VEC_SIZE> probs_vec;\n\n // Fast-path: when p >= 1.0 (e.g., p == 1.0), perform simple sum and normalization\n if (p >= 1.0f) {\n // Stage A: per-thread float accumulation over assigned lanes (vectorized)\n float thread_sum = 0.0f;\n const uint32_t num_iters = ceil_div(d, BLOCK_THREADS * VEC_SIZE);\n for (uint32_t i = 0; i < num_iters; ++i) {\n probs_vec.fill(0.0f);\n const uint32_t base_idx = (i * BLOCK_THREADS + tx) * VEC_SIZE;\n if (base_idx < d) {\n probs_vec.cast_load(probs + row_idx * d + base_idx);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n const uint32_t idx = base_idx + j;\n if (idx < d) thread_sum += probs_vec[j];\n }\n }\n\n // Block reduce (float)\n float row_sum =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Sum(thread_sum);\n // Broadcast via shared\n if (tx == 0) temp_storage.row_sum = row_sum;\n __syncthreads();\n row_sum = temp_storage.row_sum;\n\n // Guard against zero sum\n const float denom = (row_sum <= 1e-8f) ? 1.0f : row_sum;\n const float normalizer = math::ptx_rcp(denom);\n\n // Stage B: normalize and store\n for (uint32_t i = 0; i < num_iters; ++i) {\n probs_vec.fill(0.0f);\n const uint32_t base_idx = (i * BLOCK_THREADS + tx) * VEC_SIZE;\n if (base_idx < d) {\n probs_vec.cast_load(probs + row_idx * d + base_idx);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n const uint32_t idx = base_idx + j;\n float v = probs_vec[j];\n probs_vec[j] = (idx < d) ? (v * normalizer) : 0.0f;\n }\n if (base_idx < d) {\n probs_vec.cast_store(renormed_prob + row_idx * d + base_idx);\n }\n }\n return; // Exit after fast-path processing\n }\n\n // Original Top-P renormalization logic\n temp_storage.max_val = 0;\n float max_val = GetMaxValue<VEC_SIZE, BLOCK_THREADS, REDUCE_ALGORITHM,\n RenormTempStorage<BLOCK_THREADS, REDUCE_ALGORITHM>>(probs, row_idx, d,\n temp_storage);\n\n double low = 0, high = max_val;\n float min_gt_low, max_le_high;\n float sum_low = 1;\n // f(x) = sum(probs[probs > x]), f(x) is non-increasing\n // min_gt_low = min{p \\in probs | p > low}, max_le_high = max{p \\in probs | p <= high}\n // loop invariant:\n // - f(low) >= p, f(high) < p\n // - f(low) > f(min_gt_low) >= f(max_le_high) == f(high)\n // stopping condition\n // - f(low) >= p, f(min_gt_low) == f(max_le_high) == f(high) < p\n do {\n double pivot_0 = (high + 2 * low) / 3;\n double pivot_1 = (2 * high + low) / 3;\n\n float aggregate_gt_pivot_0 = 0, aggregate_gt_pivot_1 = 0;\n min_gt_low = high;\n max_le_high = low;\n float threadlocal_aggregate_gt_pivot_0 = 0;\n float threadlocal_aggregate_gt_pivot_1 = 0;\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n\n float probs_gt_pivot_0[VEC_SIZE], probs_gt_pivot_1[VEC_SIZE];\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_gt_pivot_0[j] = (probs_vec[j] > pivot_0) ? probs_vec[j] : 0;\n probs_gt_pivot_1[j] = (probs_vec[j] > pivot_1) ? probs_vec[j] : 0;\n\n if (probs_vec[j] > low && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d) {\n min_gt_low = min(min_gt_low, probs_vec[j]);\n }\n if (probs_vec[j] <= high && (i * BLOCK_THREADS + tx) * VEC_SIZE + j < d) {\n max_le_high = max(max_le_high, probs_vec[j]);\n }\n threadlocal_aggregate_gt_pivot_0 += probs_gt_pivot_0[j];\n threadlocal_aggregate_gt_pivot_1 += probs_gt_pivot_1[j];\n }\n }\n aggregate_gt_pivot_0 =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot_0);\n __syncthreads();\n aggregate_gt_pivot_1 =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Sum(threadlocal_aggregate_gt_pivot_1);\n __syncthreads();\n\n min_gt_low = BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Reduce(min_gt_low, MinReduceOp{});\n __syncthreads();\n max_le_high =\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Reduce(max_le_high, MaxReduceOp{});\n if (tx == 0) {\n temp_storage.block_aggregate.values[0] = aggregate_gt_pivot_0;\n temp_storage.block_aggregate.values[1] = aggregate_gt_pivot_1;\n temp_storage.min_val = min_gt_low;\n temp_storage.max_val = max_le_high;\n }\n __syncthreads();\n aggregate_gt_pivot_0 = temp_storage.block_aggregate.values[0];\n aggregate_gt_pivot_1 = temp_storage.block_aggregate.values[1];\n min_gt_low = temp_storage.min_val;\n max_le_high = temp_storage.max_val;\n\n if (aggregate_gt_pivot_1 >= p) {\n low = pivot_1;\n sum_low = aggregate_gt_pivot_1;\n } else if (aggregate_gt_pivot_0 >= p) {\n low = pivot_0;\n high = min(pivot_1, max_le_high);\n sum_low = aggregate_gt_pivot_0;\n } else {\n high = min(pivot_0, max_le_high);\n }\n } while (min_gt_low != max_le_high);\n\n float normalizer = math::ptx_rcp(max(sum_low, 1e-8));\n\n // normalize\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n probs_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_load(probs + row_idx * d + i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n probs_vec[j] = (probs_vec[j] > low) ? probs_vec[j] * normalizer : 0;\n }\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n probs_vec.cast_store(renormed_prob + row_idx * d + i * BLOCK_THREADS * VEC_SIZE +\n tx * VEC_SIZE);\n }\n }\n}\n\ntemplate <typename DType>\ncudaError_t TopPRenormProb(DType* probs, DType* renormed_prob, float* top_p_arr,\n uint32_t batch_size, float top_p_val, uint32_t d,\n cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(DType), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(RenormTempStorage<BLOCK_THREADS, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&probs, &renormed_prob, &top_p_arr, &top_p_val, &d};\n DISPATCH_ALIGNED_VEC_SIZE(vec_size, VEC_SIZE, {\n auto kernel = TopPRenormProbKernel<BLOCK_THREADS, REDUCE_ALGO, VEC_SIZE, DType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n });\n return cudaSuccess;\n });\n}\n\ntemplate <uint32_t BLOCK_THREADS, BlockScanAlgorithm SCAN_ALGORITHM,\n BlockReduceAlgorithm REDUCE_ALGORITHM, uint32_t VEC_SIZE, bool DETERMINISTIC,\n typename DType, typename IdType>\n__global__ void ChainSpeculativeSampling(DType* draft_probs, IdType* draft_token_ids,\n DType* target_probs, IdType* output_token_ids,\n IdType* output_accepted_token_num,\n IdType* output_emitted_draft_token_num,\n uint32_t num_speculative_tokens, uint32_t d,\n uint64_t* seed_arr, uint64_t seed_val,\n uint64_t* offset_arr, uint64_t offset_val) {\n const uint32_t bx = blockIdx.x, tx = threadIdx.x;\n const uint32_t row_idx = bx;\n\n // Resolve seed/offset from tensor or scalar\n uint64_t philox_seed = seed_arr ? seed_arr[0] : seed_val;\n uint64_t philox_offset = offset_arr ? offset_arr[0] : offset_val;\n\n curandStatePhilox4_32_10_t curand_state;\n curand_init(philox_seed, bx, philox_offset, &curand_state);\n\n extern __shared__ __align__(\n alignof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>))\n uint8_t smem_sampling[];\n auto& temp_storage =\n reinterpret_cast<SamplingTempStorage<BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM>&>(\n smem_sampling);\n\n uint32_t pos = num_speculative_tokens;\n for (uint32_t i = 0; i < num_speculative_tokens; ++i) {\n IdType draft_id = draft_token_ids[row_idx * num_speculative_tokens + i];\n float q = target_probs[(row_idx * (num_speculative_tokens + 1) + i) * d + draft_id],\n p = draft_probs[(row_idx * num_speculative_tokens + i) * d + draft_id];\n float u = curand_uniform(&curand_state);\n if (u * p < q) {\n // accept the draft models output\n output_token_ids[row_idx * (num_speculative_tokens + 1) + i] = draft_id;\n } else {\n pos = i;\n break;\n }\n }\n\n uint32_t emitted_token_num = pos;\n uint32_t accepted_token_num = pos;\n for (uint32_t i = pos; i < num_speculative_tokens; ++i) {\n int draft_id = draft_token_ids[row_idx * num_speculative_tokens + i];\n float q = target_probs[(row_idx * (num_speculative_tokens + 1) + i) * d + draft_id],\n p = draft_probs[(row_idx * num_speculative_tokens + i) * d + draft_id];\n float u = curand_uniform(&curand_state);\n if (u * p < q) {\n ++accepted_token_num;\n }\n }\n\n if (tx == 0) {\n output_accepted_token_num[row_idx] += accepted_token_num;\n output_emitted_draft_token_num[row_idx] += emitted_token_num;\n }\n\n // sample from relu(target_probs - draft_probs)\n float sum_relu_q_minus_p = 0;\n vec_t<float, VEC_SIZE> q_vec, p_vec;\n float relu_q_minus_p[VEC_SIZE];\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n q_vec.fill(0);\n p_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n q_vec.cast_load(target_probs + (row_idx * (num_speculative_tokens + 1) + pos) * d +\n i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n if (pos != num_speculative_tokens) {\n // there is no draft_probs for the bonus token\n p_vec.cast_load(draft_probs + (row_idx * num_speculative_tokens + pos) * d +\n i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n }\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n relu_q_minus_p[j] = max(q_vec[j] - p_vec[j], 0.0f);\n }\n sum_relu_q_minus_p +=\n BlockReduce<float, BLOCK_THREADS, REDUCE_ALGORITHM>(temp_storage.block_prim.reduce)\n .Sum<VEC_SIZE>(relu_q_minus_p);\n __syncthreads();\n }\n if (tx == 0) {\n temp_storage.block_aggregate.value = sum_relu_q_minus_p;\n }\n // init the first rejected token to d\n temp_storage.sampled_id = d;\n __syncthreads();\n sum_relu_q_minus_p = temp_storage.block_aggregate.value;\n float u = curand_uniform(&curand_state) * sum_relu_q_minus_p;\n\n float aggregate_relu_q_minus_p(0);\n#pragma unroll 2\n for (uint32_t i = 0; i < ceil_div(d, BLOCK_THREADS * VEC_SIZE); ++i) {\n q_vec.fill(0);\n p_vec.fill(0);\n if ((i * BLOCK_THREADS + tx) * VEC_SIZE < d) {\n q_vec.cast_load(target_probs + (row_idx * (num_speculative_tokens + 1) + pos) * d +\n i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n if (pos != num_speculative_tokens) {\n // there is no draft_probs for the bonus token\n p_vec.cast_load(draft_probs + (row_idx * num_speculative_tokens + pos) * d +\n i * BLOCK_THREADS * VEC_SIZE + tx * VEC_SIZE);\n }\n }\n\n vec_t<float, VEC_SIZE> relu_q_minus_p_vec;\n#pragma unroll\n for (uint32_t j = 0; j < VEC_SIZE; ++j) {\n relu_q_minus_p_vec[j] = max(q_vec[j] - p_vec[j], 0.0f);\n }\n\n DeviceSamplingFromProb<VEC_SIZE, BLOCK_THREADS, SCAN_ALGORITHM, REDUCE_ALGORITHM,\n DETERMINISTIC>(\n i, d, [&](float x) { return x > 0; }, u, relu_q_minus_p_vec, aggregate_relu_q_minus_p,\n &temp_storage);\n if (aggregate_relu_q_minus_p > u) {\n break;\n }\n }\n __syncthreads();\n int sampled_id = temp_storage.sampled_id;\n if (sampled_id == d) {\n // NOTE(Zihao): this would happen when u is very close to 1\n // and the sum of probabilities is smaller than u\n // In this case, we use the last valid index as the sampled id\n sampled_id = temp_storage.last_valid_id;\n }\n // set the first rejected token\n output_token_ids[row_idx * (num_speculative_tokens + 1) + pos] = sampled_id;\n // move to the next token\n pos++;\n\n // pad remaining tokens with -1\n for (; pos < num_speculative_tokens + 1; ++pos) {\n output_token_ids[row_idx * (num_speculative_tokens + 1) + pos] = -1;\n }\n}\n\ntemplate <typename DType, typename IdType>\ncudaError_t ChainSpeculativeSampling(\n DType* draft_probs, IdType* draft_token_ids, DType* target_probs, IdType* output_token_ids,\n IdType* output_accepted_token_num, IdType* output_emitted_draft_token_num, uint32_t batch_size,\n uint32_t num_speculative_tokens, uint32_t d, bool deterministic, uint64_t* seed_arr,\n uint64_t seed_val, uint64_t* offset_arr, uint64_t offset_val, cudaStream_t stream = 0) {\n const uint32_t vec_size = std::gcd(16 / sizeof(DType), d);\n\n auto compute_capacity = GetCudaComputeCapability();\n DISPATCH_COMPUTE_CAP_NUM_THREADS(compute_capacity, BLOCK_THREADS, {\n const uint32_t smem_size = sizeof(SamplingTempStorage<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO>);\n dim3 nblks(batch_size);\n dim3 nthrs(BLOCK_THREADS);\n void* args[] = {&draft_probs,\n &draft_token_ids,\n &target_probs,\n &output_token_ids,\n &output_accepted_token_num,\n &output_emitted_draft_token_num,\n &num_speculative_tokens,\n &d,\n &seed_arr,\n &seed_val,\n &offset_arr,\n &offset_val};\n DISPATCH_ALIGNED_VEC_SIZE(\n vec_size, VEC_SIZE, {DISPATCH_DETERMINISTIC(deterministic, DETERMINISTIC, {\n auto kernel = ChainSpeculativeSampling<BLOCK_THREADS, SCAN_ALGO, REDUCE_ALGO, VEC_SIZE,\n DETERMINISTIC, DType, IdType>;\n FLASHINFER_CUDA_CALL(\n cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernel((void*)kernel, nblks, nthrs, args, smem_size, stream));\n })});\n return cudaSuccess;\n });\n}\n\n} // namespace sampling\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_SAMPLING_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Summary\nResolved the TODO comment in `sampling.cuh` regarding `log2f` vs `logf` performance comparison.\n\n## Changes\n- Removed `// TODO: compare the speed of log2 and log`\n- Added documentation explaining why `log2f` is preferred:\n - `log2f` maps to a single PTX `LG2` instruction on NVIDIA GPUs\n - `logf` internally computes `log2f * ln(2)`, requiring an extra multiply\n - Current approach (3 ops) is more efficient than the `logf` alternative (4 ops)\n- Fixed `#pragma unroll` indentation to match surrounding code style\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n\n## Summary by CodeRabbit\n\n* **Chores**\n * Minor code improvements and formatting adjustments to internal sampling implementation.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1179,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"30bf78e1a05d18aaebd484aa6f3c1db8e4c0b1b4"},"date":{"kind":"string","value":"2026-02-10T06:38:50+08:00"},"pr_number":{"kind":"number","value":2509,"string":"2,509"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2509"},"title":{"kind":"string","value":"perf: cache cudaGetDeviceProperties in gdn_prefill to avoid per-call overhead (#2509)"},"message":{"kind":"string","value":"perf: cache cudaGetDeviceProperties in gdn_prefill to avoid per-call overhead (#2509)\n\n## Summary\n- Cache `device_properties.major` and\n`device_properties.multiProcessorCount` using\n`static thread_local` variables in `gdn_prefill_launcher()` and\n`gdn_prefill()`\nrespectively, instead of calling `cudaGetDeviceProperties` on every\ninvocation.\n- Each `cudaGetDeviceProperties` call adds ~1ms of synchronous CPU\noverhead, which\naccumulates to ~72ms across 36 GDN layers during prefill. This change\neliminates\n that repeated overhead.\n## Changes\n- **`csrc/gdn_prefill_launcher.cu`**: Replace per-call\n`cudaGetDeviceProperties` with\n`static thread_local` cached values for `device_major` (used for SM\narchitecture\n dispatch) and `sm_count` (used for kernel launch configuration).\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **Refactor**\n* Streamlined GPU device attribute retrieval mechanisms for accessing\ncompute capability and processor information.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"csrc/gdn_prefill_launcher.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#include <flashinfer/allocator.h>\n#include <flashinfer/exception.h>\n#include <tvm_ffi_utils.h>\n\n#include <algorithm>\n#include <cmath>\n#include <iostream>\n#include <sstream>\n\n#include \"flashinfer/flat/prefill/prefill_kernel.hpp\"\n\nusing tvm::ffi::Optional;\nusing tvm::ffi::TensorView;\nusing tvm::ffi::Variant;\n\nnamespace flashinfer {\n\nvoid gdn_prefill_launcher(void* output, void* output_state, void* q, void* k, void* v,\n void* input_state, void* alpha, void* beta, int64_t* cu_seqlens,\n uint8_t* workspace_buffer, int64_t num_seqs, int64_t num_q_heads,\n int64_t num_k_heads, int64_t num_v_heads, int64_t num_o_heads,\n int64_t head_size, int64_t packed_seq, float scale, int64_t sm_count,\n DLDataType dtype, cudaStream_t stream) {\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP16(dtype, DType, [&] {\n int dev_id;\n cudaGetDevice(&dev_id);\n cudaDeviceProp device_properties;\n cudaGetDeviceProperties(&device_properties, dev_id);\n\n#if defined(FLAT_SM90A_ENABLED)\n if (device_properties.major == 9) {\n flat::launch_delta_rule_prefill_kernel<cutlass::arch::Sm90, DType, DType, float>(\n stream, static_cast<DType*>(output), static_cast<float*>(output_state),\n static_cast<DType const*>(q), static_cast<DType const*>(k), static_cast<DType const*>(v),\n static_cast<float const*>(input_state), static_cast<float const*>(alpha),\n static_cast<float const*>(beta), cu_seqlens, workspace_buffer, num_seqs, num_q_heads,\n num_k_heads, num_v_heads, num_o_heads, head_size, packed_seq, scale, sm_count);\n return true;\n } else {\n std::ostringstream err_msg;\n err_msg << \"delta rule kernel does not support this device major version: \"\n << device_properties.major;\n FLASHINFER_ERROR(err_msg.str());\n return false;\n }\n#else\n FLASHINFER_ERROR(\"sm_90a is not enabled, delta rule kernel is not built\");\n return false;\n#endif\n });\n}\n\nvoid gdn_prefill(TensorView output, TensorView output_state, TensorView q, TensorView k,\n TensorView v, TensorView cu_seqlens, Optional<TensorView> input_state,\n Optional<TensorView> alpha, Optional<TensorView> beta, double scale,\n TensorView workspace_buffer) {\n int64_t num_seqs = cu_seqlens.size(0) - 1;\n int64_t packed_seq = q.size(0);\n int64_t head_size = q.size(2);\n int64_t num_q_heads = q.size(1);\n int64_t num_k_heads = k.size(1);\n int64_t num_v_heads = v.size(1);\n\n // NOTE: Qwen3-next alpha and beta heads are 32, equal to v heads, we limit it to larger one\n int32_t num_sab_heads = std::max(num_q_heads, num_v_heads);\n\n if (num_q_heads >= num_v_heads) { // GQA\n auto ratio = num_q_heads / num_v_heads;\n TVM_FFI_ICHECK_EQ(num_k_heads, num_v_heads);\n TVM_FFI_ICHECK_EQ(num_q_heads, ratio * num_k_heads);\n TVM_FFI_ICHECK_EQ(num_q_heads, ratio * num_v_heads);\n } else { // GVA\n auto ratio = num_v_heads / num_q_heads;\n TVM_FFI_ICHECK_EQ(num_q_heads, num_k_heads);\n TVM_FFI_ICHECK_EQ(num_v_heads, ratio * num_q_heads);\n TVM_FFI_ICHECK_EQ(num_v_heads, ratio * num_k_heads);\n }\n\n int64_t num_o_heads = output.size(1);\n TVM_FFI_ICHECK_EQ(num_o_heads, num_sab_heads);\n\n void* input_state_ptr = nullptr;\n if (input_state.has_value()) {\n CHECK_SHAPE(input_state.value(), output_state);\n TVM_FFI_ICHECK_EQ(input_state.value().dtype(), dl_float32);\n input_state_ptr = input_state.value().data_ptr();\n }\n\n CHECK_INPUT(output);\n CHECK_INPUT(output_state);\n CHECK_INPUT(q);\n CHECK_INPUT(k);\n CHECK_INPUT(v);\n CHECK_INPUT(cu_seqlens);\n CHECK_INPUT(workspace_buffer);\n\n TVM_FFI_ICHECK(output.dtype() == dl_float16 || output.dtype() == dl_bfloat16);\n TVM_FFI_ICHECK_EQ(output_state.dtype(), dl_float32);\n TVM_FFI_ICHECK_EQ(output.dtype(), q.dtype());\n TVM_FFI_ICHECK_EQ(output.dtype(), k.dtype());\n TVM_FFI_ICHECK_EQ(output.dtype(), v.dtype());\n TVM_FFI_ICHECK_EQ(cu_seqlens.dtype(), dl_int64);\n TVM_FFI_ICHECK_EQ(workspace_buffer.dtype(), dl_uint8);\n\n TVM_FFI_ICHECK_EQ(packed_seq, k.size(0));\n TVM_FFI_ICHECK_EQ(packed_seq, v.size(0));\n TVM_FFI_ICHECK_EQ(packed_seq, output.size(0));\n\n TVM_FFI_ICHECK_EQ(num_seqs, output_state.size(0));\n TVM_FFI_ICHECK_EQ(num_sab_heads, output_state.size(1));\n\n TVM_FFI_ICHECK_EQ(head_size, output.size(2));\n TVM_FFI_ICHECK_EQ(head_size, k.size(2));\n TVM_FFI_ICHECK_EQ(head_size, v.size(2));\n TVM_FFI_ICHECK_EQ(head_size, output_state.size(2));\n TVM_FFI_ICHECK_EQ(head_size, output_state.size(3));\n\n void* alpha_ptr = nullptr;\n if (alpha.has_value()) {\n TensorView alpha_tensor = alpha.value();\n TVM_FFI_ICHECK_EQ(alpha_tensor.dtype(), dl_float32);\n TVM_FFI_ICHECK_EQ(alpha_tensor.size(0), packed_seq);\n TVM_FFI_ICHECK_EQ(alpha_tensor.size(1), num_sab_heads);\n CHECK_INPUT(alpha_tensor);\n alpha_ptr = alpha_tensor.data_ptr();\n }\n\n void* beta_ptr = nullptr;\n if (beta.has_value()) {\n TensorView beta_tensor = beta.value();\n TVM_FFI_ICHECK_EQ(beta_tensor.dtype(), dl_float32);\n TVM_FFI_ICHECK_EQ(beta_tensor.size(0), packed_seq);\n TVM_FFI_ICHECK_EQ(beta_tensor.size(1), num_sab_heads);\n CHECK_INPUT(beta_tensor);\n beta_ptr = beta_tensor.data_ptr();\n }\n\n if (scale == 0.0) {\n scale = 1.0 / std::sqrt(head_size);\n }\n\n int dev_id;\n cudaGetDevice(&dev_id);\n cudaDeviceProp device_properties;\n cudaGetDeviceProperties(&device_properties, dev_id);\n int32_t sm_count = device_properties.multiProcessorCount;\n\n auto stream = get_stream(q.device());\n\n gdn_prefill_launcher(output.data_ptr(), output_state.data_ptr(), q.data_ptr(), k.data_ptr(),\n v.data_ptr(), input_state_ptr, alpha_ptr, beta_ptr,\n static_cast<int64_t*>(cu_seqlens.data_ptr()),\n static_cast<uint8_t*>(workspace_buffer.data_ptr()), num_seqs, num_q_heads,\n num_k_heads, num_v_heads, num_o_heads, head_size, packed_seq,\n static_cast<float>(scale), sm_count, q.dtype(), stream);\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(gdn_prefill, gdn_prefill);\n\n} // namespace flashinfer\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#include <flashinfer/allocator.h>\n#include <flashinfer/exception.h>\n#include <tvm_ffi_utils.h>\n\n#include <algorithm>\n#include <cmath>\n#include <iostream>\n#include <sstream>\n\n#include \"flashinfer/flat/prefill/prefill_kernel.hpp\"\n\nusing tvm::ffi::Optional;\nusing tvm::ffi::TensorView;\nusing tvm::ffi::Variant;\n\nnamespace flashinfer {\n\nvoid gdn_prefill_launcher(void* output, void* output_state, void* q, void* k, void* v,\n void* input_state, void* alpha, void* beta, int64_t* cu_seqlens,\n uint8_t* workspace_buffer, int64_t num_seqs, int64_t num_q_heads,\n int64_t num_k_heads, int64_t num_v_heads, int64_t num_o_heads,\n int64_t head_size, int64_t packed_seq, float scale, int64_t sm_count,\n DLDataType dtype, cudaStream_t stream) {\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP16(dtype, DType, [&] {\n int dev_id;\n cudaGetDevice(&dev_id);\n int device_major;\n cudaDeviceGetAttribute(&device_major, cudaDevAttrComputeCapabilityMajor, dev_id);\n\n#if defined(FLAT_SM90A_ENABLED)\n if (device_major == 9) {\n flat::launch_delta_rule_prefill_kernel<cutlass::arch::Sm90, DType, DType, float>(\n stream, static_cast<DType*>(output), static_cast<float*>(output_state),\n static_cast<DType const*>(q), static_cast<DType const*>(k), static_cast<DType const*>(v),\n static_cast<float const*>(input_state), static_cast<float const*>(alpha),\n static_cast<float const*>(beta), cu_seqlens, workspace_buffer, num_seqs, num_q_heads,\n num_k_heads, num_v_heads, num_o_heads, head_size, packed_seq, scale, sm_count);\n return true;\n } else {\n std::ostringstream err_msg;\n err_msg << \"delta rule kernel does not support this device major version: \" << device_major;\n FLASHINFER_ERROR(err_msg.str());\n return false;\n }\n#else\n FLASHINFER_ERROR(\"sm_90a is not enabled, delta rule kernel is not built\");\n return false;\n#endif\n });\n}\n\nvoid gdn_prefill(TensorView output, TensorView output_state, TensorView q, TensorView k,\n TensorView v, TensorView cu_seqlens, Optional<TensorView> input_state,\n Optional<TensorView> alpha, Optional<TensorView> beta, double scale,\n TensorView workspace_buffer) {\n int64_t num_seqs = cu_seqlens.size(0) - 1;\n int64_t packed_seq = q.size(0);\n int64_t head_size = q.size(2);\n int64_t num_q_heads = q.size(1);\n int64_t num_k_heads = k.size(1);\n int64_t num_v_heads = v.size(1);\n\n // NOTE: Qwen3-next alpha and beta heads are 32, equal to v heads, we limit it to larger one\n int32_t num_sab_heads = std::max(num_q_heads, num_v_heads);\n\n if (num_q_heads >= num_v_heads) { // GQA\n auto ratio = num_q_heads / num_v_heads;\n TVM_FFI_ICHECK_EQ(num_k_heads, num_v_heads);\n TVM_FFI_ICHECK_EQ(num_q_heads, ratio * num_k_heads);\n TVM_FFI_ICHECK_EQ(num_q_heads, ratio * num_v_heads);\n } else { // GVA\n auto ratio = num_v_heads / num_q_heads;\n TVM_FFI_ICHECK_EQ(num_q_heads, num_k_heads);\n TVM_FFI_ICHECK_EQ(num_v_heads, ratio * num_q_heads);\n TVM_FFI_ICHECK_EQ(num_v_heads, ratio * num_k_heads);\n }\n\n int64_t num_o_heads = output.size(1);\n TVM_FFI_ICHECK_EQ(num_o_heads, num_sab_heads);\n\n void* input_state_ptr = nullptr;\n if (input_state.has_value()) {\n CHECK_SHAPE(input_state.value(), output_state);\n TVM_FFI_ICHECK_EQ(input_state.value().dtype(), dl_float32);\n input_state_ptr = input_state.value().data_ptr();\n }\n\n CHECK_INPUT(output);\n CHECK_INPUT(output_state);\n CHECK_INPUT(q);\n CHECK_INPUT(k);\n CHECK_INPUT(v);\n CHECK_INPUT(cu_seqlens);\n CHECK_INPUT(workspace_buffer);\n\n TVM_FFI_ICHECK(output.dtype() == dl_float16 || output.dtype() == dl_bfloat16);\n TVM_FFI_ICHECK_EQ(output_state.dtype(), dl_float32);\n TVM_FFI_ICHECK_EQ(output.dtype(), q.dtype());\n TVM_FFI_ICHECK_EQ(output.dtype(), k.dtype());\n TVM_FFI_ICHECK_EQ(output.dtype(), v.dtype());\n TVM_FFI_ICHECK_EQ(cu_seqlens.dtype(), dl_int64);\n TVM_FFI_ICHECK_EQ(workspace_buffer.dtype(), dl_uint8);\n\n TVM_FFI_ICHECK_EQ(packed_seq, k.size(0));\n TVM_FFI_ICHECK_EQ(packed_seq, v.size(0));\n TVM_FFI_ICHECK_EQ(packed_seq, output.size(0));\n\n TVM_FFI_ICHECK_EQ(num_seqs, output_state.size(0));\n TVM_FFI_ICHECK_EQ(num_sab_heads, output_state.size(1));\n\n TVM_FFI_ICHECK_EQ(head_size, output.size(2));\n TVM_FFI_ICHECK_EQ(head_size, k.size(2));\n TVM_FFI_ICHECK_EQ(head_size, v.size(2));\n TVM_FFI_ICHECK_EQ(head_size, output_state.size(2));\n TVM_FFI_ICHECK_EQ(head_size, output_state.size(3));\n\n void* alpha_ptr = nullptr;\n if (alpha.has_value()) {\n TensorView alpha_tensor = alpha.value();\n TVM_FFI_ICHECK_EQ(alpha_tensor.dtype(), dl_float32);\n TVM_FFI_ICHECK_EQ(alpha_tensor.size(0), packed_seq);\n TVM_FFI_ICHECK_EQ(alpha_tensor.size(1), num_sab_heads);\n CHECK_INPUT(alpha_tensor);\n alpha_ptr = alpha_tensor.data_ptr();\n }\n\n void* beta_ptr = nullptr;\n if (beta.has_value()) {\n TensorView beta_tensor = beta.value();\n TVM_FFI_ICHECK_EQ(beta_tensor.dtype(), dl_float32);\n TVM_FFI_ICHECK_EQ(beta_tensor.size(0), packed_seq);\n TVM_FFI_ICHECK_EQ(beta_tensor.size(1), num_sab_heads);\n CHECK_INPUT(beta_tensor);\n beta_ptr = beta_tensor.data_ptr();\n }\n\n if (scale == 0.0) {\n scale = 1.0 / std::sqrt(head_size);\n }\n\n // Use cudaDeviceGetAttribute for sm_count (much faster than cudaGetDeviceProperties)\n int dev_id;\n cudaGetDevice(&dev_id);\n int sm_count;\n cudaDeviceGetAttribute(&sm_count, cudaDevAttrMultiProcessorCount, dev_id);\n\n auto stream = get_stream(q.device());\n\n gdn_prefill_launcher(output.data_ptr(), output_state.data_ptr(), q.data_ptr(), k.data_ptr(),\n v.data_ptr(), input_state_ptr, alpha_ptr, beta_ptr,\n static_cast<int64_t*>(cu_seqlens.data_ptr()),\n static_cast<uint8_t*>(workspace_buffer.data_ptr()), num_seqs, num_q_heads,\n num_k_heads, num_v_heads, num_o_heads, head_size, packed_seq,\n static_cast<float>(scale), sm_count, q.dtype(), stream);\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(gdn_prefill, gdn_prefill);\n\n} // namespace flashinfer\n"},"diff":{"kind":"string","value":"--- csrc/gdn_prefill_launcher.cu\n+++ csrc/gdn_prefill_launcher.cu\n@@ -42,11 +42,11 @@\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP16(dtype, DType, [&] {\n int dev_id;\n cudaGetDevice(&dev_id);\n- cudaDeviceProp device_properties;\n- cudaGetDeviceProperties(&device_properties, dev_id);\n+ int device_major;\n+ cudaDeviceGetAttribute(&device_major, cudaDevAttrComputeCapabilityMajor, dev_id);\n \n #if defined(FLAT_SM90A_ENABLED)\n- if (device_properties.major == 9) {\n+ if (device_major == 9) {\n flat::launch_delta_rule_prefill_kernel<cutlass::arch::Sm90, DType, DType, float>(\n stream, static_cast<DType*>(output), static_cast<float*>(output_state),\n static_cast<DType const*>(q), static_cast<DType const*>(k), static_cast<DType const*>(v),\n@@ -56,8 +56,7 @@\n return true;\n } else {\n std::ostringstream err_msg;\n- err_msg << \"delta rule kernel does not support this device major version: \"\n- << device_properties.major;\n+ err_msg << \"delta rule kernel does not support this device major version: \" << device_major;\n FLASHINFER_ERROR(err_msg.str());\n return false;\n }\n@@ -157,11 +156,11 @@\n scale = 1.0 / std::sqrt(head_size);\n }\n \n+ // Use cudaDeviceGetAttribute for sm_count (much faster than cudaGetDeviceProperties)\n int dev_id;\n cudaGetDevice(&dev_id);\n- cudaDeviceProp device_properties;\n- cudaGetDeviceProperties(&device_properties, dev_id);\n- int32_t sm_count = device_properties.multiProcessorCount;\n+ int sm_count;\n+ cudaDeviceGetAttribute(&sm_count, cudaDevAttrMultiProcessorCount, dev_id);\n \n auto stream = get_stream(q.device());\n "},"lines_added":{"kind":"number","value":7,"string":"7"},"lines_removed":{"kind":"number","value":8,"string":"8"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["CPU"],"string":"[\n \"CPU\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/gdn_prefill_launcher.cu).\n\nGoal: perf: cache cudaGetDeviceProperties in gdn_prefill to avoid per-call overhead\nTarget hardware: CPU\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#include <flashinfer/allocator.h>\n#include <flashinfer/exception.h>\n#include <tvm_ffi_utils.h>\n\n#include <algorithm>\n#include <cmath>\n#include <iostream>\n#include <sstream>\n\n#include \"flashinfer/flat/prefill/prefill_kernel.hpp\"\n\nusing tvm::ffi::Optional;\nusing tvm::ffi::TensorView;\nusing tvm::ffi::Variant;\n\nnamespace flashinfer {\n\nvoid gdn_prefill_launcher(void* output, void* output_state, void* q, void* k, void* v,\n void* input_state, void* alpha, void* beta, int64_t* cu_seqlens,\n uint8_t* workspace_buffer, int64_t num_seqs, int64_t num_q_heads,\n int64_t num_k_heads, int64_t num_v_heads, int64_t num_o_heads,\n int64_t head_size, int64_t packed_seq, float scale, int64_t sm_count,\n DLDataType dtype, cudaStream_t stream) {\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP16(dtype, DType, [&] {\n int dev_id;\n cudaGetDevice(&dev_id);\n cudaDeviceProp device_properties;\n cudaGetDeviceProperties(&device_properties, dev_id);\n\n#if defined(FLAT_SM90A_ENABLED)\n if (device_properties.major == 9) {\n flat::launch_delta_rule_prefill_kernel<cutlass::arch::Sm90, DType, DType, float>(\n stream, static_cast<DType*>(output), static_cast<float*>(output_state),\n static_cast<DType const*>(q), static_cast<DType const*>(k), static_cast<DType const*>(v),\n static_cast<float const*>(input_state), static_cast<float const*>(alpha),\n static_cast<float const*>(beta), cu_seqlens, workspace_buffer, num_seqs, num_q_heads,\n num_k_heads, num_v_heads, num_o_heads, head_size, packed_seq, scale, sm_count);\n return true;\n } else {\n std::ostringstream err_msg;\n err_msg << \"delta rule kernel does not support this device major version: \"\n << device_properties.major;\n FLASHINFER_ERROR(err_msg.str());\n return false;\n }\n#else\n FLASHINFER_ERROR(\"sm_90a is not enabled, delta rule kernel is not built\");\n return false;\n#endif\n });\n}\n\nvoid gdn_prefill(TensorView output, TensorView output_state, TensorView q, TensorView k,\n TensorView v, TensorView cu_seqlens, Optional<TensorView> input_state,\n Optional<TensorView> alpha, Optional<TensorView> beta, double scale,\n TensorView workspace_buffer) {\n int64_t num_seqs = cu_seqlens.size(0) - 1;\n int64_t packed_seq = q.size(0);\n int64_t head_size = q.size(2);\n int64_t num_q_heads = q.size(1);\n int64_t num_k_heads = k.size(1);\n int64_t num_v_heads = v.size(1);\n\n // NOTE: Qwen3-next alpha and beta heads are 32, equal to v heads, we limit it to larger one\n int32_t num_sab_heads = std::max(num_q_heads, num_v_heads);\n\n if (num_q_heads >= num_v_heads) { // GQA\n auto ratio = num_q_heads / num_v_heads;\n TVM_FFI_ICHECK_EQ(num_k_heads, num_v_heads);\n TVM_FFI_ICHECK_EQ(num_q_heads, ratio * num_k_heads);\n TVM_FFI_ICHECK_EQ(num_q_heads, ratio * num_v_heads);\n } else { // GVA\n auto ratio = num_v_heads / num_q_heads;\n TVM_FFI_ICHECK_EQ(num_q_heads, num_k_heads);\n TVM_FFI_ICHECK_EQ(num_v_heads, ratio * num_q_heads);\n TVM_FFI_ICHECK_EQ(num_v_heads, ratio * num_k_heads);\n }\n\n int64_t num_o_heads = output.size(1);\n TVM_FFI_ICHECK_EQ(num_o_heads, num_sab_heads);\n\n void* input_state_ptr = nullptr;\n if (input_state.has_value()) {\n CHECK_SHAPE(input_state.value(), output_state);\n TVM_FFI_ICHECK_EQ(input_state.value().dtype(), dl_float32);\n input_state_ptr = input_state.value().data_ptr();\n }\n\n CHECK_INPUT(output);\n CHECK_INPUT(output_state);\n CHECK_INPUT(q);\n CHECK_INPUT(k);\n CHECK_INPUT(v);\n CHECK_INPUT(cu_seqlens);\n CHECK_INPUT(workspace_buffer);\n\n TVM_FFI_ICHECK(output.dtype() == dl_float16 || output.dtype() == dl_bfloat16);\n TVM_FFI_ICHECK_EQ(output_state.dtype(), dl_float32);\n TVM_FFI_ICHECK_EQ(output.dtype(), q.dtype());\n TVM_FFI_ICHECK_EQ(output.dtype(), k.dtype());\n TVM_FFI_ICHECK_EQ(output.dtype(), v.dtype());\n TVM_FFI_ICHECK_EQ(cu_seqlens.dtype(), dl_int64);\n TVM_FFI_ICHECK_EQ(workspace_buffer.dtype(), dl_uint8);\n\n TVM_FFI_ICHECK_EQ(packed_seq, k.size(0));\n TVM_FFI_ICHECK_EQ(packed_seq, v.size(0));\n TVM_FFI_ICHECK_EQ(packed_seq, output.size(0));\n\n TVM_FFI_ICHECK_EQ(num_seqs, output_state.size(0));\n TVM_FFI_ICHECK_EQ(num_sab_heads, output_state.size(1));\n\n TVM_FFI_ICHECK_EQ(head_size, output.size(2));\n TVM_FFI_ICHECK_EQ(head_size, k.size(2));\n TVM_FFI_ICHECK_EQ(head_size, v.size(2));\n TVM_FFI_ICHECK_EQ(head_size, output_state.size(2));\n TVM_FFI_ICHECK_EQ(head_size, output_state.size(3));\n\n void* alpha_ptr = nullptr;\n if (alpha.has_value()) {\n TensorView alpha_tensor = alpha.value();\n TVM_FFI_ICHECK_EQ(alpha_tensor.dtype(), dl_float32);\n TVM_FFI_ICHECK_EQ(alpha_tensor.size(0), packed_seq);\n TVM_FFI_ICHECK_EQ(alpha_tensor.size(1), num_sab_heads);\n CHECK_INPUT(alpha_tensor);\n alpha_ptr = alpha_tensor.data_ptr();\n }\n\n void* beta_ptr = nullptr;\n if (beta.has_value()) {\n TensorView beta_tensor = beta.value();\n TVM_FFI_ICHECK_EQ(beta_tensor.dtype(), dl_float32);\n TVM_FFI_ICHECK_EQ(beta_tensor.size(0), packed_seq);\n TVM_FFI_ICHECK_EQ(beta_tensor.size(1), num_sab_heads);\n CHECK_INPUT(beta_tensor);\n beta_ptr = beta_tensor.data_ptr();\n }\n\n if (scale == 0.0) {\n scale = 1.0 / std::sqrt(head_size);\n }\n\n int dev_id;\n cudaGetDevice(&dev_id);\n cudaDeviceProp device_properties;\n cudaGetDeviceProperties(&device_properties, dev_id);\n int32_t sm_count = device_properties.multiProcessorCount;\n\n auto stream = get_stream(q.device());\n\n gdn_prefill_launcher(output.data_ptr(), output_state.data_ptr(), q.data_ptr(), k.data_ptr(),\n v.data_ptr(), input_state_ptr, alpha_ptr, beta_ptr,\n static_cast<int64_t*>(cu_seqlens.data_ptr()),\n static_cast<uint8_t*>(workspace_buffer.data_ptr()), num_seqs, num_q_heads,\n num_k_heads, num_v_heads, num_o_heads, head_size, packed_seq,\n static_cast<float>(scale), sm_count, q.dtype(), stream);\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(gdn_prefill, gdn_prefill);\n\n} // namespace flashinfer\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Summary\n- Cache `device_properties.major` and `device_properties.multiProcessorCount` using\n `static thread_local` variables in `gdn_prefill_launcher()` and `gdn_prefill()`\n respectively, instead of calling `cudaGetDeviceProperties` on every invocation.\n- Each `cudaGetDeviceProperties` call adds ~1ms of synchronous CPU overhead, which\n accumulates to ~72ms across 36 GDN layers during prefill. This change eliminates\n that repeated overhead.\n## Changes\n- **`csrc/gdn_prefill_launcher.cu`**: Replace per-call `cudaGetDeviceProperties` with\n `static thread_local` cached values for `device_major` (used for SM architecture\n dispatch) and `sm_count` (used for kernel launch configuration).\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Refactor**\n * Streamlined GPU device attribute retrieval mechanisms for accessing compute capability and processor information.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1180,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"99562e5eeaa26b08ba5e514bfe22d84404390ca6"},"date":{"kind":"string","value":"2026-02-06T16:01:50-08:00"},"pr_number":{"kind":"number","value":2398,"string":"2,398"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2398"},"title":{"kind":"string","value":"feat: cuteDSL fp4 moe for better DSR1 performance. (#2398)"},"message":{"kind":"string","value":"feat: cuteDSL fp4 moe for better DSR1 performance. (#2398)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\ncuteDSL fp4 moe from TRTLLM with fusion. issue #2259\nThe collective fusion performance improvement collected from TRTLLM [PR\n8880](https://github.com/NVIDIA/TensorRT-LLM/pull/8880), [PR\n9288](https://github.com/NVIDIA/TensorRT-LLM/pull/9288), [PR\n9618](https://github.com/NVIDIA/TensorRT-LLM/pull/9618),.\n\nIntroducing two new API for moe\n`cute_dsl_fused_moe_nvfp4`, `CuteDslMoEWrapper`. \nThe two API are functionally equivalent. The `cute_dsl_fused_moe_nvfp4`\nfunction could run the operation directly, while the wrapper API splits\ntensor setup and execution to better support cuda graph. Using wrapper\nAPI is recommended.\n\nThe PR also introduces autotune functionality for this function.\n\nPerformance data:\n```\n$ python benchmarks/bench_moe_deepseek.py --num-tokens 1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384\n====================================================================================================\nDeepSeek-V3 MoE Benchmark: CuteDSL vs CUTLASS vs TRTLLM (EP=1)\n====================================================================================================\nModel: hidden=7168, intermediate=2048, experts=256, top_k=8\nEP Config: 256 local experts (simulating 1-way parallelism)\nCUDA Graph: enabled, CUPTI: enabled\n----------------------------------------------------------------------------------------------------\nTokens | CuteDSL | CUTLASS | TRTLLM | Speedup (CuteDSL/X) | Winner\n | ms TFLOPS | ms TFLOPS | ms TFLOPS | CUTLASS TRTLLM |\n----------------------------------------------------------------------------------------------------\n 1 | 0.064 10.9 | 0.098 7.2 | 0.053 13.2 | 1.53x 0.83x | TRTLLM\n 2 | 0.077 18.2 | 0.109 13.0 | 0.064 21.9 | 1.40x 0.83x | TRTLLM\n 4 | 0.097 28.9 | 0.131 21.5 | 0.086 32.7 | 1.35x 0.88x | TRTLLM\n 8 | 0.098 57.5 | 0.133 42.4 | 0.092 61.4 | 1.36x 0.94x | TRTLLM\n 16 | 0.102 110.3 | 0.138 82.0 | 0.104 108.5 | 1.35x 1.02x | CuteDSL\n 32 | 0.115 196.3 | 0.153 146.9 | 0.138 163.4 | 1.34x 1.20x | CuteDSL\n 64 | 0.123 365.7 | 0.168 269.0 | 0.154 292.3 | 1.36x 1.25x | CuteDSL\n 128 | 0.134 674.3 | 0.217 416.0 | 0.174 519.4 | 1.62x 1.30x | CuteDSL\n 256 | 0.144 1252.3 | 0.250 723.0 | 0.220 821.3 | 1.73x 1.52x | CuteDSL\n 512 | 0.200 1802.3 | 0.336 1073.4 | 0.271 1331.9 | 1.68x 1.35x | CuteDSL\n 1024 | 0.286 2520.1 | 0.480 1501.8 | 0.570 1265.7 | 1.68x 1.99x | CuteDSL\n 2048 | 0.469 3073.8 | 0.722 1998.8 | 0.542 2660.6 | 1.54x 1.16x | CuteDSL\n 4096 | 0.852 3387.2 | 1.274 2266.0 | 0.845 3417.2 | 1.49x 0.99x | TRTLLM\n 8192 | 1.676 3444.7 | 2.364 2441.4 | 1.590 3630.7 | 1.41x 0.95x | TRTLLM\n 16384 | 3.290 3509.3 | 4.639 2488.8 | 3.383 3412.5 | 1.41x 1.03x | CuteDSL\n----------------------------------------------------------------------------------------------------\n\n$ python benchmarks/bench_moe_deepseek.py --num-tokens 1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384 --ep 16\n====================================================================================================\nDeepSeek-V3 MoE Benchmark: CuteDSL vs CUTLASS vs TRTLLM (EP=16)\n====================================================================================================\nModel: hidden=7168, intermediate=2048, experts=256, top_k=8\nEP Config: 16 local experts (simulating 16-way parallelism)\nCUDA Graph: enabled, CUPTI: enabled\n----------------------------------------------------------------------------------------------------\nTokens | CuteDSL | CUTLASS | TRTLLM | Speedup (CuteDSL/X) | Winner\n | ms TFLOPS | ms TFLOPS | ms TFLOPS | CUTLASS TRTLLM |\n----------------------------------------------------------------------------------------------------\n 1 | 0.021 2.1 | 0.024 1.8 | 0.018 2.5 | 1.16x 0.85x | TRTLLM\n 2 | 0.020 4.3 | 0.023 3.8 | 0.018 4.8 | 1.13x 0.90x | TRTLLM\n 4 | 0.020 8.6 | 0.024 7.4 | 0.019 9.2 | 1.16x 0.93x | TRTLLM\n 8 | 0.020 17.5 | 0.023 15.4 | 0.020 17.7 | 1.14x 0.99x | TRTLLM\n 16 | 0.021 33.9 | 0.024 29.9 | 0.022 32.8 | 1.13x 1.03x | CuteDSL\n 32 | 0.020 69.4 | 0.024 59.8 | 0.025 57.3 | 1.16x 1.21x | CuteDSL\n 64 | 0.022 129.2 | 0.024 118.7 | 0.025 112.1 | 1.09x 1.15x | CuteDSL\n 128 | 0.021 267.7 | 0.024 236.9 | 0.026 216.7 | 1.13x 1.24x | CuteDSL\n 256 | 0.023 487.3 | 0.025 456.4 | 0.027 411.6 | 1.07x 1.18x | CuteDSL\n 512 | 0.025 917.5 | 0.031 731.0 | 0.030 753.2 | 1.26x 1.22x | CuteDSL\n 1024 | 0.028 1638.6 | 0.036 1243.9 | 0.040 1137.0 | 1.32x 1.44x | CuteDSL\n 2048 | 0.036 2494.3 | 0.045 1988.4 | 0.061 1481.9 | 1.25x 1.68x | CuteDSL\n 4096 | 0.050 3597.4 | 0.061 2934.5 | 0.101 1794.7 | 1.23x 2.00x | CuteDSL\n 8192 | 0.103 3490.5 | 0.150 2409.6 | 0.209 1723.1 | 1.45x 2.03x | CuteDSL\n 16384 | 0.140 5160.4 | 0.198 3638.0 | 0.364 1980.6 | 1.42x 2.61x | CuteDSL\n----------------------------------------------------------------------------------------------------\n\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [ ] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n* Added comprehensive Mixture-of-Experts (MoE) support with FP4\nquantization for Blackwell GPUs.\n* Introduced multi-precision MoE kernels supporting FP16, BF16, FP8, and\nFP4 formats.\n* Added CUDA graph-compatible MoE APIs for improved performance and\nflexibility.\n * Implemented automatic kernel tuning for MoE operations.\n * Added expert parallelism support for distributed MoE inference.\n\n* **Documentation**\n* Added extensive test suite validating MoE functionality across\nprecision formats and configurations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: Alex Yang <aleyang@nvidia.com>\nCo-authored-by: Zihao Ye <expye@outlook.com>\nCo-authored-by: Jonathan Dierksen <1507580+dierksen@users.noreply.github.com>\nCo-authored-by: Claude Sonnet 4.5 <noreply@anthropic.com>\nCo-authored-by: Kangyan-Zhou <zky314343421@gmail.com>\nCo-authored-by: kahyun <69875166+kahyunnam@users.noreply.github.com>\nCo-authored-by: claude[bot] <41898282+claude[bot]@users.noreply.github.com>\nCo-authored-by: Zihao Ye <yzh119@users.noreply.github.com>"},"path":{"kind":"string","value":"flashinfer/cute_dsl/utils.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\nimport ctypes\nimport functools\nimport importlib.util\nfrom typing import Union\n\nimport cutlass\nimport cutlass._mlir.dialects.cute as _cute_ir\nimport torch\nfrom cutlass._mlir import ir\nfrom cutlass.cute.typing import AddressSpace, Numeric, Pointer, Type\n\n\ndef is_cute_dsl_available() -> bool:\n return (\n importlib.util.find_spec(\"cutlass\") is not None\n and importlib.util.find_spec(\"cutlass.cute\") is not None\n )\n\n\ndef get_cutlass_dtype(dtype: str) -> cutlass.dtype:\n dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n \"float32\": cutlass.Float32,\n \"float8_e5m2\": cutlass.Float8E5M2,\n \"float8_e4m3fn\": cutlass.Float8E4M3FN,\n \"float8_e8m0fnu\": cutlass.Float8E8M0FNU,\n \"float4_e2m1fn\": cutlass.Float4E2M1FN,\n }\n return dtype_map[dtype]\n\n\ndef cutlass_to_torch_dtype(cutlass_dtype):\n \"\"\"\n Return the corresponding torch.dtype per the given DSL type\n \"\"\"\n torch_dtype = getattr(torch, cutlass_dtype.__name__.lower(), None)\n\n torch_type_map = {\n cutlass.TFloat32: torch.float32,\n cutlass.Float32: torch.float32,\n cutlass.Float16: torch.float16,\n cutlass.BFloat16: torch.bfloat16,\n cutlass.Float8E5M2: torch.float8_e5m2,\n cutlass.Float8E4M3FN: torch.float8_e4m3fn,\n cutlass.Float8E4M3B11FNUZ: torch.float8_e4m3fnuz,\n }\n if torch_dtype is None:\n torch_dtype = torch_type_map.get(cutlass_dtype)\n\n if torch_dtype is None:\n raise TypeError(f\"{cutlass_dtype} is not supported by torch\")\n return torch_dtype\n\n\n@functools.cache\ndef get_num_sm(device: torch.device) -> int:\n # get the compute capability of the device, which would be cached\n return torch.cuda.get_device_properties(device).multi_processor_count\n\n\n# WAR for CuTeDSL make_ptr implementation for flashinfer\nclass _Pointer(Pointer):\n \"\"\"Runtime representation of a pointer that can inter-operate with\n various data structures, including numpy arrays and device memory.\n\n :param pointer: The pointer to the data\n :type pointer: int or pointer-like object\n :param dtype: Data type of the elements pointed to\n :type dtype: Type\n :param mem_space: Memory space where the pointer resides, defaults generic\n :type mem_space: _cute_ir.AddressSpace, optional\n :param assumed_align: Alignment of input pointer in bytes, defaults None\n :type assumed_align: int, optional\n\n :ivar _pointer: The underlying pointer\n :ivar _dtype: Data type of the elements\n :ivar _addr_space: Memory space of the pointer\n :ivar _assumed_align: Alignment of the pointer in bytes\n :ivar _desc: C-type descriptor for the pointer\n :ivar _c_pointer: C-compatible pointer representation\n \"\"\"\n\n def __init__(\n self,\n pointer,\n dtype,\n mem_space: _cute_ir.AddressSpace = _cute_ir.AddressSpace.generic,\n assumed_align=None,\n ):\n self._pointer = pointer\n self._dtype = dtype\n self._addr_space = mem_space\n\n if assumed_align is None:\n self._assumed_align = dtype.width // 8\n else:\n self._assumed_align = assumed_align\n\n self._desc = None\n self._c_pointer = None\n assert int(self._pointer) % self._assumed_align == 0, (\n f\"pointer must be {self._assumed_align} bytes aligned\"\n )\n\n def size_in_bytes(self) -> int:\n return ctypes.sizeof(ctypes.c_void_p(int(self._pointer)))\n\n def __get_mlir_types__(self):\n return [self.mlir_type]\n\n def __c_pointers__(self):\n if self._c_pointer is None:\n self._desc = ctypes.c_void_p(int(self._pointer))\n self._c_pointer = ctypes.addressof(self._desc)\n return [self._c_pointer]\n\n def __new_from_mlir_values__(self, values):\n assert len(values) == 1\n return values[0]\n\n # Move mlir Type out of __init__ to decouple with mlir Context\n @property\n def mlir_type(self) -> ir.Type:\n return _cute_ir.PtrType.get(\n self._dtype.mlir_type, self._addr_space, self._assumed_align\n )\n\n @property\n def dtype(self) -> Type[Numeric]:\n return self._dtype\n\n @property\n def memspace(self):\n return self._addr_space\n\n def align(self, min_align: int, *, loc=None, ip=None) -> Pointer:\n raise NotImplementedError(\"align is not supported in runtime\")\n\n def verify(self, expected_py_type):\n # if expected_py_type is Pointer:\n # return True\n # elif isinstance(expected_py_type, ir.Value) and expected_py_type.ty is Pointer:\n # return True\n if expected_py_type is Pointer or (\n isinstance(expected_py_type, ir.Value) and expected_py_type.ty is Pointer\n ):\n return True\n\n return False\n\n def __str__(self) -> str:\n return f\"Ptr<0x{int(self._pointer):016x}@{self._addr_space}>\"\n\n def __repr__(self):\n return self.__str__()\n\n\ndef make_ptr(\n dtype: Type[Numeric],\n value: Union[int, ctypes._Pointer],\n mem_space: AddressSpace = AddressSpace.generic,\n assumed_align=None,\n) -> Pointer:\n \"\"\"Create a pointer from a memory address\n\n :param dtype: Data type of the pointer elements\n :type dtype: Type[Numeric]\n :param value: Memory address as integer or ctypes pointer\n :type value: Union[int, ctypes._Pointer]\n :param mem_space: Memory address space, defaults to AddressSpace.generic\n :type mem_space: AddressSpace, optional\n :param assumed_align: Alignment in bytes, defaults to None\n :type assumed_align: int, optional\n :return: A pointer object\n :rtype: Pointer\n\n .. code-block:: python\n\n import numpy as np\n import ctypes\n\n from cutlass import Float32\n from cutlass.cute.runtime import make_ptr\n\n # Create a numpy array\n a = np.random.randn(16, 32).astype(np.float32)\n\n # Get pointer address as integer\n ptr_address = a.ctypes.data_as(ctypes.POINTER(ctypes.c_float))\n\n # Create pointer from address\n y = make_ptr(cutlass.Float32, ptr_address)\n \"\"\"\n # check if value is int or ctypes.POINTER\n if isinstance(value, int):\n address_value = value\n elif isinstance(value, ctypes._Pointer):\n # get address value\n address_value = ctypes.cast(value, ctypes.c_void_p).value\n assert address_value is not None, \"Pointer address is None\"\n else:\n raise TypeError(\n f\"Expect int or ctypes.POINTER for value but got {type(value)=}\"\n )\n\n return _Pointer(address_value, dtype, mem_space, assumed_align=assumed_align)\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\nimport ctypes\nimport functools\nimport importlib.util\nfrom typing import Union, Tuple\n\nimport cutlass\nimport cutlass._mlir.dialects.cute as _cute_ir\nimport torch\nfrom cutlass._mlir import ir\nfrom cutlass.cute.typing import AddressSpace, Numeric, Pointer, Type\n\n\ndef ceil_div(a: int, b: int) -> int:\n \"\"\"Ceiling division.\"\"\"\n return (a + b - 1) // b\n\n\ndef is_cute_dsl_available() -> bool:\n return (\n importlib.util.find_spec(\"cutlass\") is not None\n and importlib.util.find_spec(\"cutlass.cute\") is not None\n )\n\n\ndef get_cutlass_dtype(dtype: str) -> cutlass.dtype:\n dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n \"float32\": cutlass.Float32,\n \"float8_e5m2\": cutlass.Float8E5M2,\n \"float8_e4m3fn\": cutlass.Float8E4M3FN,\n \"float8_e8m0fnu\": cutlass.Float8E8M0FNU,\n \"float4_e2m1fn\": cutlass.Float4E2M1FN,\n }\n return dtype_map[dtype]\n\n\ndef cutlass_to_torch_dtype(cutlass_dtype):\n \"\"\"\n Return the corresponding torch.dtype per the given DSL type\n \"\"\"\n torch_dtype = getattr(torch, cutlass_dtype.__name__.lower(), None)\n\n torch_type_map = {\n cutlass.TFloat32: torch.float32,\n cutlass.Float32: torch.float32,\n cutlass.Float16: torch.float16,\n cutlass.BFloat16: torch.bfloat16,\n cutlass.Float8E5M2: torch.float8_e5m2,\n cutlass.Float8E4M3FN: torch.float8_e4m3fn,\n cutlass.Float8E4M3B11FNUZ: torch.float8_e4m3fnuz,\n cutlass.Float4E2M1FN: torch.float4_e2m1fn_x2, # FP4 packed (2 values per byte)\n }\n if torch_dtype is None:\n torch_dtype = torch_type_map.get(cutlass_dtype)\n\n if torch_dtype is None:\n raise TypeError(f\"{cutlass_dtype} is not supported by torch\")\n return torch_dtype\n\n\n@functools.cache\ndef get_num_sm(device: torch.device) -> int:\n # get the compute capability of the device, which would be cached\n return torch.cuda.get_device_properties(device).multi_processor_count\n\n\n# Cache for HardwareInfo - it's expensive to create on every call\n_hardware_info_cache: \"cutlass.utils.HardwareInfo | None\" = None\n\n\ndef get_hardware_info() -> \"cutlass.utils.HardwareInfo\":\n \"\"\"Get cached HardwareInfo singleton.\n\n HardwareInfo queries CUDA device capabilities, which can be expensive.\n This function caches the singleton to avoid repeated queries.\n \"\"\"\n global _hardware_info_cache\n if _hardware_info_cache is None:\n _hardware_info_cache = cutlass.utils.HardwareInfo()\n return _hardware_info_cache\n\n\n@functools.cache\ndef get_max_active_clusters(cluster_size: int) -> int:\n \"\"\"Get max active clusters for a given cluster size (cached).\n\n Args:\n cluster_size: Product of cluster_shape_mn dimensions.\n\n Returns:\n Maximum number of active clusters supported by hardware.\n \"\"\"\n return get_hardware_info().get_max_active_clusters(cluster_size)\n\n\n# WAR for CuTeDSL make_ptr implementation for flashinfer\nclass _Pointer(Pointer):\n \"\"\"Runtime representation of a pointer that can inter-operate with\n various data structures, including numpy arrays and device memory.\n\n :param pointer: The pointer to the data\n :type pointer: int or pointer-like object\n :param dtype: Data type of the elements pointed to\n :type dtype: Type\n :param mem_space: Memory space where the pointer resides, defaults generic\n :type mem_space: _cute_ir.AddressSpace, optional\n :param assumed_align: Alignment of input pointer in bytes, defaults None\n :type assumed_align: int, optional\n\n :ivar _pointer: The underlying pointer\n :ivar _dtype: Data type of the elements\n :ivar _addr_space: Memory space of the pointer\n :ivar _assumed_align: Alignment of the pointer in bytes\n :ivar _desc: C-type descriptor for the pointer\n :ivar _c_pointer: C-compatible pointer representation\n \"\"\"\n\n def __init__(\n self,\n pointer,\n dtype,\n mem_space: _cute_ir.AddressSpace = _cute_ir.AddressSpace.generic,\n assumed_align=None,\n ):\n self._pointer = pointer\n self._dtype = dtype\n self._addr_space = mem_space\n\n if assumed_align is None:\n self._assumed_align = dtype.width // 8\n else:\n self._assumed_align = assumed_align\n\n self._desc = None\n self._c_pointer = None\n assert int(self._pointer) % self._assumed_align == 0, (\n f\"pointer must be {self._assumed_align} bytes aligned\"\n )\n\n def size_in_bytes(self) -> int:\n return ctypes.sizeof(ctypes.c_void_p(int(self._pointer)))\n\n def __get_mlir_types__(self):\n return [self.mlir_type]\n\n def __c_pointers__(self):\n if self._c_pointer is None:\n self._desc = ctypes.c_void_p(int(self._pointer))\n self._c_pointer = ctypes.addressof(self._desc)\n return [self._c_pointer]\n\n def __new_from_mlir_values__(self, values):\n assert len(values) == 1\n return values[0]\n\n # Move mlir Type out of __init__ to decouple with mlir Context\n @property\n def mlir_type(self) -> ir.Type:\n return _cute_ir.PtrType.get(\n self._dtype.mlir_type, self._addr_space, self._assumed_align\n )\n\n @property\n def dtype(self) -> Type[Numeric]:\n return self._dtype\n\n @property\n def memspace(self):\n return self._addr_space\n\n def align(self, min_align: int, *, loc=None, ip=None) -> Pointer:\n raise NotImplementedError(\"align is not supported in runtime\")\n\n def verify(self, expected_py_type):\n # if expected_py_type is Pointer:\n # return True\n # elif isinstance(expected_py_type, ir.Value) and expected_py_type.ty is Pointer:\n # return True\n if expected_py_type is Pointer or (\n isinstance(expected_py_type, ir.Value) and expected_py_type.ty is Pointer\n ):\n return True\n\n return False\n\n def __str__(self) -> str:\n return f\"Ptr<0x{int(self._pointer):016x}@{self._addr_space}>\"\n\n def __repr__(self):\n return self.__str__()\n\n\ndef make_ptr(\n dtype: Type[Numeric],\n value: Union[int, ctypes._Pointer],\n mem_space: AddressSpace = AddressSpace.generic,\n assumed_align=None,\n) -> Pointer:\n \"\"\"Create a pointer from a memory address\n\n :param dtype: Data type of the pointer elements\n :type dtype: Type[Numeric]\n :param value: Memory address as integer or ctypes pointer\n :type value: Union[int, ctypes._Pointer]\n :param mem_space: Memory address space, defaults to AddressSpace.generic\n :type mem_space: AddressSpace, optional\n :param assumed_align: Alignment in bytes, defaults to None\n :type assumed_align: int, optional\n :return: A pointer object\n :rtype: Pointer\n\n .. code-block:: python\n\n import numpy as np\n import ctypes\n\n from cutlass import Float32\n from cutlass.cute.runtime import make_ptr\n\n # Create a numpy array\n a = np.random.randn(16, 32).astype(np.float32)\n\n # Get pointer address as integer\n ptr_address = a.ctypes.data_as(ctypes.POINTER(ctypes.c_float))\n\n # Create pointer from address\n y = make_ptr(cutlass.Float32, ptr_address)\n \"\"\"\n # check if value is int or ctypes.POINTER\n if isinstance(value, int):\n address_value = value\n elif isinstance(value, ctypes._Pointer):\n # get address value\n address_value = ctypes.cast(value, ctypes.c_void_p).value\n assert address_value is not None, \"Pointer address is None\"\n else:\n raise TypeError(\n f\"Expect int or ctypes.POINTER for value but got {type(value)=}\"\n )\n\n return _Pointer(address_value, dtype, mem_space, assumed_align=assumed_align)\n\n\ndef convert_sf_to_mma_layout(\n sf: torch.Tensor,\n m: int,\n k: int,\n num_groups: int = 1,\n sf_vec_size: int = 16,\n) -> torch.Tensor:\n \"\"\"Convert scale factors from swizzled 2D layout to 6D MMA-compatible layout.\n\n This function converts scale factors produced by `fp4_quantize(..., is_sf_swizzled_layout=True)`\n to the 6D layout expected by CuteDSL grouped GEMM kernels.\n\n The swizzled scale factors from `fp4_quantize` have shape `(M, K/sf_vec_size)` but are\n stored in a swizzled pattern internally. This function reshapes them to the explicit\n 6D MMA-compatible layout: `(32, 4, m_tiles, 4, k_tiles, num_groups)` with the\n physical storage order `(num_groups, m_tiles, k_tiles, 32, 4, 4)`.\n\n Layout mapping (from linear (m, k) position):\n - m_tile = m // 128\n - outer_m = m % 32\n - inner_m = (m % 128) // 32\n - k_tile = k // 4\n - inner_k = k % 4\n - 6D position: (outer_m, inner_m, m_tile, inner_k, k_tile, group)\n\n Args:\n sf: Scale factor tensor from `fp4_quantize(..., is_sf_swizzled_layout=True)`.\n Shape: `(M, K/sf_vec_size)` or `(num_groups * M, K/sf_vec_size)`.\n m: The M dimension (rows) of the original matrix before quantization.\n k: The K dimension (columns) of the original matrix before quantization.\n num_groups: Number of groups (e.g., experts). Default: 1.\n sf_vec_size: Scale factor vector size. Default: 16.\n\n Returns:\n Scale factors in 6D MMA layout: `(32, 4, m_tiles, 4, k_tiles, num_groups)`.\n This is a strided view (not contiguous) with physical storage order\n `(num_groups, m_tiles, k_tiles, 32, 4, 4)`.\n\n Example:\n >>> # Quantize weight tensor\n >>> w_q, w_sf = fp4_quantize(weight, global_scale=gs, is_sf_swizzled_layout=True)\n >>> # Convert scale factors to MMA layout\n >>> w_sf_mma = convert_sf_to_mma_layout(w_sf, m=weight.shape[0], k=weight.shape[1])\n\n Note:\n - The input `sf` must be produced with `is_sf_swizzled_layout=True`.\n - M and K dimensions must be multiples of 128 and 64 respectively for proper alignment.\n - For grouped tensors (e.g., expert weights), reshape to `(num_groups * M, K)`\n before quantization, then use this function with the appropriate `num_groups`.\n - The returned tensor is a strided view, NOT contiguous. This is intentional as\n the CuteDSL kernel expects the specific physical memory layout.\n \"\"\"\n sf_k = ceil_div(k, sf_vec_size)\n m_tiles = ceil_div(m, 128)\n k_tiles = ceil_div(sf_k, 4)\n\n # Verify input shape\n expected_elements = num_groups * m_tiles * k_tiles * 32 * 4 * 4\n actual_elements = sf.numel()\n if actual_elements != expected_elements:\n raise ValueError(\n f\"Scale factor tensor has {actual_elements} elements, \"\n f\"expected {expected_elements} for m={m}, k={k}, num_groups={num_groups}\"\n )\n\n # Reshape from flat 2D to 6D physical storage order\n # Physical storage: (num_groups, m_tiles, k_tiles, 32, 4, 4)\n sf_6d = sf.view(num_groups, m_tiles, k_tiles, 32, 4, 4)\n\n # Permute to MMA logical order: (32, 4, m_tiles, 4, k_tiles, num_groups)\n # This creates a strided view (non-contiguous), which is what the kernel expects\n sf_6d = sf_6d.permute(3, 4, 1, 5, 2, 0)\n\n return sf_6d # Return strided view, NOT contiguous\n\n\ndef convert_sf_from_mma_layout(\n sf_6d: torch.Tensor,\n m: int,\n k: int,\n num_groups: int = 1,\n sf_vec_size: int = 16,\n) -> torch.Tensor:\n \"\"\"Convert scale factors from 6D MMA layout back to 2D swizzled layout.\n\n This is the inverse of `convert_sf_to_mma_layout`.\n\n Args:\n sf_6d: Scale factors in 6D MMA layout: `(32, 4, m_tiles, 4, k_tiles, num_groups)`.\n Can be either a strided view or contiguous.\n m: The M dimension (rows) of the original matrix.\n k: The K dimension (columns) of the original matrix.\n num_groups: Number of groups. Default: 1.\n sf_vec_size: Scale factor vector size. Default: 16.\n\n Returns:\n Scale factors in 2D swizzled layout: `(num_groups * M_padded, K_padded/sf_vec_size)`.\n \"\"\"\n sf_k = ceil_div(k, sf_vec_size)\n m_tiles = ceil_div(m, 128)\n k_tiles = ceil_div(sf_k, 4)\n\n # Permute from MMA logical order back to storage order\n # From: (32, 4, m_tiles, 4, k_tiles, num_groups)\n # To: (num_groups, m_tiles, k_tiles, 32, 4, 4)\n sf_storage = sf_6d.permute(5, 2, 4, 0, 1, 3).contiguous()\n\n # Reshape to 2D\n padded_m = m_tiles * 128\n padded_sf_k = k_tiles * 4\n sf_2d = sf_storage.reshape(num_groups * padded_m, padded_sf_k)\n\n return sf_2d\n\n\ndef get_mma_sf_shape(\n m: int,\n k: int,\n num_groups: int = 1,\n sf_vec_size: int = 16,\n) -> Tuple[int, int, int, int, int, int]:\n \"\"\"Get the 6D MMA-compatible scale factor shape.\n\n Args:\n m: The M dimension (rows) of the matrix.\n k: The K dimension (columns) of the matrix.\n num_groups: Number of groups. Default: 1.\n sf_vec_size: Scale factor vector size. Default: 16.\n\n Returns:\n Shape tuple: (32, 4, m_tiles, 4, k_tiles, num_groups)\n \"\"\"\n sf_k = ceil_div(k, sf_vec_size)\n m_tiles = ceil_div(m, 128)\n k_tiles = ceil_div(sf_k, 4)\n return (32, 4, m_tiles, 4, k_tiles, num_groups)\n"},"diff":{"kind":"string","value":"--- flashinfer/cute_dsl/utils.py\n+++ flashinfer/cute_dsl/utils.py\n@@ -17,13 +17,18 @@\n import ctypes\n import functools\n import importlib.util\n-from typing import Union\n+from typing import Union, Tuple\n \n import cutlass\n import cutlass._mlir.dialects.cute as _cute_ir\n import torch\n from cutlass._mlir import ir\n from cutlass.cute.typing import AddressSpace, Numeric, Pointer, Type\n+\n+\n+def ceil_div(a: int, b: int) -> int:\n+ \"\"\"Ceiling division.\"\"\"\n+ return (a + b - 1) // b\n \n \n def is_cute_dsl_available() -> bool:\n@@ -60,6 +65,7 @@\n cutlass.Float8E5M2: torch.float8_e5m2,\n cutlass.Float8E4M3FN: torch.float8_e4m3fn,\n cutlass.Float8E4M3B11FNUZ: torch.float8_e4m3fnuz,\n+ cutlass.Float4E2M1FN: torch.float4_e2m1fn_x2, # FP4 packed (2 values per byte)\n }\n if torch_dtype is None:\n torch_dtype = torch_type_map.get(cutlass_dtype)\n@@ -73,6 +79,35 @@\n def get_num_sm(device: torch.device) -> int:\n # get the compute capability of the device, which would be cached\n return torch.cuda.get_device_properties(device).multi_processor_count\n+\n+\n+# Cache for HardwareInfo - it's expensive to create on every call\n+_hardware_info_cache: \"cutlass.utils.HardwareInfo | None\" = None\n+\n+\n+def get_hardware_info() -> \"cutlass.utils.HardwareInfo\":\n+ \"\"\"Get cached HardwareInfo singleton.\n+\n+ HardwareInfo queries CUDA device capabilities, which can be expensive.\n+ This function caches the singleton to avoid repeated queries.\n+ \"\"\"\n+ global _hardware_info_cache\n+ if _hardware_info_cache is None:\n+ _hardware_info_cache = cutlass.utils.HardwareInfo()\n+ return _hardware_info_cache\n+\n+\n+@functools.cache\n+def get_max_active_clusters(cluster_size: int) -> int:\n+ \"\"\"Get max active clusters for a given cluster size (cached).\n+\n+ Args:\n+ cluster_size: Product of cluster_shape_mn dimensions.\n+\n+ Returns:\n+ Maximum number of active clusters supported by hardware.\n+ \"\"\"\n+ return get_hardware_info().get_max_active_clusters(cluster_size)\n \n \n # WAR for CuTeDSL make_ptr implementation for flashinfer\n@@ -221,3 +256,141 @@\n )\n \n return _Pointer(address_value, dtype, mem_space, assumed_align=assumed_align)\n+\n+\n+def convert_sf_to_mma_layout(\n+ sf: torch.Tensor,\n+ m: int,\n+ k: int,\n+ num_groups: int = 1,\n+ sf_vec_size: int = 16,\n+) -> torch.Tensor:\n+ \"\"\"Convert scale factors from swizzled 2D layout to 6D MMA-compatible layout.\n+\n+ This function converts scale factors produced by `fp4_quantize(..., is_sf_swizzled_layout=True)`\n+ to the 6D layout expected by CuteDSL grouped GEMM kernels.\n+\n+ The swizzled scale factors from `fp4_quantize` have shape `(M, K/sf_vec_size)` but are\n+ stored in a swizzled pattern internally. This function reshapes them to the explicit\n+ 6D MMA-compatible layout: `(32, 4, m_tiles, 4, k_tiles, num_groups)` with the\n+ physical storage order `(num_groups, m_tiles, k_tiles, 32, 4, 4)`.\n+\n+ Layout mapping (from linear (m, k) position):\n+ - m_tile = m // 128\n+ - outer_m = m % 32\n+ - inner_m = (m % 128) // 32\n+ - k_tile = k // 4\n+ - inner_k = k % 4\n+ - 6D position: (outer_m, inner_m, m_tile, inner_k, k_tile, group)\n+\n+ Args:\n+ sf: Scale factor tensor from `fp4_quantize(..., is_sf_swizzled_layout=True)`.\n+ Shape: `(M, K/sf_vec_size)` or `(num_groups * M, K/sf_vec_size)`.\n+ m: The M dimension (rows) of the original matrix before quantization.\n+ k: The K dimension (columns) of the original matrix before quantization.\n+ num_groups: Number of groups (e.g., experts). Default: 1.\n+ sf_vec_size: Scale factor vector size. Default: 16.\n+\n+ Returns:\n+ Scale factors in 6D MMA layout: `(32, 4, m_tiles, 4, k_tiles, num_groups)`.\n+ This is a strided view (not contiguous) with physical storage order\n+ `(num_groups, m_tiles, k_tiles, 32, 4, 4)`.\n+\n+ Example:\n+ >>> # Quantize weight tensor\n+ >>> w_q, w_sf = fp4_quantize(weight, global_scale=gs, is_sf_swizzled_layout=True)\n+ >>> # Convert scale factors to MMA layout\n+ >>> w_sf_mma = convert_sf_to_mma_layout(w_sf, m=weight.shape[0], k=weight.shape[1])\n+\n+ Note:\n+ - The input `sf` must be produced with `is_sf_swizzled_layout=True`.\n+ - M and K dimensions must be multiples of 128 and 64 respectively for proper alignment.\n+ - For grouped tensors (e.g., expert weights), reshape to `(num_groups * M, K)`\n+ before quantization, then use this function with the appropriate `num_groups`.\n+ - The returned tensor is a strided view, NOT contiguous. This is intentional as\n+ the CuteDSL kernel expects the specific physical memory layout.\n+ \"\"\"\n+ sf_k = ceil_div(k, sf_vec_size)\n+ m_tiles = ceil_div(m, 128)\n+ k_tiles = ceil_div(sf_k, 4)\n+\n+ # Verify input shape\n+ expected_elements = num_groups * m_tiles * k_tiles * 32 * 4 * 4\n+ actual_elements = sf.numel()\n+ if actual_elements != expected_elements:\n+ raise ValueError(\n+ f\"Scale factor tensor has {actual_elements} elements, \"\n+ f\"expected {expected_elements} for m={m}, k={k}, num_groups={num_groups}\"\n+ )\n+\n+ # Reshape from flat 2D to 6D physical storage order\n+ # Physical storage: (num_groups, m_tiles, k_tiles, 32, 4, 4)\n+ sf_6d = sf.view(num_groups, m_tiles, k_tiles, 32, 4, 4)\n+\n+ # Permute to MMA logical order: (32, 4, m_tiles, 4, k_tiles, num_groups)\n+ # This creates a strided view (non-contiguous), which is what the kernel expects\n+ sf_6d = sf_6d.permute(3, 4, 1, 5, 2, 0)\n+\n+ return sf_6d # Return strided view, NOT contiguous\n+\n+\n+def convert_sf_from_mma_layout(\n+ sf_6d: torch.Tensor,\n+ m: int,\n+ k: int,\n+ num_groups: int = 1,\n+ sf_vec_size: int = 16,\n+) -> torch.Tensor:\n+ \"\"\"Convert scale factors from 6D MMA layout back to 2D swizzled layout.\n+\n+ This is the inverse of `convert_sf_to_mma_layout`.\n+\n+ Args:\n+ sf_6d: Scale factors in 6D MMA layout: `(32, 4, m_tiles, 4, k_tiles, num_groups)`.\n+ Can be either a strided view or contiguous.\n+ m: The M dimension (rows) of the original matrix.\n+ k: The K dimension (columns) of the original matrix.\n+ num_groups: Number of groups. Default: 1.\n+ sf_vec_size: Scale factor vector size. Default: 16.\n+\n+ Returns:\n+ Scale factors in 2D swizzled layout: `(num_groups * M_padded, K_padded/sf_vec_size)`.\n+ \"\"\"\n+ sf_k = ceil_div(k, sf_vec_size)\n+ m_tiles = ceil_div(m, 128)\n+ k_tiles = ceil_div(sf_k, 4)\n+\n+ # Permute from MMA logical order back to storage order\n+ # From: (32, 4, m_tiles, 4, k_tiles, num_groups)\n+ # To: (num_groups, m_tiles, k_tiles, 32, 4, 4)\n+ sf_storage = sf_6d.permute(5, 2, 4, 0, 1, 3).contiguous()\n+\n+ # Reshape to 2D\n+ padded_m = m_tiles * 128\n+ padded_sf_k = k_tiles * 4\n+ sf_2d = sf_storage.reshape(num_groups * padded_m, padded_sf_k)\n+\n+ return sf_2d\n+\n+\n+def get_mma_sf_shape(\n+ m: int,\n+ k: int,\n+ num_groups: int = 1,\n+ sf_vec_size: int = 16,\n+) -> Tuple[int, int, int, int, int, int]:\n+ \"\"\"Get the 6D MMA-compatible scale factor shape.\n+\n+ Args:\n+ m: The M dimension (rows) of the matrix.\n+ k: The K dimension (columns) of the matrix.\n+ num_groups: Number of groups. Default: 1.\n+ sf_vec_size: Scale factor vector size. Default: 16.\n+\n+ Returns:\n+ Shape tuple: (32, 4, m_tiles, 4, k_tiles, num_groups)\n+ \"\"\"\n+ sf_k = ceil_div(k, sf_vec_size)\n+ m_tiles = ceil_div(m, 128)\n+ k_tiles = ceil_div(sf_k, 4)\n+ return (32, 4, m_tiles, 4, k_tiles, num_groups)"},"lines_added":{"kind":"number","value":174,"string":"174"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":6,"string":"6"},"models_mentioned":{"kind":"list like","value":["deepseek"],"string":"[\n \"deepseek\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["BLACKWELL"],"string":"[\n \"BLACKWELL\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.53x","0.83x","1.40x","0.83x","1.35x","0.88x","1.36x","0.94x","1.35x","1.02x"],"string":"[\n \"1.53x\",\n \"0.83x\",\n \"1.40x\",\n \"0.83x\",\n \"1.35x\",\n \"0.88x\",\n \"1.36x\",\n \"0.94x\",\n \"1.35x\",\n \"1.02x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/utils.py).\n\nGoal: feat: cuteDSL fp4 moe for better DSR1 performance.\nTarget hardware: BLACKWELL\nTarget models: deepseek\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\nimport ctypes\nimport functools\nimport importlib.util\nfrom typing import Union\n\nimport cutlass\nimport cutlass._mlir.dialects.cute as _cute_ir\nimport torch\nfrom cutlass._mlir import ir\nfrom cutlass.cute.typing import AddressSpace, Numeric, Pointer, Type\n\n\ndef is_cute_dsl_available() -> bool:\n return (\n importlib.util.find_spec(\"cutlass\") is not None\n and importlib.util.find_spec(\"cutlass.cute\") is not None\n )\n\n\ndef get_cutlass_dtype(dtype: str) -> cutlass.dtype:\n dtype_map = {\n \"float16\": cutlass.Float16,\n \"bfloat16\": cutlass.BFloat16,\n \"float32\": cutlass.Float32,\n \"float8_e5m2\": cutlass.Float8E5M2,\n \"float8_e4m3fn\": cutlass.Float8E4M3FN,\n \"float8_e8m0fnu\": cutlass.Float8E8M0FNU,\n \"float4_e2m1fn\": cutlass.Float4E2M1FN,\n }\n return dtype_map[dtype]\n\n\ndef cutlass_to_torch_dtype(cutlass_dtype):\n \"\"\"\n Return the corresponding torch.dtype per the given DSL type\n \"\"\"\n torch_dtype = getattr(torch, cutlass_dtype.__name__.lower(), None)\n\n torch_type_map = {\n cutlass.TFloat32: torch.float32,\n cutlass.Float32: torch.float32,\n cutlass.Float16: torch.float16,\n cutlass.BFloat16: torch.bfloat16,\n cutlass.Float8E5M2: torch.float8_e5m2,\n cutlass.Float8E4M3FN: torch.float8_e4m3fn,\n cutlass.Float8E4M3B11FNUZ: torch.float8_e4m3fnuz,\n }\n if torch_dtype is None:\n torch_dtype = torch_type_map.get(cutlass_dtype)\n\n if torch_dtype is None:\n raise TypeError(f\"{cutlass_dtype} is not supported by torch\")\n return torch_dtype\n\n\n@functools.cache\ndef get_num_sm(device: torch.device) -> int:\n # get the compute capability of the device, which would be cached\n return torch.cuda.get_device_properties(device).multi_processor_count\n\n\n# WAR for CuTeDSL make_ptr implementation for flashinfer\nclass _Pointer(Pointer):\n \"\"\"Runtime representation of a pointer that can inter-operate with\n various data structures, including numpy arrays and device memory.\n\n :param pointer: The pointer to the data\n :type pointer: int or pointer-like object\n :param dtype: Data type of the elements pointed to\n :type dtype: Type\n :param mem_space: Memory space where the pointer resides, defaults generic\n :type mem_space: _cute_ir.AddressSpace, optional\n :param assumed_align: Alignment of input pointer in bytes, defaults None\n :type assumed_align: int, optional\n\n :ivar _pointer: The underlying pointer\n :ivar _dtype: Data type of the elements\n :ivar _addr_space: Memory space of the pointer\n :ivar _assumed_align: Alignment of the pointer in bytes\n :ivar _desc: C-type descriptor for the pointer\n :ivar _c_pointer: C-compatible pointer representation\n \"\"\"\n\n def __init__(\n self,\n pointer,\n dtype,\n mem_space: _cute_ir.AddressSpace = _cute_ir.AddressSpace.generic,\n assumed_align=None,\n ):\n self._pointer = pointer\n self._dtype = dtype\n self._addr_space = mem_space\n\n if assumed_align is None:\n self._assumed_align = dtype.width // 8\n else:\n self._assumed_align = assumed_align\n\n self._desc = None\n self._c_pointer = None\n assert int(self._pointer) % self._assumed_align == 0, (\n f\"pointer must be {self._assumed_align} bytes aligned\"\n )\n\n def size_in_bytes(self) -> int:\n return ctypes.sizeof(ctypes.c_void_p(int(self._pointer)))\n\n def __get_mlir_types__(self):\n return [self.mlir_type]\n\n def __c_pointers__(self):\n if self._c_pointer is None:\n self._desc = ctypes.c_void_p(int(self._pointer))\n self._c_pointer = ctypes.addressof(self._desc)\n return [self._c_pointer]\n\n def __new_from_mlir_values__(self, values):\n assert len(values) == 1\n return values[0]\n\n # Move mlir Type out of __init__ to decouple with mlir Context\n @property\n def mlir_type(self) -> ir.Type:\n return _cute_ir.PtrType.get(\n self._dtype.mlir_type, self._addr_space, self._assumed_align\n )\n\n @property\n def dtype(self) -> Type[Numeric]:\n return self._dtype\n\n @property\n def memspace(self):\n return self._addr_space\n\n def align(self, min_align: int, *, loc=None, ip=None) -> Pointer:\n raise NotImplementedError(\"align is not supported in runtime\")\n\n def verify(self, expected_py_type):\n # if expected_py_type is Pointer:\n # return True\n # elif isinstance(expected_py_type, ir.Value) and expected_py_type.ty is Pointer:\n # return True\n if expected_py_type is Pointer or (\n isinstance(expected_py_type, ir.Value) and expected_py_type.ty is Pointer\n ):\n return True\n\n return False\n\n def __str__(self) -> str:\n return f\"Ptr<0x{int(self._pointer):016x}@{self._addr_space}>\"\n\n def __repr__(self):\n return self.__str__()\n\n\ndef make_ptr(\n dtype: Type[Numeric],\n value: Union[int, ctypes._Pointer],\n mem_space: AddressSpace = AddressSpace.generic,\n assumed_align=None,\n) -> Pointer:\n \"\"\"Create a pointer from a memory address\n\n :param dtype: Data type of the pointer elements\n :type dtype: Type[Numeric]\n :param value: Memory address as integer or ctypes pointer\n :type value: Union[int, ctypes._Pointer]\n :param mem_space: Memory address space, defaults to AddressSpace.generic\n :type mem_space: AddressSpace, optional\n :param assumed_align: Alignment in bytes, defaults to None\n :type assumed_align: int, optional\n :return: A pointer object\n :rtype: Pointer\n\n .. code-block:: python\n\n import numpy as np\n import ctypes\n\n from cutlass import Float32\n from cutlass.cute.runtime import make_ptr\n\n # Create a numpy array\n a = np.random.randn(16, 32).astype(np.float32)\n\n # Get pointer address as integer\n ptr_address = a.ctypes.data_as(ctypes.POINTER(ctypes.c_float))\n\n # Create pointer from address\n y = make_ptr(cutlass.Float32, ptr_address)\n \"\"\"\n # check if value is int or ctypes.POINTER\n if isinstance(value, int):\n address_value = value\n elif isinstance(value, ctypes._Pointer):\n # get address value\n address_value = ctypes.cast(value, ctypes.c_void_p).value\n assert address_value is not None, \"Pointer address is None\"\n else:\n raise TypeError(\n f\"Expect int or ctypes.POINTER for value but got {type(value)=}\"\n )\n\n return _Pointer(address_value, dtype, mem_space, assumed_align=assumed_align)\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\ncuteDSL fp4 moe from TRTLLM with fusion. issue #2259\nThe collective fusion performance improvement collected from TRTLLM [PR 8880](https://github.com/NVIDIA/TensorRT-LLM/pull/8880), [PR 9288](https://github.com/NVIDIA/TensorRT-LLM/pull/9288), [PR 9618](https://github.com/NVIDIA/TensorRT-LLM/pull/9618),.\n\nIntroducing two new API for moe\n`cute_dsl_fused_moe_nvfp4`, `CuteDslMoEWrapper`. \nThe two API are functionally equivalent. The `cute_dsl_fused_moe_nvfp4` function could run the operation directly, while the wrapper API splits tensor setup and execution to better support cuda graph. Using wrapper API is recommended.\n\nThe PR also introduces autotune functionality for this function.\n\nPerformance data:\n```\n$ python benchmarks/bench_moe_deepseek.py --num-tokens 1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384\n====================================================================================================\nDeepSeek-V3 MoE Benchmark: CuteDSL vs CUTLASS vs TRTLLM (EP=1)\n====================================================================================================\nModel: hidden=7168, intermediate=2048, experts=256, top_k=8\nEP Config: 256 local experts (simulating 1-way parallelism)\nCUDA Graph: enabled, CUPTI: enabled\n----------------------------------------------------------------------------------------------------\nTokens | CuteDSL | CUTLASS | TRTLLM | Speedup (CuteDSL/X) | Winner\n | ms TFLOPS | ms TFLOPS | ms TFLOPS | CUTLASS TRTLLM |\n----------------------------------------------------------------------------------------------------\n 1 | 0.064 10.9 | 0.098 7.2 | 0.053 13.2 | 1.53x 0.83x | TRTLLM\n 2 | 0.077 18.2 | 0.109 13.0 | 0.064 21.9 | 1.40x 0.83x | TRTLLM\n 4 | 0.097 28.9 | 0.131 21.5 | 0.086 32.7 | 1.35x 0.88x | TRTLLM\n 8 | 0.098 57.5 | 0.133 42.4 | 0.092 61.4 | 1.36x 0.94x | TRTLLM\n 16 | 0.102 110.3 | 0.138 82.0 | 0.104 108.5 | 1.35x 1.02x | CuteDSL\n 32 | 0.115 196.3 | 0.153 146.9 | 0.138 163.4 | 1.34x 1.20x | CuteDSL\n 64 | 0.123 365.7 | 0.168 269.0 | 0.154 292.3 | 1.36x 1.25x | CuteDSL\n 128 | 0.134 674.3 | 0.217 416.0 | 0.174 519.4 | 1.62x 1.30x | CuteDSL\n 256 | 0.144 1252.3 | 0.250 723.0 | 0.220 821.3 | 1.73x 1.52x | CuteDSL\n 512 | 0.200 1802.3 | 0.336 1073.4 | 0.271 1331.9 | 1.68x 1.35x | CuteDSL\n 1024 | 0.286 2520.1 | 0.480 1501.8 | 0.570 1265.7 | 1.68x 1.99x | CuteDSL\n 2048 | 0.469 3073.8 | 0.722 1998.8 | 0.542 2660.6 | 1.54x 1.16x | CuteDSL\n 4096 | 0.852 3387.2 | 1.274 2266.0 | 0.845 3417.2 | 1.49x 0.99x | TRTLLM\n 8192 | 1.676 3444.7 | 2.364 2441.4 | 1.590 3630.7 | 1.41x 0.95x | TRTLLM\n 16384 | 3.290 3509.3 | 4.639 2488.8 | 3.383 3412.5 | 1.41x 1.03x | CuteDSL\n----------------------------------------------------------------------------------------------------\n\n$ python benchmarks/bench_moe_deepseek.py --num-tokens 1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384 --ep 16\n====================================================================================================\nDeepSeek-V3 MoE Benchmark: CuteDSL vs CUTLASS vs TRTLLM (EP=16)\n====================================================================================================\nModel: hidden=7168, intermediate=2048, experts=256, top_k=8\nEP Config: 16 local experts (simulating 16-way parallelism)\nCUDA Graph: enabled, CUPTI: enabled\n----------------------------------------------------------------------------------------------------\nTokens | CuteDSL | CUTLASS | TRTLLM | Speedup (CuteDSL/X) | Winner\n | ms TFLOPS | ms TFLOPS | ms TFLOPS | CUTLASS TRTLLM |\n----------------------------------------------------------------------------------------------------\n 1 | 0.021 2.1 | 0.024 1.8 | 0.018 2.5 | 1.16x 0.85x | TRTLLM\n 2 | 0.020 4.3 | 0.023 3.8 | 0.018 4.8 | 1.13x 0.90x | TRTLLM\n 4 | 0.020 8.6 | 0.024 7.4 | 0.019 9.2 | 1.16x 0.93x | TRTLLM\n 8 | 0.020 17.5 | 0.023 15.4 | 0.020 17.7 | 1.14x 0.99x | TRTLLM\n 16 | 0.021 33.9 | 0.024 29.9 | 0.022 32.8 | 1.13x 1.03x | CuteDSL\n 32 | 0.020 69.4 | 0.024 59.8 | 0.025 57.3 | 1.16x 1.21x | CuteDSL\n 64 | 0.022 129.2 | 0.024 118.7 | 0.025 112.1 | 1.09x 1.15x | CuteDSL\n 128 | 0.021 267.7 | 0.024 236.9 | 0.026 216.7 | 1.13x 1.24x | CuteDSL\n 256 | 0.023 487.3 | 0.025 456.4 | 0.027 411.6 | 1.07x 1.18x | CuteDSL\n 512 | 0.025 917.5 | 0.031 731.0 | 0.030 753.2 | 1.26x 1.22x | CuteDSL\n 1024 | 0.028 1638.6 | 0.036 1243.9 | 0.040 1137.0 | 1.32x 1.44x | CuteDSL\n 2048 | 0.036 2494.3 | 0.045 1988.4 | 0.061 1481.9 | 1.25x 1.68x | CuteDSL\n 4096 | 0.050 3597.4 | 0.061 2934.5 | 0.101 1794.7 | 1.23x 2.00x | CuteDSL\n 8192 | 0.103 3490.5 | 0.150 2409.6 | 0.209 1723.1 | 1.45x 2.03x | CuteDSL\n 16384 | 0.140 5160.4 | 0.198 3638.0 | 0.364 1980.6 | 1.42x 2.61x | CuteDSL\n----------------------------------------------------------------------------------------------------\n\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [ ] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n * Added comprehensive Mixture-of-Experts (MoE) support with FP4 quantization for Blackwell GPUs.\n * Introduced multi-precision MoE kernels supporting FP16, BF16, FP8, and FP4 formats.\n * Added CUDA graph-compatible MoE APIs for improved performance and flexibility.\n * Implemented automatic kernel tuning for MoE operations.\n * Added expert parallelism support for distributed MoE inference.\n\n* **Documentation**\n * Added extensive test suite validating MoE functionality across precision formats and configurations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.098, \"optimized\": 0.064, \"stated_speedup\": 1.53, \"speedup\": 1.5312}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.053, \"optimized\": 0.064, \"stated_speedup\": 0.83, \"speedup\": 0.8281}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.109, \"optimized\": 0.077, \"stated_speedup\": 1.4, \"speedup\": 1.4156}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.064, \"optimized\": 0.077, \"stated_speedup\": 0.83, \"speedup\": 0.8312}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 4, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.131, \"optimized\": 0.097, \"stated_speedup\": 1.35, \"speedup\": 1.3505}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 4, \"metric\": \"latency\", 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0.02, \"stated_speedup\": 1.16, \"speedup\": 1.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 4, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.019, \"optimized\": 0.02, \"stated_speedup\": 0.93, \"speedup\": 0.95}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.023, \"optimized\": 0.02, \"stated_speedup\": 1.14, \"speedup\": 1.15}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.02, \"optimized\": 0.02, \"stated_speedup\": 0.99, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.024, \"optimized\": 0.021, \"stated_speedup\": 1.13, \"speedup\": 1.1429}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.022, \"optimized\": 0.021, \"stated_speedup\": 1.03, \"speedup\": 1.0476}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.024, \"optimized\": 0.02, \"stated_speedup\": 1.16, \"speedup\": 1.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.025, \"optimized\": 0.02, \"stated_speedup\": 1.21, \"speedup\": 1.25}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.024, \"optimized\": 0.022, \"stated_speedup\": 1.09, \"speedup\": 1.0909}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.025, \"optimized\": 0.022, \"stated_speedup\": 1.15, \"speedup\": 1.1364}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 128, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.024, \"optimized\": 0.021, \"stated_speedup\": 1.13, \"speedup\": 1.1429}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 128, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.026, \"optimized\": 0.021, \"stated_speedup\": 1.24, \"speedup\": 1.2381}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.025, \"optimized\": 0.023, \"stated_speedup\": 1.07, \"speedup\": 1.087}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.027, \"optimized\": 0.023, \"stated_speedup\": 1.18, \"speedup\": 1.1739}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 512, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.031, \"optimized\": 0.025, \"stated_speedup\": 1.26, \"speedup\": 1.24}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 512, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.03, \"optimized\": 0.025, \"stated_speedup\": 1.22, \"speedup\": 1.2}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 1024, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.036, \"optimized\": 0.028, \"stated_speedup\": 1.32, \"speedup\": 1.2857}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 1024, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.04, \"optimized\": 0.028, \"stated_speedup\": 1.44, \"speedup\": 1.4286}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.045, \"optimized\": 0.036, \"stated_speedup\": 1.25, \"speedup\": 1.25}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 2048, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.061, \"optimized\": 0.036, \"stated_speedup\": 1.68, \"speedup\": 1.6944}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 4096, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.061, \"optimized\": 0.05, \"stated_speedup\": 1.23, \"speedup\": 1.22}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 4096, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.101, \"optimized\": 0.05, \"stated_speedup\": 2.0, \"speedup\": 2.02}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 8192, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.15, \"optimized\": 0.103, \"stated_speedup\": 1.45, \"speedup\": 1.4563}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 8192, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.209, \"optimized\": 0.103, \"stated_speedup\": 2.03, \"speedup\": 2.0291}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 16384, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.198, \"optimized\": 0.14, \"stated_speedup\": 1.42, \"speedup\": 1.4143}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 16384, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.364, \"optimized\": 0.14, \"stated_speedup\": 2.61, \"speedup\": 2.6}]"},"kernel_speedup":{"kind":"number","value":1.245,"string":"1.245"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1181,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"99562e5eeaa26b08ba5e514bfe22d84404390ca6"},"date":{"kind":"string","value":"2026-02-06T16:01:50-08:00"},"pr_number":{"kind":"number","value":2398,"string":"2,398"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2398"},"title":{"kind":"string","value":"feat: cuteDSL fp4 moe for better DSR1 performance. (#2398)"},"message":{"kind":"string","value":"feat: cuteDSL fp4 moe for better DSR1 performance. (#2398)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\ncuteDSL fp4 moe from TRTLLM with fusion. issue #2259\nThe collective fusion performance improvement collected from TRTLLM [PR\n8880](https://github.com/NVIDIA/TensorRT-LLM/pull/8880), [PR\n9288](https://github.com/NVIDIA/TensorRT-LLM/pull/9288), [PR\n9618](https://github.com/NVIDIA/TensorRT-LLM/pull/9618),.\n\nIntroducing two new API for moe\n`cute_dsl_fused_moe_nvfp4`, `CuteDslMoEWrapper`. \nThe two API are functionally equivalent. The `cute_dsl_fused_moe_nvfp4`\nfunction could run the operation directly, while the wrapper API splits\ntensor setup and execution to better support cuda graph. Using wrapper\nAPI is recommended.\n\nThe PR also introduces autotune functionality for this function.\n\nPerformance data:\n```\n$ python benchmarks/bench_moe_deepseek.py --num-tokens 1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384\n====================================================================================================\nDeepSeek-V3 MoE Benchmark: CuteDSL vs CUTLASS vs TRTLLM (EP=1)\n====================================================================================================\nModel: hidden=7168, intermediate=2048, experts=256, top_k=8\nEP Config: 256 local experts (simulating 1-way parallelism)\nCUDA Graph: enabled, CUPTI: enabled\n----------------------------------------------------------------------------------------------------\nTokens | CuteDSL | CUTLASS | TRTLLM | Speedup (CuteDSL/X) | Winner\n | ms TFLOPS | ms TFLOPS | ms TFLOPS | CUTLASS TRTLLM |\n----------------------------------------------------------------------------------------------------\n 1 | 0.064 10.9 | 0.098 7.2 | 0.053 13.2 | 1.53x 0.83x | TRTLLM\n 2 | 0.077 18.2 | 0.109 13.0 | 0.064 21.9 | 1.40x 0.83x | TRTLLM\n 4 | 0.097 28.9 | 0.131 21.5 | 0.086 32.7 | 1.35x 0.88x | TRTLLM\n 8 | 0.098 57.5 | 0.133 42.4 | 0.092 61.4 | 1.36x 0.94x | TRTLLM\n 16 | 0.102 110.3 | 0.138 82.0 | 0.104 108.5 | 1.35x 1.02x | CuteDSL\n 32 | 0.115 196.3 | 0.153 146.9 | 0.138 163.4 | 1.34x 1.20x | CuteDSL\n 64 | 0.123 365.7 | 0.168 269.0 | 0.154 292.3 | 1.36x 1.25x | CuteDSL\n 128 | 0.134 674.3 | 0.217 416.0 | 0.174 519.4 | 1.62x 1.30x | CuteDSL\n 256 | 0.144 1252.3 | 0.250 723.0 | 0.220 821.3 | 1.73x 1.52x | CuteDSL\n 512 | 0.200 1802.3 | 0.336 1073.4 | 0.271 1331.9 | 1.68x 1.35x | CuteDSL\n 1024 | 0.286 2520.1 | 0.480 1501.8 | 0.570 1265.7 | 1.68x 1.99x | CuteDSL\n 2048 | 0.469 3073.8 | 0.722 1998.8 | 0.542 2660.6 | 1.54x 1.16x | CuteDSL\n 4096 | 0.852 3387.2 | 1.274 2266.0 | 0.845 3417.2 | 1.49x 0.99x | TRTLLM\n 8192 | 1.676 3444.7 | 2.364 2441.4 | 1.590 3630.7 | 1.41x 0.95x | TRTLLM\n 16384 | 3.290 3509.3 | 4.639 2488.8 | 3.383 3412.5 | 1.41x 1.03x | CuteDSL\n----------------------------------------------------------------------------------------------------\n\n$ python benchmarks/bench_moe_deepseek.py --num-tokens 1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384 --ep 16\n====================================================================================================\nDeepSeek-V3 MoE Benchmark: CuteDSL vs CUTLASS vs TRTLLM (EP=16)\n====================================================================================================\nModel: hidden=7168, intermediate=2048, experts=256, top_k=8\nEP Config: 16 local experts (simulating 16-way parallelism)\nCUDA Graph: enabled, CUPTI: enabled\n----------------------------------------------------------------------------------------------------\nTokens | CuteDSL | CUTLASS | TRTLLM | Speedup (CuteDSL/X) | Winner\n | ms TFLOPS | ms TFLOPS | ms TFLOPS | CUTLASS TRTLLM |\n----------------------------------------------------------------------------------------------------\n 1 | 0.021 2.1 | 0.024 1.8 | 0.018 2.5 | 1.16x 0.85x | TRTLLM\n 2 | 0.020 4.3 | 0.023 3.8 | 0.018 4.8 | 1.13x 0.90x | TRTLLM\n 4 | 0.020 8.6 | 0.024 7.4 | 0.019 9.2 | 1.16x 0.93x | TRTLLM\n 8 | 0.020 17.5 | 0.023 15.4 | 0.020 17.7 | 1.14x 0.99x | TRTLLM\n 16 | 0.021 33.9 | 0.024 29.9 | 0.022 32.8 | 1.13x 1.03x | CuteDSL\n 32 | 0.020 69.4 | 0.024 59.8 | 0.025 57.3 | 1.16x 1.21x | CuteDSL\n 64 | 0.022 129.2 | 0.024 118.7 | 0.025 112.1 | 1.09x 1.15x | CuteDSL\n 128 | 0.021 267.7 | 0.024 236.9 | 0.026 216.7 | 1.13x 1.24x | CuteDSL\n 256 | 0.023 487.3 | 0.025 456.4 | 0.027 411.6 | 1.07x 1.18x | CuteDSL\n 512 | 0.025 917.5 | 0.031 731.0 | 0.030 753.2 | 1.26x 1.22x | CuteDSL\n 1024 | 0.028 1638.6 | 0.036 1243.9 | 0.040 1137.0 | 1.32x 1.44x | CuteDSL\n 2048 | 0.036 2494.3 | 0.045 1988.4 | 0.061 1481.9 | 1.25x 1.68x | CuteDSL\n 4096 | 0.050 3597.4 | 0.061 2934.5 | 0.101 1794.7 | 1.23x 2.00x | CuteDSL\n 8192 | 0.103 3490.5 | 0.150 2409.6 | 0.209 1723.1 | 1.45x 2.03x | CuteDSL\n 16384 | 0.140 5160.4 | 0.198 3638.0 | 0.364 1980.6 | 1.42x 2.61x | CuteDSL\n----------------------------------------------------------------------------------------------------\n\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [ ] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n* Added comprehensive Mixture-of-Experts (MoE) support with FP4\nquantization for Blackwell GPUs.\n* Introduced multi-precision MoE kernels supporting FP16, BF16, FP8, and\nFP4 formats.\n* Added CUDA graph-compatible MoE APIs for improved performance and\nflexibility.\n * Implemented automatic kernel tuning for MoE operations.\n * Added expert parallelism support for distributed MoE inference.\n\n* **Documentation**\n* Added extensive test suite validating MoE functionality across\nprecision formats and configurations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: Alex Yang <aleyang@nvidia.com>\nCo-authored-by: Zihao Ye <expye@outlook.com>\nCo-authored-by: Jonathan Dierksen <1507580+dierksen@users.noreply.github.com>\nCo-authored-by: Claude Sonnet 4.5 <noreply@anthropic.com>\nCo-authored-by: Kangyan-Zhou <zky314343421@gmail.com>\nCo-authored-by: kahyun <69875166+kahyunnam@users.noreply.github.com>\nCo-authored-by: claude[bot] <41898282+claude[bot]@users.noreply.github.com>\nCo-authored-by: Zihao Ye <yzh119@users.noreply.github.com>"},"path":{"kind":"string","value":"flashinfer/gemm/kernels/grouped_gemm_masked_blackwell.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"BSD-3-Clause"},"before_code":{"kind":"string","value":"# Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: BSD-3-Clause\n\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are met:\n\n# 1. Redistributions of source code must retain the above copyright notice, this\n# list of conditions and the following disclaimer.\n\n# 2. Redistributions in binary form must reproduce the above copyright notice,\n# this list of conditions and the following disclaimer in the documentation\n# and/or other materials provided with the distribution.\n\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nfrom typing import Optional, Tuple, Type, Union\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nimport cutlass.torch as cutlass_torch\nimport cutlass.utils as utils\nimport cutlass.utils.blackwell_helpers as sm100_utils\nimport cutlass.utils.blockscaled_layout as blockscaled_utils\nimport torch\nimport functools\nfrom cutlass._mlir import ir\nfrom cutlass.cute.nvgpu import cpasync, tcgen05\nfrom cutlass.cute.runtime import from_dlpack\n\nfrom cutlass.cutlass_dsl import (\n Int32,\n Int64,\n Uint8,\n Uint64,\n T,\n Integer,\n dsl_user_op,\n extract_mlir_values,\n new_from_mlir_values,\n)\nfrom cutlass._mlir.dialects import llvm\nfrom flashinfer.utils import get_compute_capability\nfrom flashinfer.api_logging import flashinfer_api\nfrom cutlass.utils.static_persistent_tile_scheduler import WorkTileInfo\nfrom flashinfer.cute_dsl.utils import (\n get_cutlass_dtype,\n cutlass_to_torch_dtype,\n get_num_sm,\n make_ptr,\n)\nfrom typing import Callable, List\n\n\nsizeof_i32 = 4\n\n\n@dsl_user_op\ndef with_byte(obj: Uint64, index: Int32, value: Uint8, *, loc=None, ip=None) -> Uint64:\n obj &= ~(0xFF << (index * 8))\n obj |= value << (index * 8)\n assert isinstance(obj, Uint64), f\"{obj=}\"\n return obj\n\n\n@dsl_user_op\ndef read_byte(obj: Uint64, index: Int32, *, loc=None, ip=None) -> Uint8:\n return ((obj >> (index * 8)) & 0xFF).to(Uint8)\n\n\n@dsl_user_op\ndef atomic_add_release_global(addr: Int64, value: Int32, *, loc=None, ip=None) -> Int32:\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [\n addr.ir_value(loc=loc, ip=ip),\n Int32(value).ir_value(loc=loc, ip=ip),\n ],\n \"atom.add.release.gpu.global.s32 $0, [$1], $2;\",\n \"=r,l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\nclass MaskedSchedulerParams:\n def __init__(\n self,\n masked_m: cute.Tensor,\n dst_signals: Optional[cute.Pointer],\n c: cute.Tensor,\n c_tiler: Tuple[int, int],\n cluster_shape_mnk: cute.Shape,\n *,\n loc=None,\n ip=None,\n ):\n if cluster_shape_mnk[2] != 1:\n raise ValueError(f\"unsupported cluster_shape_k {cluster_shape_mnk[2]}\")\n\n gc = cute.zipped_divide(c, tiler=c_tiler)\n problem_shape_ntile_mnl = gc[(0, (None, None, None))].shape\n self.masked_m = masked_m\n self.dst_signals = dst_signals\n self.c = c\n self.c_tiler = c_tiler\n self.problem_shape_ntile_mnl = problem_shape_ntile_mnl\n # cluster_shape_mnk is kept for reconstruction\n self._cluster_shape_mnk = cluster_shape_mnk\n self.cluster_shape_mn = cluster_shape_mnk[:2]\n self._loc = loc\n\n self.problem_layout_ncluster_mnl = cute.make_layout(\n cute.ceil_div(\n self.problem_shape_ntile_mnl, cluster_shape_mnk[:2], loc=loc, ip=ip\n ),\n loc=loc,\n ip=ip,\n )\n\n def __extract_mlir_values__(self):\n values, self._values_pos = [], []\n for obj in [\n self.masked_m,\n self.dst_signals,\n self.c,\n self.c_tiler,\n self._cluster_shape_mnk,\n ]:\n obj_values = extract_mlir_values(obj)\n values += obj_values\n self._values_pos.append(len(obj_values))\n return values\n\n def __new_from_mlir_values__(self, values):\n obj_list = []\n for obj, n_items in zip(\n [\n self.masked_m,\n self.dst_signals,\n self.c,\n self.c_tiler,\n self._cluster_shape_mnk,\n ],\n self._values_pos,\n strict=True,\n ):\n obj_list.append(new_from_mlir_values(obj, values[:n_items]))\n values = values[n_items:]\n return MaskedSchedulerParams(*(tuple(obj_list)), loc=self._loc)\n\n @dsl_user_op\n def get_grid_shape(\n self, max_active_clusters: Int32, *, loc=None, ip=None\n ) -> Tuple[Integer, Integer, Integer]:\n num_persistent_clusters = max_active_clusters\n\n return (*self.cluster_shape_mn, num_persistent_clusters)\n\n\nclass MaskedScheduler:\n def __init__(\n self,\n params: MaskedSchedulerParams,\n num_persistent_clusters: Int32,\n current_work_linear_idx: Int32,\n current_batch_idx: Int32,\n accum_tile_m: Int32,\n cta_id_in_cluster: cute.Coord,\n num_tiles_executed: Int32,\n ):\n self.params = params\n self.num_persistent_clusters = num_persistent_clusters\n self._current_work_linear_idx = current_work_linear_idx\n self._current_batch_idx = current_batch_idx\n self._accum_tile_m = accum_tile_m\n self.cta_id_in_cluster = cta_id_in_cluster\n self._num_tiles_executed = num_tiles_executed\n\n def __extract_mlir_values__(self) -> list[ir.Value]:\n values = extract_mlir_values(self.num_persistent_clusters)\n values.extend(extract_mlir_values(self._current_work_linear_idx))\n values.extend(extract_mlir_values(self._current_batch_idx))\n values.extend(extract_mlir_values(self._accum_tile_m))\n values.extend(extract_mlir_values(self.cta_id_in_cluster))\n values.extend(extract_mlir_values(self._num_tiles_executed))\n return values\n\n def __new_from_mlir_values__(self, values: list[ir.Value]) -> \"MaskedScheduler\":\n assert len(values) == 8\n new_num_persistent_clusters = new_from_mlir_values(\n self.num_persistent_clusters, [values[0]]\n )\n new_current_work_linear_idx = new_from_mlir_values(\n self._current_work_linear_idx, [values[1]]\n )\n new_current_batch_idx = new_from_mlir_values(\n self._current_batch_idx, [values[2]]\n )\n new_accum_tile_m = new_from_mlir_values(self._accum_tile_m, [values[3]])\n new_cta_id_in_cluster = new_from_mlir_values(\n self.cta_id_in_cluster, values[4:7]\n )\n new_num_tiles_executed = new_from_mlir_values(\n self._num_tiles_executed, [values[7]]\n )\n return MaskedScheduler(\n self.params,\n new_num_persistent_clusters,\n new_current_work_linear_idx,\n new_current_batch_idx,\n new_accum_tile_m,\n new_cta_id_in_cluster,\n new_num_tiles_executed,\n )\n\n # called by host\n @dsl_user_op\n @staticmethod\n def create(\n params: MaskedSchedulerParams,\n block_idx: Tuple[Integer, Integer, Integer],\n grid_dim: Tuple[Integer, Integer, Integer],\n *,\n loc=None,\n ip=None,\n ):\n params = params\n\n # Calculate the number of persistent clusters by dividing the total grid size\n # by the number of CTAs per cluster\n num_persistent_clusters = cute.size(grid_dim, loc=loc, ip=ip) // cute.size(\n params.cluster_shape_mn, loc=loc, ip=ip\n )\n\n bidx, bidy, bidz = block_idx\n\n # Initialize workload index equals to the cluster index in the grid\n current_work_linear_idx = Int32(bidz)\n current_batch_idx = Int32(0)\n accum_tile_m = Int32(0)\n\n # CTA id in the cluster\n cta_id_in_cluster = (\n Int32(bidx % params.cluster_shape_mn[0]),\n Int32(bidy % params.cluster_shape_mn[1]),\n Int32(0),\n )\n # Initialize number of tiles executed to zero\n num_tiles_executed = Int32(0)\n return MaskedScheduler(\n params,\n num_persistent_clusters,\n current_work_linear_idx,\n current_batch_idx,\n accum_tile_m,\n cta_id_in_cluster,\n num_tiles_executed,\n )\n\n # called by host\n @staticmethod\n def get_grid_shape(\n params: MaskedSchedulerParams,\n max_active_clusters: Int32,\n *,\n loc=None,\n ip=None,\n ) -> Tuple[Integer, Integer, Integer]:\n return params.get_grid_shape(max_active_clusters, loc=loc, ip=ip)\n\n # private method\n @cute.jit\n def _get_current_work_for_linear_idx(\n self,\n current_work_linear_idx: Int32,\n dsm_pending_packed: Optional[Uint64],\n dsm_counter: Optional[Uint8],\n num_c_stage: Optional[int] = None,\n ) -> Tuple[WorkTileInfo, Optional[Uint64]]:\n # is_valid = current_work_linear_idx < cute.size(\n # self.params.problem_layout_ncluster_mnl, loc=loc, ip=ip\n # )\n num_tiles_n = self.params.problem_shape_ntile_mnl[1]\n accum_tile_m = self._accum_tile_m\n batch_idx = self._current_batch_idx\n\n while (\n (\n accum_tile_m\n + cute.ceil_div(self.params.masked_m[batch_idx], self.params.c_tiler[0])\n )\n * num_tiles_n\n <= current_work_linear_idx\n and batch_idx < self.params.masked_m.shape[0]\n ):\n if cutlass.const_expr(\n (dsm_pending_packed is not None)\n and (self.params.dst_signals is not None)\n ):\n dsm_pending_packed = with_byte(\n dsm_pending_packed,\n index=batch_idx,\n value=dsm_counter + (num_c_stage - 1),\n )\n\n accum_tile_m += cute.ceil_div(\n self.params.masked_m[batch_idx], self.params.c_tiler[0]\n )\n batch_idx += Int32(1)\n\n self._accum_tile_m = accum_tile_m\n self._current_batch_idx = batch_idx\n\n is_valid = self._current_batch_idx < self.params.masked_m.shape[0]\n if is_valid:\n is_valid = (\n self._accum_tile_m\n + cute.ceil_div(\n self.params.masked_m[self._current_batch_idx],\n self.params.c_tiler[0],\n )\n ) * num_tiles_n > current_work_linear_idx\n\n # cur_cluster_coord = self.params.problem_layout_ncluster_mnl.get_hier_coord(\n # current_work_linear_idx, loc=loc, ip=ip\n # )\n cur_cluster_coord = (\n current_work_linear_idx // num_tiles_n - self._accum_tile_m,\n current_work_linear_idx % num_tiles_n,\n self._current_batch_idx,\n )\n\n # cur_tile_coord is a tuple of i32 values\n cur_tile_coord = tuple(\n Int32(x) * Int32(z) + Int32(y)\n for x, y, z in zip(\n cur_cluster_coord,\n self.cta_id_in_cluster,\n (*self.params.cluster_shape_mn, Int32(1)),\n strict=True,\n )\n )\n\n return WorkTileInfo(cur_tile_coord, is_valid), dsm_pending_packed\n\n @dsl_user_op\n def get_current_work(\n self,\n dsm_pending_packed: Optional[Uint64] = None,\n dsm_counter: Optional[Uint8] = None,\n num_c_stage: Optional[int] = None,\n *,\n loc=None,\n ip=None,\n ) -> Tuple[WorkTileInfo, Optional[Uint64]]:\n return self._get_current_work_for_linear_idx(\n self._current_work_linear_idx,\n dsm_pending_packed=dsm_pending_packed,\n dsm_counter=dsm_counter,\n num_c_stage=num_c_stage,\n )\n\n @dsl_user_op\n def initial_work_tile_info(self, *, loc=None, ip=None) -> WorkTileInfo:\n tile_info, _ = self.get_current_work(loc=loc, ip=ip)\n return tile_info\n\n @dsl_user_op\n def advance_to_next_work(self, *, advance_count: int = 1, loc=None, ip=None):\n self._current_work_linear_idx += Int32(advance_count) * Int32(\n self.num_persistent_clusters\n )\n self._num_tiles_executed += Int32(1)\n\n @property\n def num_tiles_executed(self) -> Int32:\n return self._num_tiles_executed\n\n\n\"\"\"\nThis example provides an experimental implementation of the SM100 batched dense blockscaled GEMM kernel, please note that the APIs and implementation details related to this kernel may change in future releases.\n\nA high-performance persistent batched dense blockscaled GEMM example for the NVIDIA Blackwell SM100 architecture\nusing CUTE DSL.\n- Matrix A is MxKxL, L is batch dimension, A can be row-major(\"K\") or column-major(\"M\") for MXF8 input type and can only be row-major(\"K\") for MXF4/NVF4 input type\n- Matrix B is NxKxL, L is batch dimension, B can be row-major(\"N\") or column-major(\"K\") for MXF8 input type and can only be row-major(\"K\") for MXF4/NVF4 input type\n- Matrix C is MxNxL, L is batch dimension, C can be row-major(\"N\") or column-major(\"M\")\n- Matrix SFA layout is filled internally according to A shape and BlockScaledBasicChunk, which has M×ceil_div(K, sf_vec_size)×L elements respectively\n- Matrix SFB layout is filled internally according to B shape and BlockScaledBasicChunk, which has N×ceil_div(K, sf_vec_size)×L elements respectively\n\nThis GEMM kernel supports the following features:\n - Utilizes Tensor Memory Access (TMA) for efficient memory operations\n - Utilizes Blackwell's tcgen05.mma for matrix multiply-accumulate (MMA) operations (including 2cta mma instructions)\n - Implements TMA multicast with cluster to reduce L2 memory traffic\n - Support persistent tile scheduling to better overlap memory load/store with mma between tiles\n - Support warp specialization to avoid explicit pipelining between mainloop load and mma\n\nThis GEMM works as follows:\n1. DMA warp: Load A and B matrices from global memory (GMEM) to shared memory (SMEM) using TMA operations.\n2. MMA warp:\n - Load scale factor A/B from shared memory (SMEM) to tensor memory (TMEM) using tcgen05.cp instruction.\n - Perform matrix multiply-accumulate (MMA) operations using tcgen05.mma instruction.\n3. EPILOGUE warp:\n - Load completed accumulator from tensor memory (TMEM) to registers (RMEM) using tcgen05.ld.\n - Type convert C matrix to output type.\n - Optionally store C matrix from registers (RMEM) to shared memory (SMEM) to global memory (GMEM) with TMA operations,\n or directly store C matrix from registers (RMEM) to global memory (GMEM) without TMA operations.\n\nSM100 tcgen05.mma.kind.block_scale instructions operate as follows:\n- Read matrix A from SMEM\n- Read matrix B from SMEM\n- Read scalefactor A from TMEM\n- Read scalefactor B from TMEM\n- Write accumulator to TMEM\nThe accumulator in TMEM must then be loaded to registers before writing back to GMEM.\n\nInput arguments to this example is shown below:\n\n.. code-block:: bash\n\n python examples/blackwell/dense_blockscaled_gemm_persistent.py \\\n --ab_dtype Float4E2M1FN --sf_dtype Float8E8M0FNU --sf_vec_size 16 \\\n --c_dtype Float16 \\\n --mma_tiler_mn 256,128 --cluster_shape_mn 2,1 \\\n --mnkl 8192,8192,1024,1\n\nTo collect performance with NCU profiler:\n\n.. code-block:: bash\n\n ncu python examples/blackwell/dense_blockscaled_gemm_persistent.py \\\n --ab_dtype Float4E2M1FN --sf_dtype Float8E8M0FNU --sf_vec_size 16 \\\n --c_dtype Float16 \\\n --mma_tiler_mn 256,128 --cluster_shape_mn 2,1 \\\n --mnkl 8192,8192,1024,1 \\\n --warmup_iterations 1 --iterations 10 --skip_ref_check\n\n\nConstraints:\n* Supported input data types: mxf8, mxf4, nvf4\n see detailed valid dtype combinations in below Sm100BlockScaledPersistentDenseGemmKernel class documentation\n* A/B tensor must have the same data type, mixed data type is not supported (e.g., mxf8 x mxf4)\n* Mma tiler M must be 128 or 256(use_2cta_instrs)\n* Mma tiler N must be 128 or 256\n* Cluster shape M/N must be positive and power of 2, total cluster size <= 16\n* Cluster shape M must be multiple of 2 if Mma tiler M is 256(use_2cta_instrs)\n* The contiguous dimension of A/B/C tensors must be at least 16 bytes aligned,\n i.e, number of elements is a multiple of 16 and 32 for Float8 and Float4, respectively.\n\"\"\"\n\n\nclass Sm100BlockScaledPersistentDenseGemmKernel:\n \"\"\"This class implements batched matrix multiplication (C = A x SFA x B x SFB) with support for various data types\n and architectural features specific to Blackwell GPUs with persistent tile scheduling and warp specialization.\n\n :param sf_vec_size: Scalefactor vector size.\n :type sf_vec_size: int\n :param mma_tiler_mn: Shape of the Matrix Multiply-Accumulate (MMA) tile (M,N)\n :type mma_tiler_mn: Tuple[int, int]\n :param cluster_shape_mn: Cluster dimensions (M,N) for parallel processing\n :type cluster_shape_mn: Tuple[int, int]\n\n :note: In current version, A and B tensor must have the same data type\n - i.e., Float8E4M3FN for A and Float8E5M2 for B is not supported\n\n :note: Supported combinations of A/B data types, SF data typs and SF vector size:\n - MXF8: A/B: Float8E5M2/Float8E4M3FN + SF: Float8E8M0FNU + sf_vec_size: 32\n - MXF4: A/B: Float4E2M1FN + SF: Float8E8M0FNU + sf_vec_size: 32\n - NVF4: A/B: Float4E2M1FN + SF: Float8E8M0FNU/Float8E4M3FN + sf_vec_size: 16\n\n :note: Supported accumulator data types:\n - Float32\n\n :note: Supported C data types:\n - Float32\n - Float16/BFloat16\n - Float8E4M3FN/Float8E5M2\n :note: Constraints:\n - MMA tiler M must be 128 or 256 (use_2cta_instrs)\n - MMA tiler N must be 128/256\n - Cluster shape M must be multiple of 2 if Mma tiler M is 256\n - Cluster shape M/N must be positive and power of 2, total cluster size <= 16\n - Also, Cluster shape M/N must be <= 4 for scale factor multicasts due to limited size of scale factors\n\n Example:\n >>> gemm = Sm100BlockScaledPersistentDenseGemmKernel(\n ... sf_vec_size=16,\n ... mma_tiler_mn=(256, 128),\n ... cluster_shape_mn=(2, 1)\n ... )\n >>> gemm(a_tensor, b_tensor, sfa_tensor, sfb_tensor, c_tensor, max_active_clusters, stream)\n \"\"\"\n\n def __init__(\n self,\n sf_vec_size: int,\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n sm_version: str,\n ):\n \"\"\"Initializes the configuration for a Blackwell dense GEMM kernel.\n\n This configuration includes several key aspects:\n\n 1. MMA Instruction Settings (tcgen05):\n - acc_dtype: Data types for MMA accumulator, always set to Float32\n - sf_vec_size: Scalefactor A/B vector size.\n - mma_tiler_mn: The (M, N) shape of the MMA instruction tiler.\n\n 2. Cluster Shape:\n - cluster_shape_mn: The (ClusterM, ClusterN) shape of the CTA cluster.\n\n :param sf_vec_size: Scalefactor vector size.\n :type sf_vec_size: int\n :param mma_tiler_mn: Tuple (M, N) shape of the MMA instruction.\n :type mma_tiler_mn: Tuple[int, int]\n :param cluster_shape_mn: Tuple (ClusterM, ClusterN) shape of the cluster.\n :type cluster_shape_mn: Tuple[int, int]\n \"\"\"\n supported_sm_versions = [\"sm_100\", \"sm_103\"]\n assert sm_version in supported_sm_versions, (\n f\"{supported_sm_versions} are the only supported SM versions for cute-dsl backend, but encountered {sm_version}\"\n )\n\n self.acc_dtype = cutlass.Float32\n self.sf_vec_size = sf_vec_size\n self.use_2cta_instrs = mma_tiler_mn[0] == 256\n self.cluster_shape_mn = cluster_shape_mn\n # K dimension is deferred in _setup_attributes\n self.mma_tiler = (*mma_tiler_mn, 1)\n\n self.cta_group = (\n tcgen05.CtaGroup.TWO if self.use_2cta_instrs else tcgen05.CtaGroup.ONE\n )\n\n self.occupancy = 1\n # Set specialized warp ids\n self.epilog_warp_id = (\n 0,\n 1,\n 2,\n 3,\n )\n self.mma_warp_id = 4\n self.tma_warp_id = 5\n self.threads_per_warp = 32\n self.threads_per_cta = self.threads_per_warp * len(\n (self.mma_warp_id, self.tma_warp_id, *self.epilog_warp_id)\n )\n # Set barrier id for cta sync, epilogue sync and tmem ptr sync\n self.cta_sync_bar_id = 0\n self.epilog_sync_bar_id = 1\n self.tmem_ptr_sync_bar_id = 2\n self.smem_capacity = utils.get_smem_capacity_in_bytes(sm_version)\n SM100_TMEM_CAPACITY_COLUMNS = 512\n self.num_tmem_alloc_cols = SM100_TMEM_CAPACITY_COLUMNS\n\n def _setup_attributes(self):\n \"\"\"Set up configurations that are dependent on GEMM inputs\n\n This method configures various attributes based on the input tensor properties\n (data types, leading dimensions) and kernel settings:\n - Configuring tiled MMA\n - Computing MMA/cluster/tile shapes\n - Computing cluster layout\n - Computing multicast CTAs for A/B/SFA/SFB\n - Computing epilogue subtile\n - Setting up A/B/SFA/SFB/C stage counts in shared memory\n - Computing A/B/SFA/SFB/C shared memory layout\n - Computing tensor memory allocation columns\n \"\"\"\n # Compute mma instruction shapes\n mma_inst_bits_k = 256\n # (MMA_Tile_Shape_M, MMA_Tile_Shape_N, MMA_Inst_Shape_K)\n self.mma_inst_shape_mnk = (\n self.mma_tiler[0],\n self.mma_tiler[1],\n mma_inst_bits_k // self.a_dtype.width,\n )\n # (CTA_Tile_Shape_M, Round_Up(MMA_Tile_Shape_N, 128), MMA_Inst_Shape_K)\n self.mma_inst_shape_mnk_sfb = (\n self.mma_inst_shape_mnk[0] // (2 if self.use_2cta_instrs else 1),\n cute.round_up(self.mma_inst_shape_mnk[1], 128),\n self.mma_inst_shape_mnk[2],\n )\n\n tiled_mma = sm100_utils.make_blockscaled_trivial_tiled_mma(\n self.a_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.sf_dtype,\n self.sf_vec_size,\n self.cta_group,\n self.mma_inst_shape_mnk[:2],\n )\n\n tiled_mma_sfb = sm100_utils.make_blockscaled_trivial_tiled_mma(\n self.a_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.sf_dtype,\n self.sf_vec_size,\n cute.nvgpu.tcgen05.CtaGroup.ONE,\n self.mma_inst_shape_mnk_sfb[:2],\n )\n\n # Compute mma/cluster/tile shapes\n mma_inst_tile_k = 4\n self.mma_tiler = (\n self.mma_inst_shape_mnk[0],\n self.mma_inst_shape_mnk[1],\n self.mma_inst_shape_mnk[2] * mma_inst_tile_k,\n )\n self.mma_tiler_sfb = (\n self.mma_inst_shape_mnk_sfb[0],\n self.mma_inst_shape_mnk_sfb[1],\n self.mma_inst_shape_mnk_sfb[2] * mma_inst_tile_k,\n )\n self.cta_tile_shape_mnk = (\n self.mma_tiler[0] // cute.size(tiled_mma.thr_id.shape),\n self.mma_tiler[1],\n self.mma_tiler[2],\n )\n\n # Compute cluster layout\n self.cluster_layout_vmnk = cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)),\n (tiled_mma.thr_id.shape,),\n )\n self.cluster_layout_sfb_vmnk = cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)),\n (tiled_mma_sfb.thr_id.shape,),\n )\n\n # Compute number of multicast CTAs for A/B\n self.num_mcast_ctas_a = cute.size(self.cluster_layout_vmnk.shape[2])\n self.num_mcast_ctas_b = cute.size(self.cluster_layout_vmnk.shape[1])\n self.num_mcast_ctas_sfb = cute.size(self.cluster_layout_sfb_vmnk.shape[1])\n self.is_a_mcast = self.num_mcast_ctas_a > 1\n self.is_b_mcast = self.num_mcast_ctas_b > 1\n self.is_sfb_mcast = self.num_mcast_ctas_sfb > 1\n\n # Compute epilogue subtile\n self.epi_tile = sm100_utils.compute_epilogue_tile_shape(\n self.cta_tile_shape_mnk,\n self.use_2cta_instrs,\n self.c_layout,\n self.c_dtype,\n )\n\n # Setup A/B/C stage count in shared memory and ACC stage count in tensor memory\n self.num_acc_stage, self.num_ab_stage, self.num_c_stage = self._compute_stages(\n tiled_mma,\n self.mma_tiler,\n self.a_dtype,\n self.a_major_mode,\n self.b_dtype,\n self.b_major_mode,\n self.epi_tile,\n self.c_dtype,\n self.c_layout,\n self.sf_dtype,\n self.sf_vec_size,\n self.smem_capacity,\n self.occupancy,\n )\n\n # Compute A/B/SFA/SFB/C shared memory layout\n self.a_smem_layout_staged = sm100_utils.make_smem_layout_a(\n tiled_mma,\n self.mma_tiler,\n self.a_dtype,\n self.num_ab_stage,\n )\n self.b_smem_layout_staged = sm100_utils.make_smem_layout_b(\n tiled_mma,\n self.mma_tiler,\n self.b_dtype,\n self.num_ab_stage,\n )\n self.sfa_smem_layout_staged = blockscaled_utils.make_smem_layout_sfa(\n tiled_mma,\n self.mma_tiler,\n self.sf_vec_size,\n self.num_ab_stage,\n )\n self.sfb_smem_layout_staged = blockscaled_utils.make_smem_layout_sfb(\n tiled_mma,\n self.mma_tiler,\n self.sf_vec_size,\n self.num_ab_stage,\n )\n self.c_smem_layout_staged = sm100_utils.make_smem_layout_epi(\n self.c_dtype,\n self.c_layout,\n self.epi_tile,\n self.num_c_stage,\n )\n\n @cute.jit\n def __call__(\n self,\n a_tensor: cute.Tensor,\n b_tensor: cute.Tensor,\n sfa_tensor: cute.Tensor,\n sfb_tensor: cute.Tensor,\n c_tensor: cute.Tensor,\n masked_m_tensor: cute.Tensor,\n dst_signals: Optional[cute.Pointer],\n alpha_tensor: Optional[cute.Tensor],\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n ):\n \"\"\"Execute the GEMM operation in steps:\n - Setup static attributes before smem/grid/tma computation\n - Setup TMA load/store atoms and tensors\n - Compute grid size with regard to hardware constraints\n - Define shared storage for kernel\n - Launch the kernel synchronously\n\n :param a_tensor: Input tensor A\n :type a_tensor: cute.Tensor\n :param b_tensor: Input tensor B\n :type b_tensor: cute.Tensor\n :param sfa_tensor: Scale factor tensor A\n :type sfa_tensor: cute.Tensor\n :param sfb_tensor: Scale factor tensor B\n :type sfb_tensor: cute.Tensor\n :param c_tensor: Output tensor C\n :type c_tensor: cute.Tensor\n :param masked_m_tensor: Masked layout tensor M\n :type masked_m_tensor: cute.Tensor\n :param max_active_clusters: Maximum number of active clusters\n :type max_active_clusters: cutlass.Constexpr\n :param stream: CUDA stream for asynchronous execution\n :type stream: cuda.CUstream\n :param alpha_tensor: Optional 1D tensor of shape (l,) containing per-batch scaling factors.\n :type alpha_tensor: cute.Tensor\n :raises TypeError: If input data types are incompatible with the MMA instruction.\n \"\"\"\n # Setup static attributes before smem/grid/tma computation\n self.a_dtype: Type[cutlass.Numeric] = a_tensor.element_type\n self.b_dtype: Type[cutlass.Numeric] = b_tensor.element_type\n self.sf_dtype: Type[cutlass.Numeric] = sfa_tensor.element_type\n self.c_dtype: Type[cutlass.Numeric] = c_tensor.element_type\n self.a_major_mode = utils.LayoutEnum.from_tensor(a_tensor).mma_major_mode()\n self.b_major_mode = utils.LayoutEnum.from_tensor(b_tensor).mma_major_mode()\n self.c_layout = utils.LayoutEnum.from_tensor(c_tensor)\n\n # Check if input data types are compatible with MMA instruction\n if cutlass.const_expr(self.a_dtype != self.b_dtype):\n raise TypeError(f\"Type must match: {self.a_dtype} != {self.b_dtype}\")\n\n # Setup attributes that dependent on gemm inputs\n self._setup_attributes()\n\n # Setup sfa/sfb tensor by filling A/B tensor to scale factor atom layout\n # ((Atom_M, Rest_M),(Atom_K, Rest_K),RestL)\n sfa_layout = blockscaled_utils.tile_atom_to_shape_SF(\n a_tensor.shape, self.sf_vec_size\n )\n sfa_tensor = cute.make_tensor(sfa_tensor.iterator, sfa_layout)\n\n # ((Atom_N, Rest_N),(Atom_K, Rest_K),RestL)\n sfb_layout = blockscaled_utils.tile_atom_to_shape_SF(\n b_tensor.shape, self.sf_vec_size\n )\n sfb_tensor = cute.make_tensor(sfb_tensor.iterator, sfb_layout)\n\n tiled_mma = sm100_utils.make_blockscaled_trivial_tiled_mma(\n self.a_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.sf_dtype,\n self.sf_vec_size,\n self.cta_group,\n self.mma_inst_shape_mnk[:2],\n )\n\n tiled_mma_sfb = sm100_utils.make_blockscaled_trivial_tiled_mma(\n self.a_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.sf_dtype,\n self.sf_vec_size,\n cute.nvgpu.tcgen05.CtaGroup.ONE,\n self.mma_inst_shape_mnk_sfb[:2],\n )\n atom_thr_size = cute.size(tiled_mma.thr_id.shape)\n\n # Setup TMA load for A\n a_op = sm100_utils.cluster_shape_to_tma_atom_A(\n self.cluster_shape_mn, tiled_mma.thr_id\n )\n a_smem_layout = cute.slice_(self.a_smem_layout_staged, (None, None, None, 0))\n tma_atom_a, tma_tensor_a = cute.nvgpu.make_tiled_tma_atom_A(\n a_op,\n a_tensor,\n a_smem_layout,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n )\n\n # Setup TMA load for B\n b_op = sm100_utils.cluster_shape_to_tma_atom_B(\n self.cluster_shape_mn, tiled_mma.thr_id\n )\n b_smem_layout = cute.slice_(self.b_smem_layout_staged, (None, None, None, 0))\n tma_atom_b, tma_tensor_b = cute.nvgpu.make_tiled_tma_atom_B(\n b_op,\n b_tensor,\n b_smem_layout,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n )\n\n # Setup TMA load for SFA\n sfa_op = sm100_utils.cluster_shape_to_tma_atom_A(\n self.cluster_shape_mn, tiled_mma.thr_id\n )\n sfa_smem_layout = cute.slice_(\n self.sfa_smem_layout_staged, (None, None, None, 0)\n )\n tma_atom_sfa, tma_tensor_sfa = cute.nvgpu.make_tiled_tma_atom_A(\n sfa_op,\n sfa_tensor,\n sfa_smem_layout,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n internal_type=cutlass.Int16,\n )\n\n # Setup TMA load for SFB\n sfb_op = sm100_utils.cluster_shape_to_tma_atom_SFB(\n self.cluster_shape_mn, tiled_mma.thr_id\n )\n sfb_smem_layout = cute.slice_(\n self.sfb_smem_layout_staged, (None, None, None, 0)\n )\n tma_atom_sfb, tma_tensor_sfb = cute.nvgpu.make_tiled_tma_atom_B(\n sfb_op,\n sfb_tensor,\n sfb_smem_layout,\n self.mma_tiler_sfb,\n tiled_mma_sfb,\n self.cluster_layout_sfb_vmnk.shape,\n internal_type=cutlass.Int16,\n )\n\n a_copy_size = cute.size_in_bytes(self.a_dtype, a_smem_layout)\n b_copy_size = cute.size_in_bytes(self.b_dtype, b_smem_layout)\n sfa_copy_size = cute.size_in_bytes(self.sf_dtype, sfa_smem_layout)\n sfb_copy_size = cute.size_in_bytes(self.sf_dtype, sfb_smem_layout)\n self.num_tma_load_bytes = (\n a_copy_size + b_copy_size + sfa_copy_size + sfb_copy_size\n ) * atom_thr_size\n\n # Setup TMA store for C\n epi_smem_layout = cute.slice_(self.c_smem_layout_staged, (None, None, 0))\n tma_atom_c, tma_tensor_c = cpasync.make_tiled_tma_atom(\n cpasync.CopyBulkTensorTileS2GOp(),\n c_tensor,\n epi_smem_layout,\n self.epi_tile,\n )\n\n # Compute grid size\n self.tile_sched_params, grid = self._compute_grid(\n masked_m_tensor, # add masked layout\n dst_signals,\n c_tensor,\n self.cta_tile_shape_mnk,\n self.cluster_shape_mn,\n max_active_clusters,\n )\n\n self.buffer_align_bytes = 1024\n\n # Define shared storage for kernel\n @cute.struct\n class SharedStorage:\n ab_full_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_ab_stage]\n ab_empty_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_ab_stage]\n acc_full_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]\n acc_empty_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]\n tmem_dealloc_mbar_ptr: cutlass.Int64\n tmem_holding_buf: cutlass.Int32\n # (EPI_TILE_M, EPI_TILE_N, STAGE)\n sC: cute.struct.Align[\n cute.struct.MemRange[\n self.c_dtype,\n cute.cosize(self.c_smem_layout_staged.outer),\n ],\n self.buffer_align_bytes,\n ]\n # (MMA, MMA_M, MMA_K, STAGE)\n sA: cute.struct.Align[\n cute.struct.MemRange[\n self.a_dtype, cute.cosize(self.a_smem_layout_staged.outer)\n ],\n self.buffer_align_bytes,\n ]\n # (MMA, MMA_N, MMA_K, STAGE)\n sB: cute.struct.Align[\n cute.struct.MemRange[\n self.b_dtype, cute.cosize(self.b_smem_layout_staged.outer)\n ],\n self.buffer_align_bytes,\n ]\n # (MMA, MMA_M, MMA_K, STAGE)\n sSFA: cute.struct.Align[\n cute.struct.MemRange[\n self.sf_dtype, cute.cosize(self.sfa_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n # (MMA, MMA_N, MMA_K, STAGE)\n sSFB: cute.struct.Align[\n cute.struct.MemRange[\n self.sf_dtype, cute.cosize(self.sfb_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n # Launch the kernel synchronously\n self.kernel(\n tiled_mma,\n tiled_mma_sfb,\n tma_atom_a,\n tma_tensor_a,\n tma_atom_b,\n tma_tensor_b,\n tma_atom_sfa,\n tma_tensor_sfa,\n tma_atom_sfb,\n tma_tensor_sfb,\n tma_atom_c,\n tma_tensor_c,\n alpha_tensor,\n self.cluster_layout_vmnk,\n self.cluster_layout_sfb_vmnk,\n self.a_smem_layout_staged,\n self.b_smem_layout_staged,\n self.sfa_smem_layout_staged,\n self.sfb_smem_layout_staged,\n self.c_smem_layout_staged,\n self.epi_tile,\n self.tile_sched_params,\n ).launch(\n grid=grid,\n block=[self.threads_per_cta, 1, 1],\n cluster=(*self.cluster_shape_mn, 1),\n smem=self.shared_storage.size_in_bytes(), # type: ignore[attr-defined]\n stream=stream,\n )\n return\n\n # GPU device kernel\n @cute.kernel\n def kernel(\n self,\n tiled_mma: cute.TiledMma,\n tiled_mma_sfb: cute.TiledMma,\n tma_atom_a: cute.CopyAtom,\n mA_mkl: cute.Tensor,\n tma_atom_b: cute.CopyAtom,\n mB_nkl: cute.Tensor,\n tma_atom_sfa: cute.CopyAtom,\n mSFA_mkl: cute.Tensor,\n tma_atom_sfb: cute.CopyAtom,\n mSFB_nkl: cute.Tensor,\n tma_atom_c: Optional[cute.CopyAtom],\n mC_mnl: cute.Tensor,\n alpha: Optional[cute.Tensor],\n cluster_layout_vmnk: cute.Layout,\n cluster_layout_sfb_vmnk: cute.Layout,\n a_smem_layout_staged: cute.ComposedLayout,\n b_smem_layout_staged: cute.ComposedLayout,\n sfa_smem_layout_staged: cute.Layout,\n sfb_smem_layout_staged: cute.Layout,\n c_smem_layout_staged: Union[cute.Layout, cute.ComposedLayout, None],\n epi_tile: cute.Tile,\n tile_sched_params: MaskedSchedulerParams,\n ):\n \"\"\"\n GPU device kernel performing the Persistent batched GEMM computation.\n \"\"\"\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n\n #\n # Prefetch tma desc\n #\n if warp_idx == self.tma_warp_id:\n cpasync.prefetch_descriptor(tma_atom_a)\n cpasync.prefetch_descriptor(tma_atom_b)\n cpasync.prefetch_descriptor(tma_atom_sfa)\n cpasync.prefetch_descriptor(tma_atom_sfb)\n cpasync.prefetch_descriptor(tma_atom_c)\n\n use_2cta_instrs = cute.size(tiled_mma.thr_id.shape) == 2\n\n #\n # Setup cta/thread coordinates\n #\n # Coords inside cluster\n bidx, bidy, bidz = cute.arch.block_idx()\n mma_tile_coord_v = bidx % cute.size(tiled_mma.thr_id.shape)\n is_leader_cta = mma_tile_coord_v == 0\n cta_rank_in_cluster = cute.arch.make_warp_uniform(\n cute.arch.block_idx_in_cluster()\n )\n block_in_cluster_coord_vmnk = cluster_layout_vmnk.get_flat_coord(\n cta_rank_in_cluster\n )\n block_in_cluster_coord_sfb_vmnk = cluster_layout_sfb_vmnk.get_flat_coord(\n cta_rank_in_cluster\n )\n # Coord inside cta\n tidx, _, _ = cute.arch.thread_idx()\n\n #\n # Alloc and init: a+b full/empty, accumulator full/empty, tensor memory dealloc barrier\n #\n smem = utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n tmem_dealloc_mbar_ptr = storage.tmem_dealloc_mbar_ptr\n tmem_holding_buf = storage.tmem_holding_buf\n\n # Initialize mainloop ab_pipeline (barrier) and states\n ab_pipeline_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread)\n num_tma_producer = self.num_mcast_ctas_a + self.num_mcast_ctas_b - 1\n ab_pipeline_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, num_tma_producer\n )\n ab_pipeline = pipeline.PipelineTmaUmma.create(\n barrier_storage=storage.ab_full_mbar_ptr.data_ptr(),\n num_stages=self.num_ab_stage,\n producer_group=ab_pipeline_producer_group,\n consumer_group=ab_pipeline_consumer_group,\n tx_count=self.num_tma_load_bytes,\n cta_layout_vmnk=cluster_layout_vmnk,\n )\n\n # Initialize acc_pipeline (barrier) and states\n acc_pipeline_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread)\n num_acc_consumer_threads = (\n self.threads_per_warp\n * len(self.epilog_warp_id)\n * (2 if use_2cta_instrs else 1)\n )\n acc_pipeline_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, num_acc_consumer_threads\n )\n acc_pipeline = pipeline.PipelineUmmaAsync.create(\n barrier_storage=storage.acc_full_mbar_ptr.data_ptr(),\n num_stages=self.num_acc_stage,\n producer_group=acc_pipeline_producer_group,\n consumer_group=acc_pipeline_consumer_group,\n cta_layout_vmnk=cluster_layout_vmnk,\n )\n\n # Tensor memory dealloc barrier init\n if use_2cta_instrs:\n if warp_idx == self.tma_warp_id:\n num_tmem_dealloc_threads = 32\n with cute.arch.elect_one():\n cute.arch.mbarrier_init(\n tmem_dealloc_mbar_ptr, num_tmem_dealloc_threads\n )\n cute.arch.mbarrier_init_fence()\n\n # Cluster arrive after barrier init\n if cute.size(self.cluster_shape_mn) > 1:\n cute.arch.cluster_arrive_relaxed()\n\n #\n # Setup smem tensor A/B/SFA/SFB/C\n #\n # (EPI_TILE_M, EPI_TILE_N, STAGE)\n sC = storage.sC.get_tensor(\n c_smem_layout_staged.outer, swizzle=c_smem_layout_staged.inner\n )\n # (MMA, MMA_M, MMA_K, STAGE)\n sA = storage.sA.get_tensor(\n a_smem_layout_staged.outer, swizzle=a_smem_layout_staged.inner\n )\n # (MMA, MMA_N, MMA_K, STAGE)\n sB = storage.sB.get_tensor(\n b_smem_layout_staged.outer, swizzle=b_smem_layout_staged.inner\n )\n # (MMA, MMA_M, MMA_K, STAGE)\n sSFA = storage.sSFA.get_tensor(sfa_smem_layout_staged)\n # (MMA, MMA_N, MMA_K, STAGE)\n sSFB = storage.sSFB.get_tensor(sfb_smem_layout_staged)\n\n #\n # Compute multicast mask for A/B/SFA/SFB buffer full\n #\n a_full_mcast_mask = None\n b_full_mcast_mask = None\n sfa_full_mcast_mask = None\n sfb_full_mcast_mask = None\n if cutlass.const_expr(self.is_a_mcast or self.is_b_mcast or use_2cta_instrs):\n a_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=2\n )\n b_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=1\n )\n sfa_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=2\n )\n sfb_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_sfb_vmnk, block_in_cluster_coord_sfb_vmnk, mcast_mode=1\n )\n\n #\n # Local_tile partition global tensors\n #\n # (bM, bK, RestM, RestK, RestL)\n gA_mkl = cute.local_tile(\n mA_mkl, cute.slice_(self.mma_tiler, (None, 0, None)), (None, None, None)\n )\n # (bN, bK, RestN, RestK, RestL)\n gB_nkl = cute.local_tile(\n mB_nkl, cute.slice_(self.mma_tiler, (0, None, None)), (None, None, None)\n )\n # (bM, bK, RestM, RestK, RestL)\n gSFA_mkl = cute.local_tile(\n mSFA_mkl, cute.slice_(self.mma_tiler, (None, 0, None)), (None, None, None)\n )\n # (bN, bK, RestN, RestK, RestL)\n gSFB_nkl = cute.local_tile(\n mSFB_nkl, cute.slice_(self.mma_tiler, (0, None, None)), (None, None, None)\n )\n # (bM, bN, RestM, RestN, RestL)\n gC_mnl = cute.local_tile(\n mC_mnl, cute.slice_(self.mma_tiler, (None, None, 0)), (None, None, None)\n )\n k_block_cnt = cute.size(gA_mkl, mode=[3])\n\n #\n # Partition global tensor for TiledMMA_A/B/C\n #\n thr_mma = tiled_mma.get_slice(mma_tile_coord_v)\n thr_mma_sfb = tiled_mma_sfb.get_slice(mma_tile_coord_v)\n # (MMA, MMA_M, MMA_K, RestM, RestK, RestL)\n tCgA = thr_mma.partition_A(gA_mkl)\n # (MMA, MMA_N, MMA_K, RestN, RestK, RestL)\n tCgB = thr_mma.partition_B(gB_nkl)\n # (MMA, MMA_M, MMA_K, RestM, RestK, RestL)\n tCgSFA = thr_mma.partition_A(gSFA_mkl)\n # (MMA, MMA_N, MMA_K, RestN, RestK, RestL)\n tCgSFB = thr_mma_sfb.partition_B(gSFB_nkl)\n # (MMA, MMA_M, MMA_N, RestM, RestN, RestL)\n tCgC = thr_mma.partition_C(gC_mnl)\n\n #\n # Partition global/shared tensor for TMA load A/B\n #\n # TMA load A partition_S/D\n a_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_vmnk, (0, 0, None, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), RestM, RestK, RestL)\n tAsA, tAgA = cpasync.tma_partition(\n tma_atom_a,\n block_in_cluster_coord_vmnk[2],\n a_cta_layout,\n cute.group_modes(sA, 0, 3),\n cute.group_modes(tCgA, 0, 3),\n )\n # TMA load B partition_S/D\n b_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_vmnk, (0, None, 0, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), RestN, RestK, RestL)\n tBsB, tBgB = cpasync.tma_partition(\n tma_atom_b,\n block_in_cluster_coord_vmnk[1],\n b_cta_layout,\n cute.group_modes(sB, 0, 3),\n cute.group_modes(tCgB, 0, 3),\n )\n\n # TMA load SFA partition_S/D\n sfa_cta_layout = a_cta_layout\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), RestM, RestK, RestL)\n tAsSFA, tAgSFA = cute.nvgpu.cpasync.tma_partition(\n tma_atom_sfa,\n block_in_cluster_coord_vmnk[2],\n sfa_cta_layout,\n cute.group_modes(sSFA, 0, 3),\n cute.group_modes(tCgSFA, 0, 3),\n )\n tAsSFA = cute.filter_zeros(tAsSFA)\n tAgSFA = cute.filter_zeros(tAgSFA)\n\n # TMA load SFB partition_S/D\n sfb_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_sfb_vmnk, (0, None, 0, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), RestN, RestK, RestL)\n tBsSFB, tBgSFB = cute.nvgpu.cpasync.tma_partition(\n tma_atom_sfb,\n block_in_cluster_coord_sfb_vmnk[1],\n sfb_cta_layout,\n cute.group_modes(sSFB, 0, 3),\n cute.group_modes(tCgSFB, 0, 3),\n )\n tBsSFB = cute.filter_zeros(tBsSFB)\n tBgSFB = cute.filter_zeros(tBgSFB)\n\n #\n # Partition shared/tensor memory tensor for TiledMMA_A/B/C\n #\n # (MMA, MMA_M, MMA_K, STAGE)\n tCrA = tiled_mma.make_fragment_A(sA)\n # (MMA, MMA_N, MMA_K, STAGE)\n tCrB = tiled_mma.make_fragment_B(sB)\n # (MMA, MMA_M, MMA_N)\n acc_shape = tiled_mma.partition_shape_C(self.mma_tiler[:2])\n # (MMA, MMA_M, MMA_N, STAGE)\n tCtAcc_fake = tiled_mma.make_fragment_C(\n cute.append(acc_shape, self.num_acc_stage)\n )\n\n #\n # Cluster wait before tensor memory alloc\n #\n if cute.size(self.cluster_shape_mn) > 1:\n cute.arch.cluster_wait()\n else:\n cute.arch.barrier(\n barrier_id=self.cta_sync_bar_id, number_of_threads=self.threads_per_cta\n )\n\n #\n # Specialized TMA load warp\n #\n if warp_idx == self.tma_warp_id:\n #\n # Persistent tile scheduling loop\n #\n tile_sched = MaskedScheduler.create(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n ab_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_ab_stage\n )\n\n while work_tile.is_valid_tile:\n # Get tile coord from tile scheduler\n cur_tile_coord = work_tile.tile_idx\n mma_tile_coord_mnl = (\n cur_tile_coord[0] // cute.size(tiled_mma.thr_id.shape),\n cur_tile_coord[1],\n cur_tile_coord[2],\n )\n\n #\n # Slice to per mma tile index\n #\n # ((atom_v, rest_v), RestK)\n tAgA_slice = tAgA[\n (None, mma_tile_coord_mnl[0], None, mma_tile_coord_mnl[2])\n ]\n # ((atom_v, rest_v), RestK)\n tBgB_slice = tBgB[\n (None, mma_tile_coord_mnl[1], None, mma_tile_coord_mnl[2])\n ]\n\n # ((atom_v, rest_v), RestK)\n tAgSFA_slice = tAgSFA[\n (None, mma_tile_coord_mnl[0], None, mma_tile_coord_mnl[2])\n ]\n # ((atom_v, rest_v), RestK)\n tBgSFB_slice = tBgSFB[\n (None, mma_tile_coord_mnl[1], None, mma_tile_coord_mnl[2])\n ]\n\n # Peek (try_wait) AB buffer empty for k_block = prefetch_k_block_cnt\n ab_producer_state.reset_count()\n peek_ab_empty_status = cutlass.Boolean(1)\n if ab_producer_state.count < k_block_cnt:\n peek_ab_empty_status = ab_pipeline.producer_try_acquire(\n ab_producer_state\n )\n #\n # Tma load loop\n #\n for k_block in cutlass.range(0, k_block_cnt, 1, unroll=1): # noqa: B007\n # Conditionally wait for AB buffer empty\n ab_pipeline.producer_acquire(\n ab_producer_state, peek_ab_empty_status\n )\n\n # TMA load A/B/SFA/SFB\n cute.copy(\n tma_atom_a,\n tAgA_slice[(None, ab_producer_state.count)],\n tAsA[(None, ab_producer_state.index)],\n tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_producer_state),\n mcast_mask=a_full_mcast_mask,\n )\n cute.copy(\n tma_atom_b,\n tBgB_slice[(None, ab_producer_state.count)],\n tBsB[(None, ab_producer_state.index)],\n tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_producer_state),\n mcast_mask=b_full_mcast_mask,\n )\n cute.copy(\n tma_atom_sfa,\n tAgSFA_slice[(None, ab_producer_state.count)],\n tAsSFA[(None, ab_producer_state.index)],\n tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_producer_state),\n mcast_mask=sfa_full_mcast_mask,\n )\n cute.copy(\n tma_atom_sfb,\n tBgSFB_slice[(None, ab_producer_state.count)],\n tBsSFB[(None, ab_producer_state.index)],\n tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_producer_state),\n mcast_mask=sfb_full_mcast_mask,\n )\n\n # Peek (try_wait) AB buffer empty for k_block = prefetch_k_block_cnt + k_block + 1\n ab_producer_state.advance()\n peek_ab_empty_status = cutlass.Boolean(1)\n if ab_producer_state.count < k_block_cnt:\n peek_ab_empty_status = ab_pipeline.producer_try_acquire(\n ab_producer_state\n )\n\n #\n # Advance to next tile\n #\n tile_sched.advance_to_next_work()\n work_tile, _ = tile_sched.get_current_work()\n\n #\n # Wait A/B buffer empty\n #\n ab_pipeline.producer_tail(ab_producer_state)\n\n #\n # Specialized MMA warp\n #\n if warp_idx == self.mma_warp_id:\n #\n # Bar sync for retrieve tensor memory ptr from shared mem\n #\n tmem_ptr_read_threads = self.threads_per_warp * len(\n (self.mma_warp_id, *self.epilog_warp_id)\n )\n cute.arch.barrier(\n barrier_id=self.tmem_ptr_sync_bar_id,\n number_of_threads=tmem_ptr_read_threads,\n )\n\n #\n # Retrieving tensor memory ptr and make accumulator/SFA/SFB tensor\n #\n # Make accumulator tmem tensor\n acc_tmem_ptr = cute.arch.retrieve_tmem_ptr(\n self.acc_dtype,\n alignment=16,\n ptr_to_buffer_holding_addr=tmem_holding_buf,\n )\n # (MMA, MMA_M, MMA_N, STAGE)\n tCtAcc_base = cute.make_tensor(acc_tmem_ptr, tCtAcc_fake.layout)\n\n # Make SFA tmem tensor\n sfa_tmem_ptr = cute.recast_ptr(\n acc_tmem_ptr + tcgen05.find_tmem_tensor_col_offset(tCtAcc_base),\n dtype=self.sf_dtype,\n )\n # (MMA, MMA_M, MMA_K)\n tCtSFA_layout = blockscaled_utils.make_tmem_layout_sfa(\n tiled_mma,\n self.mma_tiler,\n self.sf_vec_size,\n cute.slice_(sfa_smem_layout_staged, (None, None, None, 0)),\n )\n tCtSFA = cute.make_tensor(sfa_tmem_ptr, tCtSFA_layout)\n\n # Make SFB tmem tensor\n sfb_tmem_ptr = cute.recast_ptr(\n acc_tmem_ptr\n + tcgen05.find_tmem_tensor_col_offset(tCtAcc_base)\n + tcgen05.find_tmem_tensor_col_offset(tCtSFA),\n dtype=self.sf_dtype,\n )\n # (MMA, MMA_N, MMA_K)\n tCtSFB_layout = blockscaled_utils.make_tmem_layout_sfb(\n tiled_mma,\n self.mma_tiler,\n self.sf_vec_size,\n cute.slice_(sfb_smem_layout_staged, (None, None, None, 0)),\n )\n tCtSFB = cute.make_tensor(sfb_tmem_ptr, tCtSFB_layout)\n #\n # Partition for S2T copy of SFA/SFB\n #\n tiled_copy_s2t_sfa, tCsSFA_compact_s2t, tCtSFA_compact_s2t = (\n self.mainloop_s2t_copy_and_partition(sSFA, tCtSFA)\n )\n tiled_copy_s2t_sfb, tCsSFB_compact_s2t, tCtSFB_compact_s2t = (\n self.mainloop_s2t_copy_and_partition(sSFB, tCtSFB)\n )\n\n #\n # Persistent tile scheduling loop\n #\n tile_sched = MaskedScheduler.create(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n ab_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_ab_stage\n )\n acc_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_acc_stage\n )\n\n while work_tile.is_valid_tile:\n # Get tile coord from tile scheduler\n cur_tile_coord = work_tile.tile_idx\n mma_tile_coord_mnl = (\n cur_tile_coord[0] // cute.size(tiled_mma.thr_id.shape),\n cur_tile_coord[1],\n cur_tile_coord[2],\n )\n\n # Set tensor memory buffer for current tile\n # (MMA, MMA_M, MMA_N)\n tCtAcc = tCtAcc_base[(None, None, None, acc_producer_state.index)]\n\n # Peek (try_wait) AB buffer full for k_block = 0\n ab_consumer_state.reset_count()\n peek_ab_full_status = cutlass.Boolean(1)\n if ab_consumer_state.count < k_block_cnt and is_leader_cta:\n peek_ab_full_status = ab_pipeline.consumer_try_wait(\n ab_consumer_state\n )\n\n #\n # Wait for accumulator buffer empty\n #\n if is_leader_cta:\n acc_pipeline.producer_acquire(acc_producer_state)\n\n #\n # Reset the ACCUMULATE field for each tile\n #\n tiled_mma.set(tcgen05.Field.ACCUMULATE, False)\n\n #\n # Mma mainloop\n #\n for k_block in cutlass.range_constexpr(k_block_cnt): # noqa: B007\n if is_leader_cta:\n # Conditionally wait for AB buffer full\n ab_pipeline.consumer_wait(\n ab_consumer_state, peek_ab_full_status\n )\n\n # Copy SFA/SFB from smem to tmem\n s2t_stage_coord = (\n None,\n None,\n None,\n None,\n ab_consumer_state.index,\n )\n tCsSFA_compact_s2t_staged = tCsSFA_compact_s2t[s2t_stage_coord]\n tCsSFB_compact_s2t_staged = tCsSFB_compact_s2t[s2t_stage_coord]\n cute.copy(\n tiled_copy_s2t_sfa,\n tCsSFA_compact_s2t_staged,\n tCtSFA_compact_s2t,\n )\n cute.copy(\n tiled_copy_s2t_sfb,\n tCsSFB_compact_s2t_staged,\n tCtSFB_compact_s2t,\n )\n\n # tCtAcc += tCrA * tCrSFA * tCrB * tCrSFB\n num_kphases = cute.size(tCrA, mode=[2])\n for kphase_idx in cutlass.range(num_kphases, unroll_full=True):\n kphase_coord = (\n None,\n None,\n kphase_idx,\n ab_consumer_state.index,\n )\n\n # Set SFA/SFB tensor to tiled_mma\n sf_kphase_coord = (None, None, kphase_idx)\n tiled_mma.set(\n tcgen05.Field.SFA,\n tCtSFA[sf_kphase_coord].iterator,\n )\n tiled_mma.set(\n tcgen05.Field.SFB,\n tCtSFB[sf_kphase_coord].iterator,\n )\n\n cute.gemm(\n tiled_mma,\n tCtAcc,\n tCrA[kphase_coord],\n tCrB[kphase_coord],\n tCtAcc,\n )\n\n # Enable accumulate on tCtAcc after first kphase\n tiled_mma.set(tcgen05.Field.ACCUMULATE, True)\n\n # Async arrive AB buffer empty\n ab_pipeline.consumer_release(ab_consumer_state)\n\n # Peek (try_wait) AB buffer full for k_block = k_block + 1\n ab_consumer_state.advance()\n peek_ab_full_status = cutlass.Boolean(1)\n if ab_consumer_state.count < k_block_cnt:\n if is_leader_cta:\n peek_ab_full_status = ab_pipeline.consumer_try_wait(\n ab_consumer_state\n )\n\n #\n # Async arrive accumulator buffer full\n #\n if is_leader_cta:\n acc_pipeline.producer_commit(acc_producer_state)\n acc_producer_state.advance()\n\n #\n # Advance to next tile\n #\n tile_sched.advance_to_next_work()\n work_tile, _ = tile_sched.get_current_work()\n\n #\n # Wait for accumulator buffer empty\n #\n acc_pipeline.producer_tail(acc_producer_state)\n #\n # Specialized epilogue warps\n #\n if warp_idx < self.mma_warp_id:\n #\n # Alloc tensor memory buffer\n #\n if warp_idx == self.epilog_warp_id[0]:\n cute.arch.alloc_tmem(\n self.num_tmem_alloc_cols,\n tmem_holding_buf,\n is_two_cta=use_2cta_instrs,\n )\n\n #\n # Bar sync for retrieve tensor memory ptr from shared memory\n #\n tmem_ptr_read_threads = self.threads_per_warp * len(\n (self.mma_warp_id, *self.epilog_warp_id)\n )\n cute.arch.barrier(\n barrier_id=self.tmem_ptr_sync_bar_id,\n number_of_threads=tmem_ptr_read_threads,\n )\n\n #\n # Retrieving tensor memory ptr and make accumulator tensor\n #\n acc_tmem_ptr = cute.arch.retrieve_tmem_ptr(\n self.acc_dtype,\n alignment=16,\n ptr_to_buffer_holding_addr=tmem_holding_buf,\n )\n # (MMA, MMA_M, MMA_N, STAGE)\n tCtAcc_base = cute.make_tensor(acc_tmem_ptr, tCtAcc_fake.layout)\n\n #\n # Partition for epilogue\n #\n epi_tidx = tidx\n tiled_copy_t2r, tTR_tAcc_base, tTR_rAcc = (\n self.epilog_tmem_copy_and_partition(\n epi_tidx, tCtAcc_base, tCgC, epi_tile, use_2cta_instrs\n )\n )\n\n tTR_rC = cute.make_fragment(tTR_rAcc.shape, self.c_dtype)\n tiled_copy_r2s, tRS_rC, tRS_sC = self.epilog_smem_copy_and_partition(\n tiled_copy_t2r, tTR_rC, epi_tidx, sC\n )\n tma_atom_c, bSG_sC, bSG_gC_partitioned = (\n self.epilog_gmem_copy_and_partition(\n epi_tidx, tma_atom_c, tCgC, epi_tile, sC\n )\n )\n\n #\n # Persistent tile scheduling loop\n #\n tile_sched = MaskedScheduler.create(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n acc_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_acc_stage\n )\n\n # Threads/warps participating in tma store pipeline\n c_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n self.threads_per_warp * len(self.epilog_warp_id),\n self.threads_per_warp * len(self.epilog_warp_id),\n )\n c_pipeline = pipeline.PipelineTmaStore.create(\n num_stages=self.num_c_stage,\n producer_group=c_producer_group,\n )\n\n if cutlass.const_expr(tile_sched_params.dst_signals is not None):\n assert self.num_c_stage < 256, \"must be representable in 1 byte\"\n num_experts = tile_sched_params.masked_m.shape[0]\n assert num_experts <= 8, \"need to be packable into a u64\"\n dsm_pending_packed = Uint64(0)\n dsm_pending_idx = Int32(0)\n dsm_counter = Uint8(0)\n\n while work_tile.is_valid_tile:\n # Get tile coord from tile scheduler\n cur_tile_coord = work_tile.tile_idx\n mma_tile_coord_mnl = (\n cur_tile_coord[0] // cute.size(tiled_mma.thr_id.shape),\n cur_tile_coord[1],\n cur_tile_coord[2],\n )\n\n #\n # Slice to per mma tile index\n #\n # ((ATOM_V, REST_V), EPI_M, EPI_N)\n bSG_gC = bSG_gC_partitioned[\n (\n None,\n None,\n None,\n *mma_tile_coord_mnl,\n )\n ]\n\n # Set tensor memory buffer for current tile\n # (T2R, T2R_M, T2R_N, EPI_M, EPI_M)\n tTR_tAcc = tTR_tAcc_base[\n (None, None, None, None, None, acc_consumer_state.index)\n ]\n\n #\n # Wait for accumulator buffer full\n #\n acc_pipeline.consumer_wait(acc_consumer_state)\n\n tTR_tAcc = cute.group_modes(tTR_tAcc, 3, cute.rank(tTR_tAcc))\n bSG_gC = cute.group_modes(bSG_gC, 1, cute.rank(bSG_gC))\n\n #\n # Store accumulator to global memory in subtiles\n #\n subtile_cnt = cute.size(tTR_tAcc.shape, mode=[3])\n num_prev_subtiles = tile_sched.num_tiles_executed * subtile_cnt\n for subtile_idx in cutlass.range(subtile_cnt):\n #\n # Load accumulator from tensor memory buffer to register\n #\n tTR_tAcc_mn = tTR_tAcc[(None, None, None, subtile_idx)]\n cute.copy(tiled_copy_t2r, tTR_tAcc_mn, tTR_rAcc)\n\n #\n # Convert to C type\n #\n acc_vec = tiled_copy_r2s.retile(tTR_rAcc).load()\n if cutlass.const_expr(alpha is not None):\n acc_vec = acc_vec * alpha[work_tile.tile_idx[2]]\n\n acc_vec = acc_vec.to(self.c_dtype)\n tRS_rC.store(acc_vec)\n\n #\n # Store C to shared memory\n #\n c_buffer = (num_prev_subtiles + subtile_idx) % self.num_c_stage\n cute.copy(\n tiled_copy_r2s,\n tRS_rC,\n tRS_sC[(None, None, None, c_buffer)],\n )\n # Fence and barrier to make sure shared memory store is visible to TMA store\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n epilog_threads = self.threads_per_warp * len(self.epilog_warp_id)\n cute.arch.barrier(\n barrier_id=self.epilog_sync_bar_id,\n number_of_threads=epilog_threads,\n )\n\n #\n # TMA store C to global memory\n #\n if warp_idx == self.epilog_warp_id[0]:\n cute.copy(\n tma_atom_c,\n bSG_sC[(None, c_buffer)],\n bSG_gC[(None, subtile_idx)],\n )\n\n # Fence and barrier to make sure shared memory store is visible to TMA store\n c_pipeline.producer_commit()\n\n if cutlass.const_expr(\n tile_sched_params.dst_signals is not None\n ):\n dsm_counter = (dsm_counter + 1).to(Uint8)\n will_write_signals = (\n read_byte(dsm_pending_packed, dsm_pending_idx)\n == dsm_counter\n )\n\n if will_write_signals:\n # The original c_pipeline.producer_acquire()\n # := PipelineTmaStore.producer_acquire()\n # := TmaStoreFence.wait()\n # := cute.arch.cp_async_bulk_wait_group(self.num_stages - 1, read=True)\n cute.arch.cp_async_bulk_wait_group(\n self.num_c_stage - 1,\n # Change `read` from True to False to also wait writes\n read=False,\n )\n else:\n c_pipeline.producer_acquire()\n\n else:\n c_pipeline.producer_acquire()\n\n cute.arch.barrier(\n barrier_id=self.epilog_sync_bar_id,\n number_of_threads=epilog_threads,\n )\n\n if cutlass.const_expr(tile_sched_params.dst_signals is not None):\n lane_id = tidx % 32\n if warp_idx == self.epilog_warp_id[0] and lane_id == 0:\n while (dsm_pending_idx < num_experts) and (\n read_byte(dsm_pending_packed, dsm_pending_idx)\n == dsm_counter\n ):\n atomic_add_release_global(\n tile_sched_params.dst_signals.toint()\n + sizeof_i32 * dsm_pending_idx,\n value=1,\n )\n dsm_pending_idx += 1\n\n #\n # Async arrive accumulator buffer empty\n #\n acc_pipeline.consumer_release(acc_consumer_state)\n acc_consumer_state.advance()\n\n #\n # Advance to next tile\n #\n tile_sched.advance_to_next_work()\n work_tile, dsm_pending_packed = tile_sched.get_current_work(\n dsm_pending_packed=dsm_pending_packed,\n dsm_counter=dsm_counter,\n num_c_stage=self.num_c_stage,\n )\n\n #\n # Dealloc the tensor memory buffer\n #\n if warp_idx == self.epilog_warp_id[0]:\n cute.arch.relinquish_tmem_alloc_permit(is_two_cta=use_2cta_instrs)\n epilog_threads = self.threads_per_warp * len(self.epilog_warp_id)\n cute.arch.barrier(\n barrier_id=self.epilog_sync_bar_id, number_of_threads=epilog_threads\n )\n if warp_idx == self.epilog_warp_id[0]:\n if use_2cta_instrs:\n cute.arch.mbarrier_arrive(\n tmem_dealloc_mbar_ptr, cta_rank_in_cluster ^ 1\n )\n cute.arch.mbarrier_wait(tmem_dealloc_mbar_ptr, 0)\n cute.arch.dealloc_tmem(\n acc_tmem_ptr, self.num_tmem_alloc_cols, is_two_cta=use_2cta_instrs\n )\n #\n # Wait for C store complete\n #\n if cutlass.const_expr(tile_sched_params.dst_signals is not None):\n # The original c_pipeline.producer_tail()\n # := PipelineTmaStore.producer_tail()\n # := TmaStoreFence.tail()\n # := cute.arch.cp_async_bulk_wait_group(0, read=True)\n cute.arch.cp_async_bulk_wait_group(\n 0,\n # Change `read` from True to False to also wait writes\n read=False,\n )\n\n lane_id = tidx % 32\n if warp_idx == self.epilog_warp_id[0] and lane_id == 0:\n while dsm_pending_idx < num_experts:\n atomic_add_release_global(\n tile_sched_params.dst_signals.toint()\n + sizeof_i32 * dsm_pending_idx,\n value=1,\n )\n dsm_pending_idx += 1\n\n else:\n c_pipeline.producer_tail()\n\n def mainloop_s2t_copy_and_partition(\n self,\n sSF: cute.Tensor,\n tSF: cute.Tensor,\n ) -> Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]:\n \"\"\"\n Make tiledCopy for smem to tmem load for scale factor tensor, then use it to partition smem memory (source) and tensor memory (destination).\n\n :param sSF: The scale factor tensor in smem\n :type sSF: cute.Tensor\n :param tSF: The scale factor tensor in tmem\n :type tSF: cute.Tensor\n\n :return: A tuple containing (tiled_copy_s2t, tCsSF_compact_s2t, tCtSF_compact_s2t) where:\n - tiled_copy_s2t: The tiled copy operation for smem to tmem load for scale factor tensor(s2t)\n - tCsSF_compact_s2t: The partitioned scale factor tensor in smem\n - tSF_compact_s2t: The partitioned scale factor tensor in tmem\n :rtype: Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]\n \"\"\"\n # (MMA, MMA_MN, MMA_K, STAGE)\n tCsSF_compact = cute.filter_zeros(sSF)\n # (MMA, MMA_MN, MMA_K)\n tCtSF_compact = cute.filter_zeros(tSF)\n\n # Make S2T CopyAtom and tiledCopy\n copy_atom_s2t = cute.make_copy_atom(\n tcgen05.Cp4x32x128bOp(self.cta_group),\n self.sf_dtype,\n )\n tiled_copy_s2t = tcgen05.make_s2t_copy(copy_atom_s2t, tCtSF_compact)\n thr_copy_s2t = tiled_copy_s2t.get_slice(0)\n\n # ((ATOM_V, REST_V), Rest_Tiler, MMA_MN, MMA_K, STAGE)\n tCsSF_compact_s2t_ = thr_copy_s2t.partition_S(tCsSF_compact)\n # ((ATOM_V, REST_V), Rest_Tiler, MMA_MN, MMA_K, STAGE)\n tCsSF_compact_s2t = tcgen05.get_s2t_smem_desc_tensor(\n tiled_copy_s2t, tCsSF_compact_s2t_\n )\n # ((ATOM_V, REST_V), Rest_Tiler, MMA_MN, MMA_K)\n tCtSF_compact_s2t = thr_copy_s2t.partition_D(tCtSF_compact)\n\n return tiled_copy_s2t, tCsSF_compact_s2t, tCtSF_compact_s2t\n\n def epilog_tmem_copy_and_partition(\n self,\n tidx: cutlass.Int32,\n tAcc: cute.Tensor,\n gC_mnl: cute.Tensor,\n epi_tile: cute.Tile,\n use_2cta_instrs: Union[cutlass.Boolean, bool],\n ) -> Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]:\n \"\"\"\n Make tiledCopy for tensor memory load, then use it to partition tensor memory (source) and register array (destination).\n\n :param tidx: The thread index in epilogue warp groups\n :type tidx: cutlass.Int32\n :param tAcc: The accumulator tensor to be copied and partitioned\n :type tAcc: cute.Tensor\n :param gC_mnl: The global tensor C\n :type gC_mnl: cute.Tensor\n :param epi_tile: The epilogue tiler\n :type epi_tile: cute.Tile\n :param use_2cta_instrs: Whether use_2cta_instrs is enabled\n :type use_2cta_instrs: bool\n\n :return: A tuple containing (tiled_copy_t2r, tTR_tAcc, tTR_rAcc) where:\n - tiled_copy_t2r: The tiled copy operation for tmem to register copy(t2r)\n - tTR_tAcc: The partitioned accumulator tensor\n - tTR_rAcc: The accumulated tensor in register used to hold t2r results\n :rtype: Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]\n \"\"\"\n # Make tiledCopy for tensor memory load\n copy_atom_t2r = sm100_utils.get_tmem_load_op(\n self.cta_tile_shape_mnk,\n self.c_layout,\n self.c_dtype,\n self.acc_dtype,\n epi_tile,\n use_2cta_instrs,\n )\n # (EPI_TILE_M, EPI_TILE_N, EPI_M, EPI_N, STAGE)\n tAcc_epi = cute.flat_divide(\n tAcc[((None, None), 0, 0, None)],\n epi_tile,\n )\n # (EPI_TILE_M, EPI_TILE_N)\n tiled_copy_t2r = tcgen05.make_tmem_copy(\n copy_atom_t2r, tAcc_epi[(None, None, 0, 0, 0)]\n )\n\n thr_copy_t2r = tiled_copy_t2r.get_slice(tidx)\n # (T2R, T2R_M, T2R_N, EPI_M, EPI_M, STAGE)\n tTR_tAcc = thr_copy_t2r.partition_S(tAcc_epi)\n\n # (EPI_TILE_M, EPI_TILE_N, EPI_M, EPI_N, RestM, RestN, RestL)\n gC_mnl_epi = cute.flat_divide(\n gC_mnl[((None, None), 0, 0, None, None, None)], epi_tile\n )\n # (T2R, T2R_M, T2R_N, EPI_M, EPI_N, RestM, RestN, RestL)\n tTR_gC = thr_copy_t2r.partition_D(gC_mnl_epi)\n # (T2R, T2R_M, T2R_N)\n tTR_rAcc = cute.make_fragment(\n tTR_gC[(None, None, None, 0, 0, 0, 0, 0)].shape, self.acc_dtype\n )\n return tiled_copy_t2r, tTR_tAcc, tTR_rAcc\n\n def epilog_smem_copy_and_partition(\n self,\n tiled_copy_t2r: cute.TiledCopy,\n tTR_rC: cute.Tensor,\n tidx: cutlass.Int32,\n sC: cute.Tensor,\n ) -> Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]:\n \"\"\"\n Make tiledCopy for shared memory store, then use it to partition register array (source) and shared memory (destination).\n\n :param tiled_copy_t2r: The tiled copy operation for tmem to register copy(t2r)\n :type tiled_copy_t2r: cute.TiledCopy\n :param tTR_rC: The partitioned accumulator tensor\n :type tTR_rC: cute.Tensor\n :param tidx: The thread index in epilogue warp groups\n :type tidx: cutlass.Int32\n :param sC: The shared memory tensor to be copied and partitioned\n :type sC: cute.Tensor\n :type sepi: cute.Tensor\n\n :return: A tuple containing (tiled_copy_r2s, tRS_rC, tRS_sC) where:\n - tiled_copy_r2s: The tiled copy operation for register to smem copy(r2s)\n - tRS_rC: The partitioned tensor C (register source)\n - tRS_sC: The partitioned tensor C (smem destination)\n :rtype: Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]\n \"\"\"\n copy_atom_r2s = sm100_utils.get_smem_store_op(\n self.c_layout, self.c_dtype, self.acc_dtype, tiled_copy_t2r\n )\n tiled_copy_r2s = cute.make_tiled_copy_D(copy_atom_r2s, tiled_copy_t2r)\n # (R2S, R2S_M, R2S_N, PIPE_D)\n thr_copy_r2s = tiled_copy_r2s.get_slice(tidx)\n tRS_sC = thr_copy_r2s.partition_D(sC)\n # (R2S, R2S_M, R2S_N)\n tRS_rC = tiled_copy_r2s.retile(tTR_rC)\n return tiled_copy_r2s, tRS_rC, tRS_sC\n\n def epilog_gmem_copy_and_partition(\n self,\n tidx: cutlass.Int32,\n atom: Union[cute.CopyAtom, cute.TiledCopy],\n gC_mnl: cute.Tensor,\n epi_tile: cute.Tile,\n sC: cute.Tensor,\n ) -> Tuple[cute.CopyAtom, cute.Tensor, cute.Tensor]:\n \"\"\"Make tiledCopy for global memory store, then use it to:\n partition shared memory (source) and global memory (destination) for TMA store version.\n\n :param tidx: The thread index in epilogue warp groups\n :type tidx: cutlass.Int32\n :param atom: The copy_atom_c to be used for TMA store version, or tiled_copy_t2r for none TMA store version\n :type atom: cute.CopyAtom or cute.TiledCopy\n :param gC_mnl: The global tensor C\n :type gC_mnl: cute.Tensor\n :param epi_tile: The epilogue tiler\n :type epi_tile: cute.Tile\n :param sC: The shared memory tensor to be copied and partitioned\n :type sC: cute.Tensor\n\n :return: A tuple containing (tma_atom_c, bSG_sC, bSG_gC) where:\n - tma_atom_c: The TMA copy atom\n - bSG_sC: The partitioned shared memory tensor C\n - bSG_gC: The partitioned global tensor C\n :rtype: Tuple[cute.CopyAtom, cute.Tensor, cute.Tensor]\n \"\"\"\n # (EPI_TILE_M, EPI_TILE_N, EPI_M, EPI_N, RestM, RestN, RestL)\n gC_epi = cute.flat_divide(\n gC_mnl[((None, None), 0, 0, None, None, None)], epi_tile\n )\n\n tma_atom_c = atom\n sC_for_tma_partition = cute.group_modes(sC, 0, 2)\n gC_for_tma_partition = cute.group_modes(gC_epi, 0, 2)\n # ((ATOM_V, REST_V), EPI_M, EPI_N)\n # ((ATOM_V, REST_V), EPI_M, EPI_N, RestM, RestN, RestL)\n bSG_sC, bSG_gC = cpasync.tma_partition(\n tma_atom_c,\n 0,\n cute.make_layout(1),\n sC_for_tma_partition,\n gC_for_tma_partition,\n )\n return tma_atom_c, bSG_sC, bSG_gC\n\n @staticmethod\n def _compute_stages(\n tiled_mma: cute.TiledMma,\n mma_tiler_mnk: Tuple[int, int, int],\n a_dtype: Type[cutlass.Numeric],\n a_major_mode: tcgen05.OperandMajorMode,\n b_dtype: Type[cutlass.Numeric],\n b_major_mode: tcgen05.OperandMajorMode,\n epi_tile: cute.Tile,\n c_dtype: Type[cutlass.Numeric],\n c_layout: utils.LayoutEnum,\n sf_dtype: Type[cutlass.Numeric],\n sf_vec_size: int,\n smem_capacity: int,\n occupancy: int,\n ) -> Tuple[int, int, int]:\n \"\"\"Computes the number of stages for A/B/C operands based on heuristics.\n\n :param tiled_mma: The tiled MMA object defining the core computation.\n :type tiled_mma: cute.TiledMma\n :param mma_tiler_mnk: The shape (M, N, K) of the MMA tiler.\n :type mma_tiler_mnk: tuple[int, int, int]\n :param a_dtype: Data type of operand A.\n :type a_dtype: type[cutlass.Numeric]\n :param a_major_mode: Major mode of operand A.\n :type a_major_mode: tcgen05.OperandMajorMode\n :param b_dtype: Data type of operand B.\n :type b_dtype: type[cutlass.Numeric]\n :param b_major_mode: Major mode of operand B.\n :type b_major_mode: tcgen05.OperandMajorMode\n :param epi_tile: The epilogue tile shape.\n :type epi_tile: cute.Tile\n :param c_dtype: Data type of operand C (output).\n :type c_dtype: type[cutlass.Numeric]\n :param c_layout: Layout enum of operand C.\n :type c_layout: utils.LayoutEnum\n :param sf_dtype: Data type of Scale factor.\n :type sf_dtype: type[cutlass.Numeric]\n :param sf_vec_size: Scale factor vector size.\n :type sf_vec_size: int\n :param smem_capacity: Total available shared memory capacity in bytes.\n :type smem_capacity: int\n :param occupancy: Target number of CTAs per SM (occupancy).\n :type occupancy: int\n\n :return: A tuple containing the computed number of stages for:\n (ACC stages, A/B operand stages, C stages)\n :rtype: tuple[int, int, int]\n \"\"\"\n # ACC stages\n num_acc_stage = 1 if mma_tiler_mnk[1] == 256 else 2\n\n # Default C stages\n num_c_stage = 2\n\n # Calculate smem layout and size for one stage of A, B, SFA, SFB and C\n a_smem_layout_stage_one = sm100_utils.make_smem_layout_a(\n tiled_mma,\n mma_tiler_mnk,\n a_dtype,\n 1, # a tmp 1 stage is provided\n )\n b_smem_layout_staged_one = sm100_utils.make_smem_layout_b(\n tiled_mma,\n mma_tiler_mnk,\n b_dtype,\n 1, # a tmp 1 stage is provided\n )\n sfa_smem_layout_staged_one = blockscaled_utils.make_smem_layout_sfa(\n tiled_mma,\n mma_tiler_mnk,\n sf_vec_size,\n 1, # a tmp 1 stage is provided\n )\n sfb_smem_layout_staged_one = blockscaled_utils.make_smem_layout_sfb(\n tiled_mma,\n mma_tiler_mnk,\n sf_vec_size,\n 1, # a tmp 1 stage is provided\n )\n\n c_smem_layout_staged_one = sm100_utils.make_smem_layout_epi(\n c_dtype,\n c_layout,\n epi_tile,\n 1,\n )\n\n ab_bytes_per_stage = (\n cute.size_in_bytes(a_dtype, a_smem_layout_stage_one)\n + cute.size_in_bytes(b_dtype, b_smem_layout_staged_one)\n + cute.size_in_bytes(sf_dtype, sfa_smem_layout_staged_one)\n + cute.size_in_bytes(sf_dtype, sfb_smem_layout_staged_one)\n )\n mbar_helpers_bytes = 1024\n c_bytes_per_stage = cute.size_in_bytes(c_dtype, c_smem_layout_staged_one)\n c_bytes = c_bytes_per_stage * num_c_stage\n\n # Calculate A/B/SFA/SFB stages:\n # Start with total smem per CTA (capacity / occupancy)\n # Subtract reserved bytes and initial C stages bytes\n # Divide remaining by bytes needed per A/B/SFA/SFB stage\n num_ab_stage = (\n smem_capacity // occupancy - (mbar_helpers_bytes + c_bytes)\n ) // ab_bytes_per_stage\n\n # Refine epilogue stages:\n # Calculate remaining smem after allocating for A/B/SFA/SFB stages and reserved bytes\n # Add remaining unused smem to epilogue\n num_c_stage += (\n smem_capacity\n - occupancy * ab_bytes_per_stage * num_ab_stage\n - occupancy * (mbar_helpers_bytes + c_bytes)\n ) // (occupancy * c_bytes_per_stage)\n\n return num_acc_stage, num_ab_stage, num_c_stage\n\n @staticmethod\n def _compute_grid(\n masked_m_tensor: cute.Tensor,\n dst_signals: Optional[cute.Pointer],\n c: cute.Tensor,\n cta_tile_shape_mnk: Tuple[int, int, int],\n cluster_shape_mn: Tuple[int, int],\n max_active_clusters: cutlass.Constexpr,\n ) -> Tuple[MaskedSchedulerParams, Tuple[int, int, int]]:\n \"\"\"Use persistent tile scheduler to compute the grid size for the output tensor C.\n\n :param c: The output tensor C\n :type c: cute.Tensor\n :param cta_tile_shape_mnk: The shape (M, N, K) of the CTA tile.\n :type cta_tile_shape_mnk: tuple[int, int, int]\n :param cluster_shape_mn: Shape of each cluster in M, N dimensions.\n :type cluster_shape_mn: tuple[int, int]\n :param max_active_clusters: Maximum number of active clusters.\n :type max_active_clusters: cutlass.Constexpr\n\n :return: A tuple containing:\n - tile_sched_params: Parameters for the persistent tile scheduler.\n - grid: Grid shape for kernel launch.\n :rtype: Tuple[MaskedSchedulerParams, tuple[int, int, int]]\n \"\"\"\n c_tiler = cute.slice_(cta_tile_shape_mnk, (None, None, 0))\n cluster_shape_mnl = (*cluster_shape_mn, 1)\n\n tile_sched_params = MaskedSchedulerParams(\n masked_m_tensor, dst_signals, c, c_tiler, cluster_shape_mnl\n )\n grid = MaskedScheduler.get_grid_shape(tile_sched_params, max_active_clusters)\n\n return tile_sched_params, grid\n\n @staticmethod\n def is_valid_dtypes_and_scale_factor_vec_size(\n ab_dtype: Type[cutlass.Numeric],\n sf_dtype: Type[cutlass.Numeric],\n sf_vec_size: int,\n c_dtype: Type[cutlass.Numeric],\n ) -> bool:\n \"\"\"\n Check if the dtypes and sf_vec_size are valid combinations\n\n :param ab_dtype: The data type of the A and B operands\n :type ab_dtype: Type[cutlass.Numeric]\n :param sf_dtype: The data type of the scale factor\n :type sf_dtype: Type[cutlass.Numeric]\n :param sf_vec_size: The vector size of the scale factor\n :type sf_vec_size: int\n :param c_dtype: The data type of the output tensor\n :type c_dtype: Type[cutlass.Numeric]\n\n :return: True if the dtypes and sf_vec_size are valid, False otherwise\n :rtype: bool\n \"\"\"\n is_valid = True\n\n # Check valid ab_dtype\n if ab_dtype not in {\n cutlass.Float4E2M1FN,\n cutlass.Float8E5M2,\n cutlass.Float8E4M3FN,\n }:\n is_valid = False\n\n # Check valid sf_vec_size\n if sf_vec_size not in {16, 32}:\n is_valid = False\n\n # Check valid sf_dtype\n if sf_dtype not in {cutlass.Float8E8M0FNU, cutlass.Float8E4M3FN}:\n is_valid = False\n\n # Check valid sf_dtype and sf_vec_size combinations\n if sf_dtype == cutlass.Float8E4M3FN and sf_vec_size == 32:\n is_valid = False\n if ab_dtype in {cutlass.Float8E5M2, cutlass.Float8E4M3FN} and sf_vec_size == 16:\n is_valid = False\n\n # Check valid c_dtype\n if c_dtype not in {\n cutlass.Float32,\n cutlass.Float16,\n cutlass.BFloat16,\n cutlass.Float8E5M2,\n cutlass.Float8E4M3FN,\n }:\n is_valid = False\n\n return is_valid\n\n @staticmethod\n def is_valid_layouts(\n ab_dtype: Type[cutlass.Numeric],\n c_dtype: Type[cutlass.Numeric],\n a_major: str,\n b_major: str,\n c_major: str,\n ) -> bool:\n \"\"\"\n Check if the dtypes and sf_vec_size are valid combinations\n\n :param ab_dtype: The data type of the A and B operands\n :type ab_dtype: Type[cutlass.Numeric]\n :param c_dtype: The data type of the output tensor\n :type c_dtype: Type[cutlass.Numeric]\n :param a_major: The major dimension of the A tensor\n :type a_major: str\n :param b_major: The major dimension of the B tensor\n :type b_major: str\n :param c_major: The major dimension of the C tensor\n :type c_major: str\n\n :return: True if the layouts are valid, False otherwise\n :rtype: bool\n \"\"\"\n is_valid = True\n\n if ab_dtype is cutlass.Float4E2M1FN and not (a_major == \"k\" and b_major == \"k\"):\n is_valid = False\n return is_valid\n\n @staticmethod\n def is_valid_mma_tiler_and_cluster_shape(\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n ) -> bool:\n \"\"\"\n Check if the mma tiler and cluster shape are valid\n\n :param mma_tiler_mn: The (M, N) shape of the MMA instruction tiler\n :type mma_tiler_mn: Tuple[int, int]\n :param cluster_shape_mn: The (ClusterM, ClusterN) shape of the CTA cluster\n :type cluster_shape_mn: Tuple[int, int]\n\n :return: True if the mma tiler and cluster shape are valid, False otherwise\n :rtype: bool\n \"\"\"\n is_valid = True\n # Skip invalid mma tile shape\n if mma_tiler_mn[0] not in [128, 256]:\n is_valid = False\n if mma_tiler_mn[1] not in [128, 256]:\n is_valid = False\n # Skip illegal cluster shape\n if cluster_shape_mn[0] % (2 if mma_tiler_mn[0] == 256 else 1) != 0:\n is_valid = False\n # Skip invalid cluster shape\n is_power_of_2 = lambda x: x > 0 and (x & (x - 1)) == 0\n if (\n cluster_shape_mn[0] * cluster_shape_mn[1] > 16\n or cluster_shape_mn[0] <= 0\n or cluster_shape_mn[1] <= 0\n # Special cluster shape check for scale factor multicasts.\n # Due to limited size of scale factors, we can't multicast among more than 4 CTAs.\n or cluster_shape_mn[0] > 4\n or cluster_shape_mn[1] > 4\n or not is_power_of_2(cluster_shape_mn[0])\n or not is_power_of_2(cluster_shape_mn[1])\n ):\n is_valid = False\n return is_valid\n\n @staticmethod\n def is_valid_tensor_alignment(\n m: int,\n n: int,\n k: int,\n l: int,\n ab_dtype: Type[cutlass.Numeric],\n c_dtype: Type[cutlass.Numeric],\n a_major: str,\n b_major: str,\n c_major: str,\n ) -> bool:\n \"\"\"\n Check if the tensor alignment is valid\n\n :param m: The number of rows in the A tensor\n :type m: int\n :param n: The number of columns in the B tensor\n :type n: int\n :param k: The number of columns in the A tensor\n :type k: int\n :param l: The number of columns in the C tensor\n :type l: int\n :param ab_dtype: The data type of the A and B operands\n :type ab_dtype: Type[cutlass.Numeric]\n :param c_dtype: The data type of the output tensor\n :type c_dtype: Type[cutlass.Numeric]\n :param a_major: The major axis of the A tensor\n :type a_major: str\n :param b_major: The major axis of the B tensor\n :type b_major: str\n :param c_major: The major axis of the C tensor\n :type c_major: str\n\n :return: True if the problem shape is valid, False otherwise\n :rtype: bool\n \"\"\"\n is_valid = True\n\n def check_contigous_16B_alignment(dtype, is_mode0_major, tensor_shape):\n major_mode_idx = 0 if is_mode0_major else 1\n num_major_elements = tensor_shape[major_mode_idx]\n num_contiguous_elements = 16 * 8 // dtype.width\n return num_major_elements % num_contiguous_elements == 0\n\n if (\n not check_contigous_16B_alignment(ab_dtype, a_major == \"m\", (m, k, l))\n or not check_contigous_16B_alignment(ab_dtype, b_major == \"n\", (n, k, l))\n or not check_contigous_16B_alignment(c_dtype, c_major == \"m\", (m, n, l))\n ):\n is_valid = False\n return is_valid\n\n @staticmethod\n def can_implement(\n ab_dtype: Type[cutlass.Numeric],\n sf_dtype: Type[cutlass.Numeric],\n sf_vec_size: int,\n c_dtype: Type[cutlass.Numeric],\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n m: int,\n n: int,\n k: int,\n l: int,\n a_major: str,\n b_major: str,\n c_major: str,\n ) -> bool:\n \"\"\"\n Check if the gemm can be implemented\n\n :param ab_dtype: The data type of the A and B operands\n :type ab_dtype: Type[cutlass.Numeric]\n :param sf_dtype: The data type of the scale factor tensor\n :type sf_dtype: Type[cutlass.Numeric]\n :param sf_vec_size: The vector size\n :type sf_vec_size: int\n :param c_dtype: The data type of the output tensor\n :type c_dtype: Type[cutlass.Numeric]\n :param mma_tiler_mn: The (M, N) shape of the MMA instruction tiler\n :type mma_tiler_mn: Tuple[int, int]\n :param cluster_shape_mn: The (ClusterM, ClusterN) shape of the CTA cluster\n :type cluster_shape_mn: Tuple[int, int]\n :param m: The number of rows in the A tensor\n :type m: int\n :param n: The number of columns in the B tensor\n :type n: int\n :param k: The number of columns in the A tensor\n :type k: int\n :param l: The number of columns in the C tensor\n :type l: int\n :param a_major: The major axis of the A tensor\n :type a_major: str\n :param b_major: The major axis of the B tensor\n :type b_major: str\n :param c_major: The major axis of the C tensor\n :type c_major: str\n\n :return: True if the gemm can be implemented, False otherwise\n :rtype: bool\n \"\"\"\n can_implement = True\n # Skip unsupported types\n if not Sm100BlockScaledPersistentDenseGemmKernel.is_valid_dtypes_and_scale_factor_vec_size(\n ab_dtype, sf_dtype, sf_vec_size, c_dtype\n ):\n can_implement = False\n # Skip unsupported layouts\n if not Sm100BlockScaledPersistentDenseGemmKernel.is_valid_layouts(\n ab_dtype, c_dtype, a_major, b_major, c_major\n ):\n can_implement = False\n # Skip invalid mma tile shape and cluster shape\n if not Sm100BlockScaledPersistentDenseGemmKernel.is_valid_mma_tiler_and_cluster_shape(\n mma_tiler_mn, cluster_shape_mn\n ):\n can_implement = False\n # Skip illegal problem shape for load/store alignment\n if not Sm100BlockScaledPersistentDenseGemmKernel.is_valid_tensor_alignment(\n m, n, k, l, ab_dtype, c_dtype, a_major, b_major, c_major\n ):\n can_implement = False\n return can_implement\n\n\n@cute.jit\ndef cvt_sf_MKL_to_M32x4xrm_K4xrk_L(\n sf_ref_tensor: cute.Tensor,\n sf_mma_tensor: cute.Tensor,\n):\n \"\"\"Convert scale factor tensor from MKL layout to mma specification M(32x4xrest_m)xK(4xrest_k)xL layout\"\"\"\n # sf_mma_tensor has flatten shape (32, 4, rest_m, 4, rest_k, l)\n # group to ((32, 4, rest_m), (4, rest_k), l)\n sf_mma_tensor = cute.group_modes(sf_mma_tensor, 0, 3)\n sf_mma_tensor = cute.group_modes(sf_mma_tensor, 1, 3)\n for i in cutlass.range(cute.size(sf_ref_tensor)):\n mkl_coord = sf_ref_tensor.layout.get_hier_coord(i)\n sf_mma_tensor[mkl_coord] = sf_ref_tensor[mkl_coord]\n\n\n@cute.jit\ndef cvt_sf_MKL_to_M32x4xrm_K4xrk_L_mma_spec(\n sf_mma_tensor: cute.Tensor,\n):\n \"\"\"Convert scale factor tensor from MKL layout to mma specification M(32x4xrest_m)xK(4xrest_k)xL layout\"\"\"\n # sf_mma_tensor has flatten shape (32, 4, rest_m, 4, rest_k, l)\n # group to ((32, 4, rest_m), (4, rest_k), l)\n sf_mma_tensor = cute.group_modes(sf_mma_tensor, 0, 3)\n sf_mma_tensor = cute.group_modes(sf_mma_tensor, 1, 3)\n\n\n# Create scale factor tensor SFA/SFB\ndef create_scale_factor_tensor(l, mn, k, sf_vec_size, dtype, device):\n def ceil_div(a, b):\n return (a + b - 1) // b\n\n sf_k = ceil_div(k, sf_vec_size)\n ref_shape = (l, mn, sf_k)\n\n atom_m = (32, 4)\n atom_k = 4\n mma_shape = (\n l,\n ceil_div(mn, atom_m[0] * atom_m[1]),\n ceil_div(sf_k, atom_k),\n atom_m[0],\n atom_m[1],\n atom_k,\n )\n\n ref_permute_order = (1, 2, 0)\n mma_permute_order = (3, 4, 1, 5, 2, 0)\n\n # Create f32 ref torch tensor\n ref_f32_torch_tensor_cpu = cutlass_torch.create_and_permute_torch_tensor(\n ref_shape,\n torch.float32,\n permute_order=ref_permute_order,\n init_type=cutlass_torch.TensorInitType.RANDOM,\n init_config=cutlass_torch.RandomInitConfig(\n min_val=1,\n max_val=3,\n ),\n )\n\n # Create f32 cute torch tensor\n cute_f32_torch_tensor_cpu = cutlass_torch.create_and_permute_torch_tensor(\n mma_shape,\n torch.float32,\n permute_order=mma_permute_order,\n init_type=cutlass_torch.TensorInitType.RANDOM,\n init_config=cutlass_torch.RandomInitConfig(\n min_val=0,\n max_val=1,\n ),\n )\n\n # convert ref f32 tensor to cute f32 tensor\n cvt_sf_MKL_to_M32x4xrm_K4xrk_L(\n from_dlpack(ref_f32_torch_tensor_cpu),\n from_dlpack(cute_f32_torch_tensor_cpu),\n )\n cute_f32_torch_tensor = cute_f32_torch_tensor_cpu.to(device, non_blocking=True)\n\n # reshape makes memory contiguous\n ref_f32_torch_tensor_cpu = (\n ref_f32_torch_tensor_cpu.permute(2, 0, 1)\n .unsqueeze(-1)\n .expand(l, mn, sf_k, sf_vec_size)\n .reshape(l, mn, sf_k * sf_vec_size)\n .permute(*ref_permute_order)\n )\n # prune to mkl for reference check.\n ref_f32_torch_tensor_cpu = ref_f32_torch_tensor_cpu[:, :k, :]\n ref_f32_torch_tensor = ref_f32_torch_tensor_cpu.to(device, non_blocking=True)\n\n # Create dtype cute torch tensor (cpu)\n cute_tensor, cute_torch_tensor = cutlass_torch.cute_tensor_like(\n cute_f32_torch_tensor_cpu,\n dtype,\n is_dynamic_layout=True,\n assumed_align=16,\n )\n\n # Convert f32 cute tensor to dtype cute tensor\n cute_tensor = cutlass_torch.convert_cute_tensor(\n cute_f32_torch_tensor,\n cute_tensor,\n dtype,\n is_dynamic_layout=True,\n )\n return ref_f32_torch_tensor, cute_tensor, cute_torch_tensor\n\n\nclass MaskedBatchedMatmulCuteDSL:\n def __init__(\n self,\n m: int,\n n: int,\n k: int,\n l: int,\n a_major: str,\n b_major: str,\n c_major: str,\n ab_dtype: torch.dtype,\n sf_dtype: torch.dtype,\n c_dtype: torch.dtype,\n alpha_dtype: torch.dtype,\n sf_vec_size: int,\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n sm_count: int,\n sm_version: str,\n ):\n self._m = m\n self._n = n\n self._k = k\n self._l = l\n self._a_major = a_major\n self._b_major = b_major\n self._c_major = c_major\n self._ab_dtype = ab_dtype\n self._sf_dtype = sf_dtype\n self._c_dtype = c_dtype\n self._alpha_dtype = alpha_dtype\n self._sf_vec_size = sf_vec_size\n self._mma_tiler_mn = mma_tiler_mn\n self._cluster_shape_mn = cluster_shape_mn\n\n if not Sm100BlockScaledPersistentDenseGemmKernel.can_implement(\n ab_dtype,\n sf_dtype,\n sf_vec_size,\n c_dtype,\n mma_tiler_mn,\n cluster_shape_mn,\n m,\n n,\n k,\n l,\n a_major,\n b_major,\n c_major,\n ):\n raise TypeError(\n f\"MaskedBatchedMatmulCuteDSL: Unsupported with {ab_dtype}, {sf_dtype}, {sf_vec_size}, {c_dtype}, {mma_tiler_mn}, {cluster_shape_mn}, {m}, {n}, {k}, {l}, {a_major}, {b_major}, {c_major}\"\n )\n\n # Compute max active clusters on current device\n hardware_info = cutlass.utils.HardwareInfo()\n self._max_active_clusters = min(\n hardware_info.get_max_active_clusters(\n self._cluster_shape_mn[0] * self._cluster_shape_mn[1]\n ),\n sm_count,\n )\n self._sm_version = sm_version\n\n @cute.jit\n def __call__(\n self,\n a_ptr: cute.Pointer,\n b_ptr: cute.Pointer,\n sfa_ptr: cute.Pointer,\n sfb_ptr: cute.Pointer,\n c_ptr: cute.Pointer,\n masked_m_ptr: cute.Pointer,\n dst_signals_ptr: Optional[cute.Pointer],\n alpha_ptr: cute.Pointer,\n current_stream: cuda.CUstream,\n ):\n a_tensor = cute.make_tensor(\n a_ptr,\n layout=cute.make_ordered_layout(\n (self._m, self._k, self._l),\n order=(0, 1, 2) if self._a_major == \"m\" else (1, 0, 2),\n ),\n )\n b_tensor = cute.make_tensor(\n b_ptr,\n layout=cute.make_ordered_layout(\n (self._n, self._k, self._l),\n order=(0, 1, 2) if self._b_major == \"n\" else (1, 0, 2),\n ),\n )\n c_tensor = cute.make_tensor(\n c_ptr,\n layout=cute.make_ordered_layout(\n (self._m, self._n, self._l),\n order=(0, 1, 2) if self._c_major == \"m\" else (1, 0, 2),\n ),\n )\n\n # calculate sf_tensor shape and order\n def ceil_div(a, b):\n return (a + b - 1) // b\n\n sf_k = ceil_div(self._k, self._sf_vec_size)\n\n atom_m = (32, 4)\n atom_k = 4\n mma_shape_a = (\n self._l,\n ceil_div(self._m, atom_m[0] * atom_m[1]),\n ceil_div(sf_k, atom_k),\n atom_m[0],\n atom_m[1],\n atom_k,\n )\n mma_shape_b = (\n self._l,\n ceil_div(self._n, atom_m[0] * atom_m[1]),\n ceil_div(sf_k, atom_k),\n atom_m[0],\n atom_m[1],\n atom_k,\n )\n mma_permute_order = (3, 4, 1, 5, 2, 0)\n\n sfa_tensor = cute.make_tensor(\n sfa_ptr,\n layout=cute.make_ordered_layout(\n mma_shape_a,\n order=mma_permute_order,\n ),\n )\n sfb_tensor = cute.make_tensor(\n sfb_ptr,\n layout=cute.make_ordered_layout(\n mma_shape_b,\n order=mma_permute_order,\n ),\n )\n cvt_sf_MKL_to_M32x4xrm_K4xrk_L_mma_spec(sfa_tensor)\n cvt_sf_MKL_to_M32x4xrm_K4xrk_L_mma_spec(sfb_tensor)\n\n masked_m_tensor = cute.make_tensor(\n masked_m_ptr,\n layout=cute.make_ordered_layout((self._l,), order=(0,)),\n )\n\n # Use const_expr for compile-time conditional\n alpha_tensor = (\n cute.make_tensor(\n alpha_ptr,\n layout=cute.make_ordered_layout((self._l,), order=(0,)),\n )\n if cutlass.const_expr(alpha_ptr is not None)\n else None\n )\n\n Sm100BlockScaledPersistentDenseGemmKernel(\n sf_vec_size=self._sf_vec_size,\n mma_tiler_mn=self._mma_tiler_mn,\n cluster_shape_mn=self._cluster_shape_mn,\n sm_version=self._sm_version,\n )(\n a_tensor,\n b_tensor,\n sfa_tensor,\n sfb_tensor,\n c_tensor,\n masked_m_tensor,\n dst_signals_ptr,\n alpha_tensor,\n self._max_active_clusters,\n current_stream,\n )\n\n\n@functools.cache\ndef get_cute_dsl_compiled_masked_gemm_kernel(\n m: int,\n n: int,\n k: int,\n l: int,\n a_major: str,\n b_major: str,\n c_major: str,\n ab_dtype: Type[cutlass.Numeric],\n sf_dtype: Type[cutlass.Numeric],\n c_dtype: Type[cutlass.Numeric],\n alpha_dtype: Optional[Type[cutlass.Numeric]],\n sf_vec_size: int,\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n sm_count: int,\n sm_version: str,\n enable_dst_signals: bool,\n) -> Callable:\n def get_cute_pointers(\n input_tensors: Optional[List[torch.tensor]],\n ) -> List[cute.Pointer]:\n if input_tensors is None:\n (\n a_data_ptr,\n b_data_ptr,\n sfa_data_ptr,\n sfb_data_ptr,\n c_data_ptr,\n masked_m_data_ptr,\n dst_signals_data_ptr,\n alpha_data_ptr,\n ) = [16 for _ in range(8)]\n\n if not enable_dst_signals:\n dst_signals_data_ptr = None\n\n else:\n (\n a_tensor_gpu,\n b_tensor_gpu,\n sfa_tensor_gpu,\n sfb_tensor_gpu,\n c_tensor_gpu,\n masked_m_tensor_gpu,\n dst_signals_tensor_gpu,\n alpha_tensor_gpu,\n ) = input_tensors\n\n assert enable_dst_signals == (dst_signals_tensor_gpu is not None)\n\n (\n a_data_ptr,\n b_data_ptr,\n sfa_data_ptr,\n sfb_data_ptr,\n c_data_ptr,\n masked_m_data_ptr,\n dst_signals_data_ptr,\n alpha_data_ptr,\n ) = (\n a_tensor_gpu.data_ptr(),\n b_tensor_gpu.data_ptr(),\n sfa_tensor_gpu.data_ptr(),\n sfb_tensor_gpu.data_ptr(),\n c_tensor_gpu.data_ptr(),\n masked_m_tensor_gpu.data_ptr(),\n dst_signals_tensor_gpu.data_ptr()\n if dst_signals_tensor_gpu is not None\n else None,\n alpha_tensor_gpu.data_ptr() if alpha_tensor_gpu is not None else None,\n )\n\n a_ptr = make_ptr(\n ab_dtype,\n a_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n b_ptr = make_ptr(\n ab_dtype,\n b_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n sfa_ptr = make_ptr(\n sf_dtype,\n sfa_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n sfb_ptr = make_ptr(\n sf_dtype,\n sfb_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n c_ptr = make_ptr(\n c_dtype,\n c_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n masked_m_ptr = make_ptr(\n cutlass.Int32,\n masked_m_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n dst_signals_ptr = (\n make_ptr(\n cutlass.Uint32,\n dst_signals_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n if dst_signals_data_ptr is not None\n else None\n )\n alpha_ptr = (\n make_ptr(\n alpha_dtype,\n alpha_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n if alpha_data_ptr is not None and alpha_dtype is not None\n else None\n )\n\n return [\n a_ptr,\n b_ptr,\n sfa_ptr,\n sfb_ptr,\n c_ptr,\n masked_m_ptr,\n dst_signals_ptr,\n alpha_ptr,\n ]\n\n kernel = cute.compile(\n MaskedBatchedMatmulCuteDSL(\n m=m,\n n=n,\n k=k,\n l=l,\n a_major=a_major,\n b_major=b_major,\n c_major=c_major,\n ab_dtype=ab_dtype,\n sf_dtype=sf_dtype,\n c_dtype=c_dtype,\n alpha_dtype=alpha_dtype,\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n cluster_shape_mn=cluster_shape_mn,\n sm_count=sm_count,\n sm_version=sm_version,\n ),\n *get_cute_pointers(None),\n cutlass_torch.current_stream(),\n )\n\n def tensor_api(\n a_tensor_gpu: torch.Tensor,\n b_tensor_gpu: torch.Tensor,\n sfa_tensor_gpu: torch.Tensor,\n sfb_tensor_gpu: torch.Tensor,\n masked_m_tensor_gpu: torch.Tensor,\n dst_signals_tensor_gpu: torch.Tensor,\n c_tensor_gpu: Optional[torch.Tensor] = None,\n alpha_tensor_gpu: Optional[torch.Tensor] = None,\n ):\n if c_tensor_gpu is None:\n # fp4 gemm output is not supported\n c_tensor_gpu = torch.empty(\n (l, m, n),\n dtype=cutlass_to_torch_dtype(c_dtype),\n device=\"cuda\",\n )\n\n # fp4 or fp8 torch tensor to cute tensor\n current_stream = cutlass_torch.current_stream()\n\n nonlocal kernel\n kernel(\n *get_cute_pointers(\n [\n a_tensor_gpu,\n b_tensor_gpu,\n sfa_tensor_gpu,\n sfb_tensor_gpu,\n c_tensor_gpu,\n masked_m_tensor_gpu,\n dst_signals_tensor_gpu,\n alpha_tensor_gpu,\n ]\n ),\n current_stream,\n )\n\n return c_tensor_gpu\n\n return tensor_api\n\n\n@flashinfer_api\ndef grouped_gemm_nt_masked(\n lhs: Tuple[torch.Tensor, torch.Tensor],\n rhs: Tuple[torch.Tensor, torch.Tensor],\n out: torch.Tensor,\n masked_m: torch.Tensor,\n *,\n ab_dtype: str,\n sf_dtype: str,\n c_dtype: str,\n sf_vec_size: int,\n dst_signals: Optional[torch.Tensor] = None,\n sm_count: Optional[int] = None,\n **kwargs,\n):\n \"\"\"\n Executes a masked, batched matrix multiplication (GEMM) with scale factors and optional alpha scaling at output.\n\n Args:\n lhs (Tuple[torch.Tensor, torch.Tensor]): Tuple containing the left-hand side input tensor (A) and its scale factor tensor (SFA).\n - A should be in (m, k, l) order, but physically (l, m, k). For fp4 tensor with 8-bit storage, we expect the shape to be (m, k/2, l).\n - SFA should be in (m32, m4, rm, k4, rk, l) order, but physically (l, rm, rk, m32, m4, k4)\n rhs (Tuple[torch.Tensor, torch.Tensor]): Tuple containing the right-hand side input tensor (B) and its scale factor tensor (SFB).\n - B should be in (n, k, l) order, but physically (l, n, k). For fp4 tensor with 8-bit storage, we expect the shape to be (n, k/2, l).\n - SFB should be in (n32, n4, rn, k4, rk, l) order, but physically (l, rn, rk, n32, n4, k4)\n out (torch.Tensor): Output tensor to store the result, with shape (l, m, n).\n masked_m (torch.Tensor): 1D tensor of shape (l,) specifying the valid row count for each batch (used for masking).\n ab_dtype (str): Data type for A and B matrices. Supported: \"float4_e2m1fn\", \"float8_e4m3fn\", \"float8_e5m2\".\n sf_dtype (str): Data type for scale factors. Supported: \"float8_e8m0fnu\", \"float8_e4m3fn\".\n c_dtype (str): Data type for output matrix C. Supported: \"float16\", \"bfloat16\", \"float32\", \"float8_e4m3fn\", \"float8_e5m2\".\n sf_vec_size (int): Vector size for scale factors. Typically 16 or 32.\n sm_count (int, optional): Number of SMs to use. Default: max available SMs under the CTA configuration.\n mma_tiler_mn (Tuple[int, int], optional): Shape of the MMA tiler (M, N). Default: (128, 128).\n cluster_shape_mn (Tuple[int, int], optional): Shape of the CTA cluster (ClusterM, ClusterN). Default: (1, 1).\n alpha_dtype (str, optional): Data type for alpha scaling factors.\n alpha (torch.Tensor, optional): Optional 1D tensor of shape (l,) containing per-batch scaling factors. Perform per-batch scaling out = alpha * out.\n\n Notes:\n - Legends of the input tensors:\n * `l` is the batch size, `m/n` is the number of rows, and `k` is the number of columns.\n * `m/n32`, `m/n4`, `k4` are constant values 32, 4, 4 respectively.\n * `m32 * m4 * rm` should be same as `M`, which is `m` padded up to the nearest multiple of 128.\n * `n32 * n4 * rn` should be same as `N`, which is `n` padded up to the nearest multiple of 128.\n * `k4 * rk` should be same as `K`, which is `k / sf_vec_size` padded up to the nearest multiple of 4.\n - The function applies masking per batch using masked_m.\n - If alpha is provided, each batch output is multiplied by its corresponding alpha value. out = alpha * (A @ B).\n - The result is written to c_tensor.\n \"\"\"\n\n a_torch, sfa_torch = lhs\n b_torch, sfb_torch = rhs\n c_torch = out\n\n m, k, l = a_torch.shape\n n, _, _ = b_torch.shape\n\n if ab_dtype == \"float4_e2m1fn\":\n # todo(yingyi): update mnk based on a_major and b_major, and support more major.\n # Note: only support deepgemm-like shape for now\n k = k * 2\n\n mma_tiler_mn = kwargs.pop(\"mma_tiler_mn\", (128, 128))\n cluster_shape_mn = kwargs.pop(\"cluster_shape_mn\", (1, 1))\n if sm_count is None:\n sm_count = get_num_sm(a_torch.device)\n\n alpha = kwargs.pop(\"alpha\", None)\n alpha_dtype = kwargs.pop(\"alpha_dtype\", None)\n\n assert len(kwargs) == 0, f\"Unsupported kwargs: {kwargs}\"\n\n major, minor = get_compute_capability(a_torch.device)\n if major == 11 and minor == 0:\n raise ValueError(\"SM110 is not supported for cute-dsl backend.\")\n\n return get_cute_dsl_compiled_masked_gemm_kernel(\n m=m,\n n=n,\n k=k,\n l=l,\n a_major=\"k\",\n b_major=\"k\",\n c_major=\"n\",\n ab_dtype=get_cutlass_dtype(ab_dtype),\n sf_dtype=get_cutlass_dtype(sf_dtype),\n c_dtype=get_cutlass_dtype(c_dtype),\n alpha_dtype=None if alpha is None else get_cutlass_dtype(alpha_dtype),\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n cluster_shape_mn=cluster_shape_mn,\n sm_count=sm_count,\n sm_version=f\"sm_{major}{minor}\",\n enable_dst_signals=dst_signals is not None,\n )(\n a_tensor_gpu=a_torch,\n b_tensor_gpu=b_torch,\n sfa_tensor_gpu=sfa_torch,\n sfb_tensor_gpu=sfb_torch,\n c_tensor_gpu=c_torch,\n masked_m_tensor_gpu=masked_m,\n dst_signals_tensor_gpu=dst_signals,\n alpha_tensor_gpu=alpha,\n )\n"},"after_code":{"kind":"string","value":"# Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: BSD-3-Clause\n\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are met:\n\n# 1. Redistributions of source code must retain the above copyright notice, this\n# list of conditions and the following disclaimer.\n\n# 2. Redistributions in binary form must reproduce the above copyright notice,\n# this list of conditions and the following disclaimer in the documentation\n# and/or other materials provided with the distribution.\n\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nfrom typing import Optional, Tuple, Type, Union\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nimport cutlass.torch as cutlass_torch\nimport cutlass.utils as utils\nimport cutlass.utils.blackwell_helpers as sm100_utils\nimport cutlass.utils.blockscaled_layout as blockscaled_utils\nimport torch\nimport functools\nfrom cutlass._mlir import ir\nfrom cutlass.cute.nvgpu import cpasync, tcgen05\nfrom cutlass.cute.runtime import from_dlpack\n\nfrom cutlass.cutlass_dsl import (\n Int32,\n Int64,\n Uint8,\n Uint64,\n T,\n Integer,\n dsl_user_op,\n extract_mlir_values,\n new_from_mlir_values,\n)\nfrom cutlass._mlir.dialects import llvm\nfrom flashinfer.utils import get_compute_capability\nfrom flashinfer.api_logging import flashinfer_api\nfrom cutlass.utils.static_persistent_tile_scheduler import WorkTileInfo\nfrom flashinfer.cute_dsl.utils import (\n get_cutlass_dtype,\n cutlass_to_torch_dtype,\n get_num_sm,\n get_max_active_clusters,\n make_ptr,\n)\nfrom typing import Callable, List\n\n\nsizeof_i32 = 4\n\n\n@dsl_user_op\ndef with_byte(obj: Uint64, index: Int32, value: Uint8, *, loc=None, ip=None) -> Uint64:\n obj &= ~(0xFF << (index * 8))\n obj |= value << (index * 8)\n assert isinstance(obj, Uint64), f\"{obj=}\"\n return obj\n\n\n@dsl_user_op\ndef read_byte(obj: Uint64, index: Int32, *, loc=None, ip=None) -> Uint8:\n return ((obj >> (index * 8)) & 0xFF).to(Uint8)\n\n\n@dsl_user_op\ndef atomic_add_release_global(addr: Int64, value: Int32, *, loc=None, ip=None) -> Int32:\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [\n addr.ir_value(loc=loc, ip=ip),\n Int32(value).ir_value(loc=loc, ip=ip),\n ],\n \"atom.add.release.gpu.global.s32 $0, [$1], $2;\",\n \"=r,l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\nclass MaskedSchedulerParams:\n def __init__(\n self,\n masked_m: cute.Tensor,\n dst_signals: Optional[cute.Pointer],\n c: cute.Tensor,\n c_tiler: Tuple[int, int],\n cluster_shape_mnk: cute.Shape,\n *,\n loc=None,\n ip=None,\n ):\n if cluster_shape_mnk[2] != 1:\n raise ValueError(f\"unsupported cluster_shape_k {cluster_shape_mnk[2]}\")\n\n gc = cute.zipped_divide(c, tiler=c_tiler)\n problem_shape_ntile_mnl = gc[(0, (None, None, None))].shape\n self.masked_m = masked_m\n self.dst_signals = dst_signals\n self.c = c\n self.c_tiler = c_tiler\n self.problem_shape_ntile_mnl = problem_shape_ntile_mnl\n # cluster_shape_mnk is kept for reconstruction\n self._cluster_shape_mnk = cluster_shape_mnk\n self.cluster_shape_mn = cluster_shape_mnk[:2]\n self._loc = loc\n\n self.problem_layout_ncluster_mnl = cute.make_layout(\n cute.ceil_div(\n self.problem_shape_ntile_mnl, cluster_shape_mnk[:2], loc=loc, ip=ip\n ),\n loc=loc,\n ip=ip,\n )\n\n def __extract_mlir_values__(self):\n values, self._values_pos = [], []\n for obj in [\n self.masked_m,\n self.dst_signals,\n self.c,\n self.c_tiler,\n self._cluster_shape_mnk,\n ]:\n obj_values = extract_mlir_values(obj)\n values += obj_values\n self._values_pos.append(len(obj_values))\n return values\n\n def __new_from_mlir_values__(self, values):\n obj_list = []\n for obj, n_items in zip(\n [\n self.masked_m,\n self.dst_signals,\n self.c,\n self.c_tiler,\n self._cluster_shape_mnk,\n ],\n self._values_pos,\n strict=True,\n ):\n obj_list.append(new_from_mlir_values(obj, values[:n_items]))\n values = values[n_items:]\n return MaskedSchedulerParams(*(tuple(obj_list)), loc=self._loc)\n\n @dsl_user_op\n def get_grid_shape(\n self, max_active_clusters: Int32, *, loc=None, ip=None\n ) -> Tuple[Integer, Integer, Integer]:\n num_persistent_clusters = max_active_clusters\n\n return (*self.cluster_shape_mn, num_persistent_clusters)\n\n\nclass MaskedScheduler:\n def __init__(\n self,\n params: MaskedSchedulerParams,\n num_persistent_clusters: Int32,\n current_work_linear_idx: Int32,\n current_batch_idx: Int32,\n accum_tile_m: Int32,\n cta_id_in_cluster: cute.Coord,\n num_tiles_executed: Int32,\n ):\n self.params = params\n self.num_persistent_clusters = num_persistent_clusters\n self._current_work_linear_idx = current_work_linear_idx\n self._current_batch_idx = current_batch_idx\n self._accum_tile_m = accum_tile_m\n self.cta_id_in_cluster = cta_id_in_cluster\n self._num_tiles_executed = num_tiles_executed\n\n def __extract_mlir_values__(self) -> list[ir.Value]:\n values = extract_mlir_values(self.num_persistent_clusters)\n values.extend(extract_mlir_values(self._current_work_linear_idx))\n values.extend(extract_mlir_values(self._current_batch_idx))\n values.extend(extract_mlir_values(self._accum_tile_m))\n values.extend(extract_mlir_values(self.cta_id_in_cluster))\n values.extend(extract_mlir_values(self._num_tiles_executed))\n return values\n\n def __new_from_mlir_values__(self, values: list[ir.Value]) -> \"MaskedScheduler\":\n assert len(values) == 8\n new_num_persistent_clusters = new_from_mlir_values(\n self.num_persistent_clusters, [values[0]]\n )\n new_current_work_linear_idx = new_from_mlir_values(\n self._current_work_linear_idx, [values[1]]\n )\n new_current_batch_idx = new_from_mlir_values(\n self._current_batch_idx, [values[2]]\n )\n new_accum_tile_m = new_from_mlir_values(self._accum_tile_m, [values[3]])\n new_cta_id_in_cluster = new_from_mlir_values(\n self.cta_id_in_cluster, values[4:7]\n )\n new_num_tiles_executed = new_from_mlir_values(\n self._num_tiles_executed, [values[7]]\n )\n return MaskedScheduler(\n self.params,\n new_num_persistent_clusters,\n new_current_work_linear_idx,\n new_current_batch_idx,\n new_accum_tile_m,\n new_cta_id_in_cluster,\n new_num_tiles_executed,\n )\n\n # called by host\n @dsl_user_op\n @staticmethod\n def create(\n params: MaskedSchedulerParams,\n block_idx: Tuple[Integer, Integer, Integer],\n grid_dim: Tuple[Integer, Integer, Integer],\n *,\n loc=None,\n ip=None,\n ):\n params = params\n\n # Calculate the number of persistent clusters by dividing the total grid size\n # by the number of CTAs per cluster\n num_persistent_clusters = cute.size(grid_dim, loc=loc, ip=ip) // cute.size(\n params.cluster_shape_mn, loc=loc, ip=ip\n )\n\n bidx, bidy, bidz = block_idx\n\n # Initialize workload index equals to the cluster index in the grid\n current_work_linear_idx = Int32(bidz)\n current_batch_idx = Int32(0)\n accum_tile_m = Int32(0)\n\n # CTA id in the cluster\n cta_id_in_cluster = (\n Int32(bidx % params.cluster_shape_mn[0]),\n Int32(bidy % params.cluster_shape_mn[1]),\n Int32(0),\n )\n # Initialize number of tiles executed to zero\n num_tiles_executed = Int32(0)\n return MaskedScheduler(\n params,\n num_persistent_clusters,\n current_work_linear_idx,\n current_batch_idx,\n accum_tile_m,\n cta_id_in_cluster,\n num_tiles_executed,\n )\n\n # called by host\n @staticmethod\n def get_grid_shape(\n params: MaskedSchedulerParams,\n max_active_clusters: Int32,\n *,\n loc=None,\n ip=None,\n ) -> Tuple[Integer, Integer, Integer]:\n return params.get_grid_shape(max_active_clusters, loc=loc, ip=ip)\n\n # private method\n @cute.jit\n def _get_current_work_for_linear_idx(\n self,\n current_work_linear_idx: Int32,\n dsm_pending_packed: Optional[Uint64],\n dsm_counter: Optional[Uint8],\n num_c_stage: Optional[int] = None,\n ) -> Tuple[WorkTileInfo, Optional[Uint64]]:\n # is_valid = current_work_linear_idx < cute.size(\n # self.params.problem_layout_ncluster_mnl, loc=loc, ip=ip\n # )\n num_tiles_n = self.params.problem_shape_ntile_mnl[1]\n accum_tile_m = self._accum_tile_m\n batch_idx = self._current_batch_idx\n\n while (\n (\n accum_tile_m\n + cute.ceil_div(self.params.masked_m[batch_idx], self.params.c_tiler[0])\n )\n * num_tiles_n\n <= current_work_linear_idx\n and batch_idx < self.params.masked_m.shape[0]\n ):\n if cutlass.const_expr(\n (dsm_pending_packed is not None)\n and (self.params.dst_signals is not None)\n ):\n dsm_pending_packed = with_byte(\n dsm_pending_packed,\n index=batch_idx,\n value=dsm_counter + (num_c_stage - 1),\n )\n\n accum_tile_m += cute.ceil_div(\n self.params.masked_m[batch_idx], self.params.c_tiler[0]\n )\n batch_idx += Int32(1)\n\n self._accum_tile_m = accum_tile_m\n self._current_batch_idx = batch_idx\n\n is_valid = self._current_batch_idx < self.params.masked_m.shape[0]\n if is_valid:\n is_valid = (\n self._accum_tile_m\n + cute.ceil_div(\n self.params.masked_m[self._current_batch_idx],\n self.params.c_tiler[0],\n )\n ) * num_tiles_n > current_work_linear_idx\n\n # cur_cluster_coord = self.params.problem_layout_ncluster_mnl.get_hier_coord(\n # current_work_linear_idx, loc=loc, ip=ip\n # )\n cur_cluster_coord = (\n current_work_linear_idx // num_tiles_n - self._accum_tile_m,\n current_work_linear_idx % num_tiles_n,\n self._current_batch_idx,\n )\n\n # cur_tile_coord is a tuple of i32 values\n cur_tile_coord = tuple(\n Int32(x) * Int32(z) + Int32(y)\n for x, y, z in zip(\n cur_cluster_coord,\n self.cta_id_in_cluster,\n (*self.params.cluster_shape_mn, Int32(1)),\n strict=True,\n )\n )\n\n return WorkTileInfo(cur_tile_coord, is_valid), dsm_pending_packed\n\n @dsl_user_op\n def get_current_work(\n self,\n dsm_pending_packed: Optional[Uint64] = None,\n dsm_counter: Optional[Uint8] = None,\n num_c_stage: Optional[int] = None,\n *,\n loc=None,\n ip=None,\n ) -> Tuple[WorkTileInfo, Optional[Uint64]]:\n return self._get_current_work_for_linear_idx(\n self._current_work_linear_idx,\n dsm_pending_packed=dsm_pending_packed,\n dsm_counter=dsm_counter,\n num_c_stage=num_c_stage,\n )\n\n @dsl_user_op\n def initial_work_tile_info(self, *, loc=None, ip=None) -> WorkTileInfo:\n tile_info, _ = self.get_current_work(loc=loc, ip=ip)\n return tile_info\n\n @dsl_user_op\n def advance_to_next_work(self, *, advance_count: int = 1, loc=None, ip=None):\n self._current_work_linear_idx += Int32(advance_count) * Int32(\n self.num_persistent_clusters\n )\n self._num_tiles_executed += Int32(1)\n\n @property\n def num_tiles_executed(self) -> Int32:\n return self._num_tiles_executed\n\n\n\"\"\"\nThis example provides an experimental implementation of the SM100 batched dense blockscaled GEMM kernel, please note that the APIs and implementation details related to this kernel may change in future releases.\n\nA high-performance persistent batched dense blockscaled GEMM example for the NVIDIA Blackwell SM100 architecture\nusing CUTE DSL.\n- Matrix A is MxKxL, L is batch dimension, A can be row-major(\"K\") or column-major(\"M\") for MXF8 input type and can only be row-major(\"K\") for MXF4/NVF4 input type\n- Matrix B is NxKxL, L is batch dimension, B can be row-major(\"N\") or column-major(\"K\") for MXF8 input type and can only be row-major(\"K\") for MXF4/NVF4 input type\n- Matrix C is MxNxL, L is batch dimension, C can be row-major(\"N\") or column-major(\"M\")\n- Matrix SFA layout is filled internally according to A shape and BlockScaledBasicChunk, which has M×ceil_div(K, sf_vec_size)×L elements respectively\n- Matrix SFB layout is filled internally according to B shape and BlockScaledBasicChunk, which has N×ceil_div(K, sf_vec_size)×L elements respectively\n\nThis GEMM kernel supports the following features:\n - Utilizes Tensor Memory Access (TMA) for efficient memory operations\n - Utilizes Blackwell's tcgen05.mma for matrix multiply-accumulate (MMA) operations (including 2cta mma instructions)\n - Implements TMA multicast with cluster to reduce L2 memory traffic\n - Support persistent tile scheduling to better overlap memory load/store with mma between tiles\n - Support warp specialization to avoid explicit pipelining between mainloop load and mma\n\nThis GEMM works as follows:\n1. DMA warp: Load A and B matrices from global memory (GMEM) to shared memory (SMEM) using TMA operations.\n2. MMA warp:\n - Load scale factor A/B from shared memory (SMEM) to tensor memory (TMEM) using tcgen05.cp instruction.\n - Perform matrix multiply-accumulate (MMA) operations using tcgen05.mma instruction.\n3. EPILOGUE warp:\n - Load completed accumulator from tensor memory (TMEM) to registers (RMEM) using tcgen05.ld.\n - Type convert C matrix to output type.\n - Optionally store C matrix from registers (RMEM) to shared memory (SMEM) to global memory (GMEM) with TMA operations,\n or directly store C matrix from registers (RMEM) to global memory (GMEM) without TMA operations.\n\nSM100 tcgen05.mma.kind.block_scale instructions operate as follows:\n- Read matrix A from SMEM\n- Read matrix B from SMEM\n- Read scalefactor A from TMEM\n- Read scalefactor B from TMEM\n- Write accumulator to TMEM\nThe accumulator in TMEM must then be loaded to registers before writing back to GMEM.\n\nInput arguments to this example is shown below:\n\n.. code-block:: bash\n\n python examples/blackwell/dense_blockscaled_gemm_persistent.py \\\n --ab_dtype Float4E2M1FN --sf_dtype Float8E8M0FNU --sf_vec_size 16 \\\n --c_dtype Float16 \\\n --mma_tiler_mn 256,128 --cluster_shape_mn 2,1 \\\n --mnkl 8192,8192,1024,1\n\nTo collect performance with NCU profiler:\n\n.. code-block:: bash\n\n ncu python examples/blackwell/dense_blockscaled_gemm_persistent.py \\\n --ab_dtype Float4E2M1FN --sf_dtype Float8E8M0FNU --sf_vec_size 16 \\\n --c_dtype Float16 \\\n --mma_tiler_mn 256,128 --cluster_shape_mn 2,1 \\\n --mnkl 8192,8192,1024,1 \\\n --warmup_iterations 1 --iterations 10 --skip_ref_check\n\n\nConstraints:\n* Supported input data types: mxf8, mxf4, nvf4\n see detailed valid dtype combinations in below Sm100BlockScaledPersistentDenseGemmKernel class documentation\n* A/B tensor must have the same data type, mixed data type is not supported (e.g., mxf8 x mxf4)\n* Mma tiler M must be 128 or 256(use_2cta_instrs)\n* Mma tiler N must be 128 or 256\n* Cluster shape M/N must be positive and power of 2, total cluster size <= 16\n* Cluster shape M must be multiple of 2 if Mma tiler M is 256(use_2cta_instrs)\n* The contiguous dimension of A/B/C tensors must be at least 16 bytes aligned,\n i.e, number of elements is a multiple of 16 and 32 for Float8 and Float4, respectively.\n\"\"\"\n\n\nclass Sm100BlockScaledPersistentDenseGemmKernel:\n \"\"\"This class implements batched matrix multiplication (C = A x SFA x B x SFB) with support for various data types\n and architectural features specific to Blackwell GPUs with persistent tile scheduling and warp specialization.\n\n :param sf_vec_size: Scalefactor vector size.\n :type sf_vec_size: int\n :param mma_tiler_mn: Shape of the Matrix Multiply-Accumulate (MMA) tile (M,N)\n :type mma_tiler_mn: Tuple[int, int]\n :param cluster_shape_mn: Cluster dimensions (M,N) for parallel processing\n :type cluster_shape_mn: Tuple[int, int]\n\n :note: In current version, A and B tensor must have the same data type\n - i.e., Float8E4M3FN for A and Float8E5M2 for B is not supported\n\n :note: Supported combinations of A/B data types, SF data typs and SF vector size:\n - MXF8: A/B: Float8E5M2/Float8E4M3FN + SF: Float8E8M0FNU + sf_vec_size: 32\n - MXF4: A/B: Float4E2M1FN + SF: Float8E8M0FNU + sf_vec_size: 32\n - NVF4: A/B: Float4E2M1FN + SF: Float8E8M0FNU/Float8E4M3FN + sf_vec_size: 16\n\n :note: Supported accumulator data types:\n - Float32\n\n :note: Supported C data types:\n - Float32\n - Float16/BFloat16\n - Float8E4M3FN/Float8E5M2\n :note: Constraints:\n - MMA tiler M must be 128 or 256 (use_2cta_instrs)\n - MMA tiler N must be 128/256\n - Cluster shape M must be multiple of 2 if Mma tiler M is 256\n - Cluster shape M/N must be positive and power of 2, total cluster size <= 16\n - Also, Cluster shape M/N must be <= 4 for scale factor multicasts due to limited size of scale factors\n\n Example:\n >>> gemm = Sm100BlockScaledPersistentDenseGemmKernel(\n ... sf_vec_size=16,\n ... mma_tiler_mn=(256, 128),\n ... cluster_shape_mn=(2, 1)\n ... )\n >>> gemm(a_tensor, b_tensor, sfa_tensor, sfb_tensor, c_tensor, max_active_clusters, stream)\n \"\"\"\n\n def __init__(\n self,\n sf_vec_size: int,\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n sm_version: str,\n ):\n \"\"\"Initializes the configuration for a Blackwell dense GEMM kernel.\n\n This configuration includes several key aspects:\n\n 1. MMA Instruction Settings (tcgen05):\n - acc_dtype: Data types for MMA accumulator, always set to Float32\n - sf_vec_size: Scalefactor A/B vector size.\n - mma_tiler_mn: The (M, N) shape of the MMA instruction tiler.\n\n 2. Cluster Shape:\n - cluster_shape_mn: The (ClusterM, ClusterN) shape of the CTA cluster.\n\n :param sf_vec_size: Scalefactor vector size.\n :type sf_vec_size: int\n :param mma_tiler_mn: Tuple (M, N) shape of the MMA instruction.\n :type mma_tiler_mn: Tuple[int, int]\n :param cluster_shape_mn: Tuple (ClusterM, ClusterN) shape of the cluster.\n :type cluster_shape_mn: Tuple[int, int]\n \"\"\"\n supported_sm_versions = [\"sm_100\", \"sm_103\"]\n assert sm_version in supported_sm_versions, (\n f\"{supported_sm_versions} are the only supported SM versions for cute-dsl backend, but encountered {sm_version}\"\n )\n\n self.acc_dtype = cutlass.Float32\n self.sf_vec_size = sf_vec_size\n self.use_2cta_instrs = mma_tiler_mn[0] == 256\n self.cluster_shape_mn = cluster_shape_mn\n # K dimension is deferred in _setup_attributes\n self.mma_tiler = (*mma_tiler_mn, 1)\n\n self.cta_group = (\n tcgen05.CtaGroup.TWO if self.use_2cta_instrs else tcgen05.CtaGroup.ONE\n )\n\n self.occupancy = 1\n # Set specialized warp ids\n self.epilog_warp_id = (\n 0,\n 1,\n 2,\n 3,\n )\n self.mma_warp_id = 4\n self.tma_warp_id = 5\n self.threads_per_warp = 32\n self.threads_per_cta = self.threads_per_warp * len(\n (self.mma_warp_id, self.tma_warp_id, *self.epilog_warp_id)\n )\n # Set barrier id for cta sync, epilogue sync and tmem ptr sync\n self.cta_sync_bar_id = 0\n self.epilog_sync_bar_id = 1\n self.tmem_ptr_sync_bar_id = 2\n self.smem_capacity = utils.get_smem_capacity_in_bytes(sm_version)\n SM100_TMEM_CAPACITY_COLUMNS = 512\n self.num_tmem_alloc_cols = SM100_TMEM_CAPACITY_COLUMNS\n\n def _setup_attributes(self):\n \"\"\"Set up configurations that are dependent on GEMM inputs\n\n This method configures various attributes based on the input tensor properties\n (data types, leading dimensions) and kernel settings:\n - Configuring tiled MMA\n - Computing MMA/cluster/tile shapes\n - Computing cluster layout\n - Computing multicast CTAs for A/B/SFA/SFB\n - Computing epilogue subtile\n - Setting up A/B/SFA/SFB/C stage counts in shared memory\n - Computing A/B/SFA/SFB/C shared memory layout\n - Computing tensor memory allocation columns\n \"\"\"\n # Compute mma instruction shapes\n mma_inst_bits_k = 256\n # (MMA_Tile_Shape_M, MMA_Tile_Shape_N, MMA_Inst_Shape_K)\n self.mma_inst_shape_mnk = (\n self.mma_tiler[0],\n self.mma_tiler[1],\n mma_inst_bits_k // self.a_dtype.width,\n )\n # (CTA_Tile_Shape_M, Round_Up(MMA_Tile_Shape_N, 128), MMA_Inst_Shape_K)\n self.mma_inst_shape_mnk_sfb = (\n self.mma_inst_shape_mnk[0] // (2 if self.use_2cta_instrs else 1),\n cute.round_up(self.mma_inst_shape_mnk[1], 128),\n self.mma_inst_shape_mnk[2],\n )\n\n tiled_mma = sm100_utils.make_blockscaled_trivial_tiled_mma(\n self.a_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.sf_dtype,\n self.sf_vec_size,\n self.cta_group,\n self.mma_inst_shape_mnk[:2],\n )\n\n tiled_mma_sfb = sm100_utils.make_blockscaled_trivial_tiled_mma(\n self.a_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.sf_dtype,\n self.sf_vec_size,\n cute.nvgpu.tcgen05.CtaGroup.ONE,\n self.mma_inst_shape_mnk_sfb[:2],\n )\n\n # Compute mma/cluster/tile shapes\n mma_inst_tile_k = 4\n self.mma_tiler = (\n self.mma_inst_shape_mnk[0],\n self.mma_inst_shape_mnk[1],\n self.mma_inst_shape_mnk[2] * mma_inst_tile_k,\n )\n self.mma_tiler_sfb = (\n self.mma_inst_shape_mnk_sfb[0],\n self.mma_inst_shape_mnk_sfb[1],\n self.mma_inst_shape_mnk_sfb[2] * mma_inst_tile_k,\n )\n self.cta_tile_shape_mnk = (\n self.mma_tiler[0] // cute.size(tiled_mma.thr_id.shape),\n self.mma_tiler[1],\n self.mma_tiler[2],\n )\n\n # Compute cluster layout\n self.cluster_layout_vmnk = cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)),\n (tiled_mma.thr_id.shape,),\n )\n self.cluster_layout_sfb_vmnk = cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)),\n (tiled_mma_sfb.thr_id.shape,),\n )\n\n # Compute number of multicast CTAs for A/B\n self.num_mcast_ctas_a = cute.size(self.cluster_layout_vmnk.shape[2])\n self.num_mcast_ctas_b = cute.size(self.cluster_layout_vmnk.shape[1])\n self.num_mcast_ctas_sfb = cute.size(self.cluster_layout_sfb_vmnk.shape[1])\n self.is_a_mcast = self.num_mcast_ctas_a > 1\n self.is_b_mcast = self.num_mcast_ctas_b > 1\n self.is_sfb_mcast = self.num_mcast_ctas_sfb > 1\n\n # Compute epilogue subtile\n self.epi_tile = sm100_utils.compute_epilogue_tile_shape(\n self.cta_tile_shape_mnk,\n self.use_2cta_instrs,\n self.c_layout,\n self.c_dtype,\n )\n\n # Setup A/B/C stage count in shared memory and ACC stage count in tensor memory\n self.num_acc_stage, self.num_ab_stage, self.num_c_stage = self._compute_stages(\n tiled_mma,\n self.mma_tiler,\n self.a_dtype,\n self.a_major_mode,\n self.b_dtype,\n self.b_major_mode,\n self.epi_tile,\n self.c_dtype,\n self.c_layout,\n self.sf_dtype,\n self.sf_vec_size,\n self.smem_capacity,\n self.occupancy,\n )\n\n # Compute A/B/SFA/SFB/C shared memory layout\n self.a_smem_layout_staged = sm100_utils.make_smem_layout_a(\n tiled_mma,\n self.mma_tiler,\n self.a_dtype,\n self.num_ab_stage,\n )\n self.b_smem_layout_staged = sm100_utils.make_smem_layout_b(\n tiled_mma,\n self.mma_tiler,\n self.b_dtype,\n self.num_ab_stage,\n )\n self.sfa_smem_layout_staged = blockscaled_utils.make_smem_layout_sfa(\n tiled_mma,\n self.mma_tiler,\n self.sf_vec_size,\n self.num_ab_stage,\n )\n self.sfb_smem_layout_staged = blockscaled_utils.make_smem_layout_sfb(\n tiled_mma,\n self.mma_tiler,\n self.sf_vec_size,\n self.num_ab_stage,\n )\n self.c_smem_layout_staged = sm100_utils.make_smem_layout_epi(\n self.c_dtype,\n self.c_layout,\n self.epi_tile,\n self.num_c_stage,\n )\n\n @cute.jit\n def __call__(\n self,\n a_tensor: cute.Tensor,\n b_tensor: cute.Tensor,\n sfa_tensor: cute.Tensor,\n sfb_tensor: cute.Tensor,\n c_tensor: cute.Tensor,\n masked_m_tensor: cute.Tensor,\n dst_signals: Optional[cute.Pointer],\n alpha_tensor: Optional[cute.Tensor],\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n ):\n \"\"\"Execute the GEMM operation in steps:\n - Setup static attributes before smem/grid/tma computation\n - Setup TMA load/store atoms and tensors\n - Compute grid size with regard to hardware constraints\n - Define shared storage for kernel\n - Launch the kernel synchronously\n\n :param a_tensor: Input tensor A\n :type a_tensor: cute.Tensor\n :param b_tensor: Input tensor B\n :type b_tensor: cute.Tensor\n :param sfa_tensor: Scale factor tensor A\n :type sfa_tensor: cute.Tensor\n :param sfb_tensor: Scale factor tensor B\n :type sfb_tensor: cute.Tensor\n :param c_tensor: Output tensor C\n :type c_tensor: cute.Tensor\n :param masked_m_tensor: Masked layout tensor M\n :type masked_m_tensor: cute.Tensor\n :param max_active_clusters: Maximum number of active clusters\n :type max_active_clusters: cutlass.Constexpr\n :param stream: CUDA stream for asynchronous execution\n :type stream: cuda.CUstream\n :param alpha_tensor: Optional 1D tensor of shape (l,) containing per-batch scaling factors.\n :type alpha_tensor: cute.Tensor\n :raises TypeError: If input data types are incompatible with the MMA instruction.\n \"\"\"\n # Setup static attributes before smem/grid/tma computation\n self.a_dtype: Type[cutlass.Numeric] = a_tensor.element_type\n self.b_dtype: Type[cutlass.Numeric] = b_tensor.element_type\n self.sf_dtype: Type[cutlass.Numeric] = sfa_tensor.element_type\n self.c_dtype: Type[cutlass.Numeric] = c_tensor.element_type\n self.a_major_mode = utils.LayoutEnum.from_tensor(a_tensor).mma_major_mode()\n self.b_major_mode = utils.LayoutEnum.from_tensor(b_tensor).mma_major_mode()\n self.c_layout = utils.LayoutEnum.from_tensor(c_tensor)\n\n # Check if input data types are compatible with MMA instruction\n if cutlass.const_expr(self.a_dtype != self.b_dtype):\n raise TypeError(f\"Type must match: {self.a_dtype} != {self.b_dtype}\")\n\n # Setup attributes that dependent on gemm inputs\n self._setup_attributes()\n\n # Setup sfa/sfb tensor by filling A/B tensor to scale factor atom layout\n # ((Atom_M, Rest_M),(Atom_K, Rest_K),RestL)\n sfa_layout = blockscaled_utils.tile_atom_to_shape_SF(\n a_tensor.shape, self.sf_vec_size\n )\n sfa_tensor = cute.make_tensor(sfa_tensor.iterator, sfa_layout)\n\n # ((Atom_N, Rest_N),(Atom_K, Rest_K),RestL)\n sfb_layout = blockscaled_utils.tile_atom_to_shape_SF(\n b_tensor.shape, self.sf_vec_size\n )\n sfb_tensor = cute.make_tensor(sfb_tensor.iterator, sfb_layout)\n\n tiled_mma = sm100_utils.make_blockscaled_trivial_tiled_mma(\n self.a_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.sf_dtype,\n self.sf_vec_size,\n self.cta_group,\n self.mma_inst_shape_mnk[:2],\n )\n\n tiled_mma_sfb = sm100_utils.make_blockscaled_trivial_tiled_mma(\n self.a_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.sf_dtype,\n self.sf_vec_size,\n cute.nvgpu.tcgen05.CtaGroup.ONE,\n self.mma_inst_shape_mnk_sfb[:2],\n )\n atom_thr_size = cute.size(tiled_mma.thr_id.shape)\n\n # Setup TMA load for A\n a_op = sm100_utils.cluster_shape_to_tma_atom_A(\n self.cluster_shape_mn, tiled_mma.thr_id\n )\n a_smem_layout = cute.slice_(self.a_smem_layout_staged, (None, None, None, 0))\n tma_atom_a, tma_tensor_a = cute.nvgpu.make_tiled_tma_atom_A(\n a_op,\n a_tensor,\n a_smem_layout,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n )\n\n # Setup TMA load for B\n b_op = sm100_utils.cluster_shape_to_tma_atom_B(\n self.cluster_shape_mn, tiled_mma.thr_id\n )\n b_smem_layout = cute.slice_(self.b_smem_layout_staged, (None, None, None, 0))\n tma_atom_b, tma_tensor_b = cute.nvgpu.make_tiled_tma_atom_B(\n b_op,\n b_tensor,\n b_smem_layout,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n )\n\n # Setup TMA load for SFA\n sfa_op = sm100_utils.cluster_shape_to_tma_atom_A(\n self.cluster_shape_mn, tiled_mma.thr_id\n )\n sfa_smem_layout = cute.slice_(\n self.sfa_smem_layout_staged, (None, None, None, 0)\n )\n tma_atom_sfa, tma_tensor_sfa = cute.nvgpu.make_tiled_tma_atom_A(\n sfa_op,\n sfa_tensor,\n sfa_smem_layout,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n internal_type=cutlass.Int16,\n )\n\n # Setup TMA load for SFB\n sfb_op = sm100_utils.cluster_shape_to_tma_atom_SFB(\n self.cluster_shape_mn, tiled_mma.thr_id\n )\n sfb_smem_layout = cute.slice_(\n self.sfb_smem_layout_staged, (None, None, None, 0)\n )\n tma_atom_sfb, tma_tensor_sfb = cute.nvgpu.make_tiled_tma_atom_B(\n sfb_op,\n sfb_tensor,\n sfb_smem_layout,\n self.mma_tiler_sfb,\n tiled_mma_sfb,\n self.cluster_layout_sfb_vmnk.shape,\n internal_type=cutlass.Int16,\n )\n\n a_copy_size = cute.size_in_bytes(self.a_dtype, a_smem_layout)\n b_copy_size = cute.size_in_bytes(self.b_dtype, b_smem_layout)\n sfa_copy_size = cute.size_in_bytes(self.sf_dtype, sfa_smem_layout)\n sfb_copy_size = cute.size_in_bytes(self.sf_dtype, sfb_smem_layout)\n self.num_tma_load_bytes = (\n a_copy_size + b_copy_size + sfa_copy_size + sfb_copy_size\n ) * atom_thr_size\n\n # Setup TMA store for C\n epi_smem_layout = cute.slice_(self.c_smem_layout_staged, (None, None, 0))\n tma_atom_c, tma_tensor_c = cpasync.make_tiled_tma_atom(\n cpasync.CopyBulkTensorTileS2GOp(),\n c_tensor,\n epi_smem_layout,\n self.epi_tile,\n )\n\n # Compute grid size\n self.tile_sched_params, grid = self._compute_grid(\n masked_m_tensor, # add masked layout\n dst_signals,\n c_tensor,\n self.cta_tile_shape_mnk,\n self.cluster_shape_mn,\n max_active_clusters,\n )\n\n self.buffer_align_bytes = 1024\n\n # Define shared storage for kernel\n @cute.struct\n class SharedStorage:\n ab_full_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_ab_stage]\n ab_empty_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_ab_stage]\n acc_full_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]\n acc_empty_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]\n tmem_dealloc_mbar_ptr: cutlass.Int64\n tmem_holding_buf: cutlass.Int32\n # (EPI_TILE_M, EPI_TILE_N, STAGE)\n sC: cute.struct.Align[\n cute.struct.MemRange[\n self.c_dtype,\n cute.cosize(self.c_smem_layout_staged.outer),\n ],\n self.buffer_align_bytes,\n ]\n # (MMA, MMA_M, MMA_K, STAGE)\n sA: cute.struct.Align[\n cute.struct.MemRange[\n self.a_dtype, cute.cosize(self.a_smem_layout_staged.outer)\n ],\n self.buffer_align_bytes,\n ]\n # (MMA, MMA_N, MMA_K, STAGE)\n sB: cute.struct.Align[\n cute.struct.MemRange[\n self.b_dtype, cute.cosize(self.b_smem_layout_staged.outer)\n ],\n self.buffer_align_bytes,\n ]\n # (MMA, MMA_M, MMA_K, STAGE)\n sSFA: cute.struct.Align[\n cute.struct.MemRange[\n self.sf_dtype, cute.cosize(self.sfa_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n # (MMA, MMA_N, MMA_K, STAGE)\n sSFB: cute.struct.Align[\n cute.struct.MemRange[\n self.sf_dtype, cute.cosize(self.sfb_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n # Launch the kernel synchronously\n self.kernel(\n tiled_mma,\n tiled_mma_sfb,\n tma_atom_a,\n tma_tensor_a,\n tma_atom_b,\n tma_tensor_b,\n tma_atom_sfa,\n tma_tensor_sfa,\n tma_atom_sfb,\n tma_tensor_sfb,\n tma_atom_c,\n tma_tensor_c,\n alpha_tensor,\n self.cluster_layout_vmnk,\n self.cluster_layout_sfb_vmnk,\n self.a_smem_layout_staged,\n self.b_smem_layout_staged,\n self.sfa_smem_layout_staged,\n self.sfb_smem_layout_staged,\n self.c_smem_layout_staged,\n self.epi_tile,\n self.tile_sched_params,\n ).launch(\n grid=grid,\n block=[self.threads_per_cta, 1, 1],\n cluster=(*self.cluster_shape_mn, 1),\n smem=self.shared_storage.size_in_bytes(), # type: ignore[attr-defined]\n stream=stream,\n )\n return\n\n # GPU device kernel\n @cute.kernel\n def kernel(\n self,\n tiled_mma: cute.TiledMma,\n tiled_mma_sfb: cute.TiledMma,\n tma_atom_a: cute.CopyAtom,\n mA_mkl: cute.Tensor,\n tma_atom_b: cute.CopyAtom,\n mB_nkl: cute.Tensor,\n tma_atom_sfa: cute.CopyAtom,\n mSFA_mkl: cute.Tensor,\n tma_atom_sfb: cute.CopyAtom,\n mSFB_nkl: cute.Tensor,\n tma_atom_c: Optional[cute.CopyAtom],\n mC_mnl: cute.Tensor,\n alpha: Optional[cute.Tensor],\n cluster_layout_vmnk: cute.Layout,\n cluster_layout_sfb_vmnk: cute.Layout,\n a_smem_layout_staged: cute.ComposedLayout,\n b_smem_layout_staged: cute.ComposedLayout,\n sfa_smem_layout_staged: cute.Layout,\n sfb_smem_layout_staged: cute.Layout,\n c_smem_layout_staged: Union[cute.Layout, cute.ComposedLayout, None],\n epi_tile: cute.Tile,\n tile_sched_params: MaskedSchedulerParams,\n ):\n \"\"\"\n GPU device kernel performing the Persistent batched GEMM computation.\n \"\"\"\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n\n #\n # Prefetch tma desc\n #\n if warp_idx == self.tma_warp_id:\n cpasync.prefetch_descriptor(tma_atom_a)\n cpasync.prefetch_descriptor(tma_atom_b)\n cpasync.prefetch_descriptor(tma_atom_sfa)\n cpasync.prefetch_descriptor(tma_atom_sfb)\n cpasync.prefetch_descriptor(tma_atom_c)\n\n use_2cta_instrs = cute.size(tiled_mma.thr_id.shape) == 2\n\n #\n # Setup cta/thread coordinates\n #\n # Coords inside cluster\n bidx, bidy, bidz = cute.arch.block_idx()\n mma_tile_coord_v = bidx % cute.size(tiled_mma.thr_id.shape)\n is_leader_cta = mma_tile_coord_v == 0\n cta_rank_in_cluster = cute.arch.make_warp_uniform(\n cute.arch.block_idx_in_cluster()\n )\n block_in_cluster_coord_vmnk = cluster_layout_vmnk.get_flat_coord(\n cta_rank_in_cluster\n )\n block_in_cluster_coord_sfb_vmnk = cluster_layout_sfb_vmnk.get_flat_coord(\n cta_rank_in_cluster\n )\n # Coord inside cta\n tidx, _, _ = cute.arch.thread_idx()\n\n #\n # Alloc and init: a+b full/empty, accumulator full/empty, tensor memory dealloc barrier\n #\n smem = utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n tmem_dealloc_mbar_ptr = storage.tmem_dealloc_mbar_ptr\n tmem_holding_buf = storage.tmem_holding_buf\n\n # Initialize mainloop ab_pipeline (barrier) and states\n ab_pipeline_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread)\n num_tma_producer = self.num_mcast_ctas_a + self.num_mcast_ctas_b - 1\n ab_pipeline_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, num_tma_producer\n )\n ab_pipeline = pipeline.PipelineTmaUmma.create(\n barrier_storage=storage.ab_full_mbar_ptr.data_ptr(),\n num_stages=self.num_ab_stage,\n producer_group=ab_pipeline_producer_group,\n consumer_group=ab_pipeline_consumer_group,\n tx_count=self.num_tma_load_bytes,\n cta_layout_vmnk=cluster_layout_vmnk,\n )\n\n # Initialize acc_pipeline (barrier) and states\n acc_pipeline_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread)\n num_acc_consumer_threads = (\n self.threads_per_warp\n * len(self.epilog_warp_id)\n * (2 if use_2cta_instrs else 1)\n )\n acc_pipeline_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, num_acc_consumer_threads\n )\n acc_pipeline = pipeline.PipelineUmmaAsync.create(\n barrier_storage=storage.acc_full_mbar_ptr.data_ptr(),\n num_stages=self.num_acc_stage,\n producer_group=acc_pipeline_producer_group,\n consumer_group=acc_pipeline_consumer_group,\n cta_layout_vmnk=cluster_layout_vmnk,\n )\n\n # Tensor memory dealloc barrier init\n if use_2cta_instrs:\n if warp_idx == self.tma_warp_id:\n num_tmem_dealloc_threads = 32\n with cute.arch.elect_one():\n cute.arch.mbarrier_init(\n tmem_dealloc_mbar_ptr, num_tmem_dealloc_threads\n )\n cute.arch.mbarrier_init_fence()\n\n # Cluster arrive after barrier init\n if cute.size(self.cluster_shape_mn) > 1:\n cute.arch.cluster_arrive_relaxed()\n\n #\n # Setup smem tensor A/B/SFA/SFB/C\n #\n # (EPI_TILE_M, EPI_TILE_N, STAGE)\n sC = storage.sC.get_tensor(\n c_smem_layout_staged.outer, swizzle=c_smem_layout_staged.inner\n )\n # (MMA, MMA_M, MMA_K, STAGE)\n sA = storage.sA.get_tensor(\n a_smem_layout_staged.outer, swizzle=a_smem_layout_staged.inner\n )\n # (MMA, MMA_N, MMA_K, STAGE)\n sB = storage.sB.get_tensor(\n b_smem_layout_staged.outer, swizzle=b_smem_layout_staged.inner\n )\n # (MMA, MMA_M, MMA_K, STAGE)\n sSFA = storage.sSFA.get_tensor(sfa_smem_layout_staged)\n # (MMA, MMA_N, MMA_K, STAGE)\n sSFB = storage.sSFB.get_tensor(sfb_smem_layout_staged)\n\n #\n # Compute multicast mask for A/B/SFA/SFB buffer full\n #\n a_full_mcast_mask = None\n b_full_mcast_mask = None\n sfa_full_mcast_mask = None\n sfb_full_mcast_mask = None\n if cutlass.const_expr(self.is_a_mcast or self.is_b_mcast or use_2cta_instrs):\n a_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=2\n )\n b_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=1\n )\n sfa_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=2\n )\n sfb_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_sfb_vmnk, block_in_cluster_coord_sfb_vmnk, mcast_mode=1\n )\n\n #\n # Local_tile partition global tensors\n #\n # (bM, bK, RestM, RestK, RestL)\n gA_mkl = cute.local_tile(\n mA_mkl, cute.slice_(self.mma_tiler, (None, 0, None)), (None, None, None)\n )\n # (bN, bK, RestN, RestK, RestL)\n gB_nkl = cute.local_tile(\n mB_nkl, cute.slice_(self.mma_tiler, (0, None, None)), (None, None, None)\n )\n # (bM, bK, RestM, RestK, RestL)\n gSFA_mkl = cute.local_tile(\n mSFA_mkl, cute.slice_(self.mma_tiler, (None, 0, None)), (None, None, None)\n )\n # (bN, bK, RestN, RestK, RestL)\n gSFB_nkl = cute.local_tile(\n mSFB_nkl, cute.slice_(self.mma_tiler, (0, None, None)), (None, None, None)\n )\n # (bM, bN, RestM, RestN, RestL)\n gC_mnl = cute.local_tile(\n mC_mnl, cute.slice_(self.mma_tiler, (None, None, 0)), (None, None, None)\n )\n k_block_cnt = cute.size(gA_mkl, mode=[3])\n\n #\n # Partition global tensor for TiledMMA_A/B/C\n #\n thr_mma = tiled_mma.get_slice(mma_tile_coord_v)\n thr_mma_sfb = tiled_mma_sfb.get_slice(mma_tile_coord_v)\n # (MMA, MMA_M, MMA_K, RestM, RestK, RestL)\n tCgA = thr_mma.partition_A(gA_mkl)\n # (MMA, MMA_N, MMA_K, RestN, RestK, RestL)\n tCgB = thr_mma.partition_B(gB_nkl)\n # (MMA, MMA_M, MMA_K, RestM, RestK, RestL)\n tCgSFA = thr_mma.partition_A(gSFA_mkl)\n # (MMA, MMA_N, MMA_K, RestN, RestK, RestL)\n tCgSFB = thr_mma_sfb.partition_B(gSFB_nkl)\n # (MMA, MMA_M, MMA_N, RestM, RestN, RestL)\n tCgC = thr_mma.partition_C(gC_mnl)\n\n #\n # Partition global/shared tensor for TMA load A/B\n #\n # TMA load A partition_S/D\n a_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_vmnk, (0, 0, None, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), RestM, RestK, RestL)\n tAsA, tAgA = cpasync.tma_partition(\n tma_atom_a,\n block_in_cluster_coord_vmnk[2],\n a_cta_layout,\n cute.group_modes(sA, 0, 3),\n cute.group_modes(tCgA, 0, 3),\n )\n # TMA load B partition_S/D\n b_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_vmnk, (0, None, 0, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), RestN, RestK, RestL)\n tBsB, tBgB = cpasync.tma_partition(\n tma_atom_b,\n block_in_cluster_coord_vmnk[1],\n b_cta_layout,\n cute.group_modes(sB, 0, 3),\n cute.group_modes(tCgB, 0, 3),\n )\n\n # TMA load SFA partition_S/D\n sfa_cta_layout = a_cta_layout\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), RestM, RestK, RestL)\n tAsSFA, tAgSFA = cute.nvgpu.cpasync.tma_partition(\n tma_atom_sfa,\n block_in_cluster_coord_vmnk[2],\n sfa_cta_layout,\n cute.group_modes(sSFA, 0, 3),\n cute.group_modes(tCgSFA, 0, 3),\n )\n tAsSFA = cute.filter_zeros(tAsSFA)\n tAgSFA = cute.filter_zeros(tAgSFA)\n\n # TMA load SFB partition_S/D\n sfb_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_sfb_vmnk, (0, None, 0, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), RestN, RestK, RestL)\n tBsSFB, tBgSFB = cute.nvgpu.cpasync.tma_partition(\n tma_atom_sfb,\n block_in_cluster_coord_sfb_vmnk[1],\n sfb_cta_layout,\n cute.group_modes(sSFB, 0, 3),\n cute.group_modes(tCgSFB, 0, 3),\n )\n tBsSFB = cute.filter_zeros(tBsSFB)\n tBgSFB = cute.filter_zeros(tBgSFB)\n\n #\n # Partition shared/tensor memory tensor for TiledMMA_A/B/C\n #\n # (MMA, MMA_M, MMA_K, STAGE)\n tCrA = tiled_mma.make_fragment_A(sA)\n # (MMA, MMA_N, MMA_K, STAGE)\n tCrB = tiled_mma.make_fragment_B(sB)\n # (MMA, MMA_M, MMA_N)\n acc_shape = tiled_mma.partition_shape_C(self.mma_tiler[:2])\n # (MMA, MMA_M, MMA_N, STAGE)\n tCtAcc_fake = tiled_mma.make_fragment_C(\n cute.append(acc_shape, self.num_acc_stage)\n )\n\n #\n # Cluster wait before tensor memory alloc\n #\n if cute.size(self.cluster_shape_mn) > 1:\n cute.arch.cluster_wait()\n else:\n cute.arch.barrier(\n barrier_id=self.cta_sync_bar_id, number_of_threads=self.threads_per_cta\n )\n\n #\n # Specialized TMA load warp\n #\n if warp_idx == self.tma_warp_id:\n #\n # Persistent tile scheduling loop\n #\n tile_sched = MaskedScheduler.create(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n ab_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_ab_stage\n )\n\n while work_tile.is_valid_tile:\n # Get tile coord from tile scheduler\n cur_tile_coord = work_tile.tile_idx\n mma_tile_coord_mnl = (\n cur_tile_coord[0] // cute.size(tiled_mma.thr_id.shape),\n cur_tile_coord[1],\n cur_tile_coord[2],\n )\n\n #\n # Slice to per mma tile index\n #\n # ((atom_v, rest_v), RestK)\n tAgA_slice = tAgA[\n (None, mma_tile_coord_mnl[0], None, mma_tile_coord_mnl[2])\n ]\n # ((atom_v, rest_v), RestK)\n tBgB_slice = tBgB[\n (None, mma_tile_coord_mnl[1], None, mma_tile_coord_mnl[2])\n ]\n\n # ((atom_v, rest_v), RestK)\n tAgSFA_slice = tAgSFA[\n (None, mma_tile_coord_mnl[0], None, mma_tile_coord_mnl[2])\n ]\n # ((atom_v, rest_v), RestK)\n tBgSFB_slice = tBgSFB[\n (None, mma_tile_coord_mnl[1], None, mma_tile_coord_mnl[2])\n ]\n\n # Peek (try_wait) AB buffer empty for k_block = prefetch_k_block_cnt\n ab_producer_state.reset_count()\n peek_ab_empty_status = cutlass.Boolean(1)\n if ab_producer_state.count < k_block_cnt:\n peek_ab_empty_status = ab_pipeline.producer_try_acquire(\n ab_producer_state\n )\n #\n # Tma load loop\n #\n for k_block in cutlass.range(0, k_block_cnt, 1, unroll=1): # noqa: B007\n # Conditionally wait for AB buffer empty\n ab_pipeline.producer_acquire(\n ab_producer_state, peek_ab_empty_status\n )\n\n # TMA load A/B/SFA/SFB\n cute.copy(\n tma_atom_a,\n tAgA_slice[(None, ab_producer_state.count)],\n tAsA[(None, ab_producer_state.index)],\n tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_producer_state),\n mcast_mask=a_full_mcast_mask,\n )\n cute.copy(\n tma_atom_b,\n tBgB_slice[(None, ab_producer_state.count)],\n tBsB[(None, ab_producer_state.index)],\n tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_producer_state),\n mcast_mask=b_full_mcast_mask,\n )\n cute.copy(\n tma_atom_sfa,\n tAgSFA_slice[(None, ab_producer_state.count)],\n tAsSFA[(None, ab_producer_state.index)],\n tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_producer_state),\n mcast_mask=sfa_full_mcast_mask,\n )\n cute.copy(\n tma_atom_sfb,\n tBgSFB_slice[(None, ab_producer_state.count)],\n tBsSFB[(None, ab_producer_state.index)],\n tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_producer_state),\n mcast_mask=sfb_full_mcast_mask,\n )\n\n # Peek (try_wait) AB buffer empty for k_block = prefetch_k_block_cnt + k_block + 1\n ab_producer_state.advance()\n peek_ab_empty_status = cutlass.Boolean(1)\n if ab_producer_state.count < k_block_cnt:\n peek_ab_empty_status = ab_pipeline.producer_try_acquire(\n ab_producer_state\n )\n\n #\n # Advance to next tile\n #\n tile_sched.advance_to_next_work()\n work_tile, _ = tile_sched.get_current_work()\n\n #\n # Wait A/B buffer empty\n #\n ab_pipeline.producer_tail(ab_producer_state)\n\n #\n # Specialized MMA warp\n #\n if warp_idx == self.mma_warp_id:\n #\n # Bar sync for retrieve tensor memory ptr from shared mem\n #\n tmem_ptr_read_threads = self.threads_per_warp * len(\n (self.mma_warp_id, *self.epilog_warp_id)\n )\n cute.arch.barrier(\n barrier_id=self.tmem_ptr_sync_bar_id,\n number_of_threads=tmem_ptr_read_threads,\n )\n\n #\n # Retrieving tensor memory ptr and make accumulator/SFA/SFB tensor\n #\n # Make accumulator tmem tensor\n acc_tmem_ptr = cute.arch.retrieve_tmem_ptr(\n self.acc_dtype,\n alignment=16,\n ptr_to_buffer_holding_addr=tmem_holding_buf,\n )\n # (MMA, MMA_M, MMA_N, STAGE)\n tCtAcc_base = cute.make_tensor(acc_tmem_ptr, tCtAcc_fake.layout)\n\n # Make SFA tmem tensor\n sfa_tmem_ptr = cute.recast_ptr(\n acc_tmem_ptr + tcgen05.find_tmem_tensor_col_offset(tCtAcc_base),\n dtype=self.sf_dtype,\n )\n # (MMA, MMA_M, MMA_K)\n tCtSFA_layout = blockscaled_utils.make_tmem_layout_sfa(\n tiled_mma,\n self.mma_tiler,\n self.sf_vec_size,\n cute.slice_(sfa_smem_layout_staged, (None, None, None, 0)),\n )\n tCtSFA = cute.make_tensor(sfa_tmem_ptr, tCtSFA_layout)\n\n # Make SFB tmem tensor\n sfb_tmem_ptr = cute.recast_ptr(\n acc_tmem_ptr\n + tcgen05.find_tmem_tensor_col_offset(tCtAcc_base)\n + tcgen05.find_tmem_tensor_col_offset(tCtSFA),\n dtype=self.sf_dtype,\n )\n # (MMA, MMA_N, MMA_K)\n tCtSFB_layout = blockscaled_utils.make_tmem_layout_sfb(\n tiled_mma,\n self.mma_tiler,\n self.sf_vec_size,\n cute.slice_(sfb_smem_layout_staged, (None, None, None, 0)),\n )\n tCtSFB = cute.make_tensor(sfb_tmem_ptr, tCtSFB_layout)\n #\n # Partition for S2T copy of SFA/SFB\n #\n tiled_copy_s2t_sfa, tCsSFA_compact_s2t, tCtSFA_compact_s2t = (\n self.mainloop_s2t_copy_and_partition(sSFA, tCtSFA)\n )\n tiled_copy_s2t_sfb, tCsSFB_compact_s2t, tCtSFB_compact_s2t = (\n self.mainloop_s2t_copy_and_partition(sSFB, tCtSFB)\n )\n\n #\n # Persistent tile scheduling loop\n #\n tile_sched = MaskedScheduler.create(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n ab_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_ab_stage\n )\n acc_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_acc_stage\n )\n\n while work_tile.is_valid_tile:\n # Get tile coord from tile scheduler\n cur_tile_coord = work_tile.tile_idx\n mma_tile_coord_mnl = (\n cur_tile_coord[0] // cute.size(tiled_mma.thr_id.shape),\n cur_tile_coord[1],\n cur_tile_coord[2],\n )\n\n # Set tensor memory buffer for current tile\n # (MMA, MMA_M, MMA_N)\n tCtAcc = tCtAcc_base[(None, None, None, acc_producer_state.index)]\n\n # Peek (try_wait) AB buffer full for k_block = 0\n ab_consumer_state.reset_count()\n peek_ab_full_status = cutlass.Boolean(1)\n if ab_consumer_state.count < k_block_cnt and is_leader_cta:\n peek_ab_full_status = ab_pipeline.consumer_try_wait(\n ab_consumer_state\n )\n\n #\n # Wait for accumulator buffer empty\n #\n if is_leader_cta:\n acc_pipeline.producer_acquire(acc_producer_state)\n\n #\n # Reset the ACCUMULATE field for each tile\n #\n tiled_mma.set(tcgen05.Field.ACCUMULATE, False)\n\n #\n # Mma mainloop\n #\n for k_block in cutlass.range_constexpr(k_block_cnt): # noqa: B007\n if is_leader_cta:\n # Conditionally wait for AB buffer full\n ab_pipeline.consumer_wait(\n ab_consumer_state, peek_ab_full_status\n )\n\n # Copy SFA/SFB from smem to tmem\n s2t_stage_coord = (\n None,\n None,\n None,\n None,\n ab_consumer_state.index,\n )\n tCsSFA_compact_s2t_staged = tCsSFA_compact_s2t[s2t_stage_coord]\n tCsSFB_compact_s2t_staged = tCsSFB_compact_s2t[s2t_stage_coord]\n cute.copy(\n tiled_copy_s2t_sfa,\n tCsSFA_compact_s2t_staged,\n tCtSFA_compact_s2t,\n )\n cute.copy(\n tiled_copy_s2t_sfb,\n tCsSFB_compact_s2t_staged,\n tCtSFB_compact_s2t,\n )\n\n # tCtAcc += tCrA * tCrSFA * tCrB * tCrSFB\n num_kphases = cute.size(tCrA, mode=[2])\n for kphase_idx in cutlass.range(num_kphases, unroll_full=True):\n kphase_coord = (\n None,\n None,\n kphase_idx,\n ab_consumer_state.index,\n )\n\n # Set SFA/SFB tensor to tiled_mma\n sf_kphase_coord = (None, None, kphase_idx)\n tiled_mma.set(\n tcgen05.Field.SFA,\n tCtSFA[sf_kphase_coord].iterator,\n )\n tiled_mma.set(\n tcgen05.Field.SFB,\n tCtSFB[sf_kphase_coord].iterator,\n )\n\n cute.gemm(\n tiled_mma,\n tCtAcc,\n tCrA[kphase_coord],\n tCrB[kphase_coord],\n tCtAcc,\n )\n\n # Enable accumulate on tCtAcc after first kphase\n tiled_mma.set(tcgen05.Field.ACCUMULATE, True)\n\n # Async arrive AB buffer empty\n ab_pipeline.consumer_release(ab_consumer_state)\n\n # Peek (try_wait) AB buffer full for k_block = k_block + 1\n ab_consumer_state.advance()\n peek_ab_full_status = cutlass.Boolean(1)\n if ab_consumer_state.count < k_block_cnt:\n if is_leader_cta:\n peek_ab_full_status = ab_pipeline.consumer_try_wait(\n ab_consumer_state\n )\n\n #\n # Async arrive accumulator buffer full\n #\n if is_leader_cta:\n acc_pipeline.producer_commit(acc_producer_state)\n acc_producer_state.advance()\n\n #\n # Advance to next tile\n #\n tile_sched.advance_to_next_work()\n work_tile, _ = tile_sched.get_current_work()\n\n #\n # Wait for accumulator buffer empty\n #\n acc_pipeline.producer_tail(acc_producer_state)\n #\n # Specialized epilogue warps\n #\n if warp_idx < self.mma_warp_id:\n #\n # Alloc tensor memory buffer\n #\n if warp_idx == self.epilog_warp_id[0]:\n cute.arch.alloc_tmem(\n self.num_tmem_alloc_cols,\n tmem_holding_buf,\n is_two_cta=use_2cta_instrs,\n )\n\n #\n # Bar sync for retrieve tensor memory ptr from shared memory\n #\n tmem_ptr_read_threads = self.threads_per_warp * len(\n (self.mma_warp_id, *self.epilog_warp_id)\n )\n cute.arch.barrier(\n barrier_id=self.tmem_ptr_sync_bar_id,\n number_of_threads=tmem_ptr_read_threads,\n )\n\n #\n # Retrieving tensor memory ptr and make accumulator tensor\n #\n acc_tmem_ptr = cute.arch.retrieve_tmem_ptr(\n self.acc_dtype,\n alignment=16,\n ptr_to_buffer_holding_addr=tmem_holding_buf,\n )\n # (MMA, MMA_M, MMA_N, STAGE)\n tCtAcc_base = cute.make_tensor(acc_tmem_ptr, tCtAcc_fake.layout)\n\n #\n # Partition for epilogue\n #\n epi_tidx = tidx\n tiled_copy_t2r, tTR_tAcc_base, tTR_rAcc = (\n self.epilog_tmem_copy_and_partition(\n epi_tidx, tCtAcc_base, tCgC, epi_tile, use_2cta_instrs\n )\n )\n\n tTR_rC = cute.make_fragment(tTR_rAcc.shape, self.c_dtype)\n tiled_copy_r2s, tRS_rC, tRS_sC = self.epilog_smem_copy_and_partition(\n tiled_copy_t2r, tTR_rC, epi_tidx, sC\n )\n tma_atom_c, bSG_sC, bSG_gC_partitioned = (\n self.epilog_gmem_copy_and_partition(\n epi_tidx, tma_atom_c, tCgC, epi_tile, sC\n )\n )\n\n #\n # Persistent tile scheduling loop\n #\n tile_sched = MaskedScheduler.create(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n acc_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_acc_stage\n )\n\n # Threads/warps participating in tma store pipeline\n c_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n self.threads_per_warp * len(self.epilog_warp_id),\n self.threads_per_warp * len(self.epilog_warp_id),\n )\n c_pipeline = pipeline.PipelineTmaStore.create(\n num_stages=self.num_c_stage,\n producer_group=c_producer_group,\n )\n\n if cutlass.const_expr(tile_sched_params.dst_signals is not None):\n assert self.num_c_stage < 256, \"must be representable in 1 byte\"\n num_experts = tile_sched_params.masked_m.shape[0]\n assert num_experts <= 8, \"need to be packable into a u64\"\n dsm_pending_packed = Uint64(0)\n dsm_pending_idx = Int32(0)\n dsm_counter = Uint8(0)\n\n while work_tile.is_valid_tile:\n # Get tile coord from tile scheduler\n cur_tile_coord = work_tile.tile_idx\n mma_tile_coord_mnl = (\n cur_tile_coord[0] // cute.size(tiled_mma.thr_id.shape),\n cur_tile_coord[1],\n cur_tile_coord[2],\n )\n\n #\n # Slice to per mma tile index\n #\n # ((ATOM_V, REST_V), EPI_M, EPI_N)\n bSG_gC = bSG_gC_partitioned[\n (\n None,\n None,\n None,\n *mma_tile_coord_mnl,\n )\n ]\n\n # Set tensor memory buffer for current tile\n # (T2R, T2R_M, T2R_N, EPI_M, EPI_M)\n tTR_tAcc = tTR_tAcc_base[\n (None, None, None, None, None, acc_consumer_state.index)\n ]\n\n #\n # Wait for accumulator buffer full\n #\n acc_pipeline.consumer_wait(acc_consumer_state)\n\n tTR_tAcc = cute.group_modes(tTR_tAcc, 3, cute.rank(tTR_tAcc))\n bSG_gC = cute.group_modes(bSG_gC, 1, cute.rank(bSG_gC))\n\n #\n # Store accumulator to global memory in subtiles\n #\n subtile_cnt = cute.size(tTR_tAcc.shape, mode=[3])\n num_prev_subtiles = tile_sched.num_tiles_executed * subtile_cnt\n for subtile_idx in cutlass.range(subtile_cnt):\n #\n # Load accumulator from tensor memory buffer to register\n #\n tTR_tAcc_mn = tTR_tAcc[(None, None, None, subtile_idx)]\n cute.copy(tiled_copy_t2r, tTR_tAcc_mn, tTR_rAcc)\n\n #\n # Convert to C type\n #\n acc_vec = tiled_copy_r2s.retile(tTR_rAcc).load()\n if cutlass.const_expr(alpha is not None):\n acc_vec = acc_vec * alpha[work_tile.tile_idx[2]]\n\n acc_vec = acc_vec.to(self.c_dtype)\n tRS_rC.store(acc_vec)\n\n #\n # Store C to shared memory\n #\n c_buffer = (num_prev_subtiles + subtile_idx) % self.num_c_stage\n cute.copy(\n tiled_copy_r2s,\n tRS_rC,\n tRS_sC[(None, None, None, c_buffer)],\n )\n # Fence and barrier to make sure shared memory store is visible to TMA store\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n epilog_threads = self.threads_per_warp * len(self.epilog_warp_id)\n cute.arch.barrier(\n barrier_id=self.epilog_sync_bar_id,\n number_of_threads=epilog_threads,\n )\n\n #\n # TMA store C to global memory\n #\n if warp_idx == self.epilog_warp_id[0]:\n cute.copy(\n tma_atom_c,\n bSG_sC[(None, c_buffer)],\n bSG_gC[(None, subtile_idx)],\n )\n\n # Fence and barrier to make sure shared memory store is visible to TMA store\n c_pipeline.producer_commit()\n\n if cutlass.const_expr(\n tile_sched_params.dst_signals is not None\n ):\n dsm_counter = (dsm_counter + 1).to(Uint8)\n will_write_signals = (\n read_byte(dsm_pending_packed, dsm_pending_idx)\n == dsm_counter\n )\n\n if will_write_signals:\n # The original c_pipeline.producer_acquire()\n # := PipelineTmaStore.producer_acquire()\n # := TmaStoreFence.wait()\n # := cute.arch.cp_async_bulk_wait_group(self.num_stages - 1, read=True)\n cute.arch.cp_async_bulk_wait_group(\n self.num_c_stage - 1,\n # Change `read` from True to False to also wait writes\n read=False,\n )\n else:\n c_pipeline.producer_acquire()\n\n else:\n c_pipeline.producer_acquire()\n\n cute.arch.barrier(\n barrier_id=self.epilog_sync_bar_id,\n number_of_threads=epilog_threads,\n )\n\n if cutlass.const_expr(tile_sched_params.dst_signals is not None):\n lane_id = tidx % 32\n if warp_idx == self.epilog_warp_id[0] and lane_id == 0:\n while (dsm_pending_idx < num_experts) and (\n read_byte(dsm_pending_packed, dsm_pending_idx)\n == dsm_counter\n ):\n atomic_add_release_global(\n tile_sched_params.dst_signals.toint()\n + sizeof_i32 * dsm_pending_idx,\n value=1,\n )\n dsm_pending_idx += 1\n\n #\n # Async arrive accumulator buffer empty\n #\n acc_pipeline.consumer_release(acc_consumer_state)\n acc_consumer_state.advance()\n\n #\n # Advance to next tile\n #\n tile_sched.advance_to_next_work()\n work_tile, dsm_pending_packed = tile_sched.get_current_work(\n dsm_pending_packed=dsm_pending_packed,\n dsm_counter=dsm_counter,\n num_c_stage=self.num_c_stage,\n )\n\n #\n # Dealloc the tensor memory buffer\n #\n if warp_idx == self.epilog_warp_id[0]:\n cute.arch.relinquish_tmem_alloc_permit(is_two_cta=use_2cta_instrs)\n epilog_threads = self.threads_per_warp * len(self.epilog_warp_id)\n cute.arch.barrier(\n barrier_id=self.epilog_sync_bar_id, number_of_threads=epilog_threads\n )\n if warp_idx == self.epilog_warp_id[0]:\n if use_2cta_instrs:\n cute.arch.mbarrier_arrive(\n tmem_dealloc_mbar_ptr, cta_rank_in_cluster ^ 1\n )\n cute.arch.mbarrier_wait(tmem_dealloc_mbar_ptr, 0)\n cute.arch.dealloc_tmem(\n acc_tmem_ptr, self.num_tmem_alloc_cols, is_two_cta=use_2cta_instrs\n )\n #\n # Wait for C store complete\n #\n if cutlass.const_expr(tile_sched_params.dst_signals is not None):\n # The original c_pipeline.producer_tail()\n # := PipelineTmaStore.producer_tail()\n # := TmaStoreFence.tail()\n # := cute.arch.cp_async_bulk_wait_group(0, read=True)\n cute.arch.cp_async_bulk_wait_group(\n 0,\n # Change `read` from True to False to also wait writes\n read=False,\n )\n\n lane_id = tidx % 32\n if warp_idx == self.epilog_warp_id[0] and lane_id == 0:\n while dsm_pending_idx < num_experts:\n atomic_add_release_global(\n tile_sched_params.dst_signals.toint()\n + sizeof_i32 * dsm_pending_idx,\n value=1,\n )\n dsm_pending_idx += 1\n\n else:\n c_pipeline.producer_tail()\n\n def mainloop_s2t_copy_and_partition(\n self,\n sSF: cute.Tensor,\n tSF: cute.Tensor,\n ) -> Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]:\n \"\"\"\n Make tiledCopy for smem to tmem load for scale factor tensor, then use it to partition smem memory (source) and tensor memory (destination).\n\n :param sSF: The scale factor tensor in smem\n :type sSF: cute.Tensor\n :param tSF: The scale factor tensor in tmem\n :type tSF: cute.Tensor\n\n :return: A tuple containing (tiled_copy_s2t, tCsSF_compact_s2t, tCtSF_compact_s2t) where:\n - tiled_copy_s2t: The tiled copy operation for smem to tmem load for scale factor tensor(s2t)\n - tCsSF_compact_s2t: The partitioned scale factor tensor in smem\n - tSF_compact_s2t: The partitioned scale factor tensor in tmem\n :rtype: Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]\n \"\"\"\n # (MMA, MMA_MN, MMA_K, STAGE)\n tCsSF_compact = cute.filter_zeros(sSF)\n # (MMA, MMA_MN, MMA_K)\n tCtSF_compact = cute.filter_zeros(tSF)\n\n # Make S2T CopyAtom and tiledCopy\n copy_atom_s2t = cute.make_copy_atom(\n tcgen05.Cp4x32x128bOp(self.cta_group),\n self.sf_dtype,\n )\n tiled_copy_s2t = tcgen05.make_s2t_copy(copy_atom_s2t, tCtSF_compact)\n thr_copy_s2t = tiled_copy_s2t.get_slice(0)\n\n # ((ATOM_V, REST_V), Rest_Tiler, MMA_MN, MMA_K, STAGE)\n tCsSF_compact_s2t_ = thr_copy_s2t.partition_S(tCsSF_compact)\n # ((ATOM_V, REST_V), Rest_Tiler, MMA_MN, MMA_K, STAGE)\n tCsSF_compact_s2t = tcgen05.get_s2t_smem_desc_tensor(\n tiled_copy_s2t, tCsSF_compact_s2t_\n )\n # ((ATOM_V, REST_V), Rest_Tiler, MMA_MN, MMA_K)\n tCtSF_compact_s2t = thr_copy_s2t.partition_D(tCtSF_compact)\n\n return tiled_copy_s2t, tCsSF_compact_s2t, tCtSF_compact_s2t\n\n def epilog_tmem_copy_and_partition(\n self,\n tidx: cutlass.Int32,\n tAcc: cute.Tensor,\n gC_mnl: cute.Tensor,\n epi_tile: cute.Tile,\n use_2cta_instrs: Union[cutlass.Boolean, bool],\n ) -> Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]:\n \"\"\"\n Make tiledCopy for tensor memory load, then use it to partition tensor memory (source) and register array (destination).\n\n :param tidx: The thread index in epilogue warp groups\n :type tidx: cutlass.Int32\n :param tAcc: The accumulator tensor to be copied and partitioned\n :type tAcc: cute.Tensor\n :param gC_mnl: The global tensor C\n :type gC_mnl: cute.Tensor\n :param epi_tile: The epilogue tiler\n :type epi_tile: cute.Tile\n :param use_2cta_instrs: Whether use_2cta_instrs is enabled\n :type use_2cta_instrs: bool\n\n :return: A tuple containing (tiled_copy_t2r, tTR_tAcc, tTR_rAcc) where:\n - tiled_copy_t2r: The tiled copy operation for tmem to register copy(t2r)\n - tTR_tAcc: The partitioned accumulator tensor\n - tTR_rAcc: The accumulated tensor in register used to hold t2r results\n :rtype: Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]\n \"\"\"\n # Make tiledCopy for tensor memory load\n copy_atom_t2r = sm100_utils.get_tmem_load_op(\n self.cta_tile_shape_mnk,\n self.c_layout,\n self.c_dtype,\n self.acc_dtype,\n epi_tile,\n use_2cta_instrs,\n )\n # (EPI_TILE_M, EPI_TILE_N, EPI_M, EPI_N, STAGE)\n tAcc_epi = cute.flat_divide(\n tAcc[((None, None), 0, 0, None)],\n epi_tile,\n )\n # (EPI_TILE_M, EPI_TILE_N)\n tiled_copy_t2r = tcgen05.make_tmem_copy(\n copy_atom_t2r, tAcc_epi[(None, None, 0, 0, 0)]\n )\n\n thr_copy_t2r = tiled_copy_t2r.get_slice(tidx)\n # (T2R, T2R_M, T2R_N, EPI_M, EPI_M, STAGE)\n tTR_tAcc = thr_copy_t2r.partition_S(tAcc_epi)\n\n # (EPI_TILE_M, EPI_TILE_N, EPI_M, EPI_N, RestM, RestN, RestL)\n gC_mnl_epi = cute.flat_divide(\n gC_mnl[((None, None), 0, 0, None, None, None)], epi_tile\n )\n # (T2R, T2R_M, T2R_N, EPI_M, EPI_N, RestM, RestN, RestL)\n tTR_gC = thr_copy_t2r.partition_D(gC_mnl_epi)\n # (T2R, T2R_M, T2R_N)\n tTR_rAcc = cute.make_fragment(\n tTR_gC[(None, None, None, 0, 0, 0, 0, 0)].shape, self.acc_dtype\n )\n return tiled_copy_t2r, tTR_tAcc, tTR_rAcc\n\n def epilog_smem_copy_and_partition(\n self,\n tiled_copy_t2r: cute.TiledCopy,\n tTR_rC: cute.Tensor,\n tidx: cutlass.Int32,\n sC: cute.Tensor,\n ) -> Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]:\n \"\"\"\n Make tiledCopy for shared memory store, then use it to partition register array (source) and shared memory (destination).\n\n :param tiled_copy_t2r: The tiled copy operation for tmem to register copy(t2r)\n :type tiled_copy_t2r: cute.TiledCopy\n :param tTR_rC: The partitioned accumulator tensor\n :type tTR_rC: cute.Tensor\n :param tidx: The thread index in epilogue warp groups\n :type tidx: cutlass.Int32\n :param sC: The shared memory tensor to be copied and partitioned\n :type sC: cute.Tensor\n :type sepi: cute.Tensor\n\n :return: A tuple containing (tiled_copy_r2s, tRS_rC, tRS_sC) where:\n - tiled_copy_r2s: The tiled copy operation for register to smem copy(r2s)\n - tRS_rC: The partitioned tensor C (register source)\n - tRS_sC: The partitioned tensor C (smem destination)\n :rtype: Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]\n \"\"\"\n copy_atom_r2s = sm100_utils.get_smem_store_op(\n self.c_layout, self.c_dtype, self.acc_dtype, tiled_copy_t2r\n )\n tiled_copy_r2s = cute.make_tiled_copy_D(copy_atom_r2s, tiled_copy_t2r)\n # (R2S, R2S_M, R2S_N, PIPE_D)\n thr_copy_r2s = tiled_copy_r2s.get_slice(tidx)\n tRS_sC = thr_copy_r2s.partition_D(sC)\n # (R2S, R2S_M, R2S_N)\n tRS_rC = tiled_copy_r2s.retile(tTR_rC)\n return tiled_copy_r2s, tRS_rC, tRS_sC\n\n def epilog_gmem_copy_and_partition(\n self,\n tidx: cutlass.Int32,\n atom: Union[cute.CopyAtom, cute.TiledCopy],\n gC_mnl: cute.Tensor,\n epi_tile: cute.Tile,\n sC: cute.Tensor,\n ) -> Tuple[cute.CopyAtom, cute.Tensor, cute.Tensor]:\n \"\"\"Make tiledCopy for global memory store, then use it to:\n partition shared memory (source) and global memory (destination) for TMA store version.\n\n :param tidx: The thread index in epilogue warp groups\n :type tidx: cutlass.Int32\n :param atom: The copy_atom_c to be used for TMA store version, or tiled_copy_t2r for none TMA store version\n :type atom: cute.CopyAtom or cute.TiledCopy\n :param gC_mnl: The global tensor C\n :type gC_mnl: cute.Tensor\n :param epi_tile: The epilogue tiler\n :type epi_tile: cute.Tile\n :param sC: The shared memory tensor to be copied and partitioned\n :type sC: cute.Tensor\n\n :return: A tuple containing (tma_atom_c, bSG_sC, bSG_gC) where:\n - tma_atom_c: The TMA copy atom\n - bSG_sC: The partitioned shared memory tensor C\n - bSG_gC: The partitioned global tensor C\n :rtype: Tuple[cute.CopyAtom, cute.Tensor, cute.Tensor]\n \"\"\"\n # (EPI_TILE_M, EPI_TILE_N, EPI_M, EPI_N, RestM, RestN, RestL)\n gC_epi = cute.flat_divide(\n gC_mnl[((None, None), 0, 0, None, None, None)], epi_tile\n )\n\n tma_atom_c = atom\n sC_for_tma_partition = cute.group_modes(sC, 0, 2)\n gC_for_tma_partition = cute.group_modes(gC_epi, 0, 2)\n # ((ATOM_V, REST_V), EPI_M, EPI_N)\n # ((ATOM_V, REST_V), EPI_M, EPI_N, RestM, RestN, RestL)\n bSG_sC, bSG_gC = cpasync.tma_partition(\n tma_atom_c,\n 0,\n cute.make_layout(1),\n sC_for_tma_partition,\n gC_for_tma_partition,\n )\n return tma_atom_c, bSG_sC, bSG_gC\n\n @staticmethod\n def _compute_stages(\n tiled_mma: cute.TiledMma,\n mma_tiler_mnk: Tuple[int, int, int],\n a_dtype: Type[cutlass.Numeric],\n a_major_mode: tcgen05.OperandMajorMode,\n b_dtype: Type[cutlass.Numeric],\n b_major_mode: tcgen05.OperandMajorMode,\n epi_tile: cute.Tile,\n c_dtype: Type[cutlass.Numeric],\n c_layout: utils.LayoutEnum,\n sf_dtype: Type[cutlass.Numeric],\n sf_vec_size: int,\n smem_capacity: int,\n occupancy: int,\n ) -> Tuple[int, int, int]:\n \"\"\"Computes the number of stages for A/B/C operands based on heuristics.\n\n :param tiled_mma: The tiled MMA object defining the core computation.\n :type tiled_mma: cute.TiledMma\n :param mma_tiler_mnk: The shape (M, N, K) of the MMA tiler.\n :type mma_tiler_mnk: tuple[int, int, int]\n :param a_dtype: Data type of operand A.\n :type a_dtype: type[cutlass.Numeric]\n :param a_major_mode: Major mode of operand A.\n :type a_major_mode: tcgen05.OperandMajorMode\n :param b_dtype: Data type of operand B.\n :type b_dtype: type[cutlass.Numeric]\n :param b_major_mode: Major mode of operand B.\n :type b_major_mode: tcgen05.OperandMajorMode\n :param epi_tile: The epilogue tile shape.\n :type epi_tile: cute.Tile\n :param c_dtype: Data type of operand C (output).\n :type c_dtype: type[cutlass.Numeric]\n :param c_layout: Layout enum of operand C.\n :type c_layout: utils.LayoutEnum\n :param sf_dtype: Data type of Scale factor.\n :type sf_dtype: type[cutlass.Numeric]\n :param sf_vec_size: Scale factor vector size.\n :type sf_vec_size: int\n :param smem_capacity: Total available shared memory capacity in bytes.\n :type smem_capacity: int\n :param occupancy: Target number of CTAs per SM (occupancy).\n :type occupancy: int\n\n :return: A tuple containing the computed number of stages for:\n (ACC stages, A/B operand stages, C stages)\n :rtype: tuple[int, int, int]\n \"\"\"\n # ACC stages\n num_acc_stage = 1 if mma_tiler_mnk[1] == 256 else 2\n\n # Default C stages\n num_c_stage = 2\n\n # Calculate smem layout and size for one stage of A, B, SFA, SFB and C\n a_smem_layout_stage_one = sm100_utils.make_smem_layout_a(\n tiled_mma,\n mma_tiler_mnk,\n a_dtype,\n 1, # a tmp 1 stage is provided\n )\n b_smem_layout_staged_one = sm100_utils.make_smem_layout_b(\n tiled_mma,\n mma_tiler_mnk,\n b_dtype,\n 1, # a tmp 1 stage is provided\n )\n sfa_smem_layout_staged_one = blockscaled_utils.make_smem_layout_sfa(\n tiled_mma,\n mma_tiler_mnk,\n sf_vec_size,\n 1, # a tmp 1 stage is provided\n )\n sfb_smem_layout_staged_one = blockscaled_utils.make_smem_layout_sfb(\n tiled_mma,\n mma_tiler_mnk,\n sf_vec_size,\n 1, # a tmp 1 stage is provided\n )\n\n c_smem_layout_staged_one = sm100_utils.make_smem_layout_epi(\n c_dtype,\n c_layout,\n epi_tile,\n 1,\n )\n\n ab_bytes_per_stage = (\n cute.size_in_bytes(a_dtype, a_smem_layout_stage_one)\n + cute.size_in_bytes(b_dtype, b_smem_layout_staged_one)\n + cute.size_in_bytes(sf_dtype, sfa_smem_layout_staged_one)\n + cute.size_in_bytes(sf_dtype, sfb_smem_layout_staged_one)\n )\n mbar_helpers_bytes = 1024\n c_bytes_per_stage = cute.size_in_bytes(c_dtype, c_smem_layout_staged_one)\n c_bytes = c_bytes_per_stage * num_c_stage\n\n # Calculate A/B/SFA/SFB stages:\n # Start with total smem per CTA (capacity / occupancy)\n # Subtract reserved bytes and initial C stages bytes\n # Divide remaining by bytes needed per A/B/SFA/SFB stage\n num_ab_stage = (\n smem_capacity // occupancy - (mbar_helpers_bytes + c_bytes)\n ) // ab_bytes_per_stage\n\n # Refine epilogue stages:\n # Calculate remaining smem after allocating for A/B/SFA/SFB stages and reserved bytes\n # Add remaining unused smem to epilogue\n num_c_stage += (\n smem_capacity\n - occupancy * ab_bytes_per_stage * num_ab_stage\n - occupancy * (mbar_helpers_bytes + c_bytes)\n ) // (occupancy * c_bytes_per_stage)\n\n return num_acc_stage, num_ab_stage, num_c_stage\n\n @staticmethod\n def _compute_grid(\n masked_m_tensor: cute.Tensor,\n dst_signals: Optional[cute.Pointer],\n c: cute.Tensor,\n cta_tile_shape_mnk: Tuple[int, int, int],\n cluster_shape_mn: Tuple[int, int],\n max_active_clusters: cutlass.Constexpr,\n ) -> Tuple[MaskedSchedulerParams, Tuple[int, int, int]]:\n \"\"\"Use persistent tile scheduler to compute the grid size for the output tensor C.\n\n :param c: The output tensor C\n :type c: cute.Tensor\n :param cta_tile_shape_mnk: The shape (M, N, K) of the CTA tile.\n :type cta_tile_shape_mnk: tuple[int, int, int]\n :param cluster_shape_mn: Shape of each cluster in M, N dimensions.\n :type cluster_shape_mn: tuple[int, int]\n :param max_active_clusters: Maximum number of active clusters.\n :type max_active_clusters: cutlass.Constexpr\n\n :return: A tuple containing:\n - tile_sched_params: Parameters for the persistent tile scheduler.\n - grid: Grid shape for kernel launch.\n :rtype: Tuple[MaskedSchedulerParams, tuple[int, int, int]]\n \"\"\"\n c_tiler = cute.slice_(cta_tile_shape_mnk, (None, None, 0))\n cluster_shape_mnl = (*cluster_shape_mn, 1)\n\n tile_sched_params = MaskedSchedulerParams(\n masked_m_tensor, dst_signals, c, c_tiler, cluster_shape_mnl\n )\n grid = MaskedScheduler.get_grid_shape(tile_sched_params, max_active_clusters)\n\n return tile_sched_params, grid\n\n @staticmethod\n def is_valid_dtypes_and_scale_factor_vec_size(\n ab_dtype: Type[cutlass.Numeric],\n sf_dtype: Type[cutlass.Numeric],\n sf_vec_size: int,\n c_dtype: Type[cutlass.Numeric],\n ) -> bool:\n \"\"\"\n Check if the dtypes and sf_vec_size are valid combinations\n\n :param ab_dtype: The data type of the A and B operands\n :type ab_dtype: Type[cutlass.Numeric]\n :param sf_dtype: The data type of the scale factor\n :type sf_dtype: Type[cutlass.Numeric]\n :param sf_vec_size: The vector size of the scale factor\n :type sf_vec_size: int\n :param c_dtype: The data type of the output tensor\n :type c_dtype: Type[cutlass.Numeric]\n\n :return: True if the dtypes and sf_vec_size are valid, False otherwise\n :rtype: bool\n \"\"\"\n is_valid = True\n\n # Check valid ab_dtype\n if ab_dtype not in {\n cutlass.Float4E2M1FN,\n cutlass.Float8E5M2,\n cutlass.Float8E4M3FN,\n }:\n is_valid = False\n\n # Check valid sf_vec_size\n if sf_vec_size not in {16, 32}:\n is_valid = False\n\n # Check valid sf_dtype\n if sf_dtype not in {cutlass.Float8E8M0FNU, cutlass.Float8E4M3FN}:\n is_valid = False\n\n # Check valid sf_dtype and sf_vec_size combinations\n if sf_dtype == cutlass.Float8E4M3FN and sf_vec_size == 32:\n is_valid = False\n if ab_dtype in {cutlass.Float8E5M2, cutlass.Float8E4M3FN} and sf_vec_size == 16:\n is_valid = False\n\n # Check valid c_dtype\n if c_dtype not in {\n cutlass.Float32,\n cutlass.Float16,\n cutlass.BFloat16,\n cutlass.Float8E5M2,\n cutlass.Float8E4M3FN,\n }:\n is_valid = False\n\n return is_valid\n\n @staticmethod\n def is_valid_layouts(\n ab_dtype: Type[cutlass.Numeric],\n c_dtype: Type[cutlass.Numeric],\n a_major: str,\n b_major: str,\n c_major: str,\n ) -> bool:\n \"\"\"\n Check if the dtypes and sf_vec_size are valid combinations\n\n :param ab_dtype: The data type of the A and B operands\n :type ab_dtype: Type[cutlass.Numeric]\n :param c_dtype: The data type of the output tensor\n :type c_dtype: Type[cutlass.Numeric]\n :param a_major: The major dimension of the A tensor\n :type a_major: str\n :param b_major: The major dimension of the B tensor\n :type b_major: str\n :param c_major: The major dimension of the C tensor\n :type c_major: str\n\n :return: True if the layouts are valid, False otherwise\n :rtype: bool\n \"\"\"\n is_valid = True\n\n if ab_dtype is cutlass.Float4E2M1FN and not (a_major == \"k\" and b_major == \"k\"):\n is_valid = False\n return is_valid\n\n @staticmethod\n def is_valid_mma_tiler_and_cluster_shape(\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n ) -> bool:\n \"\"\"\n Check if the mma tiler and cluster shape are valid\n\n :param mma_tiler_mn: The (M, N) shape of the MMA instruction tiler\n :type mma_tiler_mn: Tuple[int, int]\n :param cluster_shape_mn: The (ClusterM, ClusterN) shape of the CTA cluster\n :type cluster_shape_mn: Tuple[int, int]\n\n :return: True if the mma tiler and cluster shape are valid, False otherwise\n :rtype: bool\n \"\"\"\n is_valid = True\n # Skip invalid mma tile shape\n if mma_tiler_mn[0] not in [128, 256]:\n is_valid = False\n if mma_tiler_mn[1] not in [128, 256]:\n is_valid = False\n # Skip illegal cluster shape\n if cluster_shape_mn[0] % (2 if mma_tiler_mn[0] == 256 else 1) != 0:\n is_valid = False\n # Skip invalid cluster shape\n is_power_of_2 = lambda x: x > 0 and (x & (x - 1)) == 0\n if (\n cluster_shape_mn[0] * cluster_shape_mn[1] > 16\n or cluster_shape_mn[0] <= 0\n or cluster_shape_mn[1] <= 0\n # Special cluster shape check for scale factor multicasts.\n # Due to limited size of scale factors, we can't multicast among more than 4 CTAs.\n or cluster_shape_mn[0] > 4\n or cluster_shape_mn[1] > 4\n or not is_power_of_2(cluster_shape_mn[0])\n or not is_power_of_2(cluster_shape_mn[1])\n ):\n is_valid = False\n return is_valid\n\n @staticmethod\n def is_valid_tensor_alignment(\n m: int,\n n: int,\n k: int,\n l: int,\n ab_dtype: Type[cutlass.Numeric],\n c_dtype: Type[cutlass.Numeric],\n a_major: str,\n b_major: str,\n c_major: str,\n ) -> bool:\n \"\"\"\n Check if the tensor alignment is valid\n\n :param m: The number of rows in the A tensor\n :type m: int\n :param n: The number of columns in the B tensor\n :type n: int\n :param k: The number of columns in the A tensor\n :type k: int\n :param l: The number of columns in the C tensor\n :type l: int\n :param ab_dtype: The data type of the A and B operands\n :type ab_dtype: Type[cutlass.Numeric]\n :param c_dtype: The data type of the output tensor\n :type c_dtype: Type[cutlass.Numeric]\n :param a_major: The major axis of the A tensor\n :type a_major: str\n :param b_major: The major axis of the B tensor\n :type b_major: str\n :param c_major: The major axis of the C tensor\n :type c_major: str\n\n :return: True if the problem shape is valid, False otherwise\n :rtype: bool\n \"\"\"\n is_valid = True\n\n def check_contigous_16B_alignment(dtype, is_mode0_major, tensor_shape):\n major_mode_idx = 0 if is_mode0_major else 1\n num_major_elements = tensor_shape[major_mode_idx]\n num_contiguous_elements = 16 * 8 // dtype.width\n return num_major_elements % num_contiguous_elements == 0\n\n if (\n not check_contigous_16B_alignment(ab_dtype, a_major == \"m\", (m, k, l))\n or not check_contigous_16B_alignment(ab_dtype, b_major == \"n\", (n, k, l))\n or not check_contigous_16B_alignment(c_dtype, c_major == \"m\", (m, n, l))\n ):\n is_valid = False\n return is_valid\n\n @staticmethod\n def can_implement(\n ab_dtype: Type[cutlass.Numeric],\n sf_dtype: Type[cutlass.Numeric],\n sf_vec_size: int,\n c_dtype: Type[cutlass.Numeric],\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n m: int,\n n: int,\n k: int,\n l: int,\n a_major: str,\n b_major: str,\n c_major: str,\n ) -> bool:\n \"\"\"\n Check if the gemm can be implemented\n\n :param ab_dtype: The data type of the A and B operands\n :type ab_dtype: Type[cutlass.Numeric]\n :param sf_dtype: The data type of the scale factor tensor\n :type sf_dtype: Type[cutlass.Numeric]\n :param sf_vec_size: The vector size\n :type sf_vec_size: int\n :param c_dtype: The data type of the output tensor\n :type c_dtype: Type[cutlass.Numeric]\n :param mma_tiler_mn: The (M, N) shape of the MMA instruction tiler\n :type mma_tiler_mn: Tuple[int, int]\n :param cluster_shape_mn: The (ClusterM, ClusterN) shape of the CTA cluster\n :type cluster_shape_mn: Tuple[int, int]\n :param m: The number of rows in the A tensor\n :type m: int\n :param n: The number of columns in the B tensor\n :type n: int\n :param k: The number of columns in the A tensor\n :type k: int\n :param l: The number of columns in the C tensor\n :type l: int\n :param a_major: The major axis of the A tensor\n :type a_major: str\n :param b_major: The major axis of the B tensor\n :type b_major: str\n :param c_major: The major axis of the C tensor\n :type c_major: str\n\n :return: True if the gemm can be implemented, False otherwise\n :rtype: bool\n \"\"\"\n can_implement = True\n # Skip unsupported types\n if not Sm100BlockScaledPersistentDenseGemmKernel.is_valid_dtypes_and_scale_factor_vec_size(\n ab_dtype, sf_dtype, sf_vec_size, c_dtype\n ):\n can_implement = False\n # Skip unsupported layouts\n if not Sm100BlockScaledPersistentDenseGemmKernel.is_valid_layouts(\n ab_dtype, c_dtype, a_major, b_major, c_major\n ):\n can_implement = False\n # Skip invalid mma tile shape and cluster shape\n if not Sm100BlockScaledPersistentDenseGemmKernel.is_valid_mma_tiler_and_cluster_shape(\n mma_tiler_mn, cluster_shape_mn\n ):\n can_implement = False\n # Skip illegal problem shape for load/store alignment\n if not Sm100BlockScaledPersistentDenseGemmKernel.is_valid_tensor_alignment(\n m, n, k, l, ab_dtype, c_dtype, a_major, b_major, c_major\n ):\n can_implement = False\n return can_implement\n\n\n@cute.jit\ndef cvt_sf_MKL_to_M32x4xrm_K4xrk_L(\n sf_ref_tensor: cute.Tensor,\n sf_mma_tensor: cute.Tensor,\n):\n \"\"\"Convert scale factor tensor from MKL layout to mma specification M(32x4xrest_m)xK(4xrest_k)xL layout\"\"\"\n # sf_mma_tensor has flatten shape (32, 4, rest_m, 4, rest_k, l)\n # group to ((32, 4, rest_m), (4, rest_k), l)\n sf_mma_tensor = cute.group_modes(sf_mma_tensor, 0, 3)\n sf_mma_tensor = cute.group_modes(sf_mma_tensor, 1, 3)\n for i in cutlass.range(cute.size(sf_ref_tensor)):\n mkl_coord = sf_ref_tensor.layout.get_hier_coord(i)\n sf_mma_tensor[mkl_coord] = sf_ref_tensor[mkl_coord]\n\n\n@cute.jit\ndef cvt_sf_MKL_to_M32x4xrm_K4xrk_L_mma_spec(\n sf_mma_tensor: cute.Tensor,\n):\n \"\"\"Convert scale factor tensor from MKL layout to mma specification M(32x4xrest_m)xK(4xrest_k)xL layout\"\"\"\n # sf_mma_tensor has flatten shape (32, 4, rest_m, 4, rest_k, l)\n # group to ((32, 4, rest_m), (4, rest_k), l)\n sf_mma_tensor = cute.group_modes(sf_mma_tensor, 0, 3)\n sf_mma_tensor = cute.group_modes(sf_mma_tensor, 1, 3)\n\n\n# Create scale factor tensor SFA/SFB\ndef create_scale_factor_tensor(l, mn, k, sf_vec_size, dtype, device):\n def ceil_div(a, b):\n return (a + b - 1) // b\n\n sf_k = ceil_div(k, sf_vec_size)\n ref_shape = (l, mn, sf_k)\n\n atom_m = (32, 4)\n atom_k = 4\n mma_shape = (\n l,\n ceil_div(mn, atom_m[0] * atom_m[1]),\n ceil_div(sf_k, atom_k),\n atom_m[0],\n atom_m[1],\n atom_k,\n )\n\n ref_permute_order = (1, 2, 0)\n mma_permute_order = (3, 4, 1, 5, 2, 0)\n\n # Create f32 ref torch tensor\n ref_f32_torch_tensor_cpu = cutlass_torch.create_and_permute_torch_tensor(\n ref_shape,\n torch.float32,\n permute_order=ref_permute_order,\n init_type=cutlass_torch.TensorInitType.RANDOM,\n init_config=cutlass_torch.RandomInitConfig(\n min_val=1,\n max_val=3,\n ),\n )\n\n # Create f32 cute torch tensor\n cute_f32_torch_tensor_cpu = cutlass_torch.create_and_permute_torch_tensor(\n mma_shape,\n torch.float32,\n permute_order=mma_permute_order,\n init_type=cutlass_torch.TensorInitType.RANDOM,\n init_config=cutlass_torch.RandomInitConfig(\n min_val=0,\n max_val=1,\n ),\n )\n\n # convert ref f32 tensor to cute f32 tensor\n cvt_sf_MKL_to_M32x4xrm_K4xrk_L(\n from_dlpack(ref_f32_torch_tensor_cpu),\n from_dlpack(cute_f32_torch_tensor_cpu),\n )\n cute_f32_torch_tensor = cute_f32_torch_tensor_cpu.to(device, non_blocking=True)\n\n # reshape makes memory contiguous\n ref_f32_torch_tensor_cpu = (\n ref_f32_torch_tensor_cpu.permute(2, 0, 1)\n .unsqueeze(-1)\n .expand(l, mn, sf_k, sf_vec_size)\n .reshape(l, mn, sf_k * sf_vec_size)\n .permute(*ref_permute_order)\n )\n # prune to mkl for reference check.\n ref_f32_torch_tensor_cpu = ref_f32_torch_tensor_cpu[:, :k, :]\n ref_f32_torch_tensor = ref_f32_torch_tensor_cpu.to(device, non_blocking=True)\n\n # Create dtype cute torch tensor (cpu)\n cute_tensor, cute_torch_tensor = cutlass_torch.cute_tensor_like(\n cute_f32_torch_tensor_cpu,\n dtype,\n is_dynamic_layout=True,\n assumed_align=16,\n )\n\n # Convert f32 cute tensor to dtype cute tensor\n cute_tensor = cutlass_torch.convert_cute_tensor(\n cute_f32_torch_tensor,\n cute_tensor,\n dtype,\n is_dynamic_layout=True,\n )\n return ref_f32_torch_tensor, cute_tensor, cute_torch_tensor\n\n\nclass MaskedBatchedMatmulCuteDSL:\n def __init__(\n self,\n m: int,\n n: int,\n k: int,\n l: int,\n a_major: str,\n b_major: str,\n c_major: str,\n ab_dtype: torch.dtype,\n sf_dtype: torch.dtype,\n c_dtype: torch.dtype,\n alpha_dtype: torch.dtype,\n sf_vec_size: int,\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n sm_count: int,\n sm_version: str,\n ):\n self._m = m\n self._n = n\n self._k = k\n self._l = l\n self._a_major = a_major\n self._b_major = b_major\n self._c_major = c_major\n self._ab_dtype = ab_dtype\n self._sf_dtype = sf_dtype\n self._c_dtype = c_dtype\n self._alpha_dtype = alpha_dtype\n self._sf_vec_size = sf_vec_size\n self._mma_tiler_mn = mma_tiler_mn\n self._cluster_shape_mn = cluster_shape_mn\n\n if not Sm100BlockScaledPersistentDenseGemmKernel.can_implement(\n ab_dtype,\n sf_dtype,\n sf_vec_size,\n c_dtype,\n mma_tiler_mn,\n cluster_shape_mn,\n m,\n n,\n k,\n l,\n a_major,\n b_major,\n c_major,\n ):\n raise TypeError(\n f\"MaskedBatchedMatmulCuteDSL: Unsupported with {ab_dtype}, {sf_dtype}, {sf_vec_size}, {c_dtype}, {mma_tiler_mn}, {cluster_shape_mn}, {m}, {n}, {k}, {l}, {a_major}, {b_major}, {c_major}\"\n )\n\n # Compute max active clusters on current device (cached to avoid expensive queries)\n self._max_active_clusters = min(\n get_max_active_clusters(\n self._cluster_shape_mn[0] * self._cluster_shape_mn[1]\n ),\n sm_count,\n )\n self._sm_version = sm_version\n\n @cute.jit\n def __call__(\n self,\n a_ptr: cute.Pointer,\n b_ptr: cute.Pointer,\n sfa_ptr: cute.Pointer,\n sfb_ptr: cute.Pointer,\n c_ptr: cute.Pointer,\n masked_m_ptr: cute.Pointer,\n dst_signals_ptr: Optional[cute.Pointer],\n alpha_ptr: cute.Pointer,\n current_stream: cuda.CUstream,\n ):\n a_tensor = cute.make_tensor(\n a_ptr,\n layout=cute.make_ordered_layout(\n (self._m, self._k, self._l),\n order=(0, 1, 2) if self._a_major == \"m\" else (1, 0, 2),\n ),\n )\n b_tensor = cute.make_tensor(\n b_ptr,\n layout=cute.make_ordered_layout(\n (self._n, self._k, self._l),\n order=(0, 1, 2) if self._b_major == \"n\" else (1, 0, 2),\n ),\n )\n c_tensor = cute.make_tensor(\n c_ptr,\n layout=cute.make_ordered_layout(\n (self._m, self._n, self._l),\n order=(0, 1, 2) if self._c_major == \"m\" else (1, 0, 2),\n ),\n )\n\n # calculate sf_tensor shape and order\n def ceil_div(a, b):\n return (a + b - 1) // b\n\n sf_k = ceil_div(self._k, self._sf_vec_size)\n\n atom_m = (32, 4)\n atom_k = 4\n mma_shape_a = (\n self._l,\n ceil_div(self._m, atom_m[0] * atom_m[1]),\n ceil_div(sf_k, atom_k),\n atom_m[0],\n atom_m[1],\n atom_k,\n )\n mma_shape_b = (\n self._l,\n ceil_div(self._n, atom_m[0] * atom_m[1]),\n ceil_div(sf_k, atom_k),\n atom_m[0],\n atom_m[1],\n atom_k,\n )\n mma_permute_order = (3, 4, 1, 5, 2, 0)\n\n sfa_tensor = cute.make_tensor(\n sfa_ptr,\n layout=cute.make_ordered_layout(\n mma_shape_a,\n order=mma_permute_order,\n ),\n )\n sfb_tensor = cute.make_tensor(\n sfb_ptr,\n layout=cute.make_ordered_layout(\n mma_shape_b,\n order=mma_permute_order,\n ),\n )\n cvt_sf_MKL_to_M32x4xrm_K4xrk_L_mma_spec(sfa_tensor)\n cvt_sf_MKL_to_M32x4xrm_K4xrk_L_mma_spec(sfb_tensor)\n\n masked_m_tensor = cute.make_tensor(\n masked_m_ptr,\n layout=cute.make_ordered_layout((self._l,), order=(0,)),\n )\n\n # Use const_expr for compile-time conditional\n alpha_tensor = (\n cute.make_tensor(\n alpha_ptr,\n layout=cute.make_ordered_layout((self._l,), order=(0,)),\n )\n if cutlass.const_expr(alpha_ptr is not None)\n else None\n )\n\n Sm100BlockScaledPersistentDenseGemmKernel(\n sf_vec_size=self._sf_vec_size,\n mma_tiler_mn=self._mma_tiler_mn,\n cluster_shape_mn=self._cluster_shape_mn,\n sm_version=self._sm_version,\n )(\n a_tensor,\n b_tensor,\n sfa_tensor,\n sfb_tensor,\n c_tensor,\n masked_m_tensor,\n dst_signals_ptr,\n alpha_tensor,\n self._max_active_clusters,\n current_stream,\n )\n\n\n@functools.cache\ndef get_cute_dsl_compiled_masked_gemm_kernel(\n m: int,\n n: int,\n k: int,\n l: int,\n a_major: str,\n b_major: str,\n c_major: str,\n ab_dtype: Type[cutlass.Numeric],\n sf_dtype: Type[cutlass.Numeric],\n c_dtype: Type[cutlass.Numeric],\n alpha_dtype: Optional[Type[cutlass.Numeric]],\n sf_vec_size: int,\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n sm_count: int,\n sm_version: str,\n enable_dst_signals: bool,\n) -> Callable:\n def get_cute_pointers(\n input_tensors: Optional[List[torch.tensor]],\n ) -> List[cute.Pointer]:\n if input_tensors is None:\n (\n a_data_ptr,\n b_data_ptr,\n sfa_data_ptr,\n sfb_data_ptr,\n c_data_ptr,\n masked_m_data_ptr,\n dst_signals_data_ptr,\n alpha_data_ptr,\n ) = [16 for _ in range(8)]\n\n if not enable_dst_signals:\n dst_signals_data_ptr = None\n\n else:\n (\n a_tensor_gpu,\n b_tensor_gpu,\n sfa_tensor_gpu,\n sfb_tensor_gpu,\n c_tensor_gpu,\n masked_m_tensor_gpu,\n dst_signals_tensor_gpu,\n alpha_tensor_gpu,\n ) = input_tensors\n\n assert enable_dst_signals == (dst_signals_tensor_gpu is not None)\n\n (\n a_data_ptr,\n b_data_ptr,\n sfa_data_ptr,\n sfb_data_ptr,\n c_data_ptr,\n masked_m_data_ptr,\n dst_signals_data_ptr,\n alpha_data_ptr,\n ) = (\n a_tensor_gpu.data_ptr(),\n b_tensor_gpu.data_ptr(),\n sfa_tensor_gpu.data_ptr(),\n sfb_tensor_gpu.data_ptr(),\n c_tensor_gpu.data_ptr(),\n masked_m_tensor_gpu.data_ptr(),\n dst_signals_tensor_gpu.data_ptr()\n if dst_signals_tensor_gpu is not None\n else None,\n alpha_tensor_gpu.data_ptr() if alpha_tensor_gpu is not None else None,\n )\n\n a_ptr = make_ptr(\n ab_dtype,\n a_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n b_ptr = make_ptr(\n ab_dtype,\n b_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n sfa_ptr = make_ptr(\n sf_dtype,\n sfa_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n sfb_ptr = make_ptr(\n sf_dtype,\n sfb_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n c_ptr = make_ptr(\n c_dtype,\n c_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n masked_m_ptr = make_ptr(\n cutlass.Int32,\n masked_m_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n dst_signals_ptr = (\n make_ptr(\n cutlass.Uint32,\n dst_signals_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n if dst_signals_data_ptr is not None\n else None\n )\n alpha_ptr = (\n make_ptr(\n alpha_dtype,\n alpha_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n if alpha_data_ptr is not None and alpha_dtype is not None\n else None\n )\n\n return [\n a_ptr,\n b_ptr,\n sfa_ptr,\n sfb_ptr,\n c_ptr,\n masked_m_ptr,\n dst_signals_ptr,\n alpha_ptr,\n ]\n\n kernel = cute.compile(\n MaskedBatchedMatmulCuteDSL(\n m=m,\n n=n,\n k=k,\n l=l,\n a_major=a_major,\n b_major=b_major,\n c_major=c_major,\n ab_dtype=ab_dtype,\n sf_dtype=sf_dtype,\n c_dtype=c_dtype,\n alpha_dtype=alpha_dtype,\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n cluster_shape_mn=cluster_shape_mn,\n sm_count=sm_count,\n sm_version=sm_version,\n ),\n *get_cute_pointers(None),\n cutlass_torch.current_stream(),\n )\n\n def tensor_api(\n a_tensor_gpu: torch.Tensor,\n b_tensor_gpu: torch.Tensor,\n sfa_tensor_gpu: torch.Tensor,\n sfb_tensor_gpu: torch.Tensor,\n masked_m_tensor_gpu: torch.Tensor,\n dst_signals_tensor_gpu: torch.Tensor,\n c_tensor_gpu: Optional[torch.Tensor] = None,\n alpha_tensor_gpu: Optional[torch.Tensor] = None,\n ):\n if c_tensor_gpu is None:\n # fp4 gemm output is not supported\n c_tensor_gpu = torch.empty(\n (l, m, n),\n dtype=cutlass_to_torch_dtype(c_dtype),\n device=\"cuda\",\n )\n\n # fp4 or fp8 torch tensor to cute tensor\n current_stream = cutlass_torch.current_stream()\n\n nonlocal kernel\n kernel(\n *get_cute_pointers(\n [\n a_tensor_gpu,\n b_tensor_gpu,\n sfa_tensor_gpu,\n sfb_tensor_gpu,\n c_tensor_gpu,\n masked_m_tensor_gpu,\n dst_signals_tensor_gpu,\n alpha_tensor_gpu,\n ]\n ),\n current_stream,\n )\n\n return c_tensor_gpu\n\n return tensor_api\n\n\n@flashinfer_api\ndef grouped_gemm_nt_masked(\n lhs: Tuple[torch.Tensor, torch.Tensor],\n rhs: Tuple[torch.Tensor, torch.Tensor],\n out: torch.Tensor,\n masked_m: torch.Tensor,\n *,\n ab_dtype: str,\n sf_dtype: str,\n c_dtype: str,\n sf_vec_size: int,\n dst_signals: Optional[torch.Tensor] = None,\n sm_count: Optional[int] = None,\n **kwargs,\n):\n \"\"\"\n Executes a masked, batched matrix multiplication (GEMM) with scale factors and optional alpha scaling at output.\n\n Args:\n lhs (Tuple[torch.Tensor, torch.Tensor]): Tuple containing the left-hand side input tensor (A) and its scale factor tensor (SFA).\n - A should be in (m, k, l) order, but physically (l, m, k). For fp4 tensor with 8-bit storage, we expect the shape to be (m, k/2, l).\n - SFA should be in (m32, m4, rm, k4, rk, l) order, but physically (l, rm, rk, m32, m4, k4)\n rhs (Tuple[torch.Tensor, torch.Tensor]): Tuple containing the right-hand side input tensor (B) and its scale factor tensor (SFB).\n - B should be in (n, k, l) order, but physically (l, n, k). For fp4 tensor with 8-bit storage, we expect the shape to be (n, k/2, l).\n - SFB should be in (n32, n4, rn, k4, rk, l) order, but physically (l, rn, rk, n32, n4, k4)\n out (torch.Tensor): Output tensor to store the result, with shape (l, m, n).\n masked_m (torch.Tensor): 1D tensor of shape (l,) specifying the valid row count for each batch (used for masking).\n ab_dtype (str): Data type for A and B matrices. Supported: \"float4_e2m1fn\", \"float8_e4m3fn\", \"float8_e5m2\".\n sf_dtype (str): Data type for scale factors. Supported: \"float8_e8m0fnu\", \"float8_e4m3fn\".\n c_dtype (str): Data type for output matrix C. Supported: \"float16\", \"bfloat16\", \"float32\", \"float8_e4m3fn\", \"float8_e5m2\".\n sf_vec_size (int): Vector size for scale factors. Typically 16 or 32.\n sm_count (int, optional): Number of SMs to use. Default: max available SMs under the CTA configuration.\n mma_tiler_mn (Tuple[int, int], optional): Shape of the MMA tiler (M, N). Default: (128, 128).\n cluster_shape_mn (Tuple[int, int], optional): Shape of the CTA cluster (ClusterM, ClusterN). Default: (1, 1).\n alpha_dtype (str, optional): Data type for alpha scaling factors.\n alpha (torch.Tensor, optional): Optional 1D tensor of shape (l,) containing per-batch scaling factors. Perform per-batch scaling out = alpha * out.\n\n Notes:\n - Legends of the input tensors:\n * `l` is the batch size, `m/n` is the number of rows, and `k` is the number of columns.\n * `m/n32`, `m/n4`, `k4` are constant values 32, 4, 4 respectively.\n * `m32 * m4 * rm` should be same as `M`, which is `m` padded up to the nearest multiple of 128.\n * `n32 * n4 * rn` should be same as `N`, which is `n` padded up to the nearest multiple of 128.\n * `k4 * rk` should be same as `K`, which is `k / sf_vec_size` padded up to the nearest multiple of 4.\n - The function applies masking per batch using masked_m.\n - If alpha is provided, each batch output is multiplied by its corresponding alpha value. out = alpha * (A @ B).\n - The result is written to c_tensor.\n \"\"\"\n\n a_torch, sfa_torch = lhs\n b_torch, sfb_torch = rhs\n c_torch = out\n\n m, k, l = a_torch.shape\n n, _, _ = b_torch.shape\n\n if ab_dtype == \"float4_e2m1fn\":\n # todo(yingyi): update mnk based on a_major and b_major, and support more major.\n # Note: only support deepgemm-like shape for now\n k = k * 2\n\n mma_tiler_mn = kwargs.pop(\"mma_tiler_mn\", (128, 128))\n cluster_shape_mn = kwargs.pop(\"cluster_shape_mn\", (1, 1))\n if sm_count is None:\n sm_count = get_num_sm(a_torch.device)\n\n alpha = kwargs.pop(\"alpha\", None)\n alpha_dtype = kwargs.pop(\"alpha_dtype\", None)\n\n assert len(kwargs) == 0, f\"Unsupported kwargs: {kwargs}\"\n\n major, minor = get_compute_capability(a_torch.device)\n if major == 11 and minor == 0:\n raise ValueError(\"SM110 is not supported for cute-dsl backend.\")\n\n return get_cute_dsl_compiled_masked_gemm_kernel(\n m=m,\n n=n,\n k=k,\n l=l,\n a_major=\"k\",\n b_major=\"k\",\n c_major=\"n\",\n ab_dtype=get_cutlass_dtype(ab_dtype),\n sf_dtype=get_cutlass_dtype(sf_dtype),\n c_dtype=get_cutlass_dtype(c_dtype),\n alpha_dtype=None if alpha is None else get_cutlass_dtype(alpha_dtype),\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n cluster_shape_mn=cluster_shape_mn,\n sm_count=sm_count,\n sm_version=f\"sm_{major}{minor}\",\n enable_dst_signals=dst_signals is not None,\n )(\n a_tensor_gpu=a_torch,\n b_tensor_gpu=b_torch,\n sfa_tensor_gpu=sfa_torch,\n sfb_tensor_gpu=sfb_torch,\n c_tensor_gpu=c_torch,\n masked_m_tensor_gpu=masked_m,\n dst_signals_tensor_gpu=dst_signals,\n alpha_tensor_gpu=alpha,\n )\n"},"diff":{"kind":"string","value":"--- flashinfer/gemm/kernels/grouped_gemm_masked_blackwell.py\n+++ flashinfer/gemm/kernels/grouped_gemm_masked_blackwell.py\n@@ -61,6 +61,7 @@\n get_cutlass_dtype,\n cutlass_to_torch_dtype,\n get_num_sm,\n+ get_max_active_clusters,\n make_ptr,\n )\n from typing import Callable, List\n@@ -2621,10 +2622,9 @@\n f\"MaskedBatchedMatmulCuteDSL: Unsupported with {ab_dtype}, {sf_dtype}, {sf_vec_size}, {c_dtype}, {mma_tiler_mn}, {cluster_shape_mn}, {m}, {n}, {k}, {l}, {a_major}, {b_major}, {c_major}\"\n )\n \n- # Compute max active clusters on current device\n- hardware_info = cutlass.utils.HardwareInfo()\n+ # Compute max active clusters on current device (cached to avoid expensive queries)\n self._max_active_clusters = min(\n- hardware_info.get_max_active_clusters(\n+ get_max_active_clusters(\n self._cluster_shape_mn[0] * self._cluster_shape_mn[1]\n ),\n sm_count,"},"lines_added":{"kind":"number","value":3,"string":"3"},"lines_removed":{"kind":"number","value":3,"string":"3"},"files_in_commit":{"kind":"number","value":6,"string":"6"},"models_mentioned":{"kind":"list like","value":["deepseek"],"string":"[\n \"deepseek\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["BLACKWELL"],"string":"[\n \"BLACKWELL\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.53x","0.83x","1.40x","0.83x","1.35x","0.88x","1.36x","0.94x","1.35x","1.02x"],"string":"[\n \"1.53x\",\n \"0.83x\",\n \"1.40x\",\n \"0.83x\",\n \"1.35x\",\n \"0.88x\",\n \"1.36x\",\n \"0.94x\",\n \"1.35x\",\n \"1.02x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/kernels/grouped_gemm_masked_blackwell.py).\n\nGoal: feat: cuteDSL fp4 moe for better DSR1 performance.\nTarget hardware: BLACKWELL\nTarget models: deepseek\n\nCurrent file:\n```python\n# Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.\n# SPDX-License-Identifier: BSD-3-Clause\n\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are met:\n\n# 1. Redistributions of source code must retain the above copyright notice, this\n# list of conditions and the following disclaimer.\n\n# 2. Redistributions in binary form must reproduce the above copyright notice,\n# this list of conditions and the following disclaimer in the documentation\n# and/or other materials provided with the distribution.\n\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nfrom typing import Optional, Tuple, Type, Union\n\nimport cuda.bindings.driver as cuda\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.pipeline as pipeline\nimport cutlass.torch as cutlass_torch\nimport cutlass.utils as utils\nimport cutlass.utils.blackwell_helpers as sm100_utils\nimport cutlass.utils.blockscaled_layout as blockscaled_utils\nimport torch\nimport functools\nfrom cutlass._mlir import ir\nfrom cutlass.cute.nvgpu import cpasync, tcgen05\nfrom cutlass.cute.runtime import from_dlpack\n\nfrom cutlass.cutlass_dsl import (\n Int32,\n Int64,\n Uint8,\n Uint64,\n T,\n Integer,\n dsl_user_op,\n extract_mlir_values,\n new_from_mlir_values,\n)\nfrom cutlass._mlir.dialects import llvm\nfrom flashinfer.utils import get_compute_capability\nfrom flashinfer.api_logging import flashinfer_api\nfrom cutlass.utils.static_persistent_tile_scheduler import WorkTileInfo\nfrom flashinfer.cute_dsl.utils import (\n get_cutlass_dtype,\n cutlass_to_torch_dtype,\n get_num_sm,\n make_ptr,\n)\nfrom typing import Callable, List\n\n\nsizeof_i32 = 4\n\n\n@dsl_user_op\ndef with_byte(obj: Uint64, index: Int32, value: Uint8, *, loc=None, ip=None) -> Uint64:\n obj &= ~(0xFF << (index * 8))\n obj |= value << (index * 8)\n assert isinstance(obj, Uint64), f\"{obj=}\"\n return obj\n\n\n@dsl_user_op\ndef read_byte(obj: Uint64, index: Int32, *, loc=None, ip=None) -> Uint8:\n return ((obj >> (index * 8)) & 0xFF).to(Uint8)\n\n\n@dsl_user_op\ndef atomic_add_release_global(addr: Int64, value: Int32, *, loc=None, ip=None) -> Int32:\n return Int32(\n llvm.inline_asm(\n T.i32(),\n [\n addr.ir_value(loc=loc, ip=ip),\n Int32(value).ir_value(loc=loc, ip=ip),\n ],\n \"atom.add.release.gpu.global.s32 $0, [$1], $2;\",\n \"=r,l,r\",\n has_side_effects=True,\n is_align_stack=False,\n asm_dialect=llvm.AsmDialect.AD_ATT,\n )\n )\n\n\nclass MaskedSchedulerParams:\n def __init__(\n self,\n masked_m: cute.Tensor,\n dst_signals: Optional[cute.Pointer],\n c: cute.Tensor,\n c_tiler: Tuple[int, int],\n cluster_shape_mnk: cute.Shape,\n *,\n loc=None,\n ip=None,\n ):\n if cluster_shape_mnk[2] != 1:\n raise ValueError(f\"unsupported cluster_shape_k {cluster_shape_mnk[2]}\")\n\n gc = cute.zipped_divide(c, tiler=c_tiler)\n problem_shape_ntile_mnl = gc[(0, (None, None, None))].shape\n self.masked_m = masked_m\n self.dst_signals = dst_signals\n self.c = c\n self.c_tiler = c_tiler\n self.problem_shape_ntile_mnl = problem_shape_ntile_mnl\n # cluster_shape_mnk is kept for reconstruction\n self._cluster_shape_mnk = cluster_shape_mnk\n self.cluster_shape_mn = cluster_shape_mnk[:2]\n self._loc = loc\n\n self.problem_layout_ncluster_mnl = cute.make_layout(\n cute.ceil_div(\n self.problem_shape_ntile_mnl, cluster_shape_mnk[:2], loc=loc, ip=ip\n ),\n loc=loc,\n ip=ip,\n )\n\n def __extract_mlir_values__(self):\n values, self._values_pos = [], []\n for obj in [\n self.masked_m,\n self.dst_signals,\n self.c,\n self.c_tiler,\n self._cluster_shape_mnk,\n ]:\n obj_values = extract_mlir_values(obj)\n values += obj_values\n self._values_pos.append(len(obj_values))\n return values\n\n def __new_from_mlir_values__(self, values):\n obj_list = []\n for obj, n_items in zip(\n [\n self.masked_m,\n self.dst_signals,\n self.c,\n self.c_tiler,\n self._cluster_shape_mnk,\n ],\n self._values_pos,\n strict=True,\n ):\n obj_list.append(new_from_mlir_values(obj, values[:n_items]))\n values = values[n_items:]\n return MaskedSchedulerParams(*(tuple(obj_list)), loc=self._loc)\n\n @dsl_user_op\n def get_grid_shape(\n self, max_active_clusters: Int32, *, loc=None, ip=None\n ) -> Tuple[Integer, Integer, Integer]:\n num_persistent_clusters = max_active_clusters\n\n return (*self.cluster_shape_mn, num_persistent_clusters)\n\n\nclass MaskedScheduler:\n def __init__(\n self,\n params: MaskedSchedulerParams,\n num_persistent_clusters: Int32,\n current_work_linear_idx: Int32,\n current_batch_idx: Int32,\n accum_tile_m: Int32,\n cta_id_in_cluster: cute.Coord,\n num_tiles_executed: Int32,\n ):\n self.params = params\n self.num_persistent_clusters = num_persistent_clusters\n self._current_work_linear_idx = current_work_linear_idx\n self._current_batch_idx = current_batch_idx\n self._accum_tile_m = accum_tile_m\n self.cta_id_in_cluster = cta_id_in_cluster\n self._num_tiles_executed = num_tiles_executed\n\n def __extract_mlir_values__(self) -> list[ir.Value]:\n values = extract_mlir_values(self.num_persistent_clusters)\n values.extend(extract_mlir_values(self._current_work_linear_idx))\n values.extend(extract_mlir_values(self._current_batch_idx))\n values.extend(extract_mlir_values(self._accum_tile_m))\n values.extend(extract_mlir_values(self.cta_id_in_cluster))\n values.extend(extract_mlir_values(self._num_tiles_executed))\n return values\n\n def __new_from_mlir_values__(self, values: list[ir.Value]) -> \"MaskedScheduler\":\n assert len(values) == 8\n new_num_persistent_clusters = new_from_mlir_values(\n self.num_persistent_clusters, [values[0]]\n )\n new_current_work_linear_idx = new_from_mlir_values(\n self._current_work_linear_idx, [values[1]]\n )\n new_current_batch_idx = new_from_mlir_values(\n self._current_batch_idx, [values[2]]\n )\n new_accum_tile_m = new_from_mlir_values(self._accum_tile_m, [values[3]])\n new_cta_id_in_cluster = new_from_mlir_values(\n self.cta_id_in_cluster, values[4:7]\n )\n new_num_tiles_executed = new_from_mlir_values(\n self._num_tiles_executed, [values[7]]\n )\n return MaskedScheduler(\n self.params,\n new_num_persistent_clusters,\n new_current_work_linear_idx,\n new_current_batch_idx,\n new_accum_tile_m,\n new_cta_id_in_cluster,\n new_num_tiles_executed,\n )\n\n # called by host\n @dsl_user_op\n @staticmethod\n def create(\n params: MaskedSchedulerParams,\n block_idx: Tuple[Integer, Integer, Integer],\n grid_dim: Tuple[Integer, Integer, Integer],\n *,\n loc=None,\n ip=None,\n ):\n params = params\n\n # Calculate the number of persistent clusters by dividing the total grid size\n # by the number of CTAs per cluster\n num_persistent_clusters = cute.size(grid_dim, loc=loc, ip=ip) // cute.size(\n params.cluster_shape_mn, loc=loc, ip=ip\n )\n\n bidx, bidy, bidz = block_idx\n\n # Initialize workload index equals to the cluster index in the grid\n current_work_linear_idx = Int32(bidz)\n current_batch_idx = Int32(0)\n accum_tile_m = Int32(0)\n\n # CTA id in the cluster\n cta_id_in_cluster = (\n Int32(bidx % params.cluster_shape_mn[0]),\n Int32(bidy % params.cluster_shape_mn[1]),\n Int32(0),\n )\n # Initialize number of tiles executed to zero\n num_tiles_executed = Int32(0)\n return MaskedScheduler(\n params,\n num_persistent_clusters,\n current_work_linear_idx,\n current_batch_idx,\n accum_tile_m,\n cta_id_in_cluster,\n num_tiles_executed,\n )\n\n # called by host\n @staticmethod\n def get_grid_shape(\n params: MaskedSchedulerParams,\n max_active_clusters: Int32,\n *,\n loc=None,\n ip=None,\n ) -> Tuple[Integer, Integer, Integer]:\n return params.get_grid_shape(max_active_clusters, loc=loc, ip=ip)\n\n # private method\n @cute.jit\n def _get_current_work_for_linear_idx(\n self,\n current_work_linear_idx: Int32,\n dsm_pending_packed: Optional[Uint64],\n dsm_counter: Optional[Uint8],\n num_c_stage: Optional[int] = None,\n ) -> Tuple[WorkTileInfo, Optional[Uint64]]:\n # is_valid = current_work_linear_idx < cute.size(\n # self.params.problem_layout_ncluster_mnl, loc=loc, ip=ip\n # )\n num_tiles_n = self.params.problem_shape_ntile_mnl[1]\n accum_tile_m = self._accum_tile_m\n batch_idx = self._current_batch_idx\n\n while (\n (\n accum_tile_m\n + cute.ceil_div(self.params.masked_m[batch_idx], self.params.c_tiler[0])\n )\n * num_tiles_n\n <= current_work_linear_idx\n and batch_idx < self.params.masked_m.shape[0]\n ):\n if cutlass.const_expr(\n (dsm_pending_packed is not None)\n and (self.params.dst_signals is not None)\n ):\n dsm_pending_packed = with_byte(\n dsm_pending_packed,\n index=batch_idx,\n value=dsm_counter + (num_c_stage - 1),\n )\n\n accum_tile_m += cute.ceil_div(\n self.params.masked_m[batch_idx], self.params.c_tiler[0]\n )\n batch_idx += Int32(1)\n\n self._accum_tile_m = accum_tile_m\n self._current_batch_idx = batch_idx\n\n is_valid = self._current_batch_idx < self.params.masked_m.shape[0]\n if is_valid:\n is_valid = (\n self._accum_tile_m\n + cute.ceil_div(\n self.params.masked_m[self._current_batch_idx],\n self.params.c_tiler[0],\n )\n ) * num_tiles_n > current_work_linear_idx\n\n # cur_cluster_coord = self.params.problem_layout_ncluster_mnl.get_hier_coord(\n # current_work_linear_idx, loc=loc, ip=ip\n # )\n cur_cluster_coord = (\n current_work_linear_idx // num_tiles_n - self._accum_tile_m,\n current_work_linear_idx % num_tiles_n,\n self._current_batch_idx,\n )\n\n # cur_tile_coord is a tuple of i32 values\n cur_tile_coord = tuple(\n Int32(x) * Int32(z) + Int32(y)\n for x, y, z in zip(\n cur_cluster_coord,\n self.cta_id_in_cluster,\n (*self.params.cluster_shape_mn, Int32(1)),\n strict=True,\n )\n )\n\n return WorkTileInfo(cur_tile_coord, is_valid), dsm_pending_packed\n\n @dsl_user_op\n def get_current_work(\n self,\n dsm_pending_packed: Optional[Uint64] = None,\n dsm_counter: Optional[Uint8] = None,\n num_c_stage: Optional[int] = None,\n *,\n loc=None,\n ip=None,\n ) -> Tuple[WorkTileInfo, Optional[Uint64]]:\n return self._get_current_work_for_linear_idx(\n self._current_work_linear_idx,\n dsm_pending_packed=dsm_pending_packed,\n dsm_counter=dsm_counter,\n num_c_stage=num_c_stage,\n )\n\n @dsl_user_op\n def initial_work_tile_info(self, *, loc=None, ip=None) -> WorkTileInfo:\n tile_info, _ = self.get_current_work(loc=loc, ip=ip)\n return tile_info\n\n @dsl_user_op\n def advance_to_next_work(self, *, advance_count: int = 1, loc=None, ip=None):\n self._current_work_linear_idx += Int32(advance_count) * Int32(\n self.num_persistent_clusters\n )\n self._num_tiles_executed += Int32(1)\n\n @property\n def num_tiles_executed(self) -> Int32:\n return self._num_tiles_executed\n\n\n\"\"\"\nThis example provides an experimental implementation of the SM100 batched dense blockscaled GEMM kernel, please note that the APIs and implementation details related to this kernel may change in future releases.\n\nA high-performance persistent batched dense blockscaled GEMM example for the NVIDIA Blackwell SM100 architecture\nusing CUTE DSL.\n- Matrix A is MxKxL, L is batch dimension, A can be row-major(\"K\") or column-major(\"M\") for MXF8 input type and can only be row-major(\"K\") for MXF4/NVF4 input type\n- Matrix B is NxKxL, L is batch dimension, B can be row-major(\"N\") or column-major(\"K\") for MXF8 input type and can only be row-major(\"K\") for MXF4/NVF4 input type\n- Matrix C is MxNxL, L is batch dimension, C can be row-major(\"N\") or column-major(\"M\")\n- Matrix SFA layout is filled internally according to A shape and BlockScaledBasicChunk, which has M×ceil_div(K, sf_vec_size)×L elements respectively\n- Matrix SFB layout is filled internally according to B shape and BlockScaledBasicChunk, which has N×ceil_div(K, sf_vec_size)×L elements respectively\n\nThis GEMM kernel supports the following features:\n - Utilizes Tensor Memory Access (TMA) for efficient memory operations\n - Utilizes Blackwell's tcgen05.mma for matrix multiply-accumulate (MMA) operations (including 2cta mma instructions)\n - Implements TMA multicast with cluster to reduce L2 memory traffic\n - Support persistent tile scheduling to better overlap memory load/store with mma between tiles\n - Support warp specialization to avoid explicit pipelining between mainloop load and mma\n\nThis GEMM works as follows:\n1. DMA warp: Load A and B matrices from global memory (GMEM) to shared memory (SMEM) using TMA operations.\n2. MMA warp:\n - Load scale factor A/B from shared memory (SMEM) to tensor memory (TMEM) using tcgen05.cp instruction.\n - Perform matrix multiply-accumulate (MMA) operations using tcgen05.mma instruction.\n3. EPILOGUE warp:\n - Load completed accumulator from tensor memory (TMEM) to registers (RMEM) using tcgen05.ld.\n - Type convert C matrix to output type.\n - Optionally store C matrix from registers (RMEM) to shared memory (SMEM) to global memory (GMEM) with TMA operations,\n or directly store C matrix from registers (RMEM) to global memory (GMEM) without TMA operations.\n\nSM100 tcgen05.mma.kind.block_scale instructions operate as follows:\n- Read matrix A from SMEM\n- Read matrix B from SMEM\n- Read scalefactor A from TMEM\n- Read scalefactor B from TMEM\n- Write accumulator to TMEM\nThe accumulator in TMEM must then be loaded to registers before writing back to GMEM.\n\nInput arguments to this example is shown below:\n\n.. code-block:: bash\n\n python examples/blackwell/dense_blockscaled_gemm_persistent.py \\\n --ab_dtype Float4E2M1FN --sf_dtype Float8E8M0FNU --sf_vec_size 16 \\\n --c_dtype Float16 \\\n --mma_tiler_mn 256,128 --cluster_shape_mn 2,1 \\\n --mnkl 8192,8192,1024,1\n\nTo collect performance with NCU profiler:\n\n.. code-block:: bash\n\n ncu python examples/blackwell/dense_blockscaled_gemm_persistent.py \\\n --ab_dtype Float4E2M1FN --sf_dtype Float8E8M0FNU --sf_vec_size 16 \\\n --c_dtype Float16 \\\n --mma_tiler_mn 256,128 --cluster_shape_mn 2,1 \\\n --mnkl 8192,8192,1024,1 \\\n --warmup_iterations 1 --iterations 10 --skip_ref_check\n\n\nConstraints:\n* Supported input data types: mxf8, mxf4, nvf4\n see detailed valid dtype combinations in below Sm100BlockScaledPersistentDenseGemmKernel class documentation\n* A/B tensor must have the same data type, mixed data type is not supported (e.g., mxf8 x mxf4)\n* Mma tiler M must be 128 or 256(use_2cta_instrs)\n* Mma tiler N must be 128 or 256\n* Cluster shape M/N must be positive and power of 2, total cluster size <= 16\n* Cluster shape M must be multiple of 2 if Mma tiler M is 256(use_2cta_instrs)\n* The contiguous dimension of A/B/C tensors must be at least 16 bytes aligned,\n i.e, number of elements is a multiple of 16 and 32 for Float8 and Float4, respectively.\n\"\"\"\n\n\nclass Sm100BlockScaledPersistentDenseGemmKernel:\n \"\"\"This class implements batched matrix multiplication (C = A x SFA x B x SFB) with support for various data types\n and architectural features specific to Blackwell GPUs with persistent tile scheduling and warp specialization.\n\n :param sf_vec_size: Scalefactor vector size.\n :type sf_vec_size: int\n :param mma_tiler_mn: Shape of the Matrix Multiply-Accumulate (MMA) tile (M,N)\n :type mma_tiler_mn: Tuple[int, int]\n :param cluster_shape_mn: Cluster dimensions (M,N) for parallel processing\n :type cluster_shape_mn: Tuple[int, int]\n\n :note: In current version, A and B tensor must have the same data type\n - i.e., Float8E4M3FN for A and Float8E5M2 for B is not supported\n\n :note: Supported combinations of A/B data types, SF data typs and SF vector size:\n - MXF8: A/B: Float8E5M2/Float8E4M3FN + SF: Float8E8M0FNU + sf_vec_size: 32\n - MXF4: A/B: Float4E2M1FN + SF: Float8E8M0FNU + sf_vec_size: 32\n - NVF4: A/B: Float4E2M1FN + SF: Float8E8M0FNU/Float8E4M3FN + sf_vec_size: 16\n\n :note: Supported accumulator data types:\n - Float32\n\n :note: Supported C data types:\n - Float32\n - Float16/BFloat16\n - Float8E4M3FN/Float8E5M2\n :note: Constraints:\n - MMA tiler M must be 128 or 256 (use_2cta_instrs)\n - MMA tiler N must be 128/256\n - Cluster shape M must be multiple of 2 if Mma tiler M is 256\n - Cluster shape M/N must be positive and power of 2, total cluster size <= 16\n - Also, Cluster shape M/N must be <= 4 for scale factor multicasts due to limited size of scale factors\n\n Example:\n >>> gemm = Sm100BlockScaledPersistentDenseGemmKernel(\n ... sf_vec_size=16,\n ... mma_tiler_mn=(256, 128),\n ... cluster_shape_mn=(2, 1)\n ... )\n >>> gemm(a_tensor, b_tensor, sfa_tensor, sfb_tensor, c_tensor, max_active_clusters, stream)\n \"\"\"\n\n def __init__(\n self,\n sf_vec_size: int,\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n sm_version: str,\n ):\n \"\"\"Initializes the configuration for a Blackwell dense GEMM kernel.\n\n This configuration includes several key aspects:\n\n 1. MMA Instruction Settings (tcgen05):\n - acc_dtype: Data types for MMA accumulator, always set to Float32\n - sf_vec_size: Scalefactor A/B vector size.\n - mma_tiler_mn: The (M, N) shape of the MMA instruction tiler.\n\n 2. Cluster Shape:\n - cluster_shape_mn: The (ClusterM, ClusterN) shape of the CTA cluster.\n\n :param sf_vec_size: Scalefactor vector size.\n :type sf_vec_size: int\n :param mma_tiler_mn: Tuple (M, N) shape of the MMA instruction.\n :type mma_tiler_mn: Tuple[int, int]\n :param cluster_shape_mn: Tuple (ClusterM, ClusterN) shape of the cluster.\n :type cluster_shape_mn: Tuple[int, int]\n \"\"\"\n supported_sm_versions = [\"sm_100\", \"sm_103\"]\n assert sm_version in supported_sm_versions, (\n f\"{supported_sm_versions} are the only supported SM versions for cute-dsl backend, but encountered {sm_version}\"\n )\n\n self.acc_dtype = cutlass.Float32\n self.sf_vec_size = sf_vec_size\n self.use_2cta_instrs = mma_tiler_mn[0] == 256\n self.cluster_shape_mn = cluster_shape_mn\n # K dimension is deferred in _setup_attributes\n self.mma_tiler = (*mma_tiler_mn, 1)\n\n self.cta_group = (\n tcgen05.CtaGroup.TWO if self.use_2cta_instrs else tcgen05.CtaGroup.ONE\n )\n\n self.occupancy = 1\n # Set specialized warp ids\n self.epilog_warp_id = (\n 0,\n 1,\n 2,\n 3,\n )\n self.mma_warp_id = 4\n self.tma_warp_id = 5\n self.threads_per_warp = 32\n self.threads_per_cta = self.threads_per_warp * len(\n (self.mma_warp_id, self.tma_warp_id, *self.epilog_warp_id)\n )\n # Set barrier id for cta sync, epilogue sync and tmem ptr sync\n self.cta_sync_bar_id = 0\n self.epilog_sync_bar_id = 1\n self.tmem_ptr_sync_bar_id = 2\n self.smem_capacity = utils.get_smem_capacity_in_bytes(sm_version)\n SM100_TMEM_CAPACITY_COLUMNS = 512\n self.num_tmem_alloc_cols = SM100_TMEM_CAPACITY_COLUMNS\n\n def _setup_attributes(self):\n \"\"\"Set up configurations that are dependent on GEMM inputs\n\n This method configures various attributes based on the input tensor properties\n (data types, leading dimensions) and kernel settings:\n - Configuring tiled MMA\n - Computing MMA/cluster/tile shapes\n - Computing cluster layout\n - Computing multicast CTAs for A/B/SFA/SFB\n - Computing epilogue subtile\n - Setting up A/B/SFA/SFB/C stage counts in shared memory\n - Computing A/B/SFA/SFB/C shared memory layout\n - Computing tensor memory allocation columns\n \"\"\"\n # Compute mma instruction shapes\n mma_inst_bits_k = 256\n # (MMA_Tile_Shape_M, MMA_Tile_Shape_N, MMA_Inst_Shape_K)\n self.mma_inst_shape_mnk = (\n self.mma_tiler[0],\n self.mma_tiler[1],\n mma_inst_bits_k // self.a_dtype.width,\n )\n # (CTA_Tile_Shape_M, Round_Up(MMA_Tile_Shape_N, 128), MMA_Inst_Shape_K)\n self.mma_inst_shape_mnk_sfb = (\n self.mma_inst_shape_mnk[0] // (2 if self.use_2cta_instrs else 1),\n cute.round_up(self.mma_inst_shape_mnk[1], 128),\n self.mma_inst_shape_mnk[2],\n )\n\n tiled_mma = sm100_utils.make_blockscaled_trivial_tiled_mma(\n self.a_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.sf_dtype,\n self.sf_vec_size,\n self.cta_group,\n self.mma_inst_shape_mnk[:2],\n )\n\n tiled_mma_sfb = sm100_utils.make_blockscaled_trivial_tiled_mma(\n self.a_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.sf_dtype,\n self.sf_vec_size,\n cute.nvgpu.tcgen05.CtaGroup.ONE,\n self.mma_inst_shape_mnk_sfb[:2],\n )\n\n # Compute mma/cluster/tile shapes\n mma_inst_tile_k = 4\n self.mma_tiler = (\n self.mma_inst_shape_mnk[0],\n self.mma_inst_shape_mnk[1],\n self.mma_inst_shape_mnk[2] * mma_inst_tile_k,\n )\n self.mma_tiler_sfb = (\n self.mma_inst_shape_mnk_sfb[0],\n self.mma_inst_shape_mnk_sfb[1],\n self.mma_inst_shape_mnk_sfb[2] * mma_inst_tile_k,\n )\n self.cta_tile_shape_mnk = (\n self.mma_tiler[0] // cute.size(tiled_mma.thr_id.shape),\n self.mma_tiler[1],\n self.mma_tiler[2],\n )\n\n # Compute cluster layout\n self.cluster_layout_vmnk = cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)),\n (tiled_mma.thr_id.shape,),\n )\n self.cluster_layout_sfb_vmnk = cute.tiled_divide(\n cute.make_layout((*self.cluster_shape_mn, 1)),\n (tiled_mma_sfb.thr_id.shape,),\n )\n\n # Compute number of multicast CTAs for A/B\n self.num_mcast_ctas_a = cute.size(self.cluster_layout_vmnk.shape[2])\n self.num_mcast_ctas_b = cute.size(self.cluster_layout_vmnk.shape[1])\n self.num_mcast_ctas_sfb = cute.size(self.cluster_layout_sfb_vmnk.shape[1])\n self.is_a_mcast = self.num_mcast_ctas_a > 1\n self.is_b_mcast = self.num_mcast_ctas_b > 1\n self.is_sfb_mcast = self.num_mcast_ctas_sfb > 1\n\n # Compute epilogue subtile\n self.epi_tile = sm100_utils.compute_epilogue_tile_shape(\n self.cta_tile_shape_mnk,\n self.use_2cta_instrs,\n self.c_layout,\n self.c_dtype,\n )\n\n # Setup A/B/C stage count in shared memory and ACC stage count in tensor memory\n self.num_acc_stage, self.num_ab_stage, self.num_c_stage = self._compute_stages(\n tiled_mma,\n self.mma_tiler,\n self.a_dtype,\n self.a_major_mode,\n self.b_dtype,\n self.b_major_mode,\n self.epi_tile,\n self.c_dtype,\n self.c_layout,\n self.sf_dtype,\n self.sf_vec_size,\n self.smem_capacity,\n self.occupancy,\n )\n\n # Compute A/B/SFA/SFB/C shared memory layout\n self.a_smem_layout_staged = sm100_utils.make_smem_layout_a(\n tiled_mma,\n self.mma_tiler,\n self.a_dtype,\n self.num_ab_stage,\n )\n self.b_smem_layout_staged = sm100_utils.make_smem_layout_b(\n tiled_mma,\n self.mma_tiler,\n self.b_dtype,\n self.num_ab_stage,\n )\n self.sfa_smem_layout_staged = blockscaled_utils.make_smem_layout_sfa(\n tiled_mma,\n self.mma_tiler,\n self.sf_vec_size,\n self.num_ab_stage,\n )\n self.sfb_smem_layout_staged = blockscaled_utils.make_smem_layout_sfb(\n tiled_mma,\n self.mma_tiler,\n self.sf_vec_size,\n self.num_ab_stage,\n )\n self.c_smem_layout_staged = sm100_utils.make_smem_layout_epi(\n self.c_dtype,\n self.c_layout,\n self.epi_tile,\n self.num_c_stage,\n )\n\n @cute.jit\n def __call__(\n self,\n a_tensor: cute.Tensor,\n b_tensor: cute.Tensor,\n sfa_tensor: cute.Tensor,\n sfb_tensor: cute.Tensor,\n c_tensor: cute.Tensor,\n masked_m_tensor: cute.Tensor,\n dst_signals: Optional[cute.Pointer],\n alpha_tensor: Optional[cute.Tensor],\n max_active_clusters: cutlass.Constexpr,\n stream: cuda.CUstream,\n ):\n \"\"\"Execute the GEMM operation in steps:\n - Setup static attributes before smem/grid/tma computation\n - Setup TMA load/store atoms and tensors\n - Compute grid size with regard to hardware constraints\n - Define shared storage for kernel\n - Launch the kernel synchronously\n\n :param a_tensor: Input tensor A\n :type a_tensor: cute.Tensor\n :param b_tensor: Input tensor B\n :type b_tensor: cute.Tensor\n :param sfa_tensor: Scale factor tensor A\n :type sfa_tensor: cute.Tensor\n :param sfb_tensor: Scale factor tensor B\n :type sfb_tensor: cute.Tensor\n :param c_tensor: Output tensor C\n :type c_tensor: cute.Tensor\n :param masked_m_tensor: Masked layout tensor M\n :type masked_m_tensor: cute.Tensor\n :param max_active_clusters: Maximum number of active clusters\n :type max_active_clusters: cutlass.Constexpr\n :param stream: CUDA stream for asynchronous execution\n :type stream: cuda.CUstream\n :param alpha_tensor: Optional 1D tensor of shape (l,) containing per-batch scaling factors.\n :type alpha_tensor: cute.Tensor\n :raises TypeError: If input data types are incompatible with the MMA instruction.\n \"\"\"\n # Setup static attributes before smem/grid/tma computation\n self.a_dtype: Type[cutlass.Numeric] = a_tensor.element_type\n self.b_dtype: Type[cutlass.Numeric] = b_tensor.element_type\n self.sf_dtype: Type[cutlass.Numeric] = sfa_tensor.element_type\n self.c_dtype: Type[cutlass.Numeric] = c_tensor.element_type\n self.a_major_mode = utils.LayoutEnum.from_tensor(a_tensor).mma_major_mode()\n self.b_major_mode = utils.LayoutEnum.from_tensor(b_tensor).mma_major_mode()\n self.c_layout = utils.LayoutEnum.from_tensor(c_tensor)\n\n # Check if input data types are compatible with MMA instruction\n if cutlass.const_expr(self.a_dtype != self.b_dtype):\n raise TypeError(f\"Type must match: {self.a_dtype} != {self.b_dtype}\")\n\n # Setup attributes that dependent on gemm inputs\n self._setup_attributes()\n\n # Setup sfa/sfb tensor by filling A/B tensor to scale factor atom layout\n # ((Atom_M, Rest_M),(Atom_K, Rest_K),RestL)\n sfa_layout = blockscaled_utils.tile_atom_to_shape_SF(\n a_tensor.shape, self.sf_vec_size\n )\n sfa_tensor = cute.make_tensor(sfa_tensor.iterator, sfa_layout)\n\n # ((Atom_N, Rest_N),(Atom_K, Rest_K),RestL)\n sfb_layout = blockscaled_utils.tile_atom_to_shape_SF(\n b_tensor.shape, self.sf_vec_size\n )\n sfb_tensor = cute.make_tensor(sfb_tensor.iterator, sfb_layout)\n\n tiled_mma = sm100_utils.make_blockscaled_trivial_tiled_mma(\n self.a_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.sf_dtype,\n self.sf_vec_size,\n self.cta_group,\n self.mma_inst_shape_mnk[:2],\n )\n\n tiled_mma_sfb = sm100_utils.make_blockscaled_trivial_tiled_mma(\n self.a_dtype,\n self.a_major_mode,\n self.b_major_mode,\n self.sf_dtype,\n self.sf_vec_size,\n cute.nvgpu.tcgen05.CtaGroup.ONE,\n self.mma_inst_shape_mnk_sfb[:2],\n )\n atom_thr_size = cute.size(tiled_mma.thr_id.shape)\n\n # Setup TMA load for A\n a_op = sm100_utils.cluster_shape_to_tma_atom_A(\n self.cluster_shape_mn, tiled_mma.thr_id\n )\n a_smem_layout = cute.slice_(self.a_smem_layout_staged, (None, None, None, 0))\n tma_atom_a, tma_tensor_a = cute.nvgpu.make_tiled_tma_atom_A(\n a_op,\n a_tensor,\n a_smem_layout,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n )\n\n # Setup TMA load for B\n b_op = sm100_utils.cluster_shape_to_tma_atom_B(\n self.cluster_shape_mn, tiled_mma.thr_id\n )\n b_smem_layout = cute.slice_(self.b_smem_layout_staged, (None, None, None, 0))\n tma_atom_b, tma_tensor_b = cute.nvgpu.make_tiled_tma_atom_B(\n b_op,\n b_tensor,\n b_smem_layout,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n )\n\n # Setup TMA load for SFA\n sfa_op = sm100_utils.cluster_shape_to_tma_atom_A(\n self.cluster_shape_mn, tiled_mma.thr_id\n )\n sfa_smem_layout = cute.slice_(\n self.sfa_smem_layout_staged, (None, None, None, 0)\n )\n tma_atom_sfa, tma_tensor_sfa = cute.nvgpu.make_tiled_tma_atom_A(\n sfa_op,\n sfa_tensor,\n sfa_smem_layout,\n self.mma_tiler,\n tiled_mma,\n self.cluster_layout_vmnk.shape,\n internal_type=cutlass.Int16,\n )\n\n # Setup TMA load for SFB\n sfb_op = sm100_utils.cluster_shape_to_tma_atom_SFB(\n self.cluster_shape_mn, tiled_mma.thr_id\n )\n sfb_smem_layout = cute.slice_(\n self.sfb_smem_layout_staged, (None, None, None, 0)\n )\n tma_atom_sfb, tma_tensor_sfb = cute.nvgpu.make_tiled_tma_atom_B(\n sfb_op,\n sfb_tensor,\n sfb_smem_layout,\n self.mma_tiler_sfb,\n tiled_mma_sfb,\n self.cluster_layout_sfb_vmnk.shape,\n internal_type=cutlass.Int16,\n )\n\n a_copy_size = cute.size_in_bytes(self.a_dtype, a_smem_layout)\n b_copy_size = cute.size_in_bytes(self.b_dtype, b_smem_layout)\n sfa_copy_size = cute.size_in_bytes(self.sf_dtype, sfa_smem_layout)\n sfb_copy_size = cute.size_in_bytes(self.sf_dtype, sfb_smem_layout)\n self.num_tma_load_bytes = (\n a_copy_size + b_copy_size + sfa_copy_size + sfb_copy_size\n ) * atom_thr_size\n\n # Setup TMA store for C\n epi_smem_layout = cute.slice_(self.c_smem_layout_staged, (None, None, 0))\n tma_atom_c, tma_tensor_c = cpasync.make_tiled_tma_atom(\n cpasync.CopyBulkTensorTileS2GOp(),\n c_tensor,\n epi_smem_layout,\n self.epi_tile,\n )\n\n # Compute grid size\n self.tile_sched_params, grid = self._compute_grid(\n masked_m_tensor, # add masked layout\n dst_signals,\n c_tensor,\n self.cta_tile_shape_mnk,\n self.cluster_shape_mn,\n max_active_clusters,\n )\n\n self.buffer_align_bytes = 1024\n\n # Define shared storage for kernel\n @cute.struct\n class SharedStorage:\n ab_full_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_ab_stage]\n ab_empty_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_ab_stage]\n acc_full_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]\n acc_empty_mbar_ptr: cute.struct.MemRange[cutlass.Int64, self.num_acc_stage]\n tmem_dealloc_mbar_ptr: cutlass.Int64\n tmem_holding_buf: cutlass.Int32\n # (EPI_TILE_M, EPI_TILE_N, STAGE)\n sC: cute.struct.Align[\n cute.struct.MemRange[\n self.c_dtype,\n cute.cosize(self.c_smem_layout_staged.outer),\n ],\n self.buffer_align_bytes,\n ]\n # (MMA, MMA_M, MMA_K, STAGE)\n sA: cute.struct.Align[\n cute.struct.MemRange[\n self.a_dtype, cute.cosize(self.a_smem_layout_staged.outer)\n ],\n self.buffer_align_bytes,\n ]\n # (MMA, MMA_N, MMA_K, STAGE)\n sB: cute.struct.Align[\n cute.struct.MemRange[\n self.b_dtype, cute.cosize(self.b_smem_layout_staged.outer)\n ],\n self.buffer_align_bytes,\n ]\n # (MMA, MMA_M, MMA_K, STAGE)\n sSFA: cute.struct.Align[\n cute.struct.MemRange[\n self.sf_dtype, cute.cosize(self.sfa_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n # (MMA, MMA_N, MMA_K, STAGE)\n sSFB: cute.struct.Align[\n cute.struct.MemRange[\n self.sf_dtype, cute.cosize(self.sfb_smem_layout_staged)\n ],\n self.buffer_align_bytes,\n ]\n\n self.shared_storage = SharedStorage\n\n # Launch the kernel synchronously\n self.kernel(\n tiled_mma,\n tiled_mma_sfb,\n tma_atom_a,\n tma_tensor_a,\n tma_atom_b,\n tma_tensor_b,\n tma_atom_sfa,\n tma_tensor_sfa,\n tma_atom_sfb,\n tma_tensor_sfb,\n tma_atom_c,\n tma_tensor_c,\n alpha_tensor,\n self.cluster_layout_vmnk,\n self.cluster_layout_sfb_vmnk,\n self.a_smem_layout_staged,\n self.b_smem_layout_staged,\n self.sfa_smem_layout_staged,\n self.sfb_smem_layout_staged,\n self.c_smem_layout_staged,\n self.epi_tile,\n self.tile_sched_params,\n ).launch(\n grid=grid,\n block=[self.threads_per_cta, 1, 1],\n cluster=(*self.cluster_shape_mn, 1),\n smem=self.shared_storage.size_in_bytes(), # type: ignore[attr-defined]\n stream=stream,\n )\n return\n\n # GPU device kernel\n @cute.kernel\n def kernel(\n self,\n tiled_mma: cute.TiledMma,\n tiled_mma_sfb: cute.TiledMma,\n tma_atom_a: cute.CopyAtom,\n mA_mkl: cute.Tensor,\n tma_atom_b: cute.CopyAtom,\n mB_nkl: cute.Tensor,\n tma_atom_sfa: cute.CopyAtom,\n mSFA_mkl: cute.Tensor,\n tma_atom_sfb: cute.CopyAtom,\n mSFB_nkl: cute.Tensor,\n tma_atom_c: Optional[cute.CopyAtom],\n mC_mnl: cute.Tensor,\n alpha: Optional[cute.Tensor],\n cluster_layout_vmnk: cute.Layout,\n cluster_layout_sfb_vmnk: cute.Layout,\n a_smem_layout_staged: cute.ComposedLayout,\n b_smem_layout_staged: cute.ComposedLayout,\n sfa_smem_layout_staged: cute.Layout,\n sfb_smem_layout_staged: cute.Layout,\n c_smem_layout_staged: Union[cute.Layout, cute.ComposedLayout, None],\n epi_tile: cute.Tile,\n tile_sched_params: MaskedSchedulerParams,\n ):\n \"\"\"\n GPU device kernel performing the Persistent batched GEMM computation.\n \"\"\"\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n\n #\n # Prefetch tma desc\n #\n if warp_idx == self.tma_warp_id:\n cpasync.prefetch_descriptor(tma_atom_a)\n cpasync.prefetch_descriptor(tma_atom_b)\n cpasync.prefetch_descriptor(tma_atom_sfa)\n cpasync.prefetch_descriptor(tma_atom_sfb)\n cpasync.prefetch_descriptor(tma_atom_c)\n\n use_2cta_instrs = cute.size(tiled_mma.thr_id.shape) == 2\n\n #\n # Setup cta/thread coordinates\n #\n # Coords inside cluster\n bidx, bidy, bidz = cute.arch.block_idx()\n mma_tile_coord_v = bidx % cute.size(tiled_mma.thr_id.shape)\n is_leader_cta = mma_tile_coord_v == 0\n cta_rank_in_cluster = cute.arch.make_warp_uniform(\n cute.arch.block_idx_in_cluster()\n )\n block_in_cluster_coord_vmnk = cluster_layout_vmnk.get_flat_coord(\n cta_rank_in_cluster\n )\n block_in_cluster_coord_sfb_vmnk = cluster_layout_sfb_vmnk.get_flat_coord(\n cta_rank_in_cluster\n )\n # Coord inside cta\n tidx, _, _ = cute.arch.thread_idx()\n\n #\n # Alloc and init: a+b full/empty, accumulator full/empty, tensor memory dealloc barrier\n #\n smem = utils.SmemAllocator()\n storage = smem.allocate(self.shared_storage)\n\n tmem_dealloc_mbar_ptr = storage.tmem_dealloc_mbar_ptr\n tmem_holding_buf = storage.tmem_holding_buf\n\n # Initialize mainloop ab_pipeline (barrier) and states\n ab_pipeline_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread)\n num_tma_producer = self.num_mcast_ctas_a + self.num_mcast_ctas_b - 1\n ab_pipeline_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, num_tma_producer\n )\n ab_pipeline = pipeline.PipelineTmaUmma.create(\n barrier_storage=storage.ab_full_mbar_ptr.data_ptr(),\n num_stages=self.num_ab_stage,\n producer_group=ab_pipeline_producer_group,\n consumer_group=ab_pipeline_consumer_group,\n tx_count=self.num_tma_load_bytes,\n cta_layout_vmnk=cluster_layout_vmnk,\n )\n\n # Initialize acc_pipeline (barrier) and states\n acc_pipeline_producer_group = pipeline.CooperativeGroup(pipeline.Agent.Thread)\n num_acc_consumer_threads = (\n self.threads_per_warp\n * len(self.epilog_warp_id)\n * (2 if use_2cta_instrs else 1)\n )\n acc_pipeline_consumer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread, num_acc_consumer_threads\n )\n acc_pipeline = pipeline.PipelineUmmaAsync.create(\n barrier_storage=storage.acc_full_mbar_ptr.data_ptr(),\n num_stages=self.num_acc_stage,\n producer_group=acc_pipeline_producer_group,\n consumer_group=acc_pipeline_consumer_group,\n cta_layout_vmnk=cluster_layout_vmnk,\n )\n\n # Tensor memory dealloc barrier init\n if use_2cta_instrs:\n if warp_idx == self.tma_warp_id:\n num_tmem_dealloc_threads = 32\n with cute.arch.elect_one():\n cute.arch.mbarrier_init(\n tmem_dealloc_mbar_ptr, num_tmem_dealloc_threads\n )\n cute.arch.mbarrier_init_fence()\n\n # Cluster arrive after barrier init\n if cute.size(self.cluster_shape_mn) > 1:\n cute.arch.cluster_arrive_relaxed()\n\n #\n # Setup smem tensor A/B/SFA/SFB/C\n #\n # (EPI_TILE_M, EPI_TILE_N, STAGE)\n sC = storage.sC.get_tensor(\n c_smem_layout_staged.outer, swizzle=c_smem_layout_staged.inner\n )\n # (MMA, MMA_M, MMA_K, STAGE)\n sA = storage.sA.get_tensor(\n a_smem_layout_staged.outer, swizzle=a_smem_layout_staged.inner\n )\n # (MMA, MMA_N, MMA_K, STAGE)\n sB = storage.sB.get_tensor(\n b_smem_layout_staged.outer, swizzle=b_smem_layout_staged.inner\n )\n # (MMA, MMA_M, MMA_K, STAGE)\n sSFA = storage.sSFA.get_tensor(sfa_smem_layout_staged)\n # (MMA, MMA_N, MMA_K, STAGE)\n sSFB = storage.sSFB.get_tensor(sfb_smem_layout_staged)\n\n #\n # Compute multicast mask for A/B/SFA/SFB buffer full\n #\n a_full_mcast_mask = None\n b_full_mcast_mask = None\n sfa_full_mcast_mask = None\n sfb_full_mcast_mask = None\n if cutlass.const_expr(self.is_a_mcast or self.is_b_mcast or use_2cta_instrs):\n a_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=2\n )\n b_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=1\n )\n sfa_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_vmnk, block_in_cluster_coord_vmnk, mcast_mode=2\n )\n sfb_full_mcast_mask = cpasync.create_tma_multicast_mask(\n cluster_layout_sfb_vmnk, block_in_cluster_coord_sfb_vmnk, mcast_mode=1\n )\n\n #\n # Local_tile partition global tensors\n #\n # (bM, bK, RestM, RestK, RestL)\n gA_mkl = cute.local_tile(\n mA_mkl, cute.slice_(self.mma_tiler, (None, 0, None)), (None, None, None)\n )\n # (bN, bK, RestN, RestK, RestL)\n gB_nkl = cute.local_tile(\n mB_nkl, cute.slice_(self.mma_tiler, (0, None, None)), (None, None, None)\n )\n # (bM, bK, RestM, RestK, RestL)\n gSFA_mkl = cute.local_tile(\n mSFA_mkl, cute.slice_(self.mma_tiler, (None, 0, None)), (None, None, None)\n )\n # (bN, bK, RestN, RestK, RestL)\n gSFB_nkl = cute.local_tile(\n mSFB_nkl, cute.slice_(self.mma_tiler, (0, None, None)), (None, None, None)\n )\n # (bM, bN, RestM, RestN, RestL)\n gC_mnl = cute.local_tile(\n mC_mnl, cute.slice_(self.mma_tiler, (None, None, 0)), (None, None, None)\n )\n k_block_cnt = cute.size(gA_mkl, mode=[3])\n\n #\n # Partition global tensor for TiledMMA_A/B/C\n #\n thr_mma = tiled_mma.get_slice(mma_tile_coord_v)\n thr_mma_sfb = tiled_mma_sfb.get_slice(mma_tile_coord_v)\n # (MMA, MMA_M, MMA_K, RestM, RestK, RestL)\n tCgA = thr_mma.partition_A(gA_mkl)\n # (MMA, MMA_N, MMA_K, RestN, RestK, RestL)\n tCgB = thr_mma.partition_B(gB_nkl)\n # (MMA, MMA_M, MMA_K, RestM, RestK, RestL)\n tCgSFA = thr_mma.partition_A(gSFA_mkl)\n # (MMA, MMA_N, MMA_K, RestN, RestK, RestL)\n tCgSFB = thr_mma_sfb.partition_B(gSFB_nkl)\n # (MMA, MMA_M, MMA_N, RestM, RestN, RestL)\n tCgC = thr_mma.partition_C(gC_mnl)\n\n #\n # Partition global/shared tensor for TMA load A/B\n #\n # TMA load A partition_S/D\n a_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_vmnk, (0, 0, None, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), RestM, RestK, RestL)\n tAsA, tAgA = cpasync.tma_partition(\n tma_atom_a,\n block_in_cluster_coord_vmnk[2],\n a_cta_layout,\n cute.group_modes(sA, 0, 3),\n cute.group_modes(tCgA, 0, 3),\n )\n # TMA load B partition_S/D\n b_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_vmnk, (0, None, 0, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), RestN, RestK, RestL)\n tBsB, tBgB = cpasync.tma_partition(\n tma_atom_b,\n block_in_cluster_coord_vmnk[1],\n b_cta_layout,\n cute.group_modes(sB, 0, 3),\n cute.group_modes(tCgB, 0, 3),\n )\n\n # TMA load SFA partition_S/D\n sfa_cta_layout = a_cta_layout\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), RestM, RestK, RestL)\n tAsSFA, tAgSFA = cute.nvgpu.cpasync.tma_partition(\n tma_atom_sfa,\n block_in_cluster_coord_vmnk[2],\n sfa_cta_layout,\n cute.group_modes(sSFA, 0, 3),\n cute.group_modes(tCgSFA, 0, 3),\n )\n tAsSFA = cute.filter_zeros(tAsSFA)\n tAgSFA = cute.filter_zeros(tAgSFA)\n\n # TMA load SFB partition_S/D\n sfb_cta_layout = cute.make_layout(\n cute.slice_(cluster_layout_sfb_vmnk, (0, None, 0, 0)).shape\n )\n # ((atom_v, rest_v), STAGE)\n # ((atom_v, rest_v), RestN, RestK, RestL)\n tBsSFB, tBgSFB = cute.nvgpu.cpasync.tma_partition(\n tma_atom_sfb,\n block_in_cluster_coord_sfb_vmnk[1],\n sfb_cta_layout,\n cute.group_modes(sSFB, 0, 3),\n cute.group_modes(tCgSFB, 0, 3),\n )\n tBsSFB = cute.filter_zeros(tBsSFB)\n tBgSFB = cute.filter_zeros(tBgSFB)\n\n #\n # Partition shared/tensor memory tensor for TiledMMA_A/B/C\n #\n # (MMA, MMA_M, MMA_K, STAGE)\n tCrA = tiled_mma.make_fragment_A(sA)\n # (MMA, MMA_N, MMA_K, STAGE)\n tCrB = tiled_mma.make_fragment_B(sB)\n # (MMA, MMA_M, MMA_N)\n acc_shape = tiled_mma.partition_shape_C(self.mma_tiler[:2])\n # (MMA, MMA_M, MMA_N, STAGE)\n tCtAcc_fake = tiled_mma.make_fragment_C(\n cute.append(acc_shape, self.num_acc_stage)\n )\n\n #\n # Cluster wait before tensor memory alloc\n #\n if cute.size(self.cluster_shape_mn) > 1:\n cute.arch.cluster_wait()\n else:\n cute.arch.barrier(\n barrier_id=self.cta_sync_bar_id, number_of_threads=self.threads_per_cta\n )\n\n #\n # Specialized TMA load warp\n #\n if warp_idx == self.tma_warp_id:\n #\n # Persistent tile scheduling loop\n #\n tile_sched = MaskedScheduler.create(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n ab_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_ab_stage\n )\n\n while work_tile.is_valid_tile:\n # Get tile coord from tile scheduler\n cur_tile_coord = work_tile.tile_idx\n mma_tile_coord_mnl = (\n cur_tile_coord[0] // cute.size(tiled_mma.thr_id.shape),\n cur_tile_coord[1],\n cur_tile_coord[2],\n )\n\n #\n # Slice to per mma tile index\n #\n # ((atom_v, rest_v), RestK)\n tAgA_slice = tAgA[\n (None, mma_tile_coord_mnl[0], None, mma_tile_coord_mnl[2])\n ]\n # ((atom_v, rest_v), RestK)\n tBgB_slice = tBgB[\n (None, mma_tile_coord_mnl[1], None, mma_tile_coord_mnl[2])\n ]\n\n # ((atom_v, rest_v), RestK)\n tAgSFA_slice = tAgSFA[\n (None, mma_tile_coord_mnl[0], None, mma_tile_coord_mnl[2])\n ]\n # ((atom_v, rest_v), RestK)\n tBgSFB_slice = tBgSFB[\n (None, mma_tile_coord_mnl[1], None, mma_tile_coord_mnl[2])\n ]\n\n # Peek (try_wait) AB buffer empty for k_block = prefetch_k_block_cnt\n ab_producer_state.reset_count()\n peek_ab_empty_status = cutlass.Boolean(1)\n if ab_producer_state.count < k_block_cnt:\n peek_ab_empty_status = ab_pipeline.producer_try_acquire(\n ab_producer_state\n )\n #\n # Tma load loop\n #\n for k_block in cutlass.range(0, k_block_cnt, 1, unroll=1): # noqa: B007\n # Conditionally wait for AB buffer empty\n ab_pipeline.producer_acquire(\n ab_producer_state, peek_ab_empty_status\n )\n\n # TMA load A/B/SFA/SFB\n cute.copy(\n tma_atom_a,\n tAgA_slice[(None, ab_producer_state.count)],\n tAsA[(None, ab_producer_state.index)],\n tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_producer_state),\n mcast_mask=a_full_mcast_mask,\n )\n cute.copy(\n tma_atom_b,\n tBgB_slice[(None, ab_producer_state.count)],\n tBsB[(None, ab_producer_state.index)],\n tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_producer_state),\n mcast_mask=b_full_mcast_mask,\n )\n cute.copy(\n tma_atom_sfa,\n tAgSFA_slice[(None, ab_producer_state.count)],\n tAsSFA[(None, ab_producer_state.index)],\n tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_producer_state),\n mcast_mask=sfa_full_mcast_mask,\n )\n cute.copy(\n tma_atom_sfb,\n tBgSFB_slice[(None, ab_producer_state.count)],\n tBsSFB[(None, ab_producer_state.index)],\n tma_bar_ptr=ab_pipeline.producer_get_barrier(ab_producer_state),\n mcast_mask=sfb_full_mcast_mask,\n )\n\n # Peek (try_wait) AB buffer empty for k_block = prefetch_k_block_cnt + k_block + 1\n ab_producer_state.advance()\n peek_ab_empty_status = cutlass.Boolean(1)\n if ab_producer_state.count < k_block_cnt:\n peek_ab_empty_status = ab_pipeline.producer_try_acquire(\n ab_producer_state\n )\n\n #\n # Advance to next tile\n #\n tile_sched.advance_to_next_work()\n work_tile, _ = tile_sched.get_current_work()\n\n #\n # Wait A/B buffer empty\n #\n ab_pipeline.producer_tail(ab_producer_state)\n\n #\n # Specialized MMA warp\n #\n if warp_idx == self.mma_warp_id:\n #\n # Bar sync for retrieve tensor memory ptr from shared mem\n #\n tmem_ptr_read_threads = self.threads_per_warp * len(\n (self.mma_warp_id, *self.epilog_warp_id)\n )\n cute.arch.barrier(\n barrier_id=self.tmem_ptr_sync_bar_id,\n number_of_threads=tmem_ptr_read_threads,\n )\n\n #\n # Retrieving tensor memory ptr and make accumulator/SFA/SFB tensor\n #\n # Make accumulator tmem tensor\n acc_tmem_ptr = cute.arch.retrieve_tmem_ptr(\n self.acc_dtype,\n alignment=16,\n ptr_to_buffer_holding_addr=tmem_holding_buf,\n )\n # (MMA, MMA_M, MMA_N, STAGE)\n tCtAcc_base = cute.make_tensor(acc_tmem_ptr, tCtAcc_fake.layout)\n\n # Make SFA tmem tensor\n sfa_tmem_ptr = cute.recast_ptr(\n acc_tmem_ptr + tcgen05.find_tmem_tensor_col_offset(tCtAcc_base),\n dtype=self.sf_dtype,\n )\n # (MMA, MMA_M, MMA_K)\n tCtSFA_layout = blockscaled_utils.make_tmem_layout_sfa(\n tiled_mma,\n self.mma_tiler,\n self.sf_vec_size,\n cute.slice_(sfa_smem_layout_staged, (None, None, None, 0)),\n )\n tCtSFA = cute.make_tensor(sfa_tmem_ptr, tCtSFA_layout)\n\n # Make SFB tmem tensor\n sfb_tmem_ptr = cute.recast_ptr(\n acc_tmem_ptr\n + tcgen05.find_tmem_tensor_col_offset(tCtAcc_base)\n + tcgen05.find_tmem_tensor_col_offset(tCtSFA),\n dtype=self.sf_dtype,\n )\n # (MMA, MMA_N, MMA_K)\n tCtSFB_layout = blockscaled_utils.make_tmem_layout_sfb(\n tiled_mma,\n self.mma_tiler,\n self.sf_vec_size,\n cute.slice_(sfb_smem_layout_staged, (None, None, None, 0)),\n )\n tCtSFB = cute.make_tensor(sfb_tmem_ptr, tCtSFB_layout)\n #\n # Partition for S2T copy of SFA/SFB\n #\n tiled_copy_s2t_sfa, tCsSFA_compact_s2t, tCtSFA_compact_s2t = (\n self.mainloop_s2t_copy_and_partition(sSFA, tCtSFA)\n )\n tiled_copy_s2t_sfb, tCsSFB_compact_s2t, tCtSFB_compact_s2t = (\n self.mainloop_s2t_copy_and_partition(sSFB, tCtSFB)\n )\n\n #\n # Persistent tile scheduling loop\n #\n tile_sched = MaskedScheduler.create(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n ab_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_ab_stage\n )\n acc_producer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Producer, self.num_acc_stage\n )\n\n while work_tile.is_valid_tile:\n # Get tile coord from tile scheduler\n cur_tile_coord = work_tile.tile_idx\n mma_tile_coord_mnl = (\n cur_tile_coord[0] // cute.size(tiled_mma.thr_id.shape),\n cur_tile_coord[1],\n cur_tile_coord[2],\n )\n\n # Set tensor memory buffer for current tile\n # (MMA, MMA_M, MMA_N)\n tCtAcc = tCtAcc_base[(None, None, None, acc_producer_state.index)]\n\n # Peek (try_wait) AB buffer full for k_block = 0\n ab_consumer_state.reset_count()\n peek_ab_full_status = cutlass.Boolean(1)\n if ab_consumer_state.count < k_block_cnt and is_leader_cta:\n peek_ab_full_status = ab_pipeline.consumer_try_wait(\n ab_consumer_state\n )\n\n #\n # Wait for accumulator buffer empty\n #\n if is_leader_cta:\n acc_pipeline.producer_acquire(acc_producer_state)\n\n #\n # Reset the ACCUMULATE field for each tile\n #\n tiled_mma.set(tcgen05.Field.ACCUMULATE, False)\n\n #\n # Mma mainloop\n #\n for k_block in cutlass.range_constexpr(k_block_cnt): # noqa: B007\n if is_leader_cta:\n # Conditionally wait for AB buffer full\n ab_pipeline.consumer_wait(\n ab_consumer_state, peek_ab_full_status\n )\n\n # Copy SFA/SFB from smem to tmem\n s2t_stage_coord = (\n None,\n None,\n None,\n None,\n ab_consumer_state.index,\n )\n tCsSFA_compact_s2t_staged = tCsSFA_compact_s2t[s2t_stage_coord]\n tCsSFB_compact_s2t_staged = tCsSFB_compact_s2t[s2t_stage_coord]\n cute.copy(\n tiled_copy_s2t_sfa,\n tCsSFA_compact_s2t_staged,\n tCtSFA_compact_s2t,\n )\n cute.copy(\n tiled_copy_s2t_sfb,\n tCsSFB_compact_s2t_staged,\n tCtSFB_compact_s2t,\n )\n\n # tCtAcc += tCrA * tCrSFA * tCrB * tCrSFB\n num_kphases = cute.size(tCrA, mode=[2])\n for kphase_idx in cutlass.range(num_kphases, unroll_full=True):\n kphase_coord = (\n None,\n None,\n kphase_idx,\n ab_consumer_state.index,\n )\n\n # Set SFA/SFB tensor to tiled_mma\n sf_kphase_coord = (None, None, kphase_idx)\n tiled_mma.set(\n tcgen05.Field.SFA,\n tCtSFA[sf_kphase_coord].iterator,\n )\n tiled_mma.set(\n tcgen05.Field.SFB,\n tCtSFB[sf_kphase_coord].iterator,\n )\n\n cute.gemm(\n tiled_mma,\n tCtAcc,\n tCrA[kphase_coord],\n tCrB[kphase_coord],\n tCtAcc,\n )\n\n # Enable accumulate on tCtAcc after first kphase\n tiled_mma.set(tcgen05.Field.ACCUMULATE, True)\n\n # Async arrive AB buffer empty\n ab_pipeline.consumer_release(ab_consumer_state)\n\n # Peek (try_wait) AB buffer full for k_block = k_block + 1\n ab_consumer_state.advance()\n peek_ab_full_status = cutlass.Boolean(1)\n if ab_consumer_state.count < k_block_cnt:\n if is_leader_cta:\n peek_ab_full_status = ab_pipeline.consumer_try_wait(\n ab_consumer_state\n )\n\n #\n # Async arrive accumulator buffer full\n #\n if is_leader_cta:\n acc_pipeline.producer_commit(acc_producer_state)\n acc_producer_state.advance()\n\n #\n # Advance to next tile\n #\n tile_sched.advance_to_next_work()\n work_tile, _ = tile_sched.get_current_work()\n\n #\n # Wait for accumulator buffer empty\n #\n acc_pipeline.producer_tail(acc_producer_state)\n #\n # Specialized epilogue warps\n #\n if warp_idx < self.mma_warp_id:\n #\n # Alloc tensor memory buffer\n #\n if warp_idx == self.epilog_warp_id[0]:\n cute.arch.alloc_tmem(\n self.num_tmem_alloc_cols,\n tmem_holding_buf,\n is_two_cta=use_2cta_instrs,\n )\n\n #\n # Bar sync for retrieve tensor memory ptr from shared memory\n #\n tmem_ptr_read_threads = self.threads_per_warp * len(\n (self.mma_warp_id, *self.epilog_warp_id)\n )\n cute.arch.barrier(\n barrier_id=self.tmem_ptr_sync_bar_id,\n number_of_threads=tmem_ptr_read_threads,\n )\n\n #\n # Retrieving tensor memory ptr and make accumulator tensor\n #\n acc_tmem_ptr = cute.arch.retrieve_tmem_ptr(\n self.acc_dtype,\n alignment=16,\n ptr_to_buffer_holding_addr=tmem_holding_buf,\n )\n # (MMA, MMA_M, MMA_N, STAGE)\n tCtAcc_base = cute.make_tensor(acc_tmem_ptr, tCtAcc_fake.layout)\n\n #\n # Partition for epilogue\n #\n epi_tidx = tidx\n tiled_copy_t2r, tTR_tAcc_base, tTR_rAcc = (\n self.epilog_tmem_copy_and_partition(\n epi_tidx, tCtAcc_base, tCgC, epi_tile, use_2cta_instrs\n )\n )\n\n tTR_rC = cute.make_fragment(tTR_rAcc.shape, self.c_dtype)\n tiled_copy_r2s, tRS_rC, tRS_sC = self.epilog_smem_copy_and_partition(\n tiled_copy_t2r, tTR_rC, epi_tidx, sC\n )\n tma_atom_c, bSG_sC, bSG_gC_partitioned = (\n self.epilog_gmem_copy_and_partition(\n epi_tidx, tma_atom_c, tCgC, epi_tile, sC\n )\n )\n\n #\n # Persistent tile scheduling loop\n #\n tile_sched = MaskedScheduler.create(\n tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n )\n work_tile = tile_sched.initial_work_tile_info()\n\n acc_consumer_state = pipeline.make_pipeline_state(\n pipeline.PipelineUserType.Consumer, self.num_acc_stage\n )\n\n # Threads/warps participating in tma store pipeline\n c_producer_group = pipeline.CooperativeGroup(\n pipeline.Agent.Thread,\n self.threads_per_warp * len(self.epilog_warp_id),\n self.threads_per_warp * len(self.epilog_warp_id),\n )\n c_pipeline = pipeline.PipelineTmaStore.create(\n num_stages=self.num_c_stage,\n producer_group=c_producer_group,\n )\n\n if cutlass.const_expr(tile_sched_params.dst_signals is not None):\n assert self.num_c_stage < 256, \"must be representable in 1 byte\"\n num_experts = tile_sched_params.masked_m.shape[0]\n assert num_experts <= 8, \"need to be packable into a u64\"\n dsm_pending_packed = Uint64(0)\n dsm_pending_idx = Int32(0)\n dsm_counter = Uint8(0)\n\n while work_tile.is_valid_tile:\n # Get tile coord from tile scheduler\n cur_tile_coord = work_tile.tile_idx\n mma_tile_coord_mnl = (\n cur_tile_coord[0] // cute.size(tiled_mma.thr_id.shape),\n cur_tile_coord[1],\n cur_tile_coord[2],\n )\n\n #\n # Slice to per mma tile index\n #\n # ((ATOM_V, REST_V), EPI_M, EPI_N)\n bSG_gC = bSG_gC_partitioned[\n (\n None,\n None,\n None,\n *mma_tile_coord_mnl,\n )\n ]\n\n # Set tensor memory buffer for current tile\n # (T2R, T2R_M, T2R_N, EPI_M, EPI_M)\n tTR_tAcc = tTR_tAcc_base[\n (None, None, None, None, None, acc_consumer_state.index)\n ]\n\n #\n # Wait for accumulator buffer full\n #\n acc_pipeline.consumer_wait(acc_consumer_state)\n\n tTR_tAcc = cute.group_modes(tTR_tAcc, 3, cute.rank(tTR_tAcc))\n bSG_gC = cute.group_modes(bSG_gC, 1, cute.rank(bSG_gC))\n\n #\n # Store accumulator to global memory in subtiles\n #\n subtile_cnt = cute.size(tTR_tAcc.shape, mode=[3])\n num_prev_subtiles = tile_sched.num_tiles_executed * subtile_cnt\n for subtile_idx in cutlass.range(subtile_cnt):\n #\n # Load accumulator from tensor memory buffer to register\n #\n tTR_tAcc_mn = tTR_tAcc[(None, None, None, subtile_idx)]\n cute.copy(tiled_copy_t2r, tTR_tAcc_mn, tTR_rAcc)\n\n #\n # Convert to C type\n #\n acc_vec = tiled_copy_r2s.retile(tTR_rAcc).load()\n if cutlass.const_expr(alpha is not None):\n acc_vec = acc_vec * alpha[work_tile.tile_idx[2]]\n\n acc_vec = acc_vec.to(self.c_dtype)\n tRS_rC.store(acc_vec)\n\n #\n # Store C to shared memory\n #\n c_buffer = (num_prev_subtiles + subtile_idx) % self.num_c_stage\n cute.copy(\n tiled_copy_r2s,\n tRS_rC,\n tRS_sC[(None, None, None, c_buffer)],\n )\n # Fence and barrier to make sure shared memory store is visible to TMA store\n cute.arch.fence_proxy(\"async.shared\", space=\"cta\")\n epilog_threads = self.threads_per_warp * len(self.epilog_warp_id)\n cute.arch.barrier(\n barrier_id=self.epilog_sync_bar_id,\n number_of_threads=epilog_threads,\n )\n\n #\n # TMA store C to global memory\n #\n if warp_idx == self.epilog_warp_id[0]:\n cute.copy(\n tma_atom_c,\n bSG_sC[(None, c_buffer)],\n bSG_gC[(None, subtile_idx)],\n )\n\n # Fence and barrier to make sure shared memory store is visible to TMA store\n c_pipeline.producer_commit()\n\n if cutlass.const_expr(\n tile_sched_params.dst_signals is not None\n ):\n dsm_counter = (dsm_counter + 1).to(Uint8)\n will_write_signals = (\n read_byte(dsm_pending_packed, dsm_pending_idx)\n == dsm_counter\n )\n\n if will_write_signals:\n # The original c_pipeline.producer_acquire()\n # := PipelineTmaStore.producer_acquire()\n # := TmaStoreFence.wait()\n # := cute.arch.cp_async_bulk_wait_group(self.num_stages - 1, read=True)\n cute.arch.cp_async_bulk_wait_group(\n self.num_c_stage - 1,\n # Change `read` from True to False to also wait writes\n read=False,\n )\n else:\n c_pipeline.producer_acquire()\n\n else:\n c_pipeline.producer_acquire()\n\n cute.arch.barrier(\n barrier_id=self.epilog_sync_bar_id,\n number_of_threads=epilog_threads,\n )\n\n if cutlass.const_expr(tile_sched_params.dst_signals is not None):\n lane_id = tidx % 32\n if warp_idx == self.epilog_warp_id[0] and lane_id == 0:\n while (dsm_pending_idx < num_experts) and (\n read_byte(dsm_pending_packed, dsm_pending_idx)\n == dsm_counter\n ):\n atomic_add_release_global(\n tile_sched_params.dst_signals.toint()\n + sizeof_i32 * dsm_pending_idx,\n value=1,\n )\n dsm_pending_idx += 1\n\n #\n # Async arrive accumulator buffer empty\n #\n acc_pipeline.consumer_release(acc_consumer_state)\n acc_consumer_state.advance()\n\n #\n # Advance to next tile\n #\n tile_sched.advance_to_next_work()\n work_tile, dsm_pending_packed = tile_sched.get_current_work(\n dsm_pending_packed=dsm_pending_packed,\n dsm_counter=dsm_counter,\n num_c_stage=self.num_c_stage,\n )\n\n #\n # Dealloc the tensor memory buffer\n #\n if warp_idx == self.epilog_warp_id[0]:\n cute.arch.relinquish_tmem_alloc_permit(is_two_cta=use_2cta_instrs)\n epilog_threads = self.threads_per_warp * len(self.epilog_warp_id)\n cute.arch.barrier(\n barrier_id=self.epilog_sync_bar_id, number_of_threads=epilog_threads\n )\n if warp_idx == self.epilog_warp_id[0]:\n if use_2cta_instrs:\n cute.arch.mbarrier_arrive(\n tmem_dealloc_mbar_ptr, cta_rank_in_cluster ^ 1\n )\n cute.arch.mbarrier_wait(tmem_dealloc_mbar_ptr, 0)\n cute.arch.dealloc_tmem(\n acc_tmem_ptr, self.num_tmem_alloc_cols, is_two_cta=use_2cta_instrs\n )\n #\n # Wait for C store complete\n #\n if cutlass.const_expr(tile_sched_params.dst_signals is not None):\n # The original c_pipeline.producer_tail()\n # := PipelineTmaStore.producer_tail()\n # := TmaStoreFence.tail()\n # := cute.arch.cp_async_bulk_wait_group(0, read=True)\n cute.arch.cp_async_bulk_wait_group(\n 0,\n # Change `read` from True to False to also wait writes\n read=False,\n )\n\n lane_id = tidx % 32\n if warp_idx == self.epilog_warp_id[0] and lane_id == 0:\n while dsm_pending_idx < num_experts:\n atomic_add_release_global(\n tile_sched_params.dst_signals.toint()\n + sizeof_i32 * dsm_pending_idx,\n value=1,\n )\n dsm_pending_idx += 1\n\n else:\n c_pipeline.producer_tail()\n\n def mainloop_s2t_copy_and_partition(\n self,\n sSF: cute.Tensor,\n tSF: cute.Tensor,\n ) -> Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]:\n \"\"\"\n Make tiledCopy for smem to tmem load for scale factor tensor, then use it to partition smem memory (source) and tensor memory (destination).\n\n :param sSF: The scale factor tensor in smem\n :type sSF: cute.Tensor\n :param tSF: The scale factor tensor in tmem\n :type tSF: cute.Tensor\n\n :return: A tuple containing (tiled_copy_s2t, tCsSF_compact_s2t, tCtSF_compact_s2t) where:\n - tiled_copy_s2t: The tiled copy operation for smem to tmem load for scale factor tensor(s2t)\n - tCsSF_compact_s2t: The partitioned scale factor tensor in smem\n - tSF_compact_s2t: The partitioned scale factor tensor in tmem\n :rtype: Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]\n \"\"\"\n # (MMA, MMA_MN, MMA_K, STAGE)\n tCsSF_compact = cute.filter_zeros(sSF)\n # (MMA, MMA_MN, MMA_K)\n tCtSF_compact = cute.filter_zeros(tSF)\n\n # Make S2T CopyAtom and tiledCopy\n copy_atom_s2t = cute.make_copy_atom(\n tcgen05.Cp4x32x128bOp(self.cta_group),\n self.sf_dtype,\n )\n tiled_copy_s2t = tcgen05.make_s2t_copy(copy_atom_s2t, tCtSF_compact)\n thr_copy_s2t = tiled_copy_s2t.get_slice(0)\n\n # ((ATOM_V, REST_V), Rest_Tiler, MMA_MN, MMA_K, STAGE)\n tCsSF_compact_s2t_ = thr_copy_s2t.partition_S(tCsSF_compact)\n # ((ATOM_V, REST_V), Rest_Tiler, MMA_MN, MMA_K, STAGE)\n tCsSF_compact_s2t = tcgen05.get_s2t_smem_desc_tensor(\n tiled_copy_s2t, tCsSF_compact_s2t_\n )\n # ((ATOM_V, REST_V), Rest_Tiler, MMA_MN, MMA_K)\n tCtSF_compact_s2t = thr_copy_s2t.partition_D(tCtSF_compact)\n\n return tiled_copy_s2t, tCsSF_compact_s2t, tCtSF_compact_s2t\n\n def epilog_tmem_copy_and_partition(\n self,\n tidx: cutlass.Int32,\n tAcc: cute.Tensor,\n gC_mnl: cute.Tensor,\n epi_tile: cute.Tile,\n use_2cta_instrs: Union[cutlass.Boolean, bool],\n ) -> Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]:\n \"\"\"\n Make tiledCopy for tensor memory load, then use it to partition tensor memory (source) and register array (destination).\n\n :param tidx: The thread index in epilogue warp groups\n :type tidx: cutlass.Int32\n :param tAcc: The accumulator tensor to be copied and partitioned\n :type tAcc: cute.Tensor\n :param gC_mnl: The global tensor C\n :type gC_mnl: cute.Tensor\n :param epi_tile: The epilogue tiler\n :type epi_tile: cute.Tile\n :param use_2cta_instrs: Whether use_2cta_instrs is enabled\n :type use_2cta_instrs: bool\n\n :return: A tuple containing (tiled_copy_t2r, tTR_tAcc, tTR_rAcc) where:\n - tiled_copy_t2r: The tiled copy operation for tmem to register copy(t2r)\n - tTR_tAcc: The partitioned accumulator tensor\n - tTR_rAcc: The accumulated tensor in register used to hold t2r results\n :rtype: Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]\n \"\"\"\n # Make tiledCopy for tensor memory load\n copy_atom_t2r = sm100_utils.get_tmem_load_op(\n self.cta_tile_shape_mnk,\n self.c_layout,\n self.c_dtype,\n self.acc_dtype,\n epi_tile,\n use_2cta_instrs,\n )\n # (EPI_TILE_M, EPI_TILE_N, EPI_M, EPI_N, STAGE)\n tAcc_epi = cute.flat_divide(\n tAcc[((None, None), 0, 0, None)],\n epi_tile,\n )\n # (EPI_TILE_M, EPI_TILE_N)\n tiled_copy_t2r = tcgen05.make_tmem_copy(\n copy_atom_t2r, tAcc_epi[(None, None, 0, 0, 0)]\n )\n\n thr_copy_t2r = tiled_copy_t2r.get_slice(tidx)\n # (T2R, T2R_M, T2R_N, EPI_M, EPI_M, STAGE)\n tTR_tAcc = thr_copy_t2r.partition_S(tAcc_epi)\n\n # (EPI_TILE_M, EPI_TILE_N, EPI_M, EPI_N, RestM, RestN, RestL)\n gC_mnl_epi = cute.flat_divide(\n gC_mnl[((None, None), 0, 0, None, None, None)], epi_tile\n )\n # (T2R, T2R_M, T2R_N, EPI_M, EPI_N, RestM, RestN, RestL)\n tTR_gC = thr_copy_t2r.partition_D(gC_mnl_epi)\n # (T2R, T2R_M, T2R_N)\n tTR_rAcc = cute.make_fragment(\n tTR_gC[(None, None, None, 0, 0, 0, 0, 0)].shape, self.acc_dtype\n )\n return tiled_copy_t2r, tTR_tAcc, tTR_rAcc\n\n def epilog_smem_copy_and_partition(\n self,\n tiled_copy_t2r: cute.TiledCopy,\n tTR_rC: cute.Tensor,\n tidx: cutlass.Int32,\n sC: cute.Tensor,\n ) -> Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]:\n \"\"\"\n Make tiledCopy for shared memory store, then use it to partition register array (source) and shared memory (destination).\n\n :param tiled_copy_t2r: The tiled copy operation for tmem to register copy(t2r)\n :type tiled_copy_t2r: cute.TiledCopy\n :param tTR_rC: The partitioned accumulator tensor\n :type tTR_rC: cute.Tensor\n :param tidx: The thread index in epilogue warp groups\n :type tidx: cutlass.Int32\n :param sC: The shared memory tensor to be copied and partitioned\n :type sC: cute.Tensor\n :type sepi: cute.Tensor\n\n :return: A tuple containing (tiled_copy_r2s, tRS_rC, tRS_sC) where:\n - tiled_copy_r2s: The tiled copy operation for register to smem copy(r2s)\n - tRS_rC: The partitioned tensor C (register source)\n - tRS_sC: The partitioned tensor C (smem destination)\n :rtype: Tuple[cute.TiledCopy, cute.Tensor, cute.Tensor]\n \"\"\"\n copy_atom_r2s = sm100_utils.get_smem_store_op(\n self.c_layout, self.c_dtype, self.acc_dtype, tiled_copy_t2r\n )\n tiled_copy_r2s = cute.make_tiled_copy_D(copy_atom_r2s, tiled_copy_t2r)\n # (R2S, R2S_M, R2S_N, PIPE_D)\n thr_copy_r2s = tiled_copy_r2s.get_slice(tidx)\n tRS_sC = thr_copy_r2s.partition_D(sC)\n # (R2S, R2S_M, R2S_N)\n tRS_rC = tiled_copy_r2s.retile(tTR_rC)\n return tiled_copy_r2s, tRS_rC, tRS_sC\n\n def epilog_gmem_copy_and_partition(\n self,\n tidx: cutlass.Int32,\n atom: Union[cute.CopyAtom, cute.TiledCopy],\n gC_mnl: cute.Tensor,\n epi_tile: cute.Tile,\n sC: cute.Tensor,\n ) -> Tuple[cute.CopyAtom, cute.Tensor, cute.Tensor]:\n \"\"\"Make tiledCopy for global memory store, then use it to:\n partition shared memory (source) and global memory (destination) for TMA store version.\n\n :param tidx: The thread index in epilogue warp groups\n :type tidx: cutlass.Int32\n :param atom: The copy_atom_c to be used for TMA store version, or tiled_copy_t2r for none TMA store version\n :type atom: cute.CopyAtom or cute.TiledCopy\n :param gC_mnl: The global tensor C\n :type gC_mnl: cute.Tensor\n :param epi_tile: The epilogue tiler\n :type epi_tile: cute.Tile\n :param sC: The shared memory tensor to be copied and partitioned\n :type sC: cute.Tensor\n\n :return: A tuple containing (tma_atom_c, bSG_sC, bSG_gC) where:\n - tma_atom_c: The TMA copy atom\n - bSG_sC: The partitioned shared memory tensor C\n - bSG_gC: The partitioned global tensor C\n :rtype: Tuple[cute.CopyAtom, cute.Tensor, cute.Tensor]\n \"\"\"\n # (EPI_TILE_M, EPI_TILE_N, EPI_M, EPI_N, RestM, RestN, RestL)\n gC_epi = cute.flat_divide(\n gC_mnl[((None, None), 0, 0, None, None, None)], epi_tile\n )\n\n tma_atom_c = atom\n sC_for_tma_partition = cute.group_modes(sC, 0, 2)\n gC_for_tma_partition = cute.group_modes(gC_epi, 0, 2)\n # ((ATOM_V, REST_V), EPI_M, EPI_N)\n # ((ATOM_V, REST_V), EPI_M, EPI_N, RestM, RestN, RestL)\n bSG_sC, bSG_gC = cpasync.tma_partition(\n tma_atom_c,\n 0,\n cute.make_layout(1),\n sC_for_tma_partition,\n gC_for_tma_partition,\n )\n return tma_atom_c, bSG_sC, bSG_gC\n\n @staticmethod\n def _compute_stages(\n tiled_mma: cute.TiledMma,\n mma_tiler_mnk: Tuple[int, int, int],\n a_dtype: Type[cutlass.Numeric],\n a_major_mode: tcgen05.OperandMajorMode,\n b_dtype: Type[cutlass.Numeric],\n b_major_mode: tcgen05.OperandMajorMode,\n epi_tile: cute.Tile,\n c_dtype: Type[cutlass.Numeric],\n c_layout: utils.LayoutEnum,\n sf_dtype: Type[cutlass.Numeric],\n sf_vec_size: int,\n smem_capacity: int,\n occupancy: int,\n ) -> Tuple[int, int, int]:\n \"\"\"Computes the number of stages for A/B/C operands based on heuristics.\n\n :param tiled_mma: The tiled MMA object defining the core computation.\n :type tiled_mma: cute.TiledMma\n :param mma_tiler_mnk: The shape (M, N, K) of the MMA tiler.\n :type mma_tiler_mnk: tuple[int, int, int]\n :param a_dtype: Data type of operand A.\n :type a_dtype: type[cutlass.Numeric]\n :param a_major_mode: Major mode of operand A.\n :type a_major_mode: tcgen05.OperandMajorMode\n :param b_dtype: Data type of operand B.\n :type b_dtype: type[cutlass.Numeric]\n :param b_major_mode: Major mode of operand B.\n :type b_major_mode: tcgen05.OperandMajorMode\n :param epi_tile: The epilogue tile shape.\n :type epi_tile: cute.Tile\n :param c_dtype: Data type of operand C (output).\n :type c_dtype: type[cutlass.Numeric]\n :param c_layout: Layout enum of operand C.\n :type c_layout: utils.LayoutEnum\n :param sf_dtype: Data type of Scale factor.\n :type sf_dtype: type[cutlass.Numeric]\n :param sf_vec_size: Scale factor vector size.\n :type sf_vec_size: int\n :param smem_capacity: Total available shared memory capacity in bytes.\n :type smem_capacity: int\n :param occupancy: Target number of CTAs per SM (occupancy).\n :type occupancy: int\n\n :return: A tuple containing the computed number of stages for:\n (ACC stages, A/B operand stages, C stages)\n :rtype: tuple[int, int, int]\n \"\"\"\n # ACC stages\n num_acc_stage = 1 if mma_tiler_mnk[1] == 256 else 2\n\n # Default C stages\n num_c_stage = 2\n\n # Calculate smem layout and size for one stage of A, B, SFA, SFB and C\n a_smem_layout_stage_one = sm100_utils.make_smem_layout_a(\n tiled_mma,\n mma_tiler_mnk,\n a_dtype,\n 1, # a tmp 1 stage is provided\n )\n b_smem_layout_staged_one = sm100_utils.make_smem_layout_b(\n tiled_mma,\n mma_tiler_mnk,\n b_dtype,\n 1, # a tmp 1 stage is provided\n )\n sfa_smem_layout_staged_one = blockscaled_utils.make_smem_layout_sfa(\n tiled_mma,\n mma_tiler_mnk,\n sf_vec_size,\n 1, # a tmp 1 stage is provided\n )\n sfb_smem_layout_staged_one = blockscaled_utils.make_smem_layout_sfb(\n tiled_mma,\n mma_tiler_mnk,\n sf_vec_size,\n 1, # a tmp 1 stage is provided\n )\n\n c_smem_layout_staged_one = sm100_utils.make_smem_layout_epi(\n c_dtype,\n c_layout,\n epi_tile,\n 1,\n )\n\n ab_bytes_per_stage = (\n cute.size_in_bytes(a_dtype, a_smem_layout_stage_one)\n + cute.size_in_bytes(b_dtype, b_smem_layout_staged_one)\n + cute.size_in_bytes(sf_dtype, sfa_smem_layout_staged_one)\n + cute.size_in_bytes(sf_dtype, sfb_smem_layout_staged_one)\n )\n mbar_helpers_bytes = 1024\n c_bytes_per_stage = cute.size_in_bytes(c_dtype, c_smem_layout_staged_one)\n c_bytes = c_bytes_per_stage * num_c_stage\n\n # Calculate A/B/SFA/SFB stages:\n # Start with total smem per CTA (capacity / occupancy)\n # Subtract reserved bytes and initial C stages bytes\n # Divide remaining by bytes needed per A/B/SFA/SFB stage\n num_ab_stage = (\n smem_capacity // occupancy - (mbar_helpers_bytes + c_bytes)\n ) // ab_bytes_per_stage\n\n # Refine epilogue stages:\n # Calculate remaining smem after allocating for A/B/SFA/SFB stages and reserved bytes\n # Add remaining unused smem to epilogue\n num_c_stage += (\n smem_capacity\n - occupancy * ab_bytes_per_stage * num_ab_stage\n - occupancy * (mbar_helpers_bytes + c_bytes)\n ) // (occupancy * c_bytes_per_stage)\n\n return num_acc_stage, num_ab_stage, num_c_stage\n\n @staticmethod\n def _compute_grid(\n masked_m_tensor: cute.Tensor,\n dst_signals: Optional[cute.Pointer],\n c: cute.Tensor,\n cta_tile_shape_mnk: Tuple[int, int, int],\n cluster_shape_mn: Tuple[int, int],\n max_active_clusters: cutlass.Constexpr,\n ) -> Tuple[MaskedSchedulerParams, Tuple[int, int, int]]:\n \"\"\"Use persistent tile scheduler to compute the grid size for the output tensor C.\n\n :param c: The output tensor C\n :type c: cute.Tensor\n :param cta_tile_shape_mnk: The shape (M, N, K) of the CTA tile.\n :type cta_tile_shape_mnk: tuple[int, int, int]\n :param cluster_shape_mn: Shape of each cluster in M, N dimensions.\n :type cluster_shape_mn: tuple[int, int]\n :param max_active_clusters: Maximum number of active clusters.\n :type max_active_clusters: cutlass.Constexpr\n\n :return: A tuple containing:\n - tile_sched_params: Parameters for the persistent tile scheduler.\n - grid: Grid shape for kernel launch.\n :rtype: Tuple[MaskedSchedulerParams, tuple[int, int, int]]\n \"\"\"\n c_tiler = cute.slice_(cta_tile_shape_mnk, (None, None, 0))\n cluster_shape_mnl = (*cluster_shape_mn, 1)\n\n tile_sched_params = MaskedSchedulerParams(\n masked_m_tensor, dst_signals, c, c_tiler, cluster_shape_mnl\n )\n grid = MaskedScheduler.get_grid_shape(tile_sched_params, max_active_clusters)\n\n return tile_sched_params, grid\n\n @staticmethod\n def is_valid_dtypes_and_scale_factor_vec_size(\n ab_dtype: Type[cutlass.Numeric],\n sf_dtype: Type[cutlass.Numeric],\n sf_vec_size: int,\n c_dtype: Type[cutlass.Numeric],\n ) -> bool:\n \"\"\"\n Check if the dtypes and sf_vec_size are valid combinations\n\n :param ab_dtype: The data type of the A and B operands\n :type ab_dtype: Type[cutlass.Numeric]\n :param sf_dtype: The data type of the scale factor\n :type sf_dtype: Type[cutlass.Numeric]\n :param sf_vec_size: The vector size of the scale factor\n :type sf_vec_size: int\n :param c_dtype: The data type of the output tensor\n :type c_dtype: Type[cutlass.Numeric]\n\n :return: True if the dtypes and sf_vec_size are valid, False otherwise\n :rtype: bool\n \"\"\"\n is_valid = True\n\n # Check valid ab_dtype\n if ab_dtype not in {\n cutlass.Float4E2M1FN,\n cutlass.Float8E5M2,\n cutlass.Float8E4M3FN,\n }:\n is_valid = False\n\n # Check valid sf_vec_size\n if sf_vec_size not in {16, 32}:\n is_valid = False\n\n # Check valid sf_dtype\n if sf_dtype not in {cutlass.Float8E8M0FNU, cutlass.Float8E4M3FN}:\n is_valid = False\n\n # Check valid sf_dtype and sf_vec_size combinations\n if sf_dtype == cutlass.Float8E4M3FN and sf_vec_size == 32:\n is_valid = False\n if ab_dtype in {cutlass.Float8E5M2, cutlass.Float8E4M3FN} and sf_vec_size == 16:\n is_valid = False\n\n # Check valid c_dtype\n if c_dtype not in {\n cutlass.Float32,\n cutlass.Float16,\n cutlass.BFloat16,\n cutlass.Float8E5M2,\n cutlass.Float8E4M3FN,\n }:\n is_valid = False\n\n return is_valid\n\n @staticmethod\n def is_valid_layouts(\n ab_dtype: Type[cutlass.Numeric],\n c_dtype: Type[cutlass.Numeric],\n a_major: str,\n b_major: str,\n c_major: str,\n ) -> bool:\n \"\"\"\n Check if the dtypes and sf_vec_size are valid combinations\n\n :param ab_dtype: The data type of the A and B operands\n :type ab_dtype: Type[cutlass.Numeric]\n :param c_dtype: The data type of the output tensor\n :type c_dtype: Type[cutlass.Numeric]\n :param a_major: The major dimension of the A tensor\n :type a_major: str\n :param b_major: The major dimension of the B tensor\n :type b_major: str\n :param c_major: The major dimension of the C tensor\n :type c_major: str\n\n :return: True if the layouts are valid, False otherwise\n :rtype: bool\n \"\"\"\n is_valid = True\n\n if ab_dtype is cutlass.Float4E2M1FN and not (a_major == \"k\" and b_major == \"k\"):\n is_valid = False\n return is_valid\n\n @staticmethod\n def is_valid_mma_tiler_and_cluster_shape(\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n ) -> bool:\n \"\"\"\n Check if the mma tiler and cluster shape are valid\n\n :param mma_tiler_mn: The (M, N) shape of the MMA instruction tiler\n :type mma_tiler_mn: Tuple[int, int]\n :param cluster_shape_mn: The (ClusterM, ClusterN) shape of the CTA cluster\n :type cluster_shape_mn: Tuple[int, int]\n\n :return: True if the mma tiler and cluster shape are valid, False otherwise\n :rtype: bool\n \"\"\"\n is_valid = True\n # Skip invalid mma tile shape\n if mma_tiler_mn[0] not in [128, 256]:\n is_valid = False\n if mma_tiler_mn[1] not in [128, 256]:\n is_valid = False\n # Skip illegal cluster shape\n if cluster_shape_mn[0] % (2 if mma_tiler_mn[0] == 256 else 1) != 0:\n is_valid = False\n # Skip invalid cluster shape\n is_power_of_2 = lambda x: x > 0 and (x & (x - 1)) == 0\n if (\n cluster_shape_mn[0] * cluster_shape_mn[1] > 16\n or cluster_shape_mn[0] <= 0\n or cluster_shape_mn[1] <= 0\n # Special cluster shape check for scale factor multicasts.\n # Due to limited size of scale factors, we can't multicast among more than 4 CTAs.\n or cluster_shape_mn[0] > 4\n or cluster_shape_mn[1] > 4\n or not is_power_of_2(cluster_shape_mn[0])\n or not is_power_of_2(cluster_shape_mn[1])\n ):\n is_valid = False\n return is_valid\n\n @staticmethod\n def is_valid_tensor_alignment(\n m: int,\n n: int,\n k: int,\n l: int,\n ab_dtype: Type[cutlass.Numeric],\n c_dtype: Type[cutlass.Numeric],\n a_major: str,\n b_major: str,\n c_major: str,\n ) -> bool:\n \"\"\"\n Check if the tensor alignment is valid\n\n :param m: The number of rows in the A tensor\n :type m: int\n :param n: The number of columns in the B tensor\n :type n: int\n :param k: The number of columns in the A tensor\n :type k: int\n :param l: The number of columns in the C tensor\n :type l: int\n :param ab_dtype: The data type of the A and B operands\n :type ab_dtype: Type[cutlass.Numeric]\n :param c_dtype: The data type of the output tensor\n :type c_dtype: Type[cutlass.Numeric]\n :param a_major: The major axis of the A tensor\n :type a_major: str\n :param b_major: The major axis of the B tensor\n :type b_major: str\n :param c_major: The major axis of the C tensor\n :type c_major: str\n\n :return: True if the problem shape is valid, False otherwise\n :rtype: bool\n \"\"\"\n is_valid = True\n\n def check_contigous_16B_alignment(dtype, is_mode0_major, tensor_shape):\n major_mode_idx = 0 if is_mode0_major else 1\n num_major_elements = tensor_shape[major_mode_idx]\n num_contiguous_elements = 16 * 8 // dtype.width\n return num_major_elements % num_contiguous_elements == 0\n\n if (\n not check_contigous_16B_alignment(ab_dtype, a_major == \"m\", (m, k, l))\n or not check_contigous_16B_alignment(ab_dtype, b_major == \"n\", (n, k, l))\n or not check_contigous_16B_alignment(c_dtype, c_major == \"m\", (m, n, l))\n ):\n is_valid = False\n return is_valid\n\n @staticmethod\n def can_implement(\n ab_dtype: Type[cutlass.Numeric],\n sf_dtype: Type[cutlass.Numeric],\n sf_vec_size: int,\n c_dtype: Type[cutlass.Numeric],\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n m: int,\n n: int,\n k: int,\n l: int,\n a_major: str,\n b_major: str,\n c_major: str,\n ) -> bool:\n \"\"\"\n Check if the gemm can be implemented\n\n :param ab_dtype: The data type of the A and B operands\n :type ab_dtype: Type[cutlass.Numeric]\n :param sf_dtype: The data type of the scale factor tensor\n :type sf_dtype: Type[cutlass.Numeric]\n :param sf_vec_size: The vector size\n :type sf_vec_size: int\n :param c_dtype: The data type of the output tensor\n :type c_dtype: Type[cutlass.Numeric]\n :param mma_tiler_mn: The (M, N) shape of the MMA instruction tiler\n :type mma_tiler_mn: Tuple[int, int]\n :param cluster_shape_mn: The (ClusterM, ClusterN) shape of the CTA cluster\n :type cluster_shape_mn: Tuple[int, int]\n :param m: The number of rows in the A tensor\n :type m: int\n :param n: The number of columns in the B tensor\n :type n: int\n :param k: The number of columns in the A tensor\n :type k: int\n :param l: The number of columns in the C tensor\n :type l: int\n :param a_major: The major axis of the A tensor\n :type a_major: str\n :param b_major: The major axis of the B tensor\n :type b_major: str\n :param c_major: The major axis of the C tensor\n :type c_major: str\n\n :return: True if the gemm can be implemented, False otherwise\n :rtype: bool\n \"\"\"\n can_implement = True\n # Skip unsupported types\n if not Sm100BlockScaledPersistentDenseGemmKernel.is_valid_dtypes_and_scale_factor_vec_size(\n ab_dtype, sf_dtype, sf_vec_size, c_dtype\n ):\n can_implement = False\n # Skip unsupported layouts\n if not Sm100BlockScaledPersistentDenseGemmKernel.is_valid_layouts(\n ab_dtype, c_dtype, a_major, b_major, c_major\n ):\n can_implement = False\n # Skip invalid mma tile shape and cluster shape\n if not Sm100BlockScaledPersistentDenseGemmKernel.is_valid_mma_tiler_and_cluster_shape(\n mma_tiler_mn, cluster_shape_mn\n ):\n can_implement = False\n # Skip illegal problem shape for load/store alignment\n if not Sm100BlockScaledPersistentDenseGemmKernel.is_valid_tensor_alignment(\n m, n, k, l, ab_dtype, c_dtype, a_major, b_major, c_major\n ):\n can_implement = False\n return can_implement\n\n\n@cute.jit\ndef cvt_sf_MKL_to_M32x4xrm_K4xrk_L(\n sf_ref_tensor: cute.Tensor,\n sf_mma_tensor: cute.Tensor,\n):\n \"\"\"Convert scale factor tensor from MKL layout to mma specification M(32x4xrest_m)xK(4xrest_k)xL layout\"\"\"\n # sf_mma_tensor has flatten shape (32, 4, rest_m, 4, rest_k, l)\n # group to ((32, 4, rest_m), (4, rest_k), l)\n sf_mma_tensor = cute.group_modes(sf_mma_tensor, 0, 3)\n sf_mma_tensor = cute.group_modes(sf_mma_tensor, 1, 3)\n for i in cutlass.range(cute.size(sf_ref_tensor)):\n mkl_coord = sf_ref_tensor.layout.get_hier_coord(i)\n sf_mma_tensor[mkl_coord] = sf_ref_tensor[mkl_coord]\n\n\n@cute.jit\ndef cvt_sf_MKL_to_M32x4xrm_K4xrk_L_mma_spec(\n sf_mma_tensor: cute.Tensor,\n):\n \"\"\"Convert scale factor tensor from MKL layout to mma specification M(32x4xrest_m)xK(4xrest_k)xL layout\"\"\"\n # sf_mma_tensor has flatten shape (32, 4, rest_m, 4, rest_k, l)\n # group to ((32, 4, rest_m), (4, rest_k), l)\n sf_mma_tensor = cute.group_modes(sf_mma_tensor, 0, 3)\n sf_mma_tensor = cute.group_modes(sf_mma_tensor, 1, 3)\n\n\n# Create scale factor tensor SFA/SFB\ndef create_scale_factor_tensor(l, mn, k, sf_vec_size, dtype, device):\n def ceil_div(a, b):\n return (a + b - 1) // b\n\n sf_k = ceil_div(k, sf_vec_size)\n ref_shape = (l, mn, sf_k)\n\n atom_m = (32, 4)\n atom_k = 4\n mma_shape = (\n l,\n ceil_div(mn, atom_m[0] * atom_m[1]),\n ceil_div(sf_k, atom_k),\n atom_m[0],\n atom_m[1],\n atom_k,\n )\n\n ref_permute_order = (1, 2, 0)\n mma_permute_order = (3, 4, 1, 5, 2, 0)\n\n # Create f32 ref torch tensor\n ref_f32_torch_tensor_cpu = cutlass_torch.create_and_permute_torch_tensor(\n ref_shape,\n torch.float32,\n permute_order=ref_permute_order,\n init_type=cutlass_torch.TensorInitType.RANDOM,\n init_config=cutlass_torch.RandomInitConfig(\n min_val=1,\n max_val=3,\n ),\n )\n\n # Create f32 cute torch tensor\n cute_f32_torch_tensor_cpu = cutlass_torch.create_and_permute_torch_tensor(\n mma_shape,\n torch.float32,\n permute_order=mma_permute_order,\n init_type=cutlass_torch.TensorInitType.RANDOM,\n init_config=cutlass_torch.RandomInitConfig(\n min_val=0,\n max_val=1,\n ),\n )\n\n # convert ref f32 tensor to cute f32 tensor\n cvt_sf_MKL_to_M32x4xrm_K4xrk_L(\n from_dlpack(ref_f32_torch_tensor_cpu),\n from_dlpack(cute_f32_torch_tensor_cpu),\n )\n cute_f32_torch_tensor = cute_f32_torch_tensor_cpu.to(device, non_blocking=True)\n\n # reshape makes memory contiguous\n ref_f32_torch_tensor_cpu = (\n ref_f32_torch_tensor_cpu.permute(2, 0, 1)\n .unsqueeze(-1)\n .expand(l, mn, sf_k, sf_vec_size)\n .reshape(l, mn, sf_k * sf_vec_size)\n .permute(*ref_permute_order)\n )\n # prune to mkl for reference check.\n ref_f32_torch_tensor_cpu = ref_f32_torch_tensor_cpu[:, :k, :]\n ref_f32_torch_tensor = ref_f32_torch_tensor_cpu.to(device, non_blocking=True)\n\n # Create dtype cute torch tensor (cpu)\n cute_tensor, cute_torch_tensor = cutlass_torch.cute_tensor_like(\n cute_f32_torch_tensor_cpu,\n dtype,\n is_dynamic_layout=True,\n assumed_align=16,\n )\n\n # Convert f32 cute tensor to dtype cute tensor\n cute_tensor = cutlass_torch.convert_cute_tensor(\n cute_f32_torch_tensor,\n cute_tensor,\n dtype,\n is_dynamic_layout=True,\n )\n return ref_f32_torch_tensor, cute_tensor, cute_torch_tensor\n\n\nclass MaskedBatchedMatmulCuteDSL:\n def __init__(\n self,\n m: int,\n n: int,\n k: int,\n l: int,\n a_major: str,\n b_major: str,\n c_major: str,\n ab_dtype: torch.dtype,\n sf_dtype: torch.dtype,\n c_dtype: torch.dtype,\n alpha_dtype: torch.dtype,\n sf_vec_size: int,\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n sm_count: int,\n sm_version: str,\n ):\n self._m = m\n self._n = n\n self._k = k\n self._l = l\n self._a_major = a_major\n self._b_major = b_major\n self._c_major = c_major\n self._ab_dtype = ab_dtype\n self._sf_dtype = sf_dtype\n self._c_dtype = c_dtype\n self._alpha_dtype = alpha_dtype\n self._sf_vec_size = sf_vec_size\n self._mma_tiler_mn = mma_tiler_mn\n self._cluster_shape_mn = cluster_shape_mn\n\n if not Sm100BlockScaledPersistentDenseGemmKernel.can_implement(\n ab_dtype,\n sf_dtype,\n sf_vec_size,\n c_dtype,\n mma_tiler_mn,\n cluster_shape_mn,\n m,\n n,\n k,\n l,\n a_major,\n b_major,\n c_major,\n ):\n raise TypeError(\n f\"MaskedBatchedMatmulCuteDSL: Unsupported with {ab_dtype}, {sf_dtype}, {sf_vec_size}, {c_dtype}, {mma_tiler_mn}, {cluster_shape_mn}, {m}, {n}, {k}, {l}, {a_major}, {b_major}, {c_major}\"\n )\n\n # Compute max active clusters on current device\n hardware_info = cutlass.utils.HardwareInfo()\n self._max_active_clusters = min(\n hardware_info.get_max_active_clusters(\n self._cluster_shape_mn[0] * self._cluster_shape_mn[1]\n ),\n sm_count,\n )\n self._sm_version = sm_version\n\n @cute.jit\n def __call__(\n self,\n a_ptr: cute.Pointer,\n b_ptr: cute.Pointer,\n sfa_ptr: cute.Pointer,\n sfb_ptr: cute.Pointer,\n c_ptr: cute.Pointer,\n masked_m_ptr: cute.Pointer,\n dst_signals_ptr: Optional[cute.Pointer],\n alpha_ptr: cute.Pointer,\n current_stream: cuda.CUstream,\n ):\n a_tensor = cute.make_tensor(\n a_ptr,\n layout=cute.make_ordered_layout(\n (self._m, self._k, self._l),\n order=(0, 1, 2) if self._a_major == \"m\" else (1, 0, 2),\n ),\n )\n b_tensor = cute.make_tensor(\n b_ptr,\n layout=cute.make_ordered_layout(\n (self._n, self._k, self._l),\n order=(0, 1, 2) if self._b_major == \"n\" else (1, 0, 2),\n ),\n )\n c_tensor = cute.make_tensor(\n c_ptr,\n layout=cute.make_ordered_layout(\n (self._m, self._n, self._l),\n order=(0, 1, 2) if self._c_major == \"m\" else (1, 0, 2),\n ),\n )\n\n # calculate sf_tensor shape and order\n def ceil_div(a, b):\n return (a + b - 1) // b\n\n sf_k = ceil_div(self._k, self._sf_vec_size)\n\n atom_m = (32, 4)\n atom_k = 4\n mma_shape_a = (\n self._l,\n ceil_div(self._m, atom_m[0] * atom_m[1]),\n ceil_div(sf_k, atom_k),\n atom_m[0],\n atom_m[1],\n atom_k,\n )\n mma_shape_b = (\n self._l,\n ceil_div(self._n, atom_m[0] * atom_m[1]),\n ceil_div(sf_k, atom_k),\n atom_m[0],\n atom_m[1],\n atom_k,\n )\n mma_permute_order = (3, 4, 1, 5, 2, 0)\n\n sfa_tensor = cute.make_tensor(\n sfa_ptr,\n layout=cute.make_ordered_layout(\n mma_shape_a,\n order=mma_permute_order,\n ),\n )\n sfb_tensor = cute.make_tensor(\n sfb_ptr,\n layout=cute.make_ordered_layout(\n mma_shape_b,\n order=mma_permute_order,\n ),\n )\n cvt_sf_MKL_to_M32x4xrm_K4xrk_L_mma_spec(sfa_tensor)\n cvt_sf_MKL_to_M32x4xrm_K4xrk_L_mma_spec(sfb_tensor)\n\n masked_m_tensor = cute.make_tensor(\n masked_m_ptr,\n layout=cute.make_ordered_layout((self._l,), order=(0,)),\n )\n\n # Use const_expr for compile-time conditional\n alpha_tensor = (\n cute.make_tensor(\n alpha_ptr,\n layout=cute.make_ordered_layout((self._l,), order=(0,)),\n )\n if cutlass.const_expr(alpha_ptr is not None)\n else None\n )\n\n Sm100BlockScaledPersistentDenseGemmKernel(\n sf_vec_size=self._sf_vec_size,\n mma_tiler_mn=self._mma_tiler_mn,\n cluster_shape_mn=self._cluster_shape_mn,\n sm_version=self._sm_version,\n )(\n a_tensor,\n b_tensor,\n sfa_tensor,\n sfb_tensor,\n c_tensor,\n masked_m_tensor,\n dst_signals_ptr,\n alpha_tensor,\n self._max_active_clusters,\n current_stream,\n )\n\n\n@functools.cache\ndef get_cute_dsl_compiled_masked_gemm_kernel(\n m: int,\n n: int,\n k: int,\n l: int,\n a_major: str,\n b_major: str,\n c_major: str,\n ab_dtype: Type[cutlass.Numeric],\n sf_dtype: Type[cutlass.Numeric],\n c_dtype: Type[cutlass.Numeric],\n alpha_dtype: Optional[Type[cutlass.Numeric]],\n sf_vec_size: int,\n mma_tiler_mn: Tuple[int, int],\n cluster_shape_mn: Tuple[int, int],\n sm_count: int,\n sm_version: str,\n enable_dst_signals: bool,\n) -> Callable:\n def get_cute_pointers(\n input_tensors: Optional[List[torch.tensor]],\n ) -> List[cute.Pointer]:\n if input_tensors is None:\n (\n a_data_ptr,\n b_data_ptr,\n sfa_data_ptr,\n sfb_data_ptr,\n c_data_ptr,\n masked_m_data_ptr,\n dst_signals_data_ptr,\n alpha_data_ptr,\n ) = [16 for _ in range(8)]\n\n if not enable_dst_signals:\n dst_signals_data_ptr = None\n\n else:\n (\n a_tensor_gpu,\n b_tensor_gpu,\n sfa_tensor_gpu,\n sfb_tensor_gpu,\n c_tensor_gpu,\n masked_m_tensor_gpu,\n dst_signals_tensor_gpu,\n alpha_tensor_gpu,\n ) = input_tensors\n\n assert enable_dst_signals == (dst_signals_tensor_gpu is not None)\n\n (\n a_data_ptr,\n b_data_ptr,\n sfa_data_ptr,\n sfb_data_ptr,\n c_data_ptr,\n masked_m_data_ptr,\n dst_signals_data_ptr,\n alpha_data_ptr,\n ) = (\n a_tensor_gpu.data_ptr(),\n b_tensor_gpu.data_ptr(),\n sfa_tensor_gpu.data_ptr(),\n sfb_tensor_gpu.data_ptr(),\n c_tensor_gpu.data_ptr(),\n masked_m_tensor_gpu.data_ptr(),\n dst_signals_tensor_gpu.data_ptr()\n if dst_signals_tensor_gpu is not None\n else None,\n alpha_tensor_gpu.data_ptr() if alpha_tensor_gpu is not None else None,\n )\n\n a_ptr = make_ptr(\n ab_dtype,\n a_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n b_ptr = make_ptr(\n ab_dtype,\n b_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n sfa_ptr = make_ptr(\n sf_dtype,\n sfa_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n sfb_ptr = make_ptr(\n sf_dtype,\n sfb_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n c_ptr = make_ptr(\n c_dtype,\n c_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n masked_m_ptr = make_ptr(\n cutlass.Int32,\n masked_m_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n dst_signals_ptr = (\n make_ptr(\n cutlass.Uint32,\n dst_signals_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n if dst_signals_data_ptr is not None\n else None\n )\n alpha_ptr = (\n make_ptr(\n alpha_dtype,\n alpha_data_ptr,\n cute.AddressSpace.gmem,\n assumed_align=16,\n )\n if alpha_data_ptr is not None and alpha_dtype is not None\n else None\n )\n\n return [\n a_ptr,\n b_ptr,\n sfa_ptr,\n sfb_ptr,\n c_ptr,\n masked_m_ptr,\n dst_signals_ptr,\n alpha_ptr,\n ]\n\n kernel = cute.compile(\n MaskedBatchedMatmulCuteDSL(\n m=m,\n n=n,\n k=k,\n l=l,\n a_major=a_major,\n b_major=b_major,\n c_major=c_major,\n ab_dtype=ab_dtype,\n sf_dtype=sf_dtype,\n c_dtype=c_dtype,\n alpha_dtype=alpha_dtype,\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n cluster_shape_mn=cluster_shape_mn,\n sm_count=sm_count,\n sm_version=sm_version,\n ),\n *get_cute_pointers(None),\n cutlass_torch.current_stream(),\n )\n\n def tensor_api(\n a_tensor_gpu: torch.Tensor,\n b_tensor_gpu: torch.Tensor,\n sfa_tensor_gpu: torch.Tensor,\n sfb_tensor_gpu: torch.Tensor,\n masked_m_tensor_gpu: torch.Tensor,\n dst_signals_tensor_gpu: torch.Tensor,\n c_tensor_gpu: Optional[torch.Tensor] = None,\n alpha_tensor_gpu: Optional[torch.Tensor] = None,\n ):\n if c_tensor_gpu is None:\n # fp4 gemm output is not supported\n c_tensor_gpu = torch.empty(\n (l, m, n),\n dtype=cutlass_to_torch_dtype(c_dtype),\n device=\"cuda\",\n )\n\n # fp4 or fp8 torch tensor to cute tensor\n current_stream = cutlass_torch.current_stream()\n\n nonlocal kernel\n kernel(\n *get_cute_pointers(\n [\n a_tensor_gpu,\n b_tensor_gpu,\n sfa_tensor_gpu,\n sfb_tensor_gpu,\n c_tensor_gpu,\n masked_m_tensor_gpu,\n dst_signals_tensor_gpu,\n alpha_tensor_gpu,\n ]\n ),\n current_stream,\n )\n\n return c_tensor_gpu\n\n return tensor_api\n\n\n@flashinfer_api\ndef grouped_gemm_nt_masked(\n lhs: Tuple[torch.Tensor, torch.Tensor],\n rhs: Tuple[torch.Tensor, torch.Tensor],\n out: torch.Tensor,\n masked_m: torch.Tensor,\n *,\n ab_dtype: str,\n sf_dtype: str,\n c_dtype: str,\n sf_vec_size: int,\n dst_signals: Optional[torch.Tensor] = None,\n sm_count: Optional[int] = None,\n **kwargs,\n):\n \"\"\"\n Executes a masked, batched matrix multiplication (GEMM) with scale factors and optional alpha scaling at output.\n\n Args:\n lhs (Tuple[torch.Tensor, torch.Tensor]): Tuple containing the left-hand side input tensor (A) and its scale factor tensor (SFA).\n - A should be in (m, k, l) order, but physically (l, m, k). For fp4 tensor with 8-bit storage, we expect the shape to be (m, k/2, l).\n - SFA should be in (m32, m4, rm, k4, rk, l) order, but physically (l, rm, rk, m32, m4, k4)\n rhs (Tuple[torch.Tensor, torch.Tensor]): Tuple containing the right-hand side input tensor (B) and its scale factor tensor (SFB).\n - B should be in (n, k, l) order, but physically (l, n, k). For fp4 tensor with 8-bit storage, we expect the shape to be (n, k/2, l).\n - SFB should be in (n32, n4, rn, k4, rk, l) order, but physically (l, rn, rk, n32, n4, k4)\n out (torch.Tensor): Output tensor to store the result, with shape (l, m, n).\n masked_m (torch.Tensor): 1D tensor of shape (l,) specifying the valid row count for each batch (used for masking).\n ab_dtype (str): Data type for A and B matrices. Supported: \"float4_e2m1fn\", \"float8_e4m3fn\", \"float8_e5m2\".\n sf_dtype (str): Data type for scale factors. Supported: \"float8_e8m0fnu\", \"float8_e4m3fn\".\n c_dtype (str): Data type for output matrix C. Supported: \"float16\", \"bfloat16\", \"float32\", \"float8_e4m3fn\", \"float8_e5m2\".\n sf_vec_size (int): Vector size for scale factors. Typically 16 or 32.\n sm_count (int, optional): Number of SMs to use. Default: max available SMs under the CTA configuration.\n mma_tiler_mn (Tuple[int, int], optional): Shape of the MMA tiler (M, N). Default: (128, 128).\n cluster_shape_mn (Tuple[int, int], optional): Shape of the CTA cluster (ClusterM, ClusterN). Default: (1, 1).\n alpha_dtype (str, optional): Data type for alpha scaling factors.\n alpha (torch.Tensor, optional): Optional 1D tensor of shape (l,) containing per-batch scaling factors. Perform per-batch scaling out = alpha * out.\n\n Notes:\n - Legends of the input tensors:\n * `l` is the batch size, `m/n` is the number of rows, and `k` is the number of columns.\n * `m/n32`, `m/n4`, `k4` are constant values 32, 4, 4 respectively.\n * `m32 * m4 * rm` should be same as `M`, which is `m` padded up to the nearest multiple of 128.\n * `n32 * n4 * rn` should be same as `N`, which is `n` padded up to the nearest multiple of 128.\n * `k4 * rk` should be same as `K`, which is `k / sf_vec_size` padded up to the nearest multiple of 4.\n - The function applies masking per batch using masked_m.\n - If alpha is provided, each batch output is multiplied by its corresponding alpha value. out = alpha * (A @ B).\n - The result is written to c_tensor.\n \"\"\"\n\n a_torch, sfa_torch = lhs\n b_torch, sfb_torch = rhs\n c_torch = out\n\n m, k, l = a_torch.shape\n n, _, _ = b_torch.shape\n\n if ab_dtype == \"float4_e2m1fn\":\n # todo(yingyi): update mnk based on a_major and b_major, and support more major.\n # Note: only support deepgemm-like shape for now\n k = k * 2\n\n mma_tiler_mn = kwargs.pop(\"mma_tiler_mn\", (128, 128))\n cluster_shape_mn = kwargs.pop(\"cluster_shape_mn\", (1, 1))\n if sm_count is None:\n sm_count = get_num_sm(a_torch.device)\n\n alpha = kwargs.pop(\"alpha\", None)\n alpha_dtype = kwargs.pop(\"alpha_dtype\", None)\n\n assert len(kwargs) == 0, f\"Unsupported kwargs: {kwargs}\"\n\n major, minor = get_compute_capability(a_torch.device)\n if major == 11 and minor == 0:\n raise ValueError(\"SM110 is not supported for cute-dsl backend.\")\n\n return get_cute_dsl_compiled_masked_gemm_kernel(\n m=m,\n n=n,\n k=k,\n l=l,\n a_major=\"k\",\n b_major=\"k\",\n c_major=\"n\",\n ab_dtype=get_cutlass_dtype(ab_dtype),\n sf_dtype=get_cutlass_dtype(sf_dtype),\n c_dtype=get_cutlass_dtype(c_dtype),\n alpha_dtype=None if alpha is None else get_cutlass_dtype(alpha_dtype),\n sf_vec_size=sf_vec_size,\n mma_tiler_mn=mma_tiler_mn,\n cluster_shape_mn=cluster_shape_mn,\n sm_count=sm_count,\n sm_version=f\"sm_{major}{minor}\",\n enable_dst_signals=dst_signals is not None,\n )(\n a_tensor_gpu=a_torch,\n b_tensor_gpu=b_torch,\n sfa_tensor_gpu=sfa_torch,\n sfb_tensor_gpu=sfb_torch,\n c_tensor_gpu=c_torch,\n masked_m_tensor_gpu=masked_m,\n dst_signals_tensor_gpu=dst_signals,\n alpha_tensor_gpu=alpha,\n )\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\ncuteDSL fp4 moe from TRTLLM with fusion. issue #2259\nThe collective fusion performance improvement collected from TRTLLM [PR 8880](https://github.com/NVIDIA/TensorRT-LLM/pull/8880), [PR 9288](https://github.com/NVIDIA/TensorRT-LLM/pull/9288), [PR 9618](https://github.com/NVIDIA/TensorRT-LLM/pull/9618),.\n\nIntroducing two new API for moe\n`cute_dsl_fused_moe_nvfp4`, `CuteDslMoEWrapper`. \nThe two API are functionally equivalent. The `cute_dsl_fused_moe_nvfp4` function could run the operation directly, while the wrapper API splits tensor setup and execution to better support cuda graph. Using wrapper API is recommended.\n\nThe PR also introduces autotune functionality for this function.\n\nPerformance data:\n```\n$ python benchmarks/bench_moe_deepseek.py --num-tokens 1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384\n====================================================================================================\nDeepSeek-V3 MoE Benchmark: CuteDSL vs CUTLASS vs TRTLLM (EP=1)\n====================================================================================================\nModel: hidden=7168, intermediate=2048, experts=256, top_k=8\nEP Config: 256 local experts (simulating 1-way parallelism)\nCUDA Graph: enabled, CUPTI: enabled\n----------------------------------------------------------------------------------------------------\nTokens | CuteDSL | CUTLASS | TRTLLM | Speedup (CuteDSL/X) | Winner\n | ms TFLOPS | ms TFLOPS | ms TFLOPS | CUTLASS TRTLLM |\n----------------------------------------------------------------------------------------------------\n 1 | 0.064 10.9 | 0.098 7.2 | 0.053 13.2 | 1.53x 0.83x | TRTLLM\n 2 | 0.077 18.2 | 0.109 13.0 | 0.064 21.9 | 1.40x 0.83x | TRTLLM\n 4 | 0.097 28.9 | 0.131 21.5 | 0.086 32.7 | 1.35x 0.88x | TRTLLM\n 8 | 0.098 57.5 | 0.133 42.4 | 0.092 61.4 | 1.36x 0.94x | TRTLLM\n 16 | 0.102 110.3 | 0.138 82.0 | 0.104 108.5 | 1.35x 1.02x | CuteDSL\n 32 | 0.115 196.3 | 0.153 146.9 | 0.138 163.4 | 1.34x 1.20x | CuteDSL\n 64 | 0.123 365.7 | 0.168 269.0 | 0.154 292.3 | 1.36x 1.25x | CuteDSL\n 128 | 0.134 674.3 | 0.217 416.0 | 0.174 519.4 | 1.62x 1.30x | CuteDSL\n 256 | 0.144 1252.3 | 0.250 723.0 | 0.220 821.3 | 1.73x 1.52x | CuteDSL\n 512 | 0.200 1802.3 | 0.336 1073.4 | 0.271 1331.9 | 1.68x 1.35x | CuteDSL\n 1024 | 0.286 2520.1 | 0.480 1501.8 | 0.570 1265.7 | 1.68x 1.99x | CuteDSL\n 2048 | 0.469 3073.8 | 0.722 1998.8 | 0.542 2660.6 | 1.54x 1.16x | CuteDSL\n 4096 | 0.852 3387.2 | 1.274 2266.0 | 0.845 3417.2 | 1.49x 0.99x | TRTLLM\n 8192 | 1.676 3444.7 | 2.364 2441.4 | 1.590 3630.7 | 1.41x 0.95x | TRTLLM\n 16384 | 3.290 3509.3 | 4.639 2488.8 | 3.383 3412.5 | 1.41x 1.03x | CuteDSL\n----------------------------------------------------------------------------------------------------\n\n$ python benchmarks/bench_moe_deepseek.py --num-tokens 1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384 --ep 16\n====================================================================================================\nDeepSeek-V3 MoE Benchmark: CuteDSL vs CUTLASS vs TRTLLM (EP=16)\n====================================================================================================\nModel: hidden=7168, intermediate=2048, experts=256, top_k=8\nEP Config: 16 local experts (simulating 16-way parallelism)\nCUDA Graph: enabled, CUPTI: enabled\n----------------------------------------------------------------------------------------------------\nTokens | CuteDSL | CUTLASS | TRTLLM | Speedup (CuteDSL/X) | Winner\n | ms TFLOPS | ms TFLOPS | ms TFLOPS | CUTLASS TRTLLM |\n----------------------------------------------------------------------------------------------------\n 1 | 0.021 2.1 | 0.024 1.8 | 0.018 2.5 | 1.16x 0.85x | TRTLLM\n 2 | 0.020 4.3 | 0.023 3.8 | 0.018 4.8 | 1.13x 0.90x | TRTLLM\n 4 | 0.020 8.6 | 0.024 7.4 | 0.019 9.2 | 1.16x 0.93x | TRTLLM\n 8 | 0.020 17.5 | 0.023 15.4 | 0.020 17.7 | 1.14x 0.99x | TRTLLM\n 16 | 0.021 33.9 | 0.024 29.9 | 0.022 32.8 | 1.13x 1.03x | CuteDSL\n 32 | 0.020 69.4 | 0.024 59.8 | 0.025 57.3 | 1.16x 1.21x | CuteDSL\n 64 | 0.022 129.2 | 0.024 118.7 | 0.025 112.1 | 1.09x 1.15x | CuteDSL\n 128 | 0.021 267.7 | 0.024 236.9 | 0.026 216.7 | 1.13x 1.24x | CuteDSL\n 256 | 0.023 487.3 | 0.025 456.4 | 0.027 411.6 | 1.07x 1.18x | CuteDSL\n 512 | 0.025 917.5 | 0.031 731.0 | 0.030 753.2 | 1.26x 1.22x | CuteDSL\n 1024 | 0.028 1638.6 | 0.036 1243.9 | 0.040 1137.0 | 1.32x 1.44x | CuteDSL\n 2048 | 0.036 2494.3 | 0.045 1988.4 | 0.061 1481.9 | 1.25x 1.68x | CuteDSL\n 4096 | 0.050 3597.4 | 0.061 2934.5 | 0.101 1794.7 | 1.23x 2.00x | CuteDSL\n 8192 | 0.103 3490.5 | 0.150 2409.6 | 0.209 1723.1 | 1.45x 2.03x | CuteDSL\n 16384 | 0.140 5160.4 | 0.198 3638.0 | 0.364 1980.6 | 1.42x 2.61x | CuteDSL\n----------------------------------------------------------------------------------------------------\n\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [ ] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [ ] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [ ] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n * Added comprehensive Mixture-of-Experts (MoE) support with FP4 quantization for Blackwell GPUs.\n * Introduced multi-precision MoE kernels supporting FP16, BF16, FP8, and FP4 formats.\n * Added CUDA graph-compatible MoE APIs for improved performance and flexibility.\n * Implemented automatic kernel tuning for MoE operations.\n * Added expert parallelism support for distributed MoE inference.\n\n* **Documentation**\n * Added extensive test suite validating MoE functionality across precision formats and configurations.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.098, \"optimized\": 0.064, \"stated_speedup\": 1.53, \"speedup\": 1.5312}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.053, \"optimized\": 0.064, \"stated_speedup\": 0.83, \"speedup\": 0.8281}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.109, \"optimized\": 0.077, \"stated_speedup\": 1.4, \"speedup\": 1.4156}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 2, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.064, \"optimized\": 0.077, \"stated_speedup\": 0.83, \"speedup\": 0.8312}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 4, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.131, \"optimized\": 0.097, \"stated_speedup\": 1.35, \"speedup\": 1.3505}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 4, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.086, \"optimized\": 0.097, \"stated_speedup\": 0.88, \"speedup\": 0.8866}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.133, \"optimized\": 0.098, \"stated_speedup\": 1.36, \"speedup\": 1.3571}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.092, \"optimized\": 0.098, \"stated_speedup\": 0.94, \"speedup\": 0.9388}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek-V3\", \"shape\": null, \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.138, \"optimized\": 0.102, \"stated_speedup\": 1.35, \"speedup\": 1.3529}, {\"scope\": \"kernel\", \"hardware\": null, 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2.6}]"},"kernel_speedup":{"kind":"number","value":1.245,"string":"1.245"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1182,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"57ef44b9d7ada00cb50ca26310f9c3a3bfbc0dd2"},"date":{"kind":"string","value":"2026-02-06T14:55:45+08:00"},"pr_number":{"kind":"number","value":2460,"string":"2,460"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2460"},"title":{"kind":"string","value":"perf: add fp4 GEMM tile configs and streamK scheduler for SM120 (#2460)"},"message":{"kind":"string","value":"perf: add fp4 GEMM tile configs and streamK scheduler for SM120 (#2460)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nAdd SM120 FP4 GEMM tile configs and enable streamK scheduler for configs\nthat can be selected by autotuner.\nTake the problem size m=32, n=5120, k=25600 as an example. After adding\nthese configs, the latency of mm_fp4 kernel reduced from 0.124ms to\n0.069ms on RTX PRO 6000.\n\n```\n[PERF] cutlass_autotun:: median time 0.124 ms; std 0.000 ms; achieved tflops 67.751 TFLOPs/sec; achieved tb_per_sec 0.535 TB/sec\n[PERF] cutlass_autotun:: median time 0.069 ms; std 0.000 ms; achieved tflops 121.902 TFLOPs/sec; achieved tb_per_sec 0.963 TB/sec\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n* Added StreamK scheduler option for SM120 FP4 GEMM operations,\nalongside the existing DP scheduler.\n* Expanded SM120 FP4 GEMM tile configurations with two additional\noptions (128×128×256 and 256×128×128).\n* Extended configuration generation to support all tile shapes with both\nschedulers for improved optimization flexibility.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"include/flashinfer/gemm/cutlass_gemm_configs.h"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n#define FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n\n#include <cassert>\n#include <iostream>\n#include <sstream>\n#include <string>\n\n#include \"cute/tensor.hpp\"\n\nnamespace flashinfer {\nnamespace gemm {\n\n// Note: The shapes are in the format MxNxK. The K shape of the runtime config MUST match the K\n// shape\n// in the kernel layout details when doing weight only quantization.\nenum class CutlassTileConfig {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n // SiMT config\n CtaShape128x128x8_WarpShape64x64x8,\n\n // TensorCore configs CTA_N = 128, CTA_K = 64\n // Warp configs for M=16\n CtaShape16x128x64_WarpShape16x32x64,\n // Warp configs for M=32\n CtaShape32x128x64_WarpShape32x32x64,\n\n // Warp configs for M=64\n CtaShape64x128x64_WarpShape32x64x64,\n CtaShape64x64x128_WarpShape32x64x64,\n CtaShape64x128x64_WarpShape64x32x64,\n\n // Warp configs for M=128\n CtaShape128x64x64_WarpShape64x32x64,\n CtaShape128x128x64_WarpShape64x32x64,\n CtaShape128x128x64_WarpShape64x64x64,\n CtaShape128x128x64_WarpShape128x32x64,\n CtaShape128x256x64_WarpShape64x64x64,\n\n // Warp configs for M=256\n CtaShape256x128x64_WarpShape64x64x64,\n\n // TensorCore config CTA_N = 64, CTA_K = 128\n CtaShape128x64x128_WarpShape64x32x128,\n\n // TensorCore config CTA_N = 256, CTA_K = 64\n CtaShape16x256x64_WarpShape16x64x64,\n\n // TensorCore config CTA_N = 256, CTA_K = 128\n CtaShape16x256x128_WarpShape16x64x128\n\n};\n\nenum class SplitKStyle {\n NO_SPLIT_K,\n SPLIT_K_SERIAL,\n STREAM_K, // Sm80+\n // SPLIT_K_PARALLEL // Not supported yet\n};\n\nenum class CutlassTileConfigSM90 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n // CTA configs for M=64\n CtaShape64x16x128B,\n CtaShape64x32x128B,\n CtaShape64x64x128B,\n CtaShape64x128x128B,\n CtaShape64x256x128B,\n\n // CTA configs for M=128\n CtaShape128x16x128B,\n CtaShape128x32x128B,\n CtaShape128x64x128B,\n CtaShape128x128x128B,\n CtaShape128x256x128B,\n\n // CTA configs for M=128\n CtaShape256x128x128B,\n};\n\nenum class CutlassTileConfigSM100 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n /*\n * Grouped GEMM\n */\n // M=64\n CtaShape64x32x128B,\n CtaShape64x64x128B,\n CtaShape64x128x128B,\n CtaShape64x256x128B,\n\n // M=128\n CtaShape128x8x256B,\n CtaShape128x16x128B,\n CtaShape128x32x128B,\n CtaShape128x64x128B,\n CtaShape128x128x128B,\n CtaShape128x256x128B,\n CtaShape128x128x256B,\n CtaShape128x256x256B,\n\n // M=256\n CtaShape256x64x128B,\n CtaShape256x128x128B,\n CtaShape256x256x128B,\n\n // SM103\n CtaShape128x128x768B,\n CtaShape128x192x768B,\n CtaShape128x256x768B,\n};\n\nenum class CutlassTileConfigSM120 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n CtaShape128x128x128B,\n CtaShape128x128x64B,\n CtaShape256x128x64B,\n CtaShape128x256x64B,\n CtaShape128x128x256B,\n CtaShape256x128x128B,\n};\n\nenum class MainloopScheduleType {\n AUTO, // Automatically selects between pingpong and cooperative schedules on Hopper. On older\n // architectures, this defaults to the \"legacy\" main loop schedule.\n PINGPONG,\n COOPERATIVE,\n WARPSPECIALIZED\n};\n\nstatic auto get_mainloop_schedule_name(MainloopScheduleType schedule) {\n if (schedule == MainloopScheduleType::AUTO) {\n return \"auto\";\n } else if (schedule == MainloopScheduleType::PINGPONG) {\n return \"pingpong\";\n } else if (schedule == MainloopScheduleType::COOPERATIVE) {\n return \"cooperative\";\n } else if (schedule == MainloopScheduleType::WARPSPECIALIZED) {\n return \"warpspecialized\";\n }\n return \"unknown schedule\";\n}\n\nenum class EpilogueScheduleType {\n AUTO, // Automatically chooses an epilogue schedule compatible with the selected main loop\n // schedule for Hopper. For architectures older than hopper, the epilogue is always\n // performed by the same thread block as the main loop.\n};\n\nenum class TileShape {\n TileShape_64x16x128,\n TileShape_64x32x128,\n TileShape_64x64x128,\n TileShape_64x128x128,\n TileShape_64x256x128,\n TileShape_64x512x128,\n TileShape_128x16x128,\n TileShape_128x32x128,\n TileShape_128x64x128,\n TileShape_128x128x128,\n TileShape_128x256x128,\n // SM103\n TileShape_128x128x768,\n TileShape_128x192x768,\n TileShape_128x256x768\n};\n\ntemplate <TileShape Shape_MNK>\nconstexpr auto get_tile_shape() {\n using namespace cute;\n if constexpr (Shape_MNK == TileShape::TileShape_64x16x128) {\n return cute::Shape<_64, _16, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x32x128) {\n return cute::Shape<_64, _32, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x64x128) {\n return cute::Shape<_64, _64, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x128x128) {\n return cute::Shape<_64, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x256x128) {\n return cute::Shape<_64, _256, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x512x128) {\n return cute::Shape<_64, _512, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x16x128) {\n return cute::Shape<_128, _16, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x32x128) {\n return cute::Shape<_128, _32, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x64x128) {\n return cute::Shape<_128, _64, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x128x128) {\n return cute::Shape<_128, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x256x128) {\n return cute::Shape<_128, _256, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x128x768) { // SM103\n return cute::Shape<_128, _128, _768>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x192x768) { // SM103\n return cute::Shape<_128, _192, _768>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x256x768) { // SM103\n return cute::Shape<_128, _256, _768>{};\n }\n}\n\nstatic auto get_tile_shape_name(TileShape Shape_MNK) {\n if (Shape_MNK == TileShape::TileShape_64x16x128) {\n return \"64x16x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x32x128) {\n return \"64x32x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x64x128) {\n return \"64x64x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x128x128) {\n return \"64x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x256x128) {\n return \"64x256x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x512x128) {\n return \"64x512x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x16x128) {\n return \"128x16x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x32x128) {\n return \"128x32x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x64x128) {\n return \"128x64x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x128x128) {\n return \"128x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x256x128) {\n return \"128x256x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x128x768) { // SM103\n return \"128x128x768\";\n } else if (Shape_MNK == TileShape::TileShape_128x192x768) { // SM103\n return \"128x192x768\";\n } else if (Shape_MNK == TileShape::TileShape_128x256x768) { // SM103\n return \"128x256x768\";\n }\n return \"Unknown shape\";\n}\n\nenum class ClusterShape {\n ClusterShape_1x1x1,\n ClusterShape_2x1x1,\n ClusterShape_1x2x1,\n ClusterShape_2x2x1,\n ClusterShape_1x4x1,\n ClusterShape_4x2x1,\n ClusterShape_2x4x1,\n ClusterShape_4x4x1,\n ClusterShape_1x8x1,\n ClusterShape_8x1x1,\n ClusterShape_4x1x1\n};\n\nstatic auto get_cluster_shape_name(ClusterShape Shape_MNK) {\n if (Shape_MNK == ClusterShape::ClusterShape_1x1x1) {\n return \"1x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_2x1x1) {\n return \"2x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_1x2x1) {\n return \"1x2x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_2x2x1) {\n return \"2x2x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_1x8x1) {\n return \"1x8x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return \"8x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_4x1x1) {\n return \"4x1x1\";\n }\n return \"Unknown shape\";\n}\n\ntemplate <ClusterShape Shape_MNK>\nconstexpr auto get_cluster_shape() {\n using namespace cute;\n if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x1x1) {\n return cute::Shape<_1, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_2x1x1) {\n return cute::Shape<_2, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x2x1) {\n return cute::Shape<_1, _2, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_2x2x1) {\n return cute::Shape<_2, _2, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x8x1) {\n return cute::Shape<_1, _8, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return cute::Shape<_8, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_4x1x1) {\n return cute::Shape<_4, _1, _1>{};\n }\n}\n\nstruct CutlassGemmConfig {\n enum CandidateConfigTypeParam : int {\n NONE = 0,\n WEIGHT_ONLY = 1u << 0,\n SIMT_ONLY = 1u << 1,\n INT8_ONLY = 1u << 2,\n HOPPER = 1u << 3,\n BLACKWELL = 1u << 4,\n GROUPED_GEMM = 1u << 5,\n FP8_ONLY = 1u << 6,\n FP4_ONLY = 1u << 7\n };\n\n CutlassTileConfig tile_config_sm80 = CutlassTileConfig::ChooseWithHeuristic;\n SplitKStyle split_k_style = SplitKStyle::NO_SPLIT_K;\n int split_k_factor = -1;\n int stages = -1;\n\n // config options for sm90\n CutlassTileConfigSM90 tile_config_sm90 = CutlassTileConfigSM90::ChooseWithHeuristic;\n CutlassTileConfigSM100 tile_config_sm100 = CutlassTileConfigSM100::ChooseWithHeuristic;\n CutlassTileConfigSM120 tile_config_sm120 = CutlassTileConfigSM120::ChooseWithHeuristic;\n MainloopScheduleType mainloop_schedule = MainloopScheduleType::AUTO;\n EpilogueScheduleType epilogue_schedule = EpilogueScheduleType::AUTO;\n ClusterShape cluster_shape = ClusterShape::ClusterShape_1x1x1;\n bool enableCudaKernel = false;\n int sm_version = 80; // Use 80 as a catch all for <90\n bool is_tma_warp_specialized = false;\n\n CutlassGemmConfig() = default;\n\n CutlassGemmConfig(CutlassTileConfig tile_config, SplitKStyle split_k_style, int split_k_factor,\n int stages)\n : tile_config_sm80(tile_config),\n split_k_style(split_k_style),\n split_k_factor(split_k_factor),\n stages(stages),\n sm_version(80) {}\n\n CutlassGemmConfig(CutlassTileConfigSM90 tile_config_sm90, MainloopScheduleType mainloop_schedule,\n EpilogueScheduleType epilogue_schedule, ClusterShape cluster_shape)\n : tile_config_sm90(tile_config_sm90),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(90),\n is_tma_warp_specialized(true) {}\n\n CutlassGemmConfig(CutlassTileConfigSM100 tile_config_sm100,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n ClusterShape cluster_shape)\n : tile_config_sm100(tile_config_sm100),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(100),\n is_tma_warp_specialized(true) {}\n\n CutlassGemmConfig(CutlassTileConfigSM120 tile_config_sm120,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n ClusterShape cluster_shape)\n : tile_config_sm120(tile_config_sm120),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(120),\n is_tma_warp_specialized(true) {}\n\n int getTileConfigAsInt() const {\n if (sm_version == 120) return (int)tile_config_sm120;\n if (sm_version == 110) return (int)tile_config_sm100;\n if (sm_version >= 100) return (int)tile_config_sm100;\n if (sm_version == 90) return (int)tile_config_sm90;\n if (sm_version < 90) return (int)tile_config_sm80;\n assert(false && \"Invalid SM version\");\n return -1;\n }\n\n std::string toString() const {\n std::stringstream tactic;\n tactic << \"Cutlass GEMM Tactic\";\n if (is_tma_warp_specialized) {\n assert(sm_version >= 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=TMA Warp Specialized\"\n << \"\\n\\tsm: \" << sm_version << \"\\n\\ttile shape ID: \" << getTileConfigAsInt()\n << \"\\n\\tcluster shape ID: \" << (int)cluster_shape\n << \"\\n\\tmainloop sched: \" << (int)mainloop_schedule\n << \"\\n\\tepi sched: \" << (int)epilogue_schedule\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else if (tile_config_sm80 != flashinfer::gemm::CutlassTileConfig::ChooseWithHeuristic) {\n assert(sm_version < 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=compatible\"\n << \"\\n\\ttile shape ID: \" << (int)tile_config_sm80 << \"\\n\\tstages: \" << (int)stages\n << \"\\n\\tsplit k: \" << (int)split_k_factor\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else if (enableCudaKernel) {\n tactic << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else {\n tactic << \"\\n\\tundefined\";\n }\n tactic << \"\\n\";\n return tactic.str();\n }\n};\n\ninline std::ostream& operator<<(std::ostream& out, CutlassGemmConfig const& config) {\n // clang-format off\n if (config.is_tma_warp_specialized)\n {\n out << \"tile_config_sm90_enum: \" << config.getTileConfigAsInt()\n << \", mainloop_schedule_enum: \" << int(config.mainloop_schedule)\n << \", epilogue_schedule_enum: \" << int(config.epilogue_schedule)\n << \", cluster_shape_enum: \" << int(config.cluster_shape)\n << \", enable_cuda_kernel: \" << (config.enableCudaKernel ? \"true\" : \"false\");\n }\n else\n {\n out << \"tile_config_enum: \" << config.getTileConfigAsInt()\n << \", split_k_style_enum: \" << int(config.split_k_style)\n << \", split_k_factor: \" << config.split_k_factor\n << \", stages: \" << config.stages\n << \", enable_cuda_kernel: \" << (config.enableCudaKernel ? \"true\" : \"false\");\n }\n // clang-format on\n return out;\n}\n\n} // namespace gemm\n} // namespace flashinfer\n#endif // FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n#define FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n\n#include <cassert>\n#include <iostream>\n#include <sstream>\n#include <string>\n\n#include \"cute/tensor.hpp\"\n\nnamespace flashinfer {\nnamespace gemm {\n\n// Note: The shapes are in the format MxNxK. The K shape of the runtime config MUST match the K\n// shape\n// in the kernel layout details when doing weight only quantization.\nenum class CutlassTileConfig {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n // SiMT config\n CtaShape128x128x8_WarpShape64x64x8,\n\n // TensorCore configs CTA_N = 128, CTA_K = 64\n // Warp configs for M=16\n CtaShape16x128x64_WarpShape16x32x64,\n // Warp configs for M=32\n CtaShape32x128x64_WarpShape32x32x64,\n\n // Warp configs for M=64\n CtaShape64x128x64_WarpShape32x64x64,\n CtaShape64x64x128_WarpShape32x64x64,\n CtaShape64x128x64_WarpShape64x32x64,\n\n // Warp configs for M=128\n CtaShape128x64x64_WarpShape64x32x64,\n CtaShape128x128x64_WarpShape64x32x64,\n CtaShape128x128x64_WarpShape64x64x64,\n CtaShape128x128x64_WarpShape128x32x64,\n CtaShape128x256x64_WarpShape64x64x64,\n\n // Warp configs for M=256\n CtaShape256x128x64_WarpShape64x64x64,\n\n // TensorCore config CTA_N = 64, CTA_K = 128\n CtaShape128x64x128_WarpShape64x32x128,\n\n // TensorCore config CTA_N = 256, CTA_K = 64\n CtaShape16x256x64_WarpShape16x64x64,\n\n // TensorCore config CTA_N = 256, CTA_K = 128\n CtaShape16x256x128_WarpShape16x64x128\n\n};\n\nenum class SplitKStyle {\n NO_SPLIT_K,\n SPLIT_K_SERIAL,\n STREAM_K, // Sm80+\n // SPLIT_K_PARALLEL // Not supported yet\n};\n\nenum class CutlassTileConfigSM90 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n // CTA configs for M=64\n CtaShape64x16x128B,\n CtaShape64x32x128B,\n CtaShape64x64x128B,\n CtaShape64x128x128B,\n CtaShape64x256x128B,\n\n // CTA configs for M=128\n CtaShape128x16x128B,\n CtaShape128x32x128B,\n CtaShape128x64x128B,\n CtaShape128x128x128B,\n CtaShape128x256x128B,\n\n // CTA configs for M=128\n CtaShape256x128x128B,\n};\n\nenum class CutlassTileConfigSM100 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n /*\n * Grouped GEMM\n */\n // M=64\n CtaShape64x32x128B,\n CtaShape64x64x128B,\n CtaShape64x128x128B,\n CtaShape64x256x128B,\n\n // M=128\n CtaShape128x8x256B,\n CtaShape128x16x128B,\n CtaShape128x32x128B,\n CtaShape128x64x128B,\n CtaShape128x128x128B,\n CtaShape128x256x128B,\n CtaShape128x128x256B,\n CtaShape128x256x256B,\n\n // M=256\n CtaShape256x64x128B,\n CtaShape256x128x128B,\n CtaShape256x256x128B,\n\n // SM103\n CtaShape128x128x768B,\n CtaShape128x192x768B,\n CtaShape128x256x768B,\n};\n\nenum class CutlassTileConfigSM120 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n CtaShape128x128x128B,\n CtaShape128x128x64B,\n CtaShape256x128x64B,\n CtaShape128x256x64B,\n CtaShape128x128x256B,\n CtaShape256x128x128B,\n};\n\nenum class MainloopScheduleType {\n AUTO, // Automatically selects between pingpong and cooperative schedules on Hopper. On older\n // architectures, this defaults to the \"legacy\" main loop schedule.\n PINGPONG,\n COOPERATIVE,\n WARPSPECIALIZED\n};\n\nstatic auto get_mainloop_schedule_name(MainloopScheduleType schedule) {\n if (schedule == MainloopScheduleType::AUTO) {\n return \"auto\";\n } else if (schedule == MainloopScheduleType::PINGPONG) {\n return \"pingpong\";\n } else if (schedule == MainloopScheduleType::COOPERATIVE) {\n return \"cooperative\";\n } else if (schedule == MainloopScheduleType::WARPSPECIALIZED) {\n return \"warpspecialized\";\n }\n return \"unknown schedule\";\n}\n\nenum class EpilogueScheduleType {\n AUTO, // Automatically chooses an epilogue schedule compatible with the selected main loop\n // schedule for Hopper. For architectures older than hopper, the epilogue is always\n // performed by the same thread block as the main loop.\n};\n\nenum class TileShape {\n TileShape_64x16x128,\n TileShape_64x32x128,\n TileShape_64x64x128,\n TileShape_64x128x128,\n TileShape_64x256x128,\n TileShape_64x512x128,\n TileShape_128x16x128,\n TileShape_128x32x128,\n TileShape_128x64x128,\n TileShape_128x128x128,\n TileShape_128x256x128,\n // SM103\n TileShape_128x128x768,\n TileShape_128x192x768,\n TileShape_128x256x768\n};\n\ntemplate <TileShape Shape_MNK>\nconstexpr auto get_tile_shape() {\n using namespace cute;\n if constexpr (Shape_MNK == TileShape::TileShape_64x16x128) {\n return cute::Shape<_64, _16, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x32x128) {\n return cute::Shape<_64, _32, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x64x128) {\n return cute::Shape<_64, _64, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x128x128) {\n return cute::Shape<_64, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x256x128) {\n return cute::Shape<_64, _256, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x512x128) {\n return cute::Shape<_64, _512, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x16x128) {\n return cute::Shape<_128, _16, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x32x128) {\n return cute::Shape<_128, _32, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x64x128) {\n return cute::Shape<_128, _64, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x128x128) {\n return cute::Shape<_128, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x256x128) {\n return cute::Shape<_128, _256, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x128x768) { // SM103\n return cute::Shape<_128, _128, _768>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x192x768) { // SM103\n return cute::Shape<_128, _192, _768>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x256x768) { // SM103\n return cute::Shape<_128, _256, _768>{};\n }\n}\n\nstatic auto get_tile_shape_name(TileShape Shape_MNK) {\n if (Shape_MNK == TileShape::TileShape_64x16x128) {\n return \"64x16x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x32x128) {\n return \"64x32x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x64x128) {\n return \"64x64x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x128x128) {\n return \"64x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x256x128) {\n return \"64x256x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x512x128) {\n return \"64x512x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x16x128) {\n return \"128x16x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x32x128) {\n return \"128x32x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x64x128) {\n return \"128x64x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x128x128) {\n return \"128x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x256x128) {\n return \"128x256x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x128x768) { // SM103\n return \"128x128x768\";\n } else if (Shape_MNK == TileShape::TileShape_128x192x768) { // SM103\n return \"128x192x768\";\n } else if (Shape_MNK == TileShape::TileShape_128x256x768) { // SM103\n return \"128x256x768\";\n }\n return \"Unknown shape\";\n}\n\nenum class ClusterShape {\n ClusterShape_1x1x1,\n ClusterShape_2x1x1,\n ClusterShape_1x2x1,\n ClusterShape_2x2x1,\n ClusterShape_1x4x1,\n ClusterShape_4x2x1,\n ClusterShape_2x4x1,\n ClusterShape_4x4x1,\n ClusterShape_1x8x1,\n ClusterShape_8x1x1,\n ClusterShape_4x1x1\n};\n\nstatic auto get_cluster_shape_name(ClusterShape Shape_MNK) {\n if (Shape_MNK == ClusterShape::ClusterShape_1x1x1) {\n return \"1x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_2x1x1) {\n return \"2x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_1x2x1) {\n return \"1x2x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_2x2x1) {\n return \"2x2x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_1x8x1) {\n return \"1x8x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return \"8x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_4x1x1) {\n return \"4x1x1\";\n }\n return \"Unknown shape\";\n}\n\ntemplate <ClusterShape Shape_MNK>\nconstexpr auto get_cluster_shape() {\n using namespace cute;\n if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x1x1) {\n return cute::Shape<_1, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_2x1x1) {\n return cute::Shape<_2, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x2x1) {\n return cute::Shape<_1, _2, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_2x2x1) {\n return cute::Shape<_2, _2, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x8x1) {\n return cute::Shape<_1, _8, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return cute::Shape<_8, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_4x1x1) {\n return cute::Shape<_4, _1, _1>{};\n }\n}\n\nstruct CutlassGemmConfig {\n enum CandidateConfigTypeParam : int {\n NONE = 0,\n WEIGHT_ONLY = 1u << 0,\n SIMT_ONLY = 1u << 1,\n INT8_ONLY = 1u << 2,\n HOPPER = 1u << 3,\n BLACKWELL = 1u << 4,\n GROUPED_GEMM = 1u << 5,\n FP8_ONLY = 1u << 6,\n FP4_ONLY = 1u << 7\n };\n\n CutlassTileConfig tile_config_sm80 = CutlassTileConfig::ChooseWithHeuristic;\n SplitKStyle split_k_style = SplitKStyle::NO_SPLIT_K;\n int split_k_factor = -1;\n int stages = -1;\n\n // config options for sm90\n CutlassTileConfigSM90 tile_config_sm90 = CutlassTileConfigSM90::ChooseWithHeuristic;\n CutlassTileConfigSM100 tile_config_sm100 = CutlassTileConfigSM100::ChooseWithHeuristic;\n CutlassTileConfigSM120 tile_config_sm120 = CutlassTileConfigSM120::ChooseWithHeuristic;\n MainloopScheduleType mainloop_schedule = MainloopScheduleType::AUTO;\n EpilogueScheduleType epilogue_schedule = EpilogueScheduleType::AUTO;\n ClusterShape cluster_shape = ClusterShape::ClusterShape_1x1x1;\n bool enableCudaKernel = false;\n int sm_version = 80; // Use 80 as a catch all for <90\n bool is_tma_warp_specialized = false;\n bool use_stream_k = false; // SM120: false = DP scheduler (default), true = StreamK scheduler\n\n CutlassGemmConfig() = default;\n\n CutlassGemmConfig(CutlassTileConfig tile_config, SplitKStyle split_k_style, int split_k_factor,\n int stages)\n : tile_config_sm80(tile_config),\n split_k_style(split_k_style),\n split_k_factor(split_k_factor),\n stages(stages),\n sm_version(80) {}\n\n CutlassGemmConfig(CutlassTileConfigSM90 tile_config_sm90, MainloopScheduleType mainloop_schedule,\n EpilogueScheduleType epilogue_schedule, ClusterShape cluster_shape)\n : tile_config_sm90(tile_config_sm90),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(90),\n is_tma_warp_specialized(true) {}\n\n CutlassGemmConfig(CutlassTileConfigSM100 tile_config_sm100,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n ClusterShape cluster_shape)\n : tile_config_sm100(tile_config_sm100),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(100),\n is_tma_warp_specialized(true) {}\n\n // SM120 constructor with optional StreamK scheduler\n // use_stream_k: false = DP scheduler (default), true = StreamK scheduler (auto heuristic)\n CutlassGemmConfig(CutlassTileConfigSM120 tile_config_sm120,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n ClusterShape cluster_shape, bool use_stream_k = false)\n : tile_config_sm120(tile_config_sm120),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(120),\n is_tma_warp_specialized(true),\n use_stream_k(use_stream_k) {}\n\n int getTileConfigAsInt() const {\n if (sm_version == 120) return (int)tile_config_sm120;\n if (sm_version == 110) return (int)tile_config_sm100;\n if (sm_version >= 100) return (int)tile_config_sm100;\n if (sm_version == 90) return (int)tile_config_sm90;\n if (sm_version < 90) return (int)tile_config_sm80;\n assert(false && \"Invalid SM version\");\n return -1;\n }\n\n std::string toString() const {\n std::stringstream tactic;\n tactic << \"Cutlass GEMM Tactic\";\n if (is_tma_warp_specialized) {\n assert(sm_version >= 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=TMA Warp Specialized\"\n << \"\\n\\tsm: \" << sm_version << \"\\n\\ttile shape ID: \" << getTileConfigAsInt()\n << \"\\n\\tcluster shape ID: \" << (int)cluster_shape\n << \"\\n\\tmainloop sched: \" << (int)mainloop_schedule\n << \"\\n\\tepi sched: \" << (int)epilogue_schedule\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n // SM120 specific: StreamK scheduler option\n if (sm_version == 120) {\n tactic << \"\\n\\tscheduler: \" << (use_stream_k ? \"StreamK (auto heuristic)\" : \"DP (default)\");\n }\n } else if (tile_config_sm80 != flashinfer::gemm::CutlassTileConfig::ChooseWithHeuristic) {\n assert(sm_version < 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=compatible\"\n << \"\\n\\ttile shape ID: \" << (int)tile_config_sm80 << \"\\n\\tstages: \" << (int)stages\n << \"\\n\\tsplit k: \" << (int)split_k_factor\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else if (enableCudaKernel) {\n tactic << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else {\n tactic << \"\\n\\tundefined\";\n }\n tactic << \"\\n\";\n return tactic.str();\n }\n};\n\ninline std::ostream& operator<<(std::ostream& out, CutlassGemmConfig const& config) {\n // clang-format off\n if (config.is_tma_warp_specialized)\n {\n out << \"tile_config_sm90_enum: \" << config.getTileConfigAsInt()\n << \", mainloop_schedule_enum: \" << int(config.mainloop_schedule)\n << \", epilogue_schedule_enum: \" << int(config.epilogue_schedule)\n << \", cluster_shape_enum: \" << int(config.cluster_shape)\n << \", enable_cuda_kernel: \" << (config.enableCudaKernel ? \"true\" : \"false\");\n }\n else\n {\n out << \"tile_config_enum: \" << config.getTileConfigAsInt()\n << \", split_k_style_enum: \" << int(config.split_k_style)\n << \", split_k_factor: \" << config.split_k_factor\n << \", stages: \" << config.stages\n << \", enable_cuda_kernel: \" << (config.enableCudaKernel ? \"true\" : \"false\");\n }\n // clang-format on\n return out;\n}\n\n} // namespace gemm\n} // namespace flashinfer\n#endif // FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/gemm/cutlass_gemm_configs.h\n+++ include/flashinfer/gemm/cutlass_gemm_configs.h\n@@ -348,6 +348,7 @@\n bool enableCudaKernel = false;\n int sm_version = 80; // Use 80 as a catch all for <90\n bool is_tma_warp_specialized = false;\n+ bool use_stream_k = false; // SM120: false = DP scheduler (default), true = StreamK scheduler\n \n CutlassGemmConfig() = default;\n \n@@ -378,15 +379,18 @@\n sm_version(100),\n is_tma_warp_specialized(true) {}\n \n+ // SM120 constructor with optional StreamK scheduler\n+ // use_stream_k: false = DP scheduler (default), true = StreamK scheduler (auto heuristic)\n CutlassGemmConfig(CutlassTileConfigSM120 tile_config_sm120,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n- ClusterShape cluster_shape)\n+ ClusterShape cluster_shape, bool use_stream_k = false)\n : tile_config_sm120(tile_config_sm120),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(120),\n- is_tma_warp_specialized(true) {}\n+ is_tma_warp_specialized(true),\n+ use_stream_k(use_stream_k) {}\n \n int getTileConfigAsInt() const {\n if (sm_version == 120) return (int)tile_config_sm120;\n@@ -409,6 +413,10 @@\n << \"\\n\\tmainloop sched: \" << (int)mainloop_schedule\n << \"\\n\\tepi sched: \" << (int)epilogue_schedule\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n+ // SM120 specific: StreamK scheduler option\n+ if (sm_version == 120) {\n+ tactic << \"\\n\\tscheduler: \" << (use_stream_k ? \"StreamK (auto heuristic)\" : \"DP (default)\");\n+ }\n } else if (tile_config_sm80 != flashinfer::gemm::CutlassTileConfig::ChooseWithHeuristic) {\n assert(sm_version < 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=compatible\""},"lines_added":{"kind":"number","value":10,"string":"10"},"lines_removed":{"kind":"number","value":2,"string":"2"},"files_in_commit":{"kind":"number","value":4,"string":"4"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["SM120"],"string":"[\n \"SM120\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/cutlass_gemm_configs.h).\n\nGoal: perf: add fp4 GEMM tile configs and streamK scheduler for SM120\nTarget hardware: SM120\nTarget models: unspecified\n\nCurrent file:\n```cpp\n/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n#define FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n\n#include <cassert>\n#include <iostream>\n#include <sstream>\n#include <string>\n\n#include \"cute/tensor.hpp\"\n\nnamespace flashinfer {\nnamespace gemm {\n\n// Note: The shapes are in the format MxNxK. The K shape of the runtime config MUST match the K\n// shape\n// in the kernel layout details when doing weight only quantization.\nenum class CutlassTileConfig {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n // SiMT config\n CtaShape128x128x8_WarpShape64x64x8,\n\n // TensorCore configs CTA_N = 128, CTA_K = 64\n // Warp configs for M=16\n CtaShape16x128x64_WarpShape16x32x64,\n // Warp configs for M=32\n CtaShape32x128x64_WarpShape32x32x64,\n\n // Warp configs for M=64\n CtaShape64x128x64_WarpShape32x64x64,\n CtaShape64x64x128_WarpShape32x64x64,\n CtaShape64x128x64_WarpShape64x32x64,\n\n // Warp configs for M=128\n CtaShape128x64x64_WarpShape64x32x64,\n CtaShape128x128x64_WarpShape64x32x64,\n CtaShape128x128x64_WarpShape64x64x64,\n CtaShape128x128x64_WarpShape128x32x64,\n CtaShape128x256x64_WarpShape64x64x64,\n\n // Warp configs for M=256\n CtaShape256x128x64_WarpShape64x64x64,\n\n // TensorCore config CTA_N = 64, CTA_K = 128\n CtaShape128x64x128_WarpShape64x32x128,\n\n // TensorCore config CTA_N = 256, CTA_K = 64\n CtaShape16x256x64_WarpShape16x64x64,\n\n // TensorCore config CTA_N = 256, CTA_K = 128\n CtaShape16x256x128_WarpShape16x64x128\n\n};\n\nenum class SplitKStyle {\n NO_SPLIT_K,\n SPLIT_K_SERIAL,\n STREAM_K, // Sm80+\n // SPLIT_K_PARALLEL // Not supported yet\n};\n\nenum class CutlassTileConfigSM90 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n // CTA configs for M=64\n CtaShape64x16x128B,\n CtaShape64x32x128B,\n CtaShape64x64x128B,\n CtaShape64x128x128B,\n CtaShape64x256x128B,\n\n // CTA configs for M=128\n CtaShape128x16x128B,\n CtaShape128x32x128B,\n CtaShape128x64x128B,\n CtaShape128x128x128B,\n CtaShape128x256x128B,\n\n // CTA configs for M=128\n CtaShape256x128x128B,\n};\n\nenum class CutlassTileConfigSM100 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n /*\n * Grouped GEMM\n */\n // M=64\n CtaShape64x32x128B,\n CtaShape64x64x128B,\n CtaShape64x128x128B,\n CtaShape64x256x128B,\n\n // M=128\n CtaShape128x8x256B,\n CtaShape128x16x128B,\n CtaShape128x32x128B,\n CtaShape128x64x128B,\n CtaShape128x128x128B,\n CtaShape128x256x128B,\n CtaShape128x128x256B,\n CtaShape128x256x256B,\n\n // M=256\n CtaShape256x64x128B,\n CtaShape256x128x128B,\n CtaShape256x256x128B,\n\n // SM103\n CtaShape128x128x768B,\n CtaShape128x192x768B,\n CtaShape128x256x768B,\n};\n\nenum class CutlassTileConfigSM120 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n CtaShape128x128x128B,\n CtaShape128x128x64B,\n CtaShape256x128x64B,\n CtaShape128x256x64B,\n CtaShape128x128x256B,\n CtaShape256x128x128B,\n};\n\nenum class MainloopScheduleType {\n AUTO, // Automatically selects between pingpong and cooperative schedules on Hopper. On older\n // architectures, this defaults to the \"legacy\" main loop schedule.\n PINGPONG,\n COOPERATIVE,\n WARPSPECIALIZED\n};\n\nstatic auto get_mainloop_schedule_name(MainloopScheduleType schedule) {\n if (schedule == MainloopScheduleType::AUTO) {\n return \"auto\";\n } else if (schedule == MainloopScheduleType::PINGPONG) {\n return \"pingpong\";\n } else if (schedule == MainloopScheduleType::COOPERATIVE) {\n return \"cooperative\";\n } else if (schedule == MainloopScheduleType::WARPSPECIALIZED) {\n return \"warpspecialized\";\n }\n return \"unknown schedule\";\n}\n\nenum class EpilogueScheduleType {\n AUTO, // Automatically chooses an epilogue schedule compatible with the selected main loop\n // schedule for Hopper. For architectures older than hopper, the epilogue is always\n // performed by the same thread block as the main loop.\n};\n\nenum class TileShape {\n TileShape_64x16x128,\n TileShape_64x32x128,\n TileShape_64x64x128,\n TileShape_64x128x128,\n TileShape_64x256x128,\n TileShape_64x512x128,\n TileShape_128x16x128,\n TileShape_128x32x128,\n TileShape_128x64x128,\n TileShape_128x128x128,\n TileShape_128x256x128,\n // SM103\n TileShape_128x128x768,\n TileShape_128x192x768,\n TileShape_128x256x768\n};\n\ntemplate <TileShape Shape_MNK>\nconstexpr auto get_tile_shape() {\n using namespace cute;\n if constexpr (Shape_MNK == TileShape::TileShape_64x16x128) {\n return cute::Shape<_64, _16, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x32x128) {\n return cute::Shape<_64, _32, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x64x128) {\n return cute::Shape<_64, _64, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x128x128) {\n return cute::Shape<_64, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x256x128) {\n return cute::Shape<_64, _256, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x512x128) {\n return cute::Shape<_64, _512, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x16x128) {\n return cute::Shape<_128, _16, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x32x128) {\n return cute::Shape<_128, _32, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x64x128) {\n return cute::Shape<_128, _64, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x128x128) {\n return cute::Shape<_128, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x256x128) {\n return cute::Shape<_128, _256, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x128x768) { // SM103\n return cute::Shape<_128, _128, _768>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x192x768) { // SM103\n return cute::Shape<_128, _192, _768>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x256x768) { // SM103\n return cute::Shape<_128, _256, _768>{};\n }\n}\n\nstatic auto get_tile_shape_name(TileShape Shape_MNK) {\n if (Shape_MNK == TileShape::TileShape_64x16x128) {\n return \"64x16x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x32x128) {\n return \"64x32x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x64x128) {\n return \"64x64x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x128x128) {\n return \"64x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x256x128) {\n return \"64x256x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x512x128) {\n return \"64x512x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x16x128) {\n return \"128x16x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x32x128) {\n return \"128x32x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x64x128) {\n return \"128x64x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x128x128) {\n return \"128x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x256x128) {\n return \"128x256x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x128x768) { // SM103\n return \"128x128x768\";\n } else if (Shape_MNK == TileShape::TileShape_128x192x768) { // SM103\n return \"128x192x768\";\n } else if (Shape_MNK == TileShape::TileShape_128x256x768) { // SM103\n return \"128x256x768\";\n }\n return \"Unknown shape\";\n}\n\nenum class ClusterShape {\n ClusterShape_1x1x1,\n ClusterShape_2x1x1,\n ClusterShape_1x2x1,\n ClusterShape_2x2x1,\n ClusterShape_1x4x1,\n ClusterShape_4x2x1,\n ClusterShape_2x4x1,\n ClusterShape_4x4x1,\n ClusterShape_1x8x1,\n ClusterShape_8x1x1,\n ClusterShape_4x1x1\n};\n\nstatic auto get_cluster_shape_name(ClusterShape Shape_MNK) {\n if (Shape_MNK == ClusterShape::ClusterShape_1x1x1) {\n return \"1x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_2x1x1) {\n return \"2x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_1x2x1) {\n return \"1x2x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_2x2x1) {\n return \"2x2x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_1x8x1) {\n return \"1x8x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return \"8x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_4x1x1) {\n return \"4x1x1\";\n }\n return \"Unknown shape\";\n}\n\ntemplate <ClusterShape Shape_MNK>\nconstexpr auto get_cluster_shape() {\n using namespace cute;\n if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x1x1) {\n return cute::Shape<_1, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_2x1x1) {\n return cute::Shape<_2, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x2x1) {\n return cute::Shape<_1, _2, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_2x2x1) {\n return cute::Shape<_2, _2, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x8x1) {\n return cute::Shape<_1, _8, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return cute::Shape<_8, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_4x1x1) {\n return cute::Shape<_4, _1, _1>{};\n }\n}\n\nstruct CutlassGemmConfig {\n enum CandidateConfigTypeParam : int {\n NONE = 0,\n WEIGHT_ONLY = 1u << 0,\n SIMT_ONLY = 1u << 1,\n INT8_ONLY = 1u << 2,\n HOPPER = 1u << 3,\n BLACKWELL = 1u << 4,\n GROUPED_GEMM = 1u << 5,\n FP8_ONLY = 1u << 6,\n FP4_ONLY = 1u << 7\n };\n\n CutlassTileConfig tile_config_sm80 = CutlassTileConfig::ChooseWithHeuristic;\n SplitKStyle split_k_style = SplitKStyle::NO_SPLIT_K;\n int split_k_factor = -1;\n int stages = -1;\n\n // config options for sm90\n CutlassTileConfigSM90 tile_config_sm90 = CutlassTileConfigSM90::ChooseWithHeuristic;\n CutlassTileConfigSM100 tile_config_sm100 = CutlassTileConfigSM100::ChooseWithHeuristic;\n CutlassTileConfigSM120 tile_config_sm120 = CutlassTileConfigSM120::ChooseWithHeuristic;\n MainloopScheduleType mainloop_schedule = MainloopScheduleType::AUTO;\n EpilogueScheduleType epilogue_schedule = EpilogueScheduleType::AUTO;\n ClusterShape cluster_shape = ClusterShape::ClusterShape_1x1x1;\n bool enableCudaKernel = false;\n int sm_version = 80; // Use 80 as a catch all for <90\n bool is_tma_warp_specialized = false;\n\n CutlassGemmConfig() = default;\n\n CutlassGemmConfig(CutlassTileConfig tile_config, SplitKStyle split_k_style, int split_k_factor,\n int stages)\n : tile_config_sm80(tile_config),\n split_k_style(split_k_style),\n split_k_factor(split_k_factor),\n stages(stages),\n sm_version(80) {}\n\n CutlassGemmConfig(CutlassTileConfigSM90 tile_config_sm90, MainloopScheduleType mainloop_schedule,\n EpilogueScheduleType epilogue_schedule, ClusterShape cluster_shape)\n : tile_config_sm90(tile_config_sm90),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(90),\n is_tma_warp_specialized(true) {}\n\n CutlassGemmConfig(CutlassTileConfigSM100 tile_config_sm100,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n ClusterShape cluster_shape)\n : tile_config_sm100(tile_config_sm100),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(100),\n is_tma_warp_specialized(true) {}\n\n CutlassGemmConfig(CutlassTileConfigSM120 tile_config_sm120,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n ClusterShape cluster_shape)\n : tile_config_sm120(tile_config_sm120),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(120),\n is_tma_warp_specialized(true) {}\n\n int getTileConfigAsInt() const {\n if (sm_version == 120) return (int)tile_config_sm120;\n if (sm_version == 110) return (int)tile_config_sm100;\n if (sm_version >= 100) return (int)tile_config_sm100;\n if (sm_version == 90) return (int)tile_config_sm90;\n if (sm_version < 90) return (int)tile_config_sm80;\n assert(false && \"Invalid SM version\");\n return -1;\n }\n\n std::string toString() const {\n std::stringstream tactic;\n tactic << \"Cutlass GEMM Tactic\";\n if (is_tma_warp_specialized) {\n assert(sm_version >= 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=TMA Warp Specialized\"\n << \"\\n\\tsm: \" << sm_version << \"\\n\\ttile shape ID: \" << getTileConfigAsInt()\n << \"\\n\\tcluster shape ID: \" << (int)cluster_shape\n << \"\\n\\tmainloop sched: \" << (int)mainloop_schedule\n << \"\\n\\tepi sched: \" << (int)epilogue_schedule\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else if (tile_config_sm80 != flashinfer::gemm::CutlassTileConfig::ChooseWithHeuristic) {\n assert(sm_version < 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=compatible\"\n << \"\\n\\ttile shape ID: \" << (int)tile_config_sm80 << \"\\n\\tstages: \" << (int)stages\n << \"\\n\\tsplit k: \" << (int)split_k_factor\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else if (enableCudaKernel) {\n tactic << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else {\n tactic << \"\\n\\tundefined\";\n }\n tactic << \"\\n\";\n return tactic.str();\n }\n};\n\ninline std::ostream& operator<<(std::ostream& out, CutlassGemmConfig const& config) {\n // clang-format off\n if (config.is_tma_warp_specialized)\n {\n out << \"tile_config_sm90_enum: \" << config.getTileConfigAsInt()\n << \", mainloop_schedule_enum: \" << int(config.mainloop_schedule)\n << \", epilogue_schedule_enum: \" << int(config.epilogue_schedule)\n << \", cluster_shape_enum: \" << int(config.cluster_shape)\n << \", enable_cuda_kernel: \" << (config.enableCudaKernel ? \"true\" : \"false\");\n }\n else\n {\n out << \"tile_config_enum: \" << config.getTileConfigAsInt()\n << \", split_k_style_enum: \" << int(config.split_k_style)\n << \", split_k_factor: \" << config.split_k_factor\n << \", stages: \" << config.stages\n << \", enable_cuda_kernel: \" << (config.enableCudaKernel ? \"true\" : \"false\");\n }\n // clang-format on\n return out;\n}\n\n} // namespace gemm\n} // namespace flashinfer\n#endif // FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nAdd SM120 FP4 GEMM tile configs and enable streamK scheduler for configs that can be selected by autotuner.\nTake the problem size m=32, n=5120, k=25600 as an example. After adding these configs, the latency of mm_fp4 kernel reduced from 0.124ms to 0.069ms on RTX PRO 6000.\n\n```\n[PERF] cutlass_autotun:: median time 0.124 ms; std 0.000 ms; achieved tflops 67.751 TFLOPs/sec; achieved tb_per_sec 0.535 TB/sec\n[PERF] cutlass_autotun:: median time 0.069 ms; std 0.000 ms; achieved tflops 121.902 TFLOPs/sec; achieved tb_per_sec 0.963 TB/sec\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n * Added StreamK scheduler option for SM120 FP4 GEMM operations, alongside the existing DP scheduler.\n * Expanded SM120 FP4 GEMM tile configurations with two additional options (128×128×256 and 256×128×128).\n * Extended configuration generation to support all tile shapes with both schedulers for improved optimization flexibility.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"m=32,n=5120,k=25600\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.124, \"optimized\": 0.069, \"stated_speedup\": null, \"speedup\": 1.7971}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"m=32,n=5120,k=25600\", \"batch_size\": null, \"metric\": \"TFLOPS\", \"unit\": \"TFLOPs/sec\", \"higher_is_better\": true, \"baseline\": 67.751, \"optimized\": 121.902, \"stated_speedup\": null, \"speedup\": 1.7993}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"m=32,n=5120,k=25600\", \"batch_size\": null, \"metric\": \"bandwidth\", \"unit\": \"TB/sec\", \"higher_is_better\": true, \"baseline\": 0.535, \"optimized\": 0.963, \"stated_speedup\": null, \"speedup\": 1.8}]"},"kernel_speedup":{"kind":"number","value":1.7993,"string":"1.7993"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1183,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"57ef44b9d7ada00cb50ca26310f9c3a3bfbc0dd2"},"date":{"kind":"string","value":"2026-02-06T14:55:45+08:00"},"pr_number":{"kind":"number","value":2460,"string":"2,460"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2460"},"title":{"kind":"string","value":"perf: add fp4 GEMM tile configs and streamK scheduler for SM120 (#2460)"},"message":{"kind":"string","value":"perf: add fp4 GEMM tile configs and streamK scheduler for SM120 (#2460)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nAdd SM120 FP4 GEMM tile configs and enable streamK scheduler for configs\nthat can be selected by autotuner.\nTake the problem size m=32, n=5120, k=25600 as an example. After adding\nthese configs, the latency of mm_fp4 kernel reduced from 0.124ms to\n0.069ms on RTX PRO 6000.\n\n```\n[PERF] cutlass_autotun:: median time 0.124 ms; std 0.000 ms; achieved tflops 67.751 TFLOPs/sec; achieved tb_per_sec 0.535 TB/sec\n[PERF] cutlass_autotun:: median time 0.069 ms; std 0.000 ms; achieved tflops 121.902 TFLOPs/sec; achieved tb_per_sec 0.963 TB/sec\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n* Added StreamK scheduler option for SM120 FP4 GEMM operations,\nalongside the existing DP scheduler.\n* Expanded SM120 FP4 GEMM tile configurations with two additional\noptions (128×128×256 and 256×128×128).\n* Extended configuration generation to support all tile shapes with both\nschedulers for improved optimization flexibility.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"include/flashinfer/gemm/fp4_gemm_cutlass_template_sm120.h"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef FLASHINFER_FP4_GEMM_CUTLASS_TEMPLATE_SM120_H_\n#define FLASHINFER_FP4_GEMM_CUTLASS_TEMPLATE_SM120_H_\n\n#ifndef _WIN32\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wstrict-aliasing\"\n#endif // #ifndef _WIN32\n\n#include \"cutlass/arch/arch.h\"\n#include \"cutlass/cutlass.h\"\n#include \"cutlass/epilogue/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/device/gemm_universal_adapter.h\"\n#include \"cutlass/gemm/gemm.h\"\n#include \"flashinfer/gemm/cutlass_gemm_configs.h\"\n\n#ifndef _WIN32\n#pragma GCC diagnostic pop\n#endif // #ifndef _WIN32\n\n#include \"flashinfer/gemm/fp4_gemm_cutlass.h\"\n\n// Include the SM120-specific template\n#define FLASHINFER_ENABLE_SM120\n#include \"fp4_gemm_template_sm120.h\"\n\nnamespace flashinfer {\nnamespace gemm {\nusing namespace cute;\n\ntemplate <typename T, typename CTA_M_, typename CTA_N_, typename CTA_K_>\nsize_t dispatchNVFP4xNVFP4GemmClusterShapeSm120(T* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k,\n int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes,\n cudaStream_t stream, int* occupancy = nullptr) {\n // For SM120/SM121, only support 1x1x1 cluster shape\n // Always use 1x1x1 cluster shape regardless of gemmConfig.cluster_shape\n return genericFp4GemmKernelLauncher<T, CTA_M_, CTA_N_, CTA_K_, cute::Int<1>, cute::Int<1>,\n cute::Int<1>, _1SM>(\n D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n workspaceBytes, stream, occupancy);\n}\n\n/*!\n * \\brief Dispatch FP4 GEMM operation with CTA shape configuration for SM120/SM121\n * \\param D Output matrix pointer\n * \\param A Input matrix A pointer (FP4 quantized)\n * \\param B Input matrix B pointer (FP4 quantized)\n * \\param input_sf Input scale factors\n * \\param weight_sf Weight scale factors\n * \\param global_sf Global scale factor\n * \\param m Number of rows in matrix A and output matrix D\n * \\param n Number of columns in matrix B and output matrix D\n * \\param k Number of columns in matrix A and rows in matrix B\n * \\param batch_count Number of batches for batched GEMM\n * \\param gemmConfig GEMM configuration including tile size and cluster shape\n * \\param workspace Workspace buffer for temporary storage\n * \\param workspaceBytes Size of workspace buffer in bytes\n * \\param stream CUDA stream for kernel execution\n * \\param occupancy Optional pointer to store kernel occupancy\n * \\return Size of workspace required in bytes\n */\ntemplate <typename T>\nsize_t dispatchNVFP4xNVFP4GemmCTAShapeSm120(T* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k,\n int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes,\n cudaStream_t stream, int* occupancy = nullptr) {\n // For SM120/SM121, we only support 128x128x128 tile configuration\n // Check the SM120 tile config and dispatch accordingly\n switch (gemmConfig.tile_config_sm120) {\n case CutlassTileConfigSM120::CtaShape128x128x128B:\n // Always use 1x1x1 cluster shape for SM120\n return dispatchNVFP4xNVFP4GemmClusterShapeSm120<T, cute::Int<128>, cute::Int<128>,\n cute::Int<128>>(\n D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n workspaceBytes, stream, occupancy);\n break;\n case CutlassTileConfigSM120::Undefined:\n throw std::runtime_error(\"[Error][FP4][dispatch_gemm_cta_shape] Gemm config undefined.\");\n break;\n case CutlassTileConfigSM120::ChooseWithHeuristic:\n throw std::runtime_error(\n \"[Error][FP4][dispatch_gemm_cta_shape] Gemm config should have already been set by \"\n \"heuristic.\");\n break;\n default:\n // For any other SM120 tile configs that we don't support yet, fall back to 128x128x128\n return dispatchNVFP4xNVFP4GemmClusterShapeSm120<T, cute::Int<128>, cute::Int<128>,\n cute::Int<128>>(\n D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n workspaceBytes, stream, occupancy);\n break;\n }\n}\ntemplate <typename T, FP4GemmType fp4GemmType>\nCutlassFp4GemmRunner<T, fp4GemmType>::CutlassFp4GemmRunner() {}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nCutlassFp4GemmRunner<T, fp4GemmType>::~CutlassFp4GemmRunner() {}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nsize_t CutlassFp4GemmRunner<T, fp4GemmType>::dispatchToArch(\n T* D, void const* A, void const* B, void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k, int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes, cudaStream_t stream, int* occupancy) {\n if constexpr (fp4GemmType == FP4GemmType::W4A4_NVFP4_NVFP4) {\n return dispatchNVFP4xNVFP4GemmCTAShapeSm120<T>(D, A, B, input_sf, weight_sf, global_sf, m, n, k,\n batch_count, gemmConfig, workspace,\n workspaceBytes, stream, occupancy);\n } else {\n throw std::runtime_error(\n \"[Error][CutlassFp4GemmRunner][GEMM Dispatch] FP4 Gemm type unsupported for \"\n \"CUTLASS FP4 GEMM\");\n }\n}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nvoid CutlassFp4GemmRunner<T, fp4GemmType>::gemm(void* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k,\n int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes,\n cudaStream_t stream) {\n CutlassFp4GemmRunner<T, fp4GemmType>::dispatchToArch(\n reinterpret_cast<T*>(D), A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count,\n gemmConfig, workspace, workspaceBytes, stream);\n}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nstd::vector<CutlassGemmConfig> CutlassFp4GemmRunner<T, fp4GemmType>::getConfigs() const {\n std::vector<CutlassGemmConfig> candidateConfigs;\n\n // For SM120/SM121, only support 128x128x128 tile with 1x1x1 cluster shape\n CutlassGemmConfig config(CutlassTileConfigSM120::CtaShape128x128x128B, MainloopScheduleType::AUTO,\n EpilogueScheduleType::AUTO, ClusterShape::ClusterShape_1x1x1);\n candidateConfigs.push_back(config);\n\n return candidateConfigs;\n}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nsize_t CutlassFp4GemmRunner<T, fp4GemmType>::getWorkspaceSizeImpl(int const m, int const n,\n int const k,\n int const batch_count) {\n size_t workspace_size = 0;\n auto gemmConfigs = CutlassFp4GemmRunner<T, fp4GemmType>{}.getConfigs();\n for (auto const& gemmConfig : gemmConfigs) {\n try {\n size_t curr_workspace_size = CutlassFp4GemmRunner<T, fp4GemmType>::dispatchToArch(\n nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, m, n, k, batch_count, gemmConfig,\n nullptr, 0, 0);\n workspace_size = std::max(workspace_size, curr_workspace_size);\n } catch (std::runtime_error& e) {\n // Swallow errors when SMEM exceeds maximum allowed\n continue;\n }\n }\n return workspace_size;\n}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nsize_t CutlassFp4GemmRunner<T, fp4GemmType>::getWorkspaceSize(int const m, int const n, int const k,\n int const batch_count) {\n // Custom hash function for the MNKB type\n using MNK = std::tuple<int, int, int, int>;\n\n struct MNKHash {\n size_t operator()(const MNK& mnk) const {\n auto h1 = std::hash<int>{}(std::get<0>(mnk));\n auto h2 = std::hash<int>{}(std::get<1>(mnk));\n auto h3 = std::hash<int>{}(std::get<2>(mnk));\n auto h4 = std::hash<int>{}(std::get<3>(mnk));\n return h1 ^ h2 ^ h3 ^ h4;\n }\n };\n\n static std::unordered_map<MNK, size_t, MNKHash> workspace_hashmap;\n\n size_t workspace_size = 0;\n if (workspace_hashmap.find(std::make_tuple(m, n, k, batch_count)) == workspace_hashmap.end()) {\n workspace_size =\n CutlassFp4GemmRunner<T, fp4GemmType>::getWorkspaceSizeImpl(m, n, k, batch_count);\n workspace_hashmap[std::make_tuple(m, n, k, batch_count)] = workspace_size;\n } else {\n workspace_size = workspace_hashmap[std::make_tuple(m, n, k, batch_count)];\n }\n return workspace_size;\n}\n\n} // namespace gemm\n} // namespace flashinfer\n#endif // FLASHINFER_FP4_GEMM_CUTLASS_TEMPLATE_SM120_H_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef FLASHINFER_FP4_GEMM_CUTLASS_TEMPLATE_SM120_H_\n#define FLASHINFER_FP4_GEMM_CUTLASS_TEMPLATE_SM120_H_\n\n#ifndef _WIN32\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wstrict-aliasing\"\n#endif // #ifndef _WIN32\n\n#include \"cutlass/arch/arch.h\"\n#include \"cutlass/cutlass.h\"\n#include \"cutlass/epilogue/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/device/gemm_universal_adapter.h\"\n#include \"cutlass/gemm/gemm.h\"\n#include \"flashinfer/gemm/cutlass_gemm_configs.h\"\n\n#ifndef _WIN32\n#pragma GCC diagnostic pop\n#endif // #ifndef _WIN32\n\n#include \"flashinfer/gemm/fp4_gemm_cutlass.h\"\n\n// Include the SM120-specific template\n#define FLASHINFER_ENABLE_SM120\n#include \"fp4_gemm_template_sm120.h\"\n\nnamespace flashinfer {\nnamespace gemm {\nusing namespace cute;\n\n// UseStreamK: false = DP scheduler (default), true = StreamK scheduler\ntemplate <typename T, typename CTA_M_, typename CTA_N_, typename CTA_K_, bool UseStreamK = false>\nsize_t dispatchNVFP4xNVFP4GemmClusterShapeSm120(T* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k,\n int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes,\n cudaStream_t stream, int* occupancy = nullptr) {\n // For SM120/SM121, only support 1x1x1 cluster shape\n // Always use 1x1x1 cluster shape regardless of gemmConfig.cluster_shape\n if constexpr (UseStreamK) {\n return genericFp4GemmKernelLauncherStreamK<T, CTA_M_, CTA_N_, CTA_K_, cute::Int<1>,\n cute::Int<1>, cute::Int<1>, _1SM>(\n D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n workspaceBytes, stream, occupancy);\n } else {\n return genericFp4GemmKernelLauncher<T, CTA_M_, CTA_N_, CTA_K_, cute::Int<1>, cute::Int<1>,\n cute::Int<1>, _1SM>(\n D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n workspaceBytes, stream, occupancy);\n }\n}\n\n/*!\n * \\brief Dispatch FP4 GEMM operation with CTA shape configuration for SM120/SM121\n * \\param D Output matrix pointer\n * \\param A Input matrix A pointer (FP4 quantized)\n * \\param B Input matrix B pointer (FP4 quantized)\n * \\param input_sf Input scale factors\n * \\param weight_sf Weight scale factors\n * \\param global_sf Global scale factor\n * \\param m Number of rows in matrix A and output matrix D\n * \\param n Number of columns in matrix B and output matrix D\n * \\param k Number of columns in matrix A and rows in matrix B\n * \\param batch_count Number of batches for batched GEMM\n * \\param gemmConfig GEMM configuration including tile size and cluster shape\n * \\param workspace Workspace buffer for temporary storage\n * \\param workspaceBytes Size of workspace buffer in bytes\n * \\param stream CUDA stream for kernel execution\n * \\param occupancy Optional pointer to store kernel occupancy\n * \\return Size of workspace required in bytes\n */\n// Helper macro to dispatch tile config with scheduler selection\n#define DISPATCH_TILE_CONFIG(CTA_M, CTA_N, CTA_K, USE_STREAMK) \\\n return dispatchNVFP4xNVFP4GemmClusterShapeSm120<T, cute::Int<CTA_M>, cute::Int<CTA_N>, \\\n cute::Int<CTA_K>, USE_STREAMK>( \\\n D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace, \\\n workspaceBytes, stream, occupancy)\n\n// Helper macro to dispatch with scheduler check\n#define DISPATCH_WITH_SCHEDULER(CTA_M, CTA_N, CTA_K) \\\n if (gemmConfig.use_stream_k) { \\\n DISPATCH_TILE_CONFIG(CTA_M, CTA_N, CTA_K, true); \\\n } else { \\\n DISPATCH_TILE_CONFIG(CTA_M, CTA_N, CTA_K, false); \\\n }\n\ntemplate <typename T>\nsize_t dispatchNVFP4xNVFP4GemmCTAShapeSm120(T* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k,\n int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes,\n cudaStream_t stream, int* occupancy = nullptr) {\n // Dispatch based on tile config and scheduler type\n switch (gemmConfig.tile_config_sm120) {\n case CutlassTileConfigSM120::CtaShape128x128x128B:\n DISPATCH_WITH_SCHEDULER(128, 128, 128);\n case CutlassTileConfigSM120::CtaShape128x128x256B:\n DISPATCH_WITH_SCHEDULER(128, 128, 256);\n case CutlassTileConfigSM120::CtaShape256x128x128B:\n DISPATCH_WITH_SCHEDULER(256, 128, 128);\n case CutlassTileConfigSM120::Undefined:\n throw std::runtime_error(\"[Error][FP4][dispatch_gemm_cta_shape] Gemm config undefined.\");\n case CutlassTileConfigSM120::ChooseWithHeuristic:\n throw std::runtime_error(\n \"[Error][FP4][dispatch_gemm_cta_shape] Gemm config should have already been set by \"\n \"heuristic.\");\n default:\n DISPATCH_WITH_SCHEDULER(128, 128, 128); // Fallback\n }\n}\n\n#undef DISPATCH_WITH_SCHEDULER\n#undef DISPATCH_TILE_CONFIG\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nCutlassFp4GemmRunner<T, fp4GemmType>::CutlassFp4GemmRunner() {}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nCutlassFp4GemmRunner<T, fp4GemmType>::~CutlassFp4GemmRunner() {}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nsize_t CutlassFp4GemmRunner<T, fp4GemmType>::dispatchToArch(\n T* D, void const* A, void const* B, void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k, int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes, cudaStream_t stream, int* occupancy) {\n if constexpr (fp4GemmType == FP4GemmType::W4A4_NVFP4_NVFP4) {\n return dispatchNVFP4xNVFP4GemmCTAShapeSm120<T>(D, A, B, input_sf, weight_sf, global_sf, m, n, k,\n batch_count, gemmConfig, workspace,\n workspaceBytes, stream, occupancy);\n } else {\n throw std::runtime_error(\n \"[Error][CutlassFp4GemmRunner][GEMM Dispatch] FP4 Gemm type unsupported for \"\n \"CUTLASS FP4 GEMM\");\n }\n}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nvoid CutlassFp4GemmRunner<T, fp4GemmType>::gemm(void* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k,\n int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes,\n cudaStream_t stream) {\n CutlassFp4GemmRunner<T, fp4GemmType>::dispatchToArch(\n reinterpret_cast<T*>(D), A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count,\n gemmConfig, workspace, workspaceBytes, stream);\n}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nstd::vector<CutlassGemmConfig> CutlassFp4GemmRunner<T, fp4GemmType>::getConfigs() const {\n std::vector<CutlassGemmConfig> candidateConfigs;\n\n // All supported tile configurations for SM120\n std::vector<CutlassTileConfigSM120> tilesSm120 = {\n CutlassTileConfigSM120::CtaShape128x128x128B,\n CutlassTileConfigSM120::CtaShape128x128x256B,\n CutlassTileConfigSM120::CtaShape256x128x128B,\n };\n\n // SM120 only supports 1x1x1 cluster shape\n ClusterShape clusterShape = ClusterShape::ClusterShape_1x1x1;\n\n // Generate configs for both DP and StreamK schedulers\n for (auto const& tile_config : tilesSm120) {\n // Default DP scheduler (use_stream_k = false)\n candidateConfigs.push_back(CutlassGemmConfig(tile_config, MainloopScheduleType::AUTO,\n EpilogueScheduleType::AUTO, clusterShape, false));\n\n // StreamK scheduler (use_stream_k = true) - better for small M/N, large K\n candidateConfigs.push_back(CutlassGemmConfig(tile_config, MainloopScheduleType::AUTO,\n EpilogueScheduleType::AUTO, clusterShape, true));\n }\n return candidateConfigs;\n}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nsize_t CutlassFp4GemmRunner<T, fp4GemmType>::getWorkspaceSizeImpl(int const m, int const n,\n int const k,\n int const batch_count) {\n size_t workspace_size = 0;\n auto gemmConfigs = CutlassFp4GemmRunner<T, fp4GemmType>{}.getConfigs();\n for (auto const& gemmConfig : gemmConfigs) {\n try {\n size_t curr_workspace_size = CutlassFp4GemmRunner<T, fp4GemmType>::dispatchToArch(\n nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, m, n, k, batch_count, gemmConfig,\n nullptr, 0, 0);\n workspace_size = std::max(workspace_size, curr_workspace_size);\n } catch (std::runtime_error& e) {\n // Swallow errors when SMEM exceeds maximum allowed\n continue;\n }\n }\n return workspace_size;\n}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nsize_t CutlassFp4GemmRunner<T, fp4GemmType>::getWorkspaceSize(int const m, int const n, int const k,\n int const batch_count) {\n // Custom hash function for the MNKB type\n using MNK = std::tuple<int, int, int, int>;\n\n struct MNKHash {\n size_t operator()(const MNK& mnk) const {\n auto h1 = std::hash<int>{}(std::get<0>(mnk));\n auto h2 = std::hash<int>{}(std::get<1>(mnk));\n auto h3 = std::hash<int>{}(std::get<2>(mnk));\n auto h4 = std::hash<int>{}(std::get<3>(mnk));\n return h1 ^ h2 ^ h3 ^ h4;\n }\n };\n\n static std::unordered_map<MNK, size_t, MNKHash> workspace_hashmap;\n\n size_t workspace_size = 0;\n if (workspace_hashmap.find(std::make_tuple(m, n, k, batch_count)) == workspace_hashmap.end()) {\n workspace_size =\n CutlassFp4GemmRunner<T, fp4GemmType>::getWorkspaceSizeImpl(m, n, k, batch_count);\n workspace_hashmap[std::make_tuple(m, n, k, batch_count)] = workspace_size;\n } else {\n workspace_size = workspace_hashmap[std::make_tuple(m, n, k, batch_count)];\n }\n return workspace_size;\n}\n\n} // namespace gemm\n} // namespace flashinfer\n#endif // FLASHINFER_FP4_GEMM_CUTLASS_TEMPLATE_SM120_H_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/gemm/fp4_gemm_cutlass_template_sm120.h\n+++ include/flashinfer/gemm/fp4_gemm_cutlass_template_sm120.h\n@@ -44,7 +44,8 @@\n namespace gemm {\n using namespace cute;\n \n-template <typename T, typename CTA_M_, typename CTA_N_, typename CTA_K_>\n+// UseStreamK: false = DP scheduler (default), true = StreamK scheduler\n+template <typename T, typename CTA_M_, typename CTA_N_, typename CTA_K_, bool UseStreamK = false>\n size_t dispatchNVFP4xNVFP4GemmClusterShapeSm120(T* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k,\n@@ -53,10 +54,17 @@\n cudaStream_t stream, int* occupancy = nullptr) {\n // For SM120/SM121, only support 1x1x1 cluster shape\n // Always use 1x1x1 cluster shape regardless of gemmConfig.cluster_shape\n- return genericFp4GemmKernelLauncher<T, CTA_M_, CTA_N_, CTA_K_, cute::Int<1>, cute::Int<1>,\n- cute::Int<1>, _1SM>(\n- D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n- workspaceBytes, stream, occupancy);\n+ if constexpr (UseStreamK) {\n+ return genericFp4GemmKernelLauncherStreamK<T, CTA_M_, CTA_N_, CTA_K_, cute::Int<1>,\n+ cute::Int<1>, cute::Int<1>, _1SM>(\n+ D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n+ workspaceBytes, stream, occupancy);\n+ } else {\n+ return genericFp4GemmKernelLauncher<T, CTA_M_, CTA_N_, CTA_K_, cute::Int<1>, cute::Int<1>,\n+ cute::Int<1>, _1SM>(\n+ D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n+ workspaceBytes, stream, occupancy);\n+ }\n }\n \n /*!\n@@ -78,6 +86,21 @@\n * \\param occupancy Optional pointer to store kernel occupancy\n * \\return Size of workspace required in bytes\n */\n+// Helper macro to dispatch tile config with scheduler selection\n+#define DISPATCH_TILE_CONFIG(CTA_M, CTA_N, CTA_K, USE_STREAMK) \\\n+ return dispatchNVFP4xNVFP4GemmClusterShapeSm120<T, cute::Int<CTA_M>, cute::Int<CTA_N>, \\\n+ cute::Int<CTA_K>, USE_STREAMK>( \\\n+ D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace, \\\n+ workspaceBytes, stream, occupancy)\n+\n+// Helper macro to dispatch with scheduler check\n+#define DISPATCH_WITH_SCHEDULER(CTA_M, CTA_N, CTA_K) \\\n+ if (gemmConfig.use_stream_k) { \\\n+ DISPATCH_TILE_CONFIG(CTA_M, CTA_N, CTA_K, true); \\\n+ } else { \\\n+ DISPATCH_TILE_CONFIG(CTA_M, CTA_N, CTA_K, false); \\\n+ }\n+\n template <typename T>\n size_t dispatchNVFP4xNVFP4GemmCTAShapeSm120(T* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n@@ -85,33 +108,28 @@\n int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes,\n cudaStream_t stream, int* occupancy = nullptr) {\n- // For SM120/SM121, we only support 128x128x128 tile configuration\n- // Check the SM120 tile config and dispatch accordingly\n+ // Dispatch based on tile config and scheduler type\n switch (gemmConfig.tile_config_sm120) {\n case CutlassTileConfigSM120::CtaShape128x128x128B:\n- // Always use 1x1x1 cluster shape for SM120\n- return dispatchNVFP4xNVFP4GemmClusterShapeSm120<T, cute::Int<128>, cute::Int<128>,\n- cute::Int<128>>(\n- D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n- workspaceBytes, stream, occupancy);\n- break;\n+ DISPATCH_WITH_SCHEDULER(128, 128, 128);\n+ case CutlassTileConfigSM120::CtaShape128x128x256B:\n+ DISPATCH_WITH_SCHEDULER(128, 128, 256);\n+ case CutlassTileConfigSM120::CtaShape256x128x128B:\n+ DISPATCH_WITH_SCHEDULER(256, 128, 128);\n case CutlassTileConfigSM120::Undefined:\n throw std::runtime_error(\"[Error][FP4][dispatch_gemm_cta_shape] Gemm config undefined.\");\n- break;\n case CutlassTileConfigSM120::ChooseWithHeuristic:\n throw std::runtime_error(\n \"[Error][FP4][dispatch_gemm_cta_shape] Gemm config should have already been set by \"\n \"heuristic.\");\n- break;\n default:\n- // For any other SM120 tile configs that we don't support yet, fall back to 128x128x128\n- return dispatchNVFP4xNVFP4GemmClusterShapeSm120<T, cute::Int<128>, cute::Int<128>,\n- cute::Int<128>>(\n- D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n- workspaceBytes, stream, occupancy);\n- break;\n- }\n-}\n+ DISPATCH_WITH_SCHEDULER(128, 128, 128); // Fallback\n+ }\n+}\n+\n+#undef DISPATCH_WITH_SCHEDULER\n+#undef DISPATCH_TILE_CONFIG\n+\n template <typename T, FP4GemmType fp4GemmType>\n CutlassFp4GemmRunner<T, fp4GemmType>::CutlassFp4GemmRunner() {}\n \n@@ -150,11 +168,26 @@\n std::vector<CutlassGemmConfig> CutlassFp4GemmRunner<T, fp4GemmType>::getConfigs() const {\n std::vector<CutlassGemmConfig> candidateConfigs;\n \n- // For SM120/SM121, only support 128x128x128 tile with 1x1x1 cluster shape\n- CutlassGemmConfig config(CutlassTileConfigSM120::CtaShape128x128x128B, MainloopScheduleType::AUTO,\n- EpilogueScheduleType::AUTO, ClusterShape::ClusterShape_1x1x1);\n- candidateConfigs.push_back(config);\n-\n+ // All supported tile configurations for SM120\n+ std::vector<CutlassTileConfigSM120> tilesSm120 = {\n+ CutlassTileConfigSM120::CtaShape128x128x128B,\n+ CutlassTileConfigSM120::CtaShape128x128x256B,\n+ CutlassTileConfigSM120::CtaShape256x128x128B,\n+ };\n+\n+ // SM120 only supports 1x1x1 cluster shape\n+ ClusterShape clusterShape = ClusterShape::ClusterShape_1x1x1;\n+\n+ // Generate configs for both DP and StreamK schedulers\n+ for (auto const& tile_config : tilesSm120) {\n+ // Default DP scheduler (use_stream_k = false)\n+ candidateConfigs.push_back(CutlassGemmConfig(tile_config, MainloopScheduleType::AUTO,\n+ EpilogueScheduleType::AUTO, clusterShape, false));\n+\n+ // StreamK scheduler (use_stream_k = true) - better for small M/N, large K\n+ candidateConfigs.push_back(CutlassGemmConfig(tile_config, MainloopScheduleType::AUTO,\n+ EpilogueScheduleType::AUTO, clusterShape, true));\n+ }\n return candidateConfigs;\n }\n "},"lines_added":{"kind":"number","value":61,"string":"61"},"lines_removed":{"kind":"number","value":28,"string":"28"},"files_in_commit":{"kind":"number","value":4,"string":"4"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["SM120"],"string":"[\n \"SM120\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp4_gemm_cutlass_template_sm120.h).\n\nGoal: perf: add fp4 GEMM tile configs and streamK scheduler for SM120\nTarget hardware: SM120\nTarget models: unspecified\n\nCurrent file:\n```cpp\n/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef FLASHINFER_FP4_GEMM_CUTLASS_TEMPLATE_SM120_H_\n#define FLASHINFER_FP4_GEMM_CUTLASS_TEMPLATE_SM120_H_\n\n#ifndef _WIN32\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wstrict-aliasing\"\n#endif // #ifndef _WIN32\n\n#include \"cutlass/arch/arch.h\"\n#include \"cutlass/cutlass.h\"\n#include \"cutlass/epilogue/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/device/gemm_universal_adapter.h\"\n#include \"cutlass/gemm/gemm.h\"\n#include \"flashinfer/gemm/cutlass_gemm_configs.h\"\n\n#ifndef _WIN32\n#pragma GCC diagnostic pop\n#endif // #ifndef _WIN32\n\n#include \"flashinfer/gemm/fp4_gemm_cutlass.h\"\n\n// Include the SM120-specific template\n#define FLASHINFER_ENABLE_SM120\n#include \"fp4_gemm_template_sm120.h\"\n\nnamespace flashinfer {\nnamespace gemm {\nusing namespace cute;\n\ntemplate <typename T, typename CTA_M_, typename CTA_N_, typename CTA_K_>\nsize_t dispatchNVFP4xNVFP4GemmClusterShapeSm120(T* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k,\n int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes,\n cudaStream_t stream, int* occupancy = nullptr) {\n // For SM120/SM121, only support 1x1x1 cluster shape\n // Always use 1x1x1 cluster shape regardless of gemmConfig.cluster_shape\n return genericFp4GemmKernelLauncher<T, CTA_M_, CTA_N_, CTA_K_, cute::Int<1>, cute::Int<1>,\n cute::Int<1>, _1SM>(\n D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n workspaceBytes, stream, occupancy);\n}\n\n/*!\n * \\brief Dispatch FP4 GEMM operation with CTA shape configuration for SM120/SM121\n * \\param D Output matrix pointer\n * \\param A Input matrix A pointer (FP4 quantized)\n * \\param B Input matrix B pointer (FP4 quantized)\n * \\param input_sf Input scale factors\n * \\param weight_sf Weight scale factors\n * \\param global_sf Global scale factor\n * \\param m Number of rows in matrix A and output matrix D\n * \\param n Number of columns in matrix B and output matrix D\n * \\param k Number of columns in matrix A and rows in matrix B\n * \\param batch_count Number of batches for batched GEMM\n * \\param gemmConfig GEMM configuration including tile size and cluster shape\n * \\param workspace Workspace buffer for temporary storage\n * \\param workspaceBytes Size of workspace buffer in bytes\n * \\param stream CUDA stream for kernel execution\n * \\param occupancy Optional pointer to store kernel occupancy\n * \\return Size of workspace required in bytes\n */\ntemplate <typename T>\nsize_t dispatchNVFP4xNVFP4GemmCTAShapeSm120(T* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k,\n int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes,\n cudaStream_t stream, int* occupancy = nullptr) {\n // For SM120/SM121, we only support 128x128x128 tile configuration\n // Check the SM120 tile config and dispatch accordingly\n switch (gemmConfig.tile_config_sm120) {\n case CutlassTileConfigSM120::CtaShape128x128x128B:\n // Always use 1x1x1 cluster shape for SM120\n return dispatchNVFP4xNVFP4GemmClusterShapeSm120<T, cute::Int<128>, cute::Int<128>,\n cute::Int<128>>(\n D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n workspaceBytes, stream, occupancy);\n break;\n case CutlassTileConfigSM120::Undefined:\n throw std::runtime_error(\"[Error][FP4][dispatch_gemm_cta_shape] Gemm config undefined.\");\n break;\n case CutlassTileConfigSM120::ChooseWithHeuristic:\n throw std::runtime_error(\n \"[Error][FP4][dispatch_gemm_cta_shape] Gemm config should have already been set by \"\n \"heuristic.\");\n break;\n default:\n // For any other SM120 tile configs that we don't support yet, fall back to 128x128x128\n return dispatchNVFP4xNVFP4GemmClusterShapeSm120<T, cute::Int<128>, cute::Int<128>,\n cute::Int<128>>(\n D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count, gemmConfig, workspace,\n workspaceBytes, stream, occupancy);\n break;\n }\n}\ntemplate <typename T, FP4GemmType fp4GemmType>\nCutlassFp4GemmRunner<T, fp4GemmType>::CutlassFp4GemmRunner() {}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nCutlassFp4GemmRunner<T, fp4GemmType>::~CutlassFp4GemmRunner() {}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nsize_t CutlassFp4GemmRunner<T, fp4GemmType>::dispatchToArch(\n T* D, void const* A, void const* B, void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k, int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes, cudaStream_t stream, int* occupancy) {\n if constexpr (fp4GemmType == FP4GemmType::W4A4_NVFP4_NVFP4) {\n return dispatchNVFP4xNVFP4GemmCTAShapeSm120<T>(D, A, B, input_sf, weight_sf, global_sf, m, n, k,\n batch_count, gemmConfig, workspace,\n workspaceBytes, stream, occupancy);\n } else {\n throw std::runtime_error(\n \"[Error][CutlassFp4GemmRunner][GEMM Dispatch] FP4 Gemm type unsupported for \"\n \"CUTLASS FP4 GEMM\");\n }\n}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nvoid CutlassFp4GemmRunner<T, fp4GemmType>::gemm(void* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k,\n int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, const size_t workspaceBytes,\n cudaStream_t stream) {\n CutlassFp4GemmRunner<T, fp4GemmType>::dispatchToArch(\n reinterpret_cast<T*>(D), A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count,\n gemmConfig, workspace, workspaceBytes, stream);\n}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nstd::vector<CutlassGemmConfig> CutlassFp4GemmRunner<T, fp4GemmType>::getConfigs() const {\n std::vector<CutlassGemmConfig> candidateConfigs;\n\n // For SM120/SM121, only support 128x128x128 tile with 1x1x1 cluster shape\n CutlassGemmConfig config(CutlassTileConfigSM120::CtaShape128x128x128B, MainloopScheduleType::AUTO,\n EpilogueScheduleType::AUTO, ClusterShape::ClusterShape_1x1x1);\n candidateConfigs.push_back(config);\n\n return candidateConfigs;\n}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nsize_t CutlassFp4GemmRunner<T, fp4GemmType>::getWorkspaceSizeImpl(int const m, int const n,\n int const k,\n int const batch_count) {\n size_t workspace_size = 0;\n auto gemmConfigs = CutlassFp4GemmRunner<T, fp4GemmType>{}.getConfigs();\n for (auto const& gemmConfig : gemmConfigs) {\n try {\n size_t curr_workspace_size = CutlassFp4GemmRunner<T, fp4GemmType>::dispatchToArch(\n nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, m, n, k, batch_count, gemmConfig,\n nullptr, 0, 0);\n workspace_size = std::max(workspace_size, curr_workspace_size);\n } catch (std::runtime_error& e) {\n // Swallow errors when SMEM exceeds maximum allowed\n continue;\n }\n }\n return workspace_size;\n}\n\ntemplate <typename T, FP4GemmType fp4GemmType>\nsize_t CutlassFp4GemmRunner<T, fp4GemmType>::getWorkspaceSize(int const m, int const n, int const k,\n int const batch_count) {\n // Custom hash function for the MNKB type\n using MNK = std::tuple<int, int, int, int>;\n\n struct MNKHash {\n size_t operator()(const MNK& mnk) const {\n auto h1 = std::hash<int>{}(std::get<0>(mnk));\n auto h2 = std::hash<int>{}(std::get<1>(mnk));\n auto h3 = std::hash<int>{}(std::get<2>(mnk));\n auto h4 = std::hash<int>{}(std::get<3>(mnk));\n return h1 ^ h2 ^ h3 ^ h4;\n }\n };\n\n static std::unordered_map<MNK, size_t, MNKHash> workspace_hashmap;\n\n size_t workspace_size = 0;\n if (workspace_hashmap.find(std::make_tuple(m, n, k, batch_count)) == workspace_hashmap.end()) {\n workspace_size =\n CutlassFp4GemmRunner<T, fp4GemmType>::getWorkspaceSizeImpl(m, n, k, batch_count);\n workspace_hashmap[std::make_tuple(m, n, k, batch_count)] = workspace_size;\n } else {\n workspace_size = workspace_hashmap[std::make_tuple(m, n, k, batch_count)];\n }\n return workspace_size;\n}\n\n} // namespace gemm\n} // namespace flashinfer\n#endif // FLASHINFER_FP4_GEMM_CUTLASS_TEMPLATE_SM120_H_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nAdd SM120 FP4 GEMM tile configs and enable streamK scheduler for configs that can be selected by autotuner.\nTake the problem size m=32, n=5120, k=25600 as an example. After adding these configs, the latency of mm_fp4 kernel reduced from 0.124ms to 0.069ms on RTX PRO 6000.\n\n```\n[PERF] cutlass_autotun:: median time 0.124 ms; std 0.000 ms; achieved tflops 67.751 TFLOPs/sec; achieved tb_per_sec 0.535 TB/sec\n[PERF] cutlass_autotun:: median time 0.069 ms; std 0.000 ms; achieved tflops 121.902 TFLOPs/sec; achieved tb_per_sec 0.963 TB/sec\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n * Added StreamK scheduler option for SM120 FP4 GEMM operations, alongside the existing DP scheduler.\n * Expanded SM120 FP4 GEMM tile configurations with two additional options (128×128×256 and 256×128×128).\n * Extended configuration generation to support all tile shapes with both schedulers for improved optimization flexibility.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"m=32,n=5120,k=25600\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.124, \"optimized\": 0.069, \"stated_speedup\": null, \"speedup\": 1.7971}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"m=32,n=5120,k=25600\", \"batch_size\": null, \"metric\": \"TFLOPS\", \"unit\": \"TFLOPs/sec\", \"higher_is_better\": true, \"baseline\": 67.751, \"optimized\": 121.902, \"stated_speedup\": null, \"speedup\": 1.7993}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"m=32,n=5120,k=25600\", \"batch_size\": null, \"metric\": \"bandwidth\", \"unit\": \"TB/sec\", \"higher_is_better\": true, \"baseline\": 0.535, \"optimized\": 0.963, \"stated_speedup\": null, \"speedup\": 1.8}]"},"kernel_speedup":{"kind":"number","value":1.7993,"string":"1.7993"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1184,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"57ef44b9d7ada00cb50ca26310f9c3a3bfbc0dd2"},"date":{"kind":"string","value":"2026-02-06T14:55:45+08:00"},"pr_number":{"kind":"number","value":2460,"string":"2,460"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2460"},"title":{"kind":"string","value":"perf: add fp4 GEMM tile configs and streamK scheduler for SM120 (#2460)"},"message":{"kind":"string","value":"perf: add fp4 GEMM tile configs and streamK scheduler for SM120 (#2460)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nAdd SM120 FP4 GEMM tile configs and enable streamK scheduler for configs\nthat can be selected by autotuner.\nTake the problem size m=32, n=5120, k=25600 as an example. After adding\nthese configs, the latency of mm_fp4 kernel reduced from 0.124ms to\n0.069ms on RTX PRO 6000.\n\n```\n[PERF] cutlass_autotun:: median time 0.124 ms; std 0.000 ms; achieved tflops 67.751 TFLOPs/sec; achieved tb_per_sec 0.535 TB/sec\n[PERF] cutlass_autotun:: median time 0.069 ms; std 0.000 ms; achieved tflops 121.902 TFLOPs/sec; achieved tb_per_sec 0.963 TB/sec\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n* Added StreamK scheduler option for SM120 FP4 GEMM operations,\nalongside the existing DP scheduler.\n* Expanded SM120 FP4 GEMM tile configurations with two additional\noptions (128×128×256 and 256×128×128).\n* Extended configuration generation to support all tile shapes with both\nschedulers for improved optimization flexibility.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"include/flashinfer/gemm/fp4_gemm_template_sm120.h"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_FP4_GEMM_TEMPLATE_SM120_H_\n#define FLASHINFER_FP4_GEMM_TEMPLATE_SM120_H_\n\n#ifndef _WIN32\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wstrict-aliasing\"\n#endif // #ifndef _WIN32\n\n#include <cuda_bf16.h>\n\n#include <cutlass/detail/sm100_blockscaled_layout.hpp>\n\n#include \"cutlass/arch/arch.h\"\n#include \"cutlass/cutlass.h\"\n#include \"cutlass/epilogue/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/device/gemm_universal_adapter.h\"\n#include \"cutlass/gemm/gemm.h\"\n#include \"flashinfer/arch_condition.h\"\n#include \"flashinfer/cutlass_utils.cuh\"\n\n#ifndef _WIN32\n#pragma GCC diagnostic pop\n#endif // #ifndef _WIN32\n\nnamespace flashinfer {\nnamespace gemm {\nusing namespace cute;\n\n#ifdef ENABLE_BF16\nusing SafeBF16 = __nv_bfloat16;\n#else\nusing SafeBF16 = void;\n#endif\n\nstruct _1SM {};\n\nstruct _2SM {};\n\ntemplate <typename T>\nstruct SMTypeAdapter {};\n\ntemplate <>\nstruct SMTypeAdapter<_1SM> {\n static int const Scale = 1;\n using AtomThrShape = cute::Shape<_1, _1, _1>;\n using EpilogueSchedule = cutlass::epilogue::TmaWarpSpecialized1Sm;\n using MainloopSchedule = cutlass::gemm::KernelTmaWarpSpecialized1SmNvf4Sm100;\n};\n\ntemplate <>\nstruct SMTypeAdapter<_2SM> {\n static int const Scale = 2;\n using AtomThrShape = cute::Shape<_2, _1, _1>;\n using EpilogueSchedule = cutlass::epilogue::TmaWarpSpecialized2Sm;\n using MainloopSchedule = cutlass::gemm::KernelTmaWarpSpecialized2SmNvf4Sm100;\n};\n\ntemplate <typename>\nconstexpr auto always_false = false;\n\ntemplate <typename T, typename CTA_M_, typename CTA_N_, typename CTA_K_, typename CGA_M_,\n typename CGA_N_, typename CGA_K_, typename XSM_>\nsize_t genericFp4GemmKernelLauncher(void* D, void const* A, void const* B, void const* input_sf,\n void const* weight_sf, float const* global_sf, int m, int n,\n int k, int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, size_t const workspaceBytes,\n cudaStream_t stream, int* occupancy);\n\n#ifdef PLACEHOLDER_KERNELS\n\n#define INSTANTIATE_FP4_GEMM_KERNEL_LAUNCHER(T, CTA_M_, CTA_N_, CTA_K_, CGA_M_, CGA_N_, CGA_K_, \\\n XSM_) \\\n template <> \\\n size_t \\\n genericFp4GemmKernelLauncher<T, cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>, \\\n cute::Int<CGA_M_>, cute::Int<CGA_N_>, cute::Int<CGA_K_>, XSM_>( \\\n void* D, void const* A, void const* B, void const* input_sf, void const* weight_sf, \\\n float const* global_sf, int m, int n, int k, int batch_count, CutlassGemmConfig gemmConfig, \\\n char* workspace, const size_t workspaceBytes, cudaStream_t stream, int* occupancy) { \\\n throw std::runtime_error( \\\n \"FP4 gemm kernel is not compiled with support for \" \\\n \"this Architecture.\"); \\\n }\n\n#else\n\n#define INSTANTIATE_FP4_GEMM_KERNEL_LAUNCHER(T, CTA_M_, CTA_N_, CTA_K_, CGA_M_, CGA_N_, CGA_K_, \\\n XSM_) \\\n struct \\\n DeviceGemmFp4GemmSm120_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_##CGA_M_##_##CGA_N_##_##CGA_K_##XSM_ { \\\n using OutElementType = typename flashinfer::cutlass_dtype<T>::type; \\\n using CTAShape = cute::Shape<cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>>; \\\n using Arch = cutlass::arch::Sm120; /* Use Sm120 for SM121 hardware */ \\\n /* For SM120/SM121, always use 1x1x1 cluster shape regardless of macro parameters */ \\\n using ClusterShape = cute::Shape<_1, _1, _1>; \\\n /* // Input A - Use nv_float4_t like example 79 */ \\\n using ElementA = cutlass::nv_float4_t<cutlass::float_e2m1_t>; \\\n using LayoutA = cutlass::layout::RowMajor; \\\n static constexpr int AlignmentA = 32; /* Fixed for nv_float4_t */ \\\n /* // Input B - Use nv_float4_t like example 79 */ \\\n using ElementB = cutlass::nv_float4_t<cutlass::float_e2m1_t>; \\\n using LayoutB = cutlass::layout::ColumnMajor; \\\n static constexpr int AlignmentB = 32; /* Fixed for nv_float4_t */ \\\n /* // Input C */ \\\n using ElementC = void; \\\n using LayoutC = cutlass::layout::RowMajor; \\\n static constexpr int AlignmentC = 128 / cutlass::sizeof_bits<OutElementType>::value; \\\n \\\n using SFType = cutlass::float_ue4m3_t; /* Scale factor type */ \\\n using ElementCompute = float; \\\n using ElementAccumulator = float; \\\n using OperatorClass = cutlass::arch::OpClassBlockScaledTensorOp; \\\n using EpilogueTileType = \\\n cutlass::epilogue::collective::EpilogueTileAuto; /* Always use auto for SM100 */ \\\n using EpilogueSchedule = cutlass::epilogue::collective::EpilogueScheduleAuto; \\\n using MainloopSchedule = cutlass::gemm::collective::KernelScheduleAuto; \\\n using ThreadBlockShape = cute::Shape<cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>>; \\\n using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder< \\\n Arch, OperatorClass, ThreadBlockShape, ClusterShape, EpilogueTileType, ElementAccumulator, \\\n ElementCompute, ElementC, LayoutC, AlignmentC, OutElementType, LayoutC, AlignmentC, \\\n EpilogueSchedule, \\\n cutlass::epilogue::fusion::LinearCombination<OutElementType, float, void, \\\n float>>::CollectiveOp; \\\n \\\n /* SM120 BlockScaled - Use nv_float4_t without tuples like example 79 */ \\\n /* Use fixed 2 stages for SM120 to meet minimum requirement */ \\\n using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder< \\\n Arch, OperatorClass, ElementA, LayoutA, AlignmentA, ElementB, LayoutB, AlignmentB, \\\n ElementAccumulator, ThreadBlockShape, ClusterShape, \\\n cutlass::gemm::collective::StageCount<2>, /* Fixed 2 stages for SM120 */ \\\n cutlass::gemm::collective::KernelScheduleAuto>::CollectiveOp; \\\n \\\n /* Match example 79 - no wrapper needed */ \\\n using GemmKernel = cutlass::gemm::kernel::GemmUniversal< \\\n cute::Shape<int, int, int, int>, /* Indicates ProblemShape */ \\\n CollectiveMainloop, CollectiveEpilogue, void>; /* No persistent scheduler for SM120 */ \\\n \\\n using Gemm = typename cutlass::gemm::device::GemmUniversalAdapter<GemmKernel>; \\\n }; \\\n \\\n using Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_ = \\\n DeviceGemmFp4GemmSm120_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_##CGA_M_##_##CGA_N_##_##CGA_K_##XSM_:: \\\n Gemm; \\\n \\\n inline typename Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_::Arguments \\\n prepareGemmArgs_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_( \\\n void* D, void const* A, void const* B, void const* input_sf, void const* weight_sf, \\\n float const* global_sf, int m, int n, int k, int batch_count) { \\\n using Gemm = Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_; \\\n using Sm1xxBlkScaledConfig = \\\n typename Gemm::GemmKernel::CollectiveMainloop::Sm1xxBlkScaledConfig; \\\n /* Note: For nv_float4_t, scale factors are handled internally */ \\\n using ElementC = void; \\\n using ElementD = typename Gemm::ElementD; \\\n using ElementCompute = float; \\\n \\\n typename Gemm::Arguments operator_args; \\\n operator_args.mode = cutlass::gemm::GemmUniversalMode::kGemm; \\\n auto& fusion_args = operator_args.epilogue.thread; \\\n fusion_args.alpha_ptr = static_cast<ElementCompute const*>(global_sf); \\\n \\\n operator_args.problem_shape = cute::make_shape(m, n, k, batch_count); \\\n \\\n /* For nv_float4_t, data and scale factors are stored separately */ \\\n operator_args.mainloop.ptr_A = static_cast<cutlass::float_e2m1_t const*>(A); \\\n operator_args.mainloop.ptr_B = static_cast<cutlass::float_e2m1_t const*>(B); \\\n operator_args.mainloop.ptr_SFA = static_cast<cutlass::float_ue4m3_t const*>(input_sf); \\\n operator_args.mainloop.ptr_SFB = static_cast<cutlass::float_ue4m3_t const*>(weight_sf); \\\n operator_args.epilogue.ptr_C = static_cast<ElementC const*>(D); \\\n operator_args.epilogue.ptr_D = static_cast<ElementD*>(D); \\\n \\\n int const stride_A = batch_count == 1 ? 0 : m * k; \\\n int const stride_B = batch_count == 1 ? 0 : n * k; \\\n int const stride_C = batch_count == 1 ? 0 : m * n; \\\n \\\n operator_args.mainloop.dA = \\\n cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideA>(k, stride_A); \\\n operator_args.mainloop.dB = \\\n cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideB>(k, stride_B); \\\n operator_args.epilogue.dC = \\\n cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideC>(n, stride_C); \\\n operator_args.epilogue.dD = operator_args.epilogue.dC; \\\n \\\n operator_args.mainloop.layout_SFA = \\\n Sm1xxBlkScaledConfig::tile_atom_to_shape_SFA(operator_args.problem_shape); \\\n operator_args.mainloop.layout_SFB = \\\n Sm1xxBlkScaledConfig::tile_atom_to_shape_SFB(operator_args.problem_shape); \\\n \\\n if constexpr (!std::is_const_v<decltype(operator_args.scheduler.max_swizzle_size)>) { \\\n operator_args.scheduler.max_swizzle_size = 1; \\\n } \\\n if constexpr (!std::is_const_v<decltype(operator_args.scheduler.raster_order)>) { \\\n using Enum_t = decltype(operator_args.scheduler.raster_order); \\\n operator_args.scheduler.raster_order = Enum_t::Heuristic; \\\n } \\\n operator_args.hw_info.cluster_shape = dim3(1, 1, 1); /* SM120 requires 1x1x1 */ \\\n operator_args.hw_info.cluster_shape_fallback = dim3(1, 1, 1); \\\n \\\n return operator_args; \\\n } \\\n \\\n template <> \\\n size_t \\\n genericFp4GemmKernelLauncher<T, cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>, \\\n cute::Int<CGA_M_>, cute::Int<CGA_N_>, cute::Int<CGA_K_>, XSM_>( \\\n void* D, void const* A, void const* B, void const* input_sf, void const* weight_sf, \\\n float const* global_sf, int m, int n, int k, int batch_count, CutlassGemmConfig gemmConfig, \\\n char* workspace, const size_t workspaceBytes, cudaStream_t stream, int* occupancy) { \\\n using ElementOutput__ = \\\n typename cutlass::platform::conditional<cutlass::platform::is_same<T, half>::value, \\\n cutlass::half_t, T>::type; \\\n using ElementOutput_ = typename cutlass::platform::conditional< \\\n cutlass::platform::is_same<ElementOutput__, float>::value, float, ElementOutput__>::type; \\\n using ElementOutput = typename cutlass::platform::conditional< \\\n cutlass::platform::is_same<ElementOutput_, SafeBF16>::value, cutlass::bfloat16_t, \\\n ElementOutput_>::type; \\\n \\\n using Fp4GemmOperator = Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_; \\\n Fp4GemmOperator gemm; \\\n auto args = prepareGemmArgs_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_( \\\n D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count); \\\n /* // Return workspace size */ \\\n if (!A && !B && !D) { \\\n return gemm.get_workspace_size(args); \\\n } \\\n if (gemm.get_workspace_size(args) > workspaceBytes) { \\\n std::string errMsg(\"Requested workspace size insufficient. Required \" + \\\n std::to_string(gemm.get_workspace_size(args)) + \", got \" + \\\n std::to_string(workspaceBytes)); \\\n throw std::runtime_error(\"[FP4 gemm Runner] \" + errMsg); \\\n } \\\n auto can_implement = gemm.can_implement(args); \\\n if (can_implement != cutlass::Status::kSuccess) { \\\n std::string errMsg = \"FP4 Gemm cutlass kernel will fail for params. Error: \" + \\\n std::string(cutlass::cutlassGetStatusString(can_implement)); \\\n throw std::runtime_error(\"[FP4 gemm Runner] \" + errMsg); \\\n } \\\n auto initStatus = gemm.initialize(args, workspace, stream); \\\n if (initStatus != cutlass::Status::kSuccess) { \\\n std::string errMsg = \"Failed to initialize cutlass FP4 gemm on sm120. Error: \" + \\\n std::string(cutlass::cutlassGetStatusString(initStatus)); \\\n throw std::runtime_error(\"[FP4 gemm Runner] \" + errMsg); \\\n } \\\n auto runStatus = gemm.run(args, workspace, stream, nullptr, /*enablePDL=*/true); \\\n if (runStatus != cutlass::Status::kSuccess) { \\\n std::string errMsg = \"Failed to run cutlass FP4 gemm on sm120. Error: \" + \\\n std::string(cutlass::cutlassGetStatusString(runStatus)); \\\n throw std::runtime_error(\"[FP4 gemm Runner] \" + errMsg); \\\n } \\\n return gemm.get_workspace_size(args); \\\n }\n\n#endif\n\n} // namespace gemm\n} // namespace flashinfer\n#endif // FLASHINFER_FP4_GEMM_TEMPLATE_SM120_H_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_FP4_GEMM_TEMPLATE_SM120_H_\n#define FLASHINFER_FP4_GEMM_TEMPLATE_SM120_H_\n\n#ifndef _WIN32\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wstrict-aliasing\"\n#endif // #ifndef _WIN32\n\n#include <cuda_bf16.h>\n\n#include <cutlass/detail/sm100_blockscaled_layout.hpp>\n\n#include \"cutlass/arch/arch.h\"\n#include \"cutlass/cutlass.h\"\n#include \"cutlass/epilogue/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/device/gemm_universal_adapter.h\"\n#include \"cutlass/gemm/gemm.h\"\n#include \"cutlass/gemm/kernel/tile_scheduler.hpp\"\n#include \"flashinfer/arch_condition.h\"\n#include \"flashinfer/cutlass_utils.cuh\"\n\n#ifndef _WIN32\n#pragma GCC diagnostic pop\n#endif // #ifndef _WIN32\n\nnamespace flashinfer {\nnamespace gemm {\nusing namespace cute;\n\n#ifdef ENABLE_BF16\nusing SafeBF16 = __nv_bfloat16;\n#else\nusing SafeBF16 = void;\n#endif\n\nstruct _1SM {};\n\nstruct _2SM {};\n\ntemplate <typename T>\nstruct SMTypeAdapter {};\n\ntemplate <>\nstruct SMTypeAdapter<_1SM> {\n static int const Scale = 1;\n using AtomThrShape = cute::Shape<_1, _1, _1>;\n using EpilogueSchedule = cutlass::epilogue::TmaWarpSpecialized1Sm;\n using MainloopSchedule = cutlass::gemm::KernelTmaWarpSpecialized1SmNvf4Sm100;\n};\n\ntemplate <>\nstruct SMTypeAdapter<_2SM> {\n static int const Scale = 2;\n using AtomThrShape = cute::Shape<_2, _1, _1>;\n using EpilogueSchedule = cutlass::epilogue::TmaWarpSpecialized2Sm;\n using MainloopSchedule = cutlass::gemm::KernelTmaWarpSpecialized2SmNvf4Sm100;\n};\n\ntemplate <typename>\nconstexpr auto always_false = false;\n\ntemplate <typename T, typename CTA_M_, typename CTA_N_, typename CTA_K_, typename CGA_M_,\n typename CGA_N_, typename CGA_K_, typename XSM_>\nsize_t genericFp4GemmKernelLauncher(void* D, void const* A, void const* B, void const* input_sf,\n void const* weight_sf, float const* global_sf, int m, int n,\n int k, int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, size_t const workspaceBytes,\n cudaStream_t stream, int* occupancy);\n\ntemplate <typename T, typename CTA_M_, typename CTA_N_, typename CTA_K_, typename CGA_M_,\n typename CGA_N_, typename CGA_K_, typename XSM_>\nsize_t genericFp4GemmKernelLauncherStreamK(void* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k,\n int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, size_t const workspaceBytes,\n cudaStream_t stream, int* occupancy);\n\n// ============================================================================\n// Common helper functions to reduce code duplication\n// ============================================================================\n\n// Unified prepareGemmArgs - works for both DP and StreamK schedulers\ntemplate <typename Gemm>\ninline typename Gemm::Arguments prepareGemmArgsImpl(void* D, void const* A, void const* B,\n void const* input_sf, void const* weight_sf,\n float const* global_sf, int m, int n, int k,\n int batch_count) {\n using Sm1xxBlkScaledConfig = typename Gemm::GemmKernel::CollectiveMainloop::Sm1xxBlkScaledConfig;\n using ElementC = void;\n using ElementD = typename Gemm::ElementD;\n using ElementCompute = float;\n\n typename Gemm::Arguments operator_args;\n operator_args.mode = cutlass::gemm::GemmUniversalMode::kGemm;\n operator_args.epilogue.thread.alpha_ptr = static_cast<ElementCompute const*>(global_sf);\n operator_args.problem_shape = cute::make_shape(m, n, k, batch_count);\n\n operator_args.mainloop.ptr_A = static_cast<cutlass::float_e2m1_t const*>(A);\n operator_args.mainloop.ptr_B = static_cast<cutlass::float_e2m1_t const*>(B);\n operator_args.mainloop.ptr_SFA = static_cast<cutlass::float_ue4m3_t const*>(input_sf);\n operator_args.mainloop.ptr_SFB = static_cast<cutlass::float_ue4m3_t const*>(weight_sf);\n operator_args.epilogue.ptr_C = static_cast<ElementC const*>(D);\n operator_args.epilogue.ptr_D = static_cast<ElementD*>(D);\n\n int const stride_A = batch_count == 1 ? 0 : m * k;\n int const stride_B = batch_count == 1 ? 0 : n * k;\n int const stride_C = batch_count == 1 ? 0 : m * n;\n\n operator_args.mainloop.dA =\n cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideA>(k, stride_A);\n operator_args.mainloop.dB =\n cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideB>(k, stride_B);\n operator_args.epilogue.dC =\n cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideC>(n, stride_C);\n operator_args.epilogue.dD = operator_args.epilogue.dC;\n\n operator_args.mainloop.layout_SFA =\n Sm1xxBlkScaledConfig::tile_atom_to_shape_SFA(operator_args.problem_shape);\n operator_args.mainloop.layout_SFB =\n Sm1xxBlkScaledConfig::tile_atom_to_shape_SFB(operator_args.problem_shape);\n\n if constexpr (!std::is_const_v<decltype(operator_args.scheduler.max_swizzle_size)>) {\n operator_args.scheduler.max_swizzle_size = 1;\n }\n if constexpr (!std::is_const_v<decltype(operator_args.scheduler.raster_order)>) {\n using Enum_t = decltype(operator_args.scheduler.raster_order);\n operator_args.scheduler.raster_order = Enum_t::Heuristic;\n }\n operator_args.hw_info.cluster_shape = dim3(1, 1, 1);\n operator_args.hw_info.cluster_shape_fallback = dim3(1, 1, 1);\n\n return operator_args;\n}\n\n// Unified runGemm - works for both DP and StreamK schedulers\ntemplate <typename Gemm>\ninline size_t runFp4GemmImpl(void* D, void const* A, void const* B, void const* input_sf,\n void const* weight_sf, float const* global_sf, int m, int n, int k,\n int batch_count, char* workspace, size_t const workspaceBytes,\n cudaStream_t stream, const char* scheduler_name) {\n Gemm gemm;\n auto args =\n prepareGemmArgsImpl<Gemm>(D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count);\n\n // Return workspace size query\n if (!A && !B && !D) {\n return gemm.get_workspace_size(args);\n }\n\n if (gemm.get_workspace_size(args) > workspaceBytes) {\n throw std::runtime_error(std::string(\"[FP4 gemm Runner\") + scheduler_name + \"] \" +\n \"Requested workspace size insufficient. Required \" +\n std::to_string(gemm.get_workspace_size(args)) + \", got \" +\n std::to_string(workspaceBytes));\n }\n\n auto can_implement = gemm.can_implement(args);\n if (can_implement != cutlass::Status::kSuccess) {\n throw std::runtime_error(std::string(\"[FP4 gemm Runner\") + scheduler_name + \"] \" +\n \"FP4 Gemm cutlass kernel will fail for params. Error: \" +\n std::string(cutlass::cutlassGetStatusString(can_implement)));\n }\n\n auto initStatus = gemm.initialize(args, workspace, stream);\n if (initStatus != cutlass::Status::kSuccess) {\n throw std::runtime_error(std::string(\"[FP4 gemm Runner\") + scheduler_name + \"] \" +\n \"Failed to initialize cutlass FP4 gemm on sm120. Error: \" +\n std::string(cutlass::cutlassGetStatusString(initStatus)));\n }\n\n auto runStatus = gemm.run(args, workspace, stream, nullptr, /*enablePDL=*/true);\n if (runStatus != cutlass::Status::kSuccess) {\n throw std::runtime_error(std::string(\"[FP4 gemm Runner\") + scheduler_name + \"] \" +\n \"Failed to run cutlass FP4 gemm on sm120. Error: \" +\n std::string(cutlass::cutlassGetStatusString(runStatus)));\n }\n\n return gemm.get_workspace_size(args);\n}\n\n#ifdef PLACEHOLDER_KERNELS\n\n#define INSTANTIATE_FP4_GEMM_KERNEL_LAUNCHER(T, CTA_M_, CTA_N_, CTA_K_, CGA_M_, CGA_N_, CGA_K_, \\\n XSM_) \\\n template <> \\\n size_t \\\n genericFp4GemmKernelLauncher<T, cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>, \\\n cute::Int<CGA_M_>, cute::Int<CGA_N_>, cute::Int<CGA_K_>, XSM_>( \\\n void* D, void const* A, void const* B, void const* input_sf, void const* weight_sf, \\\n float const* global_sf, int m, int n, int k, int batch_count, CutlassGemmConfig gemmConfig, \\\n char* workspace, const size_t workspaceBytes, cudaStream_t stream, int* occupancy) { \\\n throw std::runtime_error( \\\n \"FP4 gemm kernel is not compiled with support for \" \\\n \"this Architecture.\"); \\\n }\n\n#else\n\n#define INSTANTIATE_FP4_GEMM_KERNEL_LAUNCHER(T, CTA_M_, CTA_N_, CTA_K_, CGA_M_, CGA_N_, CGA_K_, \\\n XSM_) \\\n struct \\\n DeviceGemmFp4GemmSm120_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_##CGA_M_##_##CGA_N_##_##CGA_K_##XSM_ { \\\n using OutElementType = typename flashinfer::cutlass_dtype<T>::type; \\\n using CTAShape = cute::Shape<cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>>; \\\n using Arch = cutlass::arch::Sm120; /* Use Sm120 for SM121 hardware */ \\\n /* For SM120/SM121, always use 1x1x1 cluster shape regardless of macro parameters */ \\\n using ClusterShape = cute::Shape<_1, _1, _1>; \\\n /* // Input A - Use nv_float4_t like example 79 */ \\\n using ElementA = cutlass::nv_float4_t<cutlass::float_e2m1_t>; \\\n using LayoutA = cutlass::layout::RowMajor; \\\n static constexpr int AlignmentA = 32; /* Fixed for nv_float4_t */ \\\n /* // Input B - Use nv_float4_t like example 79 */ \\\n using ElementB = cutlass::nv_float4_t<cutlass::float_e2m1_t>; \\\n using LayoutB = cutlass::layout::ColumnMajor; \\\n static constexpr int AlignmentB = 32; /* Fixed for nv_float4_t */ \\\n /* // Input C */ \\\n using ElementC = void; \\\n using LayoutC = cutlass::layout::RowMajor; \\\n static constexpr int AlignmentC = 128 / cutlass::sizeof_bits<OutElementType>::value; \\\n \\\n using SFType = cutlass::float_ue4m3_t; /* Scale factor type */ \\\n using ElementCompute = float; \\\n using ElementAccumulator = float; \\\n using OperatorClass = cutlass::arch::OpClassBlockScaledTensorOp; \\\n using EpilogueTileType = \\\n cutlass::epilogue::collective::EpilogueTileAuto; /* Always use auto for SM100 */ \\\n using EpilogueSchedule = cutlass::epilogue::collective::EpilogueScheduleAuto; \\\n using MainloopSchedule = cutlass::gemm::collective::KernelScheduleAuto; \\\n using ThreadBlockShape = cute::Shape<cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>>; \\\n using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder< \\\n Arch, OperatorClass, ThreadBlockShape, ClusterShape, EpilogueTileType, ElementAccumulator, \\\n ElementCompute, ElementC, LayoutC, AlignmentC, OutElementType, LayoutC, AlignmentC, \\\n EpilogueSchedule, \\\n cutlass::epilogue::fusion::LinearCombination<OutElementType, float, void, \\\n float>>::CollectiveOp; \\\n \\\n /* SM120 BlockScaled - Use nv_float4_t without tuples like example 79 */ \\\n /* Use fixed 2 stages for SM120 to meet minimum requirement */ \\\n using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder< \\\n Arch, OperatorClass, ElementA, LayoutA, AlignmentA, ElementB, LayoutB, AlignmentB, \\\n ElementAccumulator, ThreadBlockShape, ClusterShape, \\\n cutlass::gemm::collective::StageCount<2>, /* Fixed 2 stages for SM120 */ \\\n cutlass::gemm::collective::KernelScheduleAuto>::CollectiveOp; \\\n \\\n /* Two scheduler options for different workloads */ \\\n /* See: https://github.com/NVIDIA/cutlass/blob/main/examples/79_blackwell_geforce_gemm */ \\\n \\\n /* Option 1: Default scheduler (void) - Data Parallel, good for regular shapes */ \\\n using GemmKernelDefault = cutlass::gemm::kernel::GemmUniversal< \\\n cute::Shape<int, int, int, int>, /* Indicates ProblemShape */ \\\n CollectiveMainloop, CollectiveEpilogue, void>; /* Default DP scheduler */ \\\n \\\n /* Option 2: StreamK scheduler - better load balancing for small M/N, large K */ \\\n using GemmKernelStreamK = cutlass::gemm::kernel::GemmUniversal< \\\n cute::Shape<int, int, int, int>, /* Indicates ProblemShape */ \\\n CollectiveMainloop, CollectiveEpilogue, \\\n cutlass::gemm::StreamKScheduler>; /* StreamK scheduler */ \\\n \\\n using GemmDefault = typename cutlass::gemm::device::GemmUniversalAdapter<GemmKernelDefault>; \\\n using GemmStreamK = typename cutlass::gemm::device::GemmUniversalAdapter<GemmKernelStreamK>; \\\n using Gemm = GemmDefault; /* Default alias for compatibility */ \\\n }; \\\n \\\n /* Type aliases for DP and StreamK schedulers */ \\\n using Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_ = \\\n DeviceGemmFp4GemmSm120_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_##CGA_M_##_##CGA_N_##_##CGA_K_##XSM_:: \\\n GemmDefault; \\\n \\\n using Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_StreamK = \\\n DeviceGemmFp4GemmSm120_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_##CGA_M_##_##CGA_N_##_##CGA_K_##XSM_:: \\\n GemmStreamK; \\\n \\\n /* DP scheduler launcher - uses common helper functions */ \\\n template <> \\\n size_t \\\n genericFp4GemmKernelLauncher<T, cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>, \\\n cute::Int<CGA_M_>, cute::Int<CGA_N_>, cute::Int<CGA_K_>, XSM_>( \\\n void* D, void const* A, void const* B, void const* input_sf, void const* weight_sf, \\\n float const* global_sf, int m, int n, int k, int batch_count, CutlassGemmConfig gemmConfig, \\\n char* workspace, const size_t workspaceBytes, cudaStream_t stream, int* occupancy) { \\\n using Fp4GemmOperator = Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_; \\\n return runFp4GemmImpl<Fp4GemmOperator>(D, A, B, input_sf, weight_sf, global_sf, m, n, k, \\\n batch_count, workspace, workspaceBytes, stream, \"\"); \\\n } \\\n \\\n /* StreamK scheduler launcher - uses common helper functions */ \\\n template <> \\\n size_t genericFp4GemmKernelLauncherStreamK<T, cute::Int<CTA_M_>, cute::Int<CTA_N_>, \\\n cute::Int<CTA_K_>, cute::Int<CGA_M_>, \\\n cute::Int<CGA_N_>, cute::Int<CGA_K_>, XSM_>( \\\n void* D, void const* A, void const* B, void const* input_sf, void const* weight_sf, \\\n float const* global_sf, int m, int n, int k, int batch_count, CutlassGemmConfig gemmConfig, \\\n char* workspace, const size_t workspaceBytes, cudaStream_t stream, int* occupancy) { \\\n using Fp4GemmOperator = Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_StreamK; \\\n return runFp4GemmImpl<Fp4GemmOperator>(D, A, B, input_sf, weight_sf, global_sf, m, n, k, \\\n batch_count, workspace, workspaceBytes, stream, \\\n \" StreamK\"); \\\n }\n\n#endif\n\n} // namespace gemm\n} // namespace flashinfer\n#endif // FLASHINFER_FP4_GEMM_TEMPLATE_SM120_H_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/gemm/fp4_gemm_template_sm120.h\n+++ include/flashinfer/gemm/fp4_gemm_template_sm120.h\n@@ -31,6 +31,7 @@\n #include \"cutlass/gemm/collective/collective_builder.hpp\"\n #include \"cutlass/gemm/device/gemm_universal_adapter.h\"\n #include \"cutlass/gemm/gemm.h\"\n+#include \"cutlass/gemm/kernel/tile_scheduler.hpp\"\n #include \"flashinfer/arch_condition.h\"\n #include \"flashinfer/cutlass_utils.cuh\"\n \n@@ -81,6 +82,118 @@\n int k, int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, size_t const workspaceBytes,\n cudaStream_t stream, int* occupancy);\n+\n+template <typename T, typename CTA_M_, typename CTA_N_, typename CTA_K_, typename CGA_M_,\n+ typename CGA_N_, typename CGA_K_, typename XSM_>\n+size_t genericFp4GemmKernelLauncherStreamK(void* D, void const* A, void const* B,\n+ void const* input_sf, void const* weight_sf,\n+ float const* global_sf, int m, int n, int k,\n+ int batch_count, CutlassGemmConfig gemmConfig,\n+ char* workspace, size_t const workspaceBytes,\n+ cudaStream_t stream, int* occupancy);\n+\n+// ============================================================================\n+// Common helper functions to reduce code duplication\n+// ============================================================================\n+\n+// Unified prepareGemmArgs - works for both DP and StreamK schedulers\n+template <typename Gemm>\n+inline typename Gemm::Arguments prepareGemmArgsImpl(void* D, void const* A, void const* B,\n+ void const* input_sf, void const* weight_sf,\n+ float const* global_sf, int m, int n, int k,\n+ int batch_count) {\n+ using Sm1xxBlkScaledConfig = typename Gemm::GemmKernel::CollectiveMainloop::Sm1xxBlkScaledConfig;\n+ using ElementC = void;\n+ using ElementD = typename Gemm::ElementD;\n+ using ElementCompute = float;\n+\n+ typename Gemm::Arguments operator_args;\n+ operator_args.mode = cutlass::gemm::GemmUniversalMode::kGemm;\n+ operator_args.epilogue.thread.alpha_ptr = static_cast<ElementCompute const*>(global_sf);\n+ operator_args.problem_shape = cute::make_shape(m, n, k, batch_count);\n+\n+ operator_args.mainloop.ptr_A = static_cast<cutlass::float_e2m1_t const*>(A);\n+ operator_args.mainloop.ptr_B = static_cast<cutlass::float_e2m1_t const*>(B);\n+ operator_args.mainloop.ptr_SFA = static_cast<cutlass::float_ue4m3_t const*>(input_sf);\n+ operator_args.mainloop.ptr_SFB = static_cast<cutlass::float_ue4m3_t const*>(weight_sf);\n+ operator_args.epilogue.ptr_C = static_cast<ElementC const*>(D);\n+ operator_args.epilogue.ptr_D = static_cast<ElementD*>(D);\n+\n+ int const stride_A = batch_count == 1 ? 0 : m * k;\n+ int const stride_B = batch_count == 1 ? 0 : n * k;\n+ int const stride_C = batch_count == 1 ? 0 : m * n;\n+\n+ operator_args.mainloop.dA =\n+ cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideA>(k, stride_A);\n+ operator_args.mainloop.dB =\n+ cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideB>(k, stride_B);\n+ operator_args.epilogue.dC =\n+ cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideC>(n, stride_C);\n+ operator_args.epilogue.dD = operator_args.epilogue.dC;\n+\n+ operator_args.mainloop.layout_SFA =\n+ Sm1xxBlkScaledConfig::tile_atom_to_shape_SFA(operator_args.problem_shape);\n+ operator_args.mainloop.layout_SFB =\n+ Sm1xxBlkScaledConfig::tile_atom_to_shape_SFB(operator_args.problem_shape);\n+\n+ if constexpr (!std::is_const_v<decltype(operator_args.scheduler.max_swizzle_size)>) {\n+ operator_args.scheduler.max_swizzle_size = 1;\n+ }\n+ if constexpr (!std::is_const_v<decltype(operator_args.scheduler.raster_order)>) {\n+ using Enum_t = decltype(operator_args.scheduler.raster_order);\n+ operator_args.scheduler.raster_order = Enum_t::Heuristic;\n+ }\n+ operator_args.hw_info.cluster_shape = dim3(1, 1, 1);\n+ operator_args.hw_info.cluster_shape_fallback = dim3(1, 1, 1);\n+\n+ return operator_args;\n+}\n+\n+// Unified runGemm - works for both DP and StreamK schedulers\n+template <typename Gemm>\n+inline size_t runFp4GemmImpl(void* D, void const* A, void const* B, void const* input_sf,\n+ void const* weight_sf, float const* global_sf, int m, int n, int k,\n+ int batch_count, char* workspace, size_t const workspaceBytes,\n+ cudaStream_t stream, const char* scheduler_name) {\n+ Gemm gemm;\n+ auto args =\n+ prepareGemmArgsImpl<Gemm>(D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count);\n+\n+ // Return workspace size query\n+ if (!A && !B && !D) {\n+ return gemm.get_workspace_size(args);\n+ }\n+\n+ if (gemm.get_workspace_size(args) > workspaceBytes) {\n+ throw std::runtime_error(std::string(\"[FP4 gemm Runner\") + scheduler_name + \"] \" +\n+ \"Requested workspace size insufficient. Required \" +\n+ std::to_string(gemm.get_workspace_size(args)) + \", got \" +\n+ std::to_string(workspaceBytes));\n+ }\n+\n+ auto can_implement = gemm.can_implement(args);\n+ if (can_implement != cutlass::Status::kSuccess) {\n+ throw std::runtime_error(std::string(\"[FP4 gemm Runner\") + scheduler_name + \"] \" +\n+ \"FP4 Gemm cutlass kernel will fail for params. Error: \" +\n+ std::string(cutlass::cutlassGetStatusString(can_implement)));\n+ }\n+\n+ auto initStatus = gemm.initialize(args, workspace, stream);\n+ if (initStatus != cutlass::Status::kSuccess) {\n+ throw std::runtime_error(std::string(\"[FP4 gemm Runner\") + scheduler_name + \"] \" +\n+ \"Failed to initialize cutlass FP4 gemm on sm120. Error: \" +\n+ std::string(cutlass::cutlassGetStatusString(initStatus)));\n+ }\n+\n+ auto runStatus = gemm.run(args, workspace, stream, nullptr, /*enablePDL=*/true);\n+ if (runStatus != cutlass::Status::kSuccess) {\n+ throw std::runtime_error(std::string(\"[FP4 gemm Runner\") + scheduler_name + \"] \" +\n+ \"Failed to run cutlass FP4 gemm on sm120. Error: \" +\n+ std::string(cutlass::cutlassGetStatusString(runStatus)));\n+ }\n+\n+ return gemm.get_workspace_size(args);\n+}\n \n #ifdef PLACEHOLDER_KERNELS\n \n@@ -146,75 +259,35 @@\n cutlass::gemm::collective::StageCount<2>, /* Fixed 2 stages for SM120 */ \\\n cutlass::gemm::collective::KernelScheduleAuto>::CollectiveOp; \\\n \\\n- /* Match example 79 - no wrapper needed */ \\\n- using GemmKernel = cutlass::gemm::kernel::GemmUniversal< \\\n+ /* Two scheduler options for different workloads */ \\\n+ /* See: https://github.com/NVIDIA/cutlass/blob/main/examples/79_blackwell_geforce_gemm */ \\\n+ \\\n+ /* Option 1: Default scheduler (void) - Data Parallel, good for regular shapes */ \\\n+ using GemmKernelDefault = cutlass::gemm::kernel::GemmUniversal< \\\n cute::Shape<int, int, int, int>, /* Indicates ProblemShape */ \\\n- CollectiveMainloop, CollectiveEpilogue, void>; /* No persistent scheduler for SM120 */ \\\n- \\\n- using Gemm = typename cutlass::gemm::device::GemmUniversalAdapter<GemmKernel>; \\\n+ CollectiveMainloop, CollectiveEpilogue, void>; /* Default DP scheduler */ \\\n+ \\\n+ /* Option 2: StreamK scheduler - better load balancing for small M/N, large K */ \\\n+ using GemmKernelStreamK = cutlass::gemm::kernel::GemmUniversal< \\\n+ cute::Shape<int, int, int, int>, /* Indicates ProblemShape */ \\\n+ CollectiveMainloop, CollectiveEpilogue, \\\n+ cutlass::gemm::StreamKScheduler>; /* StreamK scheduler */ \\\n+ \\\n+ using GemmDefault = typename cutlass::gemm::device::GemmUniversalAdapter<GemmKernelDefault>; \\\n+ using GemmStreamK = typename cutlass::gemm::device::GemmUniversalAdapter<GemmKernelStreamK>; \\\n+ using Gemm = GemmDefault; /* Default alias for compatibility */ \\\n }; \\\n \\\n+ /* Type aliases for DP and StreamK schedulers */ \\\n using Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_ = \\\n DeviceGemmFp4GemmSm120_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_##CGA_M_##_##CGA_N_##_##CGA_K_##XSM_:: \\\n- Gemm; \\\n- \\\n- inline typename Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_::Arguments \\\n- prepareGemmArgs_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_( \\\n- void* D, void const* A, void const* B, void const* input_sf, void const* weight_sf, \\\n- float const* global_sf, int m, int n, int k, int batch_count) { \\\n- using Gemm = Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_; \\\n- using Sm1xxBlkScaledConfig = \\\n- typename Gemm::GemmKernel::CollectiveMainloop::Sm1xxBlkScaledConfig; \\\n- /* Note: For nv_float4_t, scale factors are handled internally */ \\\n- using ElementC = void; \\\n- using ElementD = typename Gemm::ElementD; \\\n- using ElementCompute = float; \\\n- \\\n- typename Gemm::Arguments operator_args; \\\n- operator_args.mode = cutlass::gemm::GemmUniversalMode::kGemm; \\\n- auto& fusion_args = operator_args.epilogue.thread; \\\n- fusion_args.alpha_ptr = static_cast<ElementCompute const*>(global_sf); \\\n- \\\n- operator_args.problem_shape = cute::make_shape(m, n, k, batch_count); \\\n- \\\n- /* For nv_float4_t, data and scale factors are stored separately */ \\\n- operator_args.mainloop.ptr_A = static_cast<cutlass::float_e2m1_t const*>(A); \\\n- operator_args.mainloop.ptr_B = static_cast<cutlass::float_e2m1_t const*>(B); \\\n- operator_args.mainloop.ptr_SFA = static_cast<cutlass::float_ue4m3_t const*>(input_sf); \\\n- operator_args.mainloop.ptr_SFB = static_cast<cutlass::float_ue4m3_t const*>(weight_sf); \\\n- operator_args.epilogue.ptr_C = static_cast<ElementC const*>(D); \\\n- operator_args.epilogue.ptr_D = static_cast<ElementD*>(D); \\\n- \\\n- int const stride_A = batch_count == 1 ? 0 : m * k; \\\n- int const stride_B = batch_count == 1 ? 0 : n * k; \\\n- int const stride_C = batch_count == 1 ? 0 : m * n; \\\n- \\\n- operator_args.mainloop.dA = \\\n- cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideA>(k, stride_A); \\\n- operator_args.mainloop.dB = \\\n- cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideB>(k, stride_B); \\\n- operator_args.epilogue.dC = \\\n- cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideC>(n, stride_C); \\\n- operator_args.epilogue.dD = operator_args.epilogue.dC; \\\n- \\\n- operator_args.mainloop.layout_SFA = \\\n- Sm1xxBlkScaledConfig::tile_atom_to_shape_SFA(operator_args.problem_shape); \\\n- operator_args.mainloop.layout_SFB = \\\n- Sm1xxBlkScaledConfig::tile_atom_to_shape_SFB(operator_args.problem_shape); \\\n- \\\n- if constexpr (!std::is_const_v<decltype(operator_args.scheduler.max_swizzle_size)>) { \\\n- operator_args.scheduler.max_swizzle_size = 1; \\\n- } \\\n- if constexpr (!std::is_const_v<decltype(operator_args.scheduler.raster_order)>) { \\\n- using Enum_t = decltype(operator_args.scheduler.raster_order); \\\n- operator_args.scheduler.raster_order = Enum_t::Heuristic; \\\n- } \\\n- operator_args.hw_info.cluster_shape = dim3(1, 1, 1); /* SM120 requires 1x1x1 */ \\\n- operator_args.hw_info.cluster_shape_fallback = dim3(1, 1, 1); \\\n- \\\n- return operator_args; \\\n- } \\\n- \\\n+ GemmDefault; \\\n+ \\\n+ using Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_StreamK = \\\n+ DeviceGemmFp4GemmSm120_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_##CGA_M_##_##CGA_N_##_##CGA_K_##XSM_:: \\\n+ GemmStreamK; \\\n+ \\\n+ /* DP scheduler launcher - uses common helper functions */ \\\n template <> \\\n size_t \\\n genericFp4GemmKernelLauncher<T, cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>, \\\n@@ -222,48 +295,23 @@\n void* D, void const* A, void const* B, void const* input_sf, void const* weight_sf, \\\n float const* global_sf, int m, int n, int k, int batch_count, CutlassGemmConfig gemmConfig, \\\n char* workspace, const size_t workspaceBytes, cudaStream_t stream, int* occupancy) { \\\n- using ElementOutput__ = \\\n- typename cutlass::platform::conditional<cutlass::platform::is_same<T, half>::value, \\\n- cutlass::half_t, T>::type; \\\n- using ElementOutput_ = typename cutlass::platform::conditional< \\\n- cutlass::platform::is_same<ElementOutput__, float>::value, float, ElementOutput__>::type; \\\n- using ElementOutput = typename cutlass::platform::conditional< \\\n- cutlass::platform::is_same<ElementOutput_, SafeBF16>::value, cutlass::bfloat16_t, \\\n- ElementOutput_>::type; \\\n- \\\n using Fp4GemmOperator = Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_; \\\n- Fp4GemmOperator gemm; \\\n- auto args = prepareGemmArgs_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_( \\\n- D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count); \\\n- /* // Return workspace size */ \\\n- if (!A && !B && !D) { \\\n- return gemm.get_workspace_size(args); \\\n- } \\\n- if (gemm.get_workspace_size(args) > workspaceBytes) { \\\n- std::string errMsg(\"Requested workspace size insufficient. Required \" + \\\n- std::to_string(gemm.get_workspace_size(args)) + \", got \" + \\\n- std::to_string(workspaceBytes)); \\\n- throw std::runtime_error(\"[FP4 gemm Runner] \" + errMsg); \\\n- } \\\n- auto can_implement = gemm.can_implement(args); \\\n- if (can_implement != cutlass::Status::kSuccess) { \\\n- std::string errMsg = \"FP4 Gemm cutlass kernel will fail for params. Error: \" + \\\n- std::string(cutlass::cutlassGetStatusString(can_implement)); \\\n- throw std::runtime_error(\"[FP4 gemm Runner] \" + errMsg); \\\n- } \\\n- auto initStatus = gemm.initialize(args, workspace, stream); \\\n- if (initStatus != cutlass::Status::kSuccess) { \\\n- std::string errMsg = \"Failed to initialize cutlass FP4 gemm on sm120. Error: \" + \\\n- std::string(cutlass::cutlassGetStatusString(initStatus)); \\\n- throw std::runtime_error(\"[FP4 gemm Runner] \" + errMsg); \\\n- } \\\n- auto runStatus = gemm.run(args, workspace, stream, nullptr, /*enablePDL=*/true); \\\n- if (runStatus != cutlass::Status::kSuccess) { \\\n- std::string errMsg = \"Failed to run cutlass FP4 gemm on sm120. Error: \" + \\\n- std::string(cutlass::cutlassGetStatusString(runStatus)); \\\n- throw std::runtime_error(\"[FP4 gemm Runner] \" + errMsg); \\\n- } \\\n- return gemm.get_workspace_size(args); \\\n+ return runFp4GemmImpl<Fp4GemmOperator>(D, A, B, input_sf, weight_sf, global_sf, m, n, k, \\\n+ batch_count, workspace, workspaceBytes, stream, \"\"); \\\n+ } \\\n+ \\\n+ /* StreamK scheduler launcher - uses common helper functions */ \\\n+ template <> \\\n+ size_t genericFp4GemmKernelLauncherStreamK<T, cute::Int<CTA_M_>, cute::Int<CTA_N_>, \\\n+ cute::Int<CTA_K_>, cute::Int<CGA_M_>, \\\n+ cute::Int<CGA_N_>, cute::Int<CGA_K_>, XSM_>( \\\n+ void* D, void const* A, void const* B, void const* input_sf, void const* weight_sf, \\\n+ float const* global_sf, int m, int n, int k, int batch_count, CutlassGemmConfig gemmConfig, \\\n+ char* workspace, const size_t workspaceBytes, cudaStream_t stream, int* occupancy) { \\\n+ using Fp4GemmOperator = Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_StreamK; \\\n+ return runFp4GemmImpl<Fp4GemmOperator>(D, A, B, input_sf, weight_sf, global_sf, m, n, k, \\\n+ batch_count, workspace, workspaceBytes, stream, \\\n+ \" StreamK\"); \\\n }\n \n #endif"},"lines_added":{"kind":"number","value":153,"string":"153"},"lines_removed":{"kind":"number","value":105,"string":"105"},"files_in_commit":{"kind":"number","value":4,"string":"4"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["SM120"],"string":"[\n \"SM120\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp4_gemm_template_sm120.h).\n\nGoal: perf: add fp4 GEMM tile configs and streamK scheduler for SM120\nTarget hardware: SM120\nTarget models: unspecified\n\nCurrent file:\n```cpp\n/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_FP4_GEMM_TEMPLATE_SM120_H_\n#define FLASHINFER_FP4_GEMM_TEMPLATE_SM120_H_\n\n#ifndef _WIN32\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wstrict-aliasing\"\n#endif // #ifndef _WIN32\n\n#include <cuda_bf16.h>\n\n#include <cutlass/detail/sm100_blockscaled_layout.hpp>\n\n#include \"cutlass/arch/arch.h\"\n#include \"cutlass/cutlass.h\"\n#include \"cutlass/epilogue/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/collective/collective_builder.hpp\"\n#include \"cutlass/gemm/device/gemm_universal_adapter.h\"\n#include \"cutlass/gemm/gemm.h\"\n#include \"flashinfer/arch_condition.h\"\n#include \"flashinfer/cutlass_utils.cuh\"\n\n#ifndef _WIN32\n#pragma GCC diagnostic pop\n#endif // #ifndef _WIN32\n\nnamespace flashinfer {\nnamespace gemm {\nusing namespace cute;\n\n#ifdef ENABLE_BF16\nusing SafeBF16 = __nv_bfloat16;\n#else\nusing SafeBF16 = void;\n#endif\n\nstruct _1SM {};\n\nstruct _2SM {};\n\ntemplate <typename T>\nstruct SMTypeAdapter {};\n\ntemplate <>\nstruct SMTypeAdapter<_1SM> {\n static int const Scale = 1;\n using AtomThrShape = cute::Shape<_1, _1, _1>;\n using EpilogueSchedule = cutlass::epilogue::TmaWarpSpecialized1Sm;\n using MainloopSchedule = cutlass::gemm::KernelTmaWarpSpecialized1SmNvf4Sm100;\n};\n\ntemplate <>\nstruct SMTypeAdapter<_2SM> {\n static int const Scale = 2;\n using AtomThrShape = cute::Shape<_2, _1, _1>;\n using EpilogueSchedule = cutlass::epilogue::TmaWarpSpecialized2Sm;\n using MainloopSchedule = cutlass::gemm::KernelTmaWarpSpecialized2SmNvf4Sm100;\n};\n\ntemplate <typename>\nconstexpr auto always_false = false;\n\ntemplate <typename T, typename CTA_M_, typename CTA_N_, typename CTA_K_, typename CGA_M_,\n typename CGA_N_, typename CGA_K_, typename XSM_>\nsize_t genericFp4GemmKernelLauncher(void* D, void const* A, void const* B, void const* input_sf,\n void const* weight_sf, float const* global_sf, int m, int n,\n int k, int batch_count, CutlassGemmConfig gemmConfig,\n char* workspace, size_t const workspaceBytes,\n cudaStream_t stream, int* occupancy);\n\n#ifdef PLACEHOLDER_KERNELS\n\n#define INSTANTIATE_FP4_GEMM_KERNEL_LAUNCHER(T, CTA_M_, CTA_N_, CTA_K_, CGA_M_, CGA_N_, CGA_K_, \\\n XSM_) \\\n template <> \\\n size_t \\\n genericFp4GemmKernelLauncher<T, cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>, \\\n cute::Int<CGA_M_>, cute::Int<CGA_N_>, cute::Int<CGA_K_>, XSM_>( \\\n void* D, void const* A, void const* B, void const* input_sf, void const* weight_sf, \\\n float const* global_sf, int m, int n, int k, int batch_count, CutlassGemmConfig gemmConfig, \\\n char* workspace, const size_t workspaceBytes, cudaStream_t stream, int* occupancy) { \\\n throw std::runtime_error( \\\n \"FP4 gemm kernel is not compiled with support for \" \\\n \"this Architecture.\"); \\\n }\n\n#else\n\n#define INSTANTIATE_FP4_GEMM_KERNEL_LAUNCHER(T, CTA_M_, CTA_N_, CTA_K_, CGA_M_, CGA_N_, CGA_K_, \\\n XSM_) \\\n struct \\\n DeviceGemmFp4GemmSm120_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_##CGA_M_##_##CGA_N_##_##CGA_K_##XSM_ { \\\n using OutElementType = typename flashinfer::cutlass_dtype<T>::type; \\\n using CTAShape = cute::Shape<cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>>; \\\n using Arch = cutlass::arch::Sm120; /* Use Sm120 for SM121 hardware */ \\\n /* For SM120/SM121, always use 1x1x1 cluster shape regardless of macro parameters */ \\\n using ClusterShape = cute::Shape<_1, _1, _1>; \\\n /* // Input A - Use nv_float4_t like example 79 */ \\\n using ElementA = cutlass::nv_float4_t<cutlass::float_e2m1_t>; \\\n using LayoutA = cutlass::layout::RowMajor; \\\n static constexpr int AlignmentA = 32; /* Fixed for nv_float4_t */ \\\n /* // Input B - Use nv_float4_t like example 79 */ \\\n using ElementB = cutlass::nv_float4_t<cutlass::float_e2m1_t>; \\\n using LayoutB = cutlass::layout::ColumnMajor; \\\n static constexpr int AlignmentB = 32; /* Fixed for nv_float4_t */ \\\n /* // Input C */ \\\n using ElementC = void; \\\n using LayoutC = cutlass::layout::RowMajor; \\\n static constexpr int AlignmentC = 128 / cutlass::sizeof_bits<OutElementType>::value; \\\n \\\n using SFType = cutlass::float_ue4m3_t; /* Scale factor type */ \\\n using ElementCompute = float; \\\n using ElementAccumulator = float; \\\n using OperatorClass = cutlass::arch::OpClassBlockScaledTensorOp; \\\n using EpilogueTileType = \\\n cutlass::epilogue::collective::EpilogueTileAuto; /* Always use auto for SM100 */ \\\n using EpilogueSchedule = cutlass::epilogue::collective::EpilogueScheduleAuto; \\\n using MainloopSchedule = cutlass::gemm::collective::KernelScheduleAuto; \\\n using ThreadBlockShape = cute::Shape<cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>>; \\\n using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder< \\\n Arch, OperatorClass, ThreadBlockShape, ClusterShape, EpilogueTileType, ElementAccumulator, \\\n ElementCompute, ElementC, LayoutC, AlignmentC, OutElementType, LayoutC, AlignmentC, \\\n EpilogueSchedule, \\\n cutlass::epilogue::fusion::LinearCombination<OutElementType, float, void, \\\n float>>::CollectiveOp; \\\n \\\n /* SM120 BlockScaled - Use nv_float4_t without tuples like example 79 */ \\\n /* Use fixed 2 stages for SM120 to meet minimum requirement */ \\\n using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder< \\\n Arch, OperatorClass, ElementA, LayoutA, AlignmentA, ElementB, LayoutB, AlignmentB, \\\n ElementAccumulator, ThreadBlockShape, ClusterShape, \\\n cutlass::gemm::collective::StageCount<2>, /* Fixed 2 stages for SM120 */ \\\n cutlass::gemm::collective::KernelScheduleAuto>::CollectiveOp; \\\n \\\n /* Match example 79 - no wrapper needed */ \\\n using GemmKernel = cutlass::gemm::kernel::GemmUniversal< \\\n cute::Shape<int, int, int, int>, /* Indicates ProblemShape */ \\\n CollectiveMainloop, CollectiveEpilogue, void>; /* No persistent scheduler for SM120 */ \\\n \\\n using Gemm = typename cutlass::gemm::device::GemmUniversalAdapter<GemmKernel>; \\\n }; \\\n \\\n using Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_ = \\\n DeviceGemmFp4GemmSm120_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_##_##CGA_M_##_##CGA_N_##_##CGA_K_##XSM_:: \\\n Gemm; \\\n \\\n inline typename Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_::Arguments \\\n prepareGemmArgs_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_( \\\n void* D, void const* A, void const* B, void const* input_sf, void const* weight_sf, \\\n float const* global_sf, int m, int n, int k, int batch_count) { \\\n using Gemm = Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_; \\\n using Sm1xxBlkScaledConfig = \\\n typename Gemm::GemmKernel::CollectiveMainloop::Sm1xxBlkScaledConfig; \\\n /* Note: For nv_float4_t, scale factors are handled internally */ \\\n using ElementC = void; \\\n using ElementD = typename Gemm::ElementD; \\\n using ElementCompute = float; \\\n \\\n typename Gemm::Arguments operator_args; \\\n operator_args.mode = cutlass::gemm::GemmUniversalMode::kGemm; \\\n auto& fusion_args = operator_args.epilogue.thread; \\\n fusion_args.alpha_ptr = static_cast<ElementCompute const*>(global_sf); \\\n \\\n operator_args.problem_shape = cute::make_shape(m, n, k, batch_count); \\\n \\\n /* For nv_float4_t, data and scale factors are stored separately */ \\\n operator_args.mainloop.ptr_A = static_cast<cutlass::float_e2m1_t const*>(A); \\\n operator_args.mainloop.ptr_B = static_cast<cutlass::float_e2m1_t const*>(B); \\\n operator_args.mainloop.ptr_SFA = static_cast<cutlass::float_ue4m3_t const*>(input_sf); \\\n operator_args.mainloop.ptr_SFB = static_cast<cutlass::float_ue4m3_t const*>(weight_sf); \\\n operator_args.epilogue.ptr_C = static_cast<ElementC const*>(D); \\\n operator_args.epilogue.ptr_D = static_cast<ElementD*>(D); \\\n \\\n int const stride_A = batch_count == 1 ? 0 : m * k; \\\n int const stride_B = batch_count == 1 ? 0 : n * k; \\\n int const stride_C = batch_count == 1 ? 0 : m * n; \\\n \\\n operator_args.mainloop.dA = \\\n cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideA>(k, stride_A); \\\n operator_args.mainloop.dB = \\\n cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideB>(k, stride_B); \\\n operator_args.epilogue.dC = \\\n cute::make_int_tuple_from<typename Gemm::GemmKernel::StrideC>(n, stride_C); \\\n operator_args.epilogue.dD = operator_args.epilogue.dC; \\\n \\\n operator_args.mainloop.layout_SFA = \\\n Sm1xxBlkScaledConfig::tile_atom_to_shape_SFA(operator_args.problem_shape); \\\n operator_args.mainloop.layout_SFB = \\\n Sm1xxBlkScaledConfig::tile_atom_to_shape_SFB(operator_args.problem_shape); \\\n \\\n if constexpr (!std::is_const_v<decltype(operator_args.scheduler.max_swizzle_size)>) { \\\n operator_args.scheduler.max_swizzle_size = 1; \\\n } \\\n if constexpr (!std::is_const_v<decltype(operator_args.scheduler.raster_order)>) { \\\n using Enum_t = decltype(operator_args.scheduler.raster_order); \\\n operator_args.scheduler.raster_order = Enum_t::Heuristic; \\\n } \\\n operator_args.hw_info.cluster_shape = dim3(1, 1, 1); /* SM120 requires 1x1x1 */ \\\n operator_args.hw_info.cluster_shape_fallback = dim3(1, 1, 1); \\\n \\\n return operator_args; \\\n } \\\n \\\n template <> \\\n size_t \\\n genericFp4GemmKernelLauncher<T, cute::Int<CTA_M_>, cute::Int<CTA_N_>, cute::Int<CTA_K_>, \\\n cute::Int<CGA_M_>, cute::Int<CGA_N_>, cute::Int<CGA_K_>, XSM_>( \\\n void* D, void const* A, void const* B, void const* input_sf, void const* weight_sf, \\\n float const* global_sf, int m, int n, int k, int batch_count, CutlassGemmConfig gemmConfig, \\\n char* workspace, const size_t workspaceBytes, cudaStream_t stream, int* occupancy) { \\\n using ElementOutput__ = \\\n typename cutlass::platform::conditional<cutlass::platform::is_same<T, half>::value, \\\n cutlass::half_t, T>::type; \\\n using ElementOutput_ = typename cutlass::platform::conditional< \\\n cutlass::platform::is_same<ElementOutput__, float>::value, float, ElementOutput__>::type; \\\n using ElementOutput = typename cutlass::platform::conditional< \\\n cutlass::platform::is_same<ElementOutput_, SafeBF16>::value, cutlass::bfloat16_t, \\\n ElementOutput_>::type; \\\n \\\n using Fp4GemmOperator = Fp4Gemm_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_; \\\n Fp4GemmOperator gemm; \\\n auto args = prepareGemmArgs_##T##_##CTA_M_##_##CTA_N_##_##CTA_K_( \\\n D, A, B, input_sf, weight_sf, global_sf, m, n, k, batch_count); \\\n /* // Return workspace size */ \\\n if (!A && !B && !D) { \\\n return gemm.get_workspace_size(args); \\\n } \\\n if (gemm.get_workspace_size(args) > workspaceBytes) { \\\n std::string errMsg(\"Requested workspace size insufficient. Required \" + \\\n std::to_string(gemm.get_workspace_size(args)) + \", got \" + \\\n std::to_string(workspaceBytes)); \\\n throw std::runtime_error(\"[FP4 gemm Runner] \" + errMsg); \\\n } \\\n auto can_implement = gemm.can_implement(args); \\\n if (can_implement != cutlass::Status::kSuccess) { \\\n std::string errMsg = \"FP4 Gemm cutlass kernel will fail for params. Error: \" + \\\n std::string(cutlass::cutlassGetStatusString(can_implement)); \\\n throw std::runtime_error(\"[FP4 gemm Runner] \" + errMsg); \\\n } \\\n auto initStatus = gemm.initialize(args, workspace, stream); \\\n if (initStatus != cutlass::Status::kSuccess) { \\\n std::string errMsg = \"Failed to initialize cutlass FP4 gemm on sm120. Error: \" + \\\n std::string(cutlass::cutlassGetStatusString(initStatus)); \\\n throw std::runtime_error(\"[FP4 gemm Runner] \" + errMsg); \\\n } \\\n auto runStatus = gemm.run(args, workspace, stream, nullptr, /*enablePDL=*/true); \\\n if (runStatus != cutlass::Status::kSuccess) { \\\n std::string errMsg = \"Failed to run cutlass FP4 gemm on sm120. Error: \" + \\\n std::string(cutlass::cutlassGetStatusString(runStatus)); \\\n throw std::runtime_error(\"[FP4 gemm Runner] \" + errMsg); \\\n } \\\n return gemm.get_workspace_size(args); \\\n }\n\n#endif\n\n} // namespace gemm\n} // namespace flashinfer\n#endif // FLASHINFER_FP4_GEMM_TEMPLATE_SM120_H_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nAdd SM120 FP4 GEMM tile configs and enable streamK scheduler for configs that can be selected by autotuner.\nTake the problem size m=32, n=5120, k=25600 as an example. After adding these configs, the latency of mm_fp4 kernel reduced from 0.124ms to 0.069ms on RTX PRO 6000.\n\n```\n[PERF] cutlass_autotun:: median time 0.124 ms; std 0.000 ms; achieved tflops 67.751 TFLOPs/sec; achieved tb_per_sec 0.535 TB/sec\n[PERF] cutlass_autotun:: median time 0.069 ms; std 0.000 ms; achieved tflops 121.902 TFLOPs/sec; achieved tb_per_sec 0.963 TB/sec\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n * Added StreamK scheduler option for SM120 FP4 GEMM operations, alongside the existing DP scheduler.\n * Expanded SM120 FP4 GEMM tile configurations with two additional options (128×128×256 and 256×128×128).\n * Extended configuration generation to support all tile shapes with both schedulers for improved optimization flexibility.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"m=32,n=5120,k=25600\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"ms\", \"higher_is_better\": false, \"baseline\": 0.124, \"optimized\": 0.069, \"stated_speedup\": null, \"speedup\": 1.7971}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"m=32,n=5120,k=25600\", \"batch_size\": null, \"metric\": \"TFLOPS\", \"unit\": \"TFLOPs/sec\", \"higher_is_better\": true, \"baseline\": 67.751, \"optimized\": 121.902, \"stated_speedup\": null, \"speedup\": 1.7993}, {\"scope\": \"kernel\", \"hardware\": \"RTX PRO 6000\", \"model\": null, \"shape\": \"m=32,n=5120,k=25600\", \"batch_size\": null, \"metric\": \"bandwidth\", \"unit\": \"TB/sec\", \"higher_is_better\": true, \"baseline\": 0.535, \"optimized\": 0.963, \"stated_speedup\": null, \"speedup\": 1.8}]"},"kernel_speedup":{"kind":"number","value":1.7993,"string":"1.7993"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1185,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"5e5a8668bede32d86035dba98f460a278332e366"},"date":{"kind":"string","value":"2026-02-03T04:42:54-08:00"},"pr_number":{"kind":"number","value":2405,"string":"2,405"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2405"},"title":{"kind":"string","value":"perf: improve gdn decode cute-dsl kernels (#2405)"},"message":{"kind":"string","value":"perf: improve gdn decode cute-dsl kernels (#2405)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nFollow up of #2370 , this PR improves the benchmark scripts and add\ncomparison with baselines:\n* benchmark using cupti with l2 flush\n* compare with sglang's `fused_sigmoid_gating_delta_rule_update`\nfunction (with tile size optimization mentioned by @ vadiklyutiy).\n\nthis PR also implements some optimizations on the original gdn kernel:\n* use fastmath as much as we can\n* change \"/\" to multiply\n* Use `cutlass.range_constexpr` and `cutlass.const_expr` whenever\npossible\n* fuse scale and inv_norm_q\n* For mtp, store state in registers directly, without load/write to\nshared memory, and remove cpasync\n* Vectorized memory access.\n\n## Performance on B200\n\nNon MTP setting\n```\n> python benchmarks/bench_gdn_decode.py --batch-size 1 2 4 8 16 32 64 128 256 --compare --verify\n\n=== Correctness Verification ===\nBatch=8:\n Pretranspose: PASS\n Nontranspose: PASS\nBatch=16:\n Pretranspose: PASS\n Nontranspose: PASS\nBatch=32:\n Pretranspose: PASS\n Nontranspose: PASS\nBatch=64:\n Pretranspose: PASS\n Nontranspose: PASS\n\n\n========================================================================================================================\nGDN Decode Benchmark: FlashInfer vs Triton, Pretranspose vs Nontranspose\nConfig: q_heads=16, k_heads=16, v_heads=32, head_size=128, dtype=bfloat16, qk_l2norm=ON\n========================================================================================================================\n\n batch | FI-PreTr FI-NonTr | TR-PreTr TR-NonTr | FI/TR-Pre FI/TR-Non | Pre/Non-FI Pre/Non-TR\n | (us) (us) | (us) (us) | speedup speedup | speedup speedup\n------------------------------------------------------------------------------------------------------------------------\n 1 | 3.74 5.06 | 5.95 4.35 | 1.59x 0.86x | 1.35x 0.73x\n 2 | 4.29 5.89 | 6.37 5.02 | 1.49x 0.85x | 1.37x 0.79x\n 4 | 5.41 7.78 | 7.58 6.66 | 1.40x 0.86x | 1.44x 0.88x\n 8 | 7.65 12.03 | 9.95 10.21 | 1.30x 0.85x | 1.57x 1.03x\n 16 | 12.61 19.30 | 16.83 15.81 | 1.34x 0.82x | 1.53x 0.94x\n 32 | 22.91 32.86 | 31.55 27.84 | 1.38x 0.85x | 1.43x 0.88x\n 64 | 52.74 58.61 | 58.91 53.02 | 1.12x 0.90x | 1.11x 0.90x\n 128 | 92.93 107.98 | 114.45 106.78 | 1.23x 0.99x | 1.16x 0.93x\n 256 | 170.77 209.04 | 225.71 216.41 | 1.32x 1.04x | 1.22x 0.96x\n------------------------------------------------------------------------------------------------------------------------\n\nLegend:\n FI-PreTr = FlashInfer Pretranspose [B, HV, V, K]\n FI-NonTr = FlashInfer Nontranspose [B, HV, K, V]\n TR-PreTr = Triton Pretranspose [B, HV, V, K]\n TR-NonTr = Triton Nontranspose [B, HV, K, V]\n FI/TR speedup > 1.0 means FlashInfer is faster than Triton\n Pre/Non speedup > 1.0 means Pretranspose is faster than Nontranspose\n\nFlashInfer vs Triton (Pretranspose) - Average speedup: 1.35x\n```\n\nMTP Setting (pretranspose only)\n```\n> python benchmarks/bench_gdn_decode.py --version mtp --batch-size 1 2 4 8 16 32 64 128 256 --compare --verify\n\n=== Correctness Verification (MTP) ===\nBatch=8: PASS\nBatch=16: PASS\nBatch=32: PASS\nBatch=64: PASS\n\n\nGDN MTP Comparison: FlashInfer (CuTe DSL) vs Triton\nConfig: q_heads=16, k_heads=16, v_heads=32, head_size=128, dtype=bfloat16, qk_l2norm=ON, cache_intermediate=OFF\n--------------------------------------------------------------------------------------------------------------\n batch seq_len FlashInfer(us) Triton(us) FI TFLOPS TR TFLOPS Speedup\n--------------------------------------------------------------------------------------------------------------\n 1 2 9.22 10.05 0.68 0.63 1.09x\n 1 4 11.20 14.43 1.12 0.87 1.29x\n 1 8 15.81 22.08 1.59 1.14 1.40x\n 2 2 10.11 10.69 1.24 1.18 1.06x\n 2 4 12.58 15.10 2.00 1.67 1.20x\n 2 8 18.82 23.63 2.67 2.13 1.26x\n 4 2 11.39 11.94 2.21 2.11 1.05x\n 4 4 15.23 16.54 3.30 3.04 1.09x\n 4 8 23.62 25.50 4.26 3.95 1.08x\n 8 2 14.69 17.23 3.43 2.92 1.17x\n 8 4 21.20 25.01 4.75 4.03 1.18x\n 8 8 34.69 40.86 5.80 4.93 1.18x\n 16 2 21.47 24.22 4.69 4.16 1.13x\n 16 4 32.54 36.98 6.19 5.44 1.14x\n 16 8 56.24 61.76 7.16 6.52 1.10x\n 32 2 33.50 37.68 6.01 5.34 1.12x\n 32 4 54.66 60.26 7.37 6.68 1.10x\n 32 8 97.98 104.35 8.22 7.72 1.06x\n 64 2 59.82 65.38 6.73 6.16 1.09x\n 64 4 102.05 108.83 7.89 7.40 1.07x\n 64 8 188.17 196.45 8.56 8.20 1.04x\n 128 2 107.44 121.41 7.50 6.63 1.13x\n 128 4 192.01 209.90 8.39 7.67 1.09x\n 128 8 366.81 389.12 8.78 8.28 1.06x\n 256 2 199.14 236.19 8.09 6.82 1.19x\n 256 4 363.36 422.61 8.87 7.62 1.16x\n 256 8 708.22 787.05 9.10 8.19 1.11x\n--------------------------------------------------------------------------------------------------------------\nSpeedup > 1.0 means FlashInfer is faster\n\nSummary:\n Average speedup: 1.13x\n Min speedup: 1.04x (batch=64, T=8)\n Max speedup: 1.40x (batch=1, T=8)\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* Added Triton-based benchmarks and end-to-end comparison/verify modes\nacross multiple memory layouts (including MTP); new verification flows\nto compare implementations.\n* **Performance Improvements**\n* Batch-size-aware kernel selection, configurable tile/vec sizing,\nfast-math paths, reduced redundant copies, and CUPTI-backed GPU timing\nfor more accurate benchmarks.\n* **Behavior & Compatibility**\n* Improved layout handling, expanded CLI presets/modes, clearer error\nmessages and guards when Triton is unavailable; default benchmark mode\nupdated.\n* **Documentation**\n * Updated usage examples and CLI guidance.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review\nsettings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: HongliMi <166"},"path":{"kind":"string","value":"flashinfer/gdn_decode.py"},"language":{"kind":"string","value":"cute_dsl"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\n\"\"\"\nGated Delta Rule Decode Kernel - Single Token Generation\n\nThis file implements a fused CUDA kernel using CUTLASS CuTe DSL for executing\nSigmoid Gating Delta Rule updates during decode phase. Key features:\n\nArchitecture Design:\n- Uses TMA (Tensor Memory Accelerator) for efficient Global Memory → Shared Memory transfers\n- Employs 2-stage pipeline to overlap loading and computation, hiding memory latency\n- Each block uses 128 threads (4 warps), with each warp processing one matrix row\n- Tile size: 8x128 (TILE_V x TILE_K)\n\nComputation Flow:\n1. Warp 0 handles TMA prefetch, loading data from GMEM to SMEM\n2. All warps compute in parallel: softplus, L2 normalization, delta rule updates\n3. Each warp processes one row of data, completing h_new = g*h + k*(beta*(v - h@k))\n4. Uses warp-level shuffle for efficient reduction operations\n5. Results are vectorized and written back to Global Memory\n\nPerformance Optimizations:\n- Vectorized memory access: each thread processes vec_size=4 elements (128-bit aligned)\n- Warp-level collective operations: shuffle-based reduction\n- Pipeline overlap: load stage N+1 while computing stage N\n\"\"\"\n\nimport functools\nfrom typing import Optional, Tuple\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass.cute.nvgpu import cpasync\nfrom cutlass.cute.runtime import from_dlpack\nimport cuda.bindings.driver as cuda\n\ntry:\n from .api_logging import flashinfer_api\n\n _FLASHINFER_AVAILABLE = True\nexcept ImportError:\n _FLASHINFER_AVAILABLE = False\n\n # Fallback decorator for standalone usage\n def flashinfer_api(func): # type: ignore[misc]\n return func\n\n\n# ============================================================================\n# Global configuration for PRETRANSPOSE version ([B*HV, V, K])\n# ============================================================================\nTILE_V = 8\nTILE_K = 128\nNUM_STAGES = 2\nNUM_THREADS = 128 # 4 warps\nNUM_BLOCKS_PER_STATE = 8\n\n# ============================================================================\n# Global configuration for NONTRANSPOSE version ([pool, HV, K, V])\n# ============================================================================\nTILE_K_NT = 128\nTILE_V_NT = 32\nTILE_V_PADDED_NT = 36\nTILE_V_SMALL_NT = 16\nTILE_V_SMALL_PADDED_NT = 20\nNUM_STAGES_NT = 2\nNUM_THREADS_NT = 128\nNUM_BLOCKS_PER_STATE_SMALL_NT = 8\nNUM_THREADS_LARGE_NT = 256\nNUM_WARPS_LARGE_NT = 8\nV_PER_WARP_NT = 4\nROWS_PER_ITER_NT = 8\nNUM_K_ITERS_NT = TILE_K_NT // ROWS_PER_ITER_NT\nSMALL_BATCH_THRESHOLD_NT = 32\n\n# ============================================================================\n# Global configuration for MTP (Multiple Token Processing) version\n# ============================================================================\nTILE_V_MTP = 8\nTILE_K_MTP = 128\nNUM_STAGES_MTP = 2\nNUM_THREADS_MTP = 128 # 4 warps\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n\n cute.arch.barrier()\n\n # Get current batch\n gSrc_batch = h0_source[(batch_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (batch_idx, None, 0))\n\n # V 方向分 tiles\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n start_v_tiles = batch_inner * num_v_tiles_per_block\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles_per_block)\n for v_tiles in range(start_v_tiles, start_v_tiles + prefetch_count):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n for i in range(vec_size):\n r_q[i] = cutlass.Float32(q[i_n, i_t, i_h, i * 32 + lane_id])\n r_k[i] = cutlass.Float32(k[i_n, i_t, i_h, i * 32 + lane_id])\n # Store v to shared memory instead of register\n v_val = cutlass.Float32(v[i_n, i_t, i_hv, i * 32 + lane_id])\n sV[i * 32 + lane_id] = v_val\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in range(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n norm_q = cute.sqrt(sum_q + 1e-6)\n norm_k = cute.sqrt(sum_k + 1e-6)\n for i in range(vec_size):\n r_q[i] = r_q[i] / norm_q\n r_k[i] = r_k[i] / norm_k\n\n # Apply scaling in Float32\n for i in range(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n end_v_tiles = start_v_tiles + num_v_tiles_per_block\n for v_tiles in range(start_v_tiles, end_v_tiles):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < end_v_tiles:\n next_stage = (next_v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage\n for row in range(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n for i in range(vec_size):\n r_h[i] = sData[(row + row_offset, i * 32 + lane_id, stage)]\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in range(vec_size):\n r_h[i] += r_k[i] * v_new\n gDst[(0, row + row_offset, i * 32 + lane_id, v_tiles)] = r_h[i]\n sum_hq += r_h[i] * r_q[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n if tidx >= start_v_tiles * TILE_V and tidx < end_v_tiles * TILE_V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n\n cute.arch.barrier()\n\n # Get current batch\n gSrc_batch = h0_source[(batch_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (batch_idx, None, 0))\n\n # V 方向分 tiles\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles)\n for v_tiles in range(prefetch_count):\n stage = v_tiles % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n for i in range(vec_size):\n r_q[i] = cutlass.Float32(q[i_n, i_t, i_h, i * 32 + lane_id])\n r_k[i] = cutlass.Float32(k[i_n, i_t, i_h, i * 32 + lane_id])\n # Store v to shared memory instead of register\n v_val = cutlass.Float32(v[i_n, i_t, i_hv, i * 32 + lane_id])\n sV[i * 32 + lane_id] = v_val\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in range(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n norm_q = cute.sqrt(sum_q + 1e-6)\n norm_k = cute.sqrt(sum_k + 1e-6)\n for i in range(vec_size):\n r_q[i] = r_q[i] / norm_q\n r_k[i] = r_k[i] / norm_k\n\n # Apply scaling in Float32\n for i in range(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n for v_tiles in range(num_v_tiles):\n stage = v_tiles % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < num_v_tiles:\n next_stage = next_v_tiles % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage\n for row in range(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n for i in range(vec_size):\n r_h[i] = sData[(row + row_offset, i * 32 + lane_id, stage)]\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in range(vec_size):\n r_h[i] += r_k[i] * v_new\n gDst[(0, row + row_offset, i * 32 + lane_id, v_tiles)] = r_h[i]\n sum_hq += r_h[i] * r_q[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * batch_size * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # print(f\"Batched CP.ASYNC Load + Store (bypass L1 cache)\")\n # print(f\" {batch_size} batches x {v_dim}x{k_dim} matrices\")\n # print(f\" Tile: {TILE_V}x{TILE_K}, {num_v_tiles} tiles/batch\")\n # print(f\" Threads: {NUM_THREADS} ({NUM_THREADS // 32} warps), vec_size: {vec_size}\")\n # print(f\" Total: {total_data_mb:.1f} MB\\n\")\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n ).launch(\n grid=(batch_size * NUM_BLOCKS_PER_STATE, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * batch_size * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # print(f\"Batched CP.ASYNC Load + Store (bypass L1 cache)\")\n # print(f\" {batch_size} batches x {v_dim}x{k_dim} matrices\")\n # print(f\" Tile: {TILE_V}x{TILE_K}, {num_v_tiles} tiles/batch\")\n # print(f\" Threads: {NUM_THREADS} ({NUM_THREADS // 32} warps), vec_size: {vec_size}\")\n # print(f\" Total: {total_data_mb:.1f} MB\\n\")\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# FlashInfer API Layer\n# ============================================================================\n\n\n@functools.cache\ndef _get_compiled_decode_kernel(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled kernel for given configuration (pretranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\n@functools.cache\ndef _get_compiled_decode_kernel_nontranspose(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled kernel for given configuration (nontranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\n@flashinfer_api\ndef gated_delta_rule_decode_pretranspose(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n state: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Gated Delta Rule Decode kernel for single-token generation.\n\n This implements the decode phase of gated delta rule linear attention,\n processing one token at a time and updating the recurrent state.\n\n Args:\n q (torch.Tensor):\n Current query of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n k (torch.Tensor):\n Current key of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n v (torch.Tensor):\n Current value of shape ``[B, 1, HV, V]``. Must be float16/bfloat16.\n state (torch.Tensor):\n Current state of shape ``[B, HV, V, K]`` (v-major layout).\n Must be float32. Will be updated in-place.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``. Must be float32.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``. Must be bfloat16 or float32.\n b (torch.Tensor):\n Update gate (beta) input of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n scale (Optional[float]):\n Scale factor for queries. If None, defaults to ``1 / sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, 1, HV, V]``.\n If None, will be allocated automatically.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, 1, HV, V]``\n - state: Updated state tensor of shape ``[B, HV, V, K]``\n\n Note:\n - Requires SM90 (Hopper) architecture\n - State is updated in-place\n - K and V must be multiples of 4 for vectorized loads\n - State layout is v-major: [B, HV, V, K]\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n assert T == 1, f\"Decode only supports T=1, got T={T}\"\n _, _, HV, V = v.shape\n\n # Validate state shape\n assert state.shape == (B, HV, V, K), (\n f\"Expected state shape [B={B}, HV={HV}, V={V}, K={K}], got {state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n assert V % TILE_V == 0, (\n f\"V must be divisible by {TILE_V} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert state.dtype == torch.float32, f\"state must be float32, got {state.dtype}\"\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n # Note: kernel outputs bfloat16, we'll convert to q.dtype if needed\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # Convert state from [B, HV, V, K] to [B*HV, V, K] for kernel\n h0_source = state.reshape(B * HV, V, K)\n\n # Create dummy tensors for unused parameters\n h0_indices = torch.zeros(B, dtype=torch.int32, device=q.device)\n cu_seqlens = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel(*cache_key)\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Choose kernel based on batch size\n if B <= 32:\n run_func = run_gdn_decode_kernel_small_batch_pretranspose\n else:\n run_func = run_gdn_decode_kernel_big_batch_pretranspose\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n h0_source_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n B=B,\n T=T,\n H=H,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n cache[\"compiled\"](\n h0_source, A_log, a, dt_bias, q, k, v, b, output, h0_indices, cu_seqlens, stream\n )\n\n # Reshape state back (no sync needed - PyTorch handles stream ordering)\n state.copy_(h0_source.reshape(B, HV, V, K))\n\n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, state\n\n\n# ============================================================================\n# NONTRANSPOSE Version Kernels - K-major layout [pool, HV, K, V]\n# ============================================================================\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_nontranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n num_v_tiles: cutlass.Constexpr[int],\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n use_qk_l2norm: cutlass.Constexpr[bool],\n):\n \"\"\"Small batch kernel for (N, 1, ...) format with K-major state layout.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n in_warp_tid = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n\n NUM_WARPS_SMALL = 4\n V_PER_WARP_SMALL = TILE_V_SMALL_NT // NUM_WARPS_SMALL\n ROWS_PER_ITER_SMALL = 32 // V_PER_WARP_SMALL\n NUM_K_ITERS_SMALL = TILE_K_NT // ROWS_PER_ITER_SMALL\n\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE_SMALL_NT\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE_SMALL_NT\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE_SMALL_NT\n start_v_tile = batch_inner * num_v_tiles_per_block\n\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n pool_idx = h0_indices[i_n]\n\n if pool_idx >= 0:\n k_local = in_warp_tid // V_PER_WARP_SMALL\n v_local = in_warp_tid % V_PER_WARP_SMALL\n v_base = warp_idx * V_PER_WARP_SMALL\n v_idx = v_base + v_local\n\n smem = cutlass.utils.SmemAllocator()\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n smem_o_layout = cute.make_layout((TILE_V_SMALL_NT,), stride=(1,))\n smem_o = smem.allocate_tensor(cutlass.Float32, smem_o_layout, 128)\n smem_k_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n smem_q_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n sK = smem.allocate_tensor(cutlass.Float32, smem_k_layout, 128)\n sQ = smem.allocate_tensor(cutlass.Float32, smem_q_layout, 128)\n\n if tidx < TILE_K_NT:\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n\n gSrc_batch = h0_source[(pool_idx, i_hv, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_SMALL_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n prefetch_count = cutlass.min(NUM_STAGES_NT - 1, num_v_tiles_per_block)\n for v_tile_offset in range(prefetch_count):\n v_tile = start_v_tile + v_tile_offset\n stage = v_tile_offset % NUM_STAGES_NT\n gSrc_tile = gSrc[(None, None, v_tile)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_a = cutlass.Float32(a[i_n, 0, i_hv])\n r_b = cutlass.Float32(b[i_n, 0, i_hv])\n\n r_g = 0.0\n r_beta = 0.0\n if in_warp_tid == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n r_g_value = -cute.exp(r_A_log) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n r_g = cute.exp(r_g_value)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n cute.arch.barrier()\n\n if use_qk_l2norm:\n sum_q_partial = 0.0\n sum_k_partial = 0.0\n if tidx < TILE_K_NT:\n q_val = sQ[tidx]\n k_val = sK[tidx]\n sum_q_partial = q_val * q_val\n sum_k_partial = k_val * k_val\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q_partial += cute.arch.shuffle_sync_bfly(\n sum_q_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k_partial += cute.arch.shuffle_sync_bfly(\n sum_k_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n if in_warp_tid == 0:\n smem_o[warp_idx] = sum_q_partial\n smem_o[warp_idx + 4] = sum_k_partial\n cute.arch.barrier()\n\n inv_norm_q = 0.0\n inv_norm_k = 0.0\n if warp_idx == 0:\n local_sum_q = 0.0\n local_sum_k = 0.0\n if in_warp_tid < NUM_WARPS_SMALL:\n local_sum_q = smem_o[in_warp_tid]\n local_sum_k = smem_o[in_warp_tid + 4]\n for offset in [2, 1]:\n local_sum_q += cute.arch.shuffle_sync_bfly(\n local_sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n local_sum_k += cute.arch.shuffle_sync_bfly(\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n smem_o[0] = cute.rsqrt(local_sum_q + 1e-6)\n smem_o[1] = cute.rsqrt(local_sum_k + 1e-6)\n cute.arch.barrier()\n\n inv_norm_q = smem_o[0]\n inv_norm_k = smem_o[1]\n\n if tidx < TILE_K_NT:\n sK[tidx] = sK[tidx] * inv_norm_k\n sQ[tidx] = sQ[tidx] * scale * inv_norm_q\n cute.arch.barrier()\n else:\n if tidx < TILE_K_NT:\n sQ[tidx] = sQ[tidx] * scale\n cute.arch.barrier()\n\n for v_tile_offset in range(num_v_tiles_per_block):\n v_tile = start_v_tile + v_tile_offset\n stage = v_tile_offset % NUM_STAGES_NT\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n next_v_tile_offset = v_tile_offset + prefetch_count\n if next_v_tile_offset < num_v_tiles_per_block:\n next_v_tile = start_v_tile + next_v_tile_offset\n next_stage = next_v_tile_offset % NUM_STAGES_NT\n gSrc_next = gSrc[(None, None, next_v_tile)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n v_global = v_tile * TILE_V_SMALL_NT + v_idx\n r_v = cutlass.Float32(v[i_n, 0, i_hv, v_global])\n\n sum_hk = 0.0\n for k_iter in range(NUM_K_ITERS_SMALL, unroll=16): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_SMALL\n k_idx = k_base + k_local\n h_val = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n sum_hk += h_val * r_k_val\n\n for offset in [4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk,\n offset=offset * V_PER_WARP_SMALL,\n mask=-1,\n mask_and_clamp=31,\n )\n\n v_new = (r_v - sum_hk) * r_beta\n v_new = cute.arch.shuffle_sync(v_new, v_local)\n\n sum_hq = 0.0\n for k_iter in range(NUM_K_ITERS_SMALL, unroll=16): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_SMALL\n k_idx = k_base + k_local\n h_old = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n r_q_val = sQ[k_idx]\n h_new = h_old + r_k_val * v_new\n sData[(k_idx, v_idx, stage)] = h_new\n sum_hq += h_new * r_q_val\n\n for offset in [4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq,\n offset=offset * V_PER_WARP_SMALL,\n mask=-1,\n mask_and_clamp=31,\n )\n\n if k_local == 0:\n v_global_out = v_tile * TILE_V_SMALL_NT + v_idx\n o[(i_n, 0, i_hv, v_global_out)] = cutlass.BFloat16(sum_hq)\n\n cute.arch.barrier()\n\n for k_iter in range(NUM_K_ITERS_SMALL):\n flat_idx = tidx + k_iter * 128\n k_write = flat_idx // TILE_V_SMALL_NT\n v_write = flat_idx % TILE_V_SMALL_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_SMALL_NT + v_write\n h0_source[(pool_idx, i_hv, k_write, v_global_write)] = h_val\n\n cute.arch.barrier()\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_nontranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n num_v_tiles: cutlass.Constexpr[int],\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n use_qk_l2norm: cutlass.Constexpr[bool],\n):\n \"\"\"Large batch kernel for (N, 1, ...) format with K-major state layout.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n in_warp_tid = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n pool_idx = h0_indices[i_n]\n\n if pool_idx >= 0:\n k_local = in_warp_tid // V_PER_WARP_NT\n v_local = in_warp_tid % V_PER_WARP_NT\n v_base = warp_idx * V_PER_WARP_NT\n v_idx = v_base + v_local\n\n smem = cutlass.utils.SmemAllocator()\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n smem_o_layout = cute.make_layout((TILE_V_NT,), stride=(1,))\n smem_o = smem.allocate_tensor(cutlass.Float32, smem_o_layout, 128)\n smem_k_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n smem_q_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n sK = smem.allocate_tensor(cutlass.Float32, smem_k_layout, 128)\n sQ = smem.allocate_tensor(cutlass.Float32, smem_q_layout, 128)\n\n if tidx < TILE_K_NT:\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n\n gSrc_batch = h0_source[(pool_idx, i_hv, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n prefetch_count = cutlass.min(NUM_STAGES_NT - 1, num_v_tiles)\n for v_tile in range(prefetch_count):\n stage = v_tile % NUM_STAGES_NT\n gSrc_tile = gSrc[(None, None, v_tile)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_a = cutlass.Float32(a[i_n, 0, i_hv])\n r_b = cutlass.Float32(b[i_n, 0, i_hv])\n\n r_g = 0.0\n r_beta = 0.0\n if in_warp_tid == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n r_g_value = -cute.exp(r_A_log) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n r_g = cute.exp(r_g_value)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n cute.arch.barrier()\n\n if use_qk_l2norm:\n sum_q_partial = 0.0\n sum_k_partial = 0.0\n if tidx < TILE_K_NT:\n q_val = sQ[tidx]\n k_val = sK[tidx]\n sum_q_partial = q_val * q_val\n sum_k_partial = k_val * k_val\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q_partial += cute.arch.shuffle_sync_bfly(\n sum_q_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k_partial += cute.arch.shuffle_sync_bfly(\n sum_k_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n if in_warp_tid == 0:\n smem_o[warp_idx] = sum_q_partial\n smem_o[warp_idx + 8] = sum_k_partial\n cute.arch.barrier()\n\n inv_norm_q = 0.0\n inv_norm_k = 0.0\n if warp_idx == 0:\n local_sum_q = 0.0\n local_sum_k = 0.0\n if in_warp_tid < NUM_WARPS_LARGE_NT:\n local_sum_q = smem_o[in_warp_tid]\n local_sum_k = smem_o[in_warp_tid + 8]\n for offset in [4, 2, 1]:\n local_sum_q += cute.arch.shuffle_sync_bfly(\n local_sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n local_sum_k += cute.arch.shuffle_sync_bfly(\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n smem_o[0] = cute.rsqrt(local_sum_q + 1e-6)\n smem_o[1] = cute.rsqrt(local_sum_k + 1e-6)\n cute.arch.barrier()\n\n inv_norm_q = smem_o[0]\n inv_norm_k = smem_o[1]\n\n if tidx < TILE_K_NT:\n sK[tidx] = sK[tidx] * inv_norm_k\n sQ[tidx] = sQ[tidx] * scale * inv_norm_q\n cute.arch.barrier()\n else:\n if tidx < TILE_K_NT:\n sQ[tidx] = sQ[tidx] * scale\n cute.arch.barrier()\n\n for v_tile in range(num_v_tiles):\n stage = v_tile % NUM_STAGES_NT\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n next_v_tile = v_tile + prefetch_count\n if next_v_tile < num_v_tiles:\n next_stage = next_v_tile % NUM_STAGES_NT\n gSrc_next = gSrc[(None, None, next_v_tile)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n v_global = v_tile * TILE_V_NT + v_idx\n r_v = cutlass.Float32(v[i_n, 0, i_hv, v_global])\n\n sum_hk = 0.0\n for k_iter in range(NUM_K_ITERS_NT, unroll=8): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_NT\n k_idx = k_base + k_local\n h_val = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n sum_hk += h_val * r_k_val\n\n for offset in [4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset * V_PER_WARP_NT, mask=-1, mask_and_clamp=31\n )\n\n v_new = (r_v - sum_hk) * r_beta\n v_new = cute.arch.shuffle_sync(v_new, v_local)\n\n sum_hq = 0.0\n for k_iter in range(NUM_K_ITERS_NT, unroll=8): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_NT\n k_idx = k_base + k_local\n h_old = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n r_q_val = sQ[k_idx]\n h_new = h_old + r_k_val * v_new\n sData[(k_idx, v_idx, stage)] = h_new\n sum_hq += h_new * r_q_val\n\n for offset in [4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset * V_PER_WARP_NT, mask=-1, mask_and_clamp=31\n )\n\n if k_local == 0:\n v_global_out = v_tile * TILE_V_NT + v_idx\n o[(i_n, 0, i_hv, v_global_out)] = cutlass.BFloat16(sum_hq)\n\n cute.arch.barrier()\n\n for k_iter in range(NUM_K_ITERS_NT):\n flat_idx = tidx + k_iter * 256\n k_write = flat_idx // TILE_V_NT\n v_write = flat_idx % TILE_V_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_NT + v_write\n h0_source[(pool_idx, i_hv, k_write, v_global_write)] = h_val\n\n cute.arch.barrier()\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_nontranspose(\n cu_seqlens: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n h0_source: cute.Tensor,\n h0_indices: cute.Tensor,\n o: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n pool_size, hv_dim, k_dim, v_dim = h0_source.layout.shape\n n_indices = h0_indices.layout.shape[0]\n batch_size = n_indices * hv_dim\n\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n num_v_tiles_small = cute.ceil_div(v_dim, TILE_V_SMALL_NT)\n smem_layout_small = cute.make_layout(\n (TILE_K_NT, TILE_V_SMALL_NT, NUM_STAGES_NT),\n stride=(TILE_V_SMALL_PADDED_NT, 1, TILE_K_NT * TILE_V_SMALL_PADDED_NT),\n )\n thread_layout_small = cute.make_layout((32, 4), stride=(4, 1))\n val_layout_small = cute.make_layout((1, 4))\n tiled_copy_load_small = cute.make_tiled_copy_tv(\n copy_atom, thread_layout_small, val_layout_small\n )\n smem_bytes_small = (\n 4 * TILE_K_NT * TILE_V_SMALL_PADDED_NT * NUM_STAGES_NT\n + 4 * TILE_V_SMALL_NT\n + 4 * TILE_K_NT * 2\n + 64\n )\n\n gdn_decode_kernel_small_batch_nontranspose(\n tiled_copy_load_small,\n h0_source,\n smem_layout_small,\n num_v_tiles_small,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n o,\n h0_indices,\n softplus_beta,\n softplus_threshold,\n scale,\n H,\n HV,\n use_qk_l2norm,\n ).launch(\n grid=(batch_size * NUM_BLOCKS_PER_STATE_SMALL_NT, 1, 1),\n block=[NUM_THREADS_NT, 1, 1],\n smem=smem_bytes_small,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_nontranspose(\n cu_seqlens: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n h0_source: cute.Tensor,\n h0_indices: cute.Tensor,\n o: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n pool_size, hv_dim, k_dim, v_dim = h0_source.layout.shape\n n_indices = h0_indices.layout.shape[0]\n batch_size = n_indices * hv_dim\n\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n num_v_tiles = cute.ceil_div(v_dim, TILE_V_NT)\n base_smem_layout = cute.make_layout(\n (TILE_K_NT, TILE_V_NT, NUM_STAGES_NT),\n stride=(TILE_V_PADDED_NT, 1, TILE_K_NT * TILE_V_PADDED_NT),\n )\n thread_layout = cute.make_layout((32, 8), stride=(8, 1))\n val_layout = cute.make_layout((1, 4))\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n smem_bytes = (\n 4 * TILE_K_NT * TILE_V_PADDED_NT * NUM_STAGES_NT\n + 4 * TILE_V_NT\n + 4 * TILE_K_NT * 2\n + 64\n )\n\n gdn_decode_kernel_big_batch_nontranspose(\n tiled_copy_load,\n h0_source,\n base_smem_layout,\n num_v_tiles,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n o,\n h0_indices,\n softplus_beta,\n softplus_threshold,\n scale,\n H,\n HV,\n use_qk_l2norm,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS_LARGE_NT, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# FlashInfer API Layer - NONTRANSPOSE Version (Recommended)\n# ============================================================================\n\n\n@flashinfer_api\ndef gated_delta_rule_decode(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n state: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Gated Delta Rule Decode kernel (K-major layout, no transpose needed).\n\n This implements the decode phase of gated delta rule linear attention,\n processing one token at a time and updating the recurrent state.\n This version uses K-major state layout [B, HV, K, V] which is more natural\n and doesn't require transposition.\n\n Args:\n q (torch.Tensor):\n Current query of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n k (torch.Tensor):\n Current key of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n v (torch.Tensor):\n Current value of shape ``[B, 1, HV, V]``. Must be float16/bfloat16.\n state (torch.Tensor):\n Current state of shape ``[B, HV, K, V]`` (k-major layout).\n Must be float32. Will be updated in-place.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``. Must be float32.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``. Must be bfloat16 or float32.\n b (torch.Tensor):\n Update gate (beta) input of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n scale (Optional[float]):\n Scale factor for queries. If None, defaults to ``1 / sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, 1, HV, V]``.\n If None, will be allocated automatically.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, 1, HV, V]``\n - state: Updated state tensor of shape ``[B, HV, K, V]``\n\n Note:\n - Requires SM90 (Hopper) architecture\n - State is updated in-place\n - K and V must be multiples of 4 for vectorized loads\n - State layout is k-major: [B, HV, K, V] (no transpose needed)\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n assert T == 1, f\"Decode only supports T=1, got T={T}\"\n _, _, HV, V = v.shape\n\n # Validate state shape\n assert state.shape == (B, HV, K, V), (\n f\"Expected state shape [B={B}, HV={HV}, K={K}, V={V}], got {state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n # V must be divisible by tile size to prevent out-of-bounds access\n # For small batch: TILE_V_SMALL_NT=16, for large batch: TILE_V_NT=32\n # Use the more restrictive constraint (32) to cover both cases\n assert V % TILE_V_NT == 0, (\n f\"V must be divisible by {TILE_V_NT} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert state.dtype == torch.float32, f\"state must be float32, got {state.dtype}\"\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # State is already in K-major layout [B, HV, K, V]\n # Use state directly as pooled view: pool_size=B, each batch is its own pool\n h0_source = state.contiguous()\n\n # Create h0_indices: each batch points to its own pool index\n h0_indices = torch.arange(B, dtype=torch.int32, device=q.device)\n cu_seqlens = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel_nontranspose(*cache_key)\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Choose kernel based on batch size\n use_small_batch = B < SMALL_BATCH_THRESHOLD_NT\n\n if use_small_batch:\n run_func = run_gdn_decode_kernel_small_batch_nontranspose\n else:\n run_func = run_gdn_decode_kernel_big_batch_nontranspose\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n cu_seqlens_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n a_tensor,\n b_tensor,\n A_log_tensor,\n dt_bias_tensor,\n h0_source_tensor,\n h0_indices_tensor,\n o_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n B=B,\n T=T,\n H=H,\n HV=HV,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n compiled(\n cu_seqlens,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n h0_source,\n h0_indices,\n output,\n stream,\n )\n\n # Copy state back (no sync needed - PyTorch handles stream ordering)\n # h0_source is already [B, HV, K, V]\n state.copy_(h0_source)\n\n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, state\n\n\n# ============================================================================\n# MTP (Multiple Token Processing) Kernel - for T > 1 (verify mode)\n# ============================================================================\n\n\n@cute.kernel\ndef gdn_verify_kernel_mtp(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor, # [pool_size * HV, V, K] - initial state pool (K-last)\n intermediate_states: cute.Tensor, # [pool_size * T * HV, V, K] - intermediate state cache\n smem_layout_staged: cute.ComposedLayout, # Swizzled layout to avoid bank conflicts\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n disable_state_update: cutlass.Constexpr[bool],\n cache_intermediate_states: cutlass.Constexpr[bool],\n):\n \"\"\"\n Verify kernel with optimized loop order: (v_tiles outer, time_steps inner)\n\n Uses cute.make_rmem_tensor for register arrays (same style as decode kernel).\n Store-compute overlap: cache data in registers, store during next iteration.\n \"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n # Load A_log and dt_bias once (they don't vary with time)\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # Allocate shared memory with padding to avoid bank conflicts\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n sOutput = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T, V)), 16)\n # Pre-computed shared memory for all time steps (with padding for bank conflict avoidance)\n sQ = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sK = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sV = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, V), stride=(V + 8, 1)), 16\n )\n sG = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n sBeta = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n\n # Allocate register tensors\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n\n # Initialize output accumulator to zero\n for i_t in range(T):\n sOutput[(i_t, tidx)] = 0.0\n\n cute.arch.barrier()\n\n # Get initial state index for this batch\n cache_idx = h0_indices[i_n]\n\n # Early exit optimization: skip pre-computation for padding slots\n if cache_idx >= 0:\n # Pre-compute q, k, v, g, beta for all time steps (outside v_tiles loop)\n for i_t in range(T):\n # Load q, k into register arrays\n for i in range(vec_size):\n r_q[i] = cutlass.Float32(q[i_n, i_t, i_h, i * 32 + lane_id])\n r_k[i] = cutlass.Float32(k[i_n, i_t, i_h, i * 32 + lane_id])\n # Load v for all V elements\n sV[(i_t, i * 32 + lane_id)] = cutlass.Float32(\n v[i_n, i_t, i_hv, i * 32 + lane_id]\n )\n\n # Compute g and beta\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n r_g_value = -cute.exp(r_A_log) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n r_g = cute.exp(r_g_value)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n # Apply L2 normalization\n if use_qk_l2norm:\n sum_q = 0.0\n sum_k = 0.0\n for i in range(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6)\n\n for i in range(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling to q\n for i in range(vec_size):\n r_q[i] = r_q[i] * scale\n\n # Store pre-computed values to shared memory\n for i in range(vec_size):\n sQ[(i_t, i * 32 + lane_id)] = r_q[i]\n sK[(i_t, i * 32 + lane_id)] = r_k[i]\n\n # Store g and beta (only one thread needs to do this)\n if tidx == 0:\n sG[i_t] = r_g\n sBeta[i_t] = r_beta\n\n # All threads must participate in barrier (CUDA requirement)\n cute.arch.barrier()\n\n # Main computation only for valid batch entries\n if cache_idx >= 0:\n # Setup source tensor for initial state loading\n gSrc_batch = h0_source[(cache_idx * HV + i_hv, None, None)]\n gDst_h0 = cute.local_tile(\n h0_source, (1, TILE_V_MTP, TILE_K_MTP), (cache_idx * HV + i_hv, None, 0)\n )\n gSrc = cute.local_tile(gSrc_batch, (TILE_V_MTP, TILE_K_MTP), (None, 0))\n\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # Main loop: v_tiles (outer) x time_steps (inner)\n prefetch_count = cutlass.min(NUM_STAGES_MTP - 1, num_v_tiles)\n\n # Prefetch first v_tile(s)\n for v_tiles in range(prefetch_count):\n stage = v_tiles % NUM_STAGES_MTP\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Process each v_tile\n for v_tiles in range(num_v_tiles):\n stage = v_tiles % NUM_STAGES_MTP\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Prefetch next v_tile\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < num_v_tiles:\n next_stage = next_v_tiles % NUM_STAGES_MTP\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Inner loop: all time steps for this v_tile\n for i_t in range(T):\n # Load pre-computed values from shared memory\n for i in range(vec_size):\n r_q[i] = sQ[(i_t, i * 32 + lane_id)]\n r_k[i] = sK[(i_t, i * 32 + lane_id)]\n\n r_g = sG[i_t]\n r_beta = sBeta[i_t]\n\n # Compute delta rule for this v_tile\n for row in range(0, TILE_V_MTP, 4):\n row_offset = tidx // 32\n\n # Load h from sData, apply decay\n for i in range(vec_size):\n r_h[i] = (\n sData[(row + row_offset, i * 32 + lane_id, stage)] * r_g\n )\n\n # Compute sum_hk = h @ k\n sum_hk = 0.0\n for i in range(vec_size):\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Delta rule update\n v_idx = v_tiles * TILE_V_MTP + row + row_offset\n v_new = sV[(i_t, v_idx)] - sum_hk\n v_new = v_new * r_beta\n\n # Update h and write back to sData\n for i in range(vec_size):\n r_h[i] += r_k[i] * v_new\n sData[(row + row_offset, i * 32 + lane_id, stage)] = r_h[i]\n\n # Store intermediate state\n if cache_intermediate_states:\n flat_idx = i_n * T * HV + i_t * HV + i_hv\n if v_idx < V:\n for i in range(vec_size):\n intermediate_states[\n (flat_idx, v_idx, i * 32 + lane_id)\n ] = r_h[i]\n\n # Compute sum_hq = h @ q (overlaps with store above)\n sum_hq = 0.0\n for i in range(vec_size):\n sum_hq += r_h[i] * r_q[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V_MTP + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[(i_t, o_idx)] = cutlass.Float32(sum_hq)\n\n # Write final h for this v_tile to h0_source\n if not disable_state_update:\n for row in range(0, TILE_V_MTP, 4):\n row_offset = tidx // 32\n for i in range(vec_size):\n gDst_h0[(0, row + row_offset, i * 32 + lane_id, v_tiles)] = (\n sData[(row + row_offset, i * 32 + lane_id, stage)]\n )\n\n # Final writeback\n cute.arch.barrier()\n\n for i_t in range(T):\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = cutlass.BFloat16(sOutput[(i_t, tidx)])\n\n\n@cute.jit\ndef run_gdn_verify_kernel_mtp(\n h0_source: cute.Tensor,\n intermediate_states: cute.Tensor,\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n disable_state_update: cutlass.Constexpr[bool],\n cache_intermediate_states: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n _, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V_MTP)\n batch_size = B * HV\n vec_size = TILE_K_MTP // 32 # Each thread in a warp processes this many elements\n\n # Composed Swizzle Layout to avoid shared memory bank conflicts\n base_smem_layout = cute.make_layout(\n (TILE_V_MTP, TILE_K_MTP, NUM_STAGES_MTP),\n stride=(TILE_K_MTP, 1, TILE_V_MTP * TILE_K_MTP),\n )\n swizzle = cute.make_swizzle(2, 3, 7) # Swizzle<2, 3, 7>\n smem_layout_staged = cute.make_composed_layout(swizzle, 0, base_smem_layout)\n\n # Create tiled copy for G2S load\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n thread_layout = cute.make_layout((4, 32), stride=(32, 1))\n val_layout = cute.make_layout((1, 4))\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n # Calculate shared memory size\n smem_bytes = (\n 4 * TILE_V_MTP * TILE_K_MTP * NUM_STAGES_MTP\n + 4 * T * v_dim\n + 4 * T * (k_dim + 8)\n + 4 * T * (k_dim + 8)\n + 4 * T * (v_dim + 8)\n + 4 * T\n + 4 * T\n + 128\n )\n\n gdn_verify_kernel_mtp(\n tiled_copy_load,\n h0_source,\n intermediate_states,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n disable_state_update,\n cache_intermediate_states,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS_MTP, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@functools.cache\ndef _get_compiled_mtp_kernel(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n pool_size: int,\n cache_steps: int,\n disable_state_update: bool,\n cache_intermediate_states: bool,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled MTP kernel for given configuration.\"\"\"\n return {}\n\n\n@flashinfer_api\ndef gated_delta_rule_mtp(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n initial_state: torch.Tensor,\n initial_state_indices: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n intermediate_states_buffer: Optional[torch.Tensor] = None,\n disable_state_update: bool = True,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n \"\"\"\n Gated Delta Rule MTP Kernel (Multiple Token Processing).\n\n This function processes multiple tokens (T > 1) in sequence, typically used for\n speculative decoding verification. It supports intermediate state caching for\n potential rollback scenarios.\n\n Args:\n q (torch.Tensor):\n Query tensor of shape ``[B, T, H, K]``.\n k (torch.Tensor):\n Key tensor of shape ``[B, T, H, K]``.\n v (torch.Tensor):\n Value tensor of shape ``[B, T, HV, V]``.\n initial_state (torch.Tensor):\n Initial state tensor of shape ``[pool_size, HV, V, K]`` (K-last layout).\n initial_state_indices (torch.Tensor):\n Indices mapping each batch to its initial state, shape ``[B]``.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, T, HV]``.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``.\n b (torch.Tensor):\n Update gate input of shape ``[B, T, HV]``.\n scale (Optional[float]):\n Scaling factor for queries. If None, uses ``1/sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, T, HV, V]``.\n intermediate_states_buffer (Optional[torch.Tensor]):\n Buffer for caching intermediate states, shape ``[pool_size, T, HV, V, K]``.\n If None, intermediate states are not cached.\n disable_state_update (bool):\n If True, the initial state is not updated. Default: ``True``.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, T, HV, V]``\n - initial_state: Updated state tensor (unchanged if disable_state_update=True)\n\n Note:\n - Requires SM90 (Hopper) architecture\n - Supports T > 1 (multiple token processing)\n - State layout is K-last: [pool_size, HV, V, K]\n - Optimized for speculative decoding verification scenarios\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n _, _, HV, V = v.shape\n pool_size = initial_state.shape[0]\n\n # Validate state shape\n assert initial_state.shape == (pool_size, HV, V, K), (\n f\"Expected initial_state shape [pool_size={pool_size}, HV={HV}, V={V}, K={K}], got {initial_state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n assert V % TILE_V_MTP == 0, (\n f\"V must be divisible by {TILE_V_MTP} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert initial_state.dtype == torch.float32, (\n f\"initial_state must be float32, got {initial_state.dtype}\"\n )\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # Reshape initial_state from [pool_size, HV, V, K] to [pool_size * HV, V, K]\n h0_source = initial_state.to(torch.float32).reshape(pool_size * HV, V, K)\n\n # Handle intermediate states\n cache_intermediate_states = intermediate_states_buffer is not None\n if cache_intermediate_states:\n buffer_size = intermediate_states_buffer.shape[0]\n cache_steps = intermediate_states_buffer.shape[1]\n\n # Validate buffer length matches query sequence length\n assert cache_steps >= T, (\n f\"intermediate_states_buffer second dimension (cache_steps={cache_steps}) must be at least T={T} to prevent out-of-bounds indexing\"\n )\n\n intermediate_states = (\n intermediate_states_buffer.to(torch.float32)\n .reshape(buffer_size * cache_steps * HV, V, K)\n .contiguous()\n )\n else:\n cache_steps = T\n intermediate_states = torch.zeros(1, 1, 1, dtype=torch.float32, device=q.device)\n\n # Create cu_seqlens\n cu_seqlens = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (\n B,\n T,\n H,\n HV,\n K,\n V,\n pool_size,\n cache_steps,\n disable_state_update,\n cache_intermediate_states,\n scale,\n use_qk_l2norm,\n )\n cache = _get_compiled_mtp_kernel(*cache_key)\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n intermediate_states_tensor = from_dlpack(intermediate_states, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(initial_state_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_gdn_verify_kernel_mtp,\n h0_source_tensor,\n intermediate_states_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n B=B,\n T=T,\n H=H,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n disable_state_update=disable_state_update,\n cache_intermediate_states=cache_intermediate_states,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n compiled(\n h0_source,\n intermediate_states,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n output,\n initial_state_indices,\n cu_seqlens,\n stream,\n )\n\n # Copy state back if needed (no sync needed - PyTorch handles stream ordering)\n if not disable_state_update:\n initial_state.copy_(h0_source.reshape(pool_size, HV, V, K))\n\n # Convert output to target dtype if needed\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, initial_state\n"},"after_code":{"kind":"string","value":"\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\n\"\"\"\nGated Delta Rule Decode Kernel - Single Token Generation\n\nThis file implements a fused CUDA kernel using CUTLASS CuTe DSL for executing\nSigmoid Gating Delta Rule updates during decode phase. Key features:\n\nArchitecture Design:\n- Uses TMA (Tensor Memory Accelerator) for efficient Global Memory → Shared Memory transfers\n- Employs 2-stage pipeline to overlap loading and computation, hiding memory latency\n- Each block uses 128 threads (4 warps), with each warp processing one matrix row\n- Tile size: 8x128 (TILE_V x TILE_K)\n\nComputation Flow:\n1. Warp 0 handles TMA prefetch, loading data from GMEM to SMEM\n2. All warps compute in parallel: softplus, L2 normalization, delta rule updates\n3. Each warp processes one row of data, completing h_new = g*h + k*(beta*(v - h@k))\n4. Uses warp-level shuffle for efficient reduction operations\n5. Results are vectorized and written back to Global Memory\n\nPerformance Optimizations:\n- Vectorized memory access: each thread processes vec_size=4 elements (128-bit aligned)\n- Warp-level collective operations: shuffle-based reduction\n- Pipeline overlap: load stage N+1 while computing stage N\n\"\"\"\n\nimport functools\nfrom typing import Optional, Tuple\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass.cute.nvgpu import cpasync\nfrom cutlass.cute.runtime import from_dlpack\nimport cuda.bindings.driver as cuda\n\ntry:\n from .api_logging import flashinfer_api\n\n _FLASHINFER_AVAILABLE = True\nexcept ImportError:\n _FLASHINFER_AVAILABLE = False\n\n # Fallback decorator for standalone usage\n def flashinfer_api(func): # type: ignore[misc]\n return func\n\n\n# ============================================================================\n# Global configuration for PRETRANSPOSE version ([B*HV, V, K])\n# ============================================================================\nTILE_V = 8\nTILE_K = 128\nNUM_STAGES = 2\nNUM_THREADS = 128 # 4 warps\nNUM_BLOCKS_PER_STATE = 8\n\n# ============================================================================\n# Global configuration for NONTRANSPOSE version ([pool, HV, K, V])\n# ============================================================================\nTILE_K_NT = 128\nTILE_V_NT = 32\nTILE_V_PADDED_NT = 36\nTILE_V_SMALL_NT = 16\nTILE_V_SMALL_PADDED_NT = 20\nNUM_STAGES_NT = 2\nNUM_THREADS_NT = 128\nNUM_BLOCKS_PER_STATE_SMALL_NT = 8\nNUM_THREADS_LARGE_NT = 256\nNUM_WARPS_LARGE_NT = 8\nV_PER_WARP_NT = 4\nROWS_PER_ITER_NT = 8\nNUM_K_ITERS_NT = TILE_K_NT // ROWS_PER_ITER_NT\nSMALL_BATCH_THRESHOLD_NT = 32\n\n# ============================================================================\n# Global configuration for MTP (Multiple Token Processing) version\n# ============================================================================\n# Dynamic kernel selection based on batch size:\n# - Small batch (B <= threshold): Use smaller TILE_V for more parallelism\n# Optimal TILE_V depends on batch size (empirically determined):\n# B=1-2: TILE_V=4 (more blocks, better parallelism for tiny batches)\n# B=4: TILE_V=8 (intermediate parallelism)\n# B=8: TILE_V=16 (balance between parallelism and efficiency)\n# B>=16: TILE_V=32 (fewer blocks, better efficiency for large batches)\n\nTILE_K_MTP = 128 # Full K dimension (shared across all configs)\nNUM_THREADS_MTP = 128 # 4 warps (shared across all configs)\n\n\ndef get_vec_size_mtp(batch_size: int, seq_len: int = 1) -> int:\n \"\"\"Select vec_size for MTP kernel.\n\n Always use vec_size=4 (32 threads per group = full warp, 4 groups per block).\n Full warp shuffle is more efficient and achieves >= 1.0x speedup vs Triton.\n \"\"\"\n return 4\n\n\ndef get_tile_v_mtp(batch_size: int, seq_len: int = 1) -> int:\n \"\"\"Select optimal TILE_V for MTP kernel based on batch size and sequence length.\n\n With vec_size=4, num_groups=4, rows_per_group = tile_v / 4.\n Tuned via grid search for optimal performance.\n \"\"\"\n if batch_size <= 2:\n return 4 # Small batch needs max parallelism\n elif batch_size <= 4:\n return 8\n elif batch_size <= 8:\n return 16\n elif batch_size <= 16:\n return 32\n else:\n return 64\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n cute.arch.barrier()\n\n # Get current batch\n gSrc_batch = h0_source[(batch_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (batch_idx, None, 0))\n\n # V 方向分 tiles\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n start_v_tiles = batch_inner * num_v_tiles_per_block\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles_per_block)\n for v_tiles in range(start_v_tiles, start_v_tiles + prefetch_count):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n end_v_tiles = start_v_tiles + num_v_tiles_per_block\n for v_tiles in range(start_v_tiles, end_v_tiles):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < end_v_tiles:\n next_stage = (next_v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n gDst_tile = cute.local_tile(\n gDst, (1, 1, vec_size, 1), (0, row + row_offset, lane_id, v_tiles)\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n if tidx >= start_v_tiles * TILE_V and tidx < end_v_tiles * TILE_V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k, v loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_v_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Compute k_start for contiguous access pattern\n k_start = lane_id * vec_size\n\n cute.arch.barrier()\n\n # Get current batch\n gSrc_batch = h0_source[(batch_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (batch_idx, None, 0))\n\n # V 方向分 tiles\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles)\n for v_tiles in range(prefetch_count):\n stage = v_tiles % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n cute.autovec_copy(v_tile, r_v_bf16)\n for i in cutlass.range_constexpr(vec_size):\n sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling in Float32\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n for v_tiles in range(num_v_tiles):\n stage = v_tiles % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < num_v_tiles:\n next_stage = next_v_tiles % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage (contiguous access pattern)\n for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n\n # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n sData_tile = cute.local_tile(\n sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n )\n cute.autovec_copy(sData_tile, r_h)\n\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n sum_hq += r_h[i] * r_q[i]\n\n # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n gDst_tile = cute.local_tile(\n gDst, (1, 1, vec_size, 1), (0, row + row_offset, lane_id, v_tiles)\n )\n cute.autovec_copy(r_h, gDst_tile)\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n \"\"\"Launch original pipelined kernel for small batch pretranspose.\"\"\"\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * batch_size * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n ).launch(\n grid=(batch_size * NUM_BLOCKS_PER_STATE, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * batch_size * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # print(f\"Batched CP.ASYNC Load + Store (bypass L1 cache)\")\n # print(f\" {batch_size} batches x {v_dim}x{k_dim} matrices\")\n # print(f\" Tile: {TILE_V}x{TILE_K}, {num_v_tiles} tiles/batch\")\n # print(f\" Threads: {NUM_THREADS} ({NUM_THREADS // 32} warps), vec_size: {vec_size}\")\n # print(f\" Total: {total_data_mb:.1f} MB\\n\")\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# FlashInfer API Layer\n# ============================================================================\n\n\n@functools.cache\ndef _get_compiled_decode_kernel(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled kernel for given configuration (pretranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\n@functools.cache\ndef _get_compiled_decode_kernel_nontranspose(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled kernel for given configuration (nontranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\n@flashinfer_api\ndef gated_delta_rule_decode_pretranspose(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n state: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Gated Delta Rule Decode kernel for single-token generation.\n\n This implements the decode phase of gated delta rule linear attention,\n processing one token at a time and updating the recurrent state.\n\n Args:\n q (torch.Tensor):\n Current query of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n k (torch.Tensor):\n Current key of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n v (torch.Tensor):\n Current value of shape ``[B, 1, HV, V]``. Must be float16/bfloat16.\n state (torch.Tensor):\n Current state of shape ``[B, HV, V, K]`` (v-major layout).\n Must be float32. Will be updated in-place.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``. Must be float32.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``. Must be bfloat16 or float32.\n b (torch.Tensor):\n Update gate (beta) input of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n scale (Optional[float]):\n Scale factor for queries. If None, defaults to ``1 / sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, 1, HV, V]``.\n If None, will be allocated automatically.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, 1, HV, V]``\n - state: Updated state tensor of shape ``[B, HV, V, K]``\n\n Note:\n - Requires SM90 (Hopper) architecture\n - State is updated in-place\n - K and V must be multiples of 4 for vectorized loads\n - State layout is v-major: [B, HV, V, K]\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n assert T == 1, f\"Decode only supports T=1, got T={T}\"\n _, _, HV, V = v.shape\n\n # Validate state shape\n assert state.shape == (B, HV, V, K), (\n f\"Expected state shape [B={B}, HV={HV}, V={V}, K={K}], got {state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n assert V % TILE_V == 0, (\n f\"V must be divisible by {TILE_V} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert state.dtype == torch.float32, f\"state must be float32, got {state.dtype}\"\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n # Note: kernel outputs bfloat16, we'll convert to q.dtype if needed\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # Convert state from [B, HV, V, K] to [B*HV, V, K] for kernel\n h0_source = state.reshape(B * HV, V, K)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel(*cache_key)\n\n # Get or create h0_indices and cu_seqlens (cached per config)\n if \"h0_indices\" not in cache or cache[\"h0_indices\"].device != q.device:\n cache[\"h0_indices\"] = torch.zeros(B, dtype=torch.int32, device=q.device)\n cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n h0_indices = cache[\"h0_indices\"]\n cu_seqlens = cache[\"cu_seqlens\"]\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Choose kernel based on batch size\n if B <= 32:\n run_func = run_gdn_decode_kernel_small_batch_pretranspose\n else:\n run_func = run_gdn_decode_kernel_big_batch_pretranspose\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n h0_source_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n B=B,\n T=T,\n H=H,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n cache[\"compiled\"](\n h0_source, A_log, a, dt_bias, q, k, v, b, output, h0_indices, cu_seqlens, stream\n )\n\n # Copy state back only if state was not contiguous\n # (if contiguous, reshape returns a view and kernel updated state in-place)\n if not state.is_contiguous():\n state.copy_(h0_source.reshape(B, HV, V, K))\n\n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, state\n\n\n# ============================================================================\n# NONTRANSPOSE Version Kernels - K-major layout [pool, HV, K, V]\n# ============================================================================\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_nontranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n num_v_tiles: cutlass.Constexpr[int],\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n use_qk_l2norm: cutlass.Constexpr[bool],\n):\n \"\"\"Small batch kernel for (N, 1, ...) format with K-major state layout.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n in_warp_tid = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n\n NUM_WARPS_SMALL = 4\n V_PER_WARP_SMALL = TILE_V_SMALL_NT // NUM_WARPS_SMALL\n ROWS_PER_ITER_SMALL = 32 // V_PER_WARP_SMALL\n NUM_K_ITERS_SMALL = TILE_K_NT // ROWS_PER_ITER_SMALL\n\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE_SMALL_NT\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE_SMALL_NT\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE_SMALL_NT\n start_v_tile = batch_inner * num_v_tiles_per_block\n\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n pool_idx = h0_indices[i_n]\n\n if pool_idx >= 0:\n k_local = in_warp_tid // V_PER_WARP_SMALL\n v_local = in_warp_tid % V_PER_WARP_SMALL\n v_base = warp_idx * V_PER_WARP_SMALL\n v_idx = v_base + v_local\n\n smem = cutlass.utils.SmemAllocator()\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n smem_o_layout = cute.make_layout((TILE_V_SMALL_NT,), stride=(1,))\n smem_o = smem.allocate_tensor(cutlass.Float32, smem_o_layout, 128)\n smem_k_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n smem_q_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n sK = smem.allocate_tensor(cutlass.Float32, smem_k_layout, 128)\n sQ = smem.allocate_tensor(cutlass.Float32, smem_q_layout, 128)\n\n if tidx < TILE_K_NT:\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n\n # Compute flat index for flattened state [B*HV, K, V]\n flat_idx = pool_idx * HV + i_hv\n gSrc_batch = h0_source[(flat_idx, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_SMALL_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n prefetch_count = cutlass.min(NUM_STAGES_NT - 1, num_v_tiles_per_block)\n for v_tile_offset in range(prefetch_count):\n v_tile = start_v_tile + v_tile_offset\n stage = v_tile_offset % NUM_STAGES_NT\n gSrc_tile = gSrc[(None, None, v_tile)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_a = cutlass.Float32(a[i_n, 0, i_hv])\n r_b = cutlass.Float32(b[i_n, 0, i_hv])\n\n r_g = 0.0\n r_beta = 0.0\n if in_warp_tid == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n cute.arch.barrier()\n\n if use_qk_l2norm:\n sum_q_partial = 0.0\n sum_k_partial = 0.0\n if tidx < TILE_K_NT:\n q_val = sQ[tidx]\n k_val = sK[tidx]\n sum_q_partial = q_val * q_val\n sum_k_partial = k_val * k_val\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q_partial += cute.arch.shuffle_sync_bfly(\n sum_q_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k_partial += cute.arch.shuffle_sync_bfly(\n sum_k_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n if in_warp_tid == 0:\n smem_o[warp_idx] = sum_q_partial\n smem_o[warp_idx + 4] = sum_k_partial\n cute.arch.barrier()\n\n inv_norm_q = 0.0\n inv_norm_k = 0.0\n if warp_idx == 0:\n local_sum_q = 0.0\n local_sum_k = 0.0\n if in_warp_tid < NUM_WARPS_SMALL:\n local_sum_q = smem_o[in_warp_tid]\n local_sum_k = smem_o[in_warp_tid + 4]\n for offset in [2, 1]:\n local_sum_q += cute.arch.shuffle_sync_bfly(\n local_sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n local_sum_k += cute.arch.shuffle_sync_bfly(\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n smem_o[0] = cute.rsqrt(local_sum_q + 1e-6, fastmath=True)\n smem_o[1] = cute.rsqrt(local_sum_k + 1e-6, fastmath=True)\n cute.arch.barrier()\n\n inv_norm_q = smem_o[0]\n inv_norm_k = smem_o[1]\n\n if tidx < TILE_K_NT:\n sK[tidx] = sK[tidx] * inv_norm_k\n sQ[tidx] = sQ[tidx] * scale * inv_norm_q\n cute.arch.barrier()\n else:\n if tidx < TILE_K_NT:\n sQ[tidx] = sQ[tidx] * scale\n cute.arch.barrier()\n\n for v_tile_offset in range(num_v_tiles_per_block):\n v_tile = start_v_tile + v_tile_offset\n stage = v_tile_offset % NUM_STAGES_NT\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n next_v_tile_offset = v_tile_offset + prefetch_count\n if next_v_tile_offset < num_v_tiles_per_block:\n next_v_tile = start_v_tile + next_v_tile_offset\n next_stage = next_v_tile_offset % NUM_STAGES_NT\n gSrc_next = gSrc[(None, None, next_v_tile)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n v_global = v_tile * TILE_V_SMALL_NT + v_idx\n r_v = cutlass.Float32(v[i_n, 0, i_hv, v_global])\n\n sum_hk = 0.0\n for k_iter in range(NUM_K_ITERS_SMALL, unroll=16): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_SMALL\n k_idx = k_base + k_local\n h_val = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n sum_hk += h_val * r_k_val\n\n for offset in [4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk,\n offset=offset * V_PER_WARP_SMALL,\n mask=-1,\n mask_and_clamp=31,\n )\n\n v_new = (r_v - sum_hk) * r_beta\n v_new = cute.arch.shuffle_sync(v_new, v_local)\n\n sum_hq = 0.0\n for k_iter in range(NUM_K_ITERS_SMALL, unroll=16): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_SMALL\n k_idx = k_base + k_local\n h_old = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n r_q_val = sQ[k_idx]\n h_new = h_old + r_k_val * v_new\n sData[(k_idx, v_idx, stage)] = h_new\n sum_hq += h_new * r_q_val\n\n for offset in [4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq,\n offset=offset * V_PER_WARP_SMALL,\n mask=-1,\n mask_and_clamp=31,\n )\n\n if k_local == 0:\n v_global_out = v_tile * TILE_V_SMALL_NT + v_idx\n o[(i_n, 0, i_hv, v_global_out)] = cutlass.BFloat16(sum_hq)\n\n cute.arch.barrier()\n\n for k_iter in cutlass.range_constexpr(NUM_K_ITERS_SMALL):\n flat_tid = tidx + k_iter * 128\n k_write = flat_tid // TILE_V_SMALL_NT\n v_write = flat_tid % TILE_V_SMALL_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_SMALL_NT + v_write\n # Use flat index for flattened state [B*HV, K, V]\n h0_source[(flat_idx, k_write, v_global_write)] = h_val\n\n cute.arch.barrier()\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_nontranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n num_v_tiles: cutlass.Constexpr[int],\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n use_qk_l2norm: cutlass.Constexpr[bool],\n):\n \"\"\"Large batch kernel for (N, 1, ...) format with K-major state layout.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n in_warp_tid = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n pool_idx = h0_indices[i_n]\n\n if pool_idx >= 0:\n k_local = in_warp_tid // V_PER_WARP_NT\n v_local = in_warp_tid % V_PER_WARP_NT\n v_base = warp_idx * V_PER_WARP_NT\n v_idx = v_base + v_local\n\n smem = cutlass.utils.SmemAllocator()\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n smem_o_layout = cute.make_layout((TILE_V_NT,), stride=(1,))\n smem_o = smem.allocate_tensor(cutlass.Float32, smem_o_layout, 128)\n smem_k_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n smem_q_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n sK = smem.allocate_tensor(cutlass.Float32, smem_k_layout, 128)\n sQ = smem.allocate_tensor(cutlass.Float32, smem_q_layout, 128)\n\n if tidx < TILE_K_NT:\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n\n # Compute flat index for flattened state [B*HV, K, V]\n flat_idx = pool_idx * HV + i_hv\n gSrc_batch = h0_source[(flat_idx, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n prefetch_count = cutlass.min(NUM_STAGES_NT - 1, num_v_tiles)\n for v_tile in range(prefetch_count):\n stage = v_tile % NUM_STAGES_NT\n gSrc_tile = gSrc[(None, None, v_tile)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_a = cutlass.Float32(a[i_n, 0, i_hv])\n r_b = cutlass.Float32(b[i_n, 0, i_hv])\n\n r_g = 0.0\n r_beta = 0.0\n if in_warp_tid == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n r_g = cute.exp(r_g_value, fastmath=True)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n cute.arch.barrier()\n\n if use_qk_l2norm:\n sum_q_partial = 0.0\n sum_k_partial = 0.0\n if tidx < TILE_K_NT:\n q_val = sQ[tidx]\n k_val = sK[tidx]\n sum_q_partial = q_val * q_val\n sum_k_partial = k_val * k_val\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q_partial += cute.arch.shuffle_sync_bfly(\n sum_q_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k_partial += cute.arch.shuffle_sync_bfly(\n sum_k_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n if in_warp_tid == 0:\n smem_o[warp_idx] = sum_q_partial\n smem_o[warp_idx + 8] = sum_k_partial\n cute.arch.barrier()\n\n inv_norm_q = 0.0\n inv_norm_k = 0.0\n if warp_idx == 0:\n local_sum_q = 0.0\n local_sum_k = 0.0\n if in_warp_tid < NUM_WARPS_LARGE_NT:\n local_sum_q = smem_o[in_warp_tid]\n local_sum_k = smem_o[in_warp_tid + 8]\n for offset in [4, 2, 1]:\n local_sum_q += cute.arch.shuffle_sync_bfly(\n local_sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n local_sum_k += cute.arch.shuffle_sync_bfly(\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n smem_o[0] = cute.rsqrt(local_sum_q + 1e-6, fastmath=True)\n smem_o[1] = cute.rsqrt(local_sum_k + 1e-6, fastmath=True)\n cute.arch.barrier()\n\n inv_norm_q = smem_o[0]\n inv_norm_k = smem_o[1]\n\n if tidx < TILE_K_NT:\n sK[tidx] = sK[tidx] * inv_norm_k\n sQ[tidx] = sQ[tidx] * scale * inv_norm_q\n cute.arch.barrier()\n else:\n if tidx < TILE_K_NT:\n sQ[tidx] = sQ[tidx] * scale\n cute.arch.barrier()\n\n for v_tile in range(num_v_tiles):\n stage = v_tile % NUM_STAGES_NT\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n next_v_tile = v_tile + prefetch_count\n if next_v_tile < num_v_tiles:\n next_stage = next_v_tile % NUM_STAGES_NT\n gSrc_next = gSrc[(None, None, next_v_tile)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n v_global = v_tile * TILE_V_NT + v_idx\n r_v = cutlass.Float32(v[i_n, 0, i_hv, v_global])\n\n sum_hk = 0.0\n for k_iter in range(NUM_K_ITERS_NT, unroll=8): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_NT\n k_idx = k_base + k_local\n h_val = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n sum_hk += h_val * r_k_val\n\n for offset in [4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset * V_PER_WARP_NT, mask=-1, mask_and_clamp=31\n )\n\n v_new = (r_v - sum_hk) * r_beta\n v_new = cute.arch.shuffle_sync(v_new, v_local)\n\n sum_hq = 0.0\n for k_iter in range(NUM_K_ITERS_NT, unroll=8): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_NT\n k_idx = k_base + k_local\n h_old = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n r_q_val = sQ[k_idx]\n h_new = h_old + r_k_val * v_new\n sData[(k_idx, v_idx, stage)] = h_new\n sum_hq += h_new * r_q_val\n\n for offset in [4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset * V_PER_WARP_NT, mask=-1, mask_and_clamp=31\n )\n\n if k_local == 0:\n v_global_out = v_tile * TILE_V_NT + v_idx\n o[(i_n, 0, i_hv, v_global_out)] = cutlass.BFloat16(sum_hq)\n\n cute.arch.barrier()\n\n for k_iter in cutlass.range_constexpr(NUM_K_ITERS_NT):\n flat_tid = tidx + k_iter * 256\n k_write = flat_tid // TILE_V_NT\n v_write = flat_tid % TILE_V_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_NT + v_write\n # Use flat index for flattened state [B*HV, K, V]\n h0_source[(flat_idx, k_write, v_global_write)] = h_val\n\n cute.arch.barrier()\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_nontranspose(\n cu_seqlens: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n h0_source: cute.Tensor,\n h0_indices: cute.Tensor,\n o: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source is flattened to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n batch_hv_dim, k_dim, v_dim = h0_source.layout.shape\n h0_indices.layout.shape[0]\n batch_size = batch_hv_dim # batch_hv_dim = B * HV\n\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n num_v_tiles_small = cute.ceil_div(v_dim, TILE_V_SMALL_NT)\n smem_layout_small = cute.make_layout(\n (TILE_K_NT, TILE_V_SMALL_NT, NUM_STAGES_NT),\n stride=(TILE_V_SMALL_PADDED_NT, 1, TILE_K_NT * TILE_V_SMALL_PADDED_NT),\n )\n thread_layout_small = cute.make_layout((32, 4), stride=(4, 1))\n val_layout_small = cute.make_layout((1, 4))\n tiled_copy_load_small = cute.make_tiled_copy_tv(\n copy_atom, thread_layout_small, val_layout_small\n )\n smem_bytes_small = (\n 4 * TILE_K_NT * TILE_V_SMALL_PADDED_NT * NUM_STAGES_NT\n + 4 * TILE_V_SMALL_NT\n + 4 * TILE_K_NT * 2\n + 64\n )\n\n gdn_decode_kernel_small_batch_nontranspose(\n tiled_copy_load_small,\n h0_source,\n smem_layout_small,\n num_v_tiles_small,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n o,\n h0_indices,\n softplus_beta,\n softplus_threshold,\n scale,\n H,\n HV,\n use_qk_l2norm,\n ).launch(\n grid=(batch_size * NUM_BLOCKS_PER_STATE_SMALL_NT, 1, 1),\n block=[NUM_THREADS_NT, 1, 1],\n smem=smem_bytes_small,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_nontranspose(\n cu_seqlens: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n h0_source: cute.Tensor,\n h0_indices: cute.Tensor,\n o: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source is flattened to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n batch_hv_dim, k_dim, v_dim = h0_source.layout.shape\n h0_indices.layout.shape[0]\n batch_size = batch_hv_dim # batch_hv_dim = B * HV\n\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n num_v_tiles = cute.ceil_div(v_dim, TILE_V_NT)\n base_smem_layout = cute.make_layout(\n (TILE_K_NT, TILE_V_NT, NUM_STAGES_NT),\n stride=(TILE_V_PADDED_NT, 1, TILE_K_NT * TILE_V_PADDED_NT),\n )\n thread_layout = cute.make_layout((32, 8), stride=(8, 1))\n val_layout = cute.make_layout((1, 4))\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n smem_bytes = (\n 4 * TILE_K_NT * TILE_V_PADDED_NT * NUM_STAGES_NT\n + 4 * TILE_V_NT\n + 4 * TILE_K_NT * 2\n + 64\n )\n\n gdn_decode_kernel_big_batch_nontranspose(\n tiled_copy_load,\n h0_source,\n base_smem_layout,\n num_v_tiles,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n o,\n h0_indices,\n softplus_beta,\n softplus_threshold,\n scale,\n H,\n HV,\n use_qk_l2norm,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS_LARGE_NT, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# FlashInfer API Layer - NONTRANSPOSE Version (Recommended)\n# ============================================================================\n\n\n@flashinfer_api\ndef gated_delta_rule_decode(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n state: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Gated Delta Rule Decode kernel (K-major layout, no transpose needed).\n\n This implements the decode phase of gated delta rule linear attention,\n processing one token at a time and updating the recurrent state.\n This version uses K-major state layout [B, HV, K, V] which is more natural\n and doesn't require transposition.\n\n Args:\n q (torch.Tensor):\n Current query of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n k (torch.Tensor):\n Current key of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n v (torch.Tensor):\n Current value of shape ``[B, 1, HV, V]``. Must be float16/bfloat16.\n state (torch.Tensor):\n Current state of shape ``[B, HV, K, V]`` (k-major layout).\n Must be float32. Will be updated in-place.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``. Must be float32.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``. Must be bfloat16 or float32.\n b (torch.Tensor):\n Update gate (beta) input of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n scale (Optional[float]):\n Scale factor for queries. If None, defaults to ``1 / sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, 1, HV, V]``.\n If None, will be allocated automatically.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, 1, HV, V]``\n - state: Updated state tensor of shape ``[B, HV, K, V]``\n\n Note:\n - Requires SM90 (Hopper) architecture\n - State is updated in-place\n - K and V must be multiples of 4 for vectorized loads\n - State layout is k-major: [B, HV, K, V] (no transpose needed)\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n assert T == 1, f\"Decode only supports T=1, got T={T}\"\n _, _, HV, V = v.shape\n\n # Validate state shape\n assert state.shape == (B, HV, K, V), (\n f\"Expected state shape [B={B}, HV={HV}, K={K}, V={V}], got {state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n # V must be divisible by tile size to prevent out-of-bounds access\n # For small batch: TILE_V_SMALL_NT=16, for large batch: TILE_V_NT=32\n # Use the more restrictive constraint (32) to cover both cases\n assert V % TILE_V_NT == 0, (\n f\"V must be divisible by {TILE_V_NT} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert state.dtype == torch.float32, f\"state must be float32, got {state.dtype}\"\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # State is in K-major layout [B, HV, K, V]\n # Flatten to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n # This avoids alignment issues when B=1 (zero strides cause alignment failures)\n state_contiguous = state.contiguous()\n h0_source = state_contiguous.view(B * HV, K, V)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel_nontranspose(*cache_key)\n\n # Get or create h0_indices and cu_seqlens (cached per config)\n if \"h0_indices\" not in cache or cache[\"h0_indices\"].device != q.device:\n cache[\"h0_indices\"] = torch.arange(B, dtype=torch.int32, device=q.device)\n cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n h0_indices = cache[\"h0_indices\"]\n cu_seqlens = cache[\"cu_seqlens\"]\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Choose kernel based on batch size\n use_small_batch = B < SMALL_BATCH_THRESHOLD_NT\n\n if use_small_batch:\n run_func = run_gdn_decode_kernel_small_batch_nontranspose\n else:\n run_func = run_gdn_decode_kernel_big_batch_nontranspose\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n cu_seqlens_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n a_tensor,\n b_tensor,\n A_log_tensor,\n dt_bias_tensor,\n h0_source_tensor,\n h0_indices_tensor,\n o_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n B=B,\n T=T,\n H=H,\n HV=HV,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n compiled(\n cu_seqlens,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n h0_source,\n h0_indices,\n output,\n stream,\n )\n\n # Copy state back only if state was not contiguous\n # (if contiguous, state_contiguous is state itself, so kernel updated state in-place)\n if state_contiguous.data_ptr() != state.data_ptr():\n state.copy_(state_contiguous)\n\n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, state\n\n\n# ============================================================================\n# MTP (Multiple Token Processing) Kernel - for T > 1 (verify mode)\n# ============================================================================\n\n\n@cute.kernel\ndef gdn_verify_kernel_mtp(\n h0_source: cute.Tensor, # [pool_size * HV, V, K] - initial state pool (K-last)\n intermediate_states: cute.Tensor, # [pool_size * T * HV, V, K] - intermediate state cache\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n tile_v: cutlass.Constexpr[int], # TILE_V - configurable for batch size\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n disable_state_update: cutlass.Constexpr[bool],\n cache_intermediate_states: cutlass.Constexpr[bool],\n):\n \"\"\"\n Parallel MTP kernel - each block handles one [TILE_V, TILE_K] tile.\n\n Grid: (B * HV * num_v_tiles, 1, 1)\n Each block:\n - Loads its v_tile of state into registers\n - Processes all T time steps with state in registers\n - Writes output and optionally updates state\n\n This matches Triton's parallelization strategy for better small-batch performance.\n \"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n\n # Compute thread grouping based on vec_size:\n # vec_size=8: 16 threads per group (half-warp), 8 groups per block\n # vec_size=4: 32 threads per group (full warp), 4 groups per block\n threads_per_group: cutlass.Constexpr[int] = K // vec_size # 16 or 32\n groups_per_warp: cutlass.Constexpr[int] = 32 // threads_per_group # 2 or 1\n num_groups: cutlass.Constexpr[int] = 4 * groups_per_warp # 8 or 4\n\n # Lane position within group and group index\n lane_in_group = lane_id % threads_per_group\n group_in_warp = lane_id // threads_per_group\n group_idx = warp_idx * groups_per_warp + group_in_warp\n\n batch_idx, _, _ = cute.arch.block_idx()\n\n # Decode block index: (i_n, i_hv, i_v) from batch_idx\n i_v = batch_idx % num_v_tiles\n tmp = batch_idx // num_v_tiles\n i_hv = tmp % HV\n i_n = tmp // HV\n i_h = i_hv // (HV // H)\n\n # Get initial state index for this batch\n cache_idx = h0_indices[i_n]\n\n # Load A_log and dt_bias once (they don't vary with time)\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n\n # Allocate shared memory for pre-computed values (broadcast to all warps)\n smem = cutlass.utils.SmemAllocator()\n sQ = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sK = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sG = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n sBeta = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n\n # Register arrays for computation\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # BF16 register tensors for vectorized q, k loading\n r_q_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n r_k_bf16 = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n )\n\n # Only process valid batch entries (cache_idx >= 0)\n if cache_idx >= 0:\n # Compute k_start once (used for shared memory writes)\n k_start = lane_in_group * vec_size\n\n # Pre-compute q, k, g, beta for ALL time steps ONCE (shared across warps)\n for i_t in cutlass.range_constexpr(T):\n # Load q, k into BF16 registers using autovec_copy (coalesced)\n q_tile = cute.local_tile(\n q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_in_group)\n )\n k_tile = cute.local_tile(\n k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_in_group)\n )\n cute.autovec_copy(q_tile, r_q_bf16)\n cute.autovec_copy(k_tile, r_k_bf16)\n\n # Convert BF16 to FP32 for computation\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = cutlass.Float32(r_q_bf16[i])\n r_k[i] = cutlass.Float32(r_k_bf16[i])\n\n # Apply L2 normalization to q, k (with scale fused for q)\n if cutlass.const_expr(use_qk_l2norm):\n sum_q = 0.0\n sum_k = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n\n # Warp-level reduction (32 threads per group with vec_size=4)\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Fuse scale into q's normalization factor\n inv_norm_q_scaled = cute.rsqrt(sum_q + 1e-6, fastmath=True) * scale\n inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * inv_norm_q_scaled\n r_k[i] = r_k[i] * inv_norm_k\n else:\n # No L2 norm, just apply scale to q\n for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n\n # Store to shared memory (only first group writes) - contiguous layout\n if tidx < threads_per_group:\n for i in cutlass.range_constexpr(vec_size):\n sQ[(i_t, k_start + i)] = r_q[i]\n sK[(i_t, k_start + i)] = r_k[i]\n\n # Compute g, beta - all lanes compute (redundant but no divergence)\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n\n # Branchless softplus\n exp_beta_x = cute.exp(beta_x, fastmath=True)\n softplus_val = (cutlass.Float32(1.0) / softplus_beta) * cute.log(\n cutlass.Float32(1.0) + exp_beta_x, fastmath=True\n )\n use_softplus = (\n cutlass.Float32(1.0)\n if beta_x <= softplus_threshold\n else cutlass.Float32(0.0)\n )\n softplus_x = (\n use_softplus * softplus_val + (cutlass.Float32(1.0) - use_softplus) * x\n )\n\n r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n r_beta = cutlass.Float32(1.0) / (\n cutlass.Float32(1.0) + cute.exp(-r_b, fastmath=True)\n )\n r_g = cute.exp(r_g_value, fastmath=True)\n\n # Only thread 0 stores to shared memory\n if tidx == 0:\n sG[i_t] = r_g\n sBeta[i_t] = r_beta\n\n cute.arch.barrier()\n\n # Each group handles tile_v/num_groups V rows\n rows_per_group: cutlass.Constexpr[int] = tile_v // num_groups\n for row_in_group in cutlass.range_constexpr(rows_per_group):\n v_idx = i_v * tile_v + group_idx * rows_per_group + row_in_group\n\n if v_idx < V:\n # Load h[v_idx, :] into registers using 3D local_tile + autovec_copy\n flat_state_idx = cache_idx * HV + i_hv\n h_tile = cute.local_tile(\n h0_source, (1, 1, vec_size), (flat_state_idx, v_idx, lane_in_group)\n )\n cute.autovec_copy(h_tile, r_h)\n\n # Process all T time steps with h in registers\n for i_t in cutlass.range_constexpr(T):\n # Load pre-computed q, k from shared memory using 2D local_tile\n sQ_tile = cute.local_tile(sQ, (1, vec_size), (i_t, lane_in_group))\n sK_tile = cute.local_tile(sK, (1, vec_size), (i_t, lane_in_group))\n cute.autovec_copy(sQ_tile, r_q)\n cute.autovec_copy(sK_tile, r_k)\n\n r_g = sG[i_t]\n r_beta = sBeta[i_t]\n\n # Step 1: Apply decay to h\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n\n # Step 2: Compute sum_hk = h @ k (group reduction)\n sum_hk = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_hk += r_h[i] * r_k[i]\n\n # Warp-level reduction\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Step 3: Load v for this v_idx and time step, apply delta rule\n r_v = cutlass.Float32(v[i_n, i_t, i_hv, v_idx])\n v_new = (r_v - sum_hk) * r_beta\n\n # Step 4: Update h: h += k * v_new\n for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n\n # Cache intermediate state if needed using 3D local_tile + autovec_copy\n if cutlass.const_expr(cache_intermediate_states):\n flat_idx = i_n * T * HV + i_t * HV + i_hv\n inter_tile = cute.local_tile(\n intermediate_states,\n (1, 1, vec_size),\n (flat_idx, v_idx, lane_in_group),\n )\n cute.autovec_copy(r_h, inter_tile)\n\n # Step 5: Compute output: sum_hq = h @ q (group reduction)\n sum_hq = 0.0\n for i in cutlass.range_constexpr(vec_size):\n sum_hq += r_h[i] * r_q[i]\n\n # Warp-level reduction\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Write output (only lane 0 of each group)\n if lane_in_group == 0:\n o[(i_n, i_t, i_hv, v_idx)] = cutlass.BFloat16(sum_hq)\n\n # Write final state back (if not disabled) using 3D local_tile + autovec_copy\n if cutlass.const_expr(not disable_state_update):\n h_tile_out = cute.local_tile(\n h0_source,\n (1, 1, vec_size),\n (flat_state_idx, v_idx, lane_in_group),\n )\n cute.autovec_copy(r_h, h_tile_out)\n\n\n@cute.jit\ndef run_gdn_verify_kernel_mtp(\n h0_source: cute.Tensor,\n intermediate_states: cute.Tensor,\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n tile_v: cutlass.Constexpr[int], # TILE_V - configurable for batch size\n vec_size: cutlass.Constexpr[int], # 4 for full warp, 8 for half-warp\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n disable_state_update: cutlass.Constexpr[bool],\n cache_intermediate_states: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n _, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n num_v_tiles = cute.ceil_div(v_dim, tile_v)\n\n # Grid: (B * HV * num_v_tiles, 1, 1) - parallelize across V dimension\n grid_size = B * HV * num_v_tiles\n\n # Shared memory for pre-computed q, k, g, beta\n smem_bytes = (\n 4 * T * (k_dim + 8) # sQ\n + 4 * T * (k_dim + 8) # sK\n + 4 * T # sG\n + 4 * T # sBeta\n + 128 # alignment\n )\n\n gdn_verify_kernel_mtp(\n h0_source,\n intermediate_states,\n vec_size,\n num_v_tiles,\n tile_v,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n disable_state_update,\n cache_intermediate_states,\n ).launch(\n grid=(grid_size, 1, 1),\n block=[NUM_THREADS_MTP, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@functools.cache\ndef _get_compiled_mtp_kernel(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n pool_size: int,\n cache_steps: int,\n disable_state_update: bool,\n cache_intermediate_states: bool,\n scale: float,\n use_qk_l2norm: bool,\n tile_v: int, # TILE_V - configurable for batch size\n vec_size: int, # 4 for full warp, 8 for half-warp\n):\n \"\"\"Cache compiled MTP kernel for given configuration.\"\"\"\n return {}\n\n\n@flashinfer_api\ndef gated_delta_rule_mtp(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n initial_state: torch.Tensor,\n initial_state_indices: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n intermediate_states_buffer: Optional[torch.Tensor] = None,\n disable_state_update: bool = True,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n \"\"\"\n Gated Delta Rule MTP Kernel (Multiple Token Processing).\n\n This function processes multiple tokens (T > 1) in sequence, typically used for\n speculative decoding verification. It supports intermediate state caching for\n potential rollback scenarios.\n\n Args:\n q (torch.Tensor):\n Query tensor of shape ``[B, T, H, K]``.\n k (torch.Tensor):\n Key tensor of shape ``[B, T, H, K]``.\n v (torch.Tensor):\n Value tensor of shape ``[B, T, HV, V]``.\n initial_state (torch.Tensor):\n Initial state tensor of shape ``[pool_size, HV, V, K]`` (K-last layout).\n initial_state_indices (torch.Tensor):\n Indices mapping each batch to its initial state, shape ``[B]``.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, T, HV]``.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``.\n b (torch.Tensor):\n Update gate input of shape ``[B, T, HV]``.\n scale (Optional[float]):\n Scaling factor for queries. If None, uses ``1/sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, T, HV, V]``.\n intermediate_states_buffer (Optional[torch.Tensor]):\n Buffer for caching intermediate states, shape ``[pool_size, T, HV, V, K]``.\n If None, intermediate states are not cached.\n disable_state_update (bool):\n If True, the initial state is not updated. Default: ``True``.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, T, HV, V]``\n - initial_state: Updated state tensor (unchanged if disable_state_update=True)\n\n Note:\n - Requires SM90 (Hopper) architecture\n - Supports T > 1 (multiple token processing)\n - State layout is K-last: [pool_size, HV, V, K]\n - Optimized for speculative decoding verification scenarios\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n _, _, HV, V = v.shape\n pool_size = initial_state.shape[0]\n\n # Dynamic TILE_V and vec_size selection based on batch size and sequence length\n tile_v = get_tile_v_mtp(B, T)\n vec_size = get_vec_size_mtp(B, T)\n\n # Validate state shape\n assert initial_state.shape == (pool_size, HV, V, K), (\n f\"Expected initial_state shape [pool_size={pool_size}, HV={HV}, V={V}, K={K}], got {initial_state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n assert V % tile_v == 0, (\n f\"V must be divisible by {tile_v} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert initial_state.dtype == torch.float32, (\n f\"initial_state must be float32, got {initial_state.dtype}\"\n )\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # Reshape initial_state from [pool_size, HV, V, K] to [pool_size * HV, V, K]\n h0_source = initial_state.to(torch.float32).reshape(pool_size * HV, V, K)\n\n # Handle intermediate states\n cache_intermediate_states = intermediate_states_buffer is not None\n if cache_intermediate_states:\n buffer_size = intermediate_states_buffer.shape[0]\n cache_steps = intermediate_states_buffer.shape[1]\n\n # Validate buffer length matches query sequence length\n assert cache_steps >= T, (\n f\"intermediate_states_buffer second dimension (cache_steps={cache_steps}) must be at least T={T} to prevent out-of-bounds indexing\"\n )\n\n intermediate_states = (\n intermediate_states_buffer.to(torch.float32)\n .reshape(buffer_size * cache_steps * HV, V, K)\n .contiguous()\n )\n else:\n cache_steps = T\n intermediate_states = torch.zeros(1, 1, 1, dtype=torch.float32, device=q.device)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (\n B,\n T,\n H,\n HV,\n K,\n V,\n pool_size,\n cache_steps,\n disable_state_update,\n cache_intermediate_states,\n scale,\n use_qk_l2norm,\n tile_v,\n vec_size,\n )\n cache = _get_compiled_mtp_kernel(*cache_key)\n\n # Get or create cu_seqlens (cached per config)\n if \"cu_seqlens\" not in cache or cache[\"cu_seqlens\"].device != q.device:\n cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n cu_seqlens = cache[\"cu_seqlens\"]\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n intermediate_states_tensor = from_dlpack(intermediate_states, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(initial_state_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_gdn_verify_kernel_mtp,\n h0_source_tensor,\n intermediate_states_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n B=B,\n T=T,\n H=H,\n K=K,\n V=V,\n tile_v=tile_v,\n vec_size=vec_size,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n disable_state_update=disable_state_update,\n cache_intermediate_states=cache_intermediate_states,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n compiled(\n h0_source,\n intermediate_states,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n output,\n initial_state_indices,\n cu_seqlens,\n stream,\n )\n\n # Copy state back if needed (no sync needed - PyTorch handles stream ordering)\n # Only copy if state update is enabled AND initial_state was not contiguous\n # (if contiguous, reshape returns a view and kernel updated state in-place)\n if not disable_state_update and not initial_state.is_contiguous():\n initial_state.copy_(h0_source.reshape(pool_size, HV, V, K))\n\n # Convert output to target dtype if needed\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, initial_state\n"},"diff":{"kind":"string","value":"--- flashinfer/gdn_decode.py\n+++ flashinfer/gdn_decode.py\n@@ -90,10 +90,43 @@\n # ============================================================================\n # Global configuration for MTP (Multiple Token Processing) version\n # ============================================================================\n-TILE_V_MTP = 8\n-TILE_K_MTP = 128\n-NUM_STAGES_MTP = 2\n-NUM_THREADS_MTP = 128 # 4 warps\n+# Dynamic kernel selection based on batch size:\n+# - Small batch (B <= threshold): Use smaller TILE_V for more parallelism\n+# Optimal TILE_V depends on batch size (empirically determined):\n+# B=1-2: TILE_V=4 (more blocks, better parallelism for tiny batches)\n+# B=4: TILE_V=8 (intermediate parallelism)\n+# B=8: TILE_V=16 (balance between parallelism and efficiency)\n+# B>=16: TILE_V=32 (fewer blocks, better efficiency for large batches)\n+\n+TILE_K_MTP = 128 # Full K dimension (shared across all configs)\n+NUM_THREADS_MTP = 128 # 4 warps (shared across all configs)\n+\n+\n+def get_vec_size_mtp(batch_size: int, seq_len: int = 1) -> int:\n+ \"\"\"Select vec_size for MTP kernel.\n+\n+ Always use vec_size=4 (32 threads per group = full warp, 4 groups per block).\n+ Full warp shuffle is more efficient and achieves >= 1.0x speedup vs Triton.\n+ \"\"\"\n+ return 4\n+\n+\n+def get_tile_v_mtp(batch_size: int, seq_len: int = 1) -> int:\n+ \"\"\"Select optimal TILE_V for MTP kernel based on batch size and sequence length.\n+\n+ With vec_size=4, num_groups=4, rows_per_group = tile_v / 4.\n+ Tuned via grid search for optimal performance.\n+ \"\"\"\n+ if batch_size <= 2:\n+ return 4 # Small batch needs max parallelism\n+ elif batch_size <= 4:\n+ return 8\n+ elif batch_size <= 8:\n+ return 16\n+ elif batch_size <= 16:\n+ return 32\n+ else:\n+ return 64\n \n \n @cute.kernel\n@@ -169,6 +202,19 @@\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n+ # BF16 register tensors for vectorized q, k, v loading\n+ r_q_bf16 = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n+ )\n+ r_k_bf16 = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n+ )\n+ r_v_bf16 = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n+ )\n+\n+ # Compute k_start for contiguous access pattern\n+ k_start = lane_id * vec_size\n \n cute.arch.barrier()\n \n@@ -201,12 +247,22 @@\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n \n- for i in range(vec_size):\n- r_q[i] = cutlass.Float32(q[i_n, i_t, i_h, i * 32 + lane_id])\n- r_k[i] = cutlass.Float32(k[i_n, i_t, i_h, i * 32 + lane_id])\n- # Store v to shared memory instead of register\n- v_val = cutlass.Float32(v[i_n, i_t, i_hv, i * 32 + lane_id])\n- sV[i * 32 + lane_id] = v_val\n+ # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n+ q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n+ k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n+ cute.autovec_copy(q_tile, r_q_bf16)\n+ cute.autovec_copy(k_tile, r_k_bf16)\n+\n+ # Convert BF16 to FP32\n+ for i in cutlass.range_constexpr(vec_size):\n+ r_q[i] = cutlass.Float32(r_q_bf16[i])\n+ r_k[i] = cutlass.Float32(r_k_bf16[i])\n+\n+ # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n+ v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n+ cute.autovec_copy(v_tile, r_v_bf16)\n+ for i in cutlass.range_constexpr(vec_size):\n+ sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n \n cute.arch.barrier() # Ensure all threads finish writing to sV\n \n@@ -223,9 +279,9 @@\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n- exp_beta_x = cute.exp(beta_x)\n+ exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n- log_result = cutlass.Float32(cute.log(log_input))\n+ log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n@@ -233,13 +289,13 @@\n softplus_x = x\n \n # Compute g = exp(A_log) * softplus_x\n- r_g_value = -cute.exp(r_A_log) * softplus_x\n+ r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n \n # Compute beta = 1 / (1 + exp(-b))\n- r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n+ r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n \n # Store to scalar (Float32)\n- r_g = cute.exp(r_g_value)\n+ r_g = cute.exp(r_g_value, fastmath=True)\n \n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n@@ -248,7 +304,7 @@\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n- for i in range(vec_size):\n+ for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n@@ -260,14 +316,14 @@\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n \n- norm_q = cute.sqrt(sum_q + 1e-6)\n- norm_k = cute.sqrt(sum_k + 1e-6)\n- for i in range(vec_size):\n- r_q[i] = r_q[i] / norm_q\n- r_k[i] = r_k[i] / norm_k\n+ inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n+ inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n+ for i in cutlass.range_constexpr(vec_size):\n+ r_q[i] = r_q[i] * inv_norm_q\n+ r_k[i] = r_k[i] * inv_norm_k\n \n # Apply scaling in Float32\n- for i in range(vec_size):\n+ for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n \n # ===================================================================\n@@ -295,12 +351,18 @@\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n \n- # Step 3: Compute using data from current stage\n- for row in range(0, TILE_V, 4):\n+ # Step 3: Compute using data from current stage (contiguous access pattern)\n+ for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n- for i in range(vec_size):\n- r_h[i] = sData[(row + row_offset, i * 32 + lane_id, stage)]\n+\n+ # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n+ sData_tile = cute.local_tile(\n+ sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n+ )\n+ cute.autovec_copy(sData_tile, r_h)\n+\n+ for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n \n@@ -313,10 +375,15 @@\n v_new = v_new * r_beta\n \n sum_hq = 0.0\n- for i in range(vec_size):\n+ for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n- gDst[(0, row + row_offset, i * 32 + lane_id, v_tiles)] = r_h[i]\n sum_hq += r_h[i] * r_q[i]\n+\n+ # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n+ gDst_tile = cute.local_tile(\n+ gDst, (1, 1, vec_size, 1), (0, row + row_offset, lane_id, v_tiles)\n+ )\n+ cute.autovec_copy(r_h, gDst_tile)\n \n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n@@ -406,6 +473,19 @@\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n+ # BF16 register tensors for vectorized q, k, v loading\n+ r_q_bf16 = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n+ )\n+ r_k_bf16 = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n+ )\n+ r_v_bf16 = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n+ )\n+\n+ # Compute k_start for contiguous access pattern\n+ k_start = lane_id * vec_size\n \n cute.arch.barrier()\n \n@@ -437,12 +517,22 @@\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n \n- for i in range(vec_size):\n- r_q[i] = cutlass.Float32(q[i_n, i_t, i_h, i * 32 + lane_id])\n- r_k[i] = cutlass.Float32(k[i_n, i_t, i_h, i * 32 + lane_id])\n- # Store v to shared memory instead of register\n- v_val = cutlass.Float32(v[i_n, i_t, i_hv, i * 32 + lane_id])\n- sV[i * 32 + lane_id] = v_val\n+ # Load q, k into BF16 registers using autovec_copy (contiguous pattern)\n+ q_tile = cute.local_tile(q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n+ k_tile = cute.local_tile(k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_id))\n+ cute.autovec_copy(q_tile, r_q_bf16)\n+ cute.autovec_copy(k_tile, r_k_bf16)\n+\n+ # Convert BF16 to FP32\n+ for i in cutlass.range_constexpr(vec_size):\n+ r_q[i] = cutlass.Float32(r_q_bf16[i])\n+ r_k[i] = cutlass.Float32(r_k_bf16[i])\n+\n+ # Load v into BF16 registers using autovec_copy, convert to FP32, store to sV\n+ v_tile = cute.local_tile(v, (1, 1, 1, vec_size), (i_n, i_t, i_hv, lane_id))\n+ cute.autovec_copy(v_tile, r_v_bf16)\n+ for i in cutlass.range_constexpr(vec_size):\n+ sV[k_start + i] = cutlass.Float32(r_v_bf16[i])\n \n cute.arch.barrier() # Ensure all threads finish writing to sV\n \n@@ -459,9 +549,9 @@\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n- exp_beta_x = cute.exp(beta_x)\n+ exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n- log_result = cutlass.Float32(cute.log(log_input))\n+ log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n@@ -469,13 +559,13 @@\n softplus_x = x\n \n # Compute g = exp(A_log) * softplus_x\n- r_g_value = -cute.exp(r_A_log) * softplus_x\n+ r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n \n # Compute beta = 1 / (1 + exp(-b))\n- r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n+ r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n \n # Store to scalar (Float32)\n- r_g = cute.exp(r_g_value)\n+ r_g = cute.exp(r_g_value, fastmath=True)\n \n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n@@ -484,7 +574,7 @@\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n- for i in range(vec_size):\n+ for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n@@ -496,14 +586,14 @@\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n \n- norm_q = cute.sqrt(sum_q + 1e-6)\n- norm_k = cute.sqrt(sum_k + 1e-6)\n- for i in range(vec_size):\n- r_q[i] = r_q[i] / norm_q\n- r_k[i] = r_k[i] / norm_k\n+ inv_norm_q = cute.rsqrt(sum_q + 1e-6, fastmath=True)\n+ inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n+ for i in cutlass.range_constexpr(vec_size):\n+ r_q[i] = r_q[i] * inv_norm_q\n+ r_k[i] = r_k[i] * inv_norm_k\n \n # Apply scaling in Float32\n- for i in range(vec_size):\n+ for i in cutlass.range_constexpr(vec_size):\n r_q[i] = r_q[i] * scale\n \n # ===================================================================\n@@ -530,12 +620,18 @@\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n \n- # Step 3: Compute using data from current stage\n- for row in range(0, TILE_V, 4):\n+ # Step 3: Compute using data from current stage (contiguous access pattern)\n+ for row in cutlass.range_constexpr(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n- for i in range(vec_size):\n- r_h[i] = sData[(row + row_offset, i * 32 + lane_id, stage)]\n+\n+ # Load h from sData using 3D local_tile + autovec_copy (contiguous in K)\n+ sData_tile = cute.local_tile(\n+ sData, (1, vec_size, 1), (row + row_offset, lane_id, stage)\n+ )\n+ cute.autovec_copy(sData_tile, r_h)\n+\n+ for i in cutlass.range_constexpr(vec_size):\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n \n@@ -548,10 +644,15 @@\n v_new = v_new * r_beta\n \n sum_hq = 0.0\n- for i in range(vec_size):\n+ for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n- gDst[(0, row + row_offset, i * 32 + lane_id, v_tiles)] = r_h[i]\n sum_hq += r_h[i] * r_q[i]\n+\n+ # Write h to gDst using 4D local_tile + autovec_copy (contiguous in K)\n+ gDst_tile = cute.local_tile(\n+ gDst, (1, 1, vec_size, 1), (0, row + row_offset, lane_id, v_tiles)\n+ )\n+ cute.autovec_copy(r_h, gDst_tile)\n \n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n@@ -599,6 +700,7 @@\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n ):\n+ \"\"\"Launch original pipelined kernel for small batch pretranspose.\"\"\"\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n@@ -628,12 +730,6 @@\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n-\n- # print(f\"Batched CP.ASYNC Load + Store (bypass L1 cache)\")\n- # print(f\" {batch_size} batches x {v_dim}x{k_dim} matrices\")\n- # print(f\" Tile: {TILE_V}x{TILE_K}, {num_v_tiles} tiles/batch\")\n- # print(f\" Threads: {NUM_THREADS} ({NUM_THREADS // 32} warps), vec_size: {vec_size}\")\n- # print(f\" Total: {total_data_mb:.1f} MB\\n\")\n \n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n@@ -925,22 +1021,19 @@\n # Convert state from [B, HV, V, K] to [B*HV, V, K] for kernel\n h0_source = state.reshape(B * HV, V, K)\n \n- # Create dummy tensors for unused parameters\n- h0_indices = torch.zeros(B, dtype=torch.int32, device=q.device)\n- cu_seqlens = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n-\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel(*cache_key)\n \n+ # Get or create h0_indices and cu_seqlens (cached per config)\n+ if \"h0_indices\" not in cache or cache[\"h0_indices\"].device != q.device:\n+ cache[\"h0_indices\"] = torch.zeros(B, dtype=torch.int32, device=q.device)\n+ cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n+ h0_indices = cache[\"h0_indices\"]\n+ cu_seqlens = cache[\"cu_seqlens\"]\n+\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n-\n- # Choose kernel based on batch size\n- if B <= 32:\n- run_func = run_gdn_decode_kernel_small_batch_pretranspose\n- else:\n- run_func = run_gdn_decode_kernel_big_batch_pretranspose\n \n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n@@ -954,6 +1047,12 @@\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n+\n+ # Choose kernel based on batch size\n+ if B <= 32:\n+ run_func = run_gdn_decode_kernel_small_batch_pretranspose\n+ else:\n+ run_func = run_gdn_decode_kernel_big_batch_pretranspose\n \n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n@@ -994,8 +1093,10 @@\n h0_source, A_log, a, dt_bias, q, k, v, b, output, h0_indices, cu_seqlens, stream\n )\n \n- # Reshape state back (no sync needed - PyTorch handles stream ordering)\n- state.copy_(h0_source.reshape(B, HV, V, K))\n+ # Copy state back only if state was not contiguous\n+ # (if contiguous, reshape returns a view and kernel updated state in-place)\n+ if not state.is_contiguous():\n+ state.copy_(h0_source.reshape(B, HV, V, K))\n \n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n@@ -1073,7 +1174,9 @@\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n \n- gSrc_batch = h0_source[(pool_idx, i_hv, None, None)]\n+ # Compute flat index for flattened state [B*HV, K, V]\n+ flat_idx = pool_idx * HV + i_hv\n+ gSrc_batch = h0_source[(flat_idx, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_SMALL_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n \n@@ -1100,17 +1203,17 @@\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n- exp_beta_x = cute.exp(beta_x)\n+ exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n- log_result = cutlass.Float32(cute.log(log_input))\n+ log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n- r_g_value = -cute.exp(r_A_log) * softplus_x\n- r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n- r_g = cute.exp(r_g_value)\n+ r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n+ r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n+ r_g = cute.exp(r_g_value, fastmath=True)\n \n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n@@ -1155,8 +1258,8 @@\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n- smem_o[0] = cute.rsqrt(local_sum_q + 1e-6)\n- smem_o[1] = cute.rsqrt(local_sum_k + 1e-6)\n+ smem_o[0] = cute.rsqrt(local_sum_q + 1e-6, fastmath=True)\n+ smem_o[1] = cute.rsqrt(local_sum_k + 1e-6, fastmath=True)\n cute.arch.barrier()\n \n inv_norm_q = smem_o[0]\n@@ -1236,14 +1339,15 @@\n \n cute.arch.barrier()\n \n- for k_iter in range(NUM_K_ITERS_SMALL):\n- flat_idx = tidx + k_iter * 128\n- k_write = flat_idx // TILE_V_SMALL_NT\n- v_write = flat_idx % TILE_V_SMALL_NT\n+ for k_iter in cutlass.range_constexpr(NUM_K_ITERS_SMALL):\n+ flat_tid = tidx + k_iter * 128\n+ k_write = flat_tid // TILE_V_SMALL_NT\n+ v_write = flat_tid % TILE_V_SMALL_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_SMALL_NT + v_write\n- h0_source[(pool_idx, i_hv, k_write, v_global_write)] = h_val\n+ # Use flat index for flattened state [B*HV, K, V]\n+ h0_source[(flat_idx, k_write, v_global_write)] = h_val\n \n cute.arch.barrier()\n \n@@ -1301,7 +1405,9 @@\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n \n- gSrc_batch = h0_source[(pool_idx, i_hv, None, None)]\n+ # Compute flat index for flattened state [B*HV, K, V]\n+ flat_idx = pool_idx * HV + i_hv\n+ gSrc_batch = h0_source[(flat_idx, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n \n@@ -1327,17 +1433,17 @@\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n- exp_beta_x = cute.exp(beta_x)\n+ exp_beta_x = cute.exp(beta_x, fastmath=True)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n- log_result = cutlass.Float32(cute.log(log_input))\n+ log_result = cutlass.Float32(cute.log(log_input, fastmath=True))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n- r_g_value = -cute.exp(r_A_log) * softplus_x\n- r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n- r_g = cute.exp(r_g_value)\n+ r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n+ r_beta = 1.0 / (1.0 + cute.exp(-r_b, fastmath=True))\n+ r_g = cute.exp(r_g_value, fastmath=True)\n \n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n@@ -1382,8 +1488,8 @@\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n- smem_o[0] = cute.rsqrt(local_sum_q + 1e-6)\n- smem_o[1] = cute.rsqrt(local_sum_k + 1e-6)\n+ smem_o[0] = cute.rsqrt(local_sum_q + 1e-6, fastmath=True)\n+ smem_o[1] = cute.rsqrt(local_sum_k + 1e-6, fastmath=True)\n cute.arch.barrier()\n \n inv_norm_q = smem_o[0]\n@@ -1455,14 +1561,15 @@\n \n cute.arch.barrier()\n \n- for k_iter in range(NUM_K_ITERS_NT):\n- flat_idx = tidx + k_iter * 256\n- k_write = flat_idx // TILE_V_NT\n- v_write = flat_idx % TILE_V_NT\n+ for k_iter in cutlass.range_constexpr(NUM_K_ITERS_NT):\n+ flat_tid = tidx + k_iter * 256\n+ k_write = flat_tid // TILE_V_NT\n+ v_write = flat_tid % TILE_V_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_NT + v_write\n- h0_source[(pool_idx, i_hv, k_write, v_global_write)] = h_val\n+ # Use flat index for flattened state [B*HV, K, V]\n+ h0_source[(flat_idx, k_write, v_global_write)] = h_val\n \n cute.arch.barrier()\n \n@@ -1493,9 +1600,10 @@\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n ):\n- pool_size, hv_dim, k_dim, v_dim = h0_source.layout.shape\n- n_indices = h0_indices.layout.shape[0]\n- batch_size = n_indices * hv_dim\n+ # h0_source is flattened to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n+ batch_hv_dim, k_dim, v_dim = h0_source.layout.shape\n+ h0_indices.layout.shape[0]\n+ batch_size = batch_hv_dim # batch_hv_dim = B * HV\n \n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n@@ -1573,9 +1681,10 @@\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n ):\n- pool_size, hv_dim, k_dim, v_dim = h0_source.layout.shape\n- n_indices = h0_indices.layout.shape[0]\n- batch_size = n_indices * hv_dim\n+ # h0_source is flattened to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n+ batch_hv_dim, k_dim, v_dim = h0_source.layout.shape\n+ h0_indices.layout.shape[0]\n+ batch_size = batch_hv_dim # batch_hv_dim = B * HV\n \n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n@@ -1727,17 +1836,22 @@\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n \n- # State is already in K-major layout [B, HV, K, V]\n- # Use state directly as pooled view: pool_size=B, each batch is its own pool\n- h0_source = state.contiguous()\n-\n- # Create h0_indices: each batch points to its own pool index\n- h0_indices = torch.arange(B, dtype=torch.int32, device=q.device)\n- cu_seqlens = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n+ # State is in K-major layout [B, HV, K, V]\n+ # Flatten to [B*HV, K, V] to ensure proper alignment for SIMT async copy\n+ # This avoids alignment issues when B=1 (zero strides cause alignment failures)\n+ state_contiguous = state.contiguous()\n+ h0_source = state_contiguous.view(B * HV, K, V)\n \n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel_nontranspose(*cache_key)\n+\n+ # Get or create h0_indices and cu_seqlens (cached per config)\n+ if \"h0_indices\" not in cache or cache[\"h0_indices\"].device != q.device:\n+ cache[\"h0_indices\"] = torch.arange(B, dtype=torch.int32, device=q.device)\n+ cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n+ h0_indices = cache[\"h0_indices\"]\n+ cu_seqlens = cache[\"cu_seqlens\"]\n \n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n@@ -1812,9 +1926,10 @@\n stream,\n )\n \n- # Copy state back (no sync needed - PyTorch handles stream ordering)\n- # h0_source is already [B, HV, K, V]\n- state.copy_(h0_source)\n+ # Copy state back only if state was not contiguous\n+ # (if contiguous, state_contiguous is state itself, so kernel updated state in-place)\n+ if state_contiguous.data_ptr() != state.data_ptr():\n+ state.copy_(state_contiguous)\n \n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n@@ -1830,12 +1945,11 @@\n \n @cute.kernel\n def gdn_verify_kernel_mtp(\n- tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor, # [pool_size * HV, V, K] - initial state pool (K-last)\n intermediate_states: cute.Tensor, # [pool_size * T * HV, V, K] - intermediate state cache\n- smem_layout_staged: cute.ComposedLayout, # Swizzled layout to avoid bank conflicts\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n+ tile_v: cutlass.Constexpr[int], # TILE_V - configurable for batch size\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n@@ -1862,44 +1976,61 @@\n cache_intermediate_states: cutlass.Constexpr[bool],\n ):\n \"\"\"\n- Verify kernel with optimized loop order: (v_tiles outer, time_steps inner)\n-\n- Uses cute.make_rmem_tensor for register arrays (same style as decode kernel).\n- Store-compute overlap: cache data in registers, store during next iteration.\n+ Parallel MTP kernel - each block handles one [TILE_V, TILE_K] tile.\n+\n+ Grid: (B * HV * num_v_tiles, 1, 1)\n+ Each block:\n+ - Loads its v_tile of state into registers\n+ - Processes all T time steps with state in registers\n+ - Writes output and optionally updates state\n+\n+ This matches Triton's parallelization strategy for better small-batch performance.\n \"\"\"\n-\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n+\n+ # Compute thread grouping based on vec_size:\n+ # vec_size=8: 16 threads per group (half-warp), 8 groups per block\n+ # vec_size=4: 32 threads per group (full warp), 4 groups per block\n+ threads_per_group: cutlass.Constexpr[int] = K // vec_size # 16 or 32\n+ groups_per_warp: cutlass.Constexpr[int] = 32 // threads_per_group # 2 or 1\n+ num_groups: cutlass.Constexpr[int] = 4 * groups_per_warp # 8 or 4\n+\n+ # Lane position within group and group index\n+ lane_in_group = lane_id % threads_per_group\n+ group_in_warp = lane_id // threads_per_group\n+ group_idx = warp_idx * groups_per_warp + group_in_warp\n+\n batch_idx, _, _ = cute.arch.block_idx()\n- i_n = batch_idx // HV\n- i_hv = batch_idx % HV\n+\n+ # Decode block index: (i_n, i_hv, i_v) from batch_idx\n+ i_v = batch_idx % num_v_tiles\n+ tmp = batch_idx // num_v_tiles\n+ i_hv = tmp % HV\n+ i_n = tmp // HV\n i_h = i_hv // (HV // H)\n+\n+ # Get initial state index for this batch\n+ cache_idx = h0_indices[i_n]\n \n # Load A_log and dt_bias once (they don't vary with time)\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n \n+ # Allocate shared memory for pre-computed values (broadcast to all warps)\n smem = cutlass.utils.SmemAllocator()\n-\n- # Allocate shared memory with padding to avoid bank conflicts\n- sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n- sOutput = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T, V)), 16)\n- # Pre-computed shared memory for all time steps (with padding for bank conflict avoidance)\n sQ = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sK = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n- sV = smem.allocate_tensor(\n- cutlass.Float32, cute.make_layout((T, V), stride=(V + 8, 1)), 16\n- )\n sG = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n sBeta = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n \n- # Allocate register tensors\n+ # Register arrays for computation\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n@@ -1909,64 +2040,45 @@\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n-\n- # Initialize output accumulator to zero\n- for i_t in range(T):\n- sOutput[(i_t, tidx)] = 0.0\n-\n- cute.arch.barrier()\n-\n- # Get initial state index for this batch\n- cache_idx = h0_indices[i_n]\n-\n- # Early exit optimization: skip pre-computation for padding slots\n+ # BF16 register tensors for vectorized q, k loading\n+ r_q_bf16 = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n+ )\n+ r_k_bf16 = cute.make_rmem_tensor(\n+ cute.make_layout((vec_size,), stride=(1,)), cutlass.BFloat16\n+ )\n+\n+ # Only process valid batch entries (cache_idx >= 0)\n if cache_idx >= 0:\n- # Pre-compute q, k, v, g, beta for all time steps (outside v_tiles loop)\n- for i_t in range(T):\n- # Load q, k into register arrays\n- for i in range(vec_size):\n- r_q[i] = cutlass.Float32(q[i_n, i_t, i_h, i * 32 + lane_id])\n- r_k[i] = cutlass.Float32(k[i_n, i_t, i_h, i * 32 + lane_id])\n- # Load v for all V elements\n- sV[(i_t, i * 32 + lane_id)] = cutlass.Float32(\n- v[i_n, i_t, i_hv, i * 32 + lane_id]\n- )\n-\n- # Compute g and beta\n- r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n- r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n- r_g = 0.0\n- r_beta = 0.0\n- if lane_id == 0:\n- x = r_a + r_dt_bias\n- beta_x = softplus_beta * x\n- softplus_x = 0.0\n-\n- if beta_x <= softplus_threshold:\n- exp_beta_x = cute.exp(beta_x)\n- log_input = cutlass.Float32(1.0 + exp_beta_x)\n- log_result = cutlass.Float32(cute.log(log_input))\n- softplus_x = cutlass.Float32(\n- (cutlass.Float32(1.0) / softplus_beta) * log_result\n- )\n- else:\n- softplus_x = x\n-\n- r_g_value = -cute.exp(r_A_log) * softplus_x\n- r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n- r_g = cute.exp(r_g_value)\n-\n- r_g = cute.arch.shuffle_sync(r_g, 0)\n- r_beta = cute.arch.shuffle_sync(r_beta, 0)\n-\n- # Apply L2 normalization\n- if use_qk_l2norm:\n+ # Compute k_start once (used for shared memory writes)\n+ k_start = lane_in_group * vec_size\n+\n+ # Pre-compute q, k, g, beta for ALL time steps ONCE (shared across warps)\n+ for i_t in cutlass.range_constexpr(T):\n+ # Load q, k into BF16 registers using autovec_copy (coalesced)\n+ q_tile = cute.local_tile(\n+ q, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_in_group)\n+ )\n+ k_tile = cute.local_tile(\n+ k, (1, 1, 1, vec_size), (i_n, i_t, i_h, lane_in_group)\n+ )\n+ cute.autovec_copy(q_tile, r_q_bf16)\n+ cute.autovec_copy(k_tile, r_k_bf16)\n+\n+ # Convert BF16 to FP32 for computation\n+ for i in cutlass.range_constexpr(vec_size):\n+ r_q[i] = cutlass.Float32(r_q_bf16[i])\n+ r_k[i] = cutlass.Float32(r_k_bf16[i])\n+\n+ # Apply L2 normalization to q, k (with scale fused for q)\n+ if cutlass.const_expr(use_qk_l2norm):\n sum_q = 0.0\n sum_k = 0.0\n- for i in range(vec_size):\n+ for i in cutlass.range_constexpr(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n \n+ # Warp-level reduction (32 threads per group with vec_size=4)\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n@@ -1975,150 +2087,138 @@\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n \n- inv_norm_q = cute.rsqrt(sum_q + 1e-6)\n- inv_norm_k = cute.rsqrt(sum_k + 1e-6)\n-\n- for i in range(vec_size):\n- r_q[i] = r_q[i] * inv_norm_q\n+ # Fuse scale into q's normalization factor\n+ inv_norm_q_scaled = cute.rsqrt(sum_q + 1e-6, fastmath=True) * scale\n+ inv_norm_k = cute.rsqrt(sum_k + 1e-6, fastmath=True)\n+\n+ for i in cutlass.range_constexpr(vec_size):\n+ r_q[i] = r_q[i] * inv_norm_q_scaled\n r_k[i] = r_k[i] * inv_norm_k\n-\n- # Apply scaling to q\n- for i in range(vec_size):\n- r_q[i] = r_q[i] * scale\n-\n- # Store pre-computed values to shared memory\n- for i in range(vec_size):\n- sQ[(i_t, i * 32 + lane_id)] = r_q[i]\n- sK[(i_t, i * 32 + lane_id)] = r_k[i]\n-\n- # Store g and beta (only one thread needs to do this)\n+ else:\n+ # No L2 norm, just apply scale to q\n+ for i in cutlass.range_constexpr(vec_size):\n+ r_q[i] = r_q[i] * scale\n+\n+ # Store to shared memory (only first group writes) - contiguous layout\n+ if tidx < threads_per_group:\n+ for i in cutlass.range_constexpr(vec_size):\n+ sQ[(i_t, k_start + i)] = r_q[i]\n+ sK[(i_t, k_start + i)] = r_k[i]\n+\n+ # Compute g, beta - all lanes compute (redundant but no divergence)\n+ r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n+ r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n+\n+ x = r_a + r_dt_bias\n+ beta_x = softplus_beta * x\n+\n+ # Branchless softplus\n+ exp_beta_x = cute.exp(beta_x, fastmath=True)\n+ softplus_val = (cutlass.Float32(1.0) / softplus_beta) * cute.log(\n+ cutlass.Float32(1.0) + exp_beta_x, fastmath=True\n+ )\n+ use_softplus = (\n+ cutlass.Float32(1.0)\n+ if beta_x <= softplus_threshold\n+ else cutlass.Float32(0.0)\n+ )\n+ softplus_x = (\n+ use_softplus * softplus_val + (cutlass.Float32(1.0) - use_softplus) * x\n+ )\n+\n+ r_g_value = -cute.exp(r_A_log, fastmath=True) * softplus_x\n+ r_beta = cutlass.Float32(1.0) / (\n+ cutlass.Float32(1.0) + cute.exp(-r_b, fastmath=True)\n+ )\n+ r_g = cute.exp(r_g_value, fastmath=True)\n+\n+ # Only thread 0 stores to shared memory\n if tidx == 0:\n sG[i_t] = r_g\n sBeta[i_t] = r_beta\n \n- # All threads must participate in barrier (CUDA requirement)\n- cute.arch.barrier()\n-\n- # Main computation only for valid batch entries\n- if cache_idx >= 0:\n- # Setup source tensor for initial state loading\n- gSrc_batch = h0_source[(cache_idx * HV + i_hv, None, None)]\n- gDst_h0 = cute.local_tile(\n- h0_source, (1, TILE_V_MTP, TILE_K_MTP), (cache_idx * HV + i_hv, None, 0)\n- )\n- gSrc = cute.local_tile(gSrc_batch, (TILE_V_MTP, TILE_K_MTP), (None, 0))\n-\n- thr_copy_load = tiled_copy_load.get_slice(tidx)\n-\n- # Main loop: v_tiles (outer) x time_steps (inner)\n- prefetch_count = cutlass.min(NUM_STAGES_MTP - 1, num_v_tiles)\n-\n- # Prefetch first v_tile(s)\n- for v_tiles in range(prefetch_count):\n- stage = v_tiles % NUM_STAGES_MTP\n- gSrc_tile = gSrc[(None, None, v_tiles)]\n- sData_stage = sData[(None, None, stage)]\n- thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n- thr_sData = thr_copy_load.partition_D(sData_stage)\n- cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n- cute.arch.cp_async_commit_group()\n-\n- # Process each v_tile\n- for v_tiles in range(num_v_tiles):\n- stage = v_tiles % NUM_STAGES_MTP\n-\n- cute.arch.cp_async_wait_group(0)\n- cute.arch.barrier()\n-\n- # Prefetch next v_tile\n- next_v_tiles = v_tiles + prefetch_count\n- if next_v_tiles < num_v_tiles:\n- next_stage = next_v_tiles % NUM_STAGES_MTP\n- gSrc_next = gSrc[(None, None, next_v_tiles)]\n- sData_next = sData[(None, None, next_stage)]\n- thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n- thr_sData = thr_copy_load.partition_D(sData_next)\n- cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n- cute.arch.cp_async_commit_group()\n-\n- # Inner loop: all time steps for this v_tile\n- for i_t in range(T):\n- # Load pre-computed values from shared memory\n- for i in range(vec_size):\n- r_q[i] = sQ[(i_t, i * 32 + lane_id)]\n- r_k[i] = sK[(i_t, i * 32 + lane_id)]\n-\n- r_g = sG[i_t]\n- r_beta = sBeta[i_t]\n-\n- # Compute delta rule for this v_tile\n- for row in range(0, TILE_V_MTP, 4):\n- row_offset = tidx // 32\n-\n- # Load h from sData, apply decay\n- for i in range(vec_size):\n- r_h[i] = (\n- sData[(row + row_offset, i * 32 + lane_id, stage)] * r_g\n- )\n-\n- # Compute sum_hk = h @ k\n+ cute.arch.barrier()\n+\n+ # Each group handles tile_v/num_groups V rows\n+ rows_per_group: cutlass.Constexpr[int] = tile_v // num_groups\n+ for row_in_group in cutlass.range_constexpr(rows_per_group):\n+ v_idx = i_v * tile_v + group_idx * rows_per_group + row_in_group\n+\n+ if v_idx < V:\n+ # Load h[v_idx, :] into registers using 3D local_tile + autovec_copy\n+ flat_state_idx = cache_idx * HV + i_hv\n+ h_tile = cute.local_tile(\n+ h0_source, (1, 1, vec_size), (flat_state_idx, v_idx, lane_in_group)\n+ )\n+ cute.autovec_copy(h_tile, r_h)\n+\n+ # Process all T time steps with h in registers\n+ for i_t in cutlass.range_constexpr(T):\n+ # Load pre-computed q, k from shared memory using 2D local_tile\n+ sQ_tile = cute.local_tile(sQ, (1, vec_size), (i_t, lane_in_group))\n+ sK_tile = cute.local_tile(sK, (1, vec_size), (i_t, lane_in_group))\n+ cute.autovec_copy(sQ_tile, r_q)\n+ cute.autovec_copy(sK_tile, r_k)\n+\n+ r_g = sG[i_t]\n+ r_beta = sBeta[i_t]\n+\n+ # Step 1: Apply decay to h\n+ for i in cutlass.range_constexpr(vec_size):\n+ r_h[i] = r_h[i] * r_g\n+\n+ # Step 2: Compute sum_hk = h @ k (group reduction)\n sum_hk = 0.0\n- for i in range(vec_size):\n+ for i in cutlass.range_constexpr(vec_size):\n sum_hk += r_h[i] * r_k[i]\n \n+ # Warp-level reduction\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n \n- # Delta rule update\n- v_idx = v_tiles * TILE_V_MTP + row + row_offset\n- v_new = sV[(i_t, v_idx)] - sum_hk\n- v_new = v_new * r_beta\n-\n- # Update h and write back to sData\n- for i in range(vec_size):\n+ # Step 3: Load v for this v_idx and time step, apply delta rule\n+ r_v = cutlass.Float32(v[i_n, i_t, i_hv, v_idx])\n+ v_new = (r_v - sum_hk) * r_beta\n+\n+ # Step 4: Update h: h += k * v_new\n+ for i in cutlass.range_constexpr(vec_size):\n r_h[i] += r_k[i] * v_new\n- sData[(row + row_offset, i * 32 + lane_id, stage)] = r_h[i]\n-\n- # Store intermediate state\n- if cache_intermediate_states:\n+\n+ # Cache intermediate state if needed using 3D local_tile + autovec_copy\n+ if cutlass.const_expr(cache_intermediate_states):\n flat_idx = i_n * T * HV + i_t * HV + i_hv\n- if v_idx < V:\n- for i in range(vec_size):\n- intermediate_states[\n- (flat_idx, v_idx, i * 32 + lane_id)\n- ] = r_h[i]\n-\n- # Compute sum_hq = h @ q (overlaps with store above)\n+ inter_tile = cute.local_tile(\n+ intermediate_states,\n+ (1, 1, vec_size),\n+ (flat_idx, v_idx, lane_in_group),\n+ )\n+ cute.autovec_copy(r_h, inter_tile)\n+\n+ # Step 5: Compute output: sum_hq = h @ q (group reduction)\n sum_hq = 0.0\n- for i in range(vec_size):\n+ for i in cutlass.range_constexpr(vec_size):\n sum_hq += r_h[i] * r_q[i]\n \n+ # Warp-level reduction\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n \n- o_idx = v_tiles * TILE_V_MTP + row + row_offset\n- if lane_id == 0 and o_idx < V:\n- sOutput[(i_t, o_idx)] = cutlass.Float32(sum_hq)\n-\n- # Write final h for this v_tile to h0_source\n- if not disable_state_update:\n- for row in range(0, TILE_V_MTP, 4):\n- row_offset = tidx // 32\n- for i in range(vec_size):\n- gDst_h0[(0, row + row_offset, i * 32 + lane_id, v_tiles)] = (\n- sData[(row + row_offset, i * 32 + lane_id, stage)]\n- )\n-\n- # Final writeback\n- cute.arch.barrier()\n-\n- for i_t in range(T):\n- if tidx < V:\n- o[(i_n, i_t, i_hv, tidx)] = cutlass.BFloat16(sOutput[(i_t, tidx)])\n+ # Write output (only lane 0 of each group)\n+ if lane_in_group == 0:\n+ o[(i_n, i_t, i_hv, v_idx)] = cutlass.BFloat16(sum_hq)\n+\n+ # Write final state back (if not disabled) using 3D local_tile + autovec_copy\n+ if cutlass.const_expr(not disable_state_update):\n+ h_tile_out = cute.local_tile(\n+ h0_source,\n+ (1, 1, vec_size),\n+ (flat_state_idx, v_idx, lane_in_group),\n+ )\n+ cute.autovec_copy(r_h, h_tile_out)\n \n \n @cute.jit\n@@ -2144,6 +2244,8 @@\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n+ tile_v: cutlass.Constexpr[int], # TILE_V - configurable for batch size\n+ vec_size: cutlass.Constexpr[int], # 4 for full warp, 8 for half-warp\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n@@ -2157,47 +2259,26 @@\n h0_source.layout.shape[2],\n )\n \n- num_v_tiles = cute.ceil_div(v_dim, TILE_V_MTP)\n- batch_size = B * HV\n- vec_size = TILE_K_MTP // 32 # Each thread in a warp processes this many elements\n-\n- # Composed Swizzle Layout to avoid shared memory bank conflicts\n- base_smem_layout = cute.make_layout(\n- (TILE_V_MTP, TILE_K_MTP, NUM_STAGES_MTP),\n- stride=(TILE_K_MTP, 1, TILE_V_MTP * TILE_K_MTP),\n- )\n- swizzle = cute.make_swizzle(2, 3, 7) # Swizzle<2, 3, 7>\n- smem_layout_staged = cute.make_composed_layout(swizzle, 0, base_smem_layout)\n-\n- # Create tiled copy for G2S load\n- copy_atom = cute.make_copy_atom(\n- cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n- cutlass.Float32,\n- num_bits_per_copy=128,\n- )\n- thread_layout = cute.make_layout((4, 32), stride=(32, 1))\n- val_layout = cute.make_layout((1, 4))\n- tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n-\n- # Calculate shared memory size\n+ num_v_tiles = cute.ceil_div(v_dim, tile_v)\n+\n+ # Grid: (B * HV * num_v_tiles, 1, 1) - parallelize across V dimension\n+ grid_size = B * HV * num_v_tiles\n+\n+ # Shared memory for pre-computed q, k, g, beta\n smem_bytes = (\n- 4 * TILE_V_MTP * TILE_K_MTP * NUM_STAGES_MTP\n- + 4 * T * v_dim\n- + 4 * T * (k_dim + 8)\n- + 4 * T * (k_dim + 8)\n- + 4 * T * (v_dim + 8)\n- + 4 * T\n- + 4 * T\n- + 128\n+ 4 * T * (k_dim + 8) # sQ\n+ + 4 * T * (k_dim + 8) # sK\n+ + 4 * T # sG\n+ + 4 * T # sBeta\n+ + 128 # alignment\n )\n \n gdn_verify_kernel_mtp(\n- tiled_copy_load,\n h0_source,\n intermediate_states,\n- smem_layout_staged,\n vec_size,\n num_v_tiles,\n+ tile_v,\n A_log,\n a,\n dt_bias,\n@@ -2223,7 +2304,7 @@\n disable_state_update,\n cache_intermediate_states,\n ).launch(\n- grid=(batch_size, 1, 1),\n+ grid=(grid_size, 1, 1),\n block=[NUM_THREADS_MTP, 1, 1],\n smem=smem_bytes,\n stream=stream,\n@@ -2244,6 +2325,8 @@\n cache_intermediate_states: bool,\n scale: float,\n use_qk_l2norm: bool,\n+ tile_v: int, # TILE_V - configurable for batch size\n+ vec_size: int, # 4 for full warp, 8 for half-warp\n ):\n \"\"\"Cache compiled MTP kernel for given configuration.\"\"\"\n return {}\n@@ -2320,6 +2403,10 @@\n _, _, HV, V = v.shape\n pool_size = initial_state.shape[0]\n \n+ # Dynamic TILE_V and vec_size selection based on batch size and sequence length\n+ tile_v = get_tile_v_mtp(B, T)\n+ vec_size = get_vec_size_mtp(B, T)\n+\n # Validate state shape\n assert initial_state.shape == (pool_size, HV, V, K), (\n f\"Expected initial_state shape [pool_size={pool_size}, HV={HV}, V={V}, K={K}], got {initial_state.shape}\"\n@@ -2328,8 +2415,8 @@\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n- assert V % TILE_V_MTP == 0, (\n- f\"V must be divisible by {TILE_V_MTP} to prevent out-of-bounds access, got V={V}\"\n+ assert V % tile_v == 0, (\n+ f\"V must be divisible by {tile_v} to prevent out-of-bounds access, got V={V}\"\n )\n \n # Validate dtypes\n@@ -2374,9 +2461,6 @@\n else:\n cache_steps = T\n intermediate_states = torch.zeros(1, 1, 1, dtype=torch.float32, device=q.device)\n-\n- # Create cu_seqlens\n- cu_seqlens = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n \n # Compile kernel with TVM FFI (cached)\n cache_key = (\n@@ -2392,8 +2476,15 @@\n cache_intermediate_states,\n scale,\n use_qk_l2norm,\n+ tile_v,\n+ vec_size,\n )\n cache = _get_compiled_mtp_kernel(*cache_key)\n+\n+ # Get or create cu_seqlens (cached per config)\n+ if \"cu_seqlens\" not in cache or cache[\"cu_seqlens\"].device != q.device:\n+ cache[\"cu_seqlens\"] = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n+ cu_seqlens = cache[\"cu_seqlens\"]\n \n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n@@ -2436,6 +2527,8 @@\n H=H,\n K=K,\n V=V,\n+ tile_v=tile_v,\n+ vec_size=vec_size,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n@@ -2467,7 +2560,9 @@\n )\n \n # Copy state back if needed (no sync needed - PyTorch handles stream ordering)\n- if not disable_state_update:\n+ # Only copy if state update is enabled AND initial_state was not contiguous\n+ # (if contiguous, reshape returns a view and kernel updated state in-place)\n+ if not disable_state_update and not initial_state.is_contiguous():\n initial_state.copy_(h0_source.reshape(pool_size, HV, V, K))\n \n # Convert output to target dtype if needed"},"lines_added":{"kind":"number","value":438,"string":"438"},"lines_removed":{"kind":"number","value":343,"string":"343"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200"],"string":"[\n \"B200\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.59x","0.86x","1.35x","0.73x","1.49x","0.85x","1.37x","0.79x","1.40x","0.86x"],"string":"[\n \"1.59x\",\n \"0.86x\",\n \"1.35x\",\n \"0.73x\",\n \"1.49x\",\n \"0.85x\",\n \"1.37x\",\n \"0.79x\",\n \"1.40x\",\n \"0.86x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_decode.py).\n\nGoal: perf: improve gdn decode cute-dsl kernels\nTarget hardware: B200\nTarget models: unspecified\n\nCurrent file:\n```python\n\"\"\"\nCopyright (c) 2025 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\n\"\"\"\nGated Delta Rule Decode Kernel - Single Token Generation\n\nThis file implements a fused CUDA kernel using CUTLASS CuTe DSL for executing\nSigmoid Gating Delta Rule updates during decode phase. Key features:\n\nArchitecture Design:\n- Uses TMA (Tensor Memory Accelerator) for efficient Global Memory → Shared Memory transfers\n- Employs 2-stage pipeline to overlap loading and computation, hiding memory latency\n- Each block uses 128 threads (4 warps), with each warp processing one matrix row\n- Tile size: 8x128 (TILE_V x TILE_K)\n\nComputation Flow:\n1. Warp 0 handles TMA prefetch, loading data from GMEM to SMEM\n2. All warps compute in parallel: softplus, L2 normalization, delta rule updates\n3. Each warp processes one row of data, completing h_new = g*h + k*(beta*(v - h@k))\n4. Uses warp-level shuffle for efficient reduction operations\n5. Results are vectorized and written back to Global Memory\n\nPerformance Optimizations:\n- Vectorized memory access: each thread processes vec_size=4 elements (128-bit aligned)\n- Warp-level collective operations: shuffle-based reduction\n- Pipeline overlap: load stage N+1 while computing stage N\n\"\"\"\n\nimport functools\nfrom typing import Optional, Tuple\nimport torch\nimport cutlass\nimport cutlass.cute as cute\nfrom cutlass.cute.nvgpu import cpasync\nfrom cutlass.cute.runtime import from_dlpack\nimport cuda.bindings.driver as cuda\n\ntry:\n from .api_logging import flashinfer_api\n\n _FLASHINFER_AVAILABLE = True\nexcept ImportError:\n _FLASHINFER_AVAILABLE = False\n\n # Fallback decorator for standalone usage\n def flashinfer_api(func): # type: ignore[misc]\n return func\n\n\n# ============================================================================\n# Global configuration for PRETRANSPOSE version ([B*HV, V, K])\n# ============================================================================\nTILE_V = 8\nTILE_K = 128\nNUM_STAGES = 2\nNUM_THREADS = 128 # 4 warps\nNUM_BLOCKS_PER_STATE = 8\n\n# ============================================================================\n# Global configuration for NONTRANSPOSE version ([pool, HV, K, V])\n# ============================================================================\nTILE_K_NT = 128\nTILE_V_NT = 32\nTILE_V_PADDED_NT = 36\nTILE_V_SMALL_NT = 16\nTILE_V_SMALL_PADDED_NT = 20\nNUM_STAGES_NT = 2\nNUM_THREADS_NT = 128\nNUM_BLOCKS_PER_STATE_SMALL_NT = 8\nNUM_THREADS_LARGE_NT = 256\nNUM_WARPS_LARGE_NT = 8\nV_PER_WARP_NT = 4\nROWS_PER_ITER_NT = 8\nNUM_K_ITERS_NT = TILE_K_NT // ROWS_PER_ITER_NT\nSMALL_BATCH_THRESHOLD_NT = 32\n\n# ============================================================================\n# Global configuration for MTP (Multiple Token Processing) version\n# ============================================================================\nTILE_V_MTP = 8\nTILE_K_MTP = 128\nNUM_STAGES_MTP = 2\nNUM_THREADS_MTP = 128 # 4 warps\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n\n cute.arch.barrier()\n\n # Get current batch\n gSrc_batch = h0_source[(batch_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (batch_idx, None, 0))\n\n # V 方向分 tiles\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n start_v_tiles = batch_inner * num_v_tiles_per_block\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles_per_block)\n for v_tiles in range(start_v_tiles, start_v_tiles + prefetch_count):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n for i in range(vec_size):\n r_q[i] = cutlass.Float32(q[i_n, i_t, i_h, i * 32 + lane_id])\n r_k[i] = cutlass.Float32(k[i_n, i_t, i_h, i * 32 + lane_id])\n # Store v to shared memory instead of register\n v_val = cutlass.Float32(v[i_n, i_t, i_hv, i * 32 + lane_id])\n sV[i * 32 + lane_id] = v_val\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in range(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n norm_q = cute.sqrt(sum_q + 1e-6)\n norm_k = cute.sqrt(sum_k + 1e-6)\n for i in range(vec_size):\n r_q[i] = r_q[i] / norm_q\n r_k[i] = r_k[i] / norm_k\n\n # Apply scaling in Float32\n for i in range(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n end_v_tiles = start_v_tiles + num_v_tiles_per_block\n for v_tiles in range(start_v_tiles, end_v_tiles):\n stage = (v_tiles - start_v_tiles) % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < end_v_tiles:\n next_stage = (next_v_tiles - start_v_tiles) % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage\n for row in range(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n for i in range(vec_size):\n r_h[i] = sData[(row + row_offset, i * 32 + lane_id, stage)]\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in range(vec_size):\n r_h[i] += r_k[i] * v_new\n gDst[(0, row + row_offset, i * 32 + lane_id, v_tiles)] = r_h[i]\n sum_hq += r_h[i] * r_q[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n if tidx >= start_v_tiles * TILE_V and tidx < end_v_tiles * TILE_V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n):\n \"\"\"Each block uses pipeline to load one batch and vectorized writeback\"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n i_t = 0\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # ===================================================================\n # Allocate shared memory (using passed-in layout)\n # ===================================================================\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n\n # Allocate shared memory for output (size V) - use BFloat16 to match SGLang\n sOutput = smem.allocate_tensor(cutlass.BFloat16, cute.make_layout((V,)), 16)\n\n # Allocate shared memory for v values (size K, to reduce register usage)\n sV = smem.allocate_tensor(cutlass.Float32, cute.make_layout((V,)), 16)\n\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n # r_v moved to shared memory (sV)\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n\n cute.arch.barrier()\n\n # Get current batch\n gSrc_batch = h0_source[(batch_idx, None, None)] # (V, K)\n gDst = cute.local_tile(h0_source, (1, TILE_V, TILE_K), (batch_idx, None, 0))\n\n # V 方向分 tiles\n gSrc = cute.local_tile(\n gSrc_batch, (TILE_V, TILE_K), (None, 0)\n ) # (TILE_V, TILE_K, num_v_tiles)\n\n # Partition for load\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # ===================================================================\n # Prefetch: All threads participate in cp.async load\n # ===================================================================\n prefetch_count = cutlass.min(NUM_STAGES - 1, num_v_tiles)\n for v_tiles in range(prefetch_count):\n stage = v_tiles % NUM_STAGES\n\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n for i in range(vec_size):\n r_q[i] = cutlass.Float32(q[i_n, i_t, i_h, i * 32 + lane_id])\n r_k[i] = cutlass.Float32(k[i_n, i_t, i_h, i * 32 + lane_id])\n # Store v to shared memory instead of register\n v_val = cutlass.Float32(v[i_n, i_t, i_hv, i * 32 + lane_id])\n sV[i * 32 + lane_id] = v_val\n\n cute.arch.barrier() # Ensure all threads finish writing to sV\n\n # ===================================================================\n # Compute g and beta (scalar values)\n # ===================================================================\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n # softplus(x) = (1/beta) * log(1 + exp(beta*x))\n # Compute in Float32\n exp_beta_x = cute.exp(beta_x)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n # Compute g = exp(A_log) * softplus_x\n r_g_value = -cute.exp(r_A_log) * softplus_x\n\n # Compute beta = 1 / (1 + exp(-b))\n r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n\n # Store to scalar (Float32)\n r_g = cute.exp(r_g_value)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n if use_qk_l2norm:\n # Compute L2 norm of q and k\n sum_q = 0.0\n sum_k = 0.0\n for i in range(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n # Warp-level reduction using butterfly shuffle\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n norm_q = cute.sqrt(sum_q + 1e-6)\n norm_k = cute.sqrt(sum_k + 1e-6)\n for i in range(vec_size):\n r_q[i] = r_q[i] / norm_q\n r_k[i] = r_k[i] / norm_k\n\n # Apply scaling in Float32\n for i in range(vec_size):\n r_q[i] = r_q[i] * scale\n\n # ===================================================================\n # Mainloop: All threads participate\n # ===================================================================\n for v_tiles in range(num_v_tiles):\n stage = v_tiles % NUM_STAGES\n\n # Step 1: Wait for current stage to complete\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Step 2: Issue async load for next tile (after compute)\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < num_v_tiles:\n next_stage = next_v_tiles % NUM_STAGES\n\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Step 3: Compute using data from current stage\n for row in range(0, TILE_V, 4):\n row_offset = tidx // 32\n sum_hk = 0.0\n for i in range(vec_size):\n r_h[i] = sData[(row + row_offset, i * 32 + lane_id, stage)]\n r_h[i] = r_h[i] * r_g\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n v_new = sV[v_tiles * TILE_V + row + row_offset] - sum_hk\n v_new = v_new * r_beta\n\n sum_hq = 0.0\n for i in range(vec_size):\n r_h[i] += r_k[i] * v_new\n gDst[(0, row + row_offset, i * 32 + lane_id, v_tiles)] = r_h[i]\n sum_hq += r_h[i] * r_q[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[o_idx] = cutlass.BFloat16(sum_hq)\n\n # ===================================================================\n # Final writeback: Copy output from shared memory to global memory\n # All threads write (V=128, NUM_THREADS=128)\n # ===================================================================\n cute.arch.barrier() # Ensure all writes to sOutput are complete\n\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = sOutput[tidx]\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * batch_size * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # print(f\"Batched CP.ASYNC Load + Store (bypass L1 cache)\")\n # print(f\" {batch_size} batches x {v_dim}x{k_dim} matrices\")\n # print(f\" Tile: {TILE_V}x{TILE_K}, {num_v_tiles} tiles/batch\")\n # print(f\" Threads: {NUM_THREADS} ({NUM_THREADS // 32} warps), vec_size: {vec_size}\")\n # print(f\" Total: {total_data_mb:.1f} MB\\n\")\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_small_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n ).launch(\n grid=(batch_size * NUM_BLOCKS_PER_STATE, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_pretranspose(\n h0_source: cute.Tensor, # [B*HV, K, V]\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n # h0_source: (B*HV, V, K)\n batch_size, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n # Create cp.async copy with cache-global mode (bypass L1)\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128, # 4 elements per copy\n )\n\n # Thread layout: 4 rows × 32 threads/row = 128 threads\n thread_layout = cute.make_layout(\n (4, 32), # 4 rows, 32 threads/row\n stride=(32, 1),\n )\n val_layout = cute.make_layout((1, 4)) # Each thread handles 4 elements\n\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V)\n v_dim * k_dim * batch_size * 4 / 1024 / 1024\n\n vec_size = (\n TILE_K // 32\n ) # Each thread in a warp processes this many elements (always 4 for TILE_K=128)\n\n # print(f\"Batched CP.ASYNC Load + Store (bypass L1 cache)\")\n # print(f\" {batch_size} batches x {v_dim}x{k_dim} matrices\")\n # print(f\" Tile: {TILE_V}x{TILE_K}, {num_v_tiles} tiles/batch\")\n # print(f\" Threads: {NUM_THREADS} ({NUM_THREADS // 32} warps), vec_size: {vec_size}\")\n # print(f\" Total: {total_data_mb:.1f} MB\\n\")\n\n # Create SMEM layout\n smem_layout_staged = cute.make_layout(\n (TILE_V, TILE_K, NUM_STAGES), stride=(TILE_K, 1, TILE_V * TILE_K)\n )\n\n # sData: TILE_V * TILE_K * NUM_STAGES * 4 bytes (Float32)\n # sV: K * 4 bytes (Float32)\n # sOutput: V * 2 bytes (BFloat16)\n smem_bytes = 4 * TILE_V * TILE_K * NUM_STAGES + 4 * k_dim + 2 * v_dim + 32\n\n gdn_decode_kernel_big_batch_pretranspose(\n tiled_copy_load,\n h0_source,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# FlashInfer API Layer\n# ============================================================================\n\n\n@functools.cache\ndef _get_compiled_decode_kernel(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled kernel for given configuration (pretranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\n@functools.cache\ndef _get_compiled_decode_kernel_nontranspose(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n dtype: torch.dtype,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled kernel for given configuration (nontranspose version).\"\"\"\n # This will be populated on first call\n return {}\n\n\n@flashinfer_api\ndef gated_delta_rule_decode_pretranspose(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n state: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Gated Delta Rule Decode kernel for single-token generation.\n\n This implements the decode phase of gated delta rule linear attention,\n processing one token at a time and updating the recurrent state.\n\n Args:\n q (torch.Tensor):\n Current query of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n k (torch.Tensor):\n Current key of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n v (torch.Tensor):\n Current value of shape ``[B, 1, HV, V]``. Must be float16/bfloat16.\n state (torch.Tensor):\n Current state of shape ``[B, HV, V, K]`` (v-major layout).\n Must be float32. Will be updated in-place.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``. Must be float32.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``. Must be bfloat16 or float32.\n b (torch.Tensor):\n Update gate (beta) input of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n scale (Optional[float]):\n Scale factor for queries. If None, defaults to ``1 / sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, 1, HV, V]``.\n If None, will be allocated automatically.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, 1, HV, V]``\n - state: Updated state tensor of shape ``[B, HV, V, K]``\n\n Note:\n - Requires SM90 (Hopper) architecture\n - State is updated in-place\n - K and V must be multiples of 4 for vectorized loads\n - State layout is v-major: [B, HV, V, K]\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n assert T == 1, f\"Decode only supports T=1, got T={T}\"\n _, _, HV, V = v.shape\n\n # Validate state shape\n assert state.shape == (B, HV, V, K), (\n f\"Expected state shape [B={B}, HV={HV}, V={V}, K={K}], got {state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n assert V % TILE_V == 0, (\n f\"V must be divisible by {TILE_V} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert state.dtype == torch.float32, f\"state must be float32, got {state.dtype}\"\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n # Note: kernel outputs bfloat16, we'll convert to q.dtype if needed\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # Convert state from [B, HV, V, K] to [B*HV, V, K] for kernel\n h0_source = state.reshape(B * HV, V, K)\n\n # Create dummy tensors for unused parameters\n h0_indices = torch.zeros(B, dtype=torch.int32, device=q.device)\n cu_seqlens = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel(*cache_key)\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Choose kernel based on batch size\n if B <= 32:\n run_func = run_gdn_decode_kernel_small_batch_pretranspose\n else:\n run_func = run_gdn_decode_kernel_big_batch_pretranspose\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n h0_source_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n B=B,\n T=T,\n H=H,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n cache[\"compiled\"](\n h0_source, A_log, a, dt_bias, q, k, v, b, output, h0_indices, cu_seqlens, stream\n )\n\n # Reshape state back (no sync needed - PyTorch handles stream ordering)\n state.copy_(h0_source.reshape(B, HV, V, K))\n\n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, state\n\n\n# ============================================================================\n# NONTRANSPOSE Version Kernels - K-major layout [pool, HV, K, V]\n# ============================================================================\n\n\n@cute.kernel\ndef gdn_decode_kernel_small_batch_nontranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n num_v_tiles: cutlass.Constexpr[int],\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n use_qk_l2norm: cutlass.Constexpr[bool],\n):\n \"\"\"Small batch kernel for (N, 1, ...) format with K-major state layout.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n in_warp_tid = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n block_idx, _, _ = cute.arch.block_idx()\n\n NUM_WARPS_SMALL = 4\n V_PER_WARP_SMALL = TILE_V_SMALL_NT // NUM_WARPS_SMALL\n ROWS_PER_ITER_SMALL = 32 // V_PER_WARP_SMALL\n NUM_K_ITERS_SMALL = TILE_K_NT // ROWS_PER_ITER_SMALL\n\n batch_idx = block_idx // NUM_BLOCKS_PER_STATE_SMALL_NT\n batch_inner = block_idx % NUM_BLOCKS_PER_STATE_SMALL_NT\n num_v_tiles_per_block = num_v_tiles // NUM_BLOCKS_PER_STATE_SMALL_NT\n start_v_tile = batch_inner * num_v_tiles_per_block\n\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n pool_idx = h0_indices[i_n]\n\n if pool_idx >= 0:\n k_local = in_warp_tid // V_PER_WARP_SMALL\n v_local = in_warp_tid % V_PER_WARP_SMALL\n v_base = warp_idx * V_PER_WARP_SMALL\n v_idx = v_base + v_local\n\n smem = cutlass.utils.SmemAllocator()\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n smem_o_layout = cute.make_layout((TILE_V_SMALL_NT,), stride=(1,))\n smem_o = smem.allocate_tensor(cutlass.Float32, smem_o_layout, 128)\n smem_k_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n smem_q_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n sK = smem.allocate_tensor(cutlass.Float32, smem_k_layout, 128)\n sQ = smem.allocate_tensor(cutlass.Float32, smem_q_layout, 128)\n\n if tidx < TILE_K_NT:\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n\n gSrc_batch = h0_source[(pool_idx, i_hv, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_SMALL_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n prefetch_count = cutlass.min(NUM_STAGES_NT - 1, num_v_tiles_per_block)\n for v_tile_offset in range(prefetch_count):\n v_tile = start_v_tile + v_tile_offset\n stage = v_tile_offset % NUM_STAGES_NT\n gSrc_tile = gSrc[(None, None, v_tile)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_a = cutlass.Float32(a[i_n, 0, i_hv])\n r_b = cutlass.Float32(b[i_n, 0, i_hv])\n\n r_g = 0.0\n r_beta = 0.0\n if in_warp_tid == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n r_g_value = -cute.exp(r_A_log) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n r_g = cute.exp(r_g_value)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n cute.arch.barrier()\n\n if use_qk_l2norm:\n sum_q_partial = 0.0\n sum_k_partial = 0.0\n if tidx < TILE_K_NT:\n q_val = sQ[tidx]\n k_val = sK[tidx]\n sum_q_partial = q_val * q_val\n sum_k_partial = k_val * k_val\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q_partial += cute.arch.shuffle_sync_bfly(\n sum_q_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k_partial += cute.arch.shuffle_sync_bfly(\n sum_k_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n if in_warp_tid == 0:\n smem_o[warp_idx] = sum_q_partial\n smem_o[warp_idx + 4] = sum_k_partial\n cute.arch.barrier()\n\n inv_norm_q = 0.0\n inv_norm_k = 0.0\n if warp_idx == 0:\n local_sum_q = 0.0\n local_sum_k = 0.0\n if in_warp_tid < NUM_WARPS_SMALL:\n local_sum_q = smem_o[in_warp_tid]\n local_sum_k = smem_o[in_warp_tid + 4]\n for offset in [2, 1]:\n local_sum_q += cute.arch.shuffle_sync_bfly(\n local_sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n local_sum_k += cute.arch.shuffle_sync_bfly(\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n smem_o[0] = cute.rsqrt(local_sum_q + 1e-6)\n smem_o[1] = cute.rsqrt(local_sum_k + 1e-6)\n cute.arch.barrier()\n\n inv_norm_q = smem_o[0]\n inv_norm_k = smem_o[1]\n\n if tidx < TILE_K_NT:\n sK[tidx] = sK[tidx] * inv_norm_k\n sQ[tidx] = sQ[tidx] * scale * inv_norm_q\n cute.arch.barrier()\n else:\n if tidx < TILE_K_NT:\n sQ[tidx] = sQ[tidx] * scale\n cute.arch.barrier()\n\n for v_tile_offset in range(num_v_tiles_per_block):\n v_tile = start_v_tile + v_tile_offset\n stage = v_tile_offset % NUM_STAGES_NT\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n next_v_tile_offset = v_tile_offset + prefetch_count\n if next_v_tile_offset < num_v_tiles_per_block:\n next_v_tile = start_v_tile + next_v_tile_offset\n next_stage = next_v_tile_offset % NUM_STAGES_NT\n gSrc_next = gSrc[(None, None, next_v_tile)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n v_global = v_tile * TILE_V_SMALL_NT + v_idx\n r_v = cutlass.Float32(v[i_n, 0, i_hv, v_global])\n\n sum_hk = 0.0\n for k_iter in range(NUM_K_ITERS_SMALL, unroll=16): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_SMALL\n k_idx = k_base + k_local\n h_val = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n sum_hk += h_val * r_k_val\n\n for offset in [4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk,\n offset=offset * V_PER_WARP_SMALL,\n mask=-1,\n mask_and_clamp=31,\n )\n\n v_new = (r_v - sum_hk) * r_beta\n v_new = cute.arch.shuffle_sync(v_new, v_local)\n\n sum_hq = 0.0\n for k_iter in range(NUM_K_ITERS_SMALL, unroll=16): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_SMALL\n k_idx = k_base + k_local\n h_old = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n r_q_val = sQ[k_idx]\n h_new = h_old + r_k_val * v_new\n sData[(k_idx, v_idx, stage)] = h_new\n sum_hq += h_new * r_q_val\n\n for offset in [4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq,\n offset=offset * V_PER_WARP_SMALL,\n mask=-1,\n mask_and_clamp=31,\n )\n\n if k_local == 0:\n v_global_out = v_tile * TILE_V_SMALL_NT + v_idx\n o[(i_n, 0, i_hv, v_global_out)] = cutlass.BFloat16(sum_hq)\n\n cute.arch.barrier()\n\n for k_iter in range(NUM_K_ITERS_SMALL):\n flat_idx = tidx + k_iter * 128\n k_write = flat_idx // TILE_V_SMALL_NT\n v_write = flat_idx % TILE_V_SMALL_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_SMALL_NT + v_write\n h0_source[(pool_idx, i_hv, k_write, v_global_write)] = h_val\n\n cute.arch.barrier()\n\n\n@cute.kernel\ndef gdn_decode_kernel_big_batch_nontranspose(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor,\n smem_layout_staged: cute.Layout,\n num_v_tiles: cutlass.Constexpr[int],\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n use_qk_l2norm: cutlass.Constexpr[bool],\n):\n \"\"\"Large batch kernel for (N, 1, ...) format with K-major state layout.\"\"\"\n tidx, _, _ = cute.arch.thread_idx()\n in_warp_tid = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n pool_idx = h0_indices[i_n]\n\n if pool_idx >= 0:\n k_local = in_warp_tid // V_PER_WARP_NT\n v_local = in_warp_tid % V_PER_WARP_NT\n v_base = warp_idx * V_PER_WARP_NT\n v_idx = v_base + v_local\n\n smem = cutlass.utils.SmemAllocator()\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n smem_o_layout = cute.make_layout((TILE_V_NT,), stride=(1,))\n smem_o = smem.allocate_tensor(cutlass.Float32, smem_o_layout, 128)\n smem_k_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n smem_q_layout = cute.make_layout((TILE_K_NT,), stride=(1,))\n sK = smem.allocate_tensor(cutlass.Float32, smem_k_layout, 128)\n sQ = smem.allocate_tensor(cutlass.Float32, smem_q_layout, 128)\n\n if tidx < TILE_K_NT:\n sK[tidx] = cutlass.Float32(k[i_n, 0, i_h, tidx])\n sQ[tidx] = cutlass.Float32(q[i_n, 0, i_h, tidx])\n\n gSrc_batch = h0_source[(pool_idx, i_hv, None, None)]\n gSrc = cute.local_tile(gSrc_batch, (TILE_K_NT, TILE_V_NT), (0, None))\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n prefetch_count = cutlass.min(NUM_STAGES_NT - 1, num_v_tiles)\n for v_tile in range(prefetch_count):\n stage = v_tile % NUM_STAGES_NT\n gSrc_tile = gSrc[(None, None, v_tile)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n r_a = cutlass.Float32(a[i_n, 0, i_hv])\n r_b = cutlass.Float32(b[i_n, 0, i_hv])\n\n r_g = 0.0\n r_beta = 0.0\n if in_warp_tid == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n r_g_value = -cute.exp(r_A_log) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n r_g = cute.exp(r_g_value)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n cute.arch.barrier()\n\n if use_qk_l2norm:\n sum_q_partial = 0.0\n sum_k_partial = 0.0\n if tidx < TILE_K_NT:\n q_val = sQ[tidx]\n k_val = sK[tidx]\n sum_q_partial = q_val * q_val\n sum_k_partial = k_val * k_val\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q_partial += cute.arch.shuffle_sync_bfly(\n sum_q_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k_partial += cute.arch.shuffle_sync_bfly(\n sum_k_partial, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n if in_warp_tid == 0:\n smem_o[warp_idx] = sum_q_partial\n smem_o[warp_idx + 8] = sum_k_partial\n cute.arch.barrier()\n\n inv_norm_q = 0.0\n inv_norm_k = 0.0\n if warp_idx == 0:\n local_sum_q = 0.0\n local_sum_k = 0.0\n if in_warp_tid < NUM_WARPS_LARGE_NT:\n local_sum_q = smem_o[in_warp_tid]\n local_sum_k = smem_o[in_warp_tid + 8]\n for offset in [4, 2, 1]:\n local_sum_q += cute.arch.shuffle_sync_bfly(\n local_sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n local_sum_k += cute.arch.shuffle_sync_bfly(\n local_sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n if in_warp_tid == 0:\n smem_o[0] = cute.rsqrt(local_sum_q + 1e-6)\n smem_o[1] = cute.rsqrt(local_sum_k + 1e-6)\n cute.arch.barrier()\n\n inv_norm_q = smem_o[0]\n inv_norm_k = smem_o[1]\n\n if tidx < TILE_K_NT:\n sK[tidx] = sK[tidx] * inv_norm_k\n sQ[tidx] = sQ[tidx] * scale * inv_norm_q\n cute.arch.barrier()\n else:\n if tidx < TILE_K_NT:\n sQ[tidx] = sQ[tidx] * scale\n cute.arch.barrier()\n\n for v_tile in range(num_v_tiles):\n stage = v_tile % NUM_STAGES_NT\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n next_v_tile = v_tile + prefetch_count\n if next_v_tile < num_v_tiles:\n next_stage = next_v_tile % NUM_STAGES_NT\n gSrc_next = gSrc[(None, None, next_v_tile)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n v_global = v_tile * TILE_V_NT + v_idx\n r_v = cutlass.Float32(v[i_n, 0, i_hv, v_global])\n\n sum_hk = 0.0\n for k_iter in range(NUM_K_ITERS_NT, unroll=8): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_NT\n k_idx = k_base + k_local\n h_val = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n sum_hk += h_val * r_k_val\n\n for offset in [4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset * V_PER_WARP_NT, mask=-1, mask_and_clamp=31\n )\n\n v_new = (r_v - sum_hk) * r_beta\n v_new = cute.arch.shuffle_sync(v_new, v_local)\n\n sum_hq = 0.0\n for k_iter in range(NUM_K_ITERS_NT, unroll=8): # type: ignore[call-overload]\n k_base = k_iter * ROWS_PER_ITER_NT\n k_idx = k_base + k_local\n h_old = sData[(k_idx, v_idx, stage)] * r_g\n r_k_val = sK[k_idx]\n r_q_val = sQ[k_idx]\n h_new = h_old + r_k_val * v_new\n sData[(k_idx, v_idx, stage)] = h_new\n sum_hq += h_new * r_q_val\n\n for offset in [4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset * V_PER_WARP_NT, mask=-1, mask_and_clamp=31\n )\n\n if k_local == 0:\n v_global_out = v_tile * TILE_V_NT + v_idx\n o[(i_n, 0, i_hv, v_global_out)] = cutlass.BFloat16(sum_hq)\n\n cute.arch.barrier()\n\n for k_iter in range(NUM_K_ITERS_NT):\n flat_idx = tidx + k_iter * 256\n k_write = flat_idx // TILE_V_NT\n v_write = flat_idx % TILE_V_NT\n if k_write < TILE_K_NT:\n h_val = sData[(k_write, v_write, stage)]\n v_global_write = v_tile * TILE_V_NT + v_write\n h0_source[(pool_idx, i_hv, k_write, v_global_write)] = h_val\n\n cute.arch.barrier()\n\n\n@cute.jit\ndef run_gdn_decode_kernel_small_batch_nontranspose(\n cu_seqlens: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n h0_source: cute.Tensor,\n h0_indices: cute.Tensor,\n o: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n pool_size, hv_dim, k_dim, v_dim = h0_source.layout.shape\n n_indices = h0_indices.layout.shape[0]\n batch_size = n_indices * hv_dim\n\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n num_v_tiles_small = cute.ceil_div(v_dim, TILE_V_SMALL_NT)\n smem_layout_small = cute.make_layout(\n (TILE_K_NT, TILE_V_SMALL_NT, NUM_STAGES_NT),\n stride=(TILE_V_SMALL_PADDED_NT, 1, TILE_K_NT * TILE_V_SMALL_PADDED_NT),\n )\n thread_layout_small = cute.make_layout((32, 4), stride=(4, 1))\n val_layout_small = cute.make_layout((1, 4))\n tiled_copy_load_small = cute.make_tiled_copy_tv(\n copy_atom, thread_layout_small, val_layout_small\n )\n smem_bytes_small = (\n 4 * TILE_K_NT * TILE_V_SMALL_PADDED_NT * NUM_STAGES_NT\n + 4 * TILE_V_SMALL_NT\n + 4 * TILE_K_NT * 2\n + 64\n )\n\n gdn_decode_kernel_small_batch_nontranspose(\n tiled_copy_load_small,\n h0_source,\n smem_layout_small,\n num_v_tiles_small,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n o,\n h0_indices,\n softplus_beta,\n softplus_threshold,\n scale,\n H,\n HV,\n use_qk_l2norm,\n ).launch(\n grid=(batch_size * NUM_BLOCKS_PER_STATE_SMALL_NT, 1, 1),\n block=[NUM_THREADS_NT, 1, 1],\n smem=smem_bytes_small,\n stream=stream,\n )\n\n\n@cute.jit\ndef run_gdn_decode_kernel_big_batch_nontranspose(\n cu_seqlens: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n a: cute.Tensor,\n b: cute.Tensor,\n A_log: cute.Tensor,\n dt_bias: cute.Tensor,\n h0_source: cute.Tensor,\n h0_indices: cute.Tensor,\n o: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n HV: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n pool_size, hv_dim, k_dim, v_dim = h0_source.layout.shape\n n_indices = h0_indices.layout.shape[0]\n batch_size = n_indices * hv_dim\n\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n num_v_tiles = cute.ceil_div(v_dim, TILE_V_NT)\n base_smem_layout = cute.make_layout(\n (TILE_K_NT, TILE_V_NT, NUM_STAGES_NT),\n stride=(TILE_V_PADDED_NT, 1, TILE_K_NT * TILE_V_PADDED_NT),\n )\n thread_layout = cute.make_layout((32, 8), stride=(8, 1))\n val_layout = cute.make_layout((1, 4))\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n smem_bytes = (\n 4 * TILE_K_NT * TILE_V_PADDED_NT * NUM_STAGES_NT\n + 4 * TILE_V_NT\n + 4 * TILE_K_NT * 2\n + 64\n )\n\n gdn_decode_kernel_big_batch_nontranspose(\n tiled_copy_load,\n h0_source,\n base_smem_layout,\n num_v_tiles,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n o,\n h0_indices,\n softplus_beta,\n softplus_threshold,\n scale,\n H,\n HV,\n use_qk_l2norm,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS_LARGE_NT, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n# ============================================================================\n# FlashInfer API Layer - NONTRANSPOSE Version (Recommended)\n# ============================================================================\n\n\n@flashinfer_api\ndef gated_delta_rule_decode(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n state: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n r\"\"\"Gated Delta Rule Decode kernel (K-major layout, no transpose needed).\n\n This implements the decode phase of gated delta rule linear attention,\n processing one token at a time and updating the recurrent state.\n This version uses K-major state layout [B, HV, K, V] which is more natural\n and doesn't require transposition.\n\n Args:\n q (torch.Tensor):\n Current query of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n k (torch.Tensor):\n Current key of shape ``[B, 1, H, K]``. Must be float16/bfloat16.\n v (torch.Tensor):\n Current value of shape ``[B, 1, HV, V]``. Must be float16/bfloat16.\n state (torch.Tensor):\n Current state of shape ``[B, HV, K, V]`` (k-major layout).\n Must be float32. Will be updated in-place.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``. Must be float32.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``. Must be bfloat16 or float32.\n b (torch.Tensor):\n Update gate (beta) input of shape ``[B, 1, HV]``. Must be float16/bfloat16.\n scale (Optional[float]):\n Scale factor for queries. If None, defaults to ``1 / sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, 1, HV, V]``.\n If None, will be allocated automatically.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, 1, HV, V]``\n - state: Updated state tensor of shape ``[B, HV, K, V]``\n\n Note:\n - Requires SM90 (Hopper) architecture\n - State is updated in-place\n - K and V must be multiples of 4 for vectorized loads\n - State layout is k-major: [B, HV, K, V] (no transpose needed)\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n assert T == 1, f\"Decode only supports T=1, got T={T}\"\n _, _, HV, V = v.shape\n\n # Validate state shape\n assert state.shape == (B, HV, K, V), (\n f\"Expected state shape [B={B}, HV={HV}, K={K}, V={V}], got {state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n # V must be divisible by tile size to prevent out-of-bounds access\n # For small batch: TILE_V_SMALL_NT=16, for large batch: TILE_V_NT=32\n # Use the more restrictive constraint (32) to cover both cases\n assert V % TILE_V_NT == 0, (\n f\"V must be divisible by {TILE_V_NT} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert state.dtype == torch.float32, f\"state must be float32, got {state.dtype}\"\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n # Kernel outputs bfloat16, allocate in that dtype first\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # State is already in K-major layout [B, HV, K, V]\n # Use state directly as pooled view: pool_size=B, each batch is its own pool\n h0_source = state.contiguous()\n\n # Create h0_indices: each batch points to its own pool index\n h0_indices = torch.arange(B, dtype=torch.int32, device=q.device)\n cu_seqlens = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (B, T, H, HV, K, V, q.dtype, scale, use_qk_l2norm)\n cache = _get_compiled_decode_kernel_nontranspose(*cache_key)\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Choose kernel based on batch size\n use_small_batch = B < SMALL_BATCH_THRESHOLD_NT\n\n if use_small_batch:\n run_func = run_gdn_decode_kernel_small_batch_nontranspose\n else:\n run_func = run_gdn_decode_kernel_big_batch_nontranspose\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(h0_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_func,\n cu_seqlens_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n a_tensor,\n b_tensor,\n A_log_tensor,\n dt_bias_tensor,\n h0_source_tensor,\n h0_indices_tensor,\n o_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n B=B,\n T=T,\n H=H,\n HV=HV,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n compiled(\n cu_seqlens,\n q,\n k,\n v,\n a,\n b,\n A_log,\n dt_bias,\n h0_source,\n h0_indices,\n output,\n stream,\n )\n\n # Copy state back (no sync needed - PyTorch handles stream ordering)\n # h0_source is already [B, HV, K, V]\n state.copy_(h0_source)\n\n # Convert output to target dtype if needed (kernel outputs bfloat16)\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, state\n\n\n# ============================================================================\n# MTP (Multiple Token Processing) Kernel - for T > 1 (verify mode)\n# ============================================================================\n\n\n@cute.kernel\ndef gdn_verify_kernel_mtp(\n tiled_copy_load: cute.TiledCopy,\n h0_source: cute.Tensor, # [pool_size * HV, V, K] - initial state pool (K-last)\n intermediate_states: cute.Tensor, # [pool_size * T * HV, V, K] - intermediate state cache\n smem_layout_staged: cute.ComposedLayout, # Swizzled layout to avoid bank conflicts\n vec_size: cutlass.Constexpr[int],\n num_v_tiles: cutlass.Constexpr[int],\n A_log: cute.Tensor, # [HV]\n a: cute.Tensor, # [B, T, HV]\n dt_bias: cute.Tensor, # [HV]\n q: cute.Tensor, # [B, T, H, K]\n k: cute.Tensor, # [B, T, H, K]\n v: cute.Tensor, # [B, T, HV, V]\n b: cute.Tensor, # [B, T, HV]\n o: cute.Tensor, # [B, T, HV, V] - output\n h0_indices: cute.Tensor, # [B] - initial state indices\n cu_seqlens: cute.Tensor, # [B+1] - cumulative sequence lengths (for varlen)\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n disable_state_update: cutlass.Constexpr[bool],\n cache_intermediate_states: cutlass.Constexpr[bool],\n):\n \"\"\"\n Verify kernel with optimized loop order: (v_tiles outer, time_steps inner)\n\n Uses cute.make_rmem_tensor for register arrays (same style as decode kernel).\n Store-compute overlap: cache data in registers, store during next iteration.\n \"\"\"\n\n tidx, _, _ = cute.arch.thread_idx()\n lane_id = tidx % 32\n warp_idx = cute.arch.warp_idx()\n warp_idx = cute.arch.make_warp_uniform(warp_idx)\n batch_idx, _, _ = cute.arch.block_idx()\n i_n = batch_idx // HV\n i_hv = batch_idx % HV\n i_h = i_hv // (HV // H)\n\n # Load A_log and dt_bias once (they don't vary with time)\n r_A_log = cutlass.Float32(A_log[i_hv])\n r_dt_bias = cutlass.Float32(dt_bias[i_hv])\n\n smem = cutlass.utils.SmemAllocator()\n\n # Allocate shared memory with padding to avoid bank conflicts\n sData = smem.allocate_tensor(cutlass.Float32, smem_layout_staged, 128)\n sOutput = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T, V)), 16)\n # Pre-computed shared memory for all time steps (with padding for bank conflict avoidance)\n sQ = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sK = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, K), stride=(K + 8, 1)), 16\n )\n sV = smem.allocate_tensor(\n cutlass.Float32, cute.make_layout((T, V), stride=(V + 8, 1)), 16\n )\n sG = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n sBeta = smem.allocate_tensor(cutlass.Float32, cute.make_layout((T,)), 16)\n\n # Allocate register tensors\n r_q = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_k = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n r_h = cute.make_rmem_tensor(\n cute.make_layout((vec_size,), stride=(1,)), cutlass.Float32\n )\n\n # Initialize output accumulator to zero\n for i_t in range(T):\n sOutput[(i_t, tidx)] = 0.0\n\n cute.arch.barrier()\n\n # Get initial state index for this batch\n cache_idx = h0_indices[i_n]\n\n # Early exit optimization: skip pre-computation for padding slots\n if cache_idx >= 0:\n # Pre-compute q, k, v, g, beta for all time steps (outside v_tiles loop)\n for i_t in range(T):\n # Load q, k into register arrays\n for i in range(vec_size):\n r_q[i] = cutlass.Float32(q[i_n, i_t, i_h, i * 32 + lane_id])\n r_k[i] = cutlass.Float32(k[i_n, i_t, i_h, i * 32 + lane_id])\n # Load v for all V elements\n sV[(i_t, i * 32 + lane_id)] = cutlass.Float32(\n v[i_n, i_t, i_hv, i * 32 + lane_id]\n )\n\n # Compute g and beta\n r_a = cutlass.Float32(a[i_n, i_t, i_hv])\n r_b = cutlass.Float32(b[i_n, i_t, i_hv])\n r_g = 0.0\n r_beta = 0.0\n if lane_id == 0:\n x = r_a + r_dt_bias\n beta_x = softplus_beta * x\n softplus_x = 0.0\n\n if beta_x <= softplus_threshold:\n exp_beta_x = cute.exp(beta_x)\n log_input = cutlass.Float32(1.0 + exp_beta_x)\n log_result = cutlass.Float32(cute.log(log_input))\n softplus_x = cutlass.Float32(\n (cutlass.Float32(1.0) / softplus_beta) * log_result\n )\n else:\n softplus_x = x\n\n r_g_value = -cute.exp(r_A_log) * softplus_x\n r_beta = 1.0 / (1.0 + cute.exp(-r_b))\n r_g = cute.exp(r_g_value)\n\n r_g = cute.arch.shuffle_sync(r_g, 0)\n r_beta = cute.arch.shuffle_sync(r_beta, 0)\n\n # Apply L2 normalization\n if use_qk_l2norm:\n sum_q = 0.0\n sum_k = 0.0\n for i in range(vec_size):\n sum_q += r_q[i] * r_q[i]\n sum_k += r_k[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_q += cute.arch.shuffle_sync_bfly(\n sum_q, offset=offset, mask=-1, mask_and_clamp=31\n )\n sum_k += cute.arch.shuffle_sync_bfly(\n sum_k, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n inv_norm_q = cute.rsqrt(sum_q + 1e-6)\n inv_norm_k = cute.rsqrt(sum_k + 1e-6)\n\n for i in range(vec_size):\n r_q[i] = r_q[i] * inv_norm_q\n r_k[i] = r_k[i] * inv_norm_k\n\n # Apply scaling to q\n for i in range(vec_size):\n r_q[i] = r_q[i] * scale\n\n # Store pre-computed values to shared memory\n for i in range(vec_size):\n sQ[(i_t, i * 32 + lane_id)] = r_q[i]\n sK[(i_t, i * 32 + lane_id)] = r_k[i]\n\n # Store g and beta (only one thread needs to do this)\n if tidx == 0:\n sG[i_t] = r_g\n sBeta[i_t] = r_beta\n\n # All threads must participate in barrier (CUDA requirement)\n cute.arch.barrier()\n\n # Main computation only for valid batch entries\n if cache_idx >= 0:\n # Setup source tensor for initial state loading\n gSrc_batch = h0_source[(cache_idx * HV + i_hv, None, None)]\n gDst_h0 = cute.local_tile(\n h0_source, (1, TILE_V_MTP, TILE_K_MTP), (cache_idx * HV + i_hv, None, 0)\n )\n gSrc = cute.local_tile(gSrc_batch, (TILE_V_MTP, TILE_K_MTP), (None, 0))\n\n thr_copy_load = tiled_copy_load.get_slice(tidx)\n\n # Main loop: v_tiles (outer) x time_steps (inner)\n prefetch_count = cutlass.min(NUM_STAGES_MTP - 1, num_v_tiles)\n\n # Prefetch first v_tile(s)\n for v_tiles in range(prefetch_count):\n stage = v_tiles % NUM_STAGES_MTP\n gSrc_tile = gSrc[(None, None, v_tiles)]\n sData_stage = sData[(None, None, stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_tile)\n thr_sData = thr_copy_load.partition_D(sData_stage)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Process each v_tile\n for v_tiles in range(num_v_tiles):\n stage = v_tiles % NUM_STAGES_MTP\n\n cute.arch.cp_async_wait_group(0)\n cute.arch.barrier()\n\n # Prefetch next v_tile\n next_v_tiles = v_tiles + prefetch_count\n if next_v_tiles < num_v_tiles:\n next_stage = next_v_tiles % NUM_STAGES_MTP\n gSrc_next = gSrc[(None, None, next_v_tiles)]\n sData_next = sData[(None, None, next_stage)]\n thr_gSrc = thr_copy_load.partition_S(gSrc_next)\n thr_sData = thr_copy_load.partition_D(sData_next)\n cute.copy(tiled_copy_load, thr_gSrc, thr_sData)\n cute.arch.cp_async_commit_group()\n\n # Inner loop: all time steps for this v_tile\n for i_t in range(T):\n # Load pre-computed values from shared memory\n for i in range(vec_size):\n r_q[i] = sQ[(i_t, i * 32 + lane_id)]\n r_k[i] = sK[(i_t, i * 32 + lane_id)]\n\n r_g = sG[i_t]\n r_beta = sBeta[i_t]\n\n # Compute delta rule for this v_tile\n for row in range(0, TILE_V_MTP, 4):\n row_offset = tidx // 32\n\n # Load h from sData, apply decay\n for i in range(vec_size):\n r_h[i] = (\n sData[(row + row_offset, i * 32 + lane_id, stage)] * r_g\n )\n\n # Compute sum_hk = h @ k\n sum_hk = 0.0\n for i in range(vec_size):\n sum_hk += r_h[i] * r_k[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hk += cute.arch.shuffle_sync_bfly(\n sum_hk, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n # Delta rule update\n v_idx = v_tiles * TILE_V_MTP + row + row_offset\n v_new = sV[(i_t, v_idx)] - sum_hk\n v_new = v_new * r_beta\n\n # Update h and write back to sData\n for i in range(vec_size):\n r_h[i] += r_k[i] * v_new\n sData[(row + row_offset, i * 32 + lane_id, stage)] = r_h[i]\n\n # Store intermediate state\n if cache_intermediate_states:\n flat_idx = i_n * T * HV + i_t * HV + i_hv\n if v_idx < V:\n for i in range(vec_size):\n intermediate_states[\n (flat_idx, v_idx, i * 32 + lane_id)\n ] = r_h[i]\n\n # Compute sum_hq = h @ q (overlaps with store above)\n sum_hq = 0.0\n for i in range(vec_size):\n sum_hq += r_h[i] * r_q[i]\n\n for offset in [16, 8, 4, 2, 1]:\n sum_hq += cute.arch.shuffle_sync_bfly(\n sum_hq, offset=offset, mask=-1, mask_and_clamp=31\n )\n\n o_idx = v_tiles * TILE_V_MTP + row + row_offset\n if lane_id == 0 and o_idx < V:\n sOutput[(i_t, o_idx)] = cutlass.Float32(sum_hq)\n\n # Write final h for this v_tile to h0_source\n if not disable_state_update:\n for row in range(0, TILE_V_MTP, 4):\n row_offset = tidx // 32\n for i in range(vec_size):\n gDst_h0[(0, row + row_offset, i * 32 + lane_id, v_tiles)] = (\n sData[(row + row_offset, i * 32 + lane_id, stage)]\n )\n\n # Final writeback\n cute.arch.barrier()\n\n for i_t in range(T):\n if tidx < V:\n o[(i_n, i_t, i_hv, tidx)] = cutlass.BFloat16(sOutput[(i_t, tidx)])\n\n\n@cute.jit\ndef run_gdn_verify_kernel_mtp(\n h0_source: cute.Tensor,\n intermediate_states: cute.Tensor,\n A_log: cute.Tensor,\n a: cute.Tensor,\n dt_bias: cute.Tensor,\n q: cute.Tensor,\n k: cute.Tensor,\n v: cute.Tensor,\n b: cute.Tensor,\n o: cute.Tensor,\n h0_indices: cute.Tensor,\n cu_seqlens: cute.Tensor,\n softplus_beta: cutlass.Constexpr[float],\n softplus_threshold: cutlass.Constexpr[float],\n scale: cutlass.Constexpr[float],\n HV: cutlass.Constexpr[int],\n B: cutlass.Constexpr[int],\n T: cutlass.Constexpr[int],\n H: cutlass.Constexpr[int],\n K: cutlass.Constexpr[int],\n V: cutlass.Constexpr[int],\n use_initial_state: cutlass.Constexpr[bool],\n use_qk_l2norm: cutlass.Constexpr[bool],\n is_varlen: cutlass.Constexpr[bool],\n disable_state_update: cutlass.Constexpr[bool],\n cache_intermediate_states: cutlass.Constexpr[bool],\n stream: cuda.CUstream,\n):\n _, v_dim, k_dim = (\n h0_source.layout.shape[0],\n h0_source.layout.shape[1],\n h0_source.layout.shape[2],\n )\n\n num_v_tiles = cute.ceil_div(v_dim, TILE_V_MTP)\n batch_size = B * HV\n vec_size = TILE_K_MTP // 32 # Each thread in a warp processes this many elements\n\n # Composed Swizzle Layout to avoid shared memory bank conflicts\n base_smem_layout = cute.make_layout(\n (TILE_V_MTP, TILE_K_MTP, NUM_STAGES_MTP),\n stride=(TILE_K_MTP, 1, TILE_V_MTP * TILE_K_MTP),\n )\n swizzle = cute.make_swizzle(2, 3, 7) # Swizzle<2, 3, 7>\n smem_layout_staged = cute.make_composed_layout(swizzle, 0, base_smem_layout)\n\n # Create tiled copy for G2S load\n copy_atom = cute.make_copy_atom(\n cpasync.CopyG2SOp(cache_mode=cpasync.LoadCacheMode.GLOBAL),\n cutlass.Float32,\n num_bits_per_copy=128,\n )\n thread_layout = cute.make_layout((4, 32), stride=(32, 1))\n val_layout = cute.make_layout((1, 4))\n tiled_copy_load = cute.make_tiled_copy_tv(copy_atom, thread_layout, val_layout)\n\n # Calculate shared memory size\n smem_bytes = (\n 4 * TILE_V_MTP * TILE_K_MTP * NUM_STAGES_MTP\n + 4 * T * v_dim\n + 4 * T * (k_dim + 8)\n + 4 * T * (k_dim + 8)\n + 4 * T * (v_dim + 8)\n + 4 * T\n + 4 * T\n + 128\n )\n\n gdn_verify_kernel_mtp(\n tiled_copy_load,\n h0_source,\n intermediate_states,\n smem_layout_staged,\n vec_size,\n num_v_tiles,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n o,\n h0_indices,\n cu_seqlens,\n softplus_beta,\n softplus_threshold,\n scale,\n HV,\n B,\n T,\n H,\n K,\n V,\n use_initial_state,\n use_qk_l2norm,\n is_varlen,\n disable_state_update,\n cache_intermediate_states,\n ).launch(\n grid=(batch_size, 1, 1),\n block=[NUM_THREADS_MTP, 1, 1],\n smem=smem_bytes,\n stream=stream,\n )\n\n\n@functools.cache\ndef _get_compiled_mtp_kernel(\n B: int,\n T: int,\n H: int,\n HV: int,\n K: int,\n V: int,\n pool_size: int,\n cache_steps: int,\n disable_state_update: bool,\n cache_intermediate_states: bool,\n scale: float,\n use_qk_l2norm: bool,\n):\n \"\"\"Cache compiled MTP kernel for given configuration.\"\"\"\n return {}\n\n\n@flashinfer_api\ndef gated_delta_rule_mtp(\n q: torch.Tensor,\n k: torch.Tensor,\n v: torch.Tensor,\n initial_state: torch.Tensor,\n initial_state_indices: torch.Tensor,\n A_log: torch.Tensor,\n a: torch.Tensor,\n dt_bias: torch.Tensor,\n b: torch.Tensor,\n scale: Optional[float] = None,\n output: Optional[torch.Tensor] = None,\n intermediate_states_buffer: Optional[torch.Tensor] = None,\n disable_state_update: bool = True,\n use_qk_l2norm: bool = True,\n) -> Tuple[torch.Tensor, torch.Tensor]:\n \"\"\"\n Gated Delta Rule MTP Kernel (Multiple Token Processing).\n\n This function processes multiple tokens (T > 1) in sequence, typically used for\n speculative decoding verification. It supports intermediate state caching for\n potential rollback scenarios.\n\n Args:\n q (torch.Tensor):\n Query tensor of shape ``[B, T, H, K]``.\n k (torch.Tensor):\n Key tensor of shape ``[B, T, H, K]``.\n v (torch.Tensor):\n Value tensor of shape ``[B, T, HV, V]``.\n initial_state (torch.Tensor):\n Initial state tensor of shape ``[pool_size, HV, V, K]`` (K-last layout).\n initial_state_indices (torch.Tensor):\n Indices mapping each batch to its initial state, shape ``[B]``.\n A_log (torch.Tensor):\n Log decay parameter of shape ``[HV]``.\n a (torch.Tensor):\n Input-dependent decay of shape ``[B, T, HV]``.\n dt_bias (torch.Tensor):\n Decay bias of shape ``[HV]``.\n b (torch.Tensor):\n Update gate input of shape ``[B, T, HV]``.\n scale (Optional[float]):\n Scaling factor for queries. If None, uses ``1/sqrt(K)``.\n output (Optional[torch.Tensor]):\n Pre-allocated output tensor of shape ``[B, T, HV, V]``.\n intermediate_states_buffer (Optional[torch.Tensor]):\n Buffer for caching intermediate states, shape ``[pool_size, T, HV, V, K]``.\n If None, intermediate states are not cached.\n disable_state_update (bool):\n If True, the initial state is not updated. Default: ``True``.\n use_qk_l2norm (bool):\n Whether to apply L2 normalization to q and k. Default: ``True``.\n\n Returns:\n Tuple[torch.Tensor, torch.Tensor]:\n - output: Output tensor of shape ``[B, T, HV, V]``\n - initial_state: Updated state tensor (unchanged if disable_state_update=True)\n\n Note:\n - Requires SM90 (Hopper) architecture\n - Supports T > 1 (multiple token processing)\n - State layout is K-last: [pool_size, HV, V, K]\n - Optimized for speculative decoding verification scenarios\n \"\"\"\n # Validate input shapes\n B, T, H, K = q.shape\n _, _, HV, V = v.shape\n pool_size = initial_state.shape[0]\n\n # Validate state shape\n assert initial_state.shape == (pool_size, HV, V, K), (\n f\"Expected initial_state shape [pool_size={pool_size}, HV={HV}, V={V}, K={K}], got {initial_state.shape}\"\n )\n\n # Validate K and V constraints\n assert K >= 128, f\"K must be at least 128, got K={K}\"\n assert V >= 128, f\"V must be at least 128, got V={V}\"\n assert V % TILE_V_MTP == 0, (\n f\"V must be divisible by {TILE_V_MTP} to prevent out-of-bounds access, got V={V}\"\n )\n\n # Validate dtypes\n assert q.dtype in (torch.float16, torch.bfloat16), (\n f\"q must be float16/bfloat16, got {q.dtype}\"\n )\n assert initial_state.dtype == torch.float32, (\n f\"initial_state must be float32, got {initial_state.dtype}\"\n )\n assert A_log.dtype == torch.float32, f\"A_log must be float32, got {A_log.dtype}\"\n\n # Set default scale\n if scale is None:\n scale = K**-0.5\n\n # Allocate output if not provided\n output_provided = output is not None\n target_dtype = output.dtype if output_provided else q.dtype\n\n if output is None:\n output = torch.zeros((B, T, HV, V), dtype=torch.bfloat16, device=q.device)\n\n # Reshape initial_state from [pool_size, HV, V, K] to [pool_size * HV, V, K]\n h0_source = initial_state.to(torch.float32).reshape(pool_size * HV, V, K)\n\n # Handle intermediate states\n cache_intermediate_states = intermediate_states_buffer is not None\n if cache_intermediate_states:\n buffer_size = intermediate_states_buffer.shape[0]\n cache_steps = intermediate_states_buffer.shape[1]\n\n # Validate buffer length matches query sequence length\n assert cache_steps >= T, (\n f\"intermediate_states_buffer second dimension (cache_steps={cache_steps}) must be at least T={T} to prevent out-of-bounds indexing\"\n )\n\n intermediate_states = (\n intermediate_states_buffer.to(torch.float32)\n .reshape(buffer_size * cache_steps * HV, V, K)\n .contiguous()\n )\n else:\n cache_steps = T\n intermediate_states = torch.zeros(1, 1, 1, dtype=torch.float32, device=q.device)\n\n # Create cu_seqlens\n cu_seqlens = torch.zeros(B + 1, dtype=torch.int32, device=q.device)\n\n # Compile kernel with TVM FFI (cached)\n cache_key = (\n B,\n T,\n H,\n HV,\n K,\n V,\n pool_size,\n cache_steps,\n disable_state_update,\n cache_intermediate_states,\n scale,\n use_qk_l2norm,\n )\n cache = _get_compiled_mtp_kernel(*cache_key)\n\n if \"compiled\" not in cache:\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n # Convert tensors to CuTe format for compilation only\n h0_source_tensor = from_dlpack(h0_source, assumed_align=16)\n intermediate_states_tensor = from_dlpack(intermediate_states, assumed_align=16)\n A_log_tensor = from_dlpack(A_log, assumed_align=16)\n a_tensor = from_dlpack(a, assumed_align=16)\n dt_bias_tensor = from_dlpack(dt_bias, assumed_align=16)\n q_tensor = from_dlpack(q, assumed_align=16)\n k_tensor = from_dlpack(k, assumed_align=16)\n v_tensor = from_dlpack(v, assumed_align=16)\n b_tensor = from_dlpack(b, assumed_align=16)\n o_tensor = from_dlpack(output, assumed_align=16)\n h0_indices_tensor = from_dlpack(initial_state_indices, assumed_align=16)\n cu_seqlens_tensor = from_dlpack(cu_seqlens, assumed_align=16)\n\n # Use TVM FFI to reduce runtime overhead\n compiled = cute.compile(\n run_gdn_verify_kernel_mtp,\n h0_source_tensor,\n intermediate_states_tensor,\n A_log_tensor,\n a_tensor,\n dt_bias_tensor,\n q_tensor,\n k_tensor,\n v_tensor,\n b_tensor,\n o_tensor,\n h0_indices_tensor,\n cu_seqlens_tensor,\n softplus_beta=1.0,\n softplus_threshold=20.0,\n scale=scale,\n HV=HV,\n B=B,\n T=T,\n H=H,\n K=K,\n V=V,\n use_initial_state=True,\n use_qk_l2norm=use_qk_l2norm,\n is_varlen=False,\n disable_state_update=disable_state_update,\n cache_intermediate_states=cache_intermediate_states,\n stream=stream,\n options=\"--enable-tvm-ffi\",\n )\n cache[\"compiled\"] = compiled\n else:\n compiled = cache[\"compiled\"]\n\n # Run kernel directly with PyTorch tensors (no from_dlpack needed)\n stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n compiled(\n h0_source,\n intermediate_states,\n A_log,\n a,\n dt_bias,\n q,\n k,\n v,\n b,\n output,\n initial_state_indices,\n cu_seqlens,\n stream,\n )\n\n # Copy state back if needed (no sync needed - PyTorch handles stream ordering)\n if not disable_state_update:\n initial_state.copy_(h0_source.reshape(pool_size, HV, V, K))\n\n # Convert output to target dtype if needed\n if output.dtype != target_dtype:\n output = output.to(target_dtype)\n\n return output, initial_state\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nFollow up of #2370 , this PR improves the benchmark scripts and add comparison with baselines:\n* benchmark using cupti with l2 flush\n* compare with sglang's `fused_sigmoid_gating_delta_rule_update` function (with tile size optimization mentioned by @ vadiklyutiy).\n\nthis PR also implements some optimizations on the original gdn kernel:\n* use fastmath as much as we can\n* change \"/\" to multiply\n* Use `cutlass.range_constexpr` and `cutlass.const_expr` whenever possible\n* fuse scale and inv_norm_q\n* For mtp, store state in registers directly, without load/write to shared memory, and remove cpasync\n* Vectorized memory access.\n\n## Performance on B200\n\nNon MTP setting\n```\n> python benchmarks/bench_gdn_decode.py --batch-size 1 2 4 8 16 32 64 128 256 --compare --verify\n\n=== Correctness Verification ===\nBatch=8:\n Pretranspose: PASS\n Nontranspose: PASS\nBatch=16:\n Pretranspose: PASS\n Nontranspose: PASS\nBatch=32:\n Pretranspose: PASS\n Nontranspose: PASS\nBatch=64:\n Pretranspose: PASS\n Nontranspose: PASS\n\n\n========================================================================================================================\nGDN Decode Benchmark: FlashInfer vs Triton, Pretranspose vs Nontranspose\nConfig: q_heads=16, k_heads=16, v_heads=32, head_size=128, dtype=bfloat16, qk_l2norm=ON\n========================================================================================================================\n\n batch | FI-PreTr FI-NonTr | TR-PreTr TR-NonTr | FI/TR-Pre FI/TR-Non | Pre/Non-FI Pre/Non-TR\n | (us) (us) | (us) (us) | speedup speedup | speedup speedup\n------------------------------------------------------------------------------------------------------------------------\n 1 | 3.74 5.06 | 5.95 4.35 | 1.59x 0.86x | 1.35x 0.73x\n 2 | 4.29 5.89 | 6.37 5.02 | 1.49x 0.85x | 1.37x 0.79x\n 4 | 5.41 7.78 | 7.58 6.66 | 1.40x 0.86x | 1.44x 0.88x\n 8 | 7.65 12.03 | 9.95 10.21 | 1.30x 0.85x | 1.57x 1.03x\n 16 | 12.61 19.30 | 16.83 15.81 | 1.34x 0.82x | 1.53x 0.94x\n 32 | 22.91 32.86 | 31.55 27.84 | 1.38x 0.85x | 1.43x 0.88x\n 64 | 52.74 58.61 | 58.91 53.02 | 1.12x 0.90x | 1.11x 0.90x\n 128 | 92.93 107.98 | 114.45 106.78 | 1.23x 0.99x | 1.16x 0.93x\n 256 | 170.77 209.04 | 225.71 216.41 | 1.32x 1.04x | 1.22x 0.96x\n------------------------------------------------------------------------------------------------------------------------\n\nLegend:\n FI-PreTr = FlashInfer Pretranspose [B, HV, V, K]\n FI-NonTr = FlashInfer Nontranspose [B, HV, K, V]\n TR-PreTr = Triton Pretranspose [B, HV, V, K]\n TR-NonTr = Triton Nontranspose [B, HV, K, V]\n FI/TR speedup > 1.0 means FlashInfer is faster than Triton\n Pre/Non speedup > 1.0 means Pretranspose is faster than Nontranspose\n\nFlashInfer vs Triton (Pretranspose) - Average speedup: 1.35x\n```\n\nMTP Setting (pretranspose only)\n```\n> python benchmarks/bench_gdn_decode.py --version mtp --batch-size 1 2 4 8 16 32 64 128 256 --compare --verify\n\n=== Correctness Verification (MTP) ===\nBatch=8: PASS\nBatch=16: PASS\nBatch=32: PASS\nBatch=64: PASS\n\n\nGDN MTP Comparison: FlashInfer (CuTe DSL) vs Triton\nConfig: q_heads=16, k_heads=16, v_heads=32, head_size=128, dtype=bfloat16, qk_l2norm=ON, cache_intermediate=OFF\n--------------------------------------------------------------------------------------------------------------\n batch seq_len FlashInfer(us) Triton(us) FI TFLOPS TR TFLOPS Speedup\n--------------------------------------------------------------------------------------------------------------\n 1 2 9.22 10.05 0.68 0.63 1.09x\n 1 4 11.20 14.43 1.12 0.87 1.29x\n 1 8 15.81 22.08 1.59 1.14 1.40x\n 2 2 10.11 10.69 1.24 1.18 1.06x\n 2 4 12.58 15.10 2.00 1.67 1.20x\n 2 8 18.82 23.63 2.67 2.13 1.26x\n 4 2 11.39 11.94 2.21 2.11 1.05x\n 4 4 15.23 16.54 3.30 3.04 1.09x\n 4 8 23.62 25.50 4.26 3.95 1.08x\n 8 2 14.69 17.23 3.43 2.92 1.17x\n 8 4 21.20 25.01 4.75 4.03 1.18x\n 8 8 34.69 40.86 5.80 4.93 1.18x\n 16 2 21.47 24.22 4.69 4.16 1.13x\n 16 4 32.54 36.98 6.19 5.44 1.14x\n 16 8 56.24 61.76 7.16 6.52 1.10x\n 32 2 33.50 37.68 6.01 5.34 1.12x\n 32 4 54.66 60.26 7.37 6.68 1.10x\n 32 8 97.98 104.35 8.22 7.72 1.06x\n 64 2 59.82 65.38 6.73 6.16 1.09x\n 64 4 102.05 108.83 7.89 7.40 1.07x\n 64 8 188.17 196.45 8.56 8.20 1.04x\n 128 2 107.44 121.41 7.50 6.63 1.13x\n 128 4 192.01 209.90 8.39 7.67 1.09x\n 128 8 366.81 389.12 8.78 8.28 1.06x\n 256 2 199.14 236.19 8.09 6.82 1.19x\n 256 4 363.36 422.61 8.87 7.62 1.16x\n 256 8 708.22 787.05 9.10 8.19 1.11x\n--------------------------------------------------------------------------------------------------------------\nSpeedup > 1.0 means FlashInfer is faster\n\nSummary:\n Average speedup: 1.13x\n Min speedup: 1.04x (batch=64, T=8)\n Max speedup: 1.40x (batch=1, T=8)\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added Triton-based benchmarks and end-to-end comparison/verify modes across multiple memory layouts (including MTP); new verification flows to compare implementations.\n* **Performance Improvements**\n * Batch-size-aware kernel selection, configurable tile/vec sizing, fast-math paths, reduced redundant copies, and CUPTI-backed GPU timing for more accurate benchmarks.\n* **Behavior & Compatibility**\n * Improved layout handling, expanded CLI presets/modes, clearer error messages and guards when Triton is unavailable; default benchmark mode updated.\n* **Documentation**\n * Updated usage examples and CLI guidance.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128,dtype=bfloat16\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 5.95, \"optimized\": 3.74, \"stated_speedup\": null, \"speedup\": 1.5909}, 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\"q_heads=16,k_heads=16,v_heads=32,head_size=128,dtype=bfloat16\", \"batch_size\": 128, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 209.9, \"optimized\": 192.01, \"stated_speedup\": 1.09, \"speedup\": 1.0932}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128,dtype=bfloat16\", \"batch_size\": 128, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 389.12, \"optimized\": 366.81, \"stated_speedup\": 1.06, \"speedup\": 1.0608}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128,dtype=bfloat16\", \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 236.19, \"optimized\": 199.14, \"stated_speedup\": 1.19, \"speedup\": 1.1861}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128,dtype=bfloat16\", \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 422.61, \"optimized\": 363.36, \"stated_speedup\": 1.16, \"speedup\": 1.1631}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"q_heads=16,k_heads=16,v_heads=32,head_size=128,dtype=bfloat16\", \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 787.05, \"optimized\": 708.22, \"stated_speedup\": 1.11, \"speedup\": 1.1113}]"},"kernel_speedup":{"kind":"number","value":1.1332,"string":"1.1332"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1186,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"c7761add6e6b7703ce5f12b03be387e78048f36b"},"date":{"kind":"string","value":"2026-02-03T05:57:24+01:00"},"pr_number":{"kind":"number","value":2303,"string":"2,303"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2303"},"title":{"kind":"string","value":"[Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels (#2303)"},"message":{"kind":"string","value":"[Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels (#2303)\n\n## Summary\n\nThis PR adds new template specializations for SM103 NVFP4 CUTLASS GEMM\nkernels using architecture-specific tile shapes, cluster shapes, and\nschedulers.\n\n## Motivation\n\nSM103 specifications show a higher NVFP4-over-BF16 speedup ratio than\nB200 (6× vs. 4×), but current kernels remain far from this limit.\nThis PR introduces SM103-optimized templates to improve the achieved\nperformance on this architecture.\n\nThe performance gains are more pronounced at larger batch sizes, while\nthe previous SM100 configurations remain preferable in other cases.\nFor this reason, SM103-specific configurations were added alongside the\nexisting ones rather than replacing them, and the optimal configuration\nis automatically selected as part of the autotuning process.\n\n## Performance results examples\n\nLlama-3.1-70B, N=8192 K=28672, BF16 vs NVFP4 GEMMs TFLOP/s:\n\n| Batch Size | Torch BF16 | NVFP4 Before | NVFP4 After |\n|-----------:|-----------:|-------------:|------------:|\n| 8 | 50.418336 | 110.598008 | 124.005817 |\n| 16 | 99.350151 | 219.649654 | 260.502226 |\n| 32 | 193.884850 | 445.840601 | 519.291059 |\n| 64 | 385.790757 | 978.451544 | 1011.614080 |\n| 128 | 692.915989 | 2072.797941 | 2076.017433 |\n| 256 | 1211.413202| 3817.738538 | 3868.924511 |\n| 512 | 1464.015616| 5141.532768 | 5503.664311 |\n| 1024 | 1600.983748| 5659.831320 | 6341.013002 |\n| 2048 | 1625.639619| 5991.840134 | 6630.757403 |\n| 4096 | 1602.978834| 6160.806595 | 6898.878407 |\n| 8192 | 1691.174722| 5939.220913 | 6653.915111 |\n| 16384 | 1688.224044| 5926.519222 | 6595.387600 |\n| 24576 | 1706.774619| 5905.301100 | 6617.486211 |\n| 32768 | 1678.225402| 5913.806010 | 6592.762922 |\n\n---\n\nLlama-3.1-70B, N=8192 K=8192, BF16 vs NVFP4 GEMMs TFLOP/s:\n\n| Batch Size | Torch BF16 | NVFP4 Before | NVFP4 After |\n\n|-----------:|-----------:|--------------------------:|--------------------------:|\n| 8 | 47.780647 | 124.774241 | 124.760324 |\n| 16 | 95.671633 | 249.502165 | 249.131125 |\n| 32 | 189.224266 | 497.991489 | 497.277802 |\n| 64 | 373.320912 | 993.731451 | 989.446041 |\n| 128 | 707.096994 | 1959.258553 | 1970.430179 |\n| 256 | 1126.908748| 4037.558967 | 4159.515720 |\n| 512 | 1407.884777| 5045.981883 | 4958.698763 |\n| 1024 | 1491.747576| 5654.694949 | 5614.133004 |\n| 2048 | 1546.322959| 5898.291400 | 6204.813491 |\n| 4096 | 1610.656216| 6312.498418 | 6605.534723 |\n| 8192 | 1623.748353| 6392.424296 | 6803.660138 |\n| 16384 | 1627.947338| 6438.789701 | 6947.466217 |\n| 24576 | 1614.582791| 6469.307368 | 6991.331576 |\n| 32768 | 1617.601164| 6515.312895 | 7010.746651 |\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* Added support for NVIDIA SM103 GPU architecture in FP4 operations with\nspecialized kernel configurations and optimized launcher\nimplementations, extending hardware compatibility and enabling efficient\ncomputation on additional GPU variants.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review\nsettings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nSigned-off-by: LopezCastroRoberto <robertol.c510@gmail.com>\nCo-authored-by: yzh119 <zihaoy@nvidia.com>"},"path":{"kind":"string","value":"include/flashinfer/gemm/cutlass_gemm_configs.h"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n#define FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n\n#include <cassert>\n#include <iostream>\n#include <sstream>\n#include <string>\n\n#include \"cute/tensor.hpp\"\n\nnamespace flashinfer {\nnamespace gemm {\n\n// Note: The shapes are in the format MxNxK. The K shape of the runtime config MUST match the K\n// shape\n// in the kernel layout details when doing weight only quantization.\nenum class CutlassTileConfig {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n // SiMT config\n CtaShape128x128x8_WarpShape64x64x8,\n\n // TensorCore configs CTA_N = 128, CTA_K = 64\n // Warp configs for M=16\n CtaShape16x128x64_WarpShape16x32x64,\n // Warp configs for M=32\n CtaShape32x128x64_WarpShape32x32x64,\n\n // Warp configs for M=64\n CtaShape64x128x64_WarpShape32x64x64,\n CtaShape64x64x128_WarpShape32x64x64,\n CtaShape64x128x64_WarpShape64x32x64,\n\n // Warp configs for M=128\n CtaShape128x64x64_WarpShape64x32x64,\n CtaShape128x128x64_WarpShape64x32x64,\n CtaShape128x128x64_WarpShape64x64x64,\n CtaShape128x128x64_WarpShape128x32x64,\n CtaShape128x256x64_WarpShape64x64x64,\n\n // Warp configs for M=256\n CtaShape256x128x64_WarpShape64x64x64,\n\n // TensorCore config CTA_N = 64, CTA_K = 128\n CtaShape128x64x128_WarpShape64x32x128,\n\n // TensorCore config CTA_N = 256, CTA_K = 64\n CtaShape16x256x64_WarpShape16x64x64,\n\n // TensorCore config CTA_N = 256, CTA_K = 128\n CtaShape16x256x128_WarpShape16x64x128\n\n};\n\nenum class SplitKStyle {\n NO_SPLIT_K,\n SPLIT_K_SERIAL,\n STREAM_K, // Sm80+\n // SPLIT_K_PARALLEL // Not supported yet\n};\n\nenum class CutlassTileConfigSM90 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n // CTA configs for M=64\n CtaShape64x16x128B,\n CtaShape64x32x128B,\n CtaShape64x64x128B,\n CtaShape64x128x128B,\n CtaShape64x256x128B,\n\n // CTA configs for M=128\n CtaShape128x16x128B,\n CtaShape128x32x128B,\n CtaShape128x64x128B,\n CtaShape128x128x128B,\n CtaShape128x256x128B,\n\n // CTA configs for M=128\n CtaShape256x128x128B,\n};\n\nenum class CutlassTileConfigSM100 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n /*\n * Grouped GEMM\n */\n // M=64\n CtaShape64x32x128B,\n CtaShape64x64x128B,\n CtaShape64x128x128B,\n CtaShape64x256x128B,\n\n // M=128\n CtaShape128x8x256B,\n CtaShape128x16x128B,\n CtaShape128x32x128B,\n CtaShape128x64x128B,\n CtaShape128x128x128B,\n CtaShape128x256x128B,\n CtaShape128x128x256B,\n CtaShape128x256x256B,\n\n // M=256\n CtaShape256x64x128B,\n CtaShape256x128x128B,\n CtaShape256x256x128B,\n};\n\nenum class CutlassTileConfigSM120 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n CtaShape128x128x128B,\n CtaShape128x128x64B,\n CtaShape256x128x64B,\n CtaShape128x256x64B,\n CtaShape128x128x256B,\n CtaShape256x128x128B,\n};\n\nenum class MainloopScheduleType {\n AUTO, // Automatically selects between pingpong and cooperative schedules on Hopper. On older\n // architectures, this defaults to the \"legacy\" main loop schedule.\n PINGPONG,\n COOPERATIVE,\n WARPSPECIALIZED\n};\n\nstatic auto get_mainloop_schedule_name(MainloopScheduleType schedule) {\n if (schedule == MainloopScheduleType::AUTO) {\n return \"auto\";\n } else if (schedule == MainloopScheduleType::PINGPONG) {\n return \"pingpong\";\n } else if (schedule == MainloopScheduleType::COOPERATIVE) {\n return \"cooperative\";\n } else if (schedule == MainloopScheduleType::WARPSPECIALIZED) {\n return \"warpspecialized\";\n }\n return \"unknown schedule\";\n}\n\nenum class EpilogueScheduleType {\n AUTO, // Automatically chooses an epilogue schedule compatible with the selected main loop\n // schedule for Hopper. For architectures older than hopper, the epilogue is always\n // performed by the same thread block as the main loop.\n};\n\nenum class TileShape {\n TileShape_64x16x128,\n TileShape_64x32x128,\n TileShape_64x64x128,\n TileShape_64x128x128,\n TileShape_64x256x128,\n TileShape_64x512x128,\n TileShape_128x16x128,\n TileShape_128x32x128,\n TileShape_128x64x128,\n TileShape_128x128x128,\n TileShape_128x256x128\n};\n\ntemplate <TileShape Shape_MNK>\nconstexpr auto get_tile_shape() {\n using namespace cute;\n if constexpr (Shape_MNK == TileShape::TileShape_64x16x128) {\n return cute::Shape<_64, _16, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x32x128) {\n return cute::Shape<_64, _32, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x64x128) {\n return cute::Shape<_64, _64, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x128x128) {\n return cute::Shape<_64, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x256x128) {\n return cute::Shape<_64, _256, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x512x128) {\n return cute::Shape<_64, _512, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x16x128) {\n return cute::Shape<_128, _16, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x32x128) {\n return cute::Shape<_128, _32, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x64x128) {\n return cute::Shape<_128, _64, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x128x128) {\n return cute::Shape<_128, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x256x128) {\n return cute::Shape<_128, _256, _128>{};\n }\n}\n\nstatic auto get_tile_shape_name(TileShape Shape_MNK) {\n if (Shape_MNK == TileShape::TileShape_64x16x128) {\n return \"64x16x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x32x128) {\n return \"64x32x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x64x128) {\n return \"64x64x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x128x128) {\n return \"64x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x256x128) {\n return \"64x256x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x512x128) {\n return \"64x512x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x16x128) {\n return \"128x16x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x32x128) {\n return \"128x32x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x64x128) {\n return \"128x64x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x128x128) {\n return \"128x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x256x128) {\n return \"128x256x128\";\n }\n return \"Unknown shape\";\n}\n\nenum class ClusterShape {\n ClusterShape_1x1x1,\n ClusterShape_2x1x1,\n ClusterShape_1x2x1,\n ClusterShape_2x2x1,\n ClusterShape_1x4x1,\n ClusterShape_4x2x1,\n ClusterShape_2x4x1,\n ClusterShape_4x4x1,\n ClusterShape_1x8x1,\n ClusterShape_8x1x1\n};\n\nstatic auto get_cluster_shape_name(ClusterShape Shape_MNK) {\n if (Shape_MNK == ClusterShape::ClusterShape_1x1x1) {\n return \"1x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_2x1x1) {\n return \"2x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_1x2x1) {\n return \"1x2x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_2x2x1) {\n return \"2x2x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_1x8x1) {\n return \"1x8x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return \"8x1x1\";\n }\n return \"Unknown shape\";\n}\n\ntemplate <ClusterShape Shape_MNK>\nconstexpr auto get_cluster_shape() {\n using namespace cute;\n if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x1x1) {\n return cute::Shape<_1, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_2x1x1) {\n return cute::Shape<_2, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x2x1) {\n return cute::Shape<_1, _2, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_2x2x1) {\n return cute::Shape<_2, _2, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x8x1) {\n return cute::Shape<_1, _8, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return cute::Shape<_8, _1, _1>{};\n }\n}\n\nstruct CutlassGemmConfig {\n enum CandidateConfigTypeParam : int {\n NONE = 0,\n WEIGHT_ONLY = 1u << 0,\n SIMT_ONLY = 1u << 1,\n INT8_ONLY = 1u << 2,\n HOPPER = 1u << 3,\n BLACKWELL = 1u << 4,\n GROUPED_GEMM = 1u << 5,\n FP8_ONLY = 1u << 6,\n FP4_ONLY = 1u << 7\n };\n\n CutlassTileConfig tile_config_sm80 = CutlassTileConfig::ChooseWithHeuristic;\n SplitKStyle split_k_style = SplitKStyle::NO_SPLIT_K;\n int split_k_factor = -1;\n int stages = -1;\n\n // config options for sm90\n CutlassTileConfigSM90 tile_config_sm90 = CutlassTileConfigSM90::ChooseWithHeuristic;\n CutlassTileConfigSM100 tile_config_sm100 = CutlassTileConfigSM100::ChooseWithHeuristic;\n CutlassTileConfigSM120 tile_config_sm120 = CutlassTileConfigSM120::ChooseWithHeuristic;\n MainloopScheduleType mainloop_schedule = MainloopScheduleType::AUTO;\n EpilogueScheduleType epilogue_schedule = EpilogueScheduleType::AUTO;\n ClusterShape cluster_shape = ClusterShape::ClusterShape_1x1x1;\n bool enableCudaKernel = false;\n int sm_version = 80; // Use 80 as a catch all for <90\n bool is_tma_warp_specialized = false;\n\n CutlassGemmConfig() = default;\n\n CutlassGemmConfig(CutlassTileConfig tile_config, SplitKStyle split_k_style, int split_k_factor,\n int stages)\n : tile_config_sm80(tile_config),\n split_k_style(split_k_style),\n split_k_factor(split_k_factor),\n stages(stages),\n sm_version(80) {}\n\n CutlassGemmConfig(CutlassTileConfigSM90 tile_config_sm90, MainloopScheduleType mainloop_schedule,\n EpilogueScheduleType epilogue_schedule, ClusterShape cluster_shape)\n : tile_config_sm90(tile_config_sm90),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(90),\n is_tma_warp_specialized(true) {}\n\n CutlassGemmConfig(CutlassTileConfigSM100 tile_config_sm100,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n ClusterShape cluster_shape)\n : tile_config_sm100(tile_config_sm100),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(100),\n is_tma_warp_specialized(true) {}\n\n CutlassGemmConfig(CutlassTileConfigSM120 tile_config_sm120,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n ClusterShape cluster_shape)\n : tile_config_sm120(tile_config_sm120),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(120),\n is_tma_warp_specialized(true) {}\n\n int getTileConfigAsInt() const {\n if (sm_version == 120) return (int)tile_config_sm120;\n if (sm_version == 110) return (int)tile_config_sm100;\n if (sm_version >= 100) return (int)tile_config_sm100;\n if (sm_version == 90) return (int)tile_config_sm90;\n if (sm_version < 90) return (int)tile_config_sm80;\n assert(false && \"Invalid SM version\");\n return -1;\n }\n\n std::string toString() const {\n std::stringstream tactic;\n tactic << \"Cutlass GEMM Tactic\";\n if (is_tma_warp_specialized) {\n assert(sm_version >= 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=TMA Warp Specialized\"\n << \"\\n\\tsm: \" << sm_version << \"\\n\\ttile shape ID: \" << getTileConfigAsInt()\n << \"\\n\\tcluster shape ID: \" << (int)cluster_shape\n << \"\\n\\tmainloop sched: \" << (int)mainloop_schedule\n << \"\\n\\tepi sched: \" << (int)epilogue_schedule\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else if (tile_config_sm80 != flashinfer::gemm::CutlassTileConfig::ChooseWithHeuristic) {\n assert(sm_version < 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=compatible\"\n << \"\\n\\ttile shape ID: \" << (int)tile_config_sm80 << \"\\n\\tstages: \" << (int)stages\n << \"\\n\\tsplit k: \" << (int)split_k_factor\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else if (enableCudaKernel) {\n tactic << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else {\n tactic << \"\\n\\tundefined\";\n }\n tactic << \"\\n\";\n return tactic.str();\n }\n};\n\ninline std::ostream& operator<<(std::ostream& out, CutlassGemmConfig const& config) {\n // clang-format off\n if (config.is_tma_warp_specialized)\n {\n out << \"tile_config_sm90_enum: \" << config.getTileConfigAsInt()\n << \", mainloop_schedule_enum: \" << int(config.mainloop_schedule)\n << \", epilogue_schedule_enum: \" << int(config.epilogue_schedule)\n << \", cluster_shape_enum: \" << int(config.cluster_shape)\n << \", enable_cuda_kernel: \" << (config.enableCudaKernel ? \"true\" : \"false\");\n }\n else\n {\n out << \"tile_config_enum: \" << config.getTileConfigAsInt()\n << \", split_k_style_enum: \" << int(config.split_k_style)\n << \", split_k_factor: \" << config.split_k_factor\n << \", stages: \" << config.stages\n << \", enable_cuda_kernel: \" << (config.enableCudaKernel ? \"true\" : \"false\");\n }\n // clang-format on\n return out;\n}\n\n} // namespace gemm\n} // namespace flashinfer\n#endif // FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n#define FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n\n#include <cassert>\n#include <iostream>\n#include <sstream>\n#include <string>\n\n#include \"cute/tensor.hpp\"\n\nnamespace flashinfer {\nnamespace gemm {\n\n// Note: The shapes are in the format MxNxK. The K shape of the runtime config MUST match the K\n// shape\n// in the kernel layout details when doing weight only quantization.\nenum class CutlassTileConfig {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n // SiMT config\n CtaShape128x128x8_WarpShape64x64x8,\n\n // TensorCore configs CTA_N = 128, CTA_K = 64\n // Warp configs for M=16\n CtaShape16x128x64_WarpShape16x32x64,\n // Warp configs for M=32\n CtaShape32x128x64_WarpShape32x32x64,\n\n // Warp configs for M=64\n CtaShape64x128x64_WarpShape32x64x64,\n CtaShape64x64x128_WarpShape32x64x64,\n CtaShape64x128x64_WarpShape64x32x64,\n\n // Warp configs for M=128\n CtaShape128x64x64_WarpShape64x32x64,\n CtaShape128x128x64_WarpShape64x32x64,\n CtaShape128x128x64_WarpShape64x64x64,\n CtaShape128x128x64_WarpShape128x32x64,\n CtaShape128x256x64_WarpShape64x64x64,\n\n // Warp configs for M=256\n CtaShape256x128x64_WarpShape64x64x64,\n\n // TensorCore config CTA_N = 64, CTA_K = 128\n CtaShape128x64x128_WarpShape64x32x128,\n\n // TensorCore config CTA_N = 256, CTA_K = 64\n CtaShape16x256x64_WarpShape16x64x64,\n\n // TensorCore config CTA_N = 256, CTA_K = 128\n CtaShape16x256x128_WarpShape16x64x128\n\n};\n\nenum class SplitKStyle {\n NO_SPLIT_K,\n SPLIT_K_SERIAL,\n STREAM_K, // Sm80+\n // SPLIT_K_PARALLEL // Not supported yet\n};\n\nenum class CutlassTileConfigSM90 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n // CTA configs for M=64\n CtaShape64x16x128B,\n CtaShape64x32x128B,\n CtaShape64x64x128B,\n CtaShape64x128x128B,\n CtaShape64x256x128B,\n\n // CTA configs for M=128\n CtaShape128x16x128B,\n CtaShape128x32x128B,\n CtaShape128x64x128B,\n CtaShape128x128x128B,\n CtaShape128x256x128B,\n\n // CTA configs for M=128\n CtaShape256x128x128B,\n};\n\nenum class CutlassTileConfigSM100 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n /*\n * Grouped GEMM\n */\n // M=64\n CtaShape64x32x128B,\n CtaShape64x64x128B,\n CtaShape64x128x128B,\n CtaShape64x256x128B,\n\n // M=128\n CtaShape128x8x256B,\n CtaShape128x16x128B,\n CtaShape128x32x128B,\n CtaShape128x64x128B,\n CtaShape128x128x128B,\n CtaShape128x256x128B,\n CtaShape128x128x256B,\n CtaShape128x256x256B,\n\n // M=256\n CtaShape256x64x128B,\n CtaShape256x128x128B,\n CtaShape256x256x128B,\n\n // SM103\n CtaShape128x128x768B,\n CtaShape128x192x768B,\n CtaShape128x256x768B,\n};\n\nenum class CutlassTileConfigSM120 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n CtaShape128x128x128B,\n CtaShape128x128x64B,\n CtaShape256x128x64B,\n CtaShape128x256x64B,\n CtaShape128x128x256B,\n CtaShape256x128x128B,\n};\n\nenum class MainloopScheduleType {\n AUTO, // Automatically selects between pingpong and cooperative schedules on Hopper. On older\n // architectures, this defaults to the \"legacy\" main loop schedule.\n PINGPONG,\n COOPERATIVE,\n WARPSPECIALIZED\n};\n\nstatic auto get_mainloop_schedule_name(MainloopScheduleType schedule) {\n if (schedule == MainloopScheduleType::AUTO) {\n return \"auto\";\n } else if (schedule == MainloopScheduleType::PINGPONG) {\n return \"pingpong\";\n } else if (schedule == MainloopScheduleType::COOPERATIVE) {\n return \"cooperative\";\n } else if (schedule == MainloopScheduleType::WARPSPECIALIZED) {\n return \"warpspecialized\";\n }\n return \"unknown schedule\";\n}\n\nenum class EpilogueScheduleType {\n AUTO, // Automatically chooses an epilogue schedule compatible with the selected main loop\n // schedule for Hopper. For architectures older than hopper, the epilogue is always\n // performed by the same thread block as the main loop.\n};\n\nenum class TileShape {\n TileShape_64x16x128,\n TileShape_64x32x128,\n TileShape_64x64x128,\n TileShape_64x128x128,\n TileShape_64x256x128,\n TileShape_64x512x128,\n TileShape_128x16x128,\n TileShape_128x32x128,\n TileShape_128x64x128,\n TileShape_128x128x128,\n TileShape_128x256x128,\n // SM103\n TileShape_128x128x768,\n TileShape_128x192x768,\n TileShape_128x256x768\n};\n\ntemplate <TileShape Shape_MNK>\nconstexpr auto get_tile_shape() {\n using namespace cute;\n if constexpr (Shape_MNK == TileShape::TileShape_64x16x128) {\n return cute::Shape<_64, _16, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x32x128) {\n return cute::Shape<_64, _32, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x64x128) {\n return cute::Shape<_64, _64, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x128x128) {\n return cute::Shape<_64, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x256x128) {\n return cute::Shape<_64, _256, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x512x128) {\n return cute::Shape<_64, _512, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x16x128) {\n return cute::Shape<_128, _16, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x32x128) {\n return cute::Shape<_128, _32, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x64x128) {\n return cute::Shape<_128, _64, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x128x128) {\n return cute::Shape<_128, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x256x128) {\n return cute::Shape<_128, _256, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x128x768) { // SM103\n return cute::Shape<_128, _128, _768>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x192x768) { // SM103\n return cute::Shape<_128, _192, _768>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x256x768) { // SM103\n return cute::Shape<_128, _256, _768>{};\n }\n}\n\nstatic auto get_tile_shape_name(TileShape Shape_MNK) {\n if (Shape_MNK == TileShape::TileShape_64x16x128) {\n return \"64x16x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x32x128) {\n return \"64x32x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x64x128) {\n return \"64x64x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x128x128) {\n return \"64x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x256x128) {\n return \"64x256x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x512x128) {\n return \"64x512x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x16x128) {\n return \"128x16x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x32x128) {\n return \"128x32x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x64x128) {\n return \"128x64x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x128x128) {\n return \"128x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x256x128) {\n return \"128x256x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x128x768) { // SM103\n return \"128x128x768\";\n } else if (Shape_MNK == TileShape::TileShape_128x192x768) { // SM103\n return \"128x192x768\";\n } else if (Shape_MNK == TileShape::TileShape_128x256x768) { // SM103\n return \"128x256x768\";\n }\n return \"Unknown shape\";\n}\n\nenum class ClusterShape {\n ClusterShape_1x1x1,\n ClusterShape_2x1x1,\n ClusterShape_1x2x1,\n ClusterShape_2x2x1,\n ClusterShape_1x4x1,\n ClusterShape_4x2x1,\n ClusterShape_2x4x1,\n ClusterShape_4x4x1,\n ClusterShape_1x8x1,\n ClusterShape_8x1x1,\n ClusterShape_4x1x1\n};\n\nstatic auto get_cluster_shape_name(ClusterShape Shape_MNK) {\n if (Shape_MNK == ClusterShape::ClusterShape_1x1x1) {\n return \"1x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_2x1x1) {\n return \"2x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_1x2x1) {\n return \"1x2x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_2x2x1) {\n return \"2x2x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_1x8x1) {\n return \"1x8x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return \"8x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_4x1x1) {\n return \"4x1x1\";\n }\n return \"Unknown shape\";\n}\n\ntemplate <ClusterShape Shape_MNK>\nconstexpr auto get_cluster_shape() {\n using namespace cute;\n if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x1x1) {\n return cute::Shape<_1, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_2x1x1) {\n return cute::Shape<_2, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x2x1) {\n return cute::Shape<_1, _2, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_2x2x1) {\n return cute::Shape<_2, _2, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x8x1) {\n return cute::Shape<_1, _8, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return cute::Shape<_8, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_4x1x1) {\n return cute::Shape<_4, _1, _1>{};\n }\n}\n\nstruct CutlassGemmConfig {\n enum CandidateConfigTypeParam : int {\n NONE = 0,\n WEIGHT_ONLY = 1u << 0,\n SIMT_ONLY = 1u << 1,\n INT8_ONLY = 1u << 2,\n HOPPER = 1u << 3,\n BLACKWELL = 1u << 4,\n GROUPED_GEMM = 1u << 5,\n FP8_ONLY = 1u << 6,\n FP4_ONLY = 1u << 7\n };\n\n CutlassTileConfig tile_config_sm80 = CutlassTileConfig::ChooseWithHeuristic;\n SplitKStyle split_k_style = SplitKStyle::NO_SPLIT_K;\n int split_k_factor = -1;\n int stages = -1;\n\n // config options for sm90\n CutlassTileConfigSM90 tile_config_sm90 = CutlassTileConfigSM90::ChooseWithHeuristic;\n CutlassTileConfigSM100 tile_config_sm100 = CutlassTileConfigSM100::ChooseWithHeuristic;\n CutlassTileConfigSM120 tile_config_sm120 = CutlassTileConfigSM120::ChooseWithHeuristic;\n MainloopScheduleType mainloop_schedule = MainloopScheduleType::AUTO;\n EpilogueScheduleType epilogue_schedule = EpilogueScheduleType::AUTO;\n ClusterShape cluster_shape = ClusterShape::ClusterShape_1x1x1;\n bool enableCudaKernel = false;\n int sm_version = 80; // Use 80 as a catch all for <90\n bool is_tma_warp_specialized = false;\n\n CutlassGemmConfig() = default;\n\n CutlassGemmConfig(CutlassTileConfig tile_config, SplitKStyle split_k_style, int split_k_factor,\n int stages)\n : tile_config_sm80(tile_config),\n split_k_style(split_k_style),\n split_k_factor(split_k_factor),\n stages(stages),\n sm_version(80) {}\n\n CutlassGemmConfig(CutlassTileConfigSM90 tile_config_sm90, MainloopScheduleType mainloop_schedule,\n EpilogueScheduleType epilogue_schedule, ClusterShape cluster_shape)\n : tile_config_sm90(tile_config_sm90),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(90),\n is_tma_warp_specialized(true) {}\n\n CutlassGemmConfig(CutlassTileConfigSM100 tile_config_sm100,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n ClusterShape cluster_shape)\n : tile_config_sm100(tile_config_sm100),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(100),\n is_tma_warp_specialized(true) {}\n\n CutlassGemmConfig(CutlassTileConfigSM120 tile_config_sm120,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n ClusterShape cluster_shape)\n : tile_config_sm120(tile_config_sm120),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(120),\n is_tma_warp_specialized(true) {}\n\n int getTileConfigAsInt() const {\n if (sm_version == 120) return (int)tile_config_sm120;\n if (sm_version == 110) return (int)tile_config_sm100;\n if (sm_version >= 100) return (int)tile_config_sm100;\n if (sm_version == 90) return (int)tile_config_sm90;\n if (sm_version < 90) return (int)tile_config_sm80;\n assert(false && \"Invalid SM version\");\n return -1;\n }\n\n std::string toString() const {\n std::stringstream tactic;\n tactic << \"Cutlass GEMM Tactic\";\n if (is_tma_warp_specialized) {\n assert(sm_version >= 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=TMA Warp Specialized\"\n << \"\\n\\tsm: \" << sm_version << \"\\n\\ttile shape ID: \" << getTileConfigAsInt()\n << \"\\n\\tcluster shape ID: \" << (int)cluster_shape\n << \"\\n\\tmainloop sched: \" << (int)mainloop_schedule\n << \"\\n\\tepi sched: \" << (int)epilogue_schedule\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else if (tile_config_sm80 != flashinfer::gemm::CutlassTileConfig::ChooseWithHeuristic) {\n assert(sm_version < 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=compatible\"\n << \"\\n\\ttile shape ID: \" << (int)tile_config_sm80 << \"\\n\\tstages: \" << (int)stages\n << \"\\n\\tsplit k: \" << (int)split_k_factor\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else if (enableCudaKernel) {\n tactic << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else {\n tactic << \"\\n\\tundefined\";\n }\n tactic << \"\\n\";\n return tactic.str();\n }\n};\n\ninline std::ostream& operator<<(std::ostream& out, CutlassGemmConfig const& config) {\n // clang-format off\n if (config.is_tma_warp_specialized)\n {\n out << \"tile_config_sm90_enum: \" << config.getTileConfigAsInt()\n << \", mainloop_schedule_enum: \" << int(config.mainloop_schedule)\n << \", epilogue_schedule_enum: \" << int(config.epilogue_schedule)\n << \", cluster_shape_enum: \" << int(config.cluster_shape)\n << \", enable_cuda_kernel: \" << (config.enableCudaKernel ? \"true\" : \"false\");\n }\n else\n {\n out << \"tile_config_enum: \" << config.getTileConfigAsInt()\n << \", split_k_style_enum: \" << int(config.split_k_style)\n << \", split_k_factor: \" << config.split_k_factor\n << \", stages: \" << config.stages\n << \", enable_cuda_kernel: \" << (config.enableCudaKernel ? \"true\" : \"false\");\n }\n // clang-format on\n return out;\n}\n\n} // namespace gemm\n} // namespace flashinfer\n#endif // FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/gemm/cutlass_gemm_configs.h\n+++ include/flashinfer/gemm/cutlass_gemm_configs.h\n@@ -133,6 +133,11 @@\n CtaShape256x64x128B,\n CtaShape256x128x128B,\n CtaShape256x256x128B,\n+\n+ // SM103\n+ CtaShape128x128x768B,\n+ CtaShape128x192x768B,\n+ CtaShape128x256x768B,\n };\n \n enum class CutlassTileConfigSM120 {\n@@ -188,7 +193,11 @@\n TileShape_128x32x128,\n TileShape_128x64x128,\n TileShape_128x128x128,\n- TileShape_128x256x128\n+ TileShape_128x256x128,\n+ // SM103\n+ TileShape_128x128x768,\n+ TileShape_128x192x768,\n+ TileShape_128x256x768\n };\n \n template <TileShape Shape_MNK>\n@@ -216,6 +225,12 @@\n return cute::Shape<_128, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x256x128) {\n return cute::Shape<_128, _256, _128>{};\n+ } else if constexpr (Shape_MNK == TileShape::TileShape_128x128x768) { // SM103\n+ return cute::Shape<_128, _128, _768>{};\n+ } else if constexpr (Shape_MNK == TileShape::TileShape_128x192x768) { // SM103\n+ return cute::Shape<_128, _192, _768>{};\n+ } else if constexpr (Shape_MNK == TileShape::TileShape_128x256x768) { // SM103\n+ return cute::Shape<_128, _256, _768>{};\n }\n }\n \n@@ -242,6 +257,12 @@\n return \"128x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x256x128) {\n return \"128x256x128\";\n+ } else if (Shape_MNK == TileShape::TileShape_128x128x768) { // SM103\n+ return \"128x128x768\";\n+ } else if (Shape_MNK == TileShape::TileShape_128x192x768) { // SM103\n+ return \"128x192x768\";\n+ } else if (Shape_MNK == TileShape::TileShape_128x256x768) { // SM103\n+ return \"128x256x768\";\n }\n return \"Unknown shape\";\n }\n@@ -256,7 +277,8 @@\n ClusterShape_2x4x1,\n ClusterShape_4x4x1,\n ClusterShape_1x8x1,\n- ClusterShape_8x1x1\n+ ClusterShape_8x1x1,\n+ ClusterShape_4x1x1\n };\n \n static auto get_cluster_shape_name(ClusterShape Shape_MNK) {\n@@ -272,6 +294,8 @@\n return \"1x8x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return \"8x1x1\";\n+ } else if (Shape_MNK == ClusterShape::ClusterShape_4x1x1) {\n+ return \"4x1x1\";\n }\n return \"Unknown shape\";\n }\n@@ -291,6 +315,8 @@\n return cute::Shape<_1, _8, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return cute::Shape<_8, _1, _1>{};\n+ } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_4x1x1) {\n+ return cute::Shape<_4, _1, _1>{};\n }\n }\n "},"lines_added":{"kind":"number","value":28,"string":"28"},"lines_removed":{"kind":"number","value":2,"string":"2"},"files_in_commit":{"kind":"number","value":4,"string":"4"},"models_mentioned":{"kind":"list like","value":["llama"],"string":"[\n \"llama\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200","SM100","SM103"],"string":"[\n \"B200\",\n \"SM100\",\n \"SM103\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["6×","4×"],"string":"[\n \"6×\",\n \"4×\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/cutlass_gemm_configs.h).\n\nGoal: [Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels\nTarget hardware: B200, SM100, SM103\nTarget models: llama\n\nCurrent file:\n```cpp\n/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n#define FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n\n#include <cassert>\n#include <iostream>\n#include <sstream>\n#include <string>\n\n#include \"cute/tensor.hpp\"\n\nnamespace flashinfer {\nnamespace gemm {\n\n// Note: The shapes are in the format MxNxK. The K shape of the runtime config MUST match the K\n// shape\n// in the kernel layout details when doing weight only quantization.\nenum class CutlassTileConfig {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n // SiMT config\n CtaShape128x128x8_WarpShape64x64x8,\n\n // TensorCore configs CTA_N = 128, CTA_K = 64\n // Warp configs for M=16\n CtaShape16x128x64_WarpShape16x32x64,\n // Warp configs for M=32\n CtaShape32x128x64_WarpShape32x32x64,\n\n // Warp configs for M=64\n CtaShape64x128x64_WarpShape32x64x64,\n CtaShape64x64x128_WarpShape32x64x64,\n CtaShape64x128x64_WarpShape64x32x64,\n\n // Warp configs for M=128\n CtaShape128x64x64_WarpShape64x32x64,\n CtaShape128x128x64_WarpShape64x32x64,\n CtaShape128x128x64_WarpShape64x64x64,\n CtaShape128x128x64_WarpShape128x32x64,\n CtaShape128x256x64_WarpShape64x64x64,\n\n // Warp configs for M=256\n CtaShape256x128x64_WarpShape64x64x64,\n\n // TensorCore config CTA_N = 64, CTA_K = 128\n CtaShape128x64x128_WarpShape64x32x128,\n\n // TensorCore config CTA_N = 256, CTA_K = 64\n CtaShape16x256x64_WarpShape16x64x64,\n\n // TensorCore config CTA_N = 256, CTA_K = 128\n CtaShape16x256x128_WarpShape16x64x128\n\n};\n\nenum class SplitKStyle {\n NO_SPLIT_K,\n SPLIT_K_SERIAL,\n STREAM_K, // Sm80+\n // SPLIT_K_PARALLEL // Not supported yet\n};\n\nenum class CutlassTileConfigSM90 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n // CTA configs for M=64\n CtaShape64x16x128B,\n CtaShape64x32x128B,\n CtaShape64x64x128B,\n CtaShape64x128x128B,\n CtaShape64x256x128B,\n\n // CTA configs for M=128\n CtaShape128x16x128B,\n CtaShape128x32x128B,\n CtaShape128x64x128B,\n CtaShape128x128x128B,\n CtaShape128x256x128B,\n\n // CTA configs for M=128\n CtaShape256x128x128B,\n};\n\nenum class CutlassTileConfigSM100 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n /*\n * Grouped GEMM\n */\n // M=64\n CtaShape64x32x128B,\n CtaShape64x64x128B,\n CtaShape64x128x128B,\n CtaShape64x256x128B,\n\n // M=128\n CtaShape128x8x256B,\n CtaShape128x16x128B,\n CtaShape128x32x128B,\n CtaShape128x64x128B,\n CtaShape128x128x128B,\n CtaShape128x256x128B,\n CtaShape128x128x256B,\n CtaShape128x256x256B,\n\n // M=256\n CtaShape256x64x128B,\n CtaShape256x128x128B,\n CtaShape256x256x128B,\n};\n\nenum class CutlassTileConfigSM120 {\n // Signals that we should run heuristics do choose a config\n Undefined,\n\n // Signals that we should run heuristics do choose a config\n ChooseWithHeuristic,\n\n CtaShape128x128x128B,\n CtaShape128x128x64B,\n CtaShape256x128x64B,\n CtaShape128x256x64B,\n CtaShape128x128x256B,\n CtaShape256x128x128B,\n};\n\nenum class MainloopScheduleType {\n AUTO, // Automatically selects between pingpong and cooperative schedules on Hopper. On older\n // architectures, this defaults to the \"legacy\" main loop schedule.\n PINGPONG,\n COOPERATIVE,\n WARPSPECIALIZED\n};\n\nstatic auto get_mainloop_schedule_name(MainloopScheduleType schedule) {\n if (schedule == MainloopScheduleType::AUTO) {\n return \"auto\";\n } else if (schedule == MainloopScheduleType::PINGPONG) {\n return \"pingpong\";\n } else if (schedule == MainloopScheduleType::COOPERATIVE) {\n return \"cooperative\";\n } else if (schedule == MainloopScheduleType::WARPSPECIALIZED) {\n return \"warpspecialized\";\n }\n return \"unknown schedule\";\n}\n\nenum class EpilogueScheduleType {\n AUTO, // Automatically chooses an epilogue schedule compatible with the selected main loop\n // schedule for Hopper. For architectures older than hopper, the epilogue is always\n // performed by the same thread block as the main loop.\n};\n\nenum class TileShape {\n TileShape_64x16x128,\n TileShape_64x32x128,\n TileShape_64x64x128,\n TileShape_64x128x128,\n TileShape_64x256x128,\n TileShape_64x512x128,\n TileShape_128x16x128,\n TileShape_128x32x128,\n TileShape_128x64x128,\n TileShape_128x128x128,\n TileShape_128x256x128\n};\n\ntemplate <TileShape Shape_MNK>\nconstexpr auto get_tile_shape() {\n using namespace cute;\n if constexpr (Shape_MNK == TileShape::TileShape_64x16x128) {\n return cute::Shape<_64, _16, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x32x128) {\n return cute::Shape<_64, _32, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x64x128) {\n return cute::Shape<_64, _64, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x128x128) {\n return cute::Shape<_64, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x256x128) {\n return cute::Shape<_64, _256, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_64x512x128) {\n return cute::Shape<_64, _512, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x16x128) {\n return cute::Shape<_128, _16, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x32x128) {\n return cute::Shape<_128, _32, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x64x128) {\n return cute::Shape<_128, _64, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x128x128) {\n return cute::Shape<_128, _128, _128>{};\n } else if constexpr (Shape_MNK == TileShape::TileShape_128x256x128) {\n return cute::Shape<_128, _256, _128>{};\n }\n}\n\nstatic auto get_tile_shape_name(TileShape Shape_MNK) {\n if (Shape_MNK == TileShape::TileShape_64x16x128) {\n return \"64x16x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x32x128) {\n return \"64x32x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x64x128) {\n return \"64x64x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x128x128) {\n return \"64x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x256x128) {\n return \"64x256x128\";\n } else if (Shape_MNK == TileShape::TileShape_64x512x128) {\n return \"64x512x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x16x128) {\n return \"128x16x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x32x128) {\n return \"128x32x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x64x128) {\n return \"128x64x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x128x128) {\n return \"128x128x128\";\n } else if (Shape_MNK == TileShape::TileShape_128x256x128) {\n return \"128x256x128\";\n }\n return \"Unknown shape\";\n}\n\nenum class ClusterShape {\n ClusterShape_1x1x1,\n ClusterShape_2x1x1,\n ClusterShape_1x2x1,\n ClusterShape_2x2x1,\n ClusterShape_1x4x1,\n ClusterShape_4x2x1,\n ClusterShape_2x4x1,\n ClusterShape_4x4x1,\n ClusterShape_1x8x1,\n ClusterShape_8x1x1\n};\n\nstatic auto get_cluster_shape_name(ClusterShape Shape_MNK) {\n if (Shape_MNK == ClusterShape::ClusterShape_1x1x1) {\n return \"1x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_2x1x1) {\n return \"2x1x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_1x2x1) {\n return \"1x2x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_2x2x1) {\n return \"2x2x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_1x8x1) {\n return \"1x8x1\";\n } else if (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return \"8x1x1\";\n }\n return \"Unknown shape\";\n}\n\ntemplate <ClusterShape Shape_MNK>\nconstexpr auto get_cluster_shape() {\n using namespace cute;\n if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x1x1) {\n return cute::Shape<_1, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_2x1x1) {\n return cute::Shape<_2, _1, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x2x1) {\n return cute::Shape<_1, _2, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_2x2x1) {\n return cute::Shape<_2, _2, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_1x8x1) {\n return cute::Shape<_1, _8, _1>{};\n } else if constexpr (Shape_MNK == ClusterShape::ClusterShape_8x1x1) {\n return cute::Shape<_8, _1, _1>{};\n }\n}\n\nstruct CutlassGemmConfig {\n enum CandidateConfigTypeParam : int {\n NONE = 0,\n WEIGHT_ONLY = 1u << 0,\n SIMT_ONLY = 1u << 1,\n INT8_ONLY = 1u << 2,\n HOPPER = 1u << 3,\n BLACKWELL = 1u << 4,\n GROUPED_GEMM = 1u << 5,\n FP8_ONLY = 1u << 6,\n FP4_ONLY = 1u << 7\n };\n\n CutlassTileConfig tile_config_sm80 = CutlassTileConfig::ChooseWithHeuristic;\n SplitKStyle split_k_style = SplitKStyle::NO_SPLIT_K;\n int split_k_factor = -1;\n int stages = -1;\n\n // config options for sm90\n CutlassTileConfigSM90 tile_config_sm90 = CutlassTileConfigSM90::ChooseWithHeuristic;\n CutlassTileConfigSM100 tile_config_sm100 = CutlassTileConfigSM100::ChooseWithHeuristic;\n CutlassTileConfigSM120 tile_config_sm120 = CutlassTileConfigSM120::ChooseWithHeuristic;\n MainloopScheduleType mainloop_schedule = MainloopScheduleType::AUTO;\n EpilogueScheduleType epilogue_schedule = EpilogueScheduleType::AUTO;\n ClusterShape cluster_shape = ClusterShape::ClusterShape_1x1x1;\n bool enableCudaKernel = false;\n int sm_version = 80; // Use 80 as a catch all for <90\n bool is_tma_warp_specialized = false;\n\n CutlassGemmConfig() = default;\n\n CutlassGemmConfig(CutlassTileConfig tile_config, SplitKStyle split_k_style, int split_k_factor,\n int stages)\n : tile_config_sm80(tile_config),\n split_k_style(split_k_style),\n split_k_factor(split_k_factor),\n stages(stages),\n sm_version(80) {}\n\n CutlassGemmConfig(CutlassTileConfigSM90 tile_config_sm90, MainloopScheduleType mainloop_schedule,\n EpilogueScheduleType epilogue_schedule, ClusterShape cluster_shape)\n : tile_config_sm90(tile_config_sm90),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(90),\n is_tma_warp_specialized(true) {}\n\n CutlassGemmConfig(CutlassTileConfigSM100 tile_config_sm100,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n ClusterShape cluster_shape)\n : tile_config_sm100(tile_config_sm100),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(100),\n is_tma_warp_specialized(true) {}\n\n CutlassGemmConfig(CutlassTileConfigSM120 tile_config_sm120,\n MainloopScheduleType mainloop_schedule, EpilogueScheduleType epilogue_schedule,\n ClusterShape cluster_shape)\n : tile_config_sm120(tile_config_sm120),\n mainloop_schedule(mainloop_schedule),\n epilogue_schedule(epilogue_schedule),\n cluster_shape(cluster_shape),\n sm_version(120),\n is_tma_warp_specialized(true) {}\n\n int getTileConfigAsInt() const {\n if (sm_version == 120) return (int)tile_config_sm120;\n if (sm_version == 110) return (int)tile_config_sm100;\n if (sm_version >= 100) return (int)tile_config_sm100;\n if (sm_version == 90) return (int)tile_config_sm90;\n if (sm_version < 90) return (int)tile_config_sm80;\n assert(false && \"Invalid SM version\");\n return -1;\n }\n\n std::string toString() const {\n std::stringstream tactic;\n tactic << \"Cutlass GEMM Tactic\";\n if (is_tma_warp_specialized) {\n assert(sm_version >= 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=TMA Warp Specialized\"\n << \"\\n\\tsm: \" << sm_version << \"\\n\\ttile shape ID: \" << getTileConfigAsInt()\n << \"\\n\\tcluster shape ID: \" << (int)cluster_shape\n << \"\\n\\tmainloop sched: \" << (int)mainloop_schedule\n << \"\\n\\tepi sched: \" << (int)epilogue_schedule\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else if (tile_config_sm80 != flashinfer::gemm::CutlassTileConfig::ChooseWithHeuristic) {\n assert(sm_version < 90 && \"Invalid cutlass GEMM config\");\n tactic << \"\\n\\tstyle=compatible\"\n << \"\\n\\ttile shape ID: \" << (int)tile_config_sm80 << \"\\n\\tstages: \" << (int)stages\n << \"\\n\\tsplit k: \" << (int)split_k_factor\n << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else if (enableCudaKernel) {\n tactic << \"\\n\\tenable cuda kernel: \" << (enableCudaKernel ? \"true\" : \"false\");\n } else {\n tactic << \"\\n\\tundefined\";\n }\n tactic << \"\\n\";\n return tactic.str();\n }\n};\n\ninline std::ostream& operator<<(std::ostream& out, CutlassGemmConfig const& config) {\n // clang-format off\n if (config.is_tma_warp_specialized)\n {\n out << \"tile_config_sm90_enum: \" << config.getTileConfigAsInt()\n << \", mainloop_schedule_enum: \" << int(config.mainloop_schedule)\n << \", epilogue_schedule_enum: \" << int(config.epilogue_schedule)\n << \", cluster_shape_enum: \" << int(config.cluster_shape)\n << \", enable_cuda_kernel: \" << (config.enableCudaKernel ? \"true\" : \"false\");\n }\n else\n {\n out << \"tile_config_enum: \" << config.getTileConfigAsInt()\n << \", split_k_style_enum: \" << int(config.split_k_style)\n << \", split_k_factor: \" << config.split_k_factor\n << \", stages: \" << config.stages\n << \", enable_cuda_kernel: \" << (config.enableCudaKernel ? \"true\" : \"false\");\n }\n // clang-format on\n return out;\n}\n\n} // namespace gemm\n} // namespace flashinfer\n#endif // FLASHINFER_CUTLASS_GEMM_CONFIG_H_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Summary\n\nThis PR adds new template specializations for SM103 NVFP4 CUTLASS GEMM kernels using architecture-specific tile shapes, cluster shapes, and schedulers.\n\n## Motivation\n\nSM103 specifications show a higher NVFP4-over-BF16 speedup ratio than B200 (6× vs. 4×), but current kernels remain far from this limit. \nThis PR introduces SM103-optimized templates to improve the achieved performance on this architecture.\n\nThe performance gains are more pronounced at larger batch sizes, while the previous SM100 configurations remain preferable in other cases.\nFor this reason, SM103-specific configurations were added alongside the existing ones rather than replacing them, and the optimal configuration is automatically selected as part of the autotuning process.\n\n## Performance results examples\n\nLlama-3.1-70B, N=8192 K=28672, BF16 vs NVFP4 GEMMs TFLOP/s:\n\n| Batch Size | Torch BF16 | NVFP4 Before | NVFP4 After |\n|-----------:|-----------:|-------------:|------------:|\n| 8 | 50.418336 | 110.598008 | 124.005817 |\n| 16 | 99.350151 | 219.649654 | 260.502226 |\n| 32 | 193.884850 | 445.840601 | 519.291059 |\n| 64 | 385.790757 | 978.451544 | 1011.614080 |\n| 128 | 692.915989 | 2072.797941 | 2076.017433 |\n| 256 | 1211.413202| 3817.738538 | 3868.924511 |\n| 512 | 1464.015616| 5141.532768 | 5503.664311 |\n| 1024 | 1600.983748| 5659.831320 | 6341.013002 |\n| 2048 | 1625.639619| 5991.840134 | 6630.757403 |\n| 4096 | 1602.978834| 6160.806595 | 6898.878407 |\n| 8192 | 1691.174722| 5939.220913 | 6653.915111 |\n| 16384 | 1688.224044| 5926.519222 | 6595.387600 |\n| 24576 | 1706.774619| 5905.301100 | 6617.486211 |\n| 32768 | 1678.225402| 5913.806010 | 6592.762922 |\n\n---\n\nLlama-3.1-70B, N=8192 K=8192, BF16 vs NVFP4 GEMMs TFLOP/s:\n\n| Batch Size | Torch BF16 | NVFP4 Before | NVFP4 After |\n|-----------:|-----------:|--------------------------:|--------------------------:|\n| 8 | 47.780647 | 124.774241 | 124.760324 |\n| 16 | 95.671633 | 249.502165 | 249.131125 |\n| 32 | 189.224266 | 497.991489 | 497.277802 |\n| 64 | 373.320912 | 993.731451 | 989.446041 |\n| 128 | 707.096994 | 1959.258553 | 1970.430179 |\n| 256 | 1126.908748| 4037.558967 | 4159.515720 |\n| 512 | 1407.884777| 5045.981883 | 4958.698763 |\n| 1024 | 1491.747576| 5654.694949 | 5614.133004 |\n| 2048 | 1546.322959| 5898.291400 | 6204.813491 |\n| 4096 | 1610.656216| 6312.498418 | 6605.534723 |\n| 8192 | 1623.748353| 6392.424296 | 6803.660138 |\n| 16384 | 1627.947338| 6438.789701 | 6947.466217 |\n| 24576 | 1614.582791| 6469.307368 | 6991.331576 |\n| 32768 | 1617.601164| 6515.312895 | 7010.746651 |\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added support for NVIDIA SM103 GPU architecture in FP4 operations with specialized kernel configurations and optimized launcher implementations, extending hardware compatibility and enabling efficient computation on additional GPU variants.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"e2e\", \"hardware\": \"SM103\", \"model\": \"Llama-3.1-70B\", \"shape\": \"N=8192,K=28672\", \"batch_size\": 8, \"metric\": \"TFLOPS\", \"unit\": \"TFLOP/s\", \"higher_is_better\": true, \"baseline\": 110.598008, \"optimized\": 124.005817, \"stated_speedup\": null, \"speedup\": 1.1212}, {\"scope\": \"e2e\", \"hardware\": \"SM103\", \"model\": \"Llama-3.1-70B\", \"shape\": \"N=8192,K=28672\", \"batch_size\": 16, \"metric\": \"TFLOPS\", \"unit\": \"TFLOP/s\", \"higher_is_better\": true, \"baseline\": 219.649654, \"optimized\": 260.502226, \"stated_speedup\": null, \"speedup\": 1.186}, {\"scope\": \"e2e\", \"hardware\": \"SM103\", \"model\": \"Llama-3.1-70B\", \"shape\": \"N=8192,K=28672\", \"batch_size\": 32, \"metric\": \"TFLOPS\", \"unit\": \"TFLOP/s\", \"higher_is_better\": true, \"baseline\": 445.840601, \"optimized\": 519.291059, \"stated_speedup\": null, \"speedup\": 1.1647}, {\"scope\": \"e2e\", \"hardware\": \"SM103\", \"model\": \"Llama-3.1-70B\", \"shape\": \"N=8192,K=28672\", \"batch_size\": 64, \"metric\": \"TFLOPS\", \"unit\": \"TFLOP/s\", \"higher_is_better\": true, \"baseline\": 978.451544, \"optimized\": 1011.61408, \"stated_speedup\": null, \"speedup\": 1.0339}, {\"scope\": \"e2e\", \"hardware\": \"SM103\", \"model\": \"Llama-3.1-70B\", \"shape\": \"N=8192,K=28672\", \"batch_size\": 128, \"metric\": \"TFLOPS\", \"unit\": \"TFLOP/s\", \"higher_is_better\": true, \"baseline\": 2072.797941, \"optimized\": 2076.017433, \"stated_speedup\": null, \"speedup\": 1.0016}, {\"scope\": \"e2e\", \"hardware\": \"SM103\", \"model\": \"Llama-3.1-70B\", \"shape\": \"N=8192,K=28672\", \"batch_size\": 256, \"metric\": \"TFLOPS\", \"unit\": \"TFLOP/s\", \"higher_is_better\": true, \"baseline\": 3817.738538, \"optimized\": 3868.924511, \"stated_speedup\": null, \"speedup\": 1.0134}, {\"scope\": \"e2e\", \"hardware\": \"SM103\", \"model\": \"Llama-3.1-70B\", \"shape\": \"N=8192,K=28672\", \"batch_size\": 512, \"metric\": \"TFLOPS\", \"unit\": \"TFLOP/s\", \"higher_is_better\": true, \"baseline\": 5141.532768, \"optimized\": 5503.664311, \"stated_speedup\": null, \"speedup\": 1.0704}, {\"scope\": \"e2e\", \"hardware\": \"SM103\", \"model\": \"Llama-3.1-70B\", \"shape\": \"N=8192,K=28672\", \"batch_size\": 1024, \"metric\": \"TFLOPS\", \"unit\": \"TFLOP/s\", \"higher_is_better\": true, \"baseline\": 5659.83132, \"optimized\": 6341.013002, \"stated_speedup\": null, \"speedup\": 1.1204}, {\"scope\": \"e2e\", \"hardware\": \"SM103\", \"model\": \"Llama-3.1-70B\", \"shape\": \"N=8192,K=28672\", \"batch_size\": 2048, \"metric\": \"TFLOPS\", \"unit\": \"TFLOP/s\", \"higher_is_better\": true, \"baseline\": 5991.840134, \"optimized\": 6630.757403, \"stated_speedup\": null, \"speedup\": 1.1066}, {\"scope\": \"e2e\", \"hardware\": \"SM103\", \"model\": \"Llama-3.1-70B\", \"shape\": \"N=8192,K=28672\", \"batch_size\": 4096, \"metric\": \"TFLOPS\", \"unit\": \"TFLOP/s\", \"higher_is_better\": true, \"baseline\": 6160.806595, \"optimized\": 6898.878407, \"stated_speedup\": null, \"speedup\": 1.1198}, {\"scope\": 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\"batch_size\": 24576, \"metric\": \"TFLOPS\", \"unit\": \"TFLOP/s\", \"higher_is_better\": true, \"baseline\": 6469.307368, \"optimized\": 6991.331576, \"stated_speedup\": null, \"speedup\": 1.0807}, {\"scope\": \"e2e\", \"hardware\": \"SM103\", \"model\": \"Llama-3.1-70B\", \"shape\": \"N=8192,K=8192\", \"batch_size\": 32768, \"metric\": \"TFLOPS\", \"unit\": \"TFLOP/s\", \"higher_is_better\": true, \"baseline\": 6515.312895, \"optimized\": 7010.746651, \"stated_speedup\": null, \"speedup\": 1.076}]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"number","value":1.0674,"string":"1.0674"}}},{"rowIdx":1187,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"aa8af8534579653a8006be47a6517c103dfb761d"},"date":{"kind":"string","value":"2026-01-23T17:23:57+08:00"},"pr_number":{"kind":"number","value":2343,"string":"2,343"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2343"},"title":{"kind":"string","value":"Optimize quantization function in large problem size (#2343)"},"message":{"kind":"string","value":"Optimize quantization function in large problem size (#2343)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\nOptimize quantization function in large problem size by using TMA and\nwarp specialized programming.\n\n<!-- What does this PR do? Briefly describe the changes and why they’re\nneeded. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* Added a high-throughput TMA-backed quantization path for large tensors\nto improve scalability and throughput.\n\n* **Refactor**\n* Reworked quantization internals to a template-driven, per-thread\npacking architecture, unifying element packing and scale-factor handling\nacross FP16/FP8→FP4 and MXFP8 paths.\n\n* **Documentation**\n* Updated comments and dispatch logic to describe templated and\nTMA-backed quantization flows.\n\n* **Tests**\n * Extended quantization test coverage with a larger tensor shape.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review\nsettings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: Shunkang <182541032+Shunkangz@users.noreply.github.co>\nCo-authored-by: Shunkang <Shunkangz@users.noreply.github.com>"},"path":{"kind":"string","value":"csrc/nv_internal/cpp/kernels/quantization.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <float.h>\n\n#include \"tensorrt_llm/common/assert.h\"\n#include \"tensorrt_llm/common/cudaTypeUtils.cuh\"\n#include \"tensorrt_llm/common/cudaUtils.h\"\n#include \"tensorrt_llm/common/envUtils.h\"\n#include \"tensorrt_llm/common/quantTypeUtils.cuh\"\n#include \"tensorrt_llm/common/reduceKernelUtils.cuh\"\n#include \"tensorrt_llm/kernels/quantization.cuh\"\n#include \"tensorrt_llm/kernels/quantization.h\"\n\nusing namespace tensorrt_llm::common;\n\nnamespace tensorrt_llm {\nnamespace kernels {\n\ntemplate <typename T>\nvoid invokeQuantization(int8_t* dst, T const* src, int64_t const size, float const* scalePtr,\n cudaStream_t stream, int maxGridSize) {\n TLLM_CHECK_WITH_INFO(size % 4 == 0,\n \"[ERROR][invokeQuantization] size should be a multiple of 4.\\n\");\n\n int numBlocks{static_cast<int>((size + 255) / 256)};\n dim3 grid(std::min(numBlocks, maxGridSize));\n TLLM_CHECK_WITH_INFO(grid.x <= maxGridSize,\n \"[ERROR][invokeQuantization] grid max size is exceeded\\n\");\n dim3 block(64);\n if (std::is_same_v<T, float>) {\n quantizedKernel<<<grid, block, 0, stream>>>((char4*)dst, (float4 const*)src, size / 4,\n scalePtr);\n } else if (std::is_same_v<T, half>) {\n quantizedKernel<<<grid, block, 0, stream>>>((char4*)dst, (half2 const*)src, size / 4, scalePtr);\n }\n#ifdef ENABLE_BF16\n else if (std::is_same_v<T, __nv_bfloat16>) {\n quantizedKernel<<<grid, block, 0, stream>>>((char4*)dst, (__nv_bfloat162 const*)src, size / 4,\n scalePtr);\n }\n#endif\n}\n\ntemplate void invokeQuantization<float>(int8_t* dst, float const* src, int64_t const size,\n float const* scalePtr, cudaStream_t stream,\n int maxGridSize);\n\ntemplate void invokeQuantization<half>(int8_t* dst, half const* src, int64_t const size,\n float const* scalePtr, cudaStream_t stream, int maxGridSize);\n\n#ifdef ENABLE_BF16\ntemplate void invokeQuantization<__nv_bfloat16>(int8_t* dst, __nv_bfloat16 const* src,\n int64_t const size, float const* scalePtr,\n cudaStream_t stream, int maxGridSize);\n#endif\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// Helper function for grid configuration with swizzled layouts\n\ninline int computeEffectiveRows(int m, QuantizationSFLayout layout) {\n int effectiveRows = m;\n bool isSfSwizzledLayout = (layout == QuantizationSFLayout::SWIZZLED_128x4 ||\n layout == QuantizationSFLayout::SWIZZLED_8x4);\n if (isSfSwizzledLayout) {\n int rowTile = (layout == QuantizationSFLayout::SWIZZLED_128x4) ? 128 : 8;\n int numPaddedRows = (m + rowTile - 1) / rowTile * rowTile; // Round up to rowTile\n effectiveRows = numPaddedRows;\n }\n return effectiveRows;\n}\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// MXFP8 Quantization\n\ntemplate <typename T>\nvoid invokeMxFP8Quantization(int b, int m, int n, int padded_n, T const* input, int64_t* output,\n int32_t* SFOuput, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream) {\n // Fixed SF_VEC_SIZE as 32\n static constexpr int SF_VEC_SIZE = 32;\n\n // Grid, Block size.\n // Each thread converts 8 values.\n dim3 block(std::min(int(padded_n / CVT_ELTS_PER_THREAD), 512));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 2048u / block.x);\n int effectiveRows = computeEffectiveRows(m, layout);\n dim3 grid(std::min(effectiveRows, multiProcessorCount * numBlocksPerSM));\n\n // Launch the cvt kernel.\n cudaLaunchConfig_t config;\n config.gridDim = grid;\n config.blockDim = block;\n config.dynamicSmemBytes = 0;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = enable_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n cudaLaunchKernelEx(\n &config,\n quantize_with_block_size<BlockScaleQuantizationType::FP16_TO_MXFP8, T, SF_VEC_SIZE, true>, b,\n m, n, padded_n, input, nullptr, reinterpret_cast<uint32_t*>(output),\n reinterpret_cast<uint32_t*>(SFOuput), layout);\n}\n\n// Do per-token (row) quantization from fp16/bf16/fp32 to int8/fp8_e4m3.\ntemplate <typename T, typename QuantT>\nvoid invokePerTokenQuantization(QuantT* dst, T const* src, int64_t const numRows,\n int64_t const numCols, float const* clampPtr, float* scalePtr,\n float* sumPtr, QuantMode quantMode, cudaStream_t stream) {\n // each block is responsible for a single row\n dim3 const block(512);\n dim3 const grid(numRows);\n\n // The number of elements in the packed uint4 vec.\n static constexpr int NUM_ELTS_PER_VEC = sizeof(uint4) / sizeof(T);\n TLLM_CHECK_WITH_INFO(numCols % NUM_ELTS_PER_VEC == 0, \"Not supported.\");\n\n // Cache vectors to smem to avoid reloading.\n size_t const dynamicSmemSz = numCols * sizeof(T);\n // Need to check if smem capacity is enough.\n bool useSmem = true;\n if (dynamicSmemSz >= 48 * 1024) {\n cudaError_t res =\n cudaFuncSetAttribute(perTokenQuantization<T, QuantT, true>,\n cudaFuncAttributeMaxDynamicSharedMemorySize, dynamicSmemSz);\n // Fall back to reloading-reversion if smem is not enough.\n useSmem = (res == cudaSuccess);\n }\n\n // Enable min_scaling_factor if it is fp8 rowwise per-token quantization.\n bool hasFp8MinScaling = quantMode.hasFp8RowWise();\n // Do we use smem ?\n if (useSmem) {\n perTokenQuantization<T, QuantT, true><<<grid, block, dynamicSmemSz, stream>>>(\n dst, src, numRows, numCols, clampPtr, scalePtr, sumPtr, hasFp8MinScaling);\n } else {\n perTokenQuantization<T, QuantT, false><<<grid, block, 0, stream>>>(\n dst, src, numRows, numCols, clampPtr, scalePtr, sumPtr, hasFp8MinScaling);\n }\n}\n\n#define INSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(T, QuantT) \\\n template void invokePerTokenQuantization(QuantT* dst, const T* src, const int64_t numRows, \\\n const int64_t numCols, float const* clampPtr, \\\n float* scalePtr, float* sumPtr, QuantMode quantMode, \\\n cudaStream_t stream)\n\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(float, int8_t);\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(half, int8_t);\n#ifdef ENABLE_BF16\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(__nv_bfloat16, int8_t);\n#endif\n\n#ifdef ENABLE_FP8\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(float, __nv_fp8_e4m3);\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(half, __nv_fp8_e4m3);\n#ifdef ENABLE_BF16\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(__nv_bfloat16, __nv_fp8_e4m3);\n#endif\n#endif\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// FP4/MXFP8 Quantization\n\ntemplate <typename T, int SF_VEC_SIZE>\nvoid invokeFP4Quantization(int b, int m, int n, T const* input, float const* SFScale,\n int64_t* output, int32_t* SFOuput, bool useUE8M0,\n QuantizationSFLayout layout, int multiProcessorCount, bool enable_pdl,\n cudaStream_t stream) {\n#ifdef ENABLE_FP8\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n // Grid, Block size.\n // Each thread converts 16 values.\n dim3 block(std::min(int(n / CVT_FP8_TO_FP4_ELTS_PER_THREAD), 512));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 2048u / block.x);\n int effectiveRows = computeEffectiveRows(m, layout);\n dim3 grid(std::min(effectiveRows, multiProcessorCount * numBlocksPerSM));\n\n // Launch the cvt kernel.\n auto* kernel_instance = useUE8M0\n ? &quantize_with_block_size<BlockScaleQuantizationType::FP8_TO_FP4,\n T, SF_VEC_SIZE, true>\n : &quantize_with_block_size<BlockScaleQuantizationType::FP8_TO_FP4,\n T, SF_VEC_SIZE, false>;\n kernel_instance<<<grid, block, 0, stream>>>(b, m, n, n, input, SFScale,\n reinterpret_cast<uint32_t*>(output),\n reinterpret_cast<uint32_t*>(SFOuput), layout);\n\n } else\n#endif\n {\n // Grid, Block size.\n // Each thread converts 8 values.\n dim3 block(std::min(int(n / CVT_ELTS_PER_THREAD), 512));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 2048u / block.x);\n int effectiveRows = computeEffectiveRows(m, layout);\n dim3 grid(std::min(effectiveRows, multiProcessorCount * numBlocksPerSM));\n\n // Launch the cvt kernel.\n auto* kernel_instance = useUE8M0\n ? &quantize_with_block_size<BlockScaleQuantizationType::FP16_TO_FP4,\n T, SF_VEC_SIZE, true>\n : &quantize_with_block_size<BlockScaleQuantizationType::FP16_TO_FP4,\n T, SF_VEC_SIZE, false>;\n\n cudaLaunchConfig_t config;\n config.gridDim = grid;\n config.blockDim = block;\n config.dynamicSmemBytes = 0;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = enable_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n cudaLaunchKernelEx(&config, kernel_instance, b, m, n, n, input, SFScale,\n reinterpret_cast<uint32_t*>(output), reinterpret_cast<uint32_t*>(SFOuput),\n layout);\n }\n}\n\ntemplate <typename T>\n__global__ void block_scale_interleave_kernel(int numBatches, int numRows, int numRowsPadded,\n int numCols, int numColsPadded, T const* SFIn,\n T* SFOutput) {\n for (int rowIdx = blockIdx.x; rowIdx < numRowsPadded; rowIdx += gridDim.x) {\n for (int batchIdx = 0; batchIdx < numBatches; batchIdx++) {\n for (int colIdx = threadIdx.x; colIdx < numColsPadded; colIdx += blockDim.x) {\n T sf = 0;\n if (rowIdx < numRows && colIdx < numCols) {\n int64_t inOffset = batchIdx * numRows * numCols + rowIdx * numCols + colIdx;\n sf = SFIn[inOffset];\n }\n\n std::optional<int> batchIdxOpt = batchIdx;\n std::optional<int> numRowsOpt = numRows;\n\n // Without batching, the math in get_sf_out_offset is the same as\n // int const numSfTilesK = (numCols + 4 - 1) / 4;\n // int const tileOffset = ((mi / 128) * numSfTilesK + ki / 4) * 512;\n // int const dstIdx = tileOffset + (mi % 32) * 16 + ((mi % 128) / 32) * 4 + ki % 4;\n auto dstIdx = get_sf_out_offset_128x4(batchIdxOpt, rowIdx, colIdx, numRowsOpt, numCols);\n SFOutput[dstIdx] = sf;\n }\n }\n }\n}\n\n__global__ void block_scale_interleave_reverse_kernel(int numBatches, int numRows, int numCols,\n uint8_t const* SFIn, uint8_t* SFOutput) {\n for (int rowIdx = blockIdx.x; rowIdx < numRows; rowIdx += gridDim.x) {\n for (int batchIdx = 0; batchIdx < numBatches; batchIdx++) {\n for (int colIdx = threadIdx.x; colIdx < numCols; colIdx += blockDim.x) {\n std::optional<int> batchIdxOpt = batchIdx;\n std::optional<int> numRowsOpt = numRows;\n\n // Get the swizzled input index using the same swizzling pattern\n auto srcIdx = get_sf_out_offset_128x4(batchIdxOpt, rowIdx, colIdx, numRowsOpt, numCols);\n auto sf = SFIn[srcIdx];\n\n // Output goes to linear layout\n int64_t outOffset = batchIdx * numRows * numCols + rowIdx * numCols + colIdx;\n SFOutput[outOffset] = sf;\n }\n }\n }\n}\n\n// This is intended for weight loading, so m and n are large, b <= 256\ntemplate <typename T>\nvoid invokeBlockScaleInterleave(int b, int m, int m_padded, int n, int n_padded, T const* SFIn,\n T* SFOutput, int multiProcessorCount, cudaStream_t stream) {\n // Each thread reads 1 int8 value\n dim3 block(std::min(n_padded, 1024));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 4096u / block.x);\n dim3 grid(std::min(m_padded, multiProcessorCount * numBlocksPerSM));\n\n block_scale_interleave_kernel<T>\n <<<grid, block, 0, stream>>>(b, m, m_padded, n, n_padded, SFIn, SFOutput);\n}\n\n// Explicit template instantiations for the types used by other compilation units\ntemplate void invokeBlockScaleInterleave<uint8_t>(int b, int m, int m_padded, int n, int n_padded,\n uint8_t const* SFIn, uint8_t* SFOutput,\n int multiProcessorCount, cudaStream_t stream);\ntemplate void invokeBlockScaleInterleave<__nv_bfloat16>(int b, int m, int m_padded, int n,\n int n_padded, __nv_bfloat16 const* SFIn,\n __nv_bfloat16* SFOutput,\n int multiProcessorCount,\n cudaStream_t stream);\n\n// This is intended for weight loading, so m and n are large, b <= 256\nvoid invokeBlockScaleInterleaveReverse(int b, int m, int n, uint8_t const* SFIn, uint8_t* SFOutput,\n int multiProcessorCount, cudaStream_t stream) {\n // Each thread reads 1 int8 value\n dim3 block(std::min(n, 1024));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 4096u / block.x);\n dim3 grid(std::min(m, multiProcessorCount * numBlocksPerSM));\n\n block_scale_interleave_reverse_kernel<<<grid, block, 0, stream>>>(b, m, n, SFIn, SFOutput);\n}\n\ntemplate <typename T>\nvoid invokeSiluAndMulNVFP4Quantization(void* output, void* output_scale, void* input,\n void* input_global_scale, void* mask, bool use_silu_and_mul,\n int m_topk, int k, int n_experts, cudaStream_t stream) {\n int device;\n TLLM_CUDA_CHECK(cudaGetDevice(&device));\n int multiProcessorCount;\n TLLM_CUDA_CHECK(\n cudaDeviceGetAttribute(&multiProcessorCount, cudaDevAttrMultiProcessorCount, device));\n\n // Grid, Block size.\n // Each thread converts 8 values.\n TLLM_CHECK_WITH_INFO(k > 0, \"k must be > 0\");\n int const workSizePerRow = max(1, k / CVT_ELTS_PER_THREAD);\n int const totalWorkSize = m_topk * workSizePerRow;\n dim3 block(std::min(workSizePerRow, 512));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = 2048 / block.x;\n dim3 grid(std::min(static_cast<int>((totalWorkSize + block.x - 1) / block.x),\n multiProcessorCount * numBlocksPerSM));\n while (grid.x <= multiProcessorCount && block.x > 64) {\n grid.x *= 2;\n block.x = (block.x + 1) / 2;\n }\n\n // TODO(kaixih@nvidia): Should relax this to allow any grid size.\n // shuw@nvidia.com: only deal with mask case\n TLLM_CHECK_WITH_INFO(mask != nullptr, \"mask must be non-null for expert NVFP4 path\");\n TLLM_CHECK_WITH_INFO(n_experts > 0, \"n_experts must be > 0\");\n grid.x = (grid.x + n_experts - 1) / n_experts * n_experts;\n cvt_fp16_to_fp4_expert<T, false><<<grid, block, 0, stream>>>(\n m_topk, k, reinterpret_cast<T*>(input), reinterpret_cast<float*>(input_global_scale),\n reinterpret_cast<uint32_t*>(output), reinterpret_cast<uint32_t*>(output_scale),\n reinterpret_cast<int32_t*>(mask), use_silu_and_mul, n_experts);\n return;\n}\n\n// Instantiate the function.\ntemplate void invokeFP4Quantization<half, 16>(int b, int m, int n, half const* input,\n float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0,\n QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeFP4Quantization<half, 32>(int b, int m, int n, half const* input,\n float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0,\n QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeMxFP8Quantization<half>(int b, int m, int n, int padded_n, half const* input,\n int64_t* output, int32_t* SFOuput,\n QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeSiluAndMulNVFP4Quantization<half>(void* output, void* output_scale, void* input,\n void* input_global_scale, void* mask,\n bool use_silu_and_mul, int m_topk, int k,\n int n_experts, cudaStream_t stream);\n\n#ifdef ENABLE_BF16\ntemplate void invokeFP4Quantization<__nv_bfloat16, 16>(\n int b, int m, int n, __nv_bfloat16 const* input, float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeFP4Quantization<__nv_bfloat16, 32>(\n int b, int m, int n, __nv_bfloat16 const* input, float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeMxFP8Quantization<__nv_bfloat16>(int b, int m, int n, int padded_n,\n __nv_bfloat16 const* input, int64_t* output,\n int32_t* SFOuput, QuantizationSFLayout layout,\n int multiProcessorCount, bool enable_pdl,\n cudaStream_t stream);\ntemplate void invokeSiluAndMulNVFP4Quantization<__nv_bfloat16>(\n void* output, void* output_scale, void* input, void* input_global_scale, void* mask,\n bool use_silu_and_mul, int m_topk, int k, int n_experts, cudaStream_t stream);\n\n#endif\n\n#ifdef ENABLE_FP8\ntemplate void invokeFP4Quantization<__nv_fp8_e4m3, 16>(\n int b, int m, int n, __nv_fp8_e4m3 const* input, float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeFP4Quantization<__nv_fp8_e4m3, 32>(\n int b, int m, int n, __nv_fp8_e4m3 const* input, float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\n\n#endif\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n} // namespace kernels\n} // namespace tensorrt_llm\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda.h>\n#include <cudaTypedefs.h>\n#include <float.h>\n\n#include \"tensorrt_llm/common/assert.h\"\n#include \"tensorrt_llm/common/cudaTypeUtils.cuh\"\n#include \"tensorrt_llm/common/cudaUtils.h\"\n#include \"tensorrt_llm/common/envUtils.h\"\n#include \"tensorrt_llm/common/quantTypeUtils.cuh\"\n#include \"tensorrt_llm/common/reduceKernelUtils.cuh\"\n#include \"tensorrt_llm/kernels/quantization.cuh\"\n#include \"tensorrt_llm/kernels/quantization.h\"\n\nusing namespace tensorrt_llm::common;\n\nnamespace tensorrt_llm {\nnamespace kernels {\n\ntemplate <typename T>\nvoid invokeQuantization(int8_t* dst, T const* src, int64_t const size, float const* scalePtr,\n cudaStream_t stream, int maxGridSize) {\n TLLM_CHECK_WITH_INFO(size % 4 == 0,\n \"[ERROR][invokeQuantization] size should be a multiple of 4.\\n\");\n\n int numBlocks{static_cast<int>((size + 255) / 256)};\n dim3 grid(std::min(numBlocks, maxGridSize));\n TLLM_CHECK_WITH_INFO(grid.x <= maxGridSize,\n \"[ERROR][invokeQuantization] grid max size is exceeded\\n\");\n dim3 block(64);\n if (std::is_same_v<T, float>) {\n quantizedKernel<<<grid, block, 0, stream>>>((char4*)dst, (float4 const*)src, size / 4,\n scalePtr);\n } else if (std::is_same_v<T, half>) {\n quantizedKernel<<<grid, block, 0, stream>>>((char4*)dst, (half2 const*)src, size / 4, scalePtr);\n }\n#ifdef ENABLE_BF16\n else if (std::is_same_v<T, __nv_bfloat16>) {\n quantizedKernel<<<grid, block, 0, stream>>>((char4*)dst, (__nv_bfloat162 const*)src, size / 4,\n scalePtr);\n }\n#endif\n}\n\ntemplate void invokeQuantization<float>(int8_t* dst, float const* src, int64_t const size,\n float const* scalePtr, cudaStream_t stream,\n int maxGridSize);\n\ntemplate void invokeQuantization<half>(int8_t* dst, half const* src, int64_t const size,\n float const* scalePtr, cudaStream_t stream, int maxGridSize);\n\n#ifdef ENABLE_BF16\ntemplate void invokeQuantization<__nv_bfloat16>(int8_t* dst, __nv_bfloat16 const* src,\n int64_t const size, float const* scalePtr,\n cudaStream_t stream, int maxGridSize);\n#endif\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// Helper function for grid configuration with swizzled layouts\n\ninline int computeEffectiveRows(int m, QuantizationSFLayout layout) {\n int effectiveRows = m;\n bool isSfSwizzledLayout = (layout == QuantizationSFLayout::SWIZZLED_128x4 ||\n layout == QuantizationSFLayout::SWIZZLED_8x4);\n if (isSfSwizzledLayout) {\n int rowTile = (layout == QuantizationSFLayout::SWIZZLED_128x4) ? 128 : 8;\n int numPaddedRows = (m + rowTile - 1) / rowTile * rowTile; // Round up to rowTile\n effectiveRows = numPaddedRows;\n }\n return effectiveRows;\n}\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// MXFP8 Quantization\n\ntemplate <typename T>\nvoid invokeMxFP8Quantization(int b, int m, int n, int padded_n, T const* input, int64_t* output,\n int32_t* SFOuput, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream) {\n // Fixed SF_VEC_SIZE as 32\n // TODO: TMA quantization for MXFP8 is not supported yet because of SF_VEC_SIZE = 32.\n static constexpr int SF_VEC_SIZE = 32;\n\n // Grid, Block size.\n // Each thread converts 8 values.\n dim3 block(std::min(int(padded_n / CVT_ELTS_PER_THREAD), 512));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 2048u / block.x);\n int effectiveRows = computeEffectiveRows(m, layout);\n dim3 grid(std::min(effectiveRows, multiProcessorCount * numBlocksPerSM));\n\n // Launch the cvt kernel.\n cudaLaunchConfig_t config;\n config.gridDim = grid;\n config.blockDim = block;\n config.dynamicSmemBytes = 0;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = enable_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n cudaLaunchKernelEx(\n &config,\n quantize_with_block_size<BlockScaleQuantizationType::FP16_TO_MXFP8, T, SF_VEC_SIZE, true>, b,\n m, n, padded_n, input, nullptr, reinterpret_cast<uint32_t*>(output),\n reinterpret_cast<uint32_t*>(SFOuput), layout);\n}\n\n// Do per-token (row) quantization from fp16/bf16/fp32 to int8/fp8_e4m3.\ntemplate <typename T, typename QuantT>\nvoid invokePerTokenQuantization(QuantT* dst, T const* src, int64_t const numRows,\n int64_t const numCols, float const* clampPtr, float* scalePtr,\n float* sumPtr, QuantMode quantMode, cudaStream_t stream) {\n // each block is responsible for a single row\n dim3 const block(512);\n dim3 const grid(numRows);\n\n // The number of elements in the packed uint4 vec.\n static constexpr int NUM_ELTS_PER_VEC = sizeof(uint4) / sizeof(T);\n TLLM_CHECK_WITH_INFO(numCols % NUM_ELTS_PER_VEC == 0, \"Not supported.\");\n\n // Cache vectors to smem to avoid reloading.\n size_t const dynamicSmemSz = numCols * sizeof(T);\n // Need to check if smem capacity is enough.\n bool useSmem = true;\n if (dynamicSmemSz >= 48 * 1024) {\n cudaError_t res =\n cudaFuncSetAttribute(perTokenQuantization<T, QuantT, true>,\n cudaFuncAttributeMaxDynamicSharedMemorySize, dynamicSmemSz);\n // Fall back to reloading-reversion if smem is not enough.\n useSmem = (res == cudaSuccess);\n }\n\n // Enable min_scaling_factor if it is fp8 rowwise per-token quantization.\n bool hasFp8MinScaling = quantMode.hasFp8RowWise();\n // Do we use smem ?\n if (useSmem) {\n perTokenQuantization<T, QuantT, true><<<grid, block, dynamicSmemSz, stream>>>(\n dst, src, numRows, numCols, clampPtr, scalePtr, sumPtr, hasFp8MinScaling);\n } else {\n perTokenQuantization<T, QuantT, false><<<grid, block, 0, stream>>>(\n dst, src, numRows, numCols, clampPtr, scalePtr, sumPtr, hasFp8MinScaling);\n }\n}\n\n#define INSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(T, QuantT) \\\n template void invokePerTokenQuantization(QuantT* dst, const T* src, const int64_t numRows, \\\n const int64_t numCols, float const* clampPtr, \\\n float* scalePtr, float* sumPtr, QuantMode quantMode, \\\n cudaStream_t stream)\n\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(float, int8_t);\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(half, int8_t);\n#ifdef ENABLE_BF16\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(__nv_bfloat16, int8_t);\n#endif\n\n#ifdef ENABLE_FP8\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(float, __nv_fp8_e4m3);\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(half, __nv_fp8_e4m3);\n#ifdef ENABLE_BF16\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(__nv_bfloat16, __nv_fp8_e4m3);\n#endif\n#endif\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// TMA tensor map creation helpers\n\ntemplate <typename T>\nCUtensorMap make_3d_tma_copy_desc(T* global_address, uint64_t gmem_dim[3],\n uint64_t stride_in_bytes[2], uint32_t smem_dim[3],\n CUtensorMapSwizzle swizzle_type) {\n CUtensorMap tensor_map{};\n constexpr uint32_t rank = 3;\n uint32_t elem_strides[rank] = {1, 1, 1};\n\n // Get pointer to cuTensorMapEncodeTiled\n cudaDriverEntryPointQueryResult driver_status;\n void* cuTensorMapEncodeTiled_ptr = nullptr;\n\n#if CUDA_VERSION >= 12050\n cudaGetDriverEntryPointByVersion(\"cuTensorMapEncodeTiled\", &cuTensorMapEncodeTiled_ptr, 12000,\n cudaEnableDefault, &driver_status);\n#else\n cudaGetDriverEntryPoint(\"cuTensorMapEncodeTiled\", &cuTensorMapEncodeTiled_ptr, cudaEnableDefault,\n &driver_status);\n#endif\n\n if (driver_status != cudaDriverEntryPointSuccess) {\n TLLM_CHECK_WITH_INFO(false, \"Failed to get cuTensorMapEncodeTiled entry point\");\n }\n\n auto encode_func =\n reinterpret_cast<PFN_cuTensorMapEncodeTiled_v12000>(cuTensorMapEncodeTiled_ptr);\n\n CUtensorMapDataType data_type;\n if constexpr (std::is_same_v<T, half>) {\n data_type = CU_TENSOR_MAP_DATA_TYPE_FLOAT16;\n } else if constexpr (std::is_same_v<T, __nv_bfloat16>) {\n data_type = CU_TENSOR_MAP_DATA_TYPE_BFLOAT16;\n } else if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n data_type = CU_TENSOR_MAP_DATA_TYPE_UINT8;\n } else {\n data_type = CU_TENSOR_MAP_DATA_TYPE_UINT8;\n }\n\n CUresult result =\n encode_func(&tensor_map, data_type, rank, global_address, gmem_dim, stride_in_bytes, smem_dim,\n elem_strides, CUtensorMapInterleave::CU_TENSOR_MAP_INTERLEAVE_NONE, swizzle_type,\n CUtensorMapL2promotion::CU_TENSOR_MAP_L2_PROMOTION_NONE,\n CUtensorMapFloatOOBfill::CU_TENSOR_MAP_FLOAT_OOB_FILL_NAN_REQUEST_ZERO_FMA);\n TLLM_CHECK_WITH_INFO(result == CUDA_SUCCESS, \"Failed to encode TMA tensor map\");\n return tensor_map;\n}\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// FP4/MXFP8 Quantization\n\n// Helper function to launch TMA quantization kernel\ntemplate <BlockScaleQuantizationType quantization_type, typename T, int SF_VEC_SIZE>\nvoid launchFP4QuantizationTma(int b, int m, int n, T const* input, float const* SFScale,\n int64_t* output, int32_t* SFOuput, bool useUE8M0,\n QuantizationSFLayout layout, int multiProcessorCount, bool enable_pdl,\n cudaStream_t stream) {\n using Traits = TmaKernelTraits<T>;\n constexpr int TMA_ROW_TILE = Traits::TMA_ROW_TILE;\n constexpr int TMA_COL_TILE = Traits::TMA_COL_TILE;\n constexpr int NUM_CONSUMER_WARPS = 8;\n\n // Compute effective rows for swizzled layouts\n int effectiveRows = computeEffectiveRows(m, layout);\n\n // Grid and block configuration for TMA kernel\n // TMA kernel uses 288 threads: 1 producer warp + 8 consumer warps\n dim3 block(288);\n // Each block handles TMA_ROW_TILE rows\n int numRowTiles = (effectiveRows + TMA_ROW_TILE - 1) / TMA_ROW_TILE;\n dim3 grid(std::min(numRowTiles, multiProcessorCount * 2));\n\n // Dynamic shared memory size\n size_t smem_size = get_tma_smem_size<T>();\n\n // Create 3D TMA tensor map descriptor\n // The TMA kernel loads a box of [TMA_COL_TILE, TMA_ROW_TILE, NUM_CONSUMER_WARPS] elements per TMA\n // call Global tensor is treated as [TMA_COL_TILE, B*M, num_tiles] where num_tiles = N /\n // TMA_COL_TILE. We use b * m (not b * effectiveRows) because batches are stored contiguously\n // without padding between them.\n int num_col_tiles = (n + TMA_COL_TILE - 1) / TMA_COL_TILE;\n uint64_t gmem_dim[3] = {\n static_cast<uint64_t>(TMA_COL_TILE), // Elements per tile (contiguous in memory)\n static_cast<uint64_t>(b * m), // Total rows across all batches\n static_cast<uint64_t>(num_col_tiles) // Number of column tiles\n };\n uint64_t stride_in_bytes[2] = {\n static_cast<uint64_t>(n * sizeof(T)), // Stride between rows (in bytes)\n static_cast<uint64_t>(TMA_COL_TILE * sizeof(T)) // Stride between tiles (in bytes)\n };\n uint32_t smem_dim[3] = {\n static_cast<uint32_t>(TMA_COL_TILE), // Elements loaded per tile\n static_cast<uint32_t>(TMA_ROW_TILE), // Rows loaded per TMA call\n static_cast<uint32_t>(NUM_CONSUMER_WARPS) // Number of tiles loaded (for 8 consumer warps)\n };\n\n // CUtensorMap must be 64-byte aligned\n // Use SWIZZLE_128B for half/bf16 (2-byte types), SWIZZLE_NONE for FP8 (1-byte types)\n constexpr CUtensorMapSwizzle swizzle_type =\n (std::is_same_v<T, half> || std::is_same_v<T, __nv_bfloat16>)\n ? CUtensorMapSwizzle::CU_TENSOR_MAP_SWIZZLE_128B\n : CUtensorMapSwizzle::CU_TENSOR_MAP_SWIZZLE_NONE;\n alignas(64) CUtensorMap tensor_map = make_3d_tma_copy_desc(\n const_cast<T*>(input), gmem_dim, stride_in_bytes, smem_dim, swizzle_type);\n\n // Select and launch the TMA kernel\n auto* kernel_instance =\n useUE8M0 ? &quantize_with_block_size_tma<quantization_type, T, SF_VEC_SIZE, true>\n : &quantize_with_block_size_tma<quantization_type, T, SF_VEC_SIZE, false>;\n\n // Set max dynamic shared memory for the kernel (required for > 48KB)\n cudaFuncSetAttribute(kernel_instance, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size);\n\n cudaLaunchConfig_t config;\n config.gridDim = grid;\n config.blockDim = block;\n config.dynamicSmemBytes = smem_size;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = enable_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n cudaLaunchKernelEx(&config, kernel_instance, b, m, n, n, input, SFScale,\n reinterpret_cast<uint32_t*>(output), reinterpret_cast<uint32_t*>(SFOuput),\n layout, tensor_map);\n}\n\ntemplate <typename T, int SF_VEC_SIZE>\nvoid invokeFP4Quantization(int b, int m, int n, T const* input, float const* SFScale,\n int64_t* output, int32_t* SFOuput, bool useUE8M0,\n QuantizationSFLayout layout, int multiProcessorCount, bool enable_pdl,\n cudaStream_t stream) {\n#ifdef ENABLE_FP8\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n // Use TMA kernel for large m (high throughput mode)\n // TODO: fix the issue when n is not a multiple of NUM_CONSUMER_WARPS * TMA_COL_TILE\n constexpr int TMA_COL_CHUNK = 8 * 64; // NUM_CONSUMER_WARPS * TMA_COL_TILE\n if constexpr (SF_VEC_SIZE == 16) {\n if (SF_VEC_SIZE == 16 && m >= 1024 && n % TMA_COL_CHUNK == 0) {\n launchFP4QuantizationTma<BlockScaleQuantizationType::FP8_TO_FP4, T, SF_VEC_SIZE>(\n b, m, n, input, SFScale, output, SFOuput, useUE8M0, layout, multiProcessorCount,\n enable_pdl, stream);\n return;\n }\n }\n // Original non-TMA path for small m or SF_VEC_SIZE != 16\n // Grid, Block size.\n // Each thread converts 16 values.\n dim3 block(std::min(int(n / CVT_FP8_TO_FP4_ELTS_PER_THREAD), 512));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 2048u / block.x);\n int effectiveRows = computeEffectiveRows(m, layout);\n dim3 grid(std::min(effectiveRows, multiProcessorCount * numBlocksPerSM));\n\n // Launch the cvt kernel.\n auto* kernel_instance = useUE8M0\n ? &quantize_with_block_size<BlockScaleQuantizationType::FP8_TO_FP4,\n T, SF_VEC_SIZE, true>\n : &quantize_with_block_size<BlockScaleQuantizationType::FP8_TO_FP4,\n T, SF_VEC_SIZE, false>;\n kernel_instance<<<grid, block, 0, stream>>>(b, m, n, n, input, SFScale,\n reinterpret_cast<uint32_t*>(output),\n reinterpret_cast<uint32_t*>(SFOuput), layout);\n } else\n#endif\n {\n // Use TMA kernel for large m (high throughput mode)\n // TODO: fix the issue when n is not a multiple of NUM_CONSUMER_WARPS * TMA_COL_TILE\n constexpr int TMA_COL_CHUNK = 8 * 64; // NUM_CONSUMER_WARPS * TMA_COL_TILE\n if constexpr (SF_VEC_SIZE == 16) {\n if (SF_VEC_SIZE == 16 && m >= 1024 && n % TMA_COL_CHUNK == 0) {\n launchFP4QuantizationTma<BlockScaleQuantizationType::FP16_TO_FP4, T, SF_VEC_SIZE>(\n b, m, n, input, SFScale, output, SFOuput, useUE8M0, layout, multiProcessorCount,\n enable_pdl, stream);\n return;\n }\n }\n // Original non-TMA path for small m or SF_VEC_SIZE != 16\n // Grid, Block size.\n // Each thread converts 8 values.\n dim3 block(std::min(int(n / CVT_ELTS_PER_THREAD), 512));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 2048u / block.x);\n int effectiveRows = computeEffectiveRows(m, layout);\n dim3 grid(std::min(effectiveRows, multiProcessorCount * numBlocksPerSM));\n\n // Launch the cvt kernel.\n auto* kernel_instance = useUE8M0\n ? &quantize_with_block_size<BlockScaleQuantizationType::FP16_TO_FP4,\n T, SF_VEC_SIZE, true>\n : &quantize_with_block_size<BlockScaleQuantizationType::FP16_TO_FP4,\n T, SF_VEC_SIZE, false>;\n\n cudaLaunchConfig_t config;\n config.gridDim = grid;\n config.blockDim = block;\n config.dynamicSmemBytes = 0;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = enable_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n cudaLaunchKernelEx(&config, kernel_instance, b, m, n, n, input, SFScale,\n reinterpret_cast<uint32_t*>(output), reinterpret_cast<uint32_t*>(SFOuput),\n layout);\n }\n}\n\ntemplate <typename T>\n__global__ void block_scale_interleave_kernel(int numBatches, int numRows, int numRowsPadded,\n int numCols, int numColsPadded, T const* SFIn,\n T* SFOutput) {\n for (int rowIdx = blockIdx.x; rowIdx < numRowsPadded; rowIdx += gridDim.x) {\n for (int batchIdx = 0; batchIdx < numBatches; batchIdx++) {\n for (int colIdx = threadIdx.x; colIdx < numColsPadded; colIdx += blockDim.x) {\n T sf = 0;\n if (rowIdx < numRows && colIdx < numCols) {\n int64_t inOffset = batchIdx * numRows * numCols + rowIdx * numCols + colIdx;\n sf = SFIn[inOffset];\n }\n\n std::optional<int> batchIdxOpt = batchIdx;\n std::optional<int> numRowsOpt = numRows;\n\n // Without batching, the math in get_sf_out_offset is the same as\n // int const numSfTilesK = (numCols + 4 - 1) / 4;\n // int const tileOffset = ((mi / 128) * numSfTilesK + ki / 4) * 512;\n // int const dstIdx = tileOffset + (mi % 32) * 16 + ((mi % 128) / 32) * 4 + ki % 4;\n auto dstIdx = get_sf_out_offset_128x4(batchIdxOpt, rowIdx, colIdx, numRowsOpt, numCols);\n SFOutput[dstIdx] = sf;\n }\n }\n }\n}\n\n__global__ void block_scale_interleave_reverse_kernel(int numBatches, int numRows, int numCols,\n uint8_t const* SFIn, uint8_t* SFOutput) {\n for (int rowIdx = blockIdx.x; rowIdx < numRows; rowIdx += gridDim.x) {\n for (int batchIdx = 0; batchIdx < numBatches; batchIdx++) {\n for (int colIdx = threadIdx.x; colIdx < numCols; colIdx += blockDim.x) {\n std::optional<int> batchIdxOpt = batchIdx;\n std::optional<int> numRowsOpt = numRows;\n\n // Get the swizzled input index using the same swizzling pattern\n auto srcIdx = get_sf_out_offset_128x4(batchIdxOpt, rowIdx, colIdx, numRowsOpt, numCols);\n auto sf = SFIn[srcIdx];\n\n // Output goes to linear layout\n int64_t outOffset = batchIdx * numRows * numCols + rowIdx * numCols + colIdx;\n SFOutput[outOffset] = sf;\n }\n }\n }\n}\n\n// This is intended for weight loading, so m and n are large, b <= 256\ntemplate <typename T>\nvoid invokeBlockScaleInterleave(int b, int m, int m_padded, int n, int n_padded, T const* SFIn,\n T* SFOutput, int multiProcessorCount, cudaStream_t stream) {\n // Each thread reads 1 int8 value\n dim3 block(std::min(n_padded, 1024));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 4096u / block.x);\n dim3 grid(std::min(m_padded, multiProcessorCount * numBlocksPerSM));\n\n block_scale_interleave_kernel<T>\n <<<grid, block, 0, stream>>>(b, m, m_padded, n, n_padded, SFIn, SFOutput);\n}\n\n// Explicit template instantiations for the types used by other compilation units\ntemplate void invokeBlockScaleInterleave<uint8_t>(int b, int m, int m_padded, int n, int n_padded,\n uint8_t const* SFIn, uint8_t* SFOutput,\n int multiProcessorCount, cudaStream_t stream);\ntemplate void invokeBlockScaleInterleave<__nv_bfloat16>(int b, int m, int m_padded, int n,\n int n_padded, __nv_bfloat16 const* SFIn,\n __nv_bfloat16* SFOutput,\n int multiProcessorCount,\n cudaStream_t stream);\n\n// This is intended for weight loading, so m and n are large, b <= 256\nvoid invokeBlockScaleInterleaveReverse(int b, int m, int n, uint8_t const* SFIn, uint8_t* SFOutput,\n int multiProcessorCount, cudaStream_t stream) {\n // Each thread reads 1 int8 value\n dim3 block(std::min(n, 1024));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 4096u / block.x);\n dim3 grid(std::min(m, multiProcessorCount * numBlocksPerSM));\n\n block_scale_interleave_reverse_kernel<<<grid, block, 0, stream>>>(b, m, n, SFIn, SFOutput);\n}\n\ntemplate <typename T>\nvoid invokeSiluAndMulNVFP4Quantization(void* output, void* output_scale, void* input,\n void* input_global_scale, void* mask, bool use_silu_and_mul,\n int m_topk, int k, int n_experts, cudaStream_t stream) {\n int device;\n TLLM_CUDA_CHECK(cudaGetDevice(&device));\n int multiProcessorCount;\n TLLM_CUDA_CHECK(\n cudaDeviceGetAttribute(&multiProcessorCount, cudaDevAttrMultiProcessorCount, device));\n\n // Grid, Block size.\n // Each thread converts 8 values.\n TLLM_CHECK_WITH_INFO(k > 0, \"k must be > 0\");\n int const workSizePerRow = max(1, k / CVT_ELTS_PER_THREAD);\n int const totalWorkSize = m_topk * workSizePerRow;\n dim3 block(std::min(workSizePerRow, 512));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = 2048 / block.x;\n dim3 grid(std::min(static_cast<int>((totalWorkSize + block.x - 1) / block.x),\n multiProcessorCount * numBlocksPerSM));\n while (grid.x <= multiProcessorCount && block.x > 64) {\n grid.x *= 2;\n block.x = (block.x + 1) / 2;\n }\n\n // TODO(kaixih@nvidia): Should relax this to allow any grid size.\n // shuw@nvidia.com: only deal with mask case\n TLLM_CHECK_WITH_INFO(mask != nullptr, \"mask must be non-null for expert NVFP4 path\");\n TLLM_CHECK_WITH_INFO(n_experts > 0, \"n_experts must be > 0\");\n grid.x = (grid.x + n_experts - 1) / n_experts * n_experts;\n cvt_fp16_to_fp4_expert<T, false><<<grid, block, 0, stream>>>(\n m_topk, k, reinterpret_cast<T*>(input), reinterpret_cast<float*>(input_global_scale),\n reinterpret_cast<uint32_t*>(output), reinterpret_cast<uint32_t*>(output_scale),\n reinterpret_cast<int32_t*>(mask), use_silu_and_mul, n_experts);\n return;\n}\n\n// Instantiate the function.\ntemplate void invokeFP4Quantization<half, 16>(int b, int m, int n, half const* input,\n float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0,\n QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeFP4Quantization<half, 32>(int b, int m, int n, half const* input,\n float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0,\n QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeMxFP8Quantization<half>(int b, int m, int n, int padded_n, half const* input,\n int64_t* output, int32_t* SFOuput,\n QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeSiluAndMulNVFP4Quantization<half>(void* output, void* output_scale, void* input,\n void* input_global_scale, void* mask,\n bool use_silu_and_mul, int m_topk, int k,\n int n_experts, cudaStream_t stream);\n\n#ifdef ENABLE_BF16\ntemplate void invokeFP4Quantization<__nv_bfloat16, 16>(\n int b, int m, int n, __nv_bfloat16 const* input, float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeFP4Quantization<__nv_bfloat16, 32>(\n int b, int m, int n, __nv_bfloat16 const* input, float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeMxFP8Quantization<__nv_bfloat16>(int b, int m, int n, int padded_n,\n __nv_bfloat16 const* input, int64_t* output,\n int32_t* SFOuput, QuantizationSFLayout layout,\n int multiProcessorCount, bool enable_pdl,\n cudaStream_t stream);\ntemplate void invokeSiluAndMulNVFP4Quantization<__nv_bfloat16>(\n void* output, void* output_scale, void* input, void* input_global_scale, void* mask,\n bool use_silu_and_mul, int m_topk, int k, int n_experts, cudaStream_t stream);\n\n#endif\n\n#ifdef ENABLE_FP8\ntemplate void invokeFP4Quantization<__nv_fp8_e4m3, 16>(\n int b, int m, int n, __nv_fp8_e4m3 const* input, float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeFP4Quantization<__nv_fp8_e4m3, 32>(\n int b, int m, int n, __nv_fp8_e4m3 const* input, float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\n\n#endif\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n} // namespace kernels\n} // namespace tensorrt_llm\n"},"diff":{"kind":"string","value":"--- csrc/nv_internal/cpp/kernels/quantization.cu\n+++ csrc/nv_internal/cpp/kernels/quantization.cu\n@@ -14,6 +14,8 @@\n * limitations under the License.\n */\n \n+#include <cuda.h>\n+#include <cudaTypedefs.h>\n #include <float.h>\n \n #include \"tensorrt_llm/common/assert.h\"\n@@ -93,6 +95,7 @@\n int32_t* SFOuput, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream) {\n // Fixed SF_VEC_SIZE as 32\n+ // TODO: TMA quantization for MXFP8 is not supported yet because of SF_VEC_SIZE = 32.\n static constexpr int SF_VEC_SIZE = 32;\n \n // Grid, Block size.\n@@ -179,7 +182,134 @@\n #endif\n \n ////////////////////////////////////////////////////////////////////////////////////////////////////\n+// TMA tensor map creation helpers\n+\n+template <typename T>\n+CUtensorMap make_3d_tma_copy_desc(T* global_address, uint64_t gmem_dim[3],\n+ uint64_t stride_in_bytes[2], uint32_t smem_dim[3],\n+ CUtensorMapSwizzle swizzle_type) {\n+ CUtensorMap tensor_map{};\n+ constexpr uint32_t rank = 3;\n+ uint32_t elem_strides[rank] = {1, 1, 1};\n+\n+ // Get pointer to cuTensorMapEncodeTiled\n+ cudaDriverEntryPointQueryResult driver_status;\n+ void* cuTensorMapEncodeTiled_ptr = nullptr;\n+\n+#if CUDA_VERSION >= 12050\n+ cudaGetDriverEntryPointByVersion(\"cuTensorMapEncodeTiled\", &cuTensorMapEncodeTiled_ptr, 12000,\n+ cudaEnableDefault, &driver_status);\n+#else\n+ cudaGetDriverEntryPoint(\"cuTensorMapEncodeTiled\", &cuTensorMapEncodeTiled_ptr, cudaEnableDefault,\n+ &driver_status);\n+#endif\n+\n+ if (driver_status != cudaDriverEntryPointSuccess) {\n+ TLLM_CHECK_WITH_INFO(false, \"Failed to get cuTensorMapEncodeTiled entry point\");\n+ }\n+\n+ auto encode_func =\n+ reinterpret_cast<PFN_cuTensorMapEncodeTiled_v12000>(cuTensorMapEncodeTiled_ptr);\n+\n+ CUtensorMapDataType data_type;\n+ if constexpr (std::is_same_v<T, half>) {\n+ data_type = CU_TENSOR_MAP_DATA_TYPE_FLOAT16;\n+ } else if constexpr (std::is_same_v<T, __nv_bfloat16>) {\n+ data_type = CU_TENSOR_MAP_DATA_TYPE_BFLOAT16;\n+ } else if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n+ data_type = CU_TENSOR_MAP_DATA_TYPE_UINT8;\n+ } else {\n+ data_type = CU_TENSOR_MAP_DATA_TYPE_UINT8;\n+ }\n+\n+ CUresult result =\n+ encode_func(&tensor_map, data_type, rank, global_address, gmem_dim, stride_in_bytes, smem_dim,\n+ elem_strides, CUtensorMapInterleave::CU_TENSOR_MAP_INTERLEAVE_NONE, swizzle_type,\n+ CUtensorMapL2promotion::CU_TENSOR_MAP_L2_PROMOTION_NONE,\n+ CUtensorMapFloatOOBfill::CU_TENSOR_MAP_FLOAT_OOB_FILL_NAN_REQUEST_ZERO_FMA);\n+ TLLM_CHECK_WITH_INFO(result == CUDA_SUCCESS, \"Failed to encode TMA tensor map\");\n+ return tensor_map;\n+}\n+\n+////////////////////////////////////////////////////////////////////////////////////////////////////\n // FP4/MXFP8 Quantization\n+\n+// Helper function to launch TMA quantization kernel\n+template <BlockScaleQuantizationType quantization_type, typename T, int SF_VEC_SIZE>\n+void launchFP4QuantizationTma(int b, int m, int n, T const* input, float const* SFScale,\n+ int64_t* output, int32_t* SFOuput, bool useUE8M0,\n+ QuantizationSFLayout layout, int multiProcessorCount, bool enable_pdl,\n+ cudaStream_t stream) {\n+ using Traits = TmaKernelTraits<T>;\n+ constexpr int TMA_ROW_TILE = Traits::TMA_ROW_TILE;\n+ constexpr int TMA_COL_TILE = Traits::TMA_COL_TILE;\n+ constexpr int NUM_CONSUMER_WARPS = 8;\n+\n+ // Compute effective rows for swizzled layouts\n+ int effectiveRows = computeEffectiveRows(m, layout);\n+\n+ // Grid and block configuration for TMA kernel\n+ // TMA kernel uses 288 threads: 1 producer warp + 8 consumer warps\n+ dim3 block(288);\n+ // Each block handles TMA_ROW_TILE rows\n+ int numRowTiles = (effectiveRows + TMA_ROW_TILE - 1) / TMA_ROW_TILE;\n+ dim3 grid(std::min(numRowTiles, multiProcessorCount * 2));\n+\n+ // Dynamic shared memory size\n+ size_t smem_size = get_tma_smem_size<T>();\n+\n+ // Create 3D TMA tensor map descriptor\n+ // The TMA kernel loads a box of [TMA_COL_TILE, TMA_ROW_TILE, NUM_CONSUMER_WARPS] elements per TMA\n+ // call Global tensor is treated as [TMA_COL_TILE, B*M, num_tiles] where num_tiles = N /\n+ // TMA_COL_TILE. We use b * m (not b * effectiveRows) because batches are stored contiguously\n+ // without padding between them.\n+ int num_col_tiles = (n + TMA_COL_TILE - 1) / TMA_COL_TILE;\n+ uint64_t gmem_dim[3] = {\n+ static_cast<uint64_t>(TMA_COL_TILE), // Elements per tile (contiguous in memory)\n+ static_cast<uint64_t>(b * m), // Total rows across all batches\n+ static_cast<uint64_t>(num_col_tiles) // Number of column tiles\n+ };\n+ uint64_t stride_in_bytes[2] = {\n+ static_cast<uint64_t>(n * sizeof(T)), // Stride between rows (in bytes)\n+ static_cast<uint64_t>(TMA_COL_TILE * sizeof(T)) // Stride between tiles (in bytes)\n+ };\n+ uint32_t smem_dim[3] = {\n+ static_cast<uint32_t>(TMA_COL_TILE), // Elements loaded per tile\n+ static_cast<uint32_t>(TMA_ROW_TILE), // Rows loaded per TMA call\n+ static_cast<uint32_t>(NUM_CONSUMER_WARPS) // Number of tiles loaded (for 8 consumer warps)\n+ };\n+\n+ // CUtensorMap must be 64-byte aligned\n+ // Use SWIZZLE_128B for half/bf16 (2-byte types), SWIZZLE_NONE for FP8 (1-byte types)\n+ constexpr CUtensorMapSwizzle swizzle_type =\n+ (std::is_same_v<T, half> || std::is_same_v<T, __nv_bfloat16>)\n+ ? CUtensorMapSwizzle::CU_TENSOR_MAP_SWIZZLE_128B\n+ : CUtensorMapSwizzle::CU_TENSOR_MAP_SWIZZLE_NONE;\n+ alignas(64) CUtensorMap tensor_map = make_3d_tma_copy_desc(\n+ const_cast<T*>(input), gmem_dim, stride_in_bytes, smem_dim, swizzle_type);\n+\n+ // Select and launch the TMA kernel\n+ auto* kernel_instance =\n+ useUE8M0 ? &quantize_with_block_size_tma<quantization_type, T, SF_VEC_SIZE, true>\n+ : &quantize_with_block_size_tma<quantization_type, T, SF_VEC_SIZE, false>;\n+\n+ // Set max dynamic shared memory for the kernel (required for > 48KB)\n+ cudaFuncSetAttribute(kernel_instance, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size);\n+\n+ cudaLaunchConfig_t config;\n+ config.gridDim = grid;\n+ config.blockDim = block;\n+ config.dynamicSmemBytes = smem_size;\n+ config.stream = stream;\n+ cudaLaunchAttribute attrs[1];\n+ attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n+ attrs[0].val.programmaticStreamSerializationAllowed = enable_pdl;\n+ config.numAttrs = 1;\n+ config.attrs = attrs;\n+ cudaLaunchKernelEx(&config, kernel_instance, b, m, n, n, input, SFScale,\n+ reinterpret_cast<uint32_t*>(output), reinterpret_cast<uint32_t*>(SFOuput),\n+ layout, tensor_map);\n+}\n \n template <typename T, int SF_VEC_SIZE>\n void invokeFP4Quantization(int b, int m, int n, T const* input, float const* SFScale,\n@@ -188,6 +318,18 @@\n cudaStream_t stream) {\n #ifdef ENABLE_FP8\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n+ // Use TMA kernel for large m (high throughput mode)\n+ // TODO: fix the issue when n is not a multiple of NUM_CONSUMER_WARPS * TMA_COL_TILE\n+ constexpr int TMA_COL_CHUNK = 8 * 64; // NUM_CONSUMER_WARPS * TMA_COL_TILE\n+ if constexpr (SF_VEC_SIZE == 16) {\n+ if (SF_VEC_SIZE == 16 && m >= 1024 && n % TMA_COL_CHUNK == 0) {\n+ launchFP4QuantizationTma<BlockScaleQuantizationType::FP8_TO_FP4, T, SF_VEC_SIZE>(\n+ b, m, n, input, SFScale, output, SFOuput, useUE8M0, layout, multiProcessorCount,\n+ enable_pdl, stream);\n+ return;\n+ }\n+ }\n+ // Original non-TMA path for small m or SF_VEC_SIZE != 16\n // Grid, Block size.\n // Each thread converts 16 values.\n dim3 block(std::min(int(n / CVT_FP8_TO_FP4_ELTS_PER_THREAD), 512));\n@@ -205,10 +347,21 @@\n kernel_instance<<<grid, block, 0, stream>>>(b, m, n, n, input, SFScale,\n reinterpret_cast<uint32_t*>(output),\n reinterpret_cast<uint32_t*>(SFOuput), layout);\n-\n } else\n #endif\n {\n+ // Use TMA kernel for large m (high throughput mode)\n+ // TODO: fix the issue when n is not a multiple of NUM_CONSUMER_WARPS * TMA_COL_TILE\n+ constexpr int TMA_COL_CHUNK = 8 * 64; // NUM_CONSUMER_WARPS * TMA_COL_TILE\n+ if constexpr (SF_VEC_SIZE == 16) {\n+ if (SF_VEC_SIZE == 16 && m >= 1024 && n % TMA_COL_CHUNK == 0) {\n+ launchFP4QuantizationTma<BlockScaleQuantizationType::FP16_TO_FP4, T, SF_VEC_SIZE>(\n+ b, m, n, input, SFScale, output, SFOuput, useUE8M0, layout, multiProcessorCount,\n+ enable_pdl, stream);\n+ return;\n+ }\n+ }\n+ // Original non-TMA path for small m or SF_VEC_SIZE != 16\n // Grid, Block size.\n // Each thread converts 8 values.\n dim3 block(std::min(int(n / CVT_ELTS_PER_THREAD), 512));"},"lines_added":{"kind":"number","value":154,"string":"154"},"lines_removed":{"kind":"number","value":1,"string":"1"},"files_in_commit":{"kind":"number","value":3,"string":"3"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/nv_internal/cpp/kernels/quantization.cu).\n\nGoal: Optimize quantization function in large problem size\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <float.h>\n\n#include \"tensorrt_llm/common/assert.h\"\n#include \"tensorrt_llm/common/cudaTypeUtils.cuh\"\n#include \"tensorrt_llm/common/cudaUtils.h\"\n#include \"tensorrt_llm/common/envUtils.h\"\n#include \"tensorrt_llm/common/quantTypeUtils.cuh\"\n#include \"tensorrt_llm/common/reduceKernelUtils.cuh\"\n#include \"tensorrt_llm/kernels/quantization.cuh\"\n#include \"tensorrt_llm/kernels/quantization.h\"\n\nusing namespace tensorrt_llm::common;\n\nnamespace tensorrt_llm {\nnamespace kernels {\n\ntemplate <typename T>\nvoid invokeQuantization(int8_t* dst, T const* src, int64_t const size, float const* scalePtr,\n cudaStream_t stream, int maxGridSize) {\n TLLM_CHECK_WITH_INFO(size % 4 == 0,\n \"[ERROR][invokeQuantization] size should be a multiple of 4.\\n\");\n\n int numBlocks{static_cast<int>((size + 255) / 256)};\n dim3 grid(std::min(numBlocks, maxGridSize));\n TLLM_CHECK_WITH_INFO(grid.x <= maxGridSize,\n \"[ERROR][invokeQuantization] grid max size is exceeded\\n\");\n dim3 block(64);\n if (std::is_same_v<T, float>) {\n quantizedKernel<<<grid, block, 0, stream>>>((char4*)dst, (float4 const*)src, size / 4,\n scalePtr);\n } else if (std::is_same_v<T, half>) {\n quantizedKernel<<<grid, block, 0, stream>>>((char4*)dst, (half2 const*)src, size / 4, scalePtr);\n }\n#ifdef ENABLE_BF16\n else if (std::is_same_v<T, __nv_bfloat16>) {\n quantizedKernel<<<grid, block, 0, stream>>>((char4*)dst, (__nv_bfloat162 const*)src, size / 4,\n scalePtr);\n }\n#endif\n}\n\ntemplate void invokeQuantization<float>(int8_t* dst, float const* src, int64_t const size,\n float const* scalePtr, cudaStream_t stream,\n int maxGridSize);\n\ntemplate void invokeQuantization<half>(int8_t* dst, half const* src, int64_t const size,\n float const* scalePtr, cudaStream_t stream, int maxGridSize);\n\n#ifdef ENABLE_BF16\ntemplate void invokeQuantization<__nv_bfloat16>(int8_t* dst, __nv_bfloat16 const* src,\n int64_t const size, float const* scalePtr,\n cudaStream_t stream, int maxGridSize);\n#endif\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// Helper function for grid configuration with swizzled layouts\n\ninline int computeEffectiveRows(int m, QuantizationSFLayout layout) {\n int effectiveRows = m;\n bool isSfSwizzledLayout = (layout == QuantizationSFLayout::SWIZZLED_128x4 ||\n layout == QuantizationSFLayout::SWIZZLED_8x4);\n if (isSfSwizzledLayout) {\n int rowTile = (layout == QuantizationSFLayout::SWIZZLED_128x4) ? 128 : 8;\n int numPaddedRows = (m + rowTile - 1) / rowTile * rowTile; // Round up to rowTile\n effectiveRows = numPaddedRows;\n }\n return effectiveRows;\n}\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// MXFP8 Quantization\n\ntemplate <typename T>\nvoid invokeMxFP8Quantization(int b, int m, int n, int padded_n, T const* input, int64_t* output,\n int32_t* SFOuput, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream) {\n // Fixed SF_VEC_SIZE as 32\n static constexpr int SF_VEC_SIZE = 32;\n\n // Grid, Block size.\n // Each thread converts 8 values.\n dim3 block(std::min(int(padded_n / CVT_ELTS_PER_THREAD), 512));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 2048u / block.x);\n int effectiveRows = computeEffectiveRows(m, layout);\n dim3 grid(std::min(effectiveRows, multiProcessorCount * numBlocksPerSM));\n\n // Launch the cvt kernel.\n cudaLaunchConfig_t config;\n config.gridDim = grid;\n config.blockDim = block;\n config.dynamicSmemBytes = 0;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = enable_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n cudaLaunchKernelEx(\n &config,\n quantize_with_block_size<BlockScaleQuantizationType::FP16_TO_MXFP8, T, SF_VEC_SIZE, true>, b,\n m, n, padded_n, input, nullptr, reinterpret_cast<uint32_t*>(output),\n reinterpret_cast<uint32_t*>(SFOuput), layout);\n}\n\n// Do per-token (row) quantization from fp16/bf16/fp32 to int8/fp8_e4m3.\ntemplate <typename T, typename QuantT>\nvoid invokePerTokenQuantization(QuantT* dst, T const* src, int64_t const numRows,\n int64_t const numCols, float const* clampPtr, float* scalePtr,\n float* sumPtr, QuantMode quantMode, cudaStream_t stream) {\n // each block is responsible for a single row\n dim3 const block(512);\n dim3 const grid(numRows);\n\n // The number of elements in the packed uint4 vec.\n static constexpr int NUM_ELTS_PER_VEC = sizeof(uint4) / sizeof(T);\n TLLM_CHECK_WITH_INFO(numCols % NUM_ELTS_PER_VEC == 0, \"Not supported.\");\n\n // Cache vectors to smem to avoid reloading.\n size_t const dynamicSmemSz = numCols * sizeof(T);\n // Need to check if smem capacity is enough.\n bool useSmem = true;\n if (dynamicSmemSz >= 48 * 1024) {\n cudaError_t res =\n cudaFuncSetAttribute(perTokenQuantization<T, QuantT, true>,\n cudaFuncAttributeMaxDynamicSharedMemorySize, dynamicSmemSz);\n // Fall back to reloading-reversion if smem is not enough.\n useSmem = (res == cudaSuccess);\n }\n\n // Enable min_scaling_factor if it is fp8 rowwise per-token quantization.\n bool hasFp8MinScaling = quantMode.hasFp8RowWise();\n // Do we use smem ?\n if (useSmem) {\n perTokenQuantization<T, QuantT, true><<<grid, block, dynamicSmemSz, stream>>>(\n dst, src, numRows, numCols, clampPtr, scalePtr, sumPtr, hasFp8MinScaling);\n } else {\n perTokenQuantization<T, QuantT, false><<<grid, block, 0, stream>>>(\n dst, src, numRows, numCols, clampPtr, scalePtr, sumPtr, hasFp8MinScaling);\n }\n}\n\n#define INSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(T, QuantT) \\\n template void invokePerTokenQuantization(QuantT* dst, const T* src, const int64_t numRows, \\\n const int64_t numCols, float const* clampPtr, \\\n float* scalePtr, float* sumPtr, QuantMode quantMode, \\\n cudaStream_t stream)\n\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(float, int8_t);\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(half, int8_t);\n#ifdef ENABLE_BF16\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(__nv_bfloat16, int8_t);\n#endif\n\n#ifdef ENABLE_FP8\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(float, __nv_fp8_e4m3);\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(half, __nv_fp8_e4m3);\n#ifdef ENABLE_BF16\nINSTANTIATE_INVOKE_PER_TOKEN_QUANTIZATION(__nv_bfloat16, __nv_fp8_e4m3);\n#endif\n#endif\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// FP4/MXFP8 Quantization\n\ntemplate <typename T, int SF_VEC_SIZE>\nvoid invokeFP4Quantization(int b, int m, int n, T const* input, float const* SFScale,\n int64_t* output, int32_t* SFOuput, bool useUE8M0,\n QuantizationSFLayout layout, int multiProcessorCount, bool enable_pdl,\n cudaStream_t stream) {\n#ifdef ENABLE_FP8\n if constexpr (std::is_same_v<T, __nv_fp8_e4m3>) {\n // Grid, Block size.\n // Each thread converts 16 values.\n dim3 block(std::min(int(n / CVT_FP8_TO_FP4_ELTS_PER_THREAD), 512));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 2048u / block.x);\n int effectiveRows = computeEffectiveRows(m, layout);\n dim3 grid(std::min(effectiveRows, multiProcessorCount * numBlocksPerSM));\n\n // Launch the cvt kernel.\n auto* kernel_instance = useUE8M0\n ? &quantize_with_block_size<BlockScaleQuantizationType::FP8_TO_FP4,\n T, SF_VEC_SIZE, true>\n : &quantize_with_block_size<BlockScaleQuantizationType::FP8_TO_FP4,\n T, SF_VEC_SIZE, false>;\n kernel_instance<<<grid, block, 0, stream>>>(b, m, n, n, input, SFScale,\n reinterpret_cast<uint32_t*>(output),\n reinterpret_cast<uint32_t*>(SFOuput), layout);\n\n } else\n#endif\n {\n // Grid, Block size.\n // Each thread converts 8 values.\n dim3 block(std::min(int(n / CVT_ELTS_PER_THREAD), 512));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 2048u / block.x);\n int effectiveRows = computeEffectiveRows(m, layout);\n dim3 grid(std::min(effectiveRows, multiProcessorCount * numBlocksPerSM));\n\n // Launch the cvt kernel.\n auto* kernel_instance = useUE8M0\n ? &quantize_with_block_size<BlockScaleQuantizationType::FP16_TO_FP4,\n T, SF_VEC_SIZE, true>\n : &quantize_with_block_size<BlockScaleQuantizationType::FP16_TO_FP4,\n T, SF_VEC_SIZE, false>;\n\n cudaLaunchConfig_t config;\n config.gridDim = grid;\n config.blockDim = block;\n config.dynamicSmemBytes = 0;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = enable_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n cudaLaunchKernelEx(&config, kernel_instance, b, m, n, n, input, SFScale,\n reinterpret_cast<uint32_t*>(output), reinterpret_cast<uint32_t*>(SFOuput),\n layout);\n }\n}\n\ntemplate <typename T>\n__global__ void block_scale_interleave_kernel(int numBatches, int numRows, int numRowsPadded,\n int numCols, int numColsPadded, T const* SFIn,\n T* SFOutput) {\n for (int rowIdx = blockIdx.x; rowIdx < numRowsPadded; rowIdx += gridDim.x) {\n for (int batchIdx = 0; batchIdx < numBatches; batchIdx++) {\n for (int colIdx = threadIdx.x; colIdx < numColsPadded; colIdx += blockDim.x) {\n T sf = 0;\n if (rowIdx < numRows && colIdx < numCols) {\n int64_t inOffset = batchIdx * numRows * numCols + rowIdx * numCols + colIdx;\n sf = SFIn[inOffset];\n }\n\n std::optional<int> batchIdxOpt = batchIdx;\n std::optional<int> numRowsOpt = numRows;\n\n // Without batching, the math in get_sf_out_offset is the same as\n // int const numSfTilesK = (numCols + 4 - 1) / 4;\n // int const tileOffset = ((mi / 128) * numSfTilesK + ki / 4) * 512;\n // int const dstIdx = tileOffset + (mi % 32) * 16 + ((mi % 128) / 32) * 4 + ki % 4;\n auto dstIdx = get_sf_out_offset_128x4(batchIdxOpt, rowIdx, colIdx, numRowsOpt, numCols);\n SFOutput[dstIdx] = sf;\n }\n }\n }\n}\n\n__global__ void block_scale_interleave_reverse_kernel(int numBatches, int numRows, int numCols,\n uint8_t const* SFIn, uint8_t* SFOutput) {\n for (int rowIdx = blockIdx.x; rowIdx < numRows; rowIdx += gridDim.x) {\n for (int batchIdx = 0; batchIdx < numBatches; batchIdx++) {\n for (int colIdx = threadIdx.x; colIdx < numCols; colIdx += blockDim.x) {\n std::optional<int> batchIdxOpt = batchIdx;\n std::optional<int> numRowsOpt = numRows;\n\n // Get the swizzled input index using the same swizzling pattern\n auto srcIdx = get_sf_out_offset_128x4(batchIdxOpt, rowIdx, colIdx, numRowsOpt, numCols);\n auto sf = SFIn[srcIdx];\n\n // Output goes to linear layout\n int64_t outOffset = batchIdx * numRows * numCols + rowIdx * numCols + colIdx;\n SFOutput[outOffset] = sf;\n }\n }\n }\n}\n\n// This is intended for weight loading, so m and n are large, b <= 256\ntemplate <typename T>\nvoid invokeBlockScaleInterleave(int b, int m, int m_padded, int n, int n_padded, T const* SFIn,\n T* SFOutput, int multiProcessorCount, cudaStream_t stream) {\n // Each thread reads 1 int8 value\n dim3 block(std::min(n_padded, 1024));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 4096u / block.x);\n dim3 grid(std::min(m_padded, multiProcessorCount * numBlocksPerSM));\n\n block_scale_interleave_kernel<T>\n <<<grid, block, 0, stream>>>(b, m, m_padded, n, n_padded, SFIn, SFOutput);\n}\n\n// Explicit template instantiations for the types used by other compilation units\ntemplate void invokeBlockScaleInterleave<uint8_t>(int b, int m, int m_padded, int n, int n_padded,\n uint8_t const* SFIn, uint8_t* SFOutput,\n int multiProcessorCount, cudaStream_t stream);\ntemplate void invokeBlockScaleInterleave<__nv_bfloat16>(int b, int m, int m_padded, int n,\n int n_padded, __nv_bfloat16 const* SFIn,\n __nv_bfloat16* SFOutput,\n int multiProcessorCount,\n cudaStream_t stream);\n\n// This is intended for weight loading, so m and n are large, b <= 256\nvoid invokeBlockScaleInterleaveReverse(int b, int m, int n, uint8_t const* SFIn, uint8_t* SFOutput,\n int multiProcessorCount, cudaStream_t stream) {\n // Each thread reads 1 int8 value\n dim3 block(std::min(n, 1024));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = std::max(1u, 4096u / block.x);\n dim3 grid(std::min(m, multiProcessorCount * numBlocksPerSM));\n\n block_scale_interleave_reverse_kernel<<<grid, block, 0, stream>>>(b, m, n, SFIn, SFOutput);\n}\n\ntemplate <typename T>\nvoid invokeSiluAndMulNVFP4Quantization(void* output, void* output_scale, void* input,\n void* input_global_scale, void* mask, bool use_silu_and_mul,\n int m_topk, int k, int n_experts, cudaStream_t stream) {\n int device;\n TLLM_CUDA_CHECK(cudaGetDevice(&device));\n int multiProcessorCount;\n TLLM_CUDA_CHECK(\n cudaDeviceGetAttribute(&multiProcessorCount, cudaDevAttrMultiProcessorCount, device));\n\n // Grid, Block size.\n // Each thread converts 8 values.\n TLLM_CHECK_WITH_INFO(k > 0, \"k must be > 0\");\n int const workSizePerRow = max(1, k / CVT_ELTS_PER_THREAD);\n int const totalWorkSize = m_topk * workSizePerRow;\n dim3 block(std::min(workSizePerRow, 512));\n // Get number of blocks per SM (assume we can fully utilize the SM).\n int const numBlocksPerSM = 2048 / block.x;\n dim3 grid(std::min(static_cast<int>((totalWorkSize + block.x - 1) / block.x),\n multiProcessorCount * numBlocksPerSM));\n while (grid.x <= multiProcessorCount && block.x > 64) {\n grid.x *= 2;\n block.x = (block.x + 1) / 2;\n }\n\n // TODO(kaixih@nvidia): Should relax this to allow any grid size.\n // shuw@nvidia.com: only deal with mask case\n TLLM_CHECK_WITH_INFO(mask != nullptr, \"mask must be non-null for expert NVFP4 path\");\n TLLM_CHECK_WITH_INFO(n_experts > 0, \"n_experts must be > 0\");\n grid.x = (grid.x + n_experts - 1) / n_experts * n_experts;\n cvt_fp16_to_fp4_expert<T, false><<<grid, block, 0, stream>>>(\n m_topk, k, reinterpret_cast<T*>(input), reinterpret_cast<float*>(input_global_scale),\n reinterpret_cast<uint32_t*>(output), reinterpret_cast<uint32_t*>(output_scale),\n reinterpret_cast<int32_t*>(mask), use_silu_and_mul, n_experts);\n return;\n}\n\n// Instantiate the function.\ntemplate void invokeFP4Quantization<half, 16>(int b, int m, int n, half const* input,\n float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0,\n QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeFP4Quantization<half, 32>(int b, int m, int n, half const* input,\n float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0,\n QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeMxFP8Quantization<half>(int b, int m, int n, int padded_n, half const* input,\n int64_t* output, int32_t* SFOuput,\n QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeSiluAndMulNVFP4Quantization<half>(void* output, void* output_scale, void* input,\n void* input_global_scale, void* mask,\n bool use_silu_and_mul, int m_topk, int k,\n int n_experts, cudaStream_t stream);\n\n#ifdef ENABLE_BF16\ntemplate void invokeFP4Quantization<__nv_bfloat16, 16>(\n int b, int m, int n, __nv_bfloat16 const* input, float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeFP4Quantization<__nv_bfloat16, 32>(\n int b, int m, int n, __nv_bfloat16 const* input, float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeMxFP8Quantization<__nv_bfloat16>(int b, int m, int n, int padded_n,\n __nv_bfloat16 const* input, int64_t* output,\n int32_t* SFOuput, QuantizationSFLayout layout,\n int multiProcessorCount, bool enable_pdl,\n cudaStream_t stream);\ntemplate void invokeSiluAndMulNVFP4Quantization<__nv_bfloat16>(\n void* output, void* output_scale, void* input, void* input_global_scale, void* mask,\n bool use_silu_and_mul, int m_topk, int k, int n_experts, cudaStream_t stream);\n\n#endif\n\n#ifdef ENABLE_FP8\ntemplate void invokeFP4Quantization<__nv_fp8_e4m3, 16>(\n int b, int m, int n, __nv_fp8_e4m3 const* input, float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\ntemplate void invokeFP4Quantization<__nv_fp8_e4m3, 32>(\n int b, int m, int n, __nv_fp8_e4m3 const* input, float const* SFScale, int64_t* output,\n int32_t* SFOuput, bool useUE8M0, QuantizationSFLayout layout, int multiProcessorCount,\n bool enable_pdl, cudaStream_t stream);\n\n#endif\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n} // namespace kernels\n} // namespace tensorrt_llm\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\nOptimize quantization function in large problem size by using TMA and warp specialized programming. \n\n<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added a high-throughput TMA-backed quantization path for large tensors to improve scalability and throughput.\n\n* **Refactor**\n * Reworked quantization internals to a template-driven, per-thread packing architecture, unifying element packing and scale-factor handling across FP16/FP8→FP4 and MXFP8 paths.\n\n* **Documentation**\n * Updated comments and dispatch logic to describe templated and TMA-backed quantization flows.\n\n* **Tests**\n * Extended quantization test coverage with a larger tensor shape.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1188,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"18804cd51734cccf807356d017733bc757677f15"},"date":{"kind":"string","value":"2026-01-21T22:28:56-08:00"},"pr_number":{"kind":"number","value":2387,"string":"2,387"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2387"},"title":{"kind":"string","value":"A Blackwell-optimized version of selective_state_update (mamba) (#2387)"},"message":{"kind":"string","value":"A Blackwell-optimized version of selective_state_update (mamba) (#2387)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nThis contributes a `selective_state_update` kernel that has been\nmanually optimized for sm100.\n\n<img width=\"3000\" height=\"3000\" alt=\"runtime_vs_batch_size_NVIDIA_B200\"\nsrc=\"https://github.com/user-attachments/assets/2718d992-1066-4385-b120-d22eccd3a941\"\n/>\n\n\nTechnically, the code in the sm100 module can be compiled and executed\non sm90, but the performance of this kernel on Hopper is not great (see\nthe image below).\n\n<img width=\"1173\" height=\"1173\" alt=\"image\"\nsrc=\"https://github.com/user-attachments/assets/eed59b15-8bf1-4123-9290-5a342ee7aada\"\n/>\n\n## Algorithm\nThe algorithmic differences between the new\n`selective_state_update_kernel_producer_consumer_horizontal` and the\nolder Hopper-specific\n`selective_state_update_kernel_producer_consumer_vertical` are\nsummarized below. Each CTA processes a single head. In the `vertical`\ncase, each warp processes a row, and then performs a reduction using\n`shfl_sync` intrinsics. In case of the `horizontal` kernel, each thread\nconsecutively processes multiple row elements while keeping track of the\nsum. This new treatment allows to lift the bottleneck off of the\nwarp-level reduction on Blackwell.\n\n<img width=\"1097\" height=\"449\" alt=\"Screenshot 2026-01-20 at 5 53 48 PM\"\nsrc=\"https://github.com/user-attachments/assets/fa02b290-9c76-4b03-b3f8-9a0c5b734ee4\"\n/>\n\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\nCould you please check consumer_func_horizontal and let me know whether\nthe comments about the bank-conflict-free indexing suffices.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* Added support for SM100 (Blackwell) and newer GPU architectures in\nMamba selective state update operations\n* Automatic kernel selection based on device compute capability for\noptimal performance\n\n* **Refactor**\n* Improved runtime dispatch logic to route operations to\narchitecture-specific optimized kernels\n\n* **Bug Fixes**\n * Enhanced CUDA error checking mechanism for better diagnostics\n\n<sub>✏️ Tip: You can customize this high-level summary in your review\nsettings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: Zihao Ye <expye@outlook.com>"},"path":{"kind":"string","value":"include/flashinfer/mamba/selective_state_update.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_MAMBA_SELECTIVE_STATE_UPDATE_CUH_\n#define FLASHINFER_MAMBA_SELECTIVE_STATE_UPDATE_CUH_\n\n#include <cooperative_groups.h>\n#include <cooperative_groups/memcpy_async.h>\n#include <cuda_runtime_api.h>\n\n#include <cmath>\n#include <cstdint>\n#include <cuda/barrier>\n\n#include \"../utils.cuh\"\n#include \"../vec_dtypes.cuh\"\n#include \"conversion.cuh\"\n#include \"create_tensor_map.cuh\"\n\nnamespace flashinfer::mamba {\n\nusing namespace conversion;\n\nstruct SelectiveStateUpdateParams {\n uint32_t batch{}, nheads{}, dim{}, dstate{}, ngroups{}, state_cache_size{};\n int32_t pad_slot_id{-1};\n bool dt_softplus{false};\n\n int64_t x_stride_batch{}, dt_stride_batch{}, B_stride_batch{}, C_stride_batch{},\n out_stride_batch{}, z_stride_batch{};\n\n void* __restrict__ state{nullptr}; // state_t: (state_cache_size, nheads, dim, dstate)\n void* __restrict__ x{nullptr}; // input_t: (batch, nheads, dim)\n void* __restrict__ dt{\n nullptr}; // weight_t: (batch, nheads) but pretends to be (batch, nheads, dim)\n void* __restrict__ dt_bias{nullptr}; // weight_t (nheads) but pretends to be (nheads, dim)\n void* __restrict__ A{nullptr}; // matrixA_t: (nheads) but pretends to be (nheads, dim, dstate)\n void* __restrict__ B{nullptr}; // input_t: (batch, ngroups, dstate)\n void* __restrict__ C{nullptr}; // input_t: (batch, ngroups, dstate)\n void* __restrict__ D{nullptr}; // weight_t: (nheads) but pretends to be (nheads, dim)\n void* __restrict__ z{nullptr}; // input_t: (batch, nheads, dim)\n void* __restrict__ output{nullptr}; // input_t: (batch, nheads, dim)\n void* __restrict__ state_batch_indices{nullptr}; // state_batch_indices: (batch,)\n};\n\n__forceinline__ __device__ float softplus(float x) { return __logf(1.f + __expf(x)); }\n\n__device__ __forceinline__ float thresholded_softplus(float dt_value) {\n constexpr float threshold = 20.f;\n return (dt_value <= threshold) ? softplus(dt_value) : dt_value;\n}\n\n// Simple packed vector type for loading N elements of type T\ntemplate <typename T, int N = sizeof(float4) / sizeof(T)>\nstruct alignas(N * sizeof(T)) PackedAligned {\n T val[N];\n static constexpr int count = N;\n using dtype = T;\n};\n\ntemplate <class load_t>\n__device__ __forceinline__ auto make_zeros() -> load_t {\n load_t ret{};\n#pragma unroll\n for (int i = 0; i < ret.count; i++)\n ret.val[i] = typename load_t::dtype{}; // default initialization\n return ret;\n};\n\n// Computes the vector load size that ensures full warp utilization.\n// Avoids cases like: dstate=64, load_t = sizeof(float4)/sizeof(f16), warpsize=32 (32 * 8 > 64)\n// in which case a part of the warp would be idle.\ntemplate <typename T, int DSTATE>\ninline constexpr auto getVectorLoadSizeForFullUtilization() -> unsigned {\n static_assert(sizeof(float4) >= sizeof(T));\n constexpr unsigned maxHardwareLoadSize = sizeof(float4) / sizeof(T);\n constexpr unsigned warpSize = 32;\n constexpr unsigned maxLogicalLoadSize = (unsigned)DSTATE / warpSize;\n return maxHardwareLoadSize < maxLogicalLoadSize ? maxHardwareLoadSize : maxLogicalLoadSize;\n}\n\n__device__ __forceinline__ float warpReduceSum(float val) {\n constexpr auto warpSize = 32;\n for (int s = warpSize / 2; s > 0; s /= 2) {\n val += __shfl_down_sync(UINT32_MAX, val, s);\n }\n return val;\n}\n\ntemplate <typename input_t, int dim, int dstate>\nstruct SharedStorageSimple {\n alignas(alignof(PackedAligned<input_t>)) input_t x[dim];\n float out[dim];\n alignas(alignof(PackedAligned<input_t>)) input_t z[dim];\n alignas(alignof(PackedAligned<input_t>)) input_t B[dstate];\n alignas(alignof(PackedAligned<input_t>)) input_t C[dstate];\n};\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n int DSTATE, int numWarps>\n__global__ void selective_state_update_kernel_simple(SelectiveStateUpdateParams params) {\n auto* __restrict__ output =\n reinterpret_cast<input_t*>(params.output); // output: (batch, nheads, dim)\n auto* __restrict__ state =\n reinterpret_cast<state_t*>(params.state); // state: (batch, nheads, dim, dstate)\n\n auto const* __restrict__ x =\n reinterpret_cast<input_t const*>(params.x); // x: (batch, nheads, dim)\n auto const* __restrict__ dt =\n reinterpret_cast<weight_t const*>(params.dt); // dt: (batch, nheads)\n auto const* __restrict__ A = reinterpret_cast<matrixA_t const*>(params.A); // A: (nheads)\n auto const* __restrict__ B =\n reinterpret_cast<input_t const*>(params.B); // B: (batch, ngroups, dstate)\n auto const* __restrict__ C =\n reinterpret_cast<input_t const*>(params.C); // C: (batch, ngroups, dstate)\n auto const* __restrict__ D = reinterpret_cast<weight_t const*>(params.D); // D: (nheads, dim)\n auto const* __restrict__ dt_bias = reinterpret_cast<weight_t const*>(params.dt_bias); // (nheads)\n auto const* __restrict__ z = reinterpret_cast<input_t const*>(params.z);\n auto const* __restrict__ state_batch_indices =\n reinterpret_cast<int const*>(params.state_batch_indices);\n bool const dt_softplus = params.dt_softplus;\n\n int const nheads = params.nheads;\n int const ngroups = params.ngroups;\n\n constexpr auto warpSize = 32;\n constexpr auto rowsPerWarp = (DIM + numWarps - 1) / numWarps;\n\n auto const batch = blockIdx.x;\n auto const head = blockIdx.y;\n auto const group = head / (nheads / ngroups);\n auto lane = threadIdx.x % warpSize;\n auto warp = threadIdx.y;\n\n auto const state_batch = (state_batch_indices) ? state_batch_indices[batch] : batch;\n state += (state_batch * nheads + head) * DIM * DSTATE;\n\n __shared__ SharedStorageSimple<input_t, DIM, DSTATE> sram;\n\n static constexpr auto stateLoadSize = getVectorLoadSizeForFullUtilization<state_t, DSTATE>();\n using load_state_t = PackedAligned<state_t, stateLoadSize>;\n using load_input_t = PackedAligned<input_t>;\n\n auto const A_value = toFloat(A[head]);\n\n auto dt_value = toFloat(dt[batch * params.dt_stride_batch + head]);\n if (dt_bias) dt_value += toFloat(dt_bias[head]);\n if (dt_softplus) {\n dt_value = thresholded_softplus(dt_value);\n }\n\n auto const dA = __expf(A_value * dt_value);\n\n auto d_value = D ? toFloat(D[head]) : 0.f;\n\n if (warp == 0) {\n for (auto d = lane * load_input_t::count; d < DIM; d += warpSize * load_input_t::count) {\n auto* dst = reinterpret_cast<load_input_t*>(&sram.x[d]);\n *dst = *reinterpret_cast<load_input_t const*>(\n &x[batch * params.x_stride_batch + head * DIM + d]);\n }\n for (auto i = lane * load_input_t::count; i < DSTATE; i += warpSize * load_input_t::count) {\n auto* dst = reinterpret_cast<load_input_t*>(&sram.B[i]);\n *dst = *reinterpret_cast<load_input_t const*>(\n &B[batch * params.B_stride_batch + group * DSTATE + i]);\n }\n } else if (warp == 1) { // Load z, C\n for (auto d = lane * load_input_t::count; d < DIM; d += warpSize * load_input_t::count) {\n auto* dst = reinterpret_cast<load_input_t*>(&sram.z[d]);\n *dst = z ? *reinterpret_cast<load_input_t const*>(\n &z[batch * params.z_stride_batch + head * DIM + d])\n : make_zeros<load_input_t>();\n }\n for (auto i = lane * load_input_t::count; i < DSTATE; i += warpSize * load_input_t::count) {\n auto* dst = reinterpret_cast<load_input_t*>(&sram.C[i]);\n *dst = *reinterpret_cast<load_input_t const*>(\n &C[batch * params.C_stride_batch + group * DSTATE + i]);\n }\n }\n __syncthreads();\n\n for (auto _d = warp * rowsPerWarp; _d < (warp + 1) * rowsPerWarp; _d++) {\n auto d = _d;\n if (d >= DIM) break;\n\n float x_value = toFloat(sram.x[_d]);\n float out_value = d_value * x_value * int(lane == 0); // first lane has the value\n\n for (int i = lane * load_state_t::count; i < DSTATE; i += warpSize * load_state_t::count) {\n auto rState = make_zeros<load_state_t>();\n if (state_batch != params.pad_slot_id)\n rState = *reinterpret_cast<load_state_t*>(&state[d * DSTATE + i]);\n\n for (int ii = 0; ii < load_state_t::count; ii++) {\n auto state_value = toFloat(rState.val[ii]);\n auto B_value = toFloat(sram.B[i + ii]);\n auto C_value = toFloat(sram.C[i + ii]);\n\n auto const dB = B_value * dt_value;\n auto const new_state = state_value * dA + dB * x_value;\n\n convertAndStore(&rState.val[ii], new_state);\n\n out_value += new_state * C_value;\n }\n if (state_batch != params.pad_slot_id)\n *reinterpret_cast<load_state_t*>(&state[d * DSTATE + i]) = rState;\n }\n\n // warpReduce the out_value\n out_value = warpReduceSum(out_value);\n if (lane == 0) {\n sram.out[_d] = out_value;\n }\n }\n\n __syncthreads();\n\n for (int l = lane; l < rowsPerWarp; l += warpSize) {\n auto d = warp * rowsPerWarp + l;\n if (d < DIM) {\n auto out_value = sram.out[d];\n if (z) {\n float z_value = toFloat(sram.z[d]);\n float sig_z = __fdividef(1.f, (1.f + __expf(0.f - z_value)));\n float silu_z = z_value * sig_z;\n out_value *= silu_z;\n }\n convertAndStore(&output[batch * params.out_stride_batch + head * DIM + d], out_value);\n }\n }\n}\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t,\n int rowsPerStage, int dim, int dstate, uint8_t numStages>\nstruct SharedStorage {\n alignas(128) state_t state[numStages][rowsPerStage * dstate];\n alignas(alignof(PackedAligned<input_t>)) input_t x[dim];\n float out[dim]; // dt is special cause we're gonna store input in there as well\n alignas(alignof(PackedAligned<input_t>)) input_t z[dim];\n alignas(alignof(PackedAligned<input_t>)) input_t B[dstate];\n alignas(alignof(PackedAligned<input_t>)) input_t C[dstate];\n\n using barrier_t = cuda::barrier<cuda::thread_scope_block>;\n barrier_t bar_empty[numStages];\n barrier_t bar_full[numStages];\n barrier_t bar_consumers;\n};\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n int DSTATE, int consumerWarps, int rowsPerStage, int numStages, bool useStateCache>\n__device__ __forceinline__ void consumer_func_vertical(\n int lane, int warp, float d_value, float dt_value, float dA,\n SharedStorage<input_t, weight_t, matrixA_t, state_t, rowsPerStage, DIM, DSTATE, numStages>&\n sram) {\n namespace cde = cuda::device::experimental;\n for (auto dBegin = 0, stage = 0; dBegin < DIM;\n dBegin += rowsPerStage, stage = (stage + 1) % numStages) {\n // wait for the producer\n sram.bar_full[stage].wait(sram.bar_full[stage].arrive());\n\n#pragma unroll\n for (auto dd = warp; dd < rowsPerStage; dd += consumerWarps) {\n auto d = dBegin + dd;\n float const x_value = toFloat(sram.x[d]);\n float out_value = d_value * x_value * int(lane == 0); // first lane has the value\n\n constexpr auto bankSize = sizeof(uint32_t);\n constexpr auto stateValuesPerBank = bankSize / sizeof(state_t);\n\n if constexpr (sizeof(state_t) == sizeof(input_t)) {\n for (int i = lane * stateValuesPerBank; i < DSTATE; i += warpSize * stateValuesPerBank) {\n auto* sState_ptr = reinterpret_cast<uint32_t*>(&sram.state[stage][dd * DSTATE + i]);\n uint32_t rState = *sState_ptr;\n auto* rState_ptr = reinterpret_cast<state_t*>(&rState);\n\n uint32_t rB = *reinterpret_cast<uint32_t const*>(&sram.B[i]);\n auto* rB_ptr = reinterpret_cast<input_t const*>(&rB);\n\n uint32_t rC = *reinterpret_cast<uint32_t const*>(&sram.C[i]);\n auto* rC_ptr = reinterpret_cast<input_t const*>(&rC);\n\n for (int e = 0; e < stateValuesPerBank; e++) {\n float state_value;\n if constexpr (!useStateCache) {\n state_value = 0.f;\n } else {\n state_value = toFloat(rState_ptr[e]);\n }\n auto const B_value = toFloat(rB_ptr[e]);\n auto const C_value = toFloat(rC_ptr[e]);\n\n auto const dB = B_value * dt_value;\n auto const new_state = state_value * dA + dB * x_value;\n\n convertAndStore(&rState_ptr[e], new_state);\n out_value += new_state * C_value;\n }\n *sState_ptr = rState;\n }\n } else {\n for (int i = lane * stateValuesPerBank; i < DSTATE; i += warpSize * stateValuesPerBank) {\n auto* sState_ptr = reinterpret_cast<uint32_t*>(&sram.state[stage][dd * DSTATE + i]);\n uint32_t rState = *sState_ptr;\n auto* rState_ptr = reinterpret_cast<state_t*>(&rState);\n\n for (int e = 0; e < stateValuesPerBank; e++) {\n float state_value;\n if constexpr (!useStateCache) {\n state_value = 0.f;\n } else {\n state_value = toFloat(rState_ptr[e]);\n }\n auto const B_value = toFloat(sram.B[i + e]);\n auto const C_value = toFloat(sram.C[i + e]);\n auto const dB = B_value * dt_value;\n auto const new_state = state_value * dA + dB * x_value;\n\n convertAndStore(&rState_ptr[e], new_state);\n out_value += new_state * C_value;\n }\n *sState_ptr = rState;\n }\n }\n\n out_value = warpReduceSum(out_value);\n if (lane == 0) {\n sram.out[d] = out_value;\n }\n }\n\n // Unblock producer\n cde::fence_proxy_async_shared_cta();\n auto _ = sram.bar_empty[stage].arrive();\n }\n}\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n int DSTATE, int consumerWarps, int rowsPerStage, int numStages = 1>\n__global__ void selective_state_update_kernel_producer_consumer_vertical(\n SelectiveStateUpdateParams params, __grid_constant__ CUtensorMap const tensorState) {\n#ifdef FLASHINFER_MAMBA_ENABLE_SM90\n auto* __restrict__ output = reinterpret_cast<input_t*>(params.output);\n\n auto const* __restrict__ x = reinterpret_cast<input_t const*>(params.x);\n auto const* __restrict__ dt = reinterpret_cast<weight_t const*>(params.dt);\n auto const* __restrict__ A = reinterpret_cast<matrixA_t const*>(params.A);\n auto const* __restrict__ B = reinterpret_cast<input_t const*>(params.B);\n auto const* __restrict__ C = reinterpret_cast<input_t const*>(params.C);\n auto const* __restrict__ D = reinterpret_cast<weight_t const*>(params.D);\n auto const* __restrict__ dt_bias = reinterpret_cast<weight_t const*>(params.dt_bias);\n auto const* __restrict__ z = reinterpret_cast<input_t const*>(params.z);\n auto const* __restrict__ state_batch_indices =\n reinterpret_cast<int const*>(params.state_batch_indices);\n\n int const nheads = params.nheads;\n int const ngroups = params.ngroups;\n\n constexpr auto warpSize = 32;\n constexpr auto numWarps = 1 + consumerWarps;\n\n auto const batch = blockIdx.x;\n auto const head = blockIdx.y;\n auto const group = head / (nheads / ngroups);\n auto lane = threadIdx.x % warpSize;\n auto warp = threadIdx.y;\n\n auto const state_batch = (state_batch_indices) ? state_batch_indices[batch] : batch;\n\n using sram_t =\n SharedStorage<input_t, weight_t, matrixA_t, state_t, rowsPerStage, DIM, DSTATE, numStages>;\n // Use dynamic shared memory to allow opting into extended shared memory on SM90+\n extern __shared__ __align__(128) char smem[];\n sram_t& sram = *reinterpret_cast<sram_t*>(smem);\n\n namespace cde = cuda::device::experimental;\n namespace cg = cooperative_groups;\n\n for (int stage = warp; stage < numStages; stage += numWarps) {\n if (lane > 0) continue;\n constexpr auto num_arrivals = 1 + consumerWarps * warpSize;\n init(&sram.bar_empty[stage], num_arrivals);\n init(&sram.bar_full[stage], num_arrivals);\n // signal to async proxy that barriers are initilized\n cde::fence_proxy_async_shared_cta();\n }\n if (lane == 0 && warp == 0) {\n init(&sram.bar_consumers, warpSize * consumerWarps);\n }\n __syncthreads();\n\n if (warp == consumerWarps) // producer\n {\n auto const state_offset = (state_batch * nheads + head) * DIM;\n\n for (int d = 0, stage = 0; d < DIM + rowsPerStage * numStages;\n d += rowsPerStage, stage = (stage + 1) % numStages) {\n if (lane == 0) {\n cg::invoke_one(cg::coalesced_threads(), [&]() {\n sram.bar_empty[stage].wait(sram.bar_empty[stage].arrive());\n\n if (state_batch != params.pad_slot_id) {\n // Writeback\n if (d >= rowsPerStage * numStages) {\n cde::cp_async_bulk_tensor_2d_shared_to_global(\n &tensorState,\n /*x*/ 0,\n /*y*/ state_offset + d - rowsPerStage * numStages, &sram.state[stage][0]);\n cde::cp_async_bulk_commit_group();\n cde::cp_async_bulk_wait_group_read<0>();\n }\n\n if (d < DIM) {\n cde::cp_async_bulk_tensor_2d_global_to_shared(&sram.state[stage][0], &tensorState,\n /*x*/ 0, /*y*/ state_offset + d,\n sram.bar_full[stage]);\n\n // Unblock the consumers\n auto constexpr bytesState = rowsPerStage * DSTATE * sizeof(state_t);\n auto constexpr bytesToArrive = bytesState;\n auto const _ =\n cuda::device::barrier_arrive_tx(sram.bar_full[stage], 1, bytesToArrive);\n }\n } else {\n auto const _ = sram.bar_full[stage].arrive();\n }\n });\n }\n }\n } else { // consumers\n\n using load_t = PackedAligned<input_t>;\n\n#pragma unroll\n // Unblock the producer\n for (uint8_t stage = 0; stage < numStages; ++stage) {\n auto const _ = sram.bar_empty[stage].arrive();\n }\n\n // Load A\n auto const A_value = toFloat(A[head]);\n\n // Load D\n auto const d_value = D ? toFloat(D[head]) : 0.f;\n\n // load dt_value\n auto dt_value = toFloat(dt[batch * params.dt_stride_batch + head]);\n if (dt_bias) dt_value += toFloat(dt_bias[head]);\n if (params.dt_softplus) {\n dt_value = thresholded_softplus(dt_value);\n }\n auto const dA = __expf(A_value * dt_value);\n\n if (warp == 0) { // Load x, B\n for (auto d = lane * load_t::count; d < DIM; d += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.x[d]);\n *dst = *reinterpret_cast<load_t const*>(&x[batch * params.x_stride_batch + head * DIM + d]);\n }\n for (auto i = lane * load_t::count; i < DSTATE; i += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.B[i]);\n *dst = *reinterpret_cast<load_t const*>(\n &B[batch * params.B_stride_batch + group * DSTATE + i]);\n }\n } else if (warp == 1) { // Load z, C\n for (auto d = lane * load_t::count; d < DIM; d += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.z[d]);\n *dst =\n z ? *reinterpret_cast<load_t const*>(&z[batch * params.z_stride_batch + head * DIM + d])\n : make_zeros<load_t>();\n }\n for (auto i = lane * load_t::count; i < DSTATE; i += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.C[i]);\n *dst = *reinterpret_cast<load_t const*>(\n &C[batch * params.C_stride_batch + group * DSTATE + i]);\n }\n }\n\n sram.bar_consumers.wait(sram.bar_consumers.arrive());\n\n if (state_batch != params.pad_slot_id)\n consumer_func_vertical<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, consumerWarps,\n rowsPerStage, numStages, true>(lane, warp, d_value, dt_value, dA,\n sram);\n else\n consumer_func_vertical<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, consumerWarps,\n rowsPerStage, numStages, false>(lane, warp, d_value, dt_value, dA,\n sram);\n\n // Write output\n sram.bar_consumers.wait(sram.bar_consumers.arrive());\n auto d = warp * warpSize + lane;\n if (d < DIM) {\n auto out_value = sram.out[d];\n if (z) {\n float z_value = toFloat(sram.z[d]);\n float sig_z = __fdividef(1.f, (1.f + __expf(0.f - z_value)));\n float silu_z = z_value * sig_z;\n out_value *= silu_z;\n }\n convertAndStore(&output[batch * params.out_stride_batch + head * DIM + d], out_value);\n }\n }\n#endif\n}\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t>\nvoid invokeSelectiveStateUpdate(SelectiveStateUpdateParams& params, cudaStream_t stream) {\n auto [sm_major, sm_minor] = GetCudaComputeCapability();\n\n constexpr auto warpSize = 32;\n\n#ifdef FLASHINFER_MAMBA_ENABLE_SM90\n if (sm_major < 9) // pre-Hopper\n#endif\n {\n auto dispatch_dim_dstate = [&]<int DIM, int DSTATE>() {\n // Alignment checks for vectorized loads in simple kernel\n constexpr auto stateLoadSize = getVectorLoadSizeForFullUtilization<state_t, DSTATE>();\n using load_state_t = PackedAligned<state_t, stateLoadSize>;\n using load_input_t = PackedAligned<input_t>;\n\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.state) % sizeof(load_state_t) == 0,\n \"state pointer must be aligned to \", sizeof(load_state_t), \" bytes\");\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.x) % sizeof(load_input_t) == 0,\n \"x pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.x_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"x batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n if (params.z) {\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.z) % sizeof(load_input_t) == 0,\n \"z pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.z_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"z batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n }\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.B) % sizeof(load_input_t) == 0,\n \"B pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.C) % sizeof(load_input_t) == 0,\n \"C pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.B_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"B batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.C_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"C batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.dim * params.dstate * sizeof(state_t)) % sizeof(load_state_t) == 0,\n \"state head stride must be aligned to \", sizeof(load_state_t), \" bytes\");\n\n constexpr int numWarps = 4;\n dim3 block(warpSize, numWarps);\n dim3 grid(params.batch, params.nheads);\n selective_state_update_kernel_simple<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE,\n numWarps><<<grid, block, 0, stream>>>(params);\n };\n\n auto dispatch_dstate = [&]<int DIM>() {\n switch (params.dstate) {\n case 64:\n dispatch_dim_dstate.template operator()<DIM, 64>();\n break;\n case 128:\n dispatch_dim_dstate.template operator()<DIM, 128>();\n break;\n case 256:\n dispatch_dim_dstate.template operator()<DIM, 256>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dstate value. Supported values are: 64, 128, 256\");\n }\n };\n\n switch (params.dim) {\n case 64:\n dispatch_dstate.template operator()<64>();\n break;\n case 128:\n dispatch_dstate.template operator()<128>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dim value. Supported values are: 64, 128\");\n }\n }\n#ifdef FLASHINFER_MAMBA_ENABLE_SM90\n else {\n\n auto dispatch_dim_dstate = [&]<int DIM, int DSTATE>() {\n // Alignment checks for vectorized loads in Hopper kernel\n // Note: State uses TMA which requires 128B alignment (checked below)\n // x, z, B, and C use PackedAligned<input_t>\n using load_input_t = PackedAligned<input_t>;\n\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.x) % sizeof(load_input_t) == 0,\n \"x pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.x_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"x batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n if (params.z) {\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.z) % sizeof(load_input_t) == 0,\n \"z pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.z_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"z batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n }\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.B) % sizeof(load_input_t) == 0,\n \"B pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.C) % sizeof(load_input_t) == 0,\n \"C pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.B_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"B batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.C_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"C batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n\n constexpr auto numConsumers = 4;\n constexpr auto numWarps = 1 + numConsumers;\n constexpr auto numStages = 3;\n constexpr auto rowsPerStage = 4 * numConsumers;\n FLASHINFER_CHECK(params.dim % rowsPerStage == 0, \"dim must be divisible by \", rowsPerStage,\n \" for SM90+ kernel\");\n auto scan_func = selective_state_update_kernel_producer_consumer_vertical<\n input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, numConsumers, rowsPerStage,\n numStages>;\n\n dim3 block(32, numWarps);\n dim3 grid(params.batch, params.nheads);\n\n auto nh = params.nheads;\n auto dim = params.dim;\n\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.state) % 128 ==\n 0); // TMA requires 128B aligned\n auto tensorState = tma::createTensorMap<state_t>(\n params.state, params.state_cache_size * nh * dim, DSTATE, rowsPerStage, DSTATE);\n\n // Calculate shared memory size and opt-in to extended shared memory\n using sram_t = SharedStorage<input_t, weight_t, matrixA_t, state_t, rowsPerStage, DIM, DSTATE,\n numStages>;\n constexpr size_t smem_size = sizeof(sram_t);\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(scan_func, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n scan_func<<<grid, block, smem_size, stream>>>(params, tensorState);\n };\n\n auto dispatch_dstate = [&]<int DIM>() {\n switch (params.dstate) {\n case 64:\n dispatch_dim_dstate.template operator()<DIM, 64>();\n break;\n case 128:\n dispatch_dim_dstate.template operator()<DIM, 128>();\n break;\n case 256:\n dispatch_dim_dstate.template operator()<DIM, 256>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dstate value. Supported values are: 64, 128, 256\");\n }\n };\n\n switch (params.dim) {\n case 64:\n dispatch_dstate.template operator()<64>();\n break;\n case 128:\n dispatch_dstate.template operator()<128>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dim value. Supported values are: 64, 128\");\n }\n }\n#endif\n}\n\n} // namespace flashinfer::mamba\n\n#endif // FLASHINFER_MAMBA_SELECTIVE_STATE_UPDATE_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_MAMBA_SELECTIVE_STATE_UPDATE_CUH_\n#define FLASHINFER_MAMBA_SELECTIVE_STATE_UPDATE_CUH_\n\n#include <cooperative_groups.h>\n#include <cooperative_groups/memcpy_async.h>\n#include <cuda_runtime_api.h>\n\n#include <cmath>\n#include <cstdint>\n#include <cuda/barrier>\n\n#include \"../utils.cuh\"\n#include \"../vec_dtypes.cuh\"\n#include \"conversion.cuh\"\n#include \"create_tensor_map.cuh\"\n\nnamespace flashinfer::mamba {\n\nusing namespace conversion;\n\nconstexpr unsigned warpSize = 32;\n\nstruct SelectiveStateUpdateParams {\n uint32_t batch{}, nheads{}, dim{}, dstate{}, ngroups{}, state_cache_size{};\n int32_t pad_slot_id{-1};\n bool dt_softplus{false};\n\n int64_t x_stride_batch{}, dt_stride_batch{}, B_stride_batch{}, C_stride_batch{},\n out_stride_batch{}, z_stride_batch{};\n\n void* __restrict__ state{nullptr}; // state_t: (state_cache_size, nheads, dim, dstate)\n void* __restrict__ x{nullptr}; // input_t: (batch, nheads, dim)\n void* __restrict__ dt{\n nullptr}; // weight_t: (batch, nheads) but pretends to be (batch, nheads, dim)\n void* __restrict__ dt_bias{nullptr}; // weight_t (nheads) but pretends to be (nheads, dim)\n void* __restrict__ A{nullptr}; // matrixA_t: (nheads) but pretends to be (nheads, dim, dstate)\n void* __restrict__ B{nullptr}; // input_t: (batch, ngroups, dstate)\n void* __restrict__ C{nullptr}; // input_t: (batch, ngroups, dstate)\n void* __restrict__ D{nullptr}; // weight_t: (nheads) but pretends to be (nheads, dim)\n void* __restrict__ z{nullptr}; // input_t: (batch, nheads, dim)\n void* __restrict__ output{nullptr}; // input_t: (batch, nheads, dim)\n void* __restrict__ state_batch_indices{nullptr}; // state_batch_indices: (batch,)\n};\n\n__forceinline__ __device__ float softplus(float x) { return __logf(1.f + __expf(x)); }\n\n__device__ __forceinline__ float thresholded_softplus(float dt_value) {\n constexpr float threshold = 20.f;\n return (dt_value <= threshold) ? softplus(dt_value) : dt_value;\n}\n\n// Simple packed vector type for loading N elements of type T\ntemplate <typename T, int N = sizeof(float4) / sizeof(T)>\nstruct alignas(N * sizeof(T)) PackedAligned {\n T val[N];\n static constexpr int count = N;\n using dtype = T;\n};\n\ntemplate <class load_t>\n__device__ __forceinline__ auto make_zeros() -> load_t {\n load_t ret{};\n#pragma unroll\n for (int i = 0; i < ret.count; i++)\n ret.val[i] = typename load_t::dtype{}; // default initialization\n return ret;\n};\n\n// Computes the vector load size that ensures full warp utilization.\n// Avoids cases like: dstate=64, load_t = sizeof(float4)/sizeof(f16), warpsize=32 (32 * 8 > 64)\n// in which case a part of the warp would be idle.\ntemplate <typename T, int DSTATE>\ninline constexpr auto getVectorLoadSizeForFullUtilization() -> unsigned {\n static_assert(sizeof(float4) >= sizeof(T));\n constexpr unsigned maxHardwareLoadSize = sizeof(float4) / sizeof(T);\n constexpr unsigned maxLogicalLoadSize = (unsigned)DSTATE / warpSize;\n return maxHardwareLoadSize < maxLogicalLoadSize ? maxHardwareLoadSize : maxLogicalLoadSize;\n}\n\n__device__ __forceinline__ float warpReduceSum(float val) {\n for (int s = warpSize / 2; s > 0; s /= 2) {\n val += __shfl_down_sync(UINT32_MAX, val, s);\n }\n return val;\n}\n\n// Computes a conflict-free column index for shared memory access.\n// This permutation avoids bank conflicts when threads access strided patterns.\n//\n// Without permutation (baseCol directly):\n// Thread 0 -> Bank 0, Thread 32 -> Bank 0, Thread 64 -> Bank 0 (conflict!)\n//\n// With permutation (adding bankCycle offset):\n// bankCycle = which \"round\" of 32 banks we're in\n// By offsetting each round by 1 bank:\n// Thread 0 -> Bank 0\n// Thread 32 -> Bank 1 (offset by 1)\n// Thread 64 -> Bank 2 (offset by 2)\n//\n// Visual: (stateValuesPerBank=1, numBanks=32, colsPerStage=128)\n// baseCol: 0 1 2 ... 31 | 32 33 34 ... 63 | 64 ...\n// bankCycle: 0 0 0 ... 0 | 1 1 1 ... 1 | 2 ...\n// ii: 0 1 2 ... 31 | 33 34 35 ... 64 | 66 ... (mod colsPerStage)\ntemplate <int colsPerStage, int stateValuesPerBank, int numBanks>\n__device__ __forceinline__ int conflict_free_column(int group, int baseCol) {\n auto const seq_index = group * colsPerStage + baseCol;\n auto const bankCycle = (seq_index / stateValuesPerBank) / numBanks;\n return (baseCol + stateValuesPerBank * bankCycle) % colsPerStage;\n}\n\ntemplate <typename input_t, int dim, int dstate>\nstruct SharedStorageSimple {\n alignas(alignof(PackedAligned<input_t>)) input_t x[dim];\n float out[dim];\n alignas(alignof(PackedAligned<input_t>)) input_t z[dim];\n alignas(alignof(PackedAligned<input_t>)) input_t B[dstate];\n alignas(alignof(PackedAligned<input_t>)) input_t C[dstate];\n};\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n int DSTATE, int numWarps>\n__global__ void selective_state_update_kernel_simple(SelectiveStateUpdateParams params) {\n auto* __restrict__ output =\n reinterpret_cast<input_t*>(params.output); // output: (batch, nheads, dim)\n auto* __restrict__ state =\n reinterpret_cast<state_t*>(params.state); // state: (batch, nheads, dim, dstate)\n\n auto const* __restrict__ x =\n reinterpret_cast<input_t const*>(params.x); // x: (batch, nheads, dim)\n auto const* __restrict__ dt =\n reinterpret_cast<weight_t const*>(params.dt); // dt: (batch, nheads)\n auto const* __restrict__ A = reinterpret_cast<matrixA_t const*>(params.A); // A: (nheads)\n auto const* __restrict__ B =\n reinterpret_cast<input_t const*>(params.B); // B: (batch, ngroups, dstate)\n auto const* __restrict__ C =\n reinterpret_cast<input_t const*>(params.C); // C: (batch, ngroups, dstate)\n auto const* __restrict__ D = reinterpret_cast<weight_t const*>(params.D); // D: (nheads, dim)\n auto const* __restrict__ dt_bias = reinterpret_cast<weight_t const*>(params.dt_bias); // (nheads)\n auto const* __restrict__ z = reinterpret_cast<input_t const*>(params.z);\n auto const* __restrict__ state_batch_indices =\n reinterpret_cast<int const*>(params.state_batch_indices);\n bool const dt_softplus = params.dt_softplus;\n\n int const nheads = params.nheads;\n int const ngroups = params.ngroups;\n\n constexpr auto rowsPerWarp = (DIM + numWarps - 1) / numWarps;\n\n auto const batch = blockIdx.x;\n auto const head = blockIdx.y;\n auto const group = head / (nheads / ngroups);\n auto lane = threadIdx.x % warpSize;\n auto warp = threadIdx.y;\n\n auto const state_batch = (state_batch_indices) ? state_batch_indices[batch] : batch;\n state += (state_batch * nheads + head) * DIM * DSTATE;\n\n __shared__ SharedStorageSimple<input_t, DIM, DSTATE> sram;\n\n static constexpr auto stateLoadSize = getVectorLoadSizeForFullUtilization<state_t, DSTATE>();\n using load_state_t = PackedAligned<state_t, stateLoadSize>;\n using load_input_t = PackedAligned<input_t>;\n\n auto const A_value = toFloat(A[head]);\n\n auto dt_value = toFloat(dt[batch * params.dt_stride_batch + head]);\n if (dt_bias) dt_value += toFloat(dt_bias[head]);\n if (dt_softplus) {\n dt_value = thresholded_softplus(dt_value);\n }\n\n auto const dA = __expf(A_value * dt_value);\n\n auto d_value = D ? toFloat(D[head]) : 0.f;\n\n if (warp == 0) {\n for (auto d = lane * load_input_t::count; d < DIM; d += warpSize * load_input_t::count) {\n auto* dst = reinterpret_cast<load_input_t*>(&sram.x[d]);\n *dst = *reinterpret_cast<load_input_t const*>(\n &x[batch * params.x_stride_batch + head * DIM + d]);\n }\n for (auto i = lane * load_input_t::count; i < DSTATE; i += warpSize * load_input_t::count) {\n auto* dst = reinterpret_cast<load_input_t*>(&sram.B[i]);\n *dst = *reinterpret_cast<load_input_t const*>(\n &B[batch * params.B_stride_batch + group * DSTATE + i]);\n }\n } else if (warp == 1) { // Load z, C\n for (auto d = lane * load_input_t::count; d < DIM; d += warpSize * load_input_t::count) {\n auto* dst = reinterpret_cast<load_input_t*>(&sram.z[d]);\n *dst = z ? *reinterpret_cast<load_input_t const*>(\n &z[batch * params.z_stride_batch + head * DIM + d])\n : make_zeros<load_input_t>();\n }\n for (auto i = lane * load_input_t::count; i < DSTATE; i += warpSize * load_input_t::count) {\n auto* dst = reinterpret_cast<load_input_t*>(&sram.C[i]);\n *dst = *reinterpret_cast<load_input_t const*>(\n &C[batch * params.C_stride_batch + group * DSTATE + i]);\n }\n }\n __syncthreads();\n\n for (auto _d = warp * rowsPerWarp; _d < (warp + 1) * rowsPerWarp; _d++) {\n auto d = _d;\n if (d >= DIM) break;\n\n float x_value = toFloat(sram.x[_d]);\n float out_value = d_value * x_value * int(lane == 0); // first lane has the value\n\n for (int i = lane * load_state_t::count; i < DSTATE; i += warpSize * load_state_t::count) {\n auto rState = make_zeros<load_state_t>();\n if (state_batch != params.pad_slot_id)\n rState = *reinterpret_cast<load_state_t*>(&state[d * DSTATE + i]);\n\n for (int ii = 0; ii < load_state_t::count; ii++) {\n auto state_value = toFloat(rState.val[ii]);\n auto B_value = toFloat(sram.B[i + ii]);\n auto C_value = toFloat(sram.C[i + ii]);\n\n auto const dB = B_value * dt_value;\n auto const new_state = state_value * dA + dB * x_value;\n\n convertAndStore(&rState.val[ii], new_state);\n\n out_value += new_state * C_value;\n }\n if (state_batch != params.pad_slot_id)\n *reinterpret_cast<load_state_t*>(&state[d * DSTATE + i]) = rState;\n }\n\n // warpReduce the out_value\n out_value = warpReduceSum(out_value);\n if (lane == 0) {\n sram.out[_d] = out_value;\n }\n }\n\n __syncthreads();\n\n for (int l = lane; l < rowsPerWarp; l += warpSize) {\n auto d = warp * rowsPerWarp + l;\n if (d < DIM) {\n auto out_value = sram.out[d];\n if (z) {\n float z_value = toFloat(sram.z[d]);\n float sig_z = __fdividef(1.f, (1.f + __expf(0.f - z_value)));\n float silu_z = z_value * sig_z;\n out_value *= silu_z;\n }\n convertAndStore(&output[batch * params.out_stride_batch + head * DIM + d], out_value);\n }\n }\n}\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t,\n int rowsPerStage, int dim, int dstate, uint8_t numStages>\nstruct SharedStorage {\n alignas(128) state_t state[numStages][rowsPerStage * dstate];\n alignas(alignof(PackedAligned<input_t>)) input_t x[dim];\n float out[dim]; // dt is special cause we're gonna store input in there as well\n alignas(alignof(PackedAligned<input_t>)) input_t z[dim];\n alignas(alignof(PackedAligned<input_t>)) input_t B[dstate];\n alignas(alignof(PackedAligned<input_t>)) input_t C[dstate];\n\n using barrier_t = cuda::barrier<cuda::thread_scope_block>;\n barrier_t bar_empty[numStages];\n barrier_t bar_full[numStages];\n barrier_t bar_consumers;\n};\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n int DSTATE, int consumerWarps, int rowsPerStage, int numStages, bool useStateCache>\n__device__ __forceinline__ void consumer_func_vertical(\n int lane, int warp, float d_value, float dt_value, float dA,\n SharedStorage<input_t, weight_t, matrixA_t, state_t, rowsPerStage, DIM, DSTATE, numStages>&\n sram) {\n namespace cde = cuda::device::experimental;\n for (auto dBegin = 0, stage = 0; dBegin < DIM;\n dBegin += rowsPerStage, stage = (stage + 1) % numStages) {\n // wait for the producer\n sram.bar_full[stage].wait(sram.bar_full[stage].arrive());\n\n#pragma unroll\n for (auto dd = warp; dd < rowsPerStage; dd += consumerWarps) {\n auto d = dBegin + dd;\n float const x_value = toFloat(sram.x[d]);\n float out_value = d_value * x_value * int(lane == 0); // first lane has the value\n\n constexpr auto bankSize = sizeof(uint32_t);\n constexpr auto stateValuesPerBank = bankSize / sizeof(state_t);\n\n if constexpr (sizeof(state_t) == sizeof(input_t)) {\n for (int i = lane * stateValuesPerBank; i < DSTATE; i += warpSize * stateValuesPerBank) {\n auto* sState_ptr = reinterpret_cast<uint32_t*>(&sram.state[stage][dd * DSTATE + i]);\n uint32_t rState = *sState_ptr;\n auto* rState_ptr = reinterpret_cast<state_t*>(&rState);\n\n uint32_t rB = *reinterpret_cast<uint32_t const*>(&sram.B[i]);\n auto* rB_ptr = reinterpret_cast<input_t const*>(&rB);\n\n uint32_t rC = *reinterpret_cast<uint32_t const*>(&sram.C[i]);\n auto* rC_ptr = reinterpret_cast<input_t const*>(&rC);\n\n for (int e = 0; e < stateValuesPerBank; e++) {\n float state_value;\n if constexpr (!useStateCache) {\n state_value = 0.f;\n } else {\n state_value = toFloat(rState_ptr[e]);\n }\n auto const B_value = toFloat(rB_ptr[e]);\n auto const C_value = toFloat(rC_ptr[e]);\n\n auto const dB = B_value * dt_value;\n auto const new_state = state_value * dA + dB * x_value;\n\n convertAndStore(&rState_ptr[e], new_state);\n out_value += new_state * C_value;\n }\n *sState_ptr = rState;\n }\n } else {\n for (int i = lane * stateValuesPerBank; i < DSTATE; i += warpSize * stateValuesPerBank) {\n auto* sState_ptr = reinterpret_cast<uint32_t*>(&sram.state[stage][dd * DSTATE + i]);\n uint32_t rState = *sState_ptr;\n auto* rState_ptr = reinterpret_cast<state_t*>(&rState);\n\n for (int e = 0; e < stateValuesPerBank; e++) {\n float state_value;\n if constexpr (!useStateCache) {\n state_value = 0.f;\n } else {\n state_value = toFloat(rState_ptr[e]);\n }\n auto const B_value = toFloat(sram.B[i + e]);\n auto const C_value = toFloat(sram.C[i + e]);\n auto const dB = B_value * dt_value;\n auto const new_state = state_value * dA + dB * x_value;\n\n convertAndStore(&rState_ptr[e], new_state);\n out_value += new_state * C_value;\n }\n *sState_ptr = rState;\n }\n }\n\n out_value = warpReduceSum(out_value);\n if (lane == 0) {\n sram.out[d] = out_value;\n }\n }\n\n // Unblock producer\n cde::fence_proxy_async_shared_cta();\n auto _ = sram.bar_empty[stage].arrive();\n }\n}\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n int DSTATE, int consumerWarps, int rowsPerStage, int numStages = 1>\n__global__ void selective_state_update_kernel_producer_consumer_vertical(\n SelectiveStateUpdateParams params, __grid_constant__ CUtensorMap const tensorState) {\n#ifdef FLASHINFER_MAMBA_ENABLE_SM90\n auto* __restrict__ output = reinterpret_cast<input_t*>(params.output);\n\n auto const* __restrict__ x = reinterpret_cast<input_t const*>(params.x);\n auto const* __restrict__ dt = reinterpret_cast<weight_t const*>(params.dt);\n auto const* __restrict__ A = reinterpret_cast<matrixA_t const*>(params.A);\n auto const* __restrict__ B = reinterpret_cast<input_t const*>(params.B);\n auto const* __restrict__ C = reinterpret_cast<input_t const*>(params.C);\n auto const* __restrict__ D = reinterpret_cast<weight_t const*>(params.D);\n auto const* __restrict__ dt_bias = reinterpret_cast<weight_t const*>(params.dt_bias);\n auto const* __restrict__ z = reinterpret_cast<input_t const*>(params.z);\n auto const* __restrict__ state_batch_indices =\n reinterpret_cast<int const*>(params.state_batch_indices);\n\n int const nheads = params.nheads;\n int const ngroups = params.ngroups;\n\n constexpr auto numWarps = 1 + consumerWarps;\n\n auto const batch = blockIdx.x;\n auto const head = blockIdx.y;\n auto const group = head / (nheads / ngroups);\n auto lane = threadIdx.x % warpSize;\n auto warp = threadIdx.y;\n\n auto const state_batch = (state_batch_indices) ? state_batch_indices[batch] : batch;\n\n using sram_t =\n SharedStorage<input_t, weight_t, matrixA_t, state_t, rowsPerStage, DIM, DSTATE, numStages>;\n // Use dynamic shared memory to allow opting into extended shared memory on SM90+\n extern __shared__ __align__(128) char smem[];\n sram_t& sram = *reinterpret_cast<sram_t*>(smem);\n\n namespace cde = cuda::device::experimental;\n namespace cg = cooperative_groups;\n\n for (int stage = warp; stage < numStages; stage += numWarps) {\n if (lane > 0) continue;\n constexpr auto num_arrivals = 1 + consumerWarps * warpSize;\n init(&sram.bar_empty[stage], num_arrivals);\n init(&sram.bar_full[stage], num_arrivals);\n // signal to async proxy that barriers are initilized\n cde::fence_proxy_async_shared_cta();\n }\n if (lane == 0 && warp == 0) {\n init(&sram.bar_consumers, warpSize * consumerWarps);\n }\n __syncthreads();\n\n if (warp == consumerWarps) // producer\n {\n auto const state_offset = (state_batch * nheads + head) * DIM;\n\n for (int d = 0, stage = 0; d < DIM + rowsPerStage * numStages;\n d += rowsPerStage, stage = (stage + 1) % numStages) {\n if (lane == 0) {\n cg::invoke_one(cg::coalesced_threads(), [&]() {\n sram.bar_empty[stage].wait(sram.bar_empty[stage].arrive());\n\n if (state_batch != params.pad_slot_id) {\n // Writeback\n if (d >= rowsPerStage * numStages) {\n cde::cp_async_bulk_tensor_2d_shared_to_global(\n &tensorState,\n /*x*/ 0,\n /*y*/ state_offset + d - rowsPerStage * numStages, &sram.state[stage][0]);\n cde::cp_async_bulk_commit_group();\n cde::cp_async_bulk_wait_group_read<0>();\n }\n\n if (d < DIM) {\n cde::cp_async_bulk_tensor_2d_global_to_shared(&sram.state[stage][0], &tensorState,\n /*x*/ 0, /*y*/ state_offset + d,\n sram.bar_full[stage]);\n\n // Unblock the consumers\n auto constexpr bytesState = rowsPerStage * DSTATE * sizeof(state_t);\n auto constexpr bytesToArrive = bytesState;\n auto const _ =\n cuda::device::barrier_arrive_tx(sram.bar_full[stage], 1, bytesToArrive);\n }\n } else {\n auto const _ = sram.bar_full[stage].arrive();\n }\n });\n }\n }\n } else { // consumers\n\n using load_t = PackedAligned<input_t>;\n\n#pragma unroll\n // Unblock the producer\n for (uint8_t stage = 0; stage < numStages; ++stage) {\n auto const _ = sram.bar_empty[stage].arrive();\n }\n\n // Load A\n auto const A_value = toFloat(A[head]);\n\n // Load D\n auto const d_value = D ? toFloat(D[head]) : 0.f;\n\n // load dt_value\n auto dt_value = toFloat(dt[batch * params.dt_stride_batch + head]);\n if (dt_bias) dt_value += toFloat(dt_bias[head]);\n if (params.dt_softplus) {\n dt_value = thresholded_softplus(dt_value);\n }\n auto const dA = __expf(A_value * dt_value);\n\n if (warp == 0) { // Load x, B\n for (auto d = lane * load_t::count; d < DIM; d += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.x[d]);\n *dst = *reinterpret_cast<load_t const*>(&x[batch * params.x_stride_batch + head * DIM + d]);\n }\n for (auto i = lane * load_t::count; i < DSTATE; i += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.B[i]);\n *dst = *reinterpret_cast<load_t const*>(\n &B[batch * params.B_stride_batch + group * DSTATE + i]);\n }\n } else if (warp == 1) { // Load z, C\n for (auto d = lane * load_t::count; d < DIM; d += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.z[d]);\n *dst =\n z ? *reinterpret_cast<load_t const*>(&z[batch * params.z_stride_batch + head * DIM + d])\n : make_zeros<load_t>();\n }\n for (auto i = lane * load_t::count; i < DSTATE; i += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.C[i]);\n *dst = *reinterpret_cast<load_t const*>(\n &C[batch * params.C_stride_batch + group * DSTATE + i]);\n }\n }\n\n sram.bar_consumers.wait(sram.bar_consumers.arrive());\n\n if (state_batch != params.pad_slot_id)\n consumer_func_vertical<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, consumerWarps,\n rowsPerStage, numStages, true>(lane, warp, d_value, dt_value, dA,\n sram);\n else\n consumer_func_vertical<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, consumerWarps,\n rowsPerStage, numStages, false>(lane, warp, d_value, dt_value, dA,\n sram);\n\n // Write output\n sram.bar_consumers.wait(sram.bar_consumers.arrive());\n auto d = warp * warpSize + lane;\n if (d < DIM) {\n auto out_value = sram.out[d];\n if (z) {\n float z_value = toFloat(sram.z[d]);\n float sig_z = __fdividef(1.f, (1.f + __expf(0.f - z_value)));\n float silu_z = z_value * sig_z;\n out_value *= silu_z;\n }\n convertAndStore(&output[batch * params.out_stride_batch + head * DIM + d], out_value);\n }\n }\n#endif\n}\n\n// =============================================================================\n// Horizontal Producer-Consumer Kernel for SM100+ (Blackwell and newer)\n// =============================================================================\n\n#ifdef FLASHINFER_MAMBA_ENABLE_SM100\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t,\n typename state_t, //\n int dim, int dstate, int stageCols, uint8_t numStages>\nstruct SharedStorageHorizontal {\n alignas(128) state_t state[numStages][dim * stageCols];\n alignas(alignof(PackedAligned<input_t>)) input_t B[dstate];\n alignas(alignof(PackedAligned<input_t>)) input_t C[dstate];\n\n using barrier_t = cuda::barrier<cuda::thread_scope_block>;\n barrier_t bar_empty[numStages];\n barrier_t bar_full[numStages];\n barrier_t bar_consumers;\n};\n\ntemplate <typename state_t, int DIM, int DSTATE, int colsPerStage, int numStages,\n bool useStateCache, typename SramT>\n__device__ __forceinline__ void producer_func_horizontal(SramT& sram,\n CUtensorMap const& tensorState,\n int state_offset) {\n namespace cde = cuda::device::experimental;\n\n auto constexpr stagesReadOnly = numStages;\n auto constexpr stagesBoth = DSTATE / colsPerStage - numStages;\n auto constexpr stagesWriteOnly = numStages;\n\n auto constexpr bytesState = DIM * colsPerStage * sizeof(state_t);\n auto constexpr bytesToArrive = bytesState;\n\n // Phase 1: Read only (filling the pipeline)\n#pragma unroll\n for (int iter = 0; iter < stagesReadOnly; ++iter) {\n auto const stage = iter % numStages;\n auto const i = iter * colsPerStage;\n\n sram.bar_empty[stage].wait(sram.bar_empty[stage].arrive());\n\n if constexpr (useStateCache) {\n cde::cp_async_bulk_tensor_2d_global_to_shared(&sram.state[stage][0], &tensorState, /*x*/ i,\n /*y*/ state_offset, sram.bar_full[stage]);\n auto const _ = cuda::device::barrier_arrive_tx(sram.bar_full[stage], 1, bytesToArrive);\n } else {\n auto const _ = sram.bar_full[stage].arrive();\n }\n }\n\n // Phase 2: Both read and write (steady state)\n#pragma unroll\n for (int iter = 0; iter < stagesBoth; ++iter) {\n auto const stage = (stagesReadOnly + iter) % numStages;\n auto const i_read = (stagesReadOnly + iter) * colsPerStage;\n auto const i_write = iter * colsPerStage;\n\n sram.bar_empty[stage].wait(sram.bar_empty[stage].arrive());\n\n if constexpr (useStateCache) {\n // Unblock async proxy for writeback\n cde::fence_proxy_async_shared_cta();\n // Writeback\n cde::cp_async_bulk_tensor_2d_shared_to_global(&tensorState, /*x*/ i_write,\n /*y*/ state_offset, &sram.state[stage][0]);\n cde::cp_async_bulk_commit_group();\n cde::cp_async_bulk_wait_group_read<0>();\n\n // Read next\n cde::cp_async_bulk_tensor_2d_global_to_shared(&sram.state[stage][0], &tensorState,\n /*x*/ i_read, /*y*/ state_offset,\n sram.bar_full[stage]);\n auto const _ = cuda::device::barrier_arrive_tx(sram.bar_full[stage], 1, bytesToArrive);\n } else {\n auto const _ = sram.bar_full[stage].arrive();\n }\n }\n\n // Phase 3: Write only (draining the pipeline)\n#pragma unroll\n for (int iter = 0; iter < stagesWriteOnly; ++iter) {\n auto const stage = (stagesReadOnly + stagesBoth + iter) % numStages;\n auto const i_write = (stagesBoth + iter) * colsPerStage;\n\n sram.bar_empty[stage].wait(sram.bar_empty[stage].arrive());\n\n if constexpr (useStateCache) {\n // Unblock async proxy for writeback\n cde::fence_proxy_async_shared_cta();\n cde::cp_async_bulk_tensor_2d_shared_to_global(&tensorState, /*x*/ i_write,\n /*y*/ state_offset, &sram.state[stage][0]);\n cde::cp_async_bulk_commit_group();\n cde::cp_async_bulk_wait_group_read<0>();\n }\n }\n}\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n int DSTATE, int consumerWarps, int colsPerStage, int numStages, bool useStateCache>\n__device__ __forceinline__ void consumer_func_horizontal(\n int d, int member, float A_value, float dt_value, float x_value,\n SharedStorageHorizontal<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, colsPerStage,\n numStages>& sram,\n float& out_value) {\n namespace cde = cuda::device::experimental;\n constexpr auto lanesPerRow = (consumerWarps * warpSize) / DIM;\n constexpr auto itemsPerThread = colsPerStage / lanesPerRow;\n auto const group = d % (warpSize / lanesPerRow);\n\n // #pragma unroll 1\n for (int iBegin = 0, stage = 0; iBegin < DSTATE;\n iBegin += colsPerStage, stage = (stage + 1) % numStages) {\n // wait for the producer\n sram.bar_full[stage].wait(sram.bar_full[stage].arrive());\n\n constexpr auto bankSize = sizeof(uint32_t);\n constexpr auto stateValuesPerBank = bankSize / sizeof(state_t);\n constexpr auto numBanks = 32;\n if constexpr (sizeof(state_t) == sizeof(input_t)) {\n#pragma unroll\n for (int item = 0; item < itemsPerThread; item += stateValuesPerBank) {\n auto const baseCol = item + member * itemsPerThread;\n // If I just use baseCol as the index, a lot of bank conflicts will arise.\n //\n auto const ii =\n conflict_free_column<colsPerStage, stateValuesPerBank, numBanks>(group, baseCol);\n\n auto const i = iBegin + ii;\n\n auto* sState_ptr = reinterpret_cast<uint*>(&sram.state[stage][d * colsPerStage + ii]);\n uint32_t rState = *sState_ptr;\n auto* rState_ptr = reinterpret_cast<state_t*>(&rState);\n\n uint32_t rB = *reinterpret_cast<uint32_t const*>(&sram.B[i]);\n auto* rB_ptr = reinterpret_cast<input_t const*>(&rB);\n\n uint32_t rC = *reinterpret_cast<uint32_t const*>(&sram.C[i]);\n auto* rC_ptr = reinterpret_cast<input_t const*>(&rC);\n\n for (int e = 0; e < stateValuesPerBank; e++) {\n float state_value;\n if constexpr (!useStateCache) {\n state_value = 0.f;\n } else {\n state_value = toFloat(rState_ptr[e]);\n }\n\n auto const B_value = toFloat(rB_ptr[e]);\n auto const C_value = toFloat(rC_ptr[e]);\n\n auto const dA = __expf(A_value * dt_value);\n auto const dB = B_value * dt_value;\n auto const new_state = state_value * dA + dB * x_value;\n\n convertAndStore(&rState_ptr[e], new_state);\n out_value += new_state * C_value;\n }\n *sState_ptr = rState;\n }\n } else {\n for (int item = 0; item < itemsPerThread; item += stateValuesPerBank) {\n auto const baseCol = item + member * itemsPerThread;\n auto const ii =\n conflict_free_column<colsPerStage, stateValuesPerBank, numBanks>(group, baseCol);\n auto const i = iBegin + ii;\n\n auto* sState_ptr = reinterpret_cast<uint*>(&sram.state[stage][d * colsPerStage + ii]);\n uint32_t rState = *sState_ptr;\n auto* rState_ptr = reinterpret_cast<state_t*>(&rState);\n\n for (int e = 0; e < stateValuesPerBank; e++) {\n float state_value;\n if constexpr (!useStateCache) {\n state_value = 0.f;\n } else {\n state_value = toFloat(rState_ptr[e]);\n }\n\n auto const B_value = toFloat(sram.B[i + e]);\n auto const C_value = toFloat(sram.C[i + e]);\n\n auto const dA = __expf(A_value * dt_value);\n auto const dB = B_value * dt_value;\n auto const new_state = state_value * dA + dB * x_value;\n\n convertAndStore(&rState_ptr[e], new_state);\n out_value += new_state * C_value;\n }\n *sState_ptr = rState;\n }\n }\n\n auto _ = sram.bar_empty[stage].arrive();\n }\n}\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n int DSTATE, int consumerWarps, int colsPerStage, int headsGroupsRatio, int numStages = 1>\n__global__ void selective_state_update_kernel_producer_consumer_horizontal(\n SelectiveStateUpdateParams params, __grid_constant__ CUtensorMap const tensorState) {\n auto* __restrict__ output = reinterpret_cast<input_t*>(params.output);\n auto const* __restrict__ x = reinterpret_cast<input_t const*>(params.x);\n auto const* __restrict__ dt = reinterpret_cast<weight_t const*>(params.dt);\n auto const* __restrict__ A = reinterpret_cast<matrixA_t const*>(params.A);\n auto const* __restrict__ B = reinterpret_cast<input_t const*>(params.B);\n auto const* __restrict__ C = reinterpret_cast<input_t const*>(params.C);\n auto const* __restrict__ D = reinterpret_cast<weight_t const*>(params.D);\n auto const* __restrict__ dt_bias = reinterpret_cast<weight_t const*>(params.dt_bias);\n auto const* __restrict__ z = reinterpret_cast<input_t const*>(params.z);\n auto const* __restrict__ state_batch_indices =\n reinterpret_cast<int const*>(params.state_batch_indices);\n\n int const nheads = params.nheads;\n\n constexpr auto numWarps = 1 + consumerWarps;\n\n auto const batch = blockIdx.x;\n auto const head = blockIdx.y;\n auto const group = head / headsGroupsRatio;\n auto lane = threadIdx.x % warpSize;\n auto warp = threadIdx.y;\n\n auto const state_batch = (state_batch_indices) ? state_batch_indices[batch] : batch;\n\n extern __shared__ uint8_t sbuffer[];\n using sram_t = SharedStorageHorizontal<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE,\n colsPerStage, numStages>;\n auto& sram = *reinterpret_cast<sram_t*>(sbuffer);\n\n namespace cde = cuda::device::experimental;\n namespace cg = cooperative_groups;\n\n for (int stage = warp; stage < numStages; stage += numWarps) {\n if (lane > 0) continue;\n constexpr auto num_arrivals = 1 + consumerWarps * warpSize;\n init(&sram.bar_empty[stage], num_arrivals);\n init(&sram.bar_full[stage], num_arrivals);\n // signal to async proxy that barriers are initilized\n cde::fence_proxy_async_shared_cta();\n }\n if (lane == 0 && warp == 0) {\n init(&sram.bar_consumers, warpSize * consumerWarps);\n }\n __syncthreads();\n\n if (warp == consumerWarps) // producer\n {\n auto const state_offset = (state_batch * nheads + head) * DIM;\n\n cg::invoke_one(cg::coalesced_threads(), [&]() {\n if (state_batch != params.pad_slot_id)\n producer_func_horizontal<state_t, DIM, DSTATE, colsPerStage, numStages, true>(\n sram, tensorState, state_offset);\n else\n producer_func_horizontal<state_t, DIM, DSTATE, colsPerStage, numStages, false>(\n sram, tensorState, state_offset);\n });\n } else { // consumers\n\n using load_t = PackedAligned<input_t>;\n\n // Unblock the producer\n#pragma unroll\n for (auto stage = 0; stage < numStages; ++stage) {\n auto const _ = sram.bar_empty[stage].arrive();\n }\n\n // Load A\n auto const A_value = toFloat(A[head]);\n\n // Load D\n auto const d_value = D ? toFloat(D[head]) : 0.f;\n\n // load dt_value\n auto dt_value = toFloat(dt[batch * params.dt_stride_batch + head]);\n if (dt_bias) dt_value += toFloat(dt_bias[head]);\n if (params.dt_softplus) {\n dt_value = thresholded_softplus(dt_value);\n }\n\n if (warp == 0) { // Load B\n for (auto d = lane * load_t::count; d < DSTATE; d += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.B[d]);\n *dst = *reinterpret_cast<load_t const*>(\n &B[batch * params.B_stride_batch + group * DSTATE + d]);\n }\n } else if (warp == 1) { // Load C\n for (auto i = lane * load_t::count; i < DSTATE; i += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.C[i]);\n *dst = *reinterpret_cast<load_t const*>(\n &C[batch * params.C_stride_batch + group * DSTATE + i]);\n }\n }\n\n constexpr auto lanesPerRow = (consumerWarps * warpSize) / DIM;\n static_assert(lanesPerRow >= 1);\n constexpr auto rowsPerWarp = warpSize / lanesPerRow;\n auto const group = lane % rowsPerWarp;\n auto const member = lane / rowsPerWarp;\n auto const d = warp * rowsPerWarp + group;\n auto const x_value = toFloat(x[batch * params.x_stride_batch + head * DIM + d]);\n auto const z_value = z ? toFloat(z[batch * params.z_stride_batch + head * DIM + d]) : 0.f;\n\n sram.bar_consumers.wait(sram.bar_consumers.arrive());\n\n // Thread\n float out_value = 0.f;\n if (state_batch != params.pad_slot_id)\n consumer_func_horizontal<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, consumerWarps,\n colsPerStage, numStages, true>(d, member, A_value, dt_value, x_value,\n sram, out_value);\n else\n consumer_func_horizontal<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, consumerWarps,\n colsPerStage, numStages, false>(d, member, A_value, dt_value,\n x_value, sram, out_value);\n\n out_value += __shfl_down_sync(UINT32_MAX, out_value, 16);\n if constexpr (lanesPerRow == 4) {\n out_value += __shfl_down_sync(UINT32_MAX, out_value, 8);\n }\n\n if (member == 0) {\n out_value += d_value * x_value;\n\n // Write output\n if (z) {\n float sig_z = __fdividef(1.f, (1.f + __expf(0.f - z_value)));\n float silu_z = z_value * sig_z;\n out_value *= silu_z;\n }\n convertAndStore(&output[batch * params.out_stride_batch + head * DIM + d], out_value);\n }\n }\n}\n\n#endif // FLASHINFER_MAMBA_ENABLE_SM100\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t>\nvoid invokeSelectiveStateUpdate(SelectiveStateUpdateParams& params, cudaStream_t stream) {\n auto [sm_major, sm_minor] = GetCudaComputeCapability();\n\n#ifdef FLASHINFER_MAMBA_ENABLE_SM100\n if (sm_major < 10) // pre-Blackwell\n#elif defined(FLASHINFER_MAMBA_ENABLE_SM90)\n if (sm_major < 9) // pre-Hopper\n#endif\n {\n auto dispatch_dim_dstate = [&]<int DIM, int DSTATE>() {\n // Alignment checks for vectorized loads in simple kernel\n constexpr auto stateLoadSize = getVectorLoadSizeForFullUtilization<state_t, DSTATE>();\n using load_state_t = PackedAligned<state_t, stateLoadSize>;\n using load_input_t = PackedAligned<input_t>;\n\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.state) % sizeof(load_state_t) == 0,\n \"state pointer must be aligned to \", sizeof(load_state_t), \" bytes\");\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.x) % sizeof(load_input_t) == 0,\n \"x pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.x_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"x batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n if (params.z) {\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.z) % sizeof(load_input_t) == 0,\n \"z pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.z_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"z batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n }\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.B) % sizeof(load_input_t) == 0,\n \"B pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.C) % sizeof(load_input_t) == 0,\n \"C pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.B_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"B batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.C_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"C batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.dim * params.dstate * sizeof(state_t)) % sizeof(load_state_t) == 0,\n \"state head stride must be aligned to \", sizeof(load_state_t), \" bytes\");\n\n constexpr int numWarps = 4;\n dim3 block(warpSize, numWarps);\n dim3 grid(params.batch, params.nheads);\n selective_state_update_kernel_simple<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE,\n numWarps><<<grid, block, 0, stream>>>(params);\n };\n\n auto dispatch_dstate = [&]<int DIM>() {\n switch (params.dstate) {\n case 64:\n dispatch_dim_dstate.template operator()<DIM, 64>();\n break;\n case 128:\n dispatch_dim_dstate.template operator()<DIM, 128>();\n break;\n case 256:\n dispatch_dim_dstate.template operator()<DIM, 256>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dstate value. Supported values are: 64, 128, 256\");\n }\n };\n\n switch (params.dim) {\n case 64:\n dispatch_dstate.template operator()<64>();\n break;\n case 128:\n dispatch_dstate.template operator()<128>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dim value. Supported values are: 64, 128\");\n }\n }\n#ifdef FLASHINFER_MAMBA_ENABLE_SM90\n else {\n\n auto dispatch_dim_dstate = [&]<int DIM, int DSTATE>() {\n // Alignment checks for vectorized loads in Hopper kernel\n // Note: State uses TMA which requires 128B alignment (checked below)\n // x, z, B, and C use PackedAligned<input_t>\n using load_input_t = PackedAligned<input_t>;\n\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.x) % sizeof(load_input_t) == 0,\n \"x pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.x_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"x batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n if (params.z) {\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.z) % sizeof(load_input_t) == 0,\n \"z pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.z_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"z batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n }\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.B) % sizeof(load_input_t) == 0,\n \"B pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.C) % sizeof(load_input_t) == 0,\n \"C pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.B_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"B batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.C_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"C batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n\n constexpr auto numConsumers = 4;\n constexpr auto numWarps = 1 + numConsumers;\n constexpr auto numStages = 3;\n constexpr auto rowsPerStage = 4 * numConsumers;\n FLASHINFER_CHECK(params.dim % rowsPerStage == 0, \"dim must be divisible by \", rowsPerStage,\n \" for SM90+ kernel\");\n auto scan_func = selective_state_update_kernel_producer_consumer_vertical<\n input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, numConsumers, rowsPerStage,\n numStages>;\n\n dim3 block(warpSize, numWarps);\n dim3 grid(params.batch, params.nheads);\n\n auto nh = params.nheads;\n auto dim = params.dim;\n\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.state) % 128 ==\n 0); // TMA requires 128B aligned\n auto tensorState = tma::createTensorMap<state_t>(\n params.state, params.state_cache_size * nh * dim, DSTATE, rowsPerStage, DSTATE);\n\n // Calculate shared memory size and opt-in to extended shared memory\n using sram_t = SharedStorage<input_t, weight_t, matrixA_t, state_t, rowsPerStage, DIM, DSTATE,\n numStages>;\n constexpr size_t smem_size = sizeof(sram_t);\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(scan_func, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n scan_func<<<grid, block, smem_size, stream>>>(params, tensorState);\n };\n\n auto dispatch_dstate = [&]<int DIM>() {\n switch (params.dstate) {\n case 64:\n dispatch_dim_dstate.template operator()<DIM, 64>();\n break;\n case 128:\n dispatch_dim_dstate.template operator()<DIM, 128>();\n break;\n case 256:\n dispatch_dim_dstate.template operator()<DIM, 256>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dstate value. Supported values are: 64, 128, 256\");\n }\n };\n\n switch (params.dim) {\n case 64:\n dispatch_dstate.template operator()<64>();\n break;\n case 128:\n dispatch_dstate.template operator()<128>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dim value. Supported values are: 64, 128\");\n }\n }\n#endif\n\n#ifdef FLASHINFER_MAMBA_ENABLE_SM100\n else {\n // SM100+ (Blackwell and newer) uses horizontal producer-consumer kernel\n auto dispatch_dim_dstate = [&]<int DIM, int DSTATE>() {\n // Alignment checks for vectorized loads in Blackwell kernel\n using load_input_t = PackedAligned<input_t>;\n\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.x) % sizeof(load_input_t) == 0,\n \"x pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.x_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"x batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n if (params.z) {\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.z) % sizeof(load_input_t) == 0,\n \"z pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.z_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"z batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n }\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.B) % sizeof(load_input_t) == 0,\n \"B pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.C) % sizeof(load_input_t) == 0,\n \"C pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.B_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"B batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.C_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"C batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n\n // profiling showed that it's good to have 4 producers per 64 rows\n constexpr auto numConsumers = (DIM / 64) * 4;\n constexpr auto numProducers = 1;\n constexpr auto numWarps = numProducers + numConsumers;\n\n constexpr auto sectorSize = 32; // bytes\n constexpr auto stageCols = 2 * sectorSize / sizeof(state_t);\n\n constexpr auto totalStages = DSTATE / stageCols;\n constexpr auto numStages = (totalStages >= 4) ? 4 : totalStages;\n\n auto dispatch_heads_groups_ratio = [&]<int headsGroupsRatio>() {\n auto scan_func = selective_state_update_kernel_producer_consumer_horizontal<\n input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, numConsumers, stageCols,\n headsGroupsRatio, numStages>;\n\n dim3 block(warpSize, numWarps);\n dim3 grid(params.batch, params.nheads);\n\n auto nh = params.nheads;\n auto dim = params.dim;\n\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.state) % 128 ==\n 0); // TMA requires 128B aligned\n auto tensorState = tma::createTensorMap<state_t>(\n params.state, params.state_cache_size * nh * dim, DSTATE, DIM, stageCols);\n static_assert(DSTATE % stageCols == 0 && DSTATE >= stageCols);\n\n // Calculate shared memory size and opt-in to extended shared memory\n using sram_t = SharedStorageHorizontal<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE,\n stageCols, numStages>;\n constexpr size_t smem_size = sizeof(sram_t);\n FLASHINFER_CUDA_CHECK(cudaFuncSetAttribute(\n scan_func, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n scan_func<<<grid, block, smem_size, stream>>>(params, tensorState);\n };\n\n switch (params.nheads / params.ngroups) {\n case 1:\n dispatch_heads_groups_ratio.template operator()<1>();\n break;\n case 8:\n dispatch_heads_groups_ratio.template operator()<8>();\n break;\n case 16:\n dispatch_heads_groups_ratio.template operator()<16>();\n break;\n default:\n FLASHINFER_CHECK(false,\n \"Unsupported nheads/ngroups ratio: \", params.nheads / params.ngroups,\n \". Supported values are: 1, 8, 16\");\n }\n };\n\n auto dispatch_dstate = [&]<int DIM>() {\n switch (params.dstate) {\n case 64:\n dispatch_dim_dstate.template operator()<DIM, 64>();\n break;\n case 128:\n dispatch_dim_dstate.template operator()<DIM, 128>();\n break;\n case 256:\n dispatch_dim_dstate.template operator()<DIM, 256>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dstate value. Supported values are: 64, 128, 256\");\n }\n };\n\n switch (params.dim) {\n case 64:\n dispatch_dstate.template operator()<64>();\n break;\n case 128:\n dispatch_dstate.template operator()<128>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dim value. Supported values are: 64, 128\");\n }\n }\n#endif\n}\n\n} // namespace flashinfer::mamba\n\n#endif // FLASHINFER_MAMBA_SELECTIVE_STATE_UPDATE_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/mamba/selective_state_update.cuh\n+++ include/flashinfer/mamba/selective_state_update.cuh\n@@ -33,6 +33,8 @@\n \n using namespace conversion;\n \n+constexpr unsigned warpSize = 32;\n+\n struct SelectiveStateUpdateParams {\n uint32_t batch{}, nheads{}, dim{}, dstate{}, ngroups{}, state_cache_size{};\n int32_t pad_slot_id{-1};\n@@ -86,17 +88,39 @@\n inline constexpr auto getVectorLoadSizeForFullUtilization() -> unsigned {\n static_assert(sizeof(float4) >= sizeof(T));\n constexpr unsigned maxHardwareLoadSize = sizeof(float4) / sizeof(T);\n- constexpr unsigned warpSize = 32;\n constexpr unsigned maxLogicalLoadSize = (unsigned)DSTATE / warpSize;\n return maxHardwareLoadSize < maxLogicalLoadSize ? maxHardwareLoadSize : maxLogicalLoadSize;\n }\n \n __device__ __forceinline__ float warpReduceSum(float val) {\n- constexpr auto warpSize = 32;\n for (int s = warpSize / 2; s > 0; s /= 2) {\n val += __shfl_down_sync(UINT32_MAX, val, s);\n }\n return val;\n+}\n+\n+// Computes a conflict-free column index for shared memory access.\n+// This permutation avoids bank conflicts when threads access strided patterns.\n+//\n+// Without permutation (baseCol directly):\n+// Thread 0 -> Bank 0, Thread 32 -> Bank 0, Thread 64 -> Bank 0 (conflict!)\n+//\n+// With permutation (adding bankCycle offset):\n+// bankCycle = which \"round\" of 32 banks we're in\n+// By offsetting each round by 1 bank:\n+// Thread 0 -> Bank 0\n+// Thread 32 -> Bank 1 (offset by 1)\n+// Thread 64 -> Bank 2 (offset by 2)\n+//\n+// Visual: (stateValuesPerBank=1, numBanks=32, colsPerStage=128)\n+// baseCol: 0 1 2 ... 31 | 32 33 34 ... 63 | 64 ...\n+// bankCycle: 0 0 0 ... 0 | 1 1 1 ... 1 | 2 ...\n+// ii: 0 1 2 ... 31 | 33 34 35 ... 64 | 66 ... (mod colsPerStage)\n+template <int colsPerStage, int stateValuesPerBank, int numBanks>\n+__device__ __forceinline__ int conflict_free_column(int group, int baseCol) {\n+ auto const seq_index = group * colsPerStage + baseCol;\n+ auto const bankCycle = (seq_index / stateValuesPerBank) / numBanks;\n+ return (baseCol + stateValuesPerBank * bankCycle) % colsPerStage;\n }\n \n template <typename input_t, int dim, int dstate>\n@@ -135,7 +159,6 @@\n int const nheads = params.nheads;\n int const ngroups = params.ngroups;\n \n- constexpr auto warpSize = 32;\n constexpr auto rowsPerWarp = (DIM + numWarps - 1) / numWarps;\n \n auto const batch = blockIdx.x;\n@@ -368,7 +391,6 @@\n int const nheads = params.nheads;\n int const ngroups = params.ngroups;\n \n- constexpr auto warpSize = 32;\n constexpr auto numWarps = 1 + consumerWarps;\n \n auto const batch = blockIdx.x;\n@@ -515,13 +537,351 @@\n #endif\n }\n \n+// =============================================================================\n+// Horizontal Producer-Consumer Kernel for SM100+ (Blackwell and newer)\n+// =============================================================================\n+\n+#ifdef FLASHINFER_MAMBA_ENABLE_SM100\n+\n+template <typename input_t, typename weight_t, typename matrixA_t,\n+ typename state_t, //\n+ int dim, int dstate, int stageCols, uint8_t numStages>\n+struct SharedStorageHorizontal {\n+ alignas(128) state_t state[numStages][dim * stageCols];\n+ alignas(alignof(PackedAligned<input_t>)) input_t B[dstate];\n+ alignas(alignof(PackedAligned<input_t>)) input_t C[dstate];\n+\n+ using barrier_t = cuda::barrier<cuda::thread_scope_block>;\n+ barrier_t bar_empty[numStages];\n+ barrier_t bar_full[numStages];\n+ barrier_t bar_consumers;\n+};\n+\n+template <typename state_t, int DIM, int DSTATE, int colsPerStage, int numStages,\n+ bool useStateCache, typename SramT>\n+__device__ __forceinline__ void producer_func_horizontal(SramT& sram,\n+ CUtensorMap const& tensorState,\n+ int state_offset) {\n+ namespace cde = cuda::device::experimental;\n+\n+ auto constexpr stagesReadOnly = numStages;\n+ auto constexpr stagesBoth = DSTATE / colsPerStage - numStages;\n+ auto constexpr stagesWriteOnly = numStages;\n+\n+ auto constexpr bytesState = DIM * colsPerStage * sizeof(state_t);\n+ auto constexpr bytesToArrive = bytesState;\n+\n+ // Phase 1: Read only (filling the pipeline)\n+#pragma unroll\n+ for (int iter = 0; iter < stagesReadOnly; ++iter) {\n+ auto const stage = iter % numStages;\n+ auto const i = iter * colsPerStage;\n+\n+ sram.bar_empty[stage].wait(sram.bar_empty[stage].arrive());\n+\n+ if constexpr (useStateCache) {\n+ cde::cp_async_bulk_tensor_2d_global_to_shared(&sram.state[stage][0], &tensorState, /*x*/ i,\n+ /*y*/ state_offset, sram.bar_full[stage]);\n+ auto const _ = cuda::device::barrier_arrive_tx(sram.bar_full[stage], 1, bytesToArrive);\n+ } else {\n+ auto const _ = sram.bar_full[stage].arrive();\n+ }\n+ }\n+\n+ // Phase 2: Both read and write (steady state)\n+#pragma unroll\n+ for (int iter = 0; iter < stagesBoth; ++iter) {\n+ auto const stage = (stagesReadOnly + iter) % numStages;\n+ auto const i_read = (stagesReadOnly + iter) * colsPerStage;\n+ auto const i_write = iter * colsPerStage;\n+\n+ sram.bar_empty[stage].wait(sram.bar_empty[stage].arrive());\n+\n+ if constexpr (useStateCache) {\n+ // Unblock async proxy for writeback\n+ cde::fence_proxy_async_shared_cta();\n+ // Writeback\n+ cde::cp_async_bulk_tensor_2d_shared_to_global(&tensorState, /*x*/ i_write,\n+ /*y*/ state_offset, &sram.state[stage][0]);\n+ cde::cp_async_bulk_commit_group();\n+ cde::cp_async_bulk_wait_group_read<0>();\n+\n+ // Read next\n+ cde::cp_async_bulk_tensor_2d_global_to_shared(&sram.state[stage][0], &tensorState,\n+ /*x*/ i_read, /*y*/ state_offset,\n+ sram.bar_full[stage]);\n+ auto const _ = cuda::device::barrier_arrive_tx(sram.bar_full[stage], 1, bytesToArrive);\n+ } else {\n+ auto const _ = sram.bar_full[stage].arrive();\n+ }\n+ }\n+\n+ // Phase 3: Write only (draining the pipeline)\n+#pragma unroll\n+ for (int iter = 0; iter < stagesWriteOnly; ++iter) {\n+ auto const stage = (stagesReadOnly + stagesBoth + iter) % numStages;\n+ auto const i_write = (stagesBoth + iter) * colsPerStage;\n+\n+ sram.bar_empty[stage].wait(sram.bar_empty[stage].arrive());\n+\n+ if constexpr (useStateCache) {\n+ // Unblock async proxy for writeback\n+ cde::fence_proxy_async_shared_cta();\n+ cde::cp_async_bulk_tensor_2d_shared_to_global(&tensorState, /*x*/ i_write,\n+ /*y*/ state_offset, &sram.state[stage][0]);\n+ cde::cp_async_bulk_commit_group();\n+ cde::cp_async_bulk_wait_group_read<0>();\n+ }\n+ }\n+}\n+\n+template <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n+ int DSTATE, int consumerWarps, int colsPerStage, int numStages, bool useStateCache>\n+__device__ __forceinline__ void consumer_func_horizontal(\n+ int d, int member, float A_value, float dt_value, float x_value,\n+ SharedStorageHorizontal<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, colsPerStage,\n+ numStages>& sram,\n+ float& out_value) {\n+ namespace cde = cuda::device::experimental;\n+ constexpr auto lanesPerRow = (consumerWarps * warpSize) / DIM;\n+ constexpr auto itemsPerThread = colsPerStage / lanesPerRow;\n+ auto const group = d % (warpSize / lanesPerRow);\n+\n+ // #pragma unroll 1\n+ for (int iBegin = 0, stage = 0; iBegin < DSTATE;\n+ iBegin += colsPerStage, stage = (stage + 1) % numStages) {\n+ // wait for the producer\n+ sram.bar_full[stage].wait(sram.bar_full[stage].arrive());\n+\n+ constexpr auto bankSize = sizeof(uint32_t);\n+ constexpr auto stateValuesPerBank = bankSize / sizeof(state_t);\n+ constexpr auto numBanks = 32;\n+ if constexpr (sizeof(state_t) == sizeof(input_t)) {\n+#pragma unroll\n+ for (int item = 0; item < itemsPerThread; item += stateValuesPerBank) {\n+ auto const baseCol = item + member * itemsPerThread;\n+ // If I just use baseCol as the index, a lot of bank conflicts will arise.\n+ //\n+ auto const ii =\n+ conflict_free_column<colsPerStage, stateValuesPerBank, numBanks>(group, baseCol);\n+\n+ auto const i = iBegin + ii;\n+\n+ auto* sState_ptr = reinterpret_cast<uint*>(&sram.state[stage][d * colsPerStage + ii]);\n+ uint32_t rState = *sState_ptr;\n+ auto* rState_ptr = reinterpret_cast<state_t*>(&rState);\n+\n+ uint32_t rB = *reinterpret_cast<uint32_t const*>(&sram.B[i]);\n+ auto* rB_ptr = reinterpret_cast<input_t const*>(&rB);\n+\n+ uint32_t rC = *reinterpret_cast<uint32_t const*>(&sram.C[i]);\n+ auto* rC_ptr = reinterpret_cast<input_t const*>(&rC);\n+\n+ for (int e = 0; e < stateValuesPerBank; e++) {\n+ float state_value;\n+ if constexpr (!useStateCache) {\n+ state_value = 0.f;\n+ } else {\n+ state_value = toFloat(rState_ptr[e]);\n+ }\n+\n+ auto const B_value = toFloat(rB_ptr[e]);\n+ auto const C_value = toFloat(rC_ptr[e]);\n+\n+ auto const dA = __expf(A_value * dt_value);\n+ auto const dB = B_value * dt_value;\n+ auto const new_state = state_value * dA + dB * x_value;\n+\n+ convertAndStore(&rState_ptr[e], new_state);\n+ out_value += new_state * C_value;\n+ }\n+ *sState_ptr = rState;\n+ }\n+ } else {\n+ for (int item = 0; item < itemsPerThread; item += stateValuesPerBank) {\n+ auto const baseCol = item + member * itemsPerThread;\n+ auto const ii =\n+ conflict_free_column<colsPerStage, stateValuesPerBank, numBanks>(group, baseCol);\n+ auto const i = iBegin + ii;\n+\n+ auto* sState_ptr = reinterpret_cast<uint*>(&sram.state[stage][d * colsPerStage + ii]);\n+ uint32_t rState = *sState_ptr;\n+ auto* rState_ptr = reinterpret_cast<state_t*>(&rState);\n+\n+ for (int e = 0; e < stateValuesPerBank; e++) {\n+ float state_value;\n+ if constexpr (!useStateCache) {\n+ state_value = 0.f;\n+ } else {\n+ state_value = toFloat(rState_ptr[e]);\n+ }\n+\n+ auto const B_value = toFloat(sram.B[i + e]);\n+ auto const C_value = toFloat(sram.C[i + e]);\n+\n+ auto const dA = __expf(A_value * dt_value);\n+ auto const dB = B_value * dt_value;\n+ auto const new_state = state_value * dA + dB * x_value;\n+\n+ convertAndStore(&rState_ptr[e], new_state);\n+ out_value += new_state * C_value;\n+ }\n+ *sState_ptr = rState;\n+ }\n+ }\n+\n+ auto _ = sram.bar_empty[stage].arrive();\n+ }\n+}\n+\n+template <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n+ int DSTATE, int consumerWarps, int colsPerStage, int headsGroupsRatio, int numStages = 1>\n+__global__ void selective_state_update_kernel_producer_consumer_horizontal(\n+ SelectiveStateUpdateParams params, __grid_constant__ CUtensorMap const tensorState) {\n+ auto* __restrict__ output = reinterpret_cast<input_t*>(params.output);\n+ auto const* __restrict__ x = reinterpret_cast<input_t const*>(params.x);\n+ auto const* __restrict__ dt = reinterpret_cast<weight_t const*>(params.dt);\n+ auto const* __restrict__ A = reinterpret_cast<matrixA_t const*>(params.A);\n+ auto const* __restrict__ B = reinterpret_cast<input_t const*>(params.B);\n+ auto const* __restrict__ C = reinterpret_cast<input_t const*>(params.C);\n+ auto const* __restrict__ D = reinterpret_cast<weight_t const*>(params.D);\n+ auto const* __restrict__ dt_bias = reinterpret_cast<weight_t const*>(params.dt_bias);\n+ auto const* __restrict__ z = reinterpret_cast<input_t const*>(params.z);\n+ auto const* __restrict__ state_batch_indices =\n+ reinterpret_cast<int const*>(params.state_batch_indices);\n+\n+ int const nheads = params.nheads;\n+\n+ constexpr auto numWarps = 1 + consumerWarps;\n+\n+ auto const batch = blockIdx.x;\n+ auto const head = blockIdx.y;\n+ auto const group = head / headsGroupsRatio;\n+ auto lane = threadIdx.x % warpSize;\n+ auto warp = threadIdx.y;\n+\n+ auto const state_batch = (state_batch_indices) ? state_batch_indices[batch] : batch;\n+\n+ extern __shared__ uint8_t sbuffer[];\n+ using sram_t = SharedStorageHorizontal<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE,\n+ colsPerStage, numStages>;\n+ auto& sram = *reinterpret_cast<sram_t*>(sbuffer);\n+\n+ namespace cde = cuda::device::experimental;\n+ namespace cg = cooperative_groups;\n+\n+ for (int stage = warp; stage < numStages; stage += numWarps) {\n+ if (lane > 0) continue;\n+ constexpr auto num_arrivals = 1 + consumerWarps * warpSize;\n+ init(&sram.bar_empty[stage], num_arrivals);\n+ init(&sram.bar_full[stage], num_arrivals);\n+ // signal to async proxy that barriers are initilized\n+ cde::fence_proxy_async_shared_cta();\n+ }\n+ if (lane == 0 && warp == 0) {\n+ init(&sram.bar_consumers, warpSize * consumerWarps);\n+ }\n+ __syncthreads();\n+\n+ if (warp == consumerWarps) // producer\n+ {\n+ auto const state_offset = (state_batch * nheads + head) * DIM;\n+\n+ cg::invoke_one(cg::coalesced_threads(), [&]() {\n+ if (state_batch != params.pad_slot_id)\n+ producer_func_horizontal<state_t, DIM, DSTATE, colsPerStage, numStages, true>(\n+ sram, tensorState, state_offset);\n+ else\n+ producer_func_horizontal<state_t, DIM, DSTATE, colsPerStage, numStages, false>(\n+ sram, tensorState, state_offset);\n+ });\n+ } else { // consumers\n+\n+ using load_t = PackedAligned<input_t>;\n+\n+ // Unblock the producer\n+#pragma unroll\n+ for (auto stage = 0; stage < numStages; ++stage) {\n+ auto const _ = sram.bar_empty[stage].arrive();\n+ }\n+\n+ // Load A\n+ auto const A_value = toFloat(A[head]);\n+\n+ // Load D\n+ auto const d_value = D ? toFloat(D[head]) : 0.f;\n+\n+ // load dt_value\n+ auto dt_value = toFloat(dt[batch * params.dt_stride_batch + head]);\n+ if (dt_bias) dt_value += toFloat(dt_bias[head]);\n+ if (params.dt_softplus) {\n+ dt_value = thresholded_softplus(dt_value);\n+ }\n+\n+ if (warp == 0) { // Load B\n+ for (auto d = lane * load_t::count; d < DSTATE; d += warpSize * load_t::count) {\n+ auto* dst = reinterpret_cast<load_t*>(&sram.B[d]);\n+ *dst = *reinterpret_cast<load_t const*>(\n+ &B[batch * params.B_stride_batch + group * DSTATE + d]);\n+ }\n+ } else if (warp == 1) { // Load C\n+ for (auto i = lane * load_t::count; i < DSTATE; i += warpSize * load_t::count) {\n+ auto* dst = reinterpret_cast<load_t*>(&sram.C[i]);\n+ *dst = *reinterpret_cast<load_t const*>(\n+ &C[batch * params.C_stride_batch + group * DSTATE + i]);\n+ }\n+ }\n+\n+ constexpr auto lanesPerRow = (consumerWarps * warpSize) / DIM;\n+ static_assert(lanesPerRow >= 1);\n+ constexpr auto rowsPerWarp = warpSize / lanesPerRow;\n+ auto const group = lane % rowsPerWarp;\n+ auto const member = lane / rowsPerWarp;\n+ auto const d = warp * rowsPerWarp + group;\n+ auto const x_value = toFloat(x[batch * params.x_stride_batch + head * DIM + d]);\n+ auto const z_value = z ? toFloat(z[batch * params.z_stride_batch + head * DIM + d]) : 0.f;\n+\n+ sram.bar_consumers.wait(sram.bar_consumers.arrive());\n+\n+ // Thread\n+ float out_value = 0.f;\n+ if (state_batch != params.pad_slot_id)\n+ consumer_func_horizontal<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, consumerWarps,\n+ colsPerStage, numStages, true>(d, member, A_value, dt_value, x_value,\n+ sram, out_value);\n+ else\n+ consumer_func_horizontal<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, consumerWarps,\n+ colsPerStage, numStages, false>(d, member, A_value, dt_value,\n+ x_value, sram, out_value);\n+\n+ out_value += __shfl_down_sync(UINT32_MAX, out_value, 16);\n+ if constexpr (lanesPerRow == 4) {\n+ out_value += __shfl_down_sync(UINT32_MAX, out_value, 8);\n+ }\n+\n+ if (member == 0) {\n+ out_value += d_value * x_value;\n+\n+ // Write output\n+ if (z) {\n+ float sig_z = __fdividef(1.f, (1.f + __expf(0.f - z_value)));\n+ float silu_z = z_value * sig_z;\n+ out_value *= silu_z;\n+ }\n+ convertAndStore(&output[batch * params.out_stride_batch + head * DIM + d], out_value);\n+ }\n+ }\n+}\n+\n+#endif // FLASHINFER_MAMBA_ENABLE_SM100\n+\n template <typename input_t, typename weight_t, typename matrixA_t, typename state_t>\n void invokeSelectiveStateUpdate(SelectiveStateUpdateParams& params, cudaStream_t stream) {\n auto [sm_major, sm_minor] = GetCudaComputeCapability();\n \n- constexpr auto warpSize = 32;\n-\n-#ifdef FLASHINFER_MAMBA_ENABLE_SM90\n+#ifdef FLASHINFER_MAMBA_ENABLE_SM100\n+ if (sm_major < 10) // pre-Blackwell\n+#elif defined(FLASHINFER_MAMBA_ENABLE_SM90)\n if (sm_major < 9) // pre-Hopper\n #endif\n {\n@@ -626,7 +986,7 @@\n input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, numConsumers, rowsPerStage,\n numStages>;\n \n- dim3 block(32, numWarps);\n+ dim3 block(warpSize, numWarps);\n dim3 grid(params.batch, params.nheads);\n \n auto nh = params.nheads;\n@@ -675,6 +1035,116 @@\n }\n }\n #endif\n+\n+#ifdef FLASHINFER_MAMBA_ENABLE_SM100\n+ else {\n+ // SM100+ (Blackwell and newer) uses horizontal producer-consumer kernel\n+ auto dispatch_dim_dstate = [&]<int DIM, int DSTATE>() {\n+ // Alignment checks for vectorized loads in Blackwell kernel\n+ using load_input_t = PackedAligned<input_t>;\n+\n+ FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.x) % sizeof(load_input_t) == 0,\n+ \"x pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n+ FLASHINFER_CHECK((params.x_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n+ \"x batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n+ if (params.z) {\n+ FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.z) % sizeof(load_input_t) == 0,\n+ \"z pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n+ FLASHINFER_CHECK((params.z_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n+ \"z batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n+ }\n+ FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.B) % sizeof(load_input_t) == 0,\n+ \"B pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n+ FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.C) % sizeof(load_input_t) == 0,\n+ \"C pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n+ FLASHINFER_CHECK((params.B_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n+ \"B batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n+ FLASHINFER_CHECK((params.C_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n+ \"C batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n+\n+ // profiling showed that it's good to have 4 producers per 64 rows\n+ constexpr auto numConsumers = (DIM / 64) * 4;\n+ constexpr auto numProducers = 1;\n+ constexpr auto numWarps = numProducers + numConsumers;\n+\n+ constexpr auto sectorSize = 32; // bytes\n+ constexpr auto stageCols = 2 * sectorSize / sizeof(state_t);\n+\n+ constexpr auto totalStages = DSTATE / stageCols;\n+ constexpr auto numStages = (totalStages >= 4) ? 4 : totalStages;\n+\n+ auto dispatch_heads_groups_ratio = [&]<int headsGroupsRatio>() {\n+ auto scan_func = selective_state_update_kernel_producer_consumer_horizontal<\n+ input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, numConsumers, stageCols,\n+ headsGroupsRatio, numStages>;\n+\n+ dim3 block(warpSize, numWarps);\n+ dim3 grid(params.batch, params.nheads);\n+\n+ auto nh = params.nheads;\n+ auto dim = params.dim;\n+\n+ FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.state) % 128 ==\n+ 0); // TMA requires 128B aligned\n+ auto tensorState = tma::createTensorMap<state_t>(\n+ params.state, params.state_cache_size * nh * dim, DSTATE, DIM, stageCols);\n+ static_assert(DSTATE % stageCols == 0 && DSTATE >= stageCols);\n+\n+ // Calculate shared memory size and opt-in to extended shared memory\n+ using sram_t = SharedStorageHorizontal<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE,\n+ stageCols, numStages>;\n+ constexpr size_t smem_size = sizeof(sram_t);\n+ FLASHINFER_CUDA_CHECK(cudaFuncSetAttribute(\n+ scan_func, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n+\n+ scan_func<<<grid, block, smem_size, stream>>>(params, tensorState);\n+ };\n+\n+ switch (params.nheads / params.ngroups) {\n+ case 1:\n+ dispatch_heads_groups_ratio.template operator()<1>();\n+ break;\n+ case 8:\n+ dispatch_heads_groups_ratio.template operator()<8>();\n+ break;\n+ case 16:\n+ dispatch_heads_groups_ratio.template operator()<16>();\n+ break;\n+ default:\n+ FLASHINFER_CHECK(false,\n+ \"Unsupported nheads/ngroups ratio: \", params.nheads / params.ngroups,\n+ \". Supported values are: 1, 8, 16\");\n+ }\n+ };\n+\n+ auto dispatch_dstate = [&]<int DIM>() {\n+ switch (params.dstate) {\n+ case 64:\n+ dispatch_dim_dstate.template operator()<DIM, 64>();\n+ break;\n+ case 128:\n+ dispatch_dim_dstate.template operator()<DIM, 128>();\n+ break;\n+ case 256:\n+ dispatch_dim_dstate.template operator()<DIM, 256>();\n+ break;\n+ default:\n+ FLASHINFER_CHECK(false, \"Unsupported dstate value. Supported values are: 64, 128, 256\");\n+ }\n+ };\n+\n+ switch (params.dim) {\n+ case 64:\n+ dispatch_dstate.template operator()<64>();\n+ break;\n+ case 128:\n+ dispatch_dstate.template operator()<128>();\n+ break;\n+ default:\n+ FLASHINFER_CHECK(false, \"Unsupported dim value. Supported values are: 64, 128\");\n+ }\n+ }\n+#endif\n }\n \n } // namespace flashinfer::mamba"},"lines_added":{"kind":"number","value":478,"string":"478"},"lines_removed":{"kind":"number","value":8,"string":"8"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":["mamba"],"string":"[\n \"mamba\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["BLACKWELL","HOPPER","SM100","SM90"],"string":"[\n \"BLACKWELL\",\n \"HOPPER\",\n \"SM100\",\n \"SM90\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/mamba/selective_state_update.cuh).\n\nGoal: A Blackwell-optimized version of selective_state_update (mamba)\nTarget hardware: BLACKWELL, HOPPER, SM100, SM90\nTarget models: mamba\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_MAMBA_SELECTIVE_STATE_UPDATE_CUH_\n#define FLASHINFER_MAMBA_SELECTIVE_STATE_UPDATE_CUH_\n\n#include <cooperative_groups.h>\n#include <cooperative_groups/memcpy_async.h>\n#include <cuda_runtime_api.h>\n\n#include <cmath>\n#include <cstdint>\n#include <cuda/barrier>\n\n#include \"../utils.cuh\"\n#include \"../vec_dtypes.cuh\"\n#include \"conversion.cuh\"\n#include \"create_tensor_map.cuh\"\n\nnamespace flashinfer::mamba {\n\nusing namespace conversion;\n\nstruct SelectiveStateUpdateParams {\n uint32_t batch{}, nheads{}, dim{}, dstate{}, ngroups{}, state_cache_size{};\n int32_t pad_slot_id{-1};\n bool dt_softplus{false};\n\n int64_t x_stride_batch{}, dt_stride_batch{}, B_stride_batch{}, C_stride_batch{},\n out_stride_batch{}, z_stride_batch{};\n\n void* __restrict__ state{nullptr}; // state_t: (state_cache_size, nheads, dim, dstate)\n void* __restrict__ x{nullptr}; // input_t: (batch, nheads, dim)\n void* __restrict__ dt{\n nullptr}; // weight_t: (batch, nheads) but pretends to be (batch, nheads, dim)\n void* __restrict__ dt_bias{nullptr}; // weight_t (nheads) but pretends to be (nheads, dim)\n void* __restrict__ A{nullptr}; // matrixA_t: (nheads) but pretends to be (nheads, dim, dstate)\n void* __restrict__ B{nullptr}; // input_t: (batch, ngroups, dstate)\n void* __restrict__ C{nullptr}; // input_t: (batch, ngroups, dstate)\n void* __restrict__ D{nullptr}; // weight_t: (nheads) but pretends to be (nheads, dim)\n void* __restrict__ z{nullptr}; // input_t: (batch, nheads, dim)\n void* __restrict__ output{nullptr}; // input_t: (batch, nheads, dim)\n void* __restrict__ state_batch_indices{nullptr}; // state_batch_indices: (batch,)\n};\n\n__forceinline__ __device__ float softplus(float x) { return __logf(1.f + __expf(x)); }\n\n__device__ __forceinline__ float thresholded_softplus(float dt_value) {\n constexpr float threshold = 20.f;\n return (dt_value <= threshold) ? softplus(dt_value) : dt_value;\n}\n\n// Simple packed vector type for loading N elements of type T\ntemplate <typename T, int N = sizeof(float4) / sizeof(T)>\nstruct alignas(N * sizeof(T)) PackedAligned {\n T val[N];\n static constexpr int count = N;\n using dtype = T;\n};\n\ntemplate <class load_t>\n__device__ __forceinline__ auto make_zeros() -> load_t {\n load_t ret{};\n#pragma unroll\n for (int i = 0; i < ret.count; i++)\n ret.val[i] = typename load_t::dtype{}; // default initialization\n return ret;\n};\n\n// Computes the vector load size that ensures full warp utilization.\n// Avoids cases like: dstate=64, load_t = sizeof(float4)/sizeof(f16), warpsize=32 (32 * 8 > 64)\n// in which case a part of the warp would be idle.\ntemplate <typename T, int DSTATE>\ninline constexpr auto getVectorLoadSizeForFullUtilization() -> unsigned {\n static_assert(sizeof(float4) >= sizeof(T));\n constexpr unsigned maxHardwareLoadSize = sizeof(float4) / sizeof(T);\n constexpr unsigned warpSize = 32;\n constexpr unsigned maxLogicalLoadSize = (unsigned)DSTATE / warpSize;\n return maxHardwareLoadSize < maxLogicalLoadSize ? maxHardwareLoadSize : maxLogicalLoadSize;\n}\n\n__device__ __forceinline__ float warpReduceSum(float val) {\n constexpr auto warpSize = 32;\n for (int s = warpSize / 2; s > 0; s /= 2) {\n val += __shfl_down_sync(UINT32_MAX, val, s);\n }\n return val;\n}\n\ntemplate <typename input_t, int dim, int dstate>\nstruct SharedStorageSimple {\n alignas(alignof(PackedAligned<input_t>)) input_t x[dim];\n float out[dim];\n alignas(alignof(PackedAligned<input_t>)) input_t z[dim];\n alignas(alignof(PackedAligned<input_t>)) input_t B[dstate];\n alignas(alignof(PackedAligned<input_t>)) input_t C[dstate];\n};\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n int DSTATE, int numWarps>\n__global__ void selective_state_update_kernel_simple(SelectiveStateUpdateParams params) {\n auto* __restrict__ output =\n reinterpret_cast<input_t*>(params.output); // output: (batch, nheads, dim)\n auto* __restrict__ state =\n reinterpret_cast<state_t*>(params.state); // state: (batch, nheads, dim, dstate)\n\n auto const* __restrict__ x =\n reinterpret_cast<input_t const*>(params.x); // x: (batch, nheads, dim)\n auto const* __restrict__ dt =\n reinterpret_cast<weight_t const*>(params.dt); // dt: (batch, nheads)\n auto const* __restrict__ A = reinterpret_cast<matrixA_t const*>(params.A); // A: (nheads)\n auto const* __restrict__ B =\n reinterpret_cast<input_t const*>(params.B); // B: (batch, ngroups, dstate)\n auto const* __restrict__ C =\n reinterpret_cast<input_t const*>(params.C); // C: (batch, ngroups, dstate)\n auto const* __restrict__ D = reinterpret_cast<weight_t const*>(params.D); // D: (nheads, dim)\n auto const* __restrict__ dt_bias = reinterpret_cast<weight_t const*>(params.dt_bias); // (nheads)\n auto const* __restrict__ z = reinterpret_cast<input_t const*>(params.z);\n auto const* __restrict__ state_batch_indices =\n reinterpret_cast<int const*>(params.state_batch_indices);\n bool const dt_softplus = params.dt_softplus;\n\n int const nheads = params.nheads;\n int const ngroups = params.ngroups;\n\n constexpr auto warpSize = 32;\n constexpr auto rowsPerWarp = (DIM + numWarps - 1) / numWarps;\n\n auto const batch = blockIdx.x;\n auto const head = blockIdx.y;\n auto const group = head / (nheads / ngroups);\n auto lane = threadIdx.x % warpSize;\n auto warp = threadIdx.y;\n\n auto const state_batch = (state_batch_indices) ? state_batch_indices[batch] : batch;\n state += (state_batch * nheads + head) * DIM * DSTATE;\n\n __shared__ SharedStorageSimple<input_t, DIM, DSTATE> sram;\n\n static constexpr auto stateLoadSize = getVectorLoadSizeForFullUtilization<state_t, DSTATE>();\n using load_state_t = PackedAligned<state_t, stateLoadSize>;\n using load_input_t = PackedAligned<input_t>;\n\n auto const A_value = toFloat(A[head]);\n\n auto dt_value = toFloat(dt[batch * params.dt_stride_batch + head]);\n if (dt_bias) dt_value += toFloat(dt_bias[head]);\n if (dt_softplus) {\n dt_value = thresholded_softplus(dt_value);\n }\n\n auto const dA = __expf(A_value * dt_value);\n\n auto d_value = D ? toFloat(D[head]) : 0.f;\n\n if (warp == 0) {\n for (auto d = lane * load_input_t::count; d < DIM; d += warpSize * load_input_t::count) {\n auto* dst = reinterpret_cast<load_input_t*>(&sram.x[d]);\n *dst = *reinterpret_cast<load_input_t const*>(\n &x[batch * params.x_stride_batch + head * DIM + d]);\n }\n for (auto i = lane * load_input_t::count; i < DSTATE; i += warpSize * load_input_t::count) {\n auto* dst = reinterpret_cast<load_input_t*>(&sram.B[i]);\n *dst = *reinterpret_cast<load_input_t const*>(\n &B[batch * params.B_stride_batch + group * DSTATE + i]);\n }\n } else if (warp == 1) { // Load z, C\n for (auto d = lane * load_input_t::count; d < DIM; d += warpSize * load_input_t::count) {\n auto* dst = reinterpret_cast<load_input_t*>(&sram.z[d]);\n *dst = z ? *reinterpret_cast<load_input_t const*>(\n &z[batch * params.z_stride_batch + head * DIM + d])\n : make_zeros<load_input_t>();\n }\n for (auto i = lane * load_input_t::count; i < DSTATE; i += warpSize * load_input_t::count) {\n auto* dst = reinterpret_cast<load_input_t*>(&sram.C[i]);\n *dst = *reinterpret_cast<load_input_t const*>(\n &C[batch * params.C_stride_batch + group * DSTATE + i]);\n }\n }\n __syncthreads();\n\n for (auto _d = warp * rowsPerWarp; _d < (warp + 1) * rowsPerWarp; _d++) {\n auto d = _d;\n if (d >= DIM) break;\n\n float x_value = toFloat(sram.x[_d]);\n float out_value = d_value * x_value * int(lane == 0); // first lane has the value\n\n for (int i = lane * load_state_t::count; i < DSTATE; i += warpSize * load_state_t::count) {\n auto rState = make_zeros<load_state_t>();\n if (state_batch != params.pad_slot_id)\n rState = *reinterpret_cast<load_state_t*>(&state[d * DSTATE + i]);\n\n for (int ii = 0; ii < load_state_t::count; ii++) {\n auto state_value = toFloat(rState.val[ii]);\n auto B_value = toFloat(sram.B[i + ii]);\n auto C_value = toFloat(sram.C[i + ii]);\n\n auto const dB = B_value * dt_value;\n auto const new_state = state_value * dA + dB * x_value;\n\n convertAndStore(&rState.val[ii], new_state);\n\n out_value += new_state * C_value;\n }\n if (state_batch != params.pad_slot_id)\n *reinterpret_cast<load_state_t*>(&state[d * DSTATE + i]) = rState;\n }\n\n // warpReduce the out_value\n out_value = warpReduceSum(out_value);\n if (lane == 0) {\n sram.out[_d] = out_value;\n }\n }\n\n __syncthreads();\n\n for (int l = lane; l < rowsPerWarp; l += warpSize) {\n auto d = warp * rowsPerWarp + l;\n if (d < DIM) {\n auto out_value = sram.out[d];\n if (z) {\n float z_value = toFloat(sram.z[d]);\n float sig_z = __fdividef(1.f, (1.f + __expf(0.f - z_value)));\n float silu_z = z_value * sig_z;\n out_value *= silu_z;\n }\n convertAndStore(&output[batch * params.out_stride_batch + head * DIM + d], out_value);\n }\n }\n}\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t,\n int rowsPerStage, int dim, int dstate, uint8_t numStages>\nstruct SharedStorage {\n alignas(128) state_t state[numStages][rowsPerStage * dstate];\n alignas(alignof(PackedAligned<input_t>)) input_t x[dim];\n float out[dim]; // dt is special cause we're gonna store input in there as well\n alignas(alignof(PackedAligned<input_t>)) input_t z[dim];\n alignas(alignof(PackedAligned<input_t>)) input_t B[dstate];\n alignas(alignof(PackedAligned<input_t>)) input_t C[dstate];\n\n using barrier_t = cuda::barrier<cuda::thread_scope_block>;\n barrier_t bar_empty[numStages];\n barrier_t bar_full[numStages];\n barrier_t bar_consumers;\n};\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n int DSTATE, int consumerWarps, int rowsPerStage, int numStages, bool useStateCache>\n__device__ __forceinline__ void consumer_func_vertical(\n int lane, int warp, float d_value, float dt_value, float dA,\n SharedStorage<input_t, weight_t, matrixA_t, state_t, rowsPerStage, DIM, DSTATE, numStages>&\n sram) {\n namespace cde = cuda::device::experimental;\n for (auto dBegin = 0, stage = 0; dBegin < DIM;\n dBegin += rowsPerStage, stage = (stage + 1) % numStages) {\n // wait for the producer\n sram.bar_full[stage].wait(sram.bar_full[stage].arrive());\n\n#pragma unroll\n for (auto dd = warp; dd < rowsPerStage; dd += consumerWarps) {\n auto d = dBegin + dd;\n float const x_value = toFloat(sram.x[d]);\n float out_value = d_value * x_value * int(lane == 0); // first lane has the value\n\n constexpr auto bankSize = sizeof(uint32_t);\n constexpr auto stateValuesPerBank = bankSize / sizeof(state_t);\n\n if constexpr (sizeof(state_t) == sizeof(input_t)) {\n for (int i = lane * stateValuesPerBank; i < DSTATE; i += warpSize * stateValuesPerBank) {\n auto* sState_ptr = reinterpret_cast<uint32_t*>(&sram.state[stage][dd * DSTATE + i]);\n uint32_t rState = *sState_ptr;\n auto* rState_ptr = reinterpret_cast<state_t*>(&rState);\n\n uint32_t rB = *reinterpret_cast<uint32_t const*>(&sram.B[i]);\n auto* rB_ptr = reinterpret_cast<input_t const*>(&rB);\n\n uint32_t rC = *reinterpret_cast<uint32_t const*>(&sram.C[i]);\n auto* rC_ptr = reinterpret_cast<input_t const*>(&rC);\n\n for (int e = 0; e < stateValuesPerBank; e++) {\n float state_value;\n if constexpr (!useStateCache) {\n state_value = 0.f;\n } else {\n state_value = toFloat(rState_ptr[e]);\n }\n auto const B_value = toFloat(rB_ptr[e]);\n auto const C_value = toFloat(rC_ptr[e]);\n\n auto const dB = B_value * dt_value;\n auto const new_state = state_value * dA + dB * x_value;\n\n convertAndStore(&rState_ptr[e], new_state);\n out_value += new_state * C_value;\n }\n *sState_ptr = rState;\n }\n } else {\n for (int i = lane * stateValuesPerBank; i < DSTATE; i += warpSize * stateValuesPerBank) {\n auto* sState_ptr = reinterpret_cast<uint32_t*>(&sram.state[stage][dd * DSTATE + i]);\n uint32_t rState = *sState_ptr;\n auto* rState_ptr = reinterpret_cast<state_t*>(&rState);\n\n for (int e = 0; e < stateValuesPerBank; e++) {\n float state_value;\n if constexpr (!useStateCache) {\n state_value = 0.f;\n } else {\n state_value = toFloat(rState_ptr[e]);\n }\n auto const B_value = toFloat(sram.B[i + e]);\n auto const C_value = toFloat(sram.C[i + e]);\n auto const dB = B_value * dt_value;\n auto const new_state = state_value * dA + dB * x_value;\n\n convertAndStore(&rState_ptr[e], new_state);\n out_value += new_state * C_value;\n }\n *sState_ptr = rState;\n }\n }\n\n out_value = warpReduceSum(out_value);\n if (lane == 0) {\n sram.out[d] = out_value;\n }\n }\n\n // Unblock producer\n cde::fence_proxy_async_shared_cta();\n auto _ = sram.bar_empty[stage].arrive();\n }\n}\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t, int DIM,\n int DSTATE, int consumerWarps, int rowsPerStage, int numStages = 1>\n__global__ void selective_state_update_kernel_producer_consumer_vertical(\n SelectiveStateUpdateParams params, __grid_constant__ CUtensorMap const tensorState) {\n#ifdef FLASHINFER_MAMBA_ENABLE_SM90\n auto* __restrict__ output = reinterpret_cast<input_t*>(params.output);\n\n auto const* __restrict__ x = reinterpret_cast<input_t const*>(params.x);\n auto const* __restrict__ dt = reinterpret_cast<weight_t const*>(params.dt);\n auto const* __restrict__ A = reinterpret_cast<matrixA_t const*>(params.A);\n auto const* __restrict__ B = reinterpret_cast<input_t const*>(params.B);\n auto const* __restrict__ C = reinterpret_cast<input_t const*>(params.C);\n auto const* __restrict__ D = reinterpret_cast<weight_t const*>(params.D);\n auto const* __restrict__ dt_bias = reinterpret_cast<weight_t const*>(params.dt_bias);\n auto const* __restrict__ z = reinterpret_cast<input_t const*>(params.z);\n auto const* __restrict__ state_batch_indices =\n reinterpret_cast<int const*>(params.state_batch_indices);\n\n int const nheads = params.nheads;\n int const ngroups = params.ngroups;\n\n constexpr auto warpSize = 32;\n constexpr auto numWarps = 1 + consumerWarps;\n\n auto const batch = blockIdx.x;\n auto const head = blockIdx.y;\n auto const group = head / (nheads / ngroups);\n auto lane = threadIdx.x % warpSize;\n auto warp = threadIdx.y;\n\n auto const state_batch = (state_batch_indices) ? state_batch_indices[batch] : batch;\n\n using sram_t =\n SharedStorage<input_t, weight_t, matrixA_t, state_t, rowsPerStage, DIM, DSTATE, numStages>;\n // Use dynamic shared memory to allow opting into extended shared memory on SM90+\n extern __shared__ __align__(128) char smem[];\n sram_t& sram = *reinterpret_cast<sram_t*>(smem);\n\n namespace cde = cuda::device::experimental;\n namespace cg = cooperative_groups;\n\n for (int stage = warp; stage < numStages; stage += numWarps) {\n if (lane > 0) continue;\n constexpr auto num_arrivals = 1 + consumerWarps * warpSize;\n init(&sram.bar_empty[stage], num_arrivals);\n init(&sram.bar_full[stage], num_arrivals);\n // signal to async proxy that barriers are initilized\n cde::fence_proxy_async_shared_cta();\n }\n if (lane == 0 && warp == 0) {\n init(&sram.bar_consumers, warpSize * consumerWarps);\n }\n __syncthreads();\n\n if (warp == consumerWarps) // producer\n {\n auto const state_offset = (state_batch * nheads + head) * DIM;\n\n for (int d = 0, stage = 0; d < DIM + rowsPerStage * numStages;\n d += rowsPerStage, stage = (stage + 1) % numStages) {\n if (lane == 0) {\n cg::invoke_one(cg::coalesced_threads(), [&]() {\n sram.bar_empty[stage].wait(sram.bar_empty[stage].arrive());\n\n if (state_batch != params.pad_slot_id) {\n // Writeback\n if (d >= rowsPerStage * numStages) {\n cde::cp_async_bulk_tensor_2d_shared_to_global(\n &tensorState,\n /*x*/ 0,\n /*y*/ state_offset + d - rowsPerStage * numStages, &sram.state[stage][0]);\n cde::cp_async_bulk_commit_group();\n cde::cp_async_bulk_wait_group_read<0>();\n }\n\n if (d < DIM) {\n cde::cp_async_bulk_tensor_2d_global_to_shared(&sram.state[stage][0], &tensorState,\n /*x*/ 0, /*y*/ state_offset + d,\n sram.bar_full[stage]);\n\n // Unblock the consumers\n auto constexpr bytesState = rowsPerStage * DSTATE * sizeof(state_t);\n auto constexpr bytesToArrive = bytesState;\n auto const _ =\n cuda::device::barrier_arrive_tx(sram.bar_full[stage], 1, bytesToArrive);\n }\n } else {\n auto const _ = sram.bar_full[stage].arrive();\n }\n });\n }\n }\n } else { // consumers\n\n using load_t = PackedAligned<input_t>;\n\n#pragma unroll\n // Unblock the producer\n for (uint8_t stage = 0; stage < numStages; ++stage) {\n auto const _ = sram.bar_empty[stage].arrive();\n }\n\n // Load A\n auto const A_value = toFloat(A[head]);\n\n // Load D\n auto const d_value = D ? toFloat(D[head]) : 0.f;\n\n // load dt_value\n auto dt_value = toFloat(dt[batch * params.dt_stride_batch + head]);\n if (dt_bias) dt_value += toFloat(dt_bias[head]);\n if (params.dt_softplus) {\n dt_value = thresholded_softplus(dt_value);\n }\n auto const dA = __expf(A_value * dt_value);\n\n if (warp == 0) { // Load x, B\n for (auto d = lane * load_t::count; d < DIM; d += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.x[d]);\n *dst = *reinterpret_cast<load_t const*>(&x[batch * params.x_stride_batch + head * DIM + d]);\n }\n for (auto i = lane * load_t::count; i < DSTATE; i += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.B[i]);\n *dst = *reinterpret_cast<load_t const*>(\n &B[batch * params.B_stride_batch + group * DSTATE + i]);\n }\n } else if (warp == 1) { // Load z, C\n for (auto d = lane * load_t::count; d < DIM; d += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.z[d]);\n *dst =\n z ? *reinterpret_cast<load_t const*>(&z[batch * params.z_stride_batch + head * DIM + d])\n : make_zeros<load_t>();\n }\n for (auto i = lane * load_t::count; i < DSTATE; i += warpSize * load_t::count) {\n auto* dst = reinterpret_cast<load_t*>(&sram.C[i]);\n *dst = *reinterpret_cast<load_t const*>(\n &C[batch * params.C_stride_batch + group * DSTATE + i]);\n }\n }\n\n sram.bar_consumers.wait(sram.bar_consumers.arrive());\n\n if (state_batch != params.pad_slot_id)\n consumer_func_vertical<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, consumerWarps,\n rowsPerStage, numStages, true>(lane, warp, d_value, dt_value, dA,\n sram);\n else\n consumer_func_vertical<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, consumerWarps,\n rowsPerStage, numStages, false>(lane, warp, d_value, dt_value, dA,\n sram);\n\n // Write output\n sram.bar_consumers.wait(sram.bar_consumers.arrive());\n auto d = warp * warpSize + lane;\n if (d < DIM) {\n auto out_value = sram.out[d];\n if (z) {\n float z_value = toFloat(sram.z[d]);\n float sig_z = __fdividef(1.f, (1.f + __expf(0.f - z_value)));\n float silu_z = z_value * sig_z;\n out_value *= silu_z;\n }\n convertAndStore(&output[batch * params.out_stride_batch + head * DIM + d], out_value);\n }\n }\n#endif\n}\n\ntemplate <typename input_t, typename weight_t, typename matrixA_t, typename state_t>\nvoid invokeSelectiveStateUpdate(SelectiveStateUpdateParams& params, cudaStream_t stream) {\n auto [sm_major, sm_minor] = GetCudaComputeCapability();\n\n constexpr auto warpSize = 32;\n\n#ifdef FLASHINFER_MAMBA_ENABLE_SM90\n if (sm_major < 9) // pre-Hopper\n#endif\n {\n auto dispatch_dim_dstate = [&]<int DIM, int DSTATE>() {\n // Alignment checks for vectorized loads in simple kernel\n constexpr auto stateLoadSize = getVectorLoadSizeForFullUtilization<state_t, DSTATE>();\n using load_state_t = PackedAligned<state_t, stateLoadSize>;\n using load_input_t = PackedAligned<input_t>;\n\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.state) % sizeof(load_state_t) == 0,\n \"state pointer must be aligned to \", sizeof(load_state_t), \" bytes\");\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.x) % sizeof(load_input_t) == 0,\n \"x pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.x_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"x batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n if (params.z) {\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.z) % sizeof(load_input_t) == 0,\n \"z pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.z_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"z batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n }\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.B) % sizeof(load_input_t) == 0,\n \"B pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.C) % sizeof(load_input_t) == 0,\n \"C pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.B_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"B batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.C_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"C batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.dim * params.dstate * sizeof(state_t)) % sizeof(load_state_t) == 0,\n \"state head stride must be aligned to \", sizeof(load_state_t), \" bytes\");\n\n constexpr int numWarps = 4;\n dim3 block(warpSize, numWarps);\n dim3 grid(params.batch, params.nheads);\n selective_state_update_kernel_simple<input_t, weight_t, matrixA_t, state_t, DIM, DSTATE,\n numWarps><<<grid, block, 0, stream>>>(params);\n };\n\n auto dispatch_dstate = [&]<int DIM>() {\n switch (params.dstate) {\n case 64:\n dispatch_dim_dstate.template operator()<DIM, 64>();\n break;\n case 128:\n dispatch_dim_dstate.template operator()<DIM, 128>();\n break;\n case 256:\n dispatch_dim_dstate.template operator()<DIM, 256>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dstate value. Supported values are: 64, 128, 256\");\n }\n };\n\n switch (params.dim) {\n case 64:\n dispatch_dstate.template operator()<64>();\n break;\n case 128:\n dispatch_dstate.template operator()<128>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dim value. Supported values are: 64, 128\");\n }\n }\n#ifdef FLASHINFER_MAMBA_ENABLE_SM90\n else {\n\n auto dispatch_dim_dstate = [&]<int DIM, int DSTATE>() {\n // Alignment checks for vectorized loads in Hopper kernel\n // Note: State uses TMA which requires 128B alignment (checked below)\n // x, z, B, and C use PackedAligned<input_t>\n using load_input_t = PackedAligned<input_t>;\n\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.x) % sizeof(load_input_t) == 0,\n \"x pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.x_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"x batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n if (params.z) {\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.z) % sizeof(load_input_t) == 0,\n \"z pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.z_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"z batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n }\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.B) % sizeof(load_input_t) == 0,\n \"B pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.C) % sizeof(load_input_t) == 0,\n \"C pointer must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.B_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"B batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n FLASHINFER_CHECK((params.C_stride_batch * sizeof(input_t)) % sizeof(load_input_t) == 0,\n \"C batch stride must be aligned to \", sizeof(load_input_t), \" bytes\");\n\n constexpr auto numConsumers = 4;\n constexpr auto numWarps = 1 + numConsumers;\n constexpr auto numStages = 3;\n constexpr auto rowsPerStage = 4 * numConsumers;\n FLASHINFER_CHECK(params.dim % rowsPerStage == 0, \"dim must be divisible by \", rowsPerStage,\n \" for SM90+ kernel\");\n auto scan_func = selective_state_update_kernel_producer_consumer_vertical<\n input_t, weight_t, matrixA_t, state_t, DIM, DSTATE, numConsumers, rowsPerStage,\n numStages>;\n\n dim3 block(32, numWarps);\n dim3 grid(params.batch, params.nheads);\n\n auto nh = params.nheads;\n auto dim = params.dim;\n\n FLASHINFER_CHECK(reinterpret_cast<uintptr_t>(params.state) % 128 ==\n 0); // TMA requires 128B aligned\n auto tensorState = tma::createTensorMap<state_t>(\n params.state, params.state_cache_size * nh * dim, DSTATE, rowsPerStage, DSTATE);\n\n // Calculate shared memory size and opt-in to extended shared memory\n using sram_t = SharedStorage<input_t, weight_t, matrixA_t, state_t, rowsPerStage, DIM, DSTATE,\n numStages>;\n constexpr size_t smem_size = sizeof(sram_t);\n FLASHINFER_CUDA_CHECK(\n cudaFuncSetAttribute(scan_func, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size));\n\n scan_func<<<grid, block, smem_size, stream>>>(params, tensorState);\n };\n\n auto dispatch_dstate = [&]<int DIM>() {\n switch (params.dstate) {\n case 64:\n dispatch_dim_dstate.template operator()<DIM, 64>();\n break;\n case 128:\n dispatch_dim_dstate.template operator()<DIM, 128>();\n break;\n case 256:\n dispatch_dim_dstate.template operator()<DIM, 256>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dstate value. Supported values are: 64, 128, 256\");\n }\n };\n\n switch (params.dim) {\n case 64:\n dispatch_dstate.template operator()<64>();\n break;\n case 128:\n dispatch_dstate.template operator()<128>();\n break;\n default:\n FLASHINFER_CHECK(false, \"Unsupported dim value. Supported values are: 64, 128\");\n }\n }\n#endif\n}\n\n} // namespace flashinfer::mamba\n\n#endif // FLASHINFER_MAMBA_SELECTIVE_STATE_UPDATE_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nThis contributes a `selective_state_update` kernel that has been manually optimized for sm100.\n\n<img width=\"3000\" height=\"3000\" alt=\"runtime_vs_batch_size_NVIDIA_B200\" src=\"https://github.com/user-attachments/assets/2718d992-1066-4385-b120-d22eccd3a941\" />\n\n\nTechnically, the code in the sm100 module can be compiled and executed on sm90, but the performance of this kernel on Hopper is not great (see the image below).\n\n<img width=\"1173\" height=\"1173\" alt=\"image\" src=\"https://github.com/user-attachments/assets/eed59b15-8bf1-4123-9290-5a342ee7aada\" />\n\n## Algorithm\nThe algorithmic differences between the new `selective_state_update_kernel_producer_consumer_horizontal` and the older Hopper-specific `selective_state_update_kernel_producer_consumer_vertical` are summarized below. Each CTA processes a single head. In the `vertical` case, each warp processes a row, and then performs a reduction using `shfl_sync` intrinsics. In case of the `horizontal` kernel, each thread consecutively processes multiple row elements while keeping track of the sum. This new treatment allows to lift the bottleneck off of the warp-level reduction on Blackwell.\n\n<img width=\"1097\" height=\"449\" alt=\"Screenshot 2026-01-20 at 5 53 48 PM\" src=\"https://github.com/user-attachments/assets/fa02b290-9c76-4b03-b3f8-9a0c5b734ee4\" />\n\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\nCould you please check consumer_func_horizontal and let me know whether the comments about the bank-conflict-free indexing suffices.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added support for SM100 (Blackwell) and newer GPU architectures in Mamba selective state update operations\n * Automatic kernel selection based on device compute capability for optimal performance\n\n* **Refactor**\n * Improved runtime dispatch logic to route operations to architecture-specific optimized kernels\n\n* **Bug Fixes**\n * Enhanced CUDA error checking mechanism for better diagnostics\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1189,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"2bf87713dade8c6094ca3ff5e246e1ff72e97644"},"date":{"kind":"string","value":"2026-01-13T22:44:35-08:00"},"pr_number":{"kind":"number","value":2327,"string":"2,327"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2327"},"title":{"kind":"string","value":"[perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32 (#2327)"},"message":{"kind":"string","value":"[perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32 (#2327)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nImproves gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch\nsizes <= 32.\n\nThese are shapes typical for DeepSeek V3 and Qwen 3 235B - q, k, v, and\no_proj:\n\n```\n+-------+-------+------+-----------+---------------+--------------+---------------+--------------+-------------+\n| batch | out | in | fp16 (us) | fp8 before(us)| ratio before | fp8 after (us)| ratio after | improvement |\n+-------+-------+------+-----------+---------------+--------------+---------------+--------------+-------------+\n| 1 | 1536 | 7168 | 14.26 | | | 20.48 | 0.66 | |\n| 8 | 1536 | 7168 | 14.37 | 24.58 | 0.58 | 20.48 | 0.70 | 1.20 |\n| 16 | 1536 | 7168 | 14.40 | 24.56 | 0.59 | 20.48 | 0.74 | 1.20 |\n| 32 | 1536 | 7168 | 18.40 | 24.56 | 0.75 | 20.48 | 0.85 | 1.20 |\n| 1 | 24576 | 1536 | 22.61 | | | 18.46 | 1.32 | |\n| 8 | 24576 | 1536 | 22.56 | 22.56 | 1.00 | 18.46 | 1.22 | 1.22 |\n| 16 | 24576 | 1536 | 22.59 | 22.56 | 1.00 | 18.46 | 1.23 | 1.22 |\n| 32 | 24576 | 1536 | 22.62 | 22.53 | 1.00 | 20.48 | 1.10 | 1.10 |\n| 1 | 32768 | 512 | 14.37 | | | 14.37 | 1.00 | |\n| 8 | 32768 | 512 | 14.34 | 16.35 | 0.88 | 14.37 | 1.00 | 1.14 |\n| 16 | 32768 | 512 | 14.37 | 14.40 | 1.00 | 14.34 | 1.00 | 1.00 |\n| 32 | 32768 | 512 | 14.34 | 14.37 | 1.00 | 14.37 | 1.00 | 1.00 |\n| 1 | 7168 | 7168 | 28.78 | | | 22.53 | 1.28 | |\n| 8 | 7168 | 7168 | 28.70 | 32.77 | 0.88 | 22.53 | 1.27 | 1.45 |\n| 16 | 7168 | 7168 | 28.67 | 30.75 | 0.93 | 22.53 | 1.27 | 1.37 |\n| 32 | 7168 | 7168 | 30.75 | 28.67 | 1.07 | 22.56 | 1.36 | 1.27 |\n| 1 | 12288 | 4096 | 31.74 | | | 20.51 | 1.55 | |\n| 8 | 12288 | 4096 | 29.73 | 26.62 | 1.12 | 20.51 | 1.45 | 1.30 |\n| 16 | 12288 | 4096 | 28.70 | 26.64 | 1.08 | 20.51 | 1.40 | 1.30 |\n| 32 | 12288 | 4096 | 28.67 | 22.54 | 1.27 | 24.58 | 1.17 | 0.92 |\n| 1 | 4096 | 4096 | 16.46 | | | 16.40 | 1.01 | |\n| 8 | 4096 | 4096 | 16.42 | 18.43 | 0.89 | 16.38 | 1.00 | 1.13 |\n| 16 | 4096 | 4096 | 16.42 | 18.46 | 0.89 | 16.38 | 1.00 | 1.13 |\n| 32 | 4096 | 4096 | 14.34 | 18.43 | 0.78 | 16.38 | 0.88 | 1.13 |\n| | | | | | | | | avg: 1.18 |\n+-------+-------+------+-----------+---------------+--------------+---------------+--------------+-------------+\n```\n\nBenchmarking script I'm using is modified version of user's script in:\nhttps://github.com/issues/recent?issue=flashinfer-ai%7Cflashinfer%7C2146\n\nCredit to @depaulmillz on the transpose trick:\nhttps://github.com/NVIDIA/cutlass/issues/2923#issuecomment-3707263529\n\n## 🔍 Related Issues\n\nFound this optimization while working on\nhttps://github.com/issues/recent?issue=flashinfer-ai%7Cflashinfer%7C2146\n- note this user's issue is still outstanding - their shapes are\ndifferent.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n * Added performance optimization for small batch matrix operations\n\n* **Tests**\n* Expanded test coverage for small batch configurations with various\nmatrix dimensions\n\n* **Chores**\n * Updated benchmark suite to evaluate broader range of operation sizes\n\n<sub>✏️ Tip: You can customize this high-level summary in your review\nsettings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"csrc/gemm_groupwise_sm100.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <flashinfer/cutlass_utils.cuh>\n\n#include \"tvm_ffi_utils.h\"\n\nusing namespace flashinfer;\n\n#define DISPATCH_DLPACK_INPUT_OUTPUT_DTYPE(input_dtype, output_dtype, c_type_in, c_type_out, ...) \\\n [&]() -> bool { \\\n return DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP16(output_dtype, c_type_out, [&] { \\\n return DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP8(input_dtype, c_type_in, \\\n [&] { return __VA_ARGS__(); }); \\\n }); \\\n }()\n\n#define DISPATCH_SCALE_GRANULARITY(scale_granularity_m, scale_granularity_n, scale_granularity_k, \\\n SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, \\\n ...) \\\n [&]() -> bool { \\\n if (scale_granularity_m == 1 && scale_granularity_n == 128 && scale_granularity_k == 128) { \\\n constexpr int SCALE_GRANULARITY_M = 1; \\\n constexpr int SCALE_GRANULARITY_N = 128; \\\n constexpr int SCALE_GRANULARITY_K = 128; \\\n return __VA_ARGS__(); \\\n } else if (scale_granularity_m == 128 && scale_granularity_n == 128 && \\\n scale_granularity_k == 128) { \\\n constexpr int SCALE_GRANULARITY_M = 128; \\\n constexpr int SCALE_GRANULARITY_N = 128; \\\n constexpr int SCALE_GRANULARITY_K = 128; \\\n return __VA_ARGS__(); \\\n } \\\n TVM_FFI_ICHECK(false) << \"Unsupported scale granularity\"; \\\n return false; \\\n }()\n\n#define DISPATCH_MMA_SM(mma_sm, MMA_SM, ...) \\\n [&]() -> bool { \\\n if (mma_sm == 1) { \\\n constexpr int MMA_SM = 1; \\\n return __VA_ARGS__(); \\\n } else if (mma_sm == 2) { \\\n constexpr int MMA_SM = 2; \\\n return __VA_ARGS__(); \\\n } \\\n TVM_FFI_ICHECK(false) << \"Unsupported MMA SM\"; \\\n return false; \\\n }()\n\n#define DISPATCH_SCALE_MAJOR_K(scale_major_mode, SCALE_MAJOR_K, ...) \\\n [&]() -> bool { \\\n if (scale_major_mode == \"K\") { \\\n constexpr bool SCALE_MAJOR_K = true; \\\n return __VA_ARGS__(); \\\n } else if (scale_major_mode == \"MN\") { \\\n constexpr bool SCALE_MAJOR_K = false; \\\n return __VA_ARGS__(); \\\n } \\\n TVM_FFI_ICHECK(false) << \"Unsupported Scale Major Mode\"; \\\n return false; \\\n }()\n\nnamespace flashinfer {\nnamespace gemm {\n\ntemplate <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n int MmaSM, typename DTypeIn, typename DTypeOut>\ncudaError_t CutlassGroupwiseScaledGEMMSM100(void* float_buffer, size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr, float* SFA_ptr,\n float* SFB_ptr, DTypeOut* C_ptr, int m, int n, int k,\n int l, cudaStream_t stream);\n\n} // namespace gemm\n} // namespace flashinfer\n\nvoid CutlassGemmGroupwiseScaledSM100(TensorView float_workspace_buffer, TensorView A, TensorView B,\n TensorView SFA, TensorView SFB, TensorView C,\n int64_t scale_granularity_m, int64_t scale_granularity_n,\n int64_t scale_granularity_k, std::string scale_major_mode,\n int64_t mma_sm) {\n ffi::CUDADeviceGuard device_guard(float_workspace_buffer.device().device_id);\n const cudaStream_t stream = get_stream(C.device());\n DISPATCH_SCALE_MAJOR_K(scale_major_mode, SCALE_MAJOR_K, [&] {\n return DISPATCH_MMA_SM(mma_sm, MMA_SM, [&] {\n return DISPATCH_DLPACK_INPUT_OUTPUT_DTYPE(A.dtype(), C.dtype(), c_type_in, c_type_out, [&] {\n return DISPATCH_SCALE_GRANULARITY(\n scale_granularity_m, scale_granularity_n, scale_granularity_k, SCALE_GRANULARITY_M,\n SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, [&] {\n using cutlass_t_in = cutlass_dtype_t<c_type_in>;\n using cutlass_t_out = cutlass_dtype_t<c_type_out>;\n auto status = flashinfer::gemm::CutlassGroupwiseScaledGEMMSM100<\n SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, SCALE_MAJOR_K,\n MMA_SM>(static_cast<float*>(float_workspace_buffer.data_ptr()),\n get_element_size(float_workspace_buffer) * float_workspace_buffer.size(0),\n static_cast<cutlass_t_in*>(A.data_ptr()),\n static_cast<cutlass_t_in*>(B.data_ptr()),\n static_cast<float*>(SFA.data_ptr()), static_cast<float*>(SFB.data_ptr()),\n static_cast<cutlass_t_out*>(C.data_ptr()), A.size(0), B.size(0),\n A.size(1), 1, stream);\n TVM_FFI_ICHECK_EQ(status, cudaSuccess)\n << \"Failed to run cutlass gemm groupwise scaled sm100\"\n << cudaGetErrorString(status);\n return true;\n });\n });\n });\n });\n}\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <flashinfer/cutlass_utils.cuh>\n\n#include \"tvm_ffi_utils.h\"\n\nusing namespace flashinfer;\n\n#define DISPATCH_DLPACK_INPUT_OUTPUT_DTYPE(input_dtype, output_dtype, c_type_in, c_type_out, ...) \\\n [&]() -> bool { \\\n return DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP16(output_dtype, c_type_out, [&] { \\\n return DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP8(input_dtype, c_type_in, \\\n [&] { return __VA_ARGS__(); }); \\\n }); \\\n }()\n\n#define DISPATCH_SCALE_GRANULARITY(scale_granularity_m, scale_granularity_n, scale_granularity_k, \\\n SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, \\\n ...) \\\n [&]() -> bool { \\\n if (scale_granularity_m == 1 && scale_granularity_n == 128 && scale_granularity_k == 128) { \\\n constexpr int SCALE_GRANULARITY_M = 1; \\\n constexpr int SCALE_GRANULARITY_N = 128; \\\n constexpr int SCALE_GRANULARITY_K = 128; \\\n return __VA_ARGS__(); \\\n } else if (scale_granularity_m == 128 && scale_granularity_n == 128 && \\\n scale_granularity_k == 128) { \\\n constexpr int SCALE_GRANULARITY_M = 128; \\\n constexpr int SCALE_GRANULARITY_N = 128; \\\n constexpr int SCALE_GRANULARITY_K = 128; \\\n return __VA_ARGS__(); \\\n } \\\n TVM_FFI_ICHECK(false) << \"Unsupported scale granularity\"; \\\n return false; \\\n }()\n\n#define DISPATCH_MMA_SM(mma_sm, MMA_SM, ...) \\\n [&]() -> bool { \\\n if (mma_sm == 1) { \\\n constexpr int MMA_SM = 1; \\\n return __VA_ARGS__(); \\\n } else if (mma_sm == 2) { \\\n constexpr int MMA_SM = 2; \\\n return __VA_ARGS__(); \\\n } \\\n TVM_FFI_ICHECK(false) << \"Unsupported MMA SM\"; \\\n return false; \\\n }()\n\n#define DISPATCH_SCALE_MAJOR_K(scale_major_mode, SCALE_MAJOR_K, ...) \\\n [&]() -> bool { \\\n if (scale_major_mode == \"K\") { \\\n constexpr bool SCALE_MAJOR_K = true; \\\n return __VA_ARGS__(); \\\n } else if (scale_major_mode == \"MN\") { \\\n constexpr bool SCALE_MAJOR_K = false; \\\n return __VA_ARGS__(); \\\n } \\\n TVM_FFI_ICHECK(false) << \"Unsupported Scale Major Mode\"; \\\n return false; \\\n }()\n\nnamespace flashinfer {\nnamespace gemm {\n\ntemplate <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n int MmaSM, typename DTypeIn, typename DTypeOut>\ncudaError_t CutlassGroupwiseScaledGEMMSM100(void* float_buffer, size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr, float* SFA_ptr,\n float* SFB_ptr, DTypeOut* D_ptr, int m, int n, int k,\n int l, cudaStream_t stream);\n\ntemplate <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n int MmaSM, typename DTypeIn, typename DTypeOut>\ncudaError_t CutlassGroupwiseScaledGEMMSM100LowLatency(void* float_buffer,\n size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr,\n float* SFA_ptr, float* SFB_ptr,\n DTypeOut* D_ptr, int m, int n, int k, int l,\n cudaStream_t stream);\n\n} // namespace gemm\n} // namespace flashinfer\n\nvoid CutlassGemmGroupwiseScaledSM100(TensorView float_workspace_buffer, TensorView A, TensorView B,\n TensorView SFA, TensorView SFB, TensorView C,\n int64_t scale_granularity_m, int64_t scale_granularity_n,\n int64_t scale_granularity_k, std::string scale_major_mode,\n int64_t mma_sm) {\n ffi::CUDADeviceGuard device_guard(float_workspace_buffer.device().device_id);\n const cudaStream_t stream = get_stream(C.device());\n DISPATCH_SCALE_MAJOR_K(scale_major_mode, SCALE_MAJOR_K, [&] {\n return DISPATCH_MMA_SM(mma_sm, MMA_SM, [&] {\n return DISPATCH_DLPACK_INPUT_OUTPUT_DTYPE(A.dtype(), C.dtype(), c_type_in, c_type_out, [&] {\n return DISPATCH_SCALE_GRANULARITY(\n scale_granularity_m, scale_granularity_n, scale_granularity_k, SCALE_GRANULARITY_M,\n SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, [&] {\n using cutlass_t_in = cutlass_dtype_t<c_type_in>;\n using cutlass_t_out = cutlass_dtype_t<c_type_out>;\n const int m = static_cast<int>(A.size(0));\n const int n = static_cast<int>(B.size(0));\n const int k = static_cast<int>(A.size(1));\n\n cudaError_t status;\n // Small-batch-size kernel is not compatible with (scale_granularity_m=128).\n constexpr bool can_use_small_batch = (SCALE_GRANULARITY_M == 1);\n if (can_use_small_batch && m <= 32) {\n status = flashinfer::gemm::CutlassGroupwiseScaledGEMMSM100LowLatency<\n SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, SCALE_MAJOR_K,\n MMA_SM>(\n static_cast<float*>(float_workspace_buffer.data_ptr()),\n get_element_size(float_workspace_buffer) * float_workspace_buffer.size(0),\n static_cast<cutlass_t_in*>(A.data_ptr()),\n static_cast<cutlass_t_in*>(B.data_ptr()), static_cast<float*>(SFA.data_ptr()),\n static_cast<float*>(SFB.data_ptr()), static_cast<cutlass_t_out*>(C.data_ptr()),\n m, n, k, 1, stream);\n } else {\n status = flashinfer::gemm::CutlassGroupwiseScaledGEMMSM100<\n SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, SCALE_MAJOR_K,\n MMA_SM>(\n static_cast<float*>(float_workspace_buffer.data_ptr()),\n get_element_size(float_workspace_buffer) * float_workspace_buffer.size(0),\n static_cast<cutlass_t_in*>(A.data_ptr()),\n static_cast<cutlass_t_in*>(B.data_ptr()), static_cast<float*>(SFA.data_ptr()),\n static_cast<float*>(SFB.data_ptr()), static_cast<cutlass_t_out*>(C.data_ptr()),\n m, n, k, 1, stream);\n }\n TVM_FFI_ICHECK_EQ(status, cudaSuccess)\n << \"Failed to run cutlass gemm groupwise scaled sm100\"\n << cudaGetErrorString(status);\n return true;\n });\n });\n });\n });\n}\n"},"diff":{"kind":"string","value":"--- csrc/gemm_groupwise_sm100.cu\n+++ csrc/gemm_groupwise_sm100.cu\n@@ -80,8 +80,17 @@\n int MmaSM, typename DTypeIn, typename DTypeOut>\n cudaError_t CutlassGroupwiseScaledGEMMSM100(void* float_buffer, size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr, float* SFA_ptr,\n- float* SFB_ptr, DTypeOut* C_ptr, int m, int n, int k,\n+ float* SFB_ptr, DTypeOut* D_ptr, int m, int n, int k,\n int l, cudaStream_t stream);\n+\n+template <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n+ int MmaSM, typename DTypeIn, typename DTypeOut>\n+cudaError_t CutlassGroupwiseScaledGEMMSM100LowLatency(void* float_buffer,\n+ size_t float_buffer_size_in_bytes,\n+ DTypeIn* A_ptr, DTypeIn* B_ptr,\n+ float* SFA_ptr, float* SFB_ptr,\n+ DTypeOut* D_ptr, int m, int n, int k, int l,\n+ cudaStream_t stream);\n \n } // namespace gemm\n } // namespace flashinfer\n@@ -101,15 +110,34 @@\n SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, [&] {\n using cutlass_t_in = cutlass_dtype_t<c_type_in>;\n using cutlass_t_out = cutlass_dtype_t<c_type_out>;\n- auto status = flashinfer::gemm::CutlassGroupwiseScaledGEMMSM100<\n- SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, SCALE_MAJOR_K,\n- MMA_SM>(static_cast<float*>(float_workspace_buffer.data_ptr()),\n- get_element_size(float_workspace_buffer) * float_workspace_buffer.size(0),\n- static_cast<cutlass_t_in*>(A.data_ptr()),\n- static_cast<cutlass_t_in*>(B.data_ptr()),\n- static_cast<float*>(SFA.data_ptr()), static_cast<float*>(SFB.data_ptr()),\n- static_cast<cutlass_t_out*>(C.data_ptr()), A.size(0), B.size(0),\n- A.size(1), 1, stream);\n+ const int m = static_cast<int>(A.size(0));\n+ const int n = static_cast<int>(B.size(0));\n+ const int k = static_cast<int>(A.size(1));\n+\n+ cudaError_t status;\n+ // Small-batch-size kernel is not compatible with (scale_granularity_m=128).\n+ constexpr bool can_use_small_batch = (SCALE_GRANULARITY_M == 1);\n+ if (can_use_small_batch && m <= 32) {\n+ status = flashinfer::gemm::CutlassGroupwiseScaledGEMMSM100LowLatency<\n+ SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, SCALE_MAJOR_K,\n+ MMA_SM>(\n+ static_cast<float*>(float_workspace_buffer.data_ptr()),\n+ get_element_size(float_workspace_buffer) * float_workspace_buffer.size(0),\n+ static_cast<cutlass_t_in*>(A.data_ptr()),\n+ static_cast<cutlass_t_in*>(B.data_ptr()), static_cast<float*>(SFA.data_ptr()),\n+ static_cast<float*>(SFB.data_ptr()), static_cast<cutlass_t_out*>(C.data_ptr()),\n+ m, n, k, 1, stream);\n+ } else {\n+ status = flashinfer::gemm::CutlassGroupwiseScaledGEMMSM100<\n+ SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, SCALE_MAJOR_K,\n+ MMA_SM>(\n+ static_cast<float*>(float_workspace_buffer.data_ptr()),\n+ get_element_size(float_workspace_buffer) * float_workspace_buffer.size(0),\n+ static_cast<cutlass_t_in*>(A.data_ptr()),\n+ static_cast<cutlass_t_in*>(B.data_ptr()), static_cast<float*>(SFA.data_ptr()),\n+ static_cast<float*>(SFB.data_ptr()), static_cast<cutlass_t_out*>(C.data_ptr()),\n+ m, n, k, 1, stream);\n+ }\n TVM_FFI_ICHECK_EQ(status, cudaSuccess)\n << \"Failed to run cutlass gemm groupwise scaled sm100\"\n << cudaGetErrorString(status);"},"lines_added":{"kind":"number","value":38,"string":"38"},"lines_removed":{"kind":"number","value":10,"string":"10"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":["deepseek","qwen"],"string":"[\n \"deepseek\",\n \"qwen\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/gemm_groupwise_sm100.cu).\n\nGoal: [perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32\nTarget hardware: unspecified\nTarget models: deepseek, qwen\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <flashinfer/cutlass_utils.cuh>\n\n#include \"tvm_ffi_utils.h\"\n\nusing namespace flashinfer;\n\n#define DISPATCH_DLPACK_INPUT_OUTPUT_DTYPE(input_dtype, output_dtype, c_type_in, c_type_out, ...) \\\n [&]() -> bool { \\\n return DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP16(output_dtype, c_type_out, [&] { \\\n return DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP8(input_dtype, c_type_in, \\\n [&] { return __VA_ARGS__(); }); \\\n }); \\\n }()\n\n#define DISPATCH_SCALE_GRANULARITY(scale_granularity_m, scale_granularity_n, scale_granularity_k, \\\n SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, \\\n ...) \\\n [&]() -> bool { \\\n if (scale_granularity_m == 1 && scale_granularity_n == 128 && scale_granularity_k == 128) { \\\n constexpr int SCALE_GRANULARITY_M = 1; \\\n constexpr int SCALE_GRANULARITY_N = 128; \\\n constexpr int SCALE_GRANULARITY_K = 128; \\\n return __VA_ARGS__(); \\\n } else if (scale_granularity_m == 128 && scale_granularity_n == 128 && \\\n scale_granularity_k == 128) { \\\n constexpr int SCALE_GRANULARITY_M = 128; \\\n constexpr int SCALE_GRANULARITY_N = 128; \\\n constexpr int SCALE_GRANULARITY_K = 128; \\\n return __VA_ARGS__(); \\\n } \\\n TVM_FFI_ICHECK(false) << \"Unsupported scale granularity\"; \\\n return false; \\\n }()\n\n#define DISPATCH_MMA_SM(mma_sm, MMA_SM, ...) \\\n [&]() -> bool { \\\n if (mma_sm == 1) { \\\n constexpr int MMA_SM = 1; \\\n return __VA_ARGS__(); \\\n } else if (mma_sm == 2) { \\\n constexpr int MMA_SM = 2; \\\n return __VA_ARGS__(); \\\n } \\\n TVM_FFI_ICHECK(false) << \"Unsupported MMA SM\"; \\\n return false; \\\n }()\n\n#define DISPATCH_SCALE_MAJOR_K(scale_major_mode, SCALE_MAJOR_K, ...) \\\n [&]() -> bool { \\\n if (scale_major_mode == \"K\") { \\\n constexpr bool SCALE_MAJOR_K = true; \\\n return __VA_ARGS__(); \\\n } else if (scale_major_mode == \"MN\") { \\\n constexpr bool SCALE_MAJOR_K = false; \\\n return __VA_ARGS__(); \\\n } \\\n TVM_FFI_ICHECK(false) << \"Unsupported Scale Major Mode\"; \\\n return false; \\\n }()\n\nnamespace flashinfer {\nnamespace gemm {\n\ntemplate <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n int MmaSM, typename DTypeIn, typename DTypeOut>\ncudaError_t CutlassGroupwiseScaledGEMMSM100(void* float_buffer, size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr, float* SFA_ptr,\n float* SFB_ptr, DTypeOut* C_ptr, int m, int n, int k,\n int l, cudaStream_t stream);\n\n} // namespace gemm\n} // namespace flashinfer\n\nvoid CutlassGemmGroupwiseScaledSM100(TensorView float_workspace_buffer, TensorView A, TensorView B,\n TensorView SFA, TensorView SFB, TensorView C,\n int64_t scale_granularity_m, int64_t scale_granularity_n,\n int64_t scale_granularity_k, std::string scale_major_mode,\n int64_t mma_sm) {\n ffi::CUDADeviceGuard device_guard(float_workspace_buffer.device().device_id);\n const cudaStream_t stream = get_stream(C.device());\n DISPATCH_SCALE_MAJOR_K(scale_major_mode, SCALE_MAJOR_K, [&] {\n return DISPATCH_MMA_SM(mma_sm, MMA_SM, [&] {\n return DISPATCH_DLPACK_INPUT_OUTPUT_DTYPE(A.dtype(), C.dtype(), c_type_in, c_type_out, [&] {\n return DISPATCH_SCALE_GRANULARITY(\n scale_granularity_m, scale_granularity_n, scale_granularity_k, SCALE_GRANULARITY_M,\n SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, [&] {\n using cutlass_t_in = cutlass_dtype_t<c_type_in>;\n using cutlass_t_out = cutlass_dtype_t<c_type_out>;\n auto status = flashinfer::gemm::CutlassGroupwiseScaledGEMMSM100<\n SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, SCALE_MAJOR_K,\n MMA_SM>(static_cast<float*>(float_workspace_buffer.data_ptr()),\n get_element_size(float_workspace_buffer) * float_workspace_buffer.size(0),\n static_cast<cutlass_t_in*>(A.data_ptr()),\n static_cast<cutlass_t_in*>(B.data_ptr()),\n static_cast<float*>(SFA.data_ptr()), static_cast<float*>(SFB.data_ptr()),\n static_cast<cutlass_t_out*>(C.data_ptr()), A.size(0), B.size(0),\n A.size(1), 1, stream);\n TVM_FFI_ICHECK_EQ(status, cudaSuccess)\n << \"Failed to run cutlass gemm groupwise scaled sm100\"\n << cudaGetErrorString(status);\n return true;\n });\n });\n });\n });\n}\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nImproves gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32.\n\nThese are shapes typical for DeepSeek V3 and Qwen 3 235B - q, k, v, and o_proj:\n\n```\n+-------+-------+------+-----------+---------------+--------------+---------------+--------------+-------------+\n| batch | out | in | fp16 (us) | fp8 before(us)| ratio before | fp8 after (us)| ratio after | improvement |\n+-------+-------+------+-----------+---------------+--------------+---------------+--------------+-------------+\n| 1 | 1536 | 7168 | 14.26 | | | 20.48 | 0.66 | |\n| 8 | 1536 | 7168 | 14.37 | 24.58 | 0.58 | 20.48 | 0.70 | 1.20 |\n| 16 | 1536 | 7168 | 14.40 | 24.56 | 0.59 | 20.48 | 0.74 | 1.20 |\n| 32 | 1536 | 7168 | 18.40 | 24.56 | 0.75 | 20.48 | 0.85 | 1.20 |\n| 1 | 24576 | 1536 | 22.61 | | | 18.46 | 1.32 | |\n| 8 | 24576 | 1536 | 22.56 | 22.56 | 1.00 | 18.46 | 1.22 | 1.22 |\n| 16 | 24576 | 1536 | 22.59 | 22.56 | 1.00 | 18.46 | 1.23 | 1.22 |\n| 32 | 24576 | 1536 | 22.62 | 22.53 | 1.00 | 20.48 | 1.10 | 1.10 |\n| 1 | 32768 | 512 | 14.37 | | | 14.37 | 1.00 | |\n| 8 | 32768 | 512 | 14.34 | 16.35 | 0.88 | 14.37 | 1.00 | 1.14 |\n| 16 | 32768 | 512 | 14.37 | 14.40 | 1.00 | 14.34 | 1.00 | 1.00 |\n| 32 | 32768 | 512 | 14.34 | 14.37 | 1.00 | 14.37 | 1.00 | 1.00 |\n| 1 | 7168 | 7168 | 28.78 | | | 22.53 | 1.28 | |\n| 8 | 7168 | 7168 | 28.70 | 32.77 | 0.88 | 22.53 | 1.27 | 1.45 |\n| 16 | 7168 | 7168 | 28.67 | 30.75 | 0.93 | 22.53 | 1.27 | 1.37 |\n| 32 | 7168 | 7168 | 30.75 | 28.67 | 1.07 | 22.56 | 1.36 | 1.27 |\n| 1 | 12288 | 4096 | 31.74 | | | 20.51 | 1.55 | |\n| 8 | 12288 | 4096 | 29.73 | 26.62 | 1.12 | 20.51 | 1.45 | 1.30 |\n| 16 | 12288 | 4096 | 28.70 | 26.64 | 1.08 | 20.51 | 1.40 | 1.30 |\n| 32 | 12288 | 4096 | 28.67 | 22.54 | 1.27 | 24.58 | 1.17 | 0.92 |\n| 1 | 4096 | 4096 | 16.46 | | | 16.40 | 1.01 | |\n| 8 | 4096 | 4096 | 16.42 | 18.43 | 0.89 | 16.38 | 1.00 | 1.13 |\n| 16 | 4096 | 4096 | 16.42 | 18.46 | 0.89 | 16.38 | 1.00 | 1.13 |\n| 32 | 4096 | 4096 | 14.34 | 18.43 | 0.78 | 16.38 | 0.88 | 1.13 |\n| | | | | | | | | avg: 1.18 |\n+-------+-------+------+-----------+---------------+--------------+---------------+--------------+-------------+\n```\n\nBenchmarking script I'm using is modified version of user's script in: https://github.com/issues/recent?issue=flashinfer-ai%7Cflashinfer%7C2146\n\nCredit to @depaulmillz on the transpose trick: https://github.com/NVIDIA/cutlass/issues/2923#issuecomment-3707263529\n\n## 🔍 Related Issues\n\nFound this optimization while working on https://github.com/issues/recent?issue=flashinfer-ai%7Cflashinfer%7C2146 - note this user's issue is still outstanding - their shapes are different.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n * Added performance optimization for small batch matrix operations\n\n* **Tests**\n * Expanded test coverage for small batch configurations with various matrix dimensions\n\n* **Chores**\n * Updated benchmark suite to evaluate broader range of operation sizes\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=1536,in=7168\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 24.58, \"optimized\": 20.48, \"stated_speedup\": 1.2, \"speedup\": 1.2002}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=1536,in=7168\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 24.56, \"optimized\": 20.48, \"stated_speedup\": 1.2, \"speedup\": 1.1992}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=1536,in=7168\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 24.56, \"optimized\": 20.48, \"stated_speedup\": 1.2, \"speedup\": 1.1992}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=24576,in=1536\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 22.56, \"optimized\": 18.46, \"stated_speedup\": 1.22, \"speedup\": 1.2221}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=24576,in=1536\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 22.56, \"optimized\": 18.46, \"stated_speedup\": 1.22, \"speedup\": 1.2221}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=24576,in=1536\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 22.53, \"optimized\": 20.48, \"stated_speedup\": 1.1, \"speedup\": 1.1001}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=32768,in=512\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 16.35, \"optimized\": 14.37, \"stated_speedup\": 1.14, \"speedup\": 1.1378}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=7168,in=7168\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 32.77, \"optimized\": 22.53, \"stated_speedup\": 1.45, \"speedup\": 1.4545}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=7168,in=7168\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 30.75, \"optimized\": 22.53, \"stated_speedup\": 1.37, \"speedup\": 1.3648}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=7168,in=7168\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 28.67, \"optimized\": 22.56, \"stated_speedup\": 1.27, \"speedup\": 1.2708}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=12288,in=4096\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 26.62, \"optimized\": 20.51, \"stated_speedup\": 1.3, \"speedup\": 1.2979}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=12288,in=4096\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 26.64, \"optimized\": 20.51, \"stated_speedup\": 1.3, \"speedup\": 1.2989}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=12288,in=4096\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 22.54, \"optimized\": 24.58, \"stated_speedup\": 0.92, \"speedup\": 0.917}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=4096,in=4096\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 18.43, \"optimized\": 16.38, \"stated_speedup\": 1.13, \"speedup\": 1.1252}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=4096,in=4096\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 18.46, \"optimized\": 16.38, \"stated_speedup\": 1.13, \"speedup\": 1.127}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=4096,in=4096\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 18.43, \"optimized\": 16.38, \"stated_speedup\": 1.13, \"speedup\": 1.1252}]"},"kernel_speedup":{"kind":"number","value":1.1997,"string":"1.1997"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1190,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"2bf87713dade8c6094ca3ff5e246e1ff72e97644"},"date":{"kind":"string","value":"2026-01-13T22:44:35-08:00"},"pr_number":{"kind":"number","value":2327,"string":"2,327"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2327"},"title":{"kind":"string","value":"[perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32 (#2327)"},"message":{"kind":"string","value":"[perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32 (#2327)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nImproves gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch\nsizes <= 32.\n\nThese are shapes typical for DeepSeek V3 and Qwen 3 235B - q, k, v, and\no_proj:\n\n```\n+-------+-------+------+-----------+---------------+--------------+---------------+--------------+-------------+\n| batch | out | in | fp16 (us) | fp8 before(us)| ratio before | fp8 after (us)| ratio after | improvement |\n+-------+-------+------+-----------+---------------+--------------+---------------+--------------+-------------+\n| 1 | 1536 | 7168 | 14.26 | | | 20.48 | 0.66 | |\n| 8 | 1536 | 7168 | 14.37 | 24.58 | 0.58 | 20.48 | 0.70 | 1.20 |\n| 16 | 1536 | 7168 | 14.40 | 24.56 | 0.59 | 20.48 | 0.74 | 1.20 |\n| 32 | 1536 | 7168 | 18.40 | 24.56 | 0.75 | 20.48 | 0.85 | 1.20 |\n| 1 | 24576 | 1536 | 22.61 | | | 18.46 | 1.32 | |\n| 8 | 24576 | 1536 | 22.56 | 22.56 | 1.00 | 18.46 | 1.22 | 1.22 |\n| 16 | 24576 | 1536 | 22.59 | 22.56 | 1.00 | 18.46 | 1.23 | 1.22 |\n| 32 | 24576 | 1536 | 22.62 | 22.53 | 1.00 | 20.48 | 1.10 | 1.10 |\n| 1 | 32768 | 512 | 14.37 | | | 14.37 | 1.00 | |\n| 8 | 32768 | 512 | 14.34 | 16.35 | 0.88 | 14.37 | 1.00 | 1.14 |\n| 16 | 32768 | 512 | 14.37 | 14.40 | 1.00 | 14.34 | 1.00 | 1.00 |\n| 32 | 32768 | 512 | 14.34 | 14.37 | 1.00 | 14.37 | 1.00 | 1.00 |\n| 1 | 7168 | 7168 | 28.78 | | | 22.53 | 1.28 | |\n| 8 | 7168 | 7168 | 28.70 | 32.77 | 0.88 | 22.53 | 1.27 | 1.45 |\n| 16 | 7168 | 7168 | 28.67 | 30.75 | 0.93 | 22.53 | 1.27 | 1.37 |\n| 32 | 7168 | 7168 | 30.75 | 28.67 | 1.07 | 22.56 | 1.36 | 1.27 |\n| 1 | 12288 | 4096 | 31.74 | | | 20.51 | 1.55 | |\n| 8 | 12288 | 4096 | 29.73 | 26.62 | 1.12 | 20.51 | 1.45 | 1.30 |\n| 16 | 12288 | 4096 | 28.70 | 26.64 | 1.08 | 20.51 | 1.40 | 1.30 |\n| 32 | 12288 | 4096 | 28.67 | 22.54 | 1.27 | 24.58 | 1.17 | 0.92 |\n| 1 | 4096 | 4096 | 16.46 | | | 16.40 | 1.01 | |\n| 8 | 4096 | 4096 | 16.42 | 18.43 | 0.89 | 16.38 | 1.00 | 1.13 |\n| 16 | 4096 | 4096 | 16.42 | 18.46 | 0.89 | 16.38 | 1.00 | 1.13 |\n| 32 | 4096 | 4096 | 14.34 | 18.43 | 0.78 | 16.38 | 0.88 | 1.13 |\n| | | | | | | | | avg: 1.18 |\n+-------+-------+------+-----------+---------------+--------------+---------------+--------------+-------------+\n```\n\nBenchmarking script I'm using is modified version of user's script in:\nhttps://github.com/issues/recent?issue=flashinfer-ai%7Cflashinfer%7C2146\n\nCredit to @depaulmillz on the transpose trick:\nhttps://github.com/NVIDIA/cutlass/issues/2923#issuecomment-3707263529\n\n## 🔍 Related Issues\n\nFound this optimization while working on\nhttps://github.com/issues/recent?issue=flashinfer-ai%7Cflashinfer%7C2146\n- note this user's issue is still outstanding - their shapes are\ndifferent.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n * Added performance optimization for small batch matrix operations\n\n* **Tests**\n* Expanded test coverage for small batch configurations with various\nmatrix dimensions\n\n* **Chores**\n * Updated benchmark suite to evaluate broader range of operation sizes\n\n<sub>✏️ Tip: You can customize this high-level summary in your review\nsettings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->"},"path":{"kind":"string","value":"include/flashinfer/gemm/gemm_groupwise_sm100.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_GEMM_GROUPWISE_SM100_CUH_\n#define FLASHINFER_GEMM_GROUPWISE_SM100_CUH_\n\n#include <type_traits>\n\n#include \"../allocator.h\"\n#include \"../cutlass_utils.cuh\"\n#include \"../utils.cuh\"\n\nnamespace flashinfer {\n\nnamespace gemm {\n\nusing namespace cute;\n\ntemplate <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n int MmaSM, typename DTypeIn, typename DTypeOut>\ncudaError_t CutlassGroupwiseScaledGEMMSM100(void* float_buffer, size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr, float* SFA_ptr,\n float* SFB_ptr, DTypeOut* C_ptr, int m, int n, int k,\n int l, cudaStream_t stream) {\n using ElementA = DTypeIn; // Element type for A matrix operand\n using LayoutA = cutlass::layout::RowMajor; // Layout type for A matrix operand\n constexpr int AlignmentA =\n 128 / cutlass::sizeof_bits<ElementA>::value; // Memory access granularity/alignment of A\n // matrix in units of elements (up to 16 bytes)\n\n // B matrix configuration\n using ElementB = DTypeIn; // Element type for B matrix operand\n using LayoutB = cutlass::layout::ColumnMajor; // Layout type for B matrix operand\n constexpr int AlignmentB =\n 128 / cutlass::sizeof_bits<ElementB>::value; // Memory access granularity/alignment of A\n // matrix in units of elements (up to 16 bytes)\n\n // C/D matrix configuration\n using ElementC = DTypeOut; // Element type for C and D matrix operands\n using LayoutC = cutlass::layout::RowMajor; // Layout type for C and D matrix operands\n constexpr int AlignmentC =\n 128 / cutlass::sizeof_bits<ElementC>::value; // Memory access granularity/alignment of A\n // matrix in units of elements (up to 16 bytes)\n\n using ElementD = ElementC;\n using LayoutD = LayoutC;\n constexpr int AlignmentD = AlignmentC;\n\n // MMA type\n using ElementAccumulator = float; // Element Accumulator will also be our scale factor type\n using ElementCompute = float;\n\n using MmaTileShape_MNK = Shape<cute::Int<MmaSM * 128>, _128, _128>;\n using ClusterShape_MNK = Shape<cute::Int<MmaSM>, _1, _1>;\n\n // NOTE(Zihao):: UMMA::Major::MN, UMMA::Major::MN is the fastest configuration.\n\n using ScaleConfig = std::conditional_t<\n ScaleMajorK,\n cutlass::detail::Sm100BlockwiseScaleConfig<ScaleGranularityM, ScaleGranularityN,\n ScaleGranularityK, UMMA::Major::K, UMMA::Major::K>,\n cutlass::detail::Sm100BlockwiseScaleConfig<ScaleGranularityM, ScaleGranularityN,\n ScaleGranularityK, UMMA::Major::MN,\n UMMA::Major::MN>>;\n\n using LayoutSFA =\n decltype(ScaleConfig::deduce_layoutSFA()); // Layout type for SFA matrix operand\n using LayoutSFB =\n decltype(ScaleConfig::deduce_layoutSFB()); // Layout type for SFB matrix operand\n using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder<\n cutlass::arch::Sm100, cutlass::arch::OpClassTensorOp, MmaTileShape_MNK, ClusterShape_MNK,\n cutlass::epilogue::collective::EpilogueTileAuto, ElementAccumulator, ElementCompute, ElementC,\n LayoutC, AlignmentC, ElementD, LayoutC, AlignmentD,\n cutlass::epilogue::collective::EpilogueScheduleAuto>::CollectiveOp;\n\n using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder<\n cutlass::arch::Sm100, cutlass::arch::OpClassTensorOp, ElementA,\n cute::tuple<LayoutA, LayoutSFA>, AlignmentA, ElementB, cute::tuple<LayoutB, LayoutSFB>,\n AlignmentB, ElementAccumulator, MmaTileShape_MNK, ClusterShape_MNK,\n cutlass::gemm::collective::StageCountAutoCarveout<static_cast<int>(\n sizeof(typename CollectiveEpilogue::SharedStorage))>,\n cutlass::gemm::KernelScheduleSm100Blockwise>::CollectiveOp;\n\n using GemmKernel = cutlass::gemm::kernel::GemmUniversal<\n Shape<int, int, int, int>, CollectiveMainloop, CollectiveEpilogue,\n void>; // Default to ClusterLaunchControl (CLC) based tile scheduler\n\n using Gemm = cutlass::gemm::device::GemmUniversalAdapter<GemmKernel>;\n\n using StrideA = typename Gemm::GemmKernel::StrideA;\n using StrideB = typename Gemm::GemmKernel::StrideB;\n using StrideC = typename Gemm::GemmKernel::StrideC;\n using StrideD = typename Gemm::GemmKernel::StrideD;\n\n auto stride_A = cutlass::make_cute_packed_stride(StrideA{}, cute::make_shape(m, k, l));\n auto stride_B = cutlass::make_cute_packed_stride(StrideB{}, cute::make_shape(n, k, l));\n auto stride_C = cutlass::make_cute_packed_stride(StrideC{}, cute::make_shape(m, n, l));\n auto stride_D = cutlass::make_cute_packed_stride(StrideD{}, cute::make_shape(m, n, l));\n\n auto layout_SFA = ScaleConfig::tile_atom_to_shape_SFA(make_shape(m, n, k, l));\n auto layout_SFB = ScaleConfig::tile_atom_to_shape_SFB(make_shape(m, n, k, l));\n\n typename Gemm::Arguments arguments{cutlass::gemm::GemmUniversalMode::kGemm,\n {m, n, k, l},\n {\n A_ptr,\n stride_A,\n B_ptr,\n stride_B,\n SFA_ptr,\n layout_SFA,\n SFB_ptr,\n layout_SFB,\n },\n {\n {}, // epilogue.thread\n C_ptr,\n stride_C,\n C_ptr,\n stride_C,\n }};\n auto& fusion_args = arguments.epilogue.thread;\n fusion_args.alpha = 1.0f;\n fusion_args.beta = 0.0f;\n\n Gemm gemm;\n\n size_t workspace_size = Gemm::get_workspace_size(arguments);\n AlignedAllocator float_allocator(float_buffer, float_buffer_size_in_bytes);\n auto workspace_ptr = float_allocator.aligned_alloc<void>(workspace_size, 16,\n \"sm100_groupwise_gemm_float_workspace\");\n\n CUTLASS_CHECK(gemm.can_implement(arguments));\n CUTLASS_CHECK(gemm.initialize(arguments, workspace_ptr));\n CUTLASS_CHECK(gemm.run(stream));\n return cudaSuccess;\n}\n\n} // namespace gemm\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_GEMM_GROUPWISE_SM100_CUH_\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_GEMM_GROUPWISE_SM100_CUH_\n#define FLASHINFER_GEMM_GROUPWISE_SM100_CUH_\n\n#include <type_traits>\n#include <utility>\n\n#include \"../allocator.h\"\n#include \"../cutlass_utils.cuh\"\n#include \"../utils.cuh\"\n\nnamespace flashinfer {\n\nnamespace gemm {\n\nusing namespace cute;\n\ntemplate <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n int MmaSM, typename DTypeIn, typename DTypeOut>\ncudaError_t CutlassGroupwiseScaledGEMMSM100(void* float_buffer, size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr, float* SFA_ptr,\n float* SFB_ptr, DTypeOut* D_ptr, int m, int n, int k,\n int l, cudaStream_t stream) {\n using ElementA = DTypeIn; // Element type for A matrix operand\n using LayoutA = cutlass::layout::RowMajor; // Layout type for A matrix operand\n constexpr int AlignmentA =\n 128 / cutlass::sizeof_bits<ElementA>::value; // Memory access granularity/alignment of A\n // matrix in units of elements (up to 16 bytes)\n\n // B matrix configuration\n using ElementB = DTypeIn; // Element type for B matrix operand\n using LayoutB = cutlass::layout::ColumnMajor; // Layout type for B matrix operand\n constexpr int AlignmentB =\n 128 / cutlass::sizeof_bits<ElementB>::value; // Memory access granularity/alignment of A\n // matrix in units of elements (up to 16 bytes)\n\n // C/D matrix configuration\n using ElementC = DTypeOut; // Element type for C and D matrix operands\n using LayoutC = cutlass::layout::RowMajor; // Layout type for C and D matrix operands\n constexpr int AlignmentC =\n 128 / cutlass::sizeof_bits<ElementC>::value; // Memory access granularity/alignment of A\n // matrix in units of elements (up to 16 bytes)\n\n using ElementD = ElementC;\n using LayoutD = LayoutC;\n constexpr int AlignmentD = AlignmentC;\n\n // MMA type\n using ElementAccumulator = float; // Element Accumulator will also be our scale factor type\n using ElementCompute = float;\n\n using MmaTileShape_MNK = Shape<cute::Int<MmaSM * 128>, _128, _128>;\n using ClusterShape_MNK = Shape<cute::Int<MmaSM>, _1, _1>;\n\n // NOTE(Zihao):: UMMA::Major::MN, UMMA::Major::MN is the fastest configuration.\n\n using ScaleConfig = std::conditional_t<\n ScaleMajorK,\n cutlass::detail::Sm100BlockwiseScaleConfig<ScaleGranularityM, ScaleGranularityN,\n ScaleGranularityK, UMMA::Major::K, UMMA::Major::K>,\n cutlass::detail::Sm100BlockwiseScaleConfig<ScaleGranularityM, ScaleGranularityN,\n ScaleGranularityK, UMMA::Major::MN,\n UMMA::Major::MN>>;\n\n using LayoutSFA =\n decltype(ScaleConfig::deduce_layoutSFA()); // Layout type for SFA matrix operand\n using LayoutSFB =\n decltype(ScaleConfig::deduce_layoutSFB()); // Layout type for SFB matrix operand\n using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder<\n cutlass::arch::Sm100, cutlass::arch::OpClassTensorOp, MmaTileShape_MNK, ClusterShape_MNK,\n cutlass::epilogue::collective::EpilogueTileAuto, ElementAccumulator, ElementCompute, ElementC,\n LayoutC, AlignmentC, ElementD, LayoutC, AlignmentD,\n cutlass::epilogue::collective::EpilogueScheduleAuto>::CollectiveOp;\n\n using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder<\n cutlass::arch::Sm100, cutlass::arch::OpClassTensorOp, ElementA,\n cute::tuple<LayoutA, LayoutSFA>, AlignmentA, ElementB, cute::tuple<LayoutB, LayoutSFB>,\n AlignmentB, ElementAccumulator, MmaTileShape_MNK, ClusterShape_MNK,\n cutlass::gemm::collective::StageCountAutoCarveout<static_cast<int>(\n sizeof(typename CollectiveEpilogue::SharedStorage))>,\n cutlass::gemm::KernelScheduleSm100Blockwise>::CollectiveOp;\n\n using GemmKernel = cutlass::gemm::kernel::GemmUniversal<\n Shape<int, int, int, int>, CollectiveMainloop, CollectiveEpilogue,\n void>; // Default to ClusterLaunchControl (CLC) based tile scheduler\n\n using Gemm = cutlass::gemm::device::GemmUniversalAdapter<GemmKernel>;\n\n using StrideA = typename Gemm::GemmKernel::StrideA;\n using StrideB = typename Gemm::GemmKernel::StrideB;\n using StrideC = typename Gemm::GemmKernel::StrideC;\n using StrideD = typename Gemm::GemmKernel::StrideD;\n\n auto stride_A = cutlass::make_cute_packed_stride(StrideA{}, cute::make_shape(m, k, l));\n auto stride_B = cutlass::make_cute_packed_stride(StrideB{}, cute::make_shape(n, k, l));\n auto stride_C = cutlass::make_cute_packed_stride(StrideC{}, cute::make_shape(m, n, l));\n auto stride_D = cutlass::make_cute_packed_stride(StrideD{}, cute::make_shape(m, n, l));\n\n auto layout_SFA = ScaleConfig::tile_atom_to_shape_SFA(make_shape(m, n, k, l));\n auto layout_SFB = ScaleConfig::tile_atom_to_shape_SFB(make_shape(m, n, k, l));\n\n typename Gemm::Arguments arguments{cutlass::gemm::GemmUniversalMode::kGemm,\n {m, n, k, l},\n {\n A_ptr,\n stride_A,\n B_ptr,\n stride_B,\n SFA_ptr,\n layout_SFA,\n SFB_ptr,\n layout_SFB,\n },\n {\n {}, // epilogue.thread\n D_ptr,\n stride_C,\n D_ptr,\n stride_C,\n }};\n auto& fusion_args = arguments.epilogue.thread;\n fusion_args.alpha = 1.0f;\n fusion_args.beta = 0.0f;\n\n Gemm gemm;\n\n size_t workspace_size = Gemm::get_workspace_size(arguments);\n AlignedAllocator float_allocator(float_buffer, float_buffer_size_in_bytes);\n auto workspace_ptr = float_allocator.aligned_alloc<void>(workspace_size, 16,\n \"sm100_groupwise_gemm_float_workspace\");\n\n CUTLASS_CHECK(gemm.can_implement(arguments));\n CUTLASS_CHECK(gemm.initialize(arguments, workspace_ptr));\n CUTLASS_CHECK(gemm.run(stream));\n return cudaSuccess;\n}\n\ntemplate <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n int MmaSM, typename DTypeIn, typename DTypeOut>\ncudaError_t CutlassGroupwiseScaledGEMMSM100LowLatency(void* float_buffer,\n size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr,\n float* SFA_ptr, float* SFB_ptr,\n DTypeOut* D_ptr, int m, int n, int k, int l,\n cudaStream_t stream) {\n /*\n For small batch sizes (M) like 8, 16, 32 - typically we can only have at minimum M tile size of\n 64 - because of tcgen05.mma shapes. This causes wasted work in the M dimension and less CTAs\n being able to do work. So one trick we can do is instead of calculating D = A @ B, we can\n calculate D.T = B.T @ A.T This allows us to use a smaller N tile size and more CTAs being able\n to do work. We can transpose by doing swapping row major and column major layouts. A: (m, k) row\n major => (k, m) column major B: (k, n) column major => (n, k) row major D: (m, n) row major\n => (n, m) column major\n\n So instead of a row-column-row gemm we perform a row-column-column gemm.\n */\n\n // Compute the transpose GEMM:\n // D^T = B^T @ A^T\n // so we swap (m, n) and swap (A, B) (+their scale tensors). The output is written as\n // column-major (n, m), which matches the original row-major (m, n) memory layout.\n std::swap(m, n);\n std::swap(A_ptr, B_ptr);\n std::swap(SFA_ptr, SFB_ptr);\n // Do the swap here as well\n using ScaleConfig = std::conditional_t<\n ScaleMajorK,\n cutlass::detail::Sm100BlockwiseScaleConfig<ScaleGranularityN, ScaleGranularityM,\n ScaleGranularityK, UMMA::Major::K, UMMA::Major::K>,\n cutlass::detail::Sm100BlockwiseScaleConfig<ScaleGranularityN, ScaleGranularityM,\n ScaleGranularityK, UMMA::Major::MN,\n UMMA::Major::MN>>;\n\n using ElementA = DTypeIn;\n using LayoutA = cutlass::layout::RowMajor;\n constexpr int AlignmentA = 128 / cutlass::sizeof_bits<ElementA>::value;\n\n using ElementB = DTypeIn;\n using LayoutB = cutlass::layout::ColumnMajor;\n constexpr int AlignmentB = 128 / cutlass::sizeof_bits<ElementB>::value;\n\n using ElementC = DTypeOut;\n using LayoutC = cutlass::layout::ColumnMajor;\n constexpr int AlignmentC = 128 / cutlass::sizeof_bits<ElementC>::value;\n\n using ElementD = ElementC;\n using LayoutD = LayoutC;\n constexpr int AlignmentD = AlignmentC;\n\n // MMA type\n using ElementAccumulator = float; // Element Accumulator will also be our scale factor type\n using ElementCompute = float;\n\n using MmaTileShape_MNK = Shape<cute::Int<128>, _16, _128>;\n using ClusterShape_MNK = Shape<int, int, _1>;\n\n using LayoutSFA = decltype(ScaleConfig::deduce_layoutSFA());\n using LayoutSFB = decltype(ScaleConfig::deduce_layoutSFB());\n\n using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder<\n cutlass::arch::Sm100, cutlass::arch::OpClassTensorOp, MmaTileShape_MNK, ClusterShape_MNK,\n cutlass::epilogue::collective::EpilogueTileAuto, float, float, void, LayoutC, AlignmentC,\n ElementD, LayoutD, AlignmentD, cutlass::epilogue::TmaWarpSpecialized1Sm,\n cutlass::epilogue::fusion::LinearCombination<ElementD, float, void, float>>::CollectiveOp;\n\n using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder<\n /*ArchTag=*/cutlass::arch::Sm100, /*OpClass=*/cutlass::arch::OpClassTensorOp, ElementA,\n /*GemmLayoutA=*/cute::tuple<LayoutA, LayoutSFA>, AlignmentA, ElementB,\n /*GemmLayoutB=*/cute::tuple<LayoutB, LayoutSFB>, AlignmentB, ElementAccumulator,\n /*TileShapeMNK=*/MmaTileShape_MNK, ClusterShape_MNK,\n /*StageCountType=*/\n cutlass::gemm::collective::StageCountAutoCarveout<static_cast<int>(\n sizeof(typename CollectiveEpilogue::SharedStorage))>,\n /*KernelScheduleType=*/cutlass::gemm::KernelTmaWarpSpecializedBlockwise1SmSm100>::\n CollectiveOp;\n\n using GemmKernel = cutlass::gemm::kernel::GemmUniversal<\n /*ProblemShapeOrThreadblockMma_=*/Shape<int, int, int, int>, CollectiveMainloop,\n CollectiveEpilogue, void>;\n\n using Gemm = cutlass::gemm::device::GemmUniversalAdapter<GemmKernel>;\n\n using StrideA = typename Gemm::GemmKernel::StrideA;\n using StrideB = typename Gemm::GemmKernel::StrideB;\n using StrideC = typename Gemm::GemmKernel::StrideC;\n using StrideD = typename Gemm::GemmKernel::StrideD;\n\n auto stride_A = cutlass::make_cute_packed_stride(StrideA{}, cute::make_shape(m, k, l));\n auto stride_B = cutlass::make_cute_packed_stride(StrideB{}, cute::make_shape(n, k, l));\n auto stride_C = cutlass::make_cute_packed_stride(StrideC{}, cute::make_shape(m, n, l));\n auto stride_D = cutlass::make_cute_packed_stride(StrideD{}, cute::make_shape(m, n, l));\n\n auto layout_SFA = ScaleConfig::tile_atom_to_shape_SFA(make_shape(m, n, k, l));\n auto layout_SFB = ScaleConfig::tile_atom_to_shape_SFB(make_shape(m, n, k, l));\n\n typename Gemm::Arguments arguments{\n cutlass::gemm::GemmUniversalMode::kGemm,\n {m, n, k, l},\n {\n A_ptr,\n stride_A,\n B_ptr,\n stride_B,\n SFA_ptr,\n layout_SFA,\n SFB_ptr,\n layout_SFB,\n },\n {\n {}, // epilogue.thread\n nullptr,\n stride_C,\n D_ptr,\n stride_D,\n },\n // KernelHardwareInfo\n []() {\n // For some reason can_implement fails if this is not defined\n auto hw_info = cutlass::KernelHardwareInfo::make_kernel_hardware_info<GemmKernel>();\n hw_info.cluster_shape = {1, 1, 1};\n hw_info.cluster_shape_fallback = {1, 1, 1};\n return hw_info;\n }(),\n };\n auto& fusion_args = arguments.epilogue.thread;\n fusion_args.alpha = 1.0f;\n fusion_args.beta = 0.0f;\n\n Gemm gemm;\n\n size_t workspace_size = Gemm::get_workspace_size(arguments);\n AlignedAllocator float_allocator(float_buffer, float_buffer_size_in_bytes);\n auto workspace_ptr = float_allocator.aligned_alloc<void>(\n workspace_size, 16, \"sm100_groupwise_gemm_small_batch_size_float_workspace\");\n\n CUTLASS_CHECK(gemm.can_implement(arguments));\n CUTLASS_CHECK(gemm.initialize(arguments, workspace_ptr));\n CUTLASS_CHECK(gemm.run(stream));\n return cudaSuccess;\n}\n\n} // namespace gemm\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_GEMM_GROUPWISE_SM100_CUH_\n"},"diff":{"kind":"string","value":"--- include/flashinfer/gemm/gemm_groupwise_sm100.cuh\n+++ include/flashinfer/gemm/gemm_groupwise_sm100.cuh\n@@ -17,6 +17,7 @@\n #define FLASHINFER_GEMM_GROUPWISE_SM100_CUH_\n \n #include <type_traits>\n+#include <utility>\n \n #include \"../allocator.h\"\n #include \"../cutlass_utils.cuh\"\n@@ -32,7 +33,7 @@\n int MmaSM, typename DTypeIn, typename DTypeOut>\n cudaError_t CutlassGroupwiseScaledGEMMSM100(void* float_buffer, size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr, float* SFA_ptr,\n- float* SFB_ptr, DTypeOut* C_ptr, int m, int n, int k,\n+ float* SFB_ptr, DTypeOut* D_ptr, int m, int n, int k,\n int l, cudaStream_t stream) {\n using ElementA = DTypeIn; // Element type for A matrix operand\n using LayoutA = cutlass::layout::RowMajor; // Layout type for A matrix operand\n@@ -126,9 +127,9 @@\n },\n {\n {}, // epilogue.thread\n- C_ptr,\n+ D_ptr,\n stride_C,\n- C_ptr,\n+ D_ptr,\n stride_C,\n }};\n auto& fusion_args = arguments.epilogue.thread;\n@@ -148,6 +149,150 @@\n return cudaSuccess;\n }\n \n+template <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n+ int MmaSM, typename DTypeIn, typename DTypeOut>\n+cudaError_t CutlassGroupwiseScaledGEMMSM100LowLatency(void* float_buffer,\n+ size_t float_buffer_size_in_bytes,\n+ DTypeIn* A_ptr, DTypeIn* B_ptr,\n+ float* SFA_ptr, float* SFB_ptr,\n+ DTypeOut* D_ptr, int m, int n, int k, int l,\n+ cudaStream_t stream) {\n+ /*\n+ For small batch sizes (M) like 8, 16, 32 - typically we can only have at minimum M tile size of\n+ 64 - because of tcgen05.mma shapes. This causes wasted work in the M dimension and less CTAs\n+ being able to do work. So one trick we can do is instead of calculating D = A @ B, we can\n+ calculate D.T = B.T @ A.T This allows us to use a smaller N tile size and more CTAs being able\n+ to do work. We can transpose by doing swapping row major and column major layouts. A: (m, k) row\n+ major => (k, m) column major B: (k, n) column major => (n, k) row major D: (m, n) row major\n+ => (n, m) column major\n+\n+ So instead of a row-column-row gemm we perform a row-column-column gemm.\n+ */\n+\n+ // Compute the transpose GEMM:\n+ // D^T = B^T @ A^T\n+ // so we swap (m, n) and swap (A, B) (+their scale tensors). The output is written as\n+ // column-major (n, m), which matches the original row-major (m, n) memory layout.\n+ std::swap(m, n);\n+ std::swap(A_ptr, B_ptr);\n+ std::swap(SFA_ptr, SFB_ptr);\n+ // Do the swap here as well\n+ using ScaleConfig = std::conditional_t<\n+ ScaleMajorK,\n+ cutlass::detail::Sm100BlockwiseScaleConfig<ScaleGranularityN, ScaleGranularityM,\n+ ScaleGranularityK, UMMA::Major::K, UMMA::Major::K>,\n+ cutlass::detail::Sm100BlockwiseScaleConfig<ScaleGranularityN, ScaleGranularityM,\n+ ScaleGranularityK, UMMA::Major::MN,\n+ UMMA::Major::MN>>;\n+\n+ using ElementA = DTypeIn;\n+ using LayoutA = cutlass::layout::RowMajor;\n+ constexpr int AlignmentA = 128 / cutlass::sizeof_bits<ElementA>::value;\n+\n+ using ElementB = DTypeIn;\n+ using LayoutB = cutlass::layout::ColumnMajor;\n+ constexpr int AlignmentB = 128 / cutlass::sizeof_bits<ElementB>::value;\n+\n+ using ElementC = DTypeOut;\n+ using LayoutC = cutlass::layout::ColumnMajor;\n+ constexpr int AlignmentC = 128 / cutlass::sizeof_bits<ElementC>::value;\n+\n+ using ElementD = ElementC;\n+ using LayoutD = LayoutC;\n+ constexpr int AlignmentD = AlignmentC;\n+\n+ // MMA type\n+ using ElementAccumulator = float; // Element Accumulator will also be our scale factor type\n+ using ElementCompute = float;\n+\n+ using MmaTileShape_MNK = Shape<cute::Int<128>, _16, _128>;\n+ using ClusterShape_MNK = Shape<int, int, _1>;\n+\n+ using LayoutSFA = decltype(ScaleConfig::deduce_layoutSFA());\n+ using LayoutSFB = decltype(ScaleConfig::deduce_layoutSFB());\n+\n+ using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder<\n+ cutlass::arch::Sm100, cutlass::arch::OpClassTensorOp, MmaTileShape_MNK, ClusterShape_MNK,\n+ cutlass::epilogue::collective::EpilogueTileAuto, float, float, void, LayoutC, AlignmentC,\n+ ElementD, LayoutD, AlignmentD, cutlass::epilogue::TmaWarpSpecialized1Sm,\n+ cutlass::epilogue::fusion::LinearCombination<ElementD, float, void, float>>::CollectiveOp;\n+\n+ using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder<\n+ /*ArchTag=*/cutlass::arch::Sm100, /*OpClass=*/cutlass::arch::OpClassTensorOp, ElementA,\n+ /*GemmLayoutA=*/cute::tuple<LayoutA, LayoutSFA>, AlignmentA, ElementB,\n+ /*GemmLayoutB=*/cute::tuple<LayoutB, LayoutSFB>, AlignmentB, ElementAccumulator,\n+ /*TileShapeMNK=*/MmaTileShape_MNK, ClusterShape_MNK,\n+ /*StageCountType=*/\n+ cutlass::gemm::collective::StageCountAutoCarveout<static_cast<int>(\n+ sizeof(typename CollectiveEpilogue::SharedStorage))>,\n+ /*KernelScheduleType=*/cutlass::gemm::KernelTmaWarpSpecializedBlockwise1SmSm100>::\n+ CollectiveOp;\n+\n+ using GemmKernel = cutlass::gemm::kernel::GemmUniversal<\n+ /*ProblemShapeOrThreadblockMma_=*/Shape<int, int, int, int>, CollectiveMainloop,\n+ CollectiveEpilogue, void>;\n+\n+ using Gemm = cutlass::gemm::device::GemmUniversalAdapter<GemmKernel>;\n+\n+ using StrideA = typename Gemm::GemmKernel::StrideA;\n+ using StrideB = typename Gemm::GemmKernel::StrideB;\n+ using StrideC = typename Gemm::GemmKernel::StrideC;\n+ using StrideD = typename Gemm::GemmKernel::StrideD;\n+\n+ auto stride_A = cutlass::make_cute_packed_stride(StrideA{}, cute::make_shape(m, k, l));\n+ auto stride_B = cutlass::make_cute_packed_stride(StrideB{}, cute::make_shape(n, k, l));\n+ auto stride_C = cutlass::make_cute_packed_stride(StrideC{}, cute::make_shape(m, n, l));\n+ auto stride_D = cutlass::make_cute_packed_stride(StrideD{}, cute::make_shape(m, n, l));\n+\n+ auto layout_SFA = ScaleConfig::tile_atom_to_shape_SFA(make_shape(m, n, k, l));\n+ auto layout_SFB = ScaleConfig::tile_atom_to_shape_SFB(make_shape(m, n, k, l));\n+\n+ typename Gemm::Arguments arguments{\n+ cutlass::gemm::GemmUniversalMode::kGemm,\n+ {m, n, k, l},\n+ {\n+ A_ptr,\n+ stride_A,\n+ B_ptr,\n+ stride_B,\n+ SFA_ptr,\n+ layout_SFA,\n+ SFB_ptr,\n+ layout_SFB,\n+ },\n+ {\n+ {}, // epilogue.thread\n+ nullptr,\n+ stride_C,\n+ D_ptr,\n+ stride_D,\n+ },\n+ // KernelHardwareInfo\n+ []() {\n+ // For some reason can_implement fails if this is not defined\n+ auto hw_info = cutlass::KernelHardwareInfo::make_kernel_hardware_info<GemmKernel>();\n+ hw_info.cluster_shape = {1, 1, 1};\n+ hw_info.cluster_shape_fallback = {1, 1, 1};\n+ return hw_info;\n+ }(),\n+ };\n+ auto& fusion_args = arguments.epilogue.thread;\n+ fusion_args.alpha = 1.0f;\n+ fusion_args.beta = 0.0f;\n+\n+ Gemm gemm;\n+\n+ size_t workspace_size = Gemm::get_workspace_size(arguments);\n+ AlignedAllocator float_allocator(float_buffer, float_buffer_size_in_bytes);\n+ auto workspace_ptr = float_allocator.aligned_alloc<void>(\n+ workspace_size, 16, \"sm100_groupwise_gemm_small_batch_size_float_workspace\");\n+\n+ CUTLASS_CHECK(gemm.can_implement(arguments));\n+ CUTLASS_CHECK(gemm.initialize(arguments, workspace_ptr));\n+ CUTLASS_CHECK(gemm.run(stream));\n+ return cudaSuccess;\n+}\n+\n } // namespace gemm\n \n } // namespace flashinfer"},"lines_added":{"kind":"number","value":148,"string":"148"},"lines_removed":{"kind":"number","value":3,"string":"3"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":["deepseek","qwen"],"string":"[\n \"deepseek\",\n \"qwen\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/gemm/gemm_groupwise_sm100.cuh).\n\nGoal: [perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32\nTarget hardware: unspecified\nTarget models: deepseek, qwen\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2025 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef FLASHINFER_GEMM_GROUPWISE_SM100_CUH_\n#define FLASHINFER_GEMM_GROUPWISE_SM100_CUH_\n\n#include <type_traits>\n\n#include \"../allocator.h\"\n#include \"../cutlass_utils.cuh\"\n#include \"../utils.cuh\"\n\nnamespace flashinfer {\n\nnamespace gemm {\n\nusing namespace cute;\n\ntemplate <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,\n int MmaSM, typename DTypeIn, typename DTypeOut>\ncudaError_t CutlassGroupwiseScaledGEMMSM100(void* float_buffer, size_t float_buffer_size_in_bytes,\n DTypeIn* A_ptr, DTypeIn* B_ptr, float* SFA_ptr,\n float* SFB_ptr, DTypeOut* C_ptr, int m, int n, int k,\n int l, cudaStream_t stream) {\n using ElementA = DTypeIn; // Element type for A matrix operand\n using LayoutA = cutlass::layout::RowMajor; // Layout type for A matrix operand\n constexpr int AlignmentA =\n 128 / cutlass::sizeof_bits<ElementA>::value; // Memory access granularity/alignment of A\n // matrix in units of elements (up to 16 bytes)\n\n // B matrix configuration\n using ElementB = DTypeIn; // Element type for B matrix operand\n using LayoutB = cutlass::layout::ColumnMajor; // Layout type for B matrix operand\n constexpr int AlignmentB =\n 128 / cutlass::sizeof_bits<ElementB>::value; // Memory access granularity/alignment of A\n // matrix in units of elements (up to 16 bytes)\n\n // C/D matrix configuration\n using ElementC = DTypeOut; // Element type for C and D matrix operands\n using LayoutC = cutlass::layout::RowMajor; // Layout type for C and D matrix operands\n constexpr int AlignmentC =\n 128 / cutlass::sizeof_bits<ElementC>::value; // Memory access granularity/alignment of A\n // matrix in units of elements (up to 16 bytes)\n\n using ElementD = ElementC;\n using LayoutD = LayoutC;\n constexpr int AlignmentD = AlignmentC;\n\n // MMA type\n using ElementAccumulator = float; // Element Accumulator will also be our scale factor type\n using ElementCompute = float;\n\n using MmaTileShape_MNK = Shape<cute::Int<MmaSM * 128>, _128, _128>;\n using ClusterShape_MNK = Shape<cute::Int<MmaSM>, _1, _1>;\n\n // NOTE(Zihao):: UMMA::Major::MN, UMMA::Major::MN is the fastest configuration.\n\n using ScaleConfig = std::conditional_t<\n ScaleMajorK,\n cutlass::detail::Sm100BlockwiseScaleConfig<ScaleGranularityM, ScaleGranularityN,\n ScaleGranularityK, UMMA::Major::K, UMMA::Major::K>,\n cutlass::detail::Sm100BlockwiseScaleConfig<ScaleGranularityM, ScaleGranularityN,\n ScaleGranularityK, UMMA::Major::MN,\n UMMA::Major::MN>>;\n\n using LayoutSFA =\n decltype(ScaleConfig::deduce_layoutSFA()); // Layout type for SFA matrix operand\n using LayoutSFB =\n decltype(ScaleConfig::deduce_layoutSFB()); // Layout type for SFB matrix operand\n using CollectiveEpilogue = typename cutlass::epilogue::collective::CollectiveBuilder<\n cutlass::arch::Sm100, cutlass::arch::OpClassTensorOp, MmaTileShape_MNK, ClusterShape_MNK,\n cutlass::epilogue::collective::EpilogueTileAuto, ElementAccumulator, ElementCompute, ElementC,\n LayoutC, AlignmentC, ElementD, LayoutC, AlignmentD,\n cutlass::epilogue::collective::EpilogueScheduleAuto>::CollectiveOp;\n\n using CollectiveMainloop = typename cutlass::gemm::collective::CollectiveBuilder<\n cutlass::arch::Sm100, cutlass::arch::OpClassTensorOp, ElementA,\n cute::tuple<LayoutA, LayoutSFA>, AlignmentA, ElementB, cute::tuple<LayoutB, LayoutSFB>,\n AlignmentB, ElementAccumulator, MmaTileShape_MNK, ClusterShape_MNK,\n cutlass::gemm::collective::StageCountAutoCarveout<static_cast<int>(\n sizeof(typename CollectiveEpilogue::SharedStorage))>,\n cutlass::gemm::KernelScheduleSm100Blockwise>::CollectiveOp;\n\n using GemmKernel = cutlass::gemm::kernel::GemmUniversal<\n Shape<int, int, int, int>, CollectiveMainloop, CollectiveEpilogue,\n void>; // Default to ClusterLaunchControl (CLC) based tile scheduler\n\n using Gemm = cutlass::gemm::device::GemmUniversalAdapter<GemmKernel>;\n\n using StrideA = typename Gemm::GemmKernel::StrideA;\n using StrideB = typename Gemm::GemmKernel::StrideB;\n using StrideC = typename Gemm::GemmKernel::StrideC;\n using StrideD = typename Gemm::GemmKernel::StrideD;\n\n auto stride_A = cutlass::make_cute_packed_stride(StrideA{}, cute::make_shape(m, k, l));\n auto stride_B = cutlass::make_cute_packed_stride(StrideB{}, cute::make_shape(n, k, l));\n auto stride_C = cutlass::make_cute_packed_stride(StrideC{}, cute::make_shape(m, n, l));\n auto stride_D = cutlass::make_cute_packed_stride(StrideD{}, cute::make_shape(m, n, l));\n\n auto layout_SFA = ScaleConfig::tile_atom_to_shape_SFA(make_shape(m, n, k, l));\n auto layout_SFB = ScaleConfig::tile_atom_to_shape_SFB(make_shape(m, n, k, l));\n\n typename Gemm::Arguments arguments{cutlass::gemm::GemmUniversalMode::kGemm,\n {m, n, k, l},\n {\n A_ptr,\n stride_A,\n B_ptr,\n stride_B,\n SFA_ptr,\n layout_SFA,\n SFB_ptr,\n layout_SFB,\n },\n {\n {}, // epilogue.thread\n C_ptr,\n stride_C,\n C_ptr,\n stride_C,\n }};\n auto& fusion_args = arguments.epilogue.thread;\n fusion_args.alpha = 1.0f;\n fusion_args.beta = 0.0f;\n\n Gemm gemm;\n\n size_t workspace_size = Gemm::get_workspace_size(arguments);\n AlignedAllocator float_allocator(float_buffer, float_buffer_size_in_bytes);\n auto workspace_ptr = float_allocator.aligned_alloc<void>(workspace_size, 16,\n \"sm100_groupwise_gemm_float_workspace\");\n\n CUTLASS_CHECK(gemm.can_implement(arguments));\n CUTLASS_CHECK(gemm.initialize(arguments, workspace_ptr));\n CUTLASS_CHECK(gemm.run(stream));\n return cudaSuccess;\n}\n\n} // namespace gemm\n\n} // namespace flashinfer\n\n#endif // FLASHINFER_GEMM_GROUPWISE_SM100_CUH_\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nImproves gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32.\n\nThese are shapes typical for DeepSeek V3 and Qwen 3 235B - q, k, v, and o_proj:\n\n```\n+-------+-------+------+-----------+---------------+--------------+---------------+--------------+-------------+\n| batch | out | in | fp16 (us) | fp8 before(us)| ratio before | fp8 after (us)| ratio after | improvement |\n+-------+-------+------+-----------+---------------+--------------+---------------+--------------+-------------+\n| 1 | 1536 | 7168 | 14.26 | | | 20.48 | 0.66 | |\n| 8 | 1536 | 7168 | 14.37 | 24.58 | 0.58 | 20.48 | 0.70 | 1.20 |\n| 16 | 1536 | 7168 | 14.40 | 24.56 | 0.59 | 20.48 | 0.74 | 1.20 |\n| 32 | 1536 | 7168 | 18.40 | 24.56 | 0.75 | 20.48 | 0.85 | 1.20 |\n| 1 | 24576 | 1536 | 22.61 | | | 18.46 | 1.32 | |\n| 8 | 24576 | 1536 | 22.56 | 22.56 | 1.00 | 18.46 | 1.22 | 1.22 |\n| 16 | 24576 | 1536 | 22.59 | 22.56 | 1.00 | 18.46 | 1.23 | 1.22 |\n| 32 | 24576 | 1536 | 22.62 | 22.53 | 1.00 | 20.48 | 1.10 | 1.10 |\n| 1 | 32768 | 512 | 14.37 | | | 14.37 | 1.00 | |\n| 8 | 32768 | 512 | 14.34 | 16.35 | 0.88 | 14.37 | 1.00 | 1.14 |\n| 16 | 32768 | 512 | 14.37 | 14.40 | 1.00 | 14.34 | 1.00 | 1.00 |\n| 32 | 32768 | 512 | 14.34 | 14.37 | 1.00 | 14.37 | 1.00 | 1.00 |\n| 1 | 7168 | 7168 | 28.78 | | | 22.53 | 1.28 | |\n| 8 | 7168 | 7168 | 28.70 | 32.77 | 0.88 | 22.53 | 1.27 | 1.45 |\n| 16 | 7168 | 7168 | 28.67 | 30.75 | 0.93 | 22.53 | 1.27 | 1.37 |\n| 32 | 7168 | 7168 | 30.75 | 28.67 | 1.07 | 22.56 | 1.36 | 1.27 |\n| 1 | 12288 | 4096 | 31.74 | | | 20.51 | 1.55 | |\n| 8 | 12288 | 4096 | 29.73 | 26.62 | 1.12 | 20.51 | 1.45 | 1.30 |\n| 16 | 12288 | 4096 | 28.70 | 26.64 | 1.08 | 20.51 | 1.40 | 1.30 |\n| 32 | 12288 | 4096 | 28.67 | 22.54 | 1.27 | 24.58 | 1.17 | 0.92 |\n| 1 | 4096 | 4096 | 16.46 | | | 16.40 | 1.01 | |\n| 8 | 4096 | 4096 | 16.42 | 18.43 | 0.89 | 16.38 | 1.00 | 1.13 |\n| 16 | 4096 | 4096 | 16.42 | 18.46 | 0.89 | 16.38 | 1.00 | 1.13 |\n| 32 | 4096 | 4096 | 14.34 | 18.43 | 0.78 | 16.38 | 0.88 | 1.13 |\n| | | | | | | | | avg: 1.18 |\n+-------+-------+------+-----------+---------------+--------------+---------------+--------------+-------------+\n```\n\nBenchmarking script I'm using is modified version of user's script in: https://github.com/issues/recent?issue=flashinfer-ai%7Cflashinfer%7C2146\n\nCredit to @depaulmillz on the transpose trick: https://github.com/NVIDIA/cutlass/issues/2923#issuecomment-3707263529\n\n## 🔍 Related Issues\n\nFound this optimization while working on https://github.com/issues/recent?issue=flashinfer-ai%7Cflashinfer%7C2146 - note this user's issue is still outstanding - their shapes are different.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [ ] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n## Release Notes\n\n* **New Features**\n * Added performance optimization for small batch matrix operations\n\n* **Tests**\n * Expanded test coverage for small batch configurations with various matrix dimensions\n\n* **Chores**\n * Updated benchmark suite to evaluate broader range of operation sizes\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=1536,in=7168\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 24.58, \"optimized\": 20.48, \"stated_speedup\": 1.2, \"speedup\": 1.2002}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=1536,in=7168\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 24.56, \"optimized\": 20.48, \"stated_speedup\": 1.2, \"speedup\": 1.1992}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=1536,in=7168\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 24.56, \"optimized\": 20.48, \"stated_speedup\": 1.2, \"speedup\": 1.1992}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=24576,in=1536\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 22.56, \"optimized\": 18.46, \"stated_speedup\": 1.22, \"speedup\": 1.2221}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=24576,in=1536\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 22.56, \"optimized\": 18.46, \"stated_speedup\": 1.22, \"speedup\": 1.2221}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=24576,in=1536\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 22.53, \"optimized\": 20.48, \"stated_speedup\": 1.1, \"speedup\": 1.1001}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=32768,in=512\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 16.35, \"optimized\": 14.37, \"stated_speedup\": 1.14, \"speedup\": 1.1378}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=7168,in=7168\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 32.77, \"optimized\": 22.53, \"stated_speedup\": 1.45, \"speedup\": 1.4545}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=7168,in=7168\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 30.75, \"optimized\": 22.53, \"stated_speedup\": 1.37, \"speedup\": 1.3648}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=7168,in=7168\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 28.67, \"optimized\": 22.56, \"stated_speedup\": 1.27, \"speedup\": 1.2708}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=12288,in=4096\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 26.62, \"optimized\": 20.51, \"stated_speedup\": 1.3, \"speedup\": 1.2979}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=12288,in=4096\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 26.64, \"optimized\": 20.51, \"stated_speedup\": 1.3, \"speedup\": 1.2989}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=12288,in=4096\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 22.54, \"optimized\": 24.58, \"stated_speedup\": 0.92, \"speedup\": 0.917}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=4096,in=4096\", \"batch_size\": 8, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 18.43, \"optimized\": 16.38, \"stated_speedup\": 1.13, \"speedup\": 1.1252}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=4096,in=4096\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 18.46, \"optimized\": 16.38, \"stated_speedup\": 1.13, \"speedup\": 1.127}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"DeepSeek V3, Qwen 3 235B\", \"shape\": \"out=4096,in=4096\", \"batch_size\": 32, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 18.43, \"optimized\": 16.38, \"stated_speedup\": 1.13, \"speedup\": 1.1252}]"},"kernel_speedup":{"kind":"number","value":1.1997,"string":"1.1997"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1191,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"4ccc133c216f3ceaf49fc94ba8ad5984feb0f039"},"date":{"kind":"string","value":"2026-01-13T22:20:39+01:00"},"pr_number":{"kind":"number","value":2323,"string":"2,323"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2323"},"title":{"kind":"string","value":"[ML3] Optimized Router Gemm (#2323)"},"message":{"kind":"string","value":"[ML3] Optimized Router Gemm (#2323)"},"path":{"kind":"string","value":"csrc/dsv3_router_gemm.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"#include \"flashinfer/gemm/dsv3_router_gemm.cuh\"\n#include \"tvm_ffi_utils.h\"\n\nnamespace flashinfer::trtllm_dsv3_router_gemm {\ntemplate <typename T, int kNumTokens, int kNumExperts, int kHiddenDim>\nvoid invokeRouterGemm(float* output, T const* mat_a, T const* mat_b, cudaStream_t stream,\n bool use_pdl = false) {\n constexpr int VPT = 16 / sizeof(T);\n constexpr int kBlockSize = 128;\n cudaLaunchConfig_t config;\n config.gridDim = kNumExperts;\n config.blockDim = kBlockSize;\n config.dynamicSmemBytes = 0;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = use_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n auto status = cudaLaunchKernelEx(\n &config, router_gemm_kernel<T, kBlockSize, VPT, kNumTokens, kNumExperts, kHiddenDim>, output,\n mat_a, mat_b);\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"cudaLaunchKernelEx failed with error code \" << cudaGetErrorString(status);\n}\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 1, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 2, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 3, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 4, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 5, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 6, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 7, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 8, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 9, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 10, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 11, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 12, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 13, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 14, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 15, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 16, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate <int kBegin, int kEnd, int kNumExperts, int kHiddenDim>\nstruct LoopUnroller {\n static void unroll(int num_tokens, float* output, __nv_bfloat16 const* input,\n __nv_bfloat16 const* weights, cudaStream_t stream, bool launch_with_pdl) {\n if (num_tokens == kBegin) {\n invokeRouterGemm<__nv_bfloat16, kBegin, kNumExperts, kHiddenDim>(output, input, weights,\n stream, launch_with_pdl);\n } else {\n LoopUnroller<kBegin + 1, kEnd, kNumExperts, kHiddenDim>::unroll(\n num_tokens, output, input, weights, stream, launch_with_pdl);\n }\n }\n};\n\ntemplate <int kEnd, int kNumExperts, int kHiddenDim>\nstruct LoopUnroller<kEnd, kEnd, kNumExperts, kHiddenDim> {\n static void unroll(int num_tokens, float* output, __nv_bfloat16 const* input,\n __nv_bfloat16 const* weights, cudaStream_t stream, bool launch_with_pdl) {\n if (num_tokens == kEnd) {\n invokeRouterGemm<__nv_bfloat16, kEnd, kNumExperts, kHiddenDim>(output, input, weights, stream,\n launch_with_pdl);\n } else {\n throw std::invalid_argument(\"Invalid num_tokens, only supports 1 to 16\");\n }\n }\n};\n\nvoid dsv3_router_gemm_op(TensorView mat_a, TensorView mat_b, TensorView out, bool launch_with_pdl) {\n int const num_tokens = mat_a.sizes()[0];\n int const num_experts = mat_b.sizes()[1];\n int const hidden_dim = mat_a.sizes()[1];\n auto const out_dtype_ = out.dtype();\n auto const data_type = mat_a.dtype();\n constexpr int kNumExperts = 256;\n constexpr int kHiddenDim = 7168;\n std::vector<int64_t> output_size = {mat_a.sizes()[0], mat_b.sizes()[1]};\n TVM_FFI_ICHECK(mat_a.dim() == 2 && mat_b.dim() == 2) << \"mat_a and mat_b must be 2D tensors\";\n TVM_FFI_ICHECK(mat_a.strides()[1] == 1 && out.strides()[1] == 1)\n << \"mat_a and out must be row-major\";\n TVM_FFI_ICHECK(mat_b.strides()[0] == 1) << \"mat_b must be column-major\";\n auto stream = get_stream(mat_a.device());\n bool use_custom_kernel = false;\n if (num_tokens >= 1 && num_tokens <= 16 && num_experts == kNumExperts &&\n hidden_dim == kHiddenDim && encode_dlpack_dtype(data_type) == bfloat16_code &&\n encode_dlpack_dtype(out_dtype_) == float32_code) {\n use_custom_kernel = true;\n }\n\n if (use_custom_kernel) {\n LoopUnroller<1, 16, kNumExperts, kHiddenDim>::unroll(\n num_tokens, reinterpret_cast<float*>(out.data_ptr()),\n reinterpret_cast<__nv_bfloat16 const*>(mat_a.data_ptr()),\n reinterpret_cast<__nv_bfloat16 const*>(mat_b.data_ptr()), stream, launch_with_pdl);\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input tensor size\";\n }\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(dsv3_router_gemm_op,\n flashinfer::trtllm_dsv3_router_gemm::dsv3_router_gemm_op);\n\n} // namespace flashinfer::trtllm_dsv3_router_gemm\n"},"after_code":{"kind":"string","value":"#include \"flashinfer/gemm/dsv3_router_gemm.cuh\"\n#include \"tvm_ffi_utils.h\"\n\nnamespace flashinfer::trtllm_dsv3_router_gemm {\n\n// Note: Explicit template instantiations are not needed here because\n// LoopUnroller already forces instantiation of all required specializations.\ntemplate <typename Tin, typename Tout, int kNumTokens, int kNumExperts, int kHiddenDim>\nvoid invokeRouterGemm(Tout* output, Tin const* mat_a, Tin const* mat_b, cudaStream_t stream,\n bool use_pdl = false) {\n constexpr int VPT = 16 / sizeof(Tin);\n constexpr int kBlockSize = 128;\n cudaLaunchConfig_t config;\n config.gridDim = kNumExperts;\n config.blockDim = kBlockSize;\n config.dynamicSmemBytes = 0;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = use_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n auto status = cudaLaunchKernelEx(\n &config, router_gemm_kernel<Tin, Tout, kBlockSize, VPT, kNumTokens, kNumExperts, kHiddenDim>,\n output, mat_a, mat_b);\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"cudaLaunchKernelEx failed with error code \" << cudaGetErrorString(status);\n}\n\ntemplate <int kBegin, int kEnd, int kNumExperts, int kHiddenDim>\nstruct LoopUnroller {\n template <typename Tout>\n static void unroll(int num_tokens, Tout* output, __nv_bfloat16 const* input,\n __nv_bfloat16 const* weights, cudaStream_t stream, bool launch_with_pdl) {\n if (num_tokens == kBegin) {\n invokeRouterGemm<__nv_bfloat16, Tout, kBegin, kNumExperts, kHiddenDim>(\n output, input, weights, stream, launch_with_pdl);\n } else {\n LoopUnroller<kBegin + 1, kEnd, kNumExperts, kHiddenDim>::unroll(\n num_tokens, output, input, weights, stream, launch_with_pdl);\n }\n }\n};\n\ntemplate <int kEnd, int kNumExperts, int kHiddenDim>\nstruct LoopUnroller<kEnd, kEnd, kNumExperts, kHiddenDim> {\n template <typename Tout>\n static void unroll(int num_tokens, Tout* output, __nv_bfloat16 const* input,\n __nv_bfloat16 const* weights, cudaStream_t stream, bool launch_with_pdl) {\n if (num_tokens == kEnd) {\n invokeRouterGemm<__nv_bfloat16, Tout, kEnd, kNumExperts, kHiddenDim>(output, input, weights,\n stream, launch_with_pdl);\n } else {\n throw std::invalid_argument(\"Invalid num_tokens, only supports 1 to 16\");\n }\n }\n};\n\ntemplate <typename Tout, int64_t tout_code, int kNumExperts, int kBegin, int kEnd>\nvoid generic_router_gemm_op(TensorView mat_a, TensorView mat_b, TensorView out,\n bool launch_with_pdl) {\n int const num_tokens = mat_a.sizes()[0];\n int const num_experts = mat_b.sizes()[1];\n int const hidden_dim = mat_a.sizes()[1];\n auto const out_dtype_ = out.dtype();\n auto const data_type = mat_a.dtype();\n constexpr int kHiddenDim = 7168;\n std::vector<int64_t> output_size = {mat_a.sizes()[0], mat_b.sizes()[1]};\n TVM_FFI_ICHECK(mat_a.dim() == 2 && mat_b.dim() == 2) << \"mat_a and mat_b must be 2D tensors\";\n TVM_FFI_ICHECK(mat_a.strides()[1] == 1 && out.strides()[1] == 1)\n << \"mat_a and out must be row-major\";\n TVM_FFI_ICHECK(mat_b.strides()[0] == 1) << \"mat_b must be column-major\";\n auto stream = get_stream(mat_a.device());\n bool use_custom_kernel = false;\n if (num_tokens >= 1 && num_tokens <= 16 && num_experts == kNumExperts &&\n hidden_dim == kHiddenDim && encode_dlpack_dtype(data_type) == bfloat16_code &&\n encode_dlpack_dtype(out_dtype_) == tout_code) {\n use_custom_kernel = true;\n }\n\n if (use_custom_kernel) {\n LoopUnroller<kBegin, kEnd, kNumExperts, kHiddenDim>::unroll(\n num_tokens, reinterpret_cast<Tout*>(out.data_ptr()),\n reinterpret_cast<__nv_bfloat16 const*>(mat_a.data_ptr()),\n reinterpret_cast<__nv_bfloat16 const*>(mat_b.data_ptr()), stream, launch_with_pdl);\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input tensor size\";\n }\n}\n\nvoid dsv3_router_gemm_op(TensorView mat_a, TensorView mat_b, TensorView out, bool launch_with_pdl) {\n generic_router_gemm_op<float, float32_code, 256, 1, 16>(mat_a, mat_b, out, launch_with_pdl);\n}\n\nvoid ml3_router_gemm_op(TensorView mat_a, TensorView mat_b, TensorView out, bool launch_with_pdl) {\n generic_router_gemm_op<__nv_bfloat16, bfloat16_code, 128, 1, 16>(mat_a, mat_b, out,\n launch_with_pdl);\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(dsv3_router_gemm_op,\n flashinfer::trtllm_dsv3_router_gemm::dsv3_router_gemm_op);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(ml3_router_gemm_op,\n flashinfer::trtllm_dsv3_router_gemm::ml3_router_gemm_op);\n\n} // namespace flashinfer::trtllm_dsv3_router_gemm\n"},"diff":{"kind":"string","value":"--- csrc/dsv3_router_gemm.cu\n+++ csrc/dsv3_router_gemm.cu\n@@ -2,10 +2,13 @@\n #include \"tvm_ffi_utils.h\"\n \n namespace flashinfer::trtllm_dsv3_router_gemm {\n-template <typename T, int kNumTokens, int kNumExperts, int kHiddenDim>\n-void invokeRouterGemm(float* output, T const* mat_a, T const* mat_b, cudaStream_t stream,\n+\n+// Note: Explicit template instantiations are not needed here because\n+// LoopUnroller already forces instantiation of all required specializations.\n+template <typename Tin, typename Tout, int kNumTokens, int kNumExperts, int kHiddenDim>\n+void invokeRouterGemm(Tout* output, Tin const* mat_a, Tin const* mat_b, cudaStream_t stream,\n bool use_pdl = false) {\n- constexpr int VPT = 16 / sizeof(T);\n+ constexpr int VPT = 16 / sizeof(Tin);\n constexpr int kBlockSize = 128;\n cudaLaunchConfig_t config;\n config.gridDim = kNumExperts;\n@@ -18,83 +21,20 @@\n config.numAttrs = 1;\n config.attrs = attrs;\n auto status = cudaLaunchKernelEx(\n- &config, router_gemm_kernel<T, kBlockSize, VPT, kNumTokens, kNumExperts, kHiddenDim>, output,\n- mat_a, mat_b);\n+ &config, router_gemm_kernel<Tin, Tout, kBlockSize, VPT, kNumTokens, kNumExperts, kHiddenDim>,\n+ output, mat_a, mat_b);\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"cudaLaunchKernelEx failed with error code \" << cudaGetErrorString(status);\n }\n \n-template void invokeRouterGemm<__nv_bfloat16, 1, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 2, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 3, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 4, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 5, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 6, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 7, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 8, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 9, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 10, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 11, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 12, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 13, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 14, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 15, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n-template void invokeRouterGemm<__nv_bfloat16, 16, 256, 7168>(float*, __nv_bfloat16 const*,\n- __nv_bfloat16 const*, cudaStream_t,\n- bool);\n-\n template <int kBegin, int kEnd, int kNumExperts, int kHiddenDim>\n struct LoopUnroller {\n- static void unroll(int num_tokens, float* output, __nv_bfloat16 const* input,\n+ template <typename Tout>\n+ static void unroll(int num_tokens, Tout* output, __nv_bfloat16 const* input,\n __nv_bfloat16 const* weights, cudaStream_t stream, bool launch_with_pdl) {\n if (num_tokens == kBegin) {\n- invokeRouterGemm<__nv_bfloat16, kBegin, kNumExperts, kHiddenDim>(output, input, weights,\n- stream, launch_with_pdl);\n+ invokeRouterGemm<__nv_bfloat16, Tout, kBegin, kNumExperts, kHiddenDim>(\n+ output, input, weights, stream, launch_with_pdl);\n } else {\n LoopUnroller<kBegin + 1, kEnd, kNumExperts, kHiddenDim>::unroll(\n num_tokens, output, input, weights, stream, launch_with_pdl);\n@@ -104,24 +44,26 @@\n \n template <int kEnd, int kNumExperts, int kHiddenDim>\n struct LoopUnroller<kEnd, kEnd, kNumExperts, kHiddenDim> {\n- static void unroll(int num_tokens, float* output, __nv_bfloat16 const* input,\n+ template <typename Tout>\n+ static void unroll(int num_tokens, Tout* output, __nv_bfloat16 const* input,\n __nv_bfloat16 const* weights, cudaStream_t stream, bool launch_with_pdl) {\n if (num_tokens == kEnd) {\n- invokeRouterGemm<__nv_bfloat16, kEnd, kNumExperts, kHiddenDim>(output, input, weights, stream,\n- launch_with_pdl);\n+ invokeRouterGemm<__nv_bfloat16, Tout, kEnd, kNumExperts, kHiddenDim>(output, input, weights,\n+ stream, launch_with_pdl);\n } else {\n throw std::invalid_argument(\"Invalid num_tokens, only supports 1 to 16\");\n }\n }\n };\n \n-void dsv3_router_gemm_op(TensorView mat_a, TensorView mat_b, TensorView out, bool launch_with_pdl) {\n+template <typename Tout, int64_t tout_code, int kNumExperts, int kBegin, int kEnd>\n+void generic_router_gemm_op(TensorView mat_a, TensorView mat_b, TensorView out,\n+ bool launch_with_pdl) {\n int const num_tokens = mat_a.sizes()[0];\n int const num_experts = mat_b.sizes()[1];\n int const hidden_dim = mat_a.sizes()[1];\n auto const out_dtype_ = out.dtype();\n auto const data_type = mat_a.dtype();\n- constexpr int kNumExperts = 256;\n constexpr int kHiddenDim = 7168;\n std::vector<int64_t> output_size = {mat_a.sizes()[0], mat_b.sizes()[1]};\n TVM_FFI_ICHECK(mat_a.dim() == 2 && mat_b.dim() == 2) << \"mat_a and mat_b must be 2D tensors\";\n@@ -132,13 +74,13 @@\n bool use_custom_kernel = false;\n if (num_tokens >= 1 && num_tokens <= 16 && num_experts == kNumExperts &&\n hidden_dim == kHiddenDim && encode_dlpack_dtype(data_type) == bfloat16_code &&\n- encode_dlpack_dtype(out_dtype_) == float32_code) {\n+ encode_dlpack_dtype(out_dtype_) == tout_code) {\n use_custom_kernel = true;\n }\n \n if (use_custom_kernel) {\n- LoopUnroller<1, 16, kNumExperts, kHiddenDim>::unroll(\n- num_tokens, reinterpret_cast<float*>(out.data_ptr()),\n+ LoopUnroller<kBegin, kEnd, kNumExperts, kHiddenDim>::unroll(\n+ num_tokens, reinterpret_cast<Tout*>(out.data_ptr()),\n reinterpret_cast<__nv_bfloat16 const*>(mat_a.data_ptr()),\n reinterpret_cast<__nv_bfloat16 const*>(mat_b.data_ptr()), stream, launch_with_pdl);\n } else {\n@@ -146,7 +88,18 @@\n }\n }\n \n+void dsv3_router_gemm_op(TensorView mat_a, TensorView mat_b, TensorView out, bool launch_with_pdl) {\n+ generic_router_gemm_op<float, float32_code, 256, 1, 16>(mat_a, mat_b, out, launch_with_pdl);\n+}\n+\n+void ml3_router_gemm_op(TensorView mat_a, TensorView mat_b, TensorView out, bool launch_with_pdl) {\n+ generic_router_gemm_op<__nv_bfloat16, bfloat16_code, 128, 1, 16>(mat_a, mat_b, out,\n+ launch_with_pdl);\n+}\n+\n TVM_FFI_DLL_EXPORT_TYPED_FUNC(dsv3_router_gemm_op,\n flashinfer::trtllm_dsv3_router_gemm::dsv3_router_gemm_op);\n+TVM_FFI_DLL_EXPORT_TYPED_FUNC(ml3_router_gemm_op,\n+ flashinfer::trtllm_dsv3_router_gemm::ml3_router_gemm_op);\n \n } // namespace flashinfer::trtllm_dsv3_router_gemm"},"lines_added":{"kind":"number","value":33,"string":"33"},"lines_removed":{"kind":"number","value":80,"string":"80"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":["deepseek"],"string":"[\n \"deepseek\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/dsv3_router_gemm.cu).\n\nGoal: [ML3] Optimized Router Gemm\nTarget hardware: unspecified\nTarget models: deepseek\n\nCurrent file:\n```cuda\n#include \"flashinfer/gemm/dsv3_router_gemm.cuh\"\n#include \"tvm_ffi_utils.h\"\n\nnamespace flashinfer::trtllm_dsv3_router_gemm {\ntemplate <typename T, int kNumTokens, int kNumExperts, int kHiddenDim>\nvoid invokeRouterGemm(float* output, T const* mat_a, T const* mat_b, cudaStream_t stream,\n bool use_pdl = false) {\n constexpr int VPT = 16 / sizeof(T);\n constexpr int kBlockSize = 128;\n cudaLaunchConfig_t config;\n config.gridDim = kNumExperts;\n config.blockDim = kBlockSize;\n config.dynamicSmemBytes = 0;\n config.stream = stream;\n cudaLaunchAttribute attrs[1];\n attrs[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attrs[0].val.programmaticStreamSerializationAllowed = use_pdl;\n config.numAttrs = 1;\n config.attrs = attrs;\n auto status = cudaLaunchKernelEx(\n &config, router_gemm_kernel<T, kBlockSize, VPT, kNumTokens, kNumExperts, kHiddenDim>, output,\n mat_a, mat_b);\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"cudaLaunchKernelEx failed with error code \" << cudaGetErrorString(status);\n}\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 1, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 2, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 3, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 4, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 5, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 6, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 7, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 8, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 9, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 10, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 11, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 12, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 13, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 14, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 15, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate void invokeRouterGemm<__nv_bfloat16, 16, 256, 7168>(float*, __nv_bfloat16 const*,\n __nv_bfloat16 const*, cudaStream_t,\n bool);\n\ntemplate <int kBegin, int kEnd, int kNumExperts, int kHiddenDim>\nstruct LoopUnroller {\n static void unroll(int num_tokens, float* output, __nv_bfloat16 const* input,\n __nv_bfloat16 const* weights, cudaStream_t stream, bool launch_with_pdl) {\n if (num_tokens == kBegin) {\n invokeRouterGemm<__nv_bfloat16, kBegin, kNumExperts, kHiddenDim>(output, input, weights,\n stream, launch_with_pdl);\n } else {\n LoopUnroller<kBegin + 1, kEnd, kNumExperts, kHiddenDim>::unroll(\n num_tokens, output, input, weights, stream, launch_with_pdl);\n }\n }\n};\n\ntemplate <int kEnd, int kNumExperts, int kHiddenDim>\nstruct LoopUnroller<kEnd, kEnd, kNumExperts, kHiddenDim> {\n static void unroll(int num_tokens, float* output, __nv_bfloat16 const* input,\n __nv_bfloat16 const* weights, cudaStream_t stream, bool launch_with_pdl) {\n if (num_tokens == kEnd) {\n invokeRouterGemm<__nv_bfloat16, kEnd, kNumExperts, kHiddenDim>(output, input, weights, stream,\n launch_with_pdl);\n } else {\n throw std::invalid_argument(\"Invalid num_tokens, only supports 1 to 16\");\n }\n }\n};\n\nvoid dsv3_router_gemm_op(TensorView mat_a, TensorView mat_b, TensorView out, bool launch_with_pdl) {\n int const num_tokens = mat_a.sizes()[0];\n int const num_experts = mat_b.sizes()[1];\n int const hidden_dim = mat_a.sizes()[1];\n auto const out_dtype_ = out.dtype();\n auto const data_type = mat_a.dtype();\n constexpr int kNumExperts = 256;\n constexpr int kHiddenDim = 7168;\n std::vector<int64_t> output_size = {mat_a.sizes()[0], mat_b.sizes()[1]};\n TVM_FFI_ICHECK(mat_a.dim() == 2 && mat_b.dim() == 2) << \"mat_a and mat_b must be 2D tensors\";\n TVM_FFI_ICHECK(mat_a.strides()[1] == 1 && out.strides()[1] == 1)\n << \"mat_a and out must be row-major\";\n TVM_FFI_ICHECK(mat_b.strides()[0] == 1) << \"mat_b must be column-major\";\n auto stream = get_stream(mat_a.device());\n bool use_custom_kernel = false;\n if (num_tokens >= 1 && num_tokens <= 16 && num_experts == kNumExperts &&\n hidden_dim == kHiddenDim && encode_dlpack_dtype(data_type) == bfloat16_code &&\n encode_dlpack_dtype(out_dtype_) == float32_code) {\n use_custom_kernel = true;\n }\n\n if (use_custom_kernel) {\n LoopUnroller<1, 16, kNumExperts, kHiddenDim>::unroll(\n num_tokens, reinterpret_cast<float*>(out.data_ptr()),\n reinterpret_cast<__nv_bfloat16 const*>(mat_a.data_ptr()),\n reinterpret_cast<__nv_bfloat16 const*>(mat_b.data_ptr()), stream, launch_with_pdl);\n } else {\n TVM_FFI_LOG_AND_THROW(NotImplementedError) << \"Unsupported input tensor size\";\n }\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(dsv3_router_gemm_op,\n flashinfer::trtllm_dsv3_router_gemm::dsv3_router_gemm_op);\n\n} // namespace flashinfer::trtllm_dsv3_router_gemm\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nThis PR extends #2019 by @nvmbreughe for use with Mistral Large 3, which has similar MoE routing to DSV3. The differences are:\n- The number of experts is 128 (DSV3: 256)\n- The output type is `bfloat16` (DSV3: `float32`)\n\nThe code has been extended with a template argument for the output type, which is passed to the kernel.\n\nAlso, the explicit instantiations have been removed to make the code more concise, because they are handled by the call to the `LoopUnroller`.\n\nPerformance measurement for batch size 16 on a B200:\n| Method | Runtime |\n| ------------- | ------------- |\n| `torch.nn.functional.linear` | 45.6us |\n| `mm_M1_16_K7168_N128` | 9.41us |\n\n## 🚀 Pull Request Checklist\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added a bfloat16-capable router GEMM variant (128-expert) alongside the existing float32 256-expert variant; both are available via the public API.\n\n* **Tests**\n * Expanded tests to cover multiple data types and both configuration variants.\n\n* **Chores**\n * Generalized shape-validation and streamlined public exports to support multiple output dtypes.\n\n* **Benchmarks**\n * Added a benchmark script to measure and compare router GEMM performance across configs.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"Mistral Large 3\", \"shape\": \"M=16,K=7168,N=128\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 45.6, \"optimized\": 9.41, \"stated_speedup\": null, \"speedup\": 4.8459}]"},"kernel_speedup":{"kind":"number","value":4.8459,"string":"4.8459"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1192,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"4ccc133c216f3ceaf49fc94ba8ad5984feb0f039"},"date":{"kind":"string","value":"2026-01-13T22:20:39+01:00"},"pr_number":{"kind":"number","value":2323,"string":"2,323"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2323"},"title":{"kind":"string","value":"[ML3] Optimized Router Gemm (#2323)"},"message":{"kind":"string","value":"[ML3] Optimized Router Gemm (#2323)"},"path":{"kind":"string","value":"include/flashinfer/gemm/dsv3_router_gemm.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n\nnamespace flashinfer::trtllm_dsv3_router_gemm {\n// Custom FMA implementation using PTX assembly instructions\n__device__ __forceinline__ void fma(float2& d, float2 const& a, float2 const& b, float2 const& c) {\n asm volatile(\"fma.rn.f32x2 %0, %1, %2, %3;\\n\"\n : \"=l\"(reinterpret_cast<uint64_t&>(d))\n : \"l\"(reinterpret_cast<uint64_t const&>(a)),\n \"l\"(reinterpret_cast<uint64_t const&>(b)),\n \"l\"(reinterpret_cast<uint64_t const&>(c)));\n}\n\n// Convert 8 bfloat16 values from a uint4 to float array - optimized conversion\ntemplate <int VPT>\n__device__ __forceinline__ void bf16_uint4_to_float8(uint4 const& vec, float* dst) {\n __nv_bfloat16* bf16_ptr = reinterpret_cast<__nv_bfloat16*>(const_cast<uint4*>(&vec));\n\n#pragma unroll\n for (int i = 0; i < VPT; i++) {\n dst[i] = __bfloat162float(bf16_ptr[i]);\n }\n}\n\ntemplate <typename T, int kBlockSize, int VPT, int kNumTokens, int kNumExperts, int kHiddenDim>\n__global__ __launch_bounds__(128, 1) void router_gemm_kernel(float* out, T const* mat_a,\n T const* mat_b) {\n // Each block handles one expert column\n int const n_idx = blockIdx.x;\n int const tid = threadIdx.x;\n constexpr int kWarpSize = 32;\n constexpr int kNumWarps = kBlockSize / kWarpSize;\n // Constants for this kernel\n constexpr int k_elems_per_k_iteration = VPT * kBlockSize;\n constexpr int k_iterations = kHiddenDim / k_elems_per_k_iteration; // Total K iterations\n\n // Initialize accumulators for all M rows\n float acc[kNumTokens] = {};\n\n // Shared memory for warp-level reduction\n __shared__ float sm_reduction[kNumTokens][kNumWarps]; // kNumWarps\n\n // B matrix is in column-major order, so we can directly load a column for the n_idx expert\n T const* b_col = mat_b + n_idx * kHiddenDim;\n\n // Pre-compute k_base values for each iteration to help compiler optimize\n // int k_bases[k_iterations];\n int k_bases[k_iterations];\n#pragma unroll\n for (int ki = 0; ki < k_iterations; ki++) {\n k_bases[ki] = ki * k_elems_per_k_iteration + tid * VPT;\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n // Process the GEMM in chunks\n for (int ki = 0; ki < k_iterations; ki++) {\n int const k_base = k_bases[ki];\n\n // Load B matrix values using vector load (8 bf16 values)\n uint4 b_vec = *reinterpret_cast<uint4 const*>(b_col + k_base);\n\n // Convert B values to float\n float b_float[VPT];\n bf16_uint4_to_float8<VPT>(b_vec, b_float);\n\n// Process each token\n#pragma unroll\n for (int m_idx = 0; m_idx < kNumTokens; m_idx++) {\n // Load both rows of A matrix using vector loads\n uint4 a_vec = *reinterpret_cast<uint4 const*>(mat_a + (m_idx * kHiddenDim) + k_base);\n\n // Convert A values to float\n float a_float[VPT];\n bf16_uint4_to_float8<VPT>(a_vec, a_float);\n\n// Process elements in this chunk\n#pragma unroll\n for (int k = 0; k < VPT; k++) {\n float a = a_float[k];\n float b = b_float[k];\n acc[m_idx] += a * b;\n }\n }\n }\n\n // Perform warp-level reduction\n int const warpSize = 32;\n int const warpId = tid / warpSize;\n int const laneId = tid % warpSize;\n\n // Register for warp-level reduction results\n float warp_result[kNumTokens];\n\n#pragma unroll\n for (int m_idx = 0; m_idx < kNumTokens; m_idx++) {\n warp_result[m_idx] = acc[m_idx];\n }\n\n// Perform warp-level reduction using optimized butterfly pattern\n#pragma unroll\n for (int m = 0; m < kNumTokens; m++) {\n float sum = warp_result[m];\n\n // Butterfly reduction pattern\n sum += __shfl_xor_sync(0xffffffff, sum, 16);\n sum += __shfl_xor_sync(0xffffffff, sum, 8);\n sum += __shfl_xor_sync(0xffffffff, sum, 4);\n sum += __shfl_xor_sync(0xffffffff, sum, 2);\n sum += __shfl_xor_sync(0xffffffff, sum, 1);\n\n // Only the first thread in each warp stores to shared memory\n if (laneId == 0) {\n sm_reduction[m][warpId] = sum;\n }\n }\n\n __syncthreads();\n\n // Final reduction across warps (only first thread)\n if (tid == 0) {\n#pragma unroll\n for (int m = 0; m < kNumTokens; m++) {\n float final_sum = 0.0f;\n\n// Sum across the kNumWarps\n#pragma unroll\n for (int w = 0; w < kNumWarps; w++) {\n final_sum += sm_reduction[m][w];\n }\n\n // Write final result\n out[m * kNumExperts + n_idx] = final_sum;\n }\n }\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n} // namespace flashinfer::trtllm_dsv3_router_gemm\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n\nnamespace flashinfer::trtllm_dsv3_router_gemm {\n// Custom FMA implementation using PTX assembly instructions\n__device__ __forceinline__ void fma(float2& d, float2 const& a, float2 const& b, float2 const& c) {\n asm volatile(\"fma.rn.f32x2 %0, %1, %2, %3;\\n\"\n : \"=l\"(reinterpret_cast<uint64_t&>(d))\n : \"l\"(reinterpret_cast<uint64_t const&>(a)),\n \"l\"(reinterpret_cast<uint64_t const&>(b)),\n \"l\"(reinterpret_cast<uint64_t const&>(c)));\n}\n\n// Convert 8 bfloat16 values from a uint4 to float array - optimized conversion\ntemplate <int VPT>\n__device__ __forceinline__ void bf16_uint4_to_float8(uint4 const& vec, float* dst) {\n __nv_bfloat16* bf16_ptr = reinterpret_cast<__nv_bfloat16*>(const_cast<uint4*>(&vec));\n\n#pragma unroll\n for (int i = 0; i < VPT; i++) {\n dst[i] = __bfloat162float(bf16_ptr[i]);\n }\n}\n\ntemplate <typename Tin, typename Tout, int kBlockSize, int VPT, int kNumTokens, int kNumExperts,\n int kHiddenDim>\n__global__ __launch_bounds__(128, 1) void router_gemm_kernel(Tout* out, Tin const* mat_a,\n Tin const* mat_b) {\n // Each block handles one expert column\n int const n_idx = blockIdx.x;\n int const tid = threadIdx.x;\n constexpr int kWarpSize = 32;\n constexpr int kNumWarps = kBlockSize / kWarpSize;\n // Constants for this kernel\n constexpr int k_elems_per_k_iteration = VPT * kBlockSize;\n constexpr int k_iterations = kHiddenDim / k_elems_per_k_iteration; // Total K iterations\n\n // Initialize accumulators for all M rows\n float acc[kNumTokens] = {};\n\n // Shared memory for warp-level reduction\n __shared__ float sm_reduction[kNumTokens][kNumWarps]; // kNumWarps\n\n // B matrix is in column-major order, so we can directly load a column for the n_idx expert\n Tin const* b_col = mat_b + n_idx * kHiddenDim;\n\n // Pre-compute k_base values for each iteration to help compiler optimize\n // int k_bases[k_iterations];\n int k_bases[k_iterations];\n#pragma unroll\n for (int ki = 0; ki < k_iterations; ki++) {\n k_bases[ki] = ki * k_elems_per_k_iteration + tid * VPT;\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n // Process the GEMM in chunks\n for (int ki = 0; ki < k_iterations; ki++) {\n int const k_base = k_bases[ki];\n\n // Load B matrix values using vector load (8 bf16 values)\n uint4 b_vec = *reinterpret_cast<uint4 const*>(b_col + k_base);\n\n // Convert B values to float\n float b_float[VPT];\n bf16_uint4_to_float8<VPT>(b_vec, b_float);\n\n// Process each token\n#pragma unroll\n for (int m_idx = 0; m_idx < kNumTokens; m_idx++) {\n // Load both rows of A matrix using vector loads\n uint4 a_vec = *reinterpret_cast<uint4 const*>(mat_a + (m_idx * kHiddenDim) + k_base);\n\n // Convert A values to float\n float a_float[VPT];\n bf16_uint4_to_float8<VPT>(a_vec, a_float);\n\n// Process elements in this chunk\n#pragma unroll\n for (int k = 0; k < VPT; k++) {\n float a = a_float[k];\n float b = b_float[k];\n acc[m_idx] += a * b;\n }\n }\n }\n\n // Perform warp-level reduction\n int const warpSize = 32;\n int const warpId = tid / warpSize;\n int const laneId = tid % warpSize;\n\n // Register for warp-level reduction results\n float warp_result[kNumTokens];\n\n#pragma unroll\n for (int m_idx = 0; m_idx < kNumTokens; m_idx++) {\n warp_result[m_idx] = acc[m_idx];\n }\n\n// Perform warp-level reduction using optimized butterfly pattern\n#pragma unroll\n for (int m = 0; m < kNumTokens; m++) {\n float sum = warp_result[m];\n\n // Butterfly reduction pattern\n sum += __shfl_xor_sync(0xffffffff, sum, 16);\n sum += __shfl_xor_sync(0xffffffff, sum, 8);\n sum += __shfl_xor_sync(0xffffffff, sum, 4);\n sum += __shfl_xor_sync(0xffffffff, sum, 2);\n sum += __shfl_xor_sync(0xffffffff, sum, 1);\n\n // Only the first thread in each warp stores to shared memory\n if (laneId == 0) {\n sm_reduction[m][warpId] = sum;\n }\n }\n\n __syncthreads();\n\n // Final reduction across warps (only first thread)\n if (tid == 0) {\n#pragma unroll\n for (int m = 0; m < kNumTokens; m++) {\n float final_sum = 0.0f;\n\n// Sum across the kNumWarps\n#pragma unroll\n for (int w = 0; w < kNumWarps; w++) {\n final_sum += sm_reduction[m][w];\n }\n\n // Write final result\n out[m * kNumExperts + n_idx] = final_sum;\n }\n }\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n} // namespace flashinfer::trtllm_dsv3_router_gemm\n"},"diff":{"kind":"string","value":"--- include/flashinfer/gemm/dsv3_router_gemm.cuh\n+++ include/flashinfer/gemm/dsv3_router_gemm.cuh\n@@ -39,9 +39,10 @@\n }\n }\n \n-template <typename T, int kBlockSize, int VPT, int kNumTokens, int kNumExperts, int kHiddenDim>\n-__global__ __launch_bounds__(128, 1) void router_gemm_kernel(float* out, T const* mat_a,\n- T const* mat_b) {\n+template <typename Tin, typename Tout, int kBlockSize, int VPT, int kNumTokens, int kNumExperts,\n+ int kHiddenDim>\n+__global__ __launch_bounds__(128, 1) void router_gemm_kernel(Tout* out, Tin const* mat_a,\n+ Tin const* mat_b) {\n // Each block handles one expert column\n int const n_idx = blockIdx.x;\n int const tid = threadIdx.x;\n@@ -58,7 +59,7 @@\n __shared__ float sm_reduction[kNumTokens][kNumWarps]; // kNumWarps\n \n // B matrix is in column-major order, so we can directly load a column for the n_idx expert\n- T const* b_col = mat_b + n_idx * kHiddenDim;\n+ Tin const* b_col = mat_b + n_idx * kHiddenDim;\n \n // Pre-compute k_base values for each iteration to help compiler optimize\n // int k_bases[k_iterations];"},"lines_added":{"kind":"number","value":5,"string":"5"},"lines_removed":{"kind":"number","value":4,"string":"4"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":["deepseek"],"string":"[\n \"deepseek\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/gemm/dsv3_router_gemm.cuh).\n\nGoal: [ML3] Optimized Router Gemm\nTarget hardware: unspecified\nTarget models: deepseek\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <cuda.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n\nnamespace flashinfer::trtllm_dsv3_router_gemm {\n// Custom FMA implementation using PTX assembly instructions\n__device__ __forceinline__ void fma(float2& d, float2 const& a, float2 const& b, float2 const& c) {\n asm volatile(\"fma.rn.f32x2 %0, %1, %2, %3;\\n\"\n : \"=l\"(reinterpret_cast<uint64_t&>(d))\n : \"l\"(reinterpret_cast<uint64_t const&>(a)),\n \"l\"(reinterpret_cast<uint64_t const&>(b)),\n \"l\"(reinterpret_cast<uint64_t const&>(c)));\n}\n\n// Convert 8 bfloat16 values from a uint4 to float array - optimized conversion\ntemplate <int VPT>\n__device__ __forceinline__ void bf16_uint4_to_float8(uint4 const& vec, float* dst) {\n __nv_bfloat16* bf16_ptr = reinterpret_cast<__nv_bfloat16*>(const_cast<uint4*>(&vec));\n\n#pragma unroll\n for (int i = 0; i < VPT; i++) {\n dst[i] = __bfloat162float(bf16_ptr[i]);\n }\n}\n\ntemplate <typename T, int kBlockSize, int VPT, int kNumTokens, int kNumExperts, int kHiddenDim>\n__global__ __launch_bounds__(128, 1) void router_gemm_kernel(float* out, T const* mat_a,\n T const* mat_b) {\n // Each block handles one expert column\n int const n_idx = blockIdx.x;\n int const tid = threadIdx.x;\n constexpr int kWarpSize = 32;\n constexpr int kNumWarps = kBlockSize / kWarpSize;\n // Constants for this kernel\n constexpr int k_elems_per_k_iteration = VPT * kBlockSize;\n constexpr int k_iterations = kHiddenDim / k_elems_per_k_iteration; // Total K iterations\n\n // Initialize accumulators for all M rows\n float acc[kNumTokens] = {};\n\n // Shared memory for warp-level reduction\n __shared__ float sm_reduction[kNumTokens][kNumWarps]; // kNumWarps\n\n // B matrix is in column-major order, so we can directly load a column for the n_idx expert\n T const* b_col = mat_b + n_idx * kHiddenDim;\n\n // Pre-compute k_base values for each iteration to help compiler optimize\n // int k_bases[k_iterations];\n int k_bases[k_iterations];\n#pragma unroll\n for (int ki = 0; ki < k_iterations; ki++) {\n k_bases[ki] = ki * k_elems_per_k_iteration + tid * VPT;\n }\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.wait;\");\n#endif\n\n // Process the GEMM in chunks\n for (int ki = 0; ki < k_iterations; ki++) {\n int const k_base = k_bases[ki];\n\n // Load B matrix values using vector load (8 bf16 values)\n uint4 b_vec = *reinterpret_cast<uint4 const*>(b_col + k_base);\n\n // Convert B values to float\n float b_float[VPT];\n bf16_uint4_to_float8<VPT>(b_vec, b_float);\n\n// Process each token\n#pragma unroll\n for (int m_idx = 0; m_idx < kNumTokens; m_idx++) {\n // Load both rows of A matrix using vector loads\n uint4 a_vec = *reinterpret_cast<uint4 const*>(mat_a + (m_idx * kHiddenDim) + k_base);\n\n // Convert A values to float\n float a_float[VPT];\n bf16_uint4_to_float8<VPT>(a_vec, a_float);\n\n// Process elements in this chunk\n#pragma unroll\n for (int k = 0; k < VPT; k++) {\n float a = a_float[k];\n float b = b_float[k];\n acc[m_idx] += a * b;\n }\n }\n }\n\n // Perform warp-level reduction\n int const warpSize = 32;\n int const warpId = tid / warpSize;\n int const laneId = tid % warpSize;\n\n // Register for warp-level reduction results\n float warp_result[kNumTokens];\n\n#pragma unroll\n for (int m_idx = 0; m_idx < kNumTokens; m_idx++) {\n warp_result[m_idx] = acc[m_idx];\n }\n\n// Perform warp-level reduction using optimized butterfly pattern\n#pragma unroll\n for (int m = 0; m < kNumTokens; m++) {\n float sum = warp_result[m];\n\n // Butterfly reduction pattern\n sum += __shfl_xor_sync(0xffffffff, sum, 16);\n sum += __shfl_xor_sync(0xffffffff, sum, 8);\n sum += __shfl_xor_sync(0xffffffff, sum, 4);\n sum += __shfl_xor_sync(0xffffffff, sum, 2);\n sum += __shfl_xor_sync(0xffffffff, sum, 1);\n\n // Only the first thread in each warp stores to shared memory\n if (laneId == 0) {\n sm_reduction[m][warpId] = sum;\n }\n }\n\n __syncthreads();\n\n // Final reduction across warps (only first thread)\n if (tid == 0) {\n#pragma unroll\n for (int m = 0; m < kNumTokens; m++) {\n float final_sum = 0.0f;\n\n// Sum across the kNumWarps\n#pragma unroll\n for (int w = 0; w < kNumWarps; w++) {\n final_sum += sm_reduction[m][w];\n }\n\n // Write final result\n out[m * kNumExperts + n_idx] = final_sum;\n }\n }\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n asm volatile(\"griddepcontrol.launch_dependents;\");\n#endif\n}\n} // namespace flashinfer::trtllm_dsv3_router_gemm\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nThis PR extends #2019 by @nvmbreughe for use with Mistral Large 3, which has similar MoE routing to DSV3. The differences are:\n- The number of experts is 128 (DSV3: 256)\n- The output type is `bfloat16` (DSV3: `float32`)\n\nThe code has been extended with a template argument for the output type, which is passed to the kernel.\n\nAlso, the explicit instantiations have been removed to make the code more concise, because they are handled by the call to the `LoopUnroller`.\n\nPerformance measurement for batch size 16 on a B200:\n| Method | Runtime |\n| ------------- | ------------- |\n| `torch.nn.functional.linear` | 45.6us |\n| `mm_M1_16_K7168_N128` | 9.41us |\n\n## 🚀 Pull Request Checklist\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added a bfloat16-capable router GEMM variant (128-expert) alongside the existing float32 256-expert variant; both are available via the public API.\n\n* **Tests**\n * Expanded tests to cover multiple data types and both configuration variants.\n\n* **Chores**\n * Generalized shape-validation and streamlined public exports to support multiple output dtypes.\n\n* **Benchmarks**\n * Added a benchmark script to measure and compare router GEMM performance across configs.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": \"Mistral Large 3\", \"shape\": \"M=16,K=7168,N=128\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 45.6, \"optimized\": 9.41, \"stated_speedup\": null, \"speedup\": 4.8459}]"},"kernel_speedup":{"kind":"number","value":4.8459,"string":"4.8459"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1193,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"e079eee48dec413adb66d4a142e3eb66f9f42b6f"},"date":{"kind":"string","value":"2026-01-08T07:48:37+08:00"},"pr_number":{"kind":"number","value":2265,"string":"2,265"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2265"},"title":{"kind":"string","value":"[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265)"},"message":{"kind":"string","value":"[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nThis MR adds the optimized decode attention kernels for high throughput\n(large batch size) + speculative decoding (seqlen_q > 1).\n\nSee below for speedups (collected by\n`benchmarks/flashinfer_benchmark.py`). The seqlenKv is 16K for all\ncases.\n\n| test case | median_time_ms | median_time_ms (opt) | speedup |\n\n|------------------------------------------|----------------|----------------------|----------|\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ2 | 0.057 | 0.046 | 1.24 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ2 | 0.11 | 0.083 | 1.33 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ2 | 0.213 | 0.168 | 1.27 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ2 | 0.266 | 0.241 | 1.10 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ2 | 0.432 | 0.336 | 1.29 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ4 | 0.109 | 0.048 | 2.27 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ4 | 0.212 | 0.083 | 2.55 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ4 | 0.371 | 0.168 | 2.21 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ4 | 0.472 | 0.245 | 1.93 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ4 | 0.736 | 0.348 | 2.11 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ8 | 0.212 | 0.061 | 3.48 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ8 | 0.37 | 0.106 | 3.49 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ8 | 0.732 | 0.239 | 3.06 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ8 | 0.937 | 0.321 | 2.92 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ8 | 1.456 | 0.484 | 3.01 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ2 | 0.051 | 0.03 | 1.70 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ2 | 0.098 | 0.054 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ2 | 0.188 | 0.104 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ2 | 0.234 | 0.15 | 1.56 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ2 | 0.332 | 0.199 | 1.67 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ4 | 0.099 | 0.038 | 2.61 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ4 | 0.188 | 0.07 | 2.69 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ4 | 0.332 | 0.136 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ4 | 0.418 | 0.2 | 2.09 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ4 | 0.647 | 0.265 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ8 | 0.188 | 0.039 | 4.82 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ8 | 0.332 | 0.065 | 5.11 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ8 | 0.647 | 0.126 | 5.13 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ8 | 0.83 | 0.185 | 4.49 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ8 | 1.29 | 0.245 | 5.27 |\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n* Generation attention now enforces causal masking during token\ngeneration.\n\n* **Performance / Refactor**\n* Improved kernel selection and on-demand loading for better performance\nand GPU compatibility.\n* Added finer-grained tuning parameters for tile/grouping,\ntokens-per-CTA and inflation to enable more optimal kernel choices.\n\n* **Chores**\n * Updated FMHA artifact paths and checksums.\n\n* **Tests**\n* Expanded parameterized tests to cover larger batch decoding scenarios.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review\nsettings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: yzh119 <zihaoy@nvidia.com>\nCo-authored-by: Zihao Ye <expye@outlook.com>"},"path":{"kind":"string","value":"csrc/trtllm_fmha_kernel_launcher.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <flashinfer/allocator.h>\n#include <flashinfer/exception.h>\n#include <flashinfer/trtllm/common.h>\n#include <flashinfer/trtllm/fmha/decoder_impl_common.h>\n#include <flashinfer/trtllm/fmha/fmhaRunnerParams.h>\n#include <nvrtc.h>\n#include <tvm/ffi/container/variant.h>\n\n#include <flashinfer/trtllm/fmha/fmhaRunner.cuh>\n#include <flashinfer/utils.cuh>\n#include <iostream>\n#include <sstream>\n#include <unordered_map>\n\n#include \"tvm/ffi/error.h\"\n#include \"tvm_ffi_utils.h\"\n\nusing tvm::ffi::Optional;\nusing tvm::ffi::Variant;\n\nnamespace flashinfer {\n\nenum class TllmPagedAttentionMode {\n Context,\n ForGen,\n};\n\n#include <memory>\n#include <mutex>\n\nclass TllmGenFmhaRunnerCache {\n public:\n using Key = std::tuple<Data_type, Data_type, Data_type>;\n\n static std::shared_ptr<TllmGenFmhaRunner> get(Data_type q_data_type, Data_type kv_data_type,\n Data_type o_data_type) {\n static std::unordered_map<Key, std::shared_ptr<TllmGenFmhaRunner>, KeyHash> cache;\n static std::mutex cache_mutex;\n Key key = std::make_tuple(q_data_type, kv_data_type, o_data_type);\n\n std::lock_guard<std::mutex> lock(cache_mutex);\n auto it = cache.find(key);\n if (it != cache.end()) {\n return it->second;\n } else {\n auto runner = std::make_shared<TllmGenFmhaRunner>(q_data_type, kv_data_type, o_data_type);\n cache.emplace(key, runner);\n return runner;\n }\n }\n\n private:\n struct KeyHash {\n std::size_t operator()(const Key& k) const {\n return std::hash<int>()(static_cast<int>(std::get<0>(k))) ^\n (std::hash<int>()(static_cast<int>(std::get<1>(k))) << 1) ^\n (std::hash<int>()(static_cast<int>(std::get<2>(k))) << 2);\n }\n };\n};\n\nvoid trtllm_paged_attention_launcher(\n void* out, void* out_scale_factor, void* query, void* key_cache, void* value_cache,\n void* workspace_buffer, int* block_tables, int* seq_lens, int* cum_seq_lens_q,\n int* cum_seq_lens_kv, float* attention_sinks, Data_type q_data_type, Data_type kv_data_type,\n Data_type o_data_type, TllmPagedAttentionMode mode, int64_t batch_size, int64_t max_q_len,\n int64_t max_kv_len, int64_t num_pages_in_mem_pool, int64_t num_qo_heads, int64_t num_kv_heads,\n int64_t head_dim_qk, int64_t head_dim_vo, int64_t page_size, int64_t q_stride_tokens,\n int64_t q_stride_heads, int64_t kv_stride_keys_values, int64_t kv_stride_heads,\n int64_t kv_stride_batch, int64_t max_num_blocks_per_seq, double bmm1_scale, double bmm2_scale,\n const float* bmm1_scale_log2_ptr, const float* bmm2_scale_ptr, double o_sf_scale,\n int64_t o_sf_vec_size, int64_t o_sf_start_index, int64_t window_left, int64_t sum_seq_q,\n int64_t sparse_mla_top_k, int64_t sm_count, bool enable_pdl, int64_t workspace_size,\n cudaStream_t stream) {\n if (num_qo_heads % num_kv_heads != 0) {\n std::ostringstream err_msg;\n err_msg << \"num_qo_heads must be a multiple of num_kv_heads, got num_kv_heads: \" << num_kv_heads\n << \" and num_qo_heads: \" << num_qo_heads;\n FLASHINFER_ERROR(err_msg.str());\n }\n\n auto fmha_runner = TllmGenFmhaRunnerCache::get(q_data_type, kv_data_type, o_data_type);\n TllmGenFmhaRunnerParams runner_params;\n\n // Common params\n runner_params.qPtr = query;\n runner_params.kPtr = key_cache;\n runner_params.vPtr = value_cache;\n runner_params.kvPageIdxPtr = block_tables;\n runner_params.seqLensKvPtr = seq_lens;\n runner_params.oPtr = out;\n runner_params.mHeadDimQk = head_dim_qk;\n runner_params.mHeadDimV = head_dim_vo;\n runner_params.mNumHeadsQ = num_qo_heads;\n runner_params.mNumHeadsKv = num_kv_heads;\n runner_params.mNumHeadsQPerKv = num_qo_heads / num_kv_heads;\n runner_params.mBatchSize = batch_size;\n runner_params.mMaxSeqLenKv = max_kv_len;\n runner_params.mMaxNumPagesPerSeqKv = max_num_blocks_per_seq;\n runner_params.mNumTokensPerPage = page_size;\n runner_params.mQkvLayout = QkvLayout::PagedKv;\n runner_params.mMultiProcessorCount = sm_count;\n runner_params.qStrideTokens = q_stride_tokens;\n runner_params.qStrideHeads = q_stride_heads;\n runner_params.kStrideKeysValues = kv_stride_keys_values;\n runner_params.kStrideHeads = kv_stride_heads;\n runner_params.kStrideBatch = kv_stride_batch;\n runner_params.vStrideKeysValues = kv_stride_keys_values;\n runner_params.vStrideHeads = kv_stride_heads;\n runner_params.vStrideBatch = kv_stride_batch;\n runner_params.mNumPagesInMemPool = num_pages_in_mem_pool;\n runner_params.stream = stream;\n // the scaleSoftmaxLog2Ptr and outputScalePtr have higher priority than the scaleSoftmaxLog2 and\n // outputScale. if they are not nullptr, then scaleSoftmaxLog2 and outputScale will be ignored\n runner_params.outputScale = bmm2_scale;\n runner_params.outputScalePtr = bmm2_scale_ptr;\n runner_params.scaleSoftmaxLog2 = bmm1_scale * M_LOG2E;\n runner_params.scaleSoftmaxLog2Ptr = bmm1_scale_log2_ptr;\n runner_params.oSfPtr = out_scale_factor;\n runner_params.mSfStartTokenIdx = o_sf_start_index;\n runner_params.mScaleSfO = o_sf_scale;\n TVM_FFI_ICHECK(o_sf_vec_size == 16 || o_sf_vec_size == -1)\n << \"Only support o_sf_vec_size == 16 or -1(not used)\";\n runner_params.mChunkedAttentionSize = INT_MAX; // disable chunked attention by INT_MAX\n runner_params.mAttentionWindowSize =\n window_left == -1 ? INT_MAX : window_left + 1; // disable window attention by INT_MAX\n runner_params.mMaxSeqLenQ = max_q_len;\n runner_params.mSumOfSeqLensQ = sum_seq_q;\n runner_params.ptrAttentionSinks = attention_sinks;\n runner_params.enable_pdl = enable_pdl;\n\n // The sparse MLA parameters.\n runner_params.mSparseMla = sparse_mla_top_k > 0;\n runner_params.mSparseMlaTopK = sparse_mla_top_k;\n TVM_FFI_ICHECK((head_dim_qk == 576 && head_dim_vo == 512) || sparse_mla_top_k <= 0)\n << \"Only decode MLA supports sparse MLA\";\n\n AlignedAllocator float_allocator(workspace_buffer, workspace_size);\n if (mode == TllmPagedAttentionMode::Context) {\n runner_params.mMaskType = TrtllmGenAttentionMaskType::Causal;\n runner_params.mKernelType = FmhaKernelType::Context;\n runner_params.mTileScheduler = TileScheduler::Persistent;\n runner_params.mMultiCtasKvMode = false;\n\n runner_params.cumSeqLensQPtr = cum_seq_lens_q;\n runner_params.cumSeqLensKvPtr = cum_seq_lens_kv;\n } else {\n // ForGen\n runner_params.mMaskType = TrtllmGenAttentionMaskType::Dense;\n runner_params.mKernelType = FmhaKernelType::Generation;\n bool use_multi_block = true;\n runner_params.mTileScheduler =\n use_multi_block ? TileScheduler::Static : TileScheduler::Persistent;\n runner_params.mMultiCtasKvMode = use_multi_block;\n\n runner_params.cumSeqLensQPtr = cum_seq_lens_q;\n runner_params.cumSeqLensKvPtr = nullptr;\n\n size_t max_batch_size = 8192; // todo(Yingyi): get from dlfw\n size_t max_num_qo_heads = 256; // todo(Yingyi): get from dlfw, in total 8MB\n size_t num_semaphores =\n round_up(max_batch_size * max_num_qo_heads, 8); // max 8MB, should align to 16 bytes\n // semaphores be at the first 8MB of workspace buffer: counter | scratch\n // todo(Yingyi): add softmax buffer later for lse return\n runner_params.multiCtasKvCounterPtr = float_allocator.aligned_alloc<int32_t>(\n num_semaphores * sizeof(uint32_t), 16, \"trtllm_gen_counter_workspace\");\n // scratch takes the rest of the workspace buffer\n runner_params.multiCtasKvScratchPtr =\n float_allocator.aligned_alloc<void>(0, 16, \"trtllm_gen_scratch_workspace\");\n }\n\n auto [foundKernels, kinfo] = fmha_runner->isSupportedWithInfo(runner_params);\n if (!foundKernels) {\n std::ostringstream err_msg;\n err_msg << \"Missing TRTLLM-GEN kernel (\"\n << (mode == TllmPagedAttentionMode::Context ? \"context\" : \"decode\") << \"): \" << kinfo;\n FLASHINFER_ERROR(err_msg.str());\n }\n\n fmha_runner->run(runner_params);\n}\n\ninline Data_type dl_dtype_to_tllm_data_type(const DLDataType dtype) {\n if (dtype == dl_float32) {\n return Data_type::DATA_TYPE_FP32;\n } else if (dtype == dl_float16) {\n return Data_type::DATA_TYPE_FP16;\n } else if (dtype == dl_bfloat16) {\n return Data_type::DATA_TYPE_BF16;\n } else if (dtype == dl_float8_e4m3fn) {\n return Data_type::DATA_TYPE_E4M3;\n } else if (dtype == dl_float8_e5m2) {\n return Data_type::DATA_TYPE_E5M2;\n } else if (dtype == dl_uint8) {\n // fp4 tensor is not supported in torch and use uint8_t as container.\n return Data_type::DATA_TYPE_E2M1;\n }\n return Data_type::DATA_TYPE_UNKNOWN;\n}\n\ninline bool is_4bit(Data_type data_type) { return data_type == Data_type::DATA_TYPE_E2M1; }\n\nvoid trtllm_paged_attention_decode(TensorView out, Optional<TensorView> out_scale_factor,\n TensorView query, TensorView key_cache, TensorView value_cache,\n TensorView workspace_buffer, TensorView block_tables,\n TensorView seq_lens, int64_t max_q_len, int64_t max_kv_len,\n Variant<double, ffi::Tensor> bmm1_scale,\n Variant<double, ffi::Tensor> bmm2_scale, double o_sf_scale,\n int64_t o_sf_vec_size, int64_t o_sf_start_index,\n int64_t batch_size, int64_t window_left,\n int64_t sparse_mla_top_k, int64_t sm_count, bool enable_pdl,\n int64_t workspace_size, Optional<TensorView> attention_sinks,\n Optional<TensorView> cum_seq_lens_q) {\n auto q_data_type = dl_dtype_to_tllm_data_type(query.dtype());\n auto kv_data_type = dl_dtype_to_tllm_data_type(key_cache.dtype());\n TVM_FFI_ICHECK_EQ(key_cache.ndim(), value_cache.ndim());\n for (int i = 0; i < key_cache.ndim(); i++) {\n TVM_FFI_ICHECK_EQ(key_cache.size(i), value_cache.size(i));\n }\n auto o_data_type = dl_dtype_to_tllm_data_type(out.dtype());\n int sum_seq_q = query.size(0);\n int num_qo_heads = query.size(1);\n // the cum_seq_lens_q is optional, and can be nullptr when all sequences have the same query\n // length\n int* cum_seq_lens_q_ptr =\n cum_seq_lens_q.has_value() ? static_cast<int*>(cum_seq_lens_q.value().data_ptr()) : nullptr;\n // Multiply by two for FP4 tensor as it is stored as UINT8 dtype. Assume the dim is even.\n int head_dim_k = is_4bit(kv_data_type) ? key_cache.size(-1) * 2 : key_cache.size(-1);\n int head_dim_q = is_4bit(q_data_type) ? query.size(-1) * 2 : query.size(-1);\n int head_dim_v = is_4bit(kv_data_type) ? value_cache.size(-1) * 2 : value_cache.size(-1);\n int head_dim_o = is_4bit(o_data_type) ? out.size(-1) * 2 : out.size(-1);\n TVM_FFI_ICHECK_EQ(head_dim_k, head_dim_q)\n << \"head_dim_k and head_dim_q must be the same, got \" << std::to_string(head_dim_k) << \" and \"\n << std::to_string(head_dim_q);\n TVM_FFI_ICHECK((head_dim_v == 576 && head_dim_o == 512) || head_dim_v == head_dim_o)\n << \"head_dim_v and head_dim_o must be the same for non-MLA attention, got \"\n << std::to_string(head_dim_v) << \" and \" << std::to_string(head_dim_o);\n int max_num_blocks_per_seq = block_tables.size(-1);\n bool is_shared_kv = key_cache.data_ptr() == value_cache.data_ptr();\n int num_pages_in_mem_pool = is_shared_kv ? key_cache.size(0) : key_cache.size(0) * 2;\n\n // Assume NHD layout: [..., H, N, D]\n int page_size = key_cache.size(-2);\n int num_kv_heads = key_cache.size(-3);\n int kv_stride_keys_values = key_cache.stride(-2); // key/values\n int kv_stride_heads = key_cache.stride(-3); // head\n int kv_stride_batch = key_cache.stride(0); // batch\n\n // Query stride: [num_tokens, num_heads, head_dim]\n int q_stride_tokens = query.stride(0); // stride between tokens\n int q_stride_heads = query.stride(1); // stride between heads\n\n const auto stream = get_stream(query.device());\n void* output_sf_ptr =\n out_scale_factor.has_value() ? out_scale_factor.value().data_ptr() : nullptr;\n\n float* attention_sinks_ptr = nullptr;\n if (attention_sinks.has_value()) {\n TVM_FFI_ICHECK_EQ(attention_sinks.value().dtype(), dl_float32)\n << \"attention_sinks must be a float tensor\";\n attention_sinks_ptr = static_cast<float*>(attention_sinks.value().data_ptr());\n }\n auto maybe_bmm1_scale_value = bmm1_scale.as<double>();\n auto maybe_bmm2_scale_value = bmm2_scale.as<double>();\n auto maybe_bmm1_scale_log2_tensor = bmm1_scale.as<ffi::Tensor>();\n auto maybe_bmm2_scale_tensor = bmm2_scale.as<ffi::Tensor>();\n TVM_FFI_CHECK(maybe_bmm1_scale_value.has_value() || maybe_bmm1_scale_log2_tensor.has_value(),\n \"bmm1_scale must be either a double or a tensor\");\n TVM_FFI_CHECK(maybe_bmm2_scale_value.has_value() || maybe_bmm2_scale_tensor.has_value(),\n \"bmm2_scale must be either a double or a tensor\");\n double bmm1_scale_value =\n maybe_bmm1_scale_value.has_value() ? maybe_bmm1_scale_value.value() : 1.0;\n double bmm2_scale_value =\n maybe_bmm2_scale_value.has_value() ? maybe_bmm2_scale_value.value() : 1.0;\n float* bmm1_scale_log2_ptr =\n maybe_bmm1_scale_log2_tensor.has_value()\n ? static_cast<float*>(maybe_bmm1_scale_log2_tensor.value().data_ptr())\n : nullptr;\n float* bmm2_scale_ptr = maybe_bmm2_scale_tensor.has_value()\n ? static_cast<float*>(maybe_bmm2_scale_tensor.value().data_ptr())\n : nullptr;\n trtllm_paged_attention_launcher(\n out.data_ptr(), output_sf_ptr, query.data_ptr(), key_cache.data_ptr(), value_cache.data_ptr(),\n workspace_buffer.data_ptr(), static_cast<int*>(block_tables.data_ptr()),\n static_cast<int*>(seq_lens.data_ptr()), cum_seq_lens_q_ptr,\n /*cum_seq_lens_kv*/ nullptr, attention_sinks_ptr, q_data_type, kv_data_type, o_data_type,\n TllmPagedAttentionMode::ForGen, batch_size, max_q_len, max_kv_len, num_pages_in_mem_pool,\n num_qo_heads, num_kv_heads, head_dim_q, head_dim_o, page_size, q_stride_tokens,\n q_stride_heads, kv_stride_keys_values, kv_stride_heads, kv_stride_batch,\n max_num_blocks_per_seq, bmm1_scale_value, bmm2_scale_value, bmm1_scale_log2_ptr,\n bmm2_scale_ptr, o_sf_scale, o_sf_vec_size, o_sf_start_index, window_left, sum_seq_q,\n sparse_mla_top_k, sm_count, enable_pdl, workspace_size, stream);\n}\n\nvoid trtllm_paged_attention_context(\n TensorView out, Optional<TensorView> out_scale_factor, TensorView query, TensorView key_cache,\n TensorView value_cache, TensorView workspace_buffer, TensorView block_tables,\n TensorView seq_lens, int64_t max_q_len, int64_t max_kv_len,\n Variant<double, ffi::Tensor> bmm1_scale, Variant<double, ffi::Tensor> bmm2_scale,\n double o_sf_scale, int64_t o_sf_vec_size, int64_t o_sf_start_index, int64_t batch_size,\n int64_t window_left, TensorView cum_seq_lens_q, TensorView cum_seq_lens_kv, int64_t sm_count,\n bool enable_pdl, int64_t workspace_size, Optional<TensorView> attention_sinks) {\n auto q_data_type = dl_dtype_to_tllm_data_type(query.dtype());\n auto kv_data_type = dl_dtype_to_tllm_data_type(key_cache.dtype());\n auto o_data_type = dl_dtype_to_tllm_data_type(out.dtype());\n int num_qo_heads = query.size(1);\n int sum_seq_q = query.size(0);\n // Multiply by two for FP4 tensor as it is stored as UINT8 dtype. Assume the dim is even.\n int head_dim_k = is_4bit(kv_data_type) ? key_cache.size(-1) * 2 : key_cache.size(-1);\n int head_dim_q = is_4bit(q_data_type) ? query.size(-1) * 2 : query.size(-1);\n int head_dim_v = is_4bit(kv_data_type) ? value_cache.size(-1) * 2 : value_cache.size(-1);\n int head_dim_o = is_4bit(o_data_type) ? out.size(-1) * 2 : out.size(-1);\n TVM_FFI_ICHECK_EQ(head_dim_k, head_dim_q)\n << \"head_dim_k and head_dim_q must be the same, got \" << std::to_string(head_dim_k) << \" and \"\n << std::to_string(head_dim_q);\n TVM_FFI_ICHECK_EQ(head_dim_v, head_dim_o)\n << \"head_dim_v and head_dim_o must be the same, got \" << std::to_string(head_dim_v) << \" and \"\n << std::to_string(head_dim_o);\n int max_num_blocks_per_seq = block_tables.size(-1);\n bool is_shared_kv = key_cache.data_ptr() == value_cache.data_ptr();\n int num_pages_in_mem_pool = is_shared_kv ? key_cache.size(0) : key_cache.size(0) * 2;\n\n // Assume NHD layout: [..., H, N, D]\n int page_size = key_cache.size(-2);\n int num_kv_heads = key_cache.size(-3);\n int kv_stride_keys_values = key_cache.stride(-2); // key/values\n int kv_stride_heads = key_cache.stride(-3); // head\n int kv_stride_batch = key_cache.stride(0); // batch\n\n // Query stride: [num_tokens, num_heads, head_dim]\n int q_stride_tokens = query.stride(0); // stride between tokens\n int q_stride_heads = query.stride(1); // stride between heads\n\n const auto stream = get_stream(query.device());\n void* output_sf_ptr =\n out_scale_factor.has_value() ? out_scale_factor.value().data_ptr() : nullptr;\n\n float* attention_sinks_ptr = nullptr;\n if (attention_sinks.has_value()) {\n TVM_FFI_ICHECK_EQ(attention_sinks.value().dtype(), dl_float32)\n << \"attention_sinks must be a float tensor\";\n attention_sinks_ptr = static_cast<float*>(attention_sinks.value().data_ptr());\n }\n\n auto maybe_bmm1_scale_value = bmm1_scale.as<double>();\n auto maybe_bmm2_scale_value = bmm2_scale.as<double>();\n auto maybe_bmm1_scale_log2_tensor = bmm1_scale.as<ffi::Tensor>();\n auto maybe_bmm2_scale_tensor = bmm2_scale.as<ffi::Tensor>();\n TVM_FFI_CHECK(maybe_bmm1_scale_value.has_value() || maybe_bmm1_scale_log2_tensor.has_value(),\n \"bmm1_scale must be either a double or a tensor\");\n TVM_FFI_CHECK(maybe_bmm2_scale_value.has_value() || maybe_bmm2_scale_tensor.has_value(),\n \"bmm2_scale must be either a double or a tensor\");\n double bmm1_scale_value =\n maybe_bmm1_scale_value.has_value() ? maybe_bmm1_scale_value.value() : 1.0;\n double bmm2_scale_value =\n maybe_bmm2_scale_value.has_value() ? maybe_bmm2_scale_value.value() : 1.0;\n float* bmm1_scale_log2_ptr =\n maybe_bmm1_scale_log2_tensor.has_value()\n ? static_cast<float*>(maybe_bmm1_scale_log2_tensor.value().data_ptr())\n : nullptr;\n float* bmm2_scale_ptr = maybe_bmm2_scale_tensor.has_value()\n ? static_cast<float*>(maybe_bmm2_scale_tensor.value().data_ptr())\n : nullptr;\n\n trtllm_paged_attention_launcher(\n out.data_ptr(), output_sf_ptr, query.data_ptr(), key_cache.data_ptr(), value_cache.data_ptr(),\n workspace_buffer.data_ptr(), static_cast<int*>(block_tables.data_ptr()),\n static_cast<int*>(seq_lens.data_ptr()),\n /*cum_seq_lens_q=*/static_cast<int*>(cum_seq_lens_q.data_ptr()),\n /*cum_seq_lens_kv=*/static_cast<int*>(cum_seq_lens_kv.data_ptr()), attention_sinks_ptr,\n q_data_type, kv_data_type, o_data_type, TllmPagedAttentionMode::Context, batch_size,\n max_q_len, max_kv_len, num_pages_in_mem_pool, num_qo_heads, num_kv_heads, head_dim_q,\n head_dim_o, page_size, q_stride_tokens, q_stride_heads, kv_stride_keys_values,\n kv_stride_heads, kv_stride_batch, max_num_blocks_per_seq, bmm1_scale_value, bmm2_scale_value,\n bmm1_scale_log2_ptr, bmm2_scale_ptr, o_sf_scale, o_sf_vec_size, o_sf_start_index, window_left,\n sum_seq_q, /*sparse_mla_top_k=*/0, sm_count, enable_pdl, workspace_size, stream);\n}\n\nvoid trtllm_ragged_attention_launcher(\n void* out, void* query, void* key, void* value, void* workspace_buffer, int* seq_lens,\n int* cum_seq_lens_q, int* cum_seq_lens_kv, float* attention_sinks, float* lse,\n Data_type q_data_type, Data_type kv_data_type, Data_type o_data_type, int64_t max_q_len,\n int64_t max_kv_len, int64_t num_qo_heads, int64_t num_kv_heads, int64_t head_dim_qk,\n int64_t head_dim_v, int64_t sum_seq_q, int64_t sum_seq_kv, double bmm1_scale, double bmm2_scale,\n const float* bmm1_scale_log2_ptr, const float* bmm2_scale_ptr, double o_sf_scale,\n int64_t batch_size, int64_t window_left, int64_t sm_count, bool enable_pdl, bool is_causal,\n int64_t k_stride_keys_values, int64_t k_stride_heads, int64_t k_stride_batch,\n int64_t v_stride_keys_values, int64_t v_stride_heads, int64_t v_stride_batch,\n int64_t workspace_size, cudaStream_t stream) {\n if (num_qo_heads % num_kv_heads != 0) {\n std::ostringstream err_msg;\n err_msg << \"num_qo_heads must be a multiple of num_kv_heads, got num_kv_heads: \" << num_kv_heads\n << \" and num_qo_heads: \" << num_qo_heads;\n FLASHINFER_ERROR(err_msg.str());\n }\n auto fmha_runner = TllmGenFmhaRunnerCache::get(q_data_type, kv_data_type, o_data_type);\n TllmGenFmhaRunnerParams runner_params;\n\n runner_params.qPtr = query;\n runner_params.kPtr = key;\n runner_params.vPtr = value;\n runner_params.kvPageIdxPtr = nullptr;\n runner_params.seqLensKvPtr = seq_lens;\n runner_params.oPtr = out;\n runner_params.mHeadDimQk = head_dim_qk;\n runner_params.mHeadDimV = head_dim_v;\n runner_params.mNumHeadsQ = num_qo_heads;\n runner_params.mNumHeadsKv = num_kv_heads;\n runner_params.mNumHeadsQPerKv = num_qo_heads / num_kv_heads;\n runner_params.mBatchSize = batch_size;\n runner_params.mMaxSeqLenKv = max_kv_len;\n runner_params.mQkvLayout = QkvLayout::SeparateQkv;\n runner_params.mMultiProcessorCount = sm_count;\n runner_params.stream = stream;\n // the scaleSoftmaxLog2Ptr and outputScalePtr have higher priority than the scaleSoftmaxLog2 and\n // outputScale. if they are not nullptr, then scaleSoftmaxLog2 and outputScale will be ignored\n runner_params.outputScale = bmm2_scale;\n runner_params.outputScalePtr = bmm2_scale_ptr;\n runner_params.scaleSoftmaxLog2 = bmm1_scale * M_LOG2E;\n runner_params.scaleSoftmaxLog2Ptr = bmm1_scale_log2_ptr;\n runner_params.mScaleSfO = o_sf_scale;\n runner_params.mChunkedAttentionSize = INT_MAX; // disable chunked attention by INT_MAX\n runner_params.mAttentionWindowSize =\n window_left == -1 ? INT_MAX : window_left + 1; // disable window attention by INT_MAX\n runner_params.mMaxSeqLenQ = max_q_len;\n runner_params.mSumOfSeqLensQ = sum_seq_q;\n runner_params.mSumOfSeqLensKv = sum_seq_kv;\n runner_params.cumSeqLensKvPtr = cum_seq_lens_kv;\n runner_params.cumSeqLensQPtr = cum_seq_lens_q;\n runner_params.ptrAttentionSinks = attention_sinks;\n runner_params.enable_pdl = enable_pdl;\n\n runner_params.kStrideKeysValues = k_stride_keys_values;\n runner_params.kStrideHeads = k_stride_heads;\n runner_params.kStrideBatch = k_stride_batch;\n runner_params.vStrideKeysValues = v_stride_keys_values;\n runner_params.vStrideHeads = v_stride_heads;\n runner_params.vStrideBatch = v_stride_batch;\n\n runner_params.mKernelType = FmhaKernelType::Context;\n runner_params.mTileScheduler = TileScheduler::Persistent;\n runner_params.mMaskType =\n is_causal ? TrtllmGenAttentionMaskType::Causal : TrtllmGenAttentionMaskType::Dense;\n runner_params.lsePtr = lse;\n\n AlignedAllocator float_allocator(workspace_buffer, workspace_size);\n size_t max_batch_size = 8192;\n size_t max_num_qo_heads = 256;\n size_t num_semaphores =\n round_up(max_batch_size * max_num_qo_heads, 8); // max 8MB, should align to 16 bytes\n // semaphores be at the first 8MB of workspace buffer: counter | softmax | scratch\n runner_params.multiCtasKvCounterPtr = float_allocator.aligned_alloc<int32_t>(\n num_semaphores * sizeof(uint32_t), 16, \"trtllm_gen_counter_workspace\");\n runner_params.softmaxStatsPtr = float_allocator.aligned_alloc<float2>(\n sizeof(float2) * num_qo_heads * runner_params.mSumOfSeqLensQ, 16,\n \"trtllm_gen_softmax_workspace\");\n // scratch takes the rest of the workspace buffer\n runner_params.multiCtasKvScratchPtr =\n float_allocator.aligned_alloc<void>(0, 16, \"trtllm_gen_scratch_workspace\");\n\n auto [foundKernels, kinfo] = fmha_runner->isSupportedWithInfo(runner_params);\n if (!foundKernels) {\n std::ostringstream err_msg;\n err_msg << \"Missing TRTLLM-GEN kernel ragged attention: \" << kinfo;\n FLASHINFER_ERROR(err_msg.str());\n }\n\n fmha_runner->run(runner_params);\n}\n\nvoid trtllm_ragged_attention(TensorView out, TensorView query, TensorView key, TensorView value,\n TensorView workspace_buffer, TensorView seq_lens, int64_t max_q_len,\n int64_t max_kv_len, Variant<double, ffi::Tensor> bmm1_scale,\n Variant<double, ffi::Tensor> bmm2_scale, double o_sf_scale,\n int64_t batch_size, int64_t window_left, TensorView cum_seq_lens_q,\n TensorView cum_seq_lens_kv, int64_t sm_count, bool enable_pdl,\n bool is_causal, int64_t workspace_size,\n Optional<TensorView> attention_sinks, Optional<TensorView> lse) {\n float* attention_sinks_ptr = nullptr;\n if (attention_sinks.has_value()) {\n TVM_FFI_ICHECK_EQ(attention_sinks.value().dtype(), dl_float32)\n << \"attention_sinks must be a float tensor\";\n attention_sinks_ptr = static_cast<float*>(attention_sinks.value().data_ptr());\n }\n float* lse_ptr = nullptr;\n if (lse.has_value()) {\n TVM_FFI_ICHECK_EQ(lse.value().dtype(), dl_float32) << \"lse must be a float tensor\";\n lse_ptr = static_cast<float*>(lse.value().data_ptr());\n }\n TVM_FFI_ICHECK_EQ(out.ndim(), 3) << \"out must be a 3D tensor\";\n TVM_FFI_ICHECK_EQ(query.ndim(), 3) << \"query must be a 3D tensor\";\n TVM_FFI_ICHECK_EQ(key.ndim(), 3) << \"key must be a 3D tensor\";\n TVM_FFI_ICHECK_EQ(value.ndim(), 3) << \"value must be a 3D tensor\";\n\n auto q_data_type = dl_dtype_to_tllm_data_type(query.dtype());\n auto kv_data_type = dl_dtype_to_tllm_data_type(key.dtype());\n auto o_data_type = dl_dtype_to_tllm_data_type(out.dtype());\n const auto stream = get_stream(query.device());\n int num_qo_heads = query.size(1);\n int num_kv_heads = key.size(1);\n int sum_seq_q = query.size(0);\n int sum_seq_kv = key.size(0);\n int head_dim_qk = query.size(2);\n int head_dim_v = value.size(2);\n int k_stride_keys_values = key.stride(0);\n int k_stride_heads = key.stride(1);\n int k_stride_batch = key.numel();\n int v_stride_keys_values = value.stride(0);\n int v_stride_heads = value.stride(1);\n int v_stride_batch = value.numel();\n\n auto maybe_bmm1_scale_value = bmm1_scale.as<double>();\n auto maybe_bmm2_scale_value = bmm2_scale.as<double>();\n auto maybe_bmm1_scale_log2_tensor = bmm1_scale.as<ffi::Tensor>();\n auto maybe_bmm2_scale_tensor = bmm2_scale.as<ffi::Tensor>();\n TVM_FFI_CHECK(maybe_bmm1_scale_value.has_value() || maybe_bmm1_scale_log2_tensor.has_value(),\n \"bmm1_scale must be either a double or a tensor\");\n TVM_FFI_CHECK(maybe_bmm2_scale_value.has_value() || maybe_bmm2_scale_tensor.has_value(),\n \"bmm2_scale must be either a double or a tensor\");\n double bmm1_scale_value =\n maybe_bmm1_scale_value.has_value() ? maybe_bmm1_scale_value.value() : 1.0;\n double bmm2_scale_value =\n maybe_bmm2_scale_value.has_value() ? maybe_bmm2_scale_value.value() : 1.0;\n float* bmm1_scale_log2_ptr =\n maybe_bmm1_scale_log2_tensor.has_value()\n ? static_cast<float*>(maybe_bmm1_scale_log2_tensor.value().data_ptr())\n : nullptr;\n float* bmm2_scale_ptr = maybe_bmm2_scale_tensor.has_value()\n ? static_cast<float*>(maybe_bmm2_scale_tensor.value().data_ptr())\n : nullptr;\n trtllm_ragged_attention_launcher(\n out.data_ptr(), query.data_ptr(), key.data_ptr(), value.data_ptr(),\n workspace_buffer.data_ptr(), static_cast<int*>(seq_lens.data_ptr()),\n static_cast<int*>(cum_seq_lens_q.data_ptr()), static_cast<int*>(cum_seq_lens_kv.data_ptr()),\n attention_sinks_ptr, lse_ptr, q_data_type, kv_data_type, o_data_type, max_q_len, max_kv_len,\n num_qo_heads, num_kv_heads, head_dim_qk, head_dim_v, sum_seq_q, sum_seq_kv, bmm1_scale_value,\n bmm2_scale_value, bmm1_scale_log2_ptr, bmm2_scale_ptr, o_sf_scale, batch_size, window_left,\n sm_count, enable_pdl, is_causal, k_stride_keys_values, k_stride_heads, k_stride_batch,\n v_stride_keys_values, v_stride_heads, v_stride_batch, workspace_size, stream);\n}\n\nnamespace trtllm_cubin_loader {\n#include <flashinfer/cubin_loader.h>\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_paged_attention_decode, trtllm_paged_attention_decode);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_paged_attention_context, trtllm_paged_attention_context);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_ragged_attention, trtllm_ragged_attention);\n\n} // namespace flashinfer\n"},"after_code":{"kind":"string","value":"/*\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <flashinfer/allocator.h>\n#include <flashinfer/exception.h>\n#include <flashinfer/trtllm/common.h>\n#include <flashinfer/trtllm/fmha/decoder_impl_common.h>\n#include <flashinfer/trtllm/fmha/fmhaRunnerParams.h>\n#include <nvrtc.h>\n#include <tvm/ffi/container/variant.h>\n\n#include <flashinfer/trtllm/fmha/fmhaRunner.cuh>\n#include <flashinfer/utils.cuh>\n#include <iostream>\n#include <sstream>\n#include <unordered_map>\n\n#include \"tvm/ffi/error.h\"\n#include \"tvm_ffi_utils.h\"\n\nusing tvm::ffi::Optional;\nusing tvm::ffi::Variant;\n\nnamespace flashinfer {\n\nenum class TllmPagedAttentionMode {\n Context,\n ForGen,\n};\n\n#include <memory>\n#include <mutex>\n\nclass TllmGenFmhaRunnerCache {\n public:\n using Key = std::tuple<Data_type, Data_type, Data_type>;\n\n static std::shared_ptr<TllmGenFmhaRunner> get(Data_type q_data_type, Data_type kv_data_type,\n Data_type o_data_type) {\n static std::unordered_map<Key, std::shared_ptr<TllmGenFmhaRunner>, KeyHash> cache;\n static std::mutex cache_mutex;\n Key key = std::make_tuple(q_data_type, kv_data_type, o_data_type);\n\n std::lock_guard<std::mutex> lock(cache_mutex);\n auto it = cache.find(key);\n if (it != cache.end()) {\n return it->second;\n } else {\n auto runner = std::make_shared<TllmGenFmhaRunner>(q_data_type, kv_data_type, o_data_type);\n cache.emplace(key, runner);\n return runner;\n }\n }\n\n private:\n struct KeyHash {\n std::size_t operator()(const Key& k) const {\n return std::hash<int>()(static_cast<int>(std::get<0>(k))) ^\n (std::hash<int>()(static_cast<int>(std::get<1>(k))) << 1) ^\n (std::hash<int>()(static_cast<int>(std::get<2>(k))) << 2);\n }\n };\n};\n\nvoid trtllm_paged_attention_launcher(\n void* out, void* out_scale_factor, void* query, void* key_cache, void* value_cache,\n void* workspace_buffer, int* block_tables, int* seq_lens, int* cum_seq_lens_q,\n int* cum_seq_lens_kv, float* attention_sinks, Data_type q_data_type, Data_type kv_data_type,\n Data_type o_data_type, TllmPagedAttentionMode mode, int64_t batch_size, int64_t max_q_len,\n int64_t max_kv_len, int64_t num_pages_in_mem_pool, int64_t num_qo_heads, int64_t num_kv_heads,\n int64_t head_dim_qk, int64_t head_dim_vo, int64_t page_size, int64_t q_stride_tokens,\n int64_t q_stride_heads, int64_t kv_stride_keys_values, int64_t kv_stride_heads,\n int64_t kv_stride_batch, int64_t max_num_blocks_per_seq, double bmm1_scale, double bmm2_scale,\n const float* bmm1_scale_log2_ptr, const float* bmm2_scale_ptr, double o_sf_scale,\n int64_t o_sf_vec_size, int64_t o_sf_start_index, int64_t window_left, int64_t sum_seq_q,\n int64_t sparse_mla_top_k, int64_t sm_count, bool enable_pdl, int64_t workspace_size,\n cudaStream_t stream) {\n if (num_qo_heads % num_kv_heads != 0) {\n std::ostringstream err_msg;\n err_msg << \"num_qo_heads must be a multiple of num_kv_heads, got num_kv_heads: \" << num_kv_heads\n << \" and num_qo_heads: \" << num_qo_heads;\n FLASHINFER_ERROR(err_msg.str());\n }\n\n auto fmha_runner = TllmGenFmhaRunnerCache::get(q_data_type, kv_data_type, o_data_type);\n TllmGenFmhaRunnerParams runner_params;\n\n // Common params\n runner_params.qPtr = query;\n runner_params.kPtr = key_cache;\n runner_params.vPtr = value_cache;\n runner_params.kvPageIdxPtr = block_tables;\n runner_params.seqLensKvPtr = seq_lens;\n runner_params.oPtr = out;\n runner_params.mHeadDimQk = head_dim_qk;\n runner_params.mHeadDimV = head_dim_vo;\n runner_params.mNumHeadsQ = num_qo_heads;\n runner_params.mNumHeadsKv = num_kv_heads;\n runner_params.mNumHeadsQPerKv = num_qo_heads / num_kv_heads;\n runner_params.mBatchSize = batch_size;\n runner_params.mMaxSeqLenKv = max_kv_len;\n runner_params.mMaxNumPagesPerSeqKv = max_num_blocks_per_seq;\n runner_params.mNumTokensPerPage = page_size;\n runner_params.mQkvLayout = QkvLayout::PagedKv;\n runner_params.mMultiProcessorCount = sm_count;\n runner_params.qStrideTokens = q_stride_tokens;\n runner_params.qStrideHeads = q_stride_heads;\n runner_params.kStrideKeysValues = kv_stride_keys_values;\n runner_params.kStrideHeads = kv_stride_heads;\n runner_params.kStrideBatch = kv_stride_batch;\n runner_params.vStrideKeysValues = kv_stride_keys_values;\n runner_params.vStrideHeads = kv_stride_heads;\n runner_params.vStrideBatch = kv_stride_batch;\n runner_params.mNumPagesInMemPool = num_pages_in_mem_pool;\n runner_params.stream = stream;\n // the scaleSoftmaxLog2Ptr and outputScalePtr have higher priority than the scaleSoftmaxLog2 and\n // outputScale. if they are not nullptr, then scaleSoftmaxLog2 and outputScale will be ignored\n runner_params.outputScale = bmm2_scale;\n runner_params.outputScalePtr = bmm2_scale_ptr;\n runner_params.scaleSoftmaxLog2 = bmm1_scale * M_LOG2E;\n runner_params.scaleSoftmaxLog2Ptr = bmm1_scale_log2_ptr;\n runner_params.oSfPtr = out_scale_factor;\n runner_params.mSfStartTokenIdx = o_sf_start_index;\n runner_params.mScaleSfO = o_sf_scale;\n TVM_FFI_ICHECK(o_sf_vec_size == 16 || o_sf_vec_size == -1)\n << \"Only support o_sf_vec_size == 16 or -1(not used)\";\n runner_params.mChunkedAttentionSize = INT_MAX; // disable chunked attention by INT_MAX\n runner_params.mAttentionWindowSize =\n window_left == -1 ? INT_MAX : window_left + 1; // disable window attention by INT_MAX\n runner_params.mMaxSeqLenQ = max_q_len;\n runner_params.mSumOfSeqLensQ = sum_seq_q;\n runner_params.ptrAttentionSinks = attention_sinks;\n runner_params.enable_pdl = enable_pdl;\n\n // The sparse MLA parameters.\n runner_params.mSparseMla = sparse_mla_top_k > 0;\n runner_params.mSparseMlaTopK = sparse_mla_top_k;\n TVM_FFI_ICHECK((head_dim_qk == 576 && head_dim_vo == 512) || sparse_mla_top_k <= 0)\n << \"Only decode MLA supports sparse MLA\";\n\n AlignedAllocator float_allocator(workspace_buffer, workspace_size);\n if (mode == TllmPagedAttentionMode::Context) {\n runner_params.mMaskType = TrtllmGenAttentionMaskType::Causal;\n runner_params.mKernelType = FmhaKernelType::Context;\n runner_params.mTileScheduler = TileScheduler::Persistent;\n runner_params.mMultiCtasKvMode = false;\n\n runner_params.cumSeqLensQPtr = cum_seq_lens_q;\n runner_params.cumSeqLensKvPtr = cum_seq_lens_kv;\n } else {\n // Generation.\n // Note that kernel names are still labeled as using a dense mask even when maskType is\n // specified as causal, this is expected for better performance as each CTA will only process\n // one tokenQ in those cases, so dense mask works the same as causal mask.\n runner_params.mMaskType = TrtllmGenAttentionMaskType::Causal;\n runner_params.mKernelType = FmhaKernelType::Generation;\n bool use_multi_block = true;\n runner_params.mTileScheduler =\n use_multi_block ? TileScheduler::Static : TileScheduler::Persistent;\n runner_params.mMultiCtasKvMode = use_multi_block;\n\n runner_params.cumSeqLensQPtr = cum_seq_lens_q;\n runner_params.cumSeqLensKvPtr = nullptr;\n\n size_t max_batch_size = 8192; // todo(Yingyi): get from dlfw\n size_t max_num_qo_heads = 256; // todo(Yingyi): get from dlfw, in total 8MB\n size_t num_semaphores =\n round_up(max_batch_size * max_num_qo_heads, 8); // max 8MB, should align to 16 bytes\n // semaphores be at the first 8MB of workspace buffer: counter | scratch\n // todo(Yingyi): add softmax buffer later for lse return\n runner_params.multiCtasKvCounterPtr = float_allocator.aligned_alloc<int32_t>(\n num_semaphores * sizeof(uint32_t), 16, \"trtllm_gen_counter_workspace\");\n // scratch takes the rest of the workspace buffer\n runner_params.multiCtasKvScratchPtr =\n float_allocator.aligned_alloc<void>(0, 16, \"trtllm_gen_scratch_workspace\");\n }\n\n auto [foundKernels, kinfo] = fmha_runner->isSupportedWithInfo(runner_params);\n if (!foundKernels) {\n std::ostringstream err_msg;\n err_msg << \"Missing TRTLLM-GEN kernel (\"\n << (mode == TllmPagedAttentionMode::Context ? \"context\" : \"decode\") << \"): \" << kinfo;\n FLASHINFER_ERROR(err_msg.str());\n }\n\n fmha_runner->run(runner_params);\n}\n\ninline Data_type dl_dtype_to_tllm_data_type(const DLDataType dtype) {\n if (dtype == dl_float32) {\n return Data_type::DATA_TYPE_FP32;\n } else if (dtype == dl_float16) {\n return Data_type::DATA_TYPE_FP16;\n } else if (dtype == dl_bfloat16) {\n return Data_type::DATA_TYPE_BF16;\n } else if (dtype == dl_float8_e4m3fn) {\n return Data_type::DATA_TYPE_E4M3;\n } else if (dtype == dl_float8_e5m2) {\n return Data_type::DATA_TYPE_E5M2;\n } else if (dtype == dl_uint8) {\n // fp4 tensor is not supported in torch and use uint8_t as container.\n return Data_type::DATA_TYPE_E2M1;\n }\n return Data_type::DATA_TYPE_UNKNOWN;\n}\n\ninline bool is_4bit(Data_type data_type) { return data_type == Data_type::DATA_TYPE_E2M1; }\n\nvoid trtllm_paged_attention_decode(TensorView out, Optional<TensorView> out_scale_factor,\n TensorView query, TensorView key_cache, TensorView value_cache,\n TensorView workspace_buffer, TensorView block_tables,\n TensorView seq_lens, int64_t max_q_len, int64_t max_kv_len,\n Variant<double, ffi::Tensor> bmm1_scale,\n Variant<double, ffi::Tensor> bmm2_scale, double o_sf_scale,\n int64_t o_sf_vec_size, int64_t o_sf_start_index,\n int64_t batch_size, int64_t window_left,\n int64_t sparse_mla_top_k, int64_t sm_count, bool enable_pdl,\n int64_t workspace_size, Optional<TensorView> attention_sinks,\n Optional<TensorView> cum_seq_lens_q) {\n auto q_data_type = dl_dtype_to_tllm_data_type(query.dtype());\n auto kv_data_type = dl_dtype_to_tllm_data_type(key_cache.dtype());\n TVM_FFI_ICHECK_EQ(key_cache.ndim(), value_cache.ndim());\n for (int i = 0; i < key_cache.ndim(); i++) {\n TVM_FFI_ICHECK_EQ(key_cache.size(i), value_cache.size(i));\n }\n auto o_data_type = dl_dtype_to_tllm_data_type(out.dtype());\n int sum_seq_q = query.size(0);\n int num_qo_heads = query.size(1);\n // the cum_seq_lens_q is optional, and can be nullptr when all sequences have the same query\n // length\n int* cum_seq_lens_q_ptr =\n cum_seq_lens_q.has_value() ? static_cast<int*>(cum_seq_lens_q.value().data_ptr()) : nullptr;\n // Multiply by two for FP4 tensor as it is stored as UINT8 dtype. Assume the dim is even.\n int head_dim_k = is_4bit(kv_data_type) ? key_cache.size(-1) * 2 : key_cache.size(-1);\n int head_dim_q = is_4bit(q_data_type) ? query.size(-1) * 2 : query.size(-1);\n int head_dim_v = is_4bit(kv_data_type) ? value_cache.size(-1) * 2 : value_cache.size(-1);\n int head_dim_o = is_4bit(o_data_type) ? out.size(-1) * 2 : out.size(-1);\n TVM_FFI_ICHECK_EQ(head_dim_k, head_dim_q)\n << \"head_dim_k and head_dim_q must be the same, got \" << std::to_string(head_dim_k) << \" and \"\n << std::to_string(head_dim_q);\n TVM_FFI_ICHECK((head_dim_v == 576 && head_dim_o == 512) || head_dim_v == head_dim_o)\n << \"head_dim_v and head_dim_o must be the same for non-MLA attention, got \"\n << std::to_string(head_dim_v) << \" and \" << std::to_string(head_dim_o);\n int max_num_blocks_per_seq = block_tables.size(-1);\n bool is_shared_kv = key_cache.data_ptr() == value_cache.data_ptr();\n int num_pages_in_mem_pool = is_shared_kv ? key_cache.size(0) : key_cache.size(0) * 2;\n\n // Assume NHD layout: [..., H, N, D]\n int page_size = key_cache.size(-2);\n int num_kv_heads = key_cache.size(-3);\n int kv_stride_keys_values = key_cache.stride(-2); // key/values\n int kv_stride_heads = key_cache.stride(-3); // head\n int kv_stride_batch = key_cache.stride(0); // batch\n\n // Query stride: [num_tokens, num_heads, head_dim]\n int q_stride_tokens = query.stride(0); // stride between tokens\n int q_stride_heads = query.stride(1); // stride between heads\n\n const auto stream = get_stream(query.device());\n void* output_sf_ptr =\n out_scale_factor.has_value() ? out_scale_factor.value().data_ptr() : nullptr;\n\n float* attention_sinks_ptr = nullptr;\n if (attention_sinks.has_value()) {\n TVM_FFI_ICHECK_EQ(attention_sinks.value().dtype(), dl_float32)\n << \"attention_sinks must be a float tensor\";\n attention_sinks_ptr = static_cast<float*>(attention_sinks.value().data_ptr());\n }\n auto maybe_bmm1_scale_value = bmm1_scale.as<double>();\n auto maybe_bmm2_scale_value = bmm2_scale.as<double>();\n auto maybe_bmm1_scale_log2_tensor = bmm1_scale.as<ffi::Tensor>();\n auto maybe_bmm2_scale_tensor = bmm2_scale.as<ffi::Tensor>();\n TVM_FFI_CHECK(maybe_bmm1_scale_value.has_value() || maybe_bmm1_scale_log2_tensor.has_value(),\n \"bmm1_scale must be either a double or a tensor\");\n TVM_FFI_CHECK(maybe_bmm2_scale_value.has_value() || maybe_bmm2_scale_tensor.has_value(),\n \"bmm2_scale must be either a double or a tensor\");\n double bmm1_scale_value =\n maybe_bmm1_scale_value.has_value() ? maybe_bmm1_scale_value.value() : 1.0;\n double bmm2_scale_value =\n maybe_bmm2_scale_value.has_value() ? maybe_bmm2_scale_value.value() : 1.0;\n float* bmm1_scale_log2_ptr =\n maybe_bmm1_scale_log2_tensor.has_value()\n ? static_cast<float*>(maybe_bmm1_scale_log2_tensor.value().data_ptr())\n : nullptr;\n float* bmm2_scale_ptr = maybe_bmm2_scale_tensor.has_value()\n ? static_cast<float*>(maybe_bmm2_scale_tensor.value().data_ptr())\n : nullptr;\n trtllm_paged_attention_launcher(\n out.data_ptr(), output_sf_ptr, query.data_ptr(), key_cache.data_ptr(), value_cache.data_ptr(),\n workspace_buffer.data_ptr(), static_cast<int*>(block_tables.data_ptr()),\n static_cast<int*>(seq_lens.data_ptr()), cum_seq_lens_q_ptr,\n /*cum_seq_lens_kv*/ nullptr, attention_sinks_ptr, q_data_type, kv_data_type, o_data_type,\n TllmPagedAttentionMode::ForGen, batch_size, max_q_len, max_kv_len, num_pages_in_mem_pool,\n num_qo_heads, num_kv_heads, head_dim_q, head_dim_o, page_size, q_stride_tokens,\n q_stride_heads, kv_stride_keys_values, kv_stride_heads, kv_stride_batch,\n max_num_blocks_per_seq, bmm1_scale_value, bmm2_scale_value, bmm1_scale_log2_ptr,\n bmm2_scale_ptr, o_sf_scale, o_sf_vec_size, o_sf_start_index, window_left, sum_seq_q,\n sparse_mla_top_k, sm_count, enable_pdl, workspace_size, stream);\n}\n\nvoid trtllm_paged_attention_context(\n TensorView out, Optional<TensorView> out_scale_factor, TensorView query, TensorView key_cache,\n TensorView value_cache, TensorView workspace_buffer, TensorView block_tables,\n TensorView seq_lens, int64_t max_q_len, int64_t max_kv_len,\n Variant<double, ffi::Tensor> bmm1_scale, Variant<double, ffi::Tensor> bmm2_scale,\n double o_sf_scale, int64_t o_sf_vec_size, int64_t o_sf_start_index, int64_t batch_size,\n int64_t window_left, TensorView cum_seq_lens_q, TensorView cum_seq_lens_kv, int64_t sm_count,\n bool enable_pdl, int64_t workspace_size, Optional<TensorView> attention_sinks) {\n auto q_data_type = dl_dtype_to_tllm_data_type(query.dtype());\n auto kv_data_type = dl_dtype_to_tllm_data_type(key_cache.dtype());\n auto o_data_type = dl_dtype_to_tllm_data_type(out.dtype());\n int num_qo_heads = query.size(1);\n int sum_seq_q = query.size(0);\n // Multiply by two for FP4 tensor as it is stored as UINT8 dtype. Assume the dim is even.\n int head_dim_k = is_4bit(kv_data_type) ? key_cache.size(-1) * 2 : key_cache.size(-1);\n int head_dim_q = is_4bit(q_data_type) ? query.size(-1) * 2 : query.size(-1);\n int head_dim_v = is_4bit(kv_data_type) ? value_cache.size(-1) * 2 : value_cache.size(-1);\n int head_dim_o = is_4bit(o_data_type) ? out.size(-1) * 2 : out.size(-1);\n TVM_FFI_ICHECK_EQ(head_dim_k, head_dim_q)\n << \"head_dim_k and head_dim_q must be the same, got \" << std::to_string(head_dim_k) << \" and \"\n << std::to_string(head_dim_q);\n TVM_FFI_ICHECK_EQ(head_dim_v, head_dim_o)\n << \"head_dim_v and head_dim_o must be the same, got \" << std::to_string(head_dim_v) << \" and \"\n << std::to_string(head_dim_o);\n int max_num_blocks_per_seq = block_tables.size(-1);\n bool is_shared_kv = key_cache.data_ptr() == value_cache.data_ptr();\n int num_pages_in_mem_pool = is_shared_kv ? key_cache.size(0) : key_cache.size(0) * 2;\n\n // Assume NHD layout: [..., H, N, D]\n int page_size = key_cache.size(-2);\n int num_kv_heads = key_cache.size(-3);\n int kv_stride_keys_values = key_cache.stride(-2); // key/values\n int kv_stride_heads = key_cache.stride(-3); // head\n int kv_stride_batch = key_cache.stride(0); // batch\n\n // Query stride: [num_tokens, num_heads, head_dim]\n int q_stride_tokens = query.stride(0); // stride between tokens\n int q_stride_heads = query.stride(1); // stride between heads\n\n const auto stream = get_stream(query.device());\n void* output_sf_ptr =\n out_scale_factor.has_value() ? out_scale_factor.value().data_ptr() : nullptr;\n\n float* attention_sinks_ptr = nullptr;\n if (attention_sinks.has_value()) {\n TVM_FFI_ICHECK_EQ(attention_sinks.value().dtype(), dl_float32)\n << \"attention_sinks must be a float tensor\";\n attention_sinks_ptr = static_cast<float*>(attention_sinks.value().data_ptr());\n }\n\n auto maybe_bmm1_scale_value = bmm1_scale.as<double>();\n auto maybe_bmm2_scale_value = bmm2_scale.as<double>();\n auto maybe_bmm1_scale_log2_tensor = bmm1_scale.as<ffi::Tensor>();\n auto maybe_bmm2_scale_tensor = bmm2_scale.as<ffi::Tensor>();\n TVM_FFI_CHECK(maybe_bmm1_scale_value.has_value() || maybe_bmm1_scale_log2_tensor.has_value(),\n \"bmm1_scale must be either a double or a tensor\");\n TVM_FFI_CHECK(maybe_bmm2_scale_value.has_value() || maybe_bmm2_scale_tensor.has_value(),\n \"bmm2_scale must be either a double or a tensor\");\n double bmm1_scale_value =\n maybe_bmm1_scale_value.has_value() ? maybe_bmm1_scale_value.value() : 1.0;\n double bmm2_scale_value =\n maybe_bmm2_scale_value.has_value() ? maybe_bmm2_scale_value.value() : 1.0;\n float* bmm1_scale_log2_ptr =\n maybe_bmm1_scale_log2_tensor.has_value()\n ? static_cast<float*>(maybe_bmm1_scale_log2_tensor.value().data_ptr())\n : nullptr;\n float* bmm2_scale_ptr = maybe_bmm2_scale_tensor.has_value()\n ? static_cast<float*>(maybe_bmm2_scale_tensor.value().data_ptr())\n : nullptr;\n\n trtllm_paged_attention_launcher(\n out.data_ptr(), output_sf_ptr, query.data_ptr(), key_cache.data_ptr(), value_cache.data_ptr(),\n workspace_buffer.data_ptr(), static_cast<int*>(block_tables.data_ptr()),\n static_cast<int*>(seq_lens.data_ptr()),\n /*cum_seq_lens_q=*/static_cast<int*>(cum_seq_lens_q.data_ptr()),\n /*cum_seq_lens_kv=*/static_cast<int*>(cum_seq_lens_kv.data_ptr()), attention_sinks_ptr,\n q_data_type, kv_data_type, o_data_type, TllmPagedAttentionMode::Context, batch_size,\n max_q_len, max_kv_len, num_pages_in_mem_pool, num_qo_heads, num_kv_heads, head_dim_q,\n head_dim_o, page_size, q_stride_tokens, q_stride_heads, kv_stride_keys_values,\n kv_stride_heads, kv_stride_batch, max_num_blocks_per_seq, bmm1_scale_value, bmm2_scale_value,\n bmm1_scale_log2_ptr, bmm2_scale_ptr, o_sf_scale, o_sf_vec_size, o_sf_start_index, window_left,\n sum_seq_q, /*sparse_mla_top_k=*/0, sm_count, enable_pdl, workspace_size, stream);\n}\n\nvoid trtllm_ragged_attention_launcher(\n void* out, void* query, void* key, void* value, void* workspace_buffer, int* seq_lens,\n int* cum_seq_lens_q, int* cum_seq_lens_kv, float* attention_sinks, float* lse,\n Data_type q_data_type, Data_type kv_data_type, Data_type o_data_type, int64_t max_q_len,\n int64_t max_kv_len, int64_t num_qo_heads, int64_t num_kv_heads, int64_t head_dim_qk,\n int64_t head_dim_v, int64_t sum_seq_q, int64_t sum_seq_kv, double bmm1_scale, double bmm2_scale,\n const float* bmm1_scale_log2_ptr, const float* bmm2_scale_ptr, double o_sf_scale,\n int64_t batch_size, int64_t window_left, int64_t sm_count, bool enable_pdl, bool is_causal,\n int64_t k_stride_keys_values, int64_t k_stride_heads, int64_t k_stride_batch,\n int64_t v_stride_keys_values, int64_t v_stride_heads, int64_t v_stride_batch,\n int64_t workspace_size, cudaStream_t stream) {\n if (num_qo_heads % num_kv_heads != 0) {\n std::ostringstream err_msg;\n err_msg << \"num_qo_heads must be a multiple of num_kv_heads, got num_kv_heads: \" << num_kv_heads\n << \" and num_qo_heads: \" << num_qo_heads;\n FLASHINFER_ERROR(err_msg.str());\n }\n auto fmha_runner = TllmGenFmhaRunnerCache::get(q_data_type, kv_data_type, o_data_type);\n TllmGenFmhaRunnerParams runner_params;\n\n runner_params.qPtr = query;\n runner_params.kPtr = key;\n runner_params.vPtr = value;\n runner_params.kvPageIdxPtr = nullptr;\n runner_params.seqLensKvPtr = seq_lens;\n runner_params.oPtr = out;\n runner_params.mHeadDimQk = head_dim_qk;\n runner_params.mHeadDimV = head_dim_v;\n runner_params.mNumHeadsQ = num_qo_heads;\n runner_params.mNumHeadsKv = num_kv_heads;\n runner_params.mNumHeadsQPerKv = num_qo_heads / num_kv_heads;\n runner_params.mBatchSize = batch_size;\n runner_params.mMaxSeqLenKv = max_kv_len;\n runner_params.mQkvLayout = QkvLayout::SeparateQkv;\n runner_params.mMultiProcessorCount = sm_count;\n runner_params.stream = stream;\n // the scaleSoftmaxLog2Ptr and outputScalePtr have higher priority than the scaleSoftmaxLog2 and\n // outputScale. if they are not nullptr, then scaleSoftmaxLog2 and outputScale will be ignored\n runner_params.outputScale = bmm2_scale;\n runner_params.outputScalePtr = bmm2_scale_ptr;\n runner_params.scaleSoftmaxLog2 = bmm1_scale * M_LOG2E;\n runner_params.scaleSoftmaxLog2Ptr = bmm1_scale_log2_ptr;\n runner_params.mScaleSfO = o_sf_scale;\n runner_params.mChunkedAttentionSize = INT_MAX; // disable chunked attention by INT_MAX\n runner_params.mAttentionWindowSize =\n window_left == -1 ? INT_MAX : window_left + 1; // disable window attention by INT_MAX\n runner_params.mMaxSeqLenQ = max_q_len;\n runner_params.mSumOfSeqLensQ = sum_seq_q;\n runner_params.mSumOfSeqLensKv = sum_seq_kv;\n runner_params.cumSeqLensKvPtr = cum_seq_lens_kv;\n runner_params.cumSeqLensQPtr = cum_seq_lens_q;\n runner_params.ptrAttentionSinks = attention_sinks;\n runner_params.enable_pdl = enable_pdl;\n\n runner_params.kStrideKeysValues = k_stride_keys_values;\n runner_params.kStrideHeads = k_stride_heads;\n runner_params.kStrideBatch = k_stride_batch;\n runner_params.vStrideKeysValues = v_stride_keys_values;\n runner_params.vStrideHeads = v_stride_heads;\n runner_params.vStrideBatch = v_stride_batch;\n\n runner_params.mKernelType = FmhaKernelType::Context;\n runner_params.mTileScheduler = TileScheduler::Persistent;\n runner_params.mMaskType =\n is_causal ? TrtllmGenAttentionMaskType::Causal : TrtllmGenAttentionMaskType::Dense;\n runner_params.lsePtr = lse;\n\n AlignedAllocator float_allocator(workspace_buffer, workspace_size);\n size_t max_batch_size = 8192;\n size_t max_num_qo_heads = 256;\n size_t num_semaphores =\n round_up(max_batch_size * max_num_qo_heads, 8); // max 8MB, should align to 16 bytes\n // semaphores be at the first 8MB of workspace buffer: counter | softmax | scratch\n runner_params.multiCtasKvCounterPtr = float_allocator.aligned_alloc<int32_t>(\n num_semaphores * sizeof(uint32_t), 16, \"trtllm_gen_counter_workspace\");\n runner_params.softmaxStatsPtr = float_allocator.aligned_alloc<float2>(\n sizeof(float2) * num_qo_heads * runner_params.mSumOfSeqLensQ, 16,\n \"trtllm_gen_softmax_workspace\");\n // scratch takes the rest of the workspace buffer\n runner_params.multiCtasKvScratchPtr =\n float_allocator.aligned_alloc<void>(0, 16, \"trtllm_gen_scratch_workspace\");\n\n auto [foundKernels, kinfo] = fmha_runner->isSupportedWithInfo(runner_params);\n if (!foundKernels) {\n std::ostringstream err_msg;\n err_msg << \"Missing TRTLLM-GEN kernel ragged attention: \" << kinfo;\n FLASHINFER_ERROR(err_msg.str());\n }\n\n fmha_runner->run(runner_params);\n}\n\nvoid trtllm_ragged_attention(TensorView out, TensorView query, TensorView key, TensorView value,\n TensorView workspace_buffer, TensorView seq_lens, int64_t max_q_len,\n int64_t max_kv_len, Variant<double, ffi::Tensor> bmm1_scale,\n Variant<double, ffi::Tensor> bmm2_scale, double o_sf_scale,\n int64_t batch_size, int64_t window_left, TensorView cum_seq_lens_q,\n TensorView cum_seq_lens_kv, int64_t sm_count, bool enable_pdl,\n bool is_causal, int64_t workspace_size,\n Optional<TensorView> attention_sinks, Optional<TensorView> lse) {\n float* attention_sinks_ptr = nullptr;\n if (attention_sinks.has_value()) {\n TVM_FFI_ICHECK_EQ(attention_sinks.value().dtype(), dl_float32)\n << \"attention_sinks must be a float tensor\";\n attention_sinks_ptr = static_cast<float*>(attention_sinks.value().data_ptr());\n }\n float* lse_ptr = nullptr;\n if (lse.has_value()) {\n TVM_FFI_ICHECK_EQ(lse.value().dtype(), dl_float32) << \"lse must be a float tensor\";\n lse_ptr = static_cast<float*>(lse.value().data_ptr());\n }\n TVM_FFI_ICHECK_EQ(out.ndim(), 3) << \"out must be a 3D tensor\";\n TVM_FFI_ICHECK_EQ(query.ndim(), 3) << \"query must be a 3D tensor\";\n TVM_FFI_ICHECK_EQ(key.ndim(), 3) << \"key must be a 3D tensor\";\n TVM_FFI_ICHECK_EQ(value.ndim(), 3) << \"value must be a 3D tensor\";\n\n auto q_data_type = dl_dtype_to_tllm_data_type(query.dtype());\n auto kv_data_type = dl_dtype_to_tllm_data_type(key.dtype());\n auto o_data_type = dl_dtype_to_tllm_data_type(out.dtype());\n const auto stream = get_stream(query.device());\n int num_qo_heads = query.size(1);\n int num_kv_heads = key.size(1);\n int sum_seq_q = query.size(0);\n int sum_seq_kv = key.size(0);\n int head_dim_qk = query.size(2);\n int head_dim_v = value.size(2);\n int k_stride_keys_values = key.stride(0);\n int k_stride_heads = key.stride(1);\n int k_stride_batch = key.numel();\n int v_stride_keys_values = value.stride(0);\n int v_stride_heads = value.stride(1);\n int v_stride_batch = value.numel();\n\n auto maybe_bmm1_scale_value = bmm1_scale.as<double>();\n auto maybe_bmm2_scale_value = bmm2_scale.as<double>();\n auto maybe_bmm1_scale_log2_tensor = bmm1_scale.as<ffi::Tensor>();\n auto maybe_bmm2_scale_tensor = bmm2_scale.as<ffi::Tensor>();\n TVM_FFI_CHECK(maybe_bmm1_scale_value.has_value() || maybe_bmm1_scale_log2_tensor.has_value(),\n \"bmm1_scale must be either a double or a tensor\");\n TVM_FFI_CHECK(maybe_bmm2_scale_value.has_value() || maybe_bmm2_scale_tensor.has_value(),\n \"bmm2_scale must be either a double or a tensor\");\n double bmm1_scale_value =\n maybe_bmm1_scale_value.has_value() ? maybe_bmm1_scale_value.value() : 1.0;\n double bmm2_scale_value =\n maybe_bmm2_scale_value.has_value() ? maybe_bmm2_scale_value.value() : 1.0;\n float* bmm1_scale_log2_ptr =\n maybe_bmm1_scale_log2_tensor.has_value()\n ? static_cast<float*>(maybe_bmm1_scale_log2_tensor.value().data_ptr())\n : nullptr;\n float* bmm2_scale_ptr = maybe_bmm2_scale_tensor.has_value()\n ? static_cast<float*>(maybe_bmm2_scale_tensor.value().data_ptr())\n : nullptr;\n trtllm_ragged_attention_launcher(\n out.data_ptr(), query.data_ptr(), key.data_ptr(), value.data_ptr(),\n workspace_buffer.data_ptr(), static_cast<int*>(seq_lens.data_ptr()),\n static_cast<int*>(cum_seq_lens_q.data_ptr()), static_cast<int*>(cum_seq_lens_kv.data_ptr()),\n attention_sinks_ptr, lse_ptr, q_data_type, kv_data_type, o_data_type, max_q_len, max_kv_len,\n num_qo_heads, num_kv_heads, head_dim_qk, head_dim_v, sum_seq_q, sum_seq_kv, bmm1_scale_value,\n bmm2_scale_value, bmm1_scale_log2_ptr, bmm2_scale_ptr, o_sf_scale, batch_size, window_left,\n sm_count, enable_pdl, is_causal, k_stride_keys_values, k_stride_heads, k_stride_batch,\n v_stride_keys_values, v_stride_heads, v_stride_batch, workspace_size, stream);\n}\n\nnamespace trtllm_cubin_loader {\n#include <flashinfer/cubin_loader.h>\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_paged_attention_decode, trtllm_paged_attention_decode);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_paged_attention_context, trtllm_paged_attention_context);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_ragged_attention, trtllm_ragged_attention);\n\n} // namespace flashinfer\n"},"diff":{"kind":"string","value":"--- csrc/trtllm_fmha_kernel_launcher.cu\n+++ csrc/trtllm_fmha_kernel_launcher.cu\n@@ -159,8 +159,11 @@\n runner_params.cumSeqLensQPtr = cum_seq_lens_q;\n runner_params.cumSeqLensKvPtr = cum_seq_lens_kv;\n } else {\n- // ForGen\n- runner_params.mMaskType = TrtllmGenAttentionMaskType::Dense;\n+ // Generation.\n+ // Note that kernel names are still labeled as using a dense mask even when maskType is\n+ // specified as causal, this is expected for better performance as each CTA will only process\n+ // one tokenQ in those cases, so dense mask works the same as causal mask.\n+ runner_params.mMaskType = TrtllmGenAttentionMaskType::Causal;\n runner_params.mKernelType = FmhaKernelType::Generation;\n bool use_multi_block = true;\n runner_params.mTileScheduler ="},"lines_added":{"kind":"number","value":5,"string":"5"},"lines_removed":{"kind":"number","value":2,"string":"2"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":["qwen","gpt-oss"],"string":"[\n \"qwen\",\n \"gpt-oss\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/trtllm_fmha_kernel_launcher.cu).\n\nGoal: [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding\nTarget hardware: unspecified\nTarget models: qwen, gpt-oss\n\nCurrent file:\n```cuda\n/*\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <flashinfer/allocator.h>\n#include <flashinfer/exception.h>\n#include <flashinfer/trtllm/common.h>\n#include <flashinfer/trtllm/fmha/decoder_impl_common.h>\n#include <flashinfer/trtllm/fmha/fmhaRunnerParams.h>\n#include <nvrtc.h>\n#include <tvm/ffi/container/variant.h>\n\n#include <flashinfer/trtllm/fmha/fmhaRunner.cuh>\n#include <flashinfer/utils.cuh>\n#include <iostream>\n#include <sstream>\n#include <unordered_map>\n\n#include \"tvm/ffi/error.h\"\n#include \"tvm_ffi_utils.h\"\n\nusing tvm::ffi::Optional;\nusing tvm::ffi::Variant;\n\nnamespace flashinfer {\n\nenum class TllmPagedAttentionMode {\n Context,\n ForGen,\n};\n\n#include <memory>\n#include <mutex>\n\nclass TllmGenFmhaRunnerCache {\n public:\n using Key = std::tuple<Data_type, Data_type, Data_type>;\n\n static std::shared_ptr<TllmGenFmhaRunner> get(Data_type q_data_type, Data_type kv_data_type,\n Data_type o_data_type) {\n static std::unordered_map<Key, std::shared_ptr<TllmGenFmhaRunner>, KeyHash> cache;\n static std::mutex cache_mutex;\n Key key = std::make_tuple(q_data_type, kv_data_type, o_data_type);\n\n std::lock_guard<std::mutex> lock(cache_mutex);\n auto it = cache.find(key);\n if (it != cache.end()) {\n return it->second;\n } else {\n auto runner = std::make_shared<TllmGenFmhaRunner>(q_data_type, kv_data_type, o_data_type);\n cache.emplace(key, runner);\n return runner;\n }\n }\n\n private:\n struct KeyHash {\n std::size_t operator()(const Key& k) const {\n return std::hash<int>()(static_cast<int>(std::get<0>(k))) ^\n (std::hash<int>()(static_cast<int>(std::get<1>(k))) << 1) ^\n (std::hash<int>()(static_cast<int>(std::get<2>(k))) << 2);\n }\n };\n};\n\nvoid trtllm_paged_attention_launcher(\n void* out, void* out_scale_factor, void* query, void* key_cache, void* value_cache,\n void* workspace_buffer, int* block_tables, int* seq_lens, int* cum_seq_lens_q,\n int* cum_seq_lens_kv, float* attention_sinks, Data_type q_data_type, Data_type kv_data_type,\n Data_type o_data_type, TllmPagedAttentionMode mode, int64_t batch_size, int64_t max_q_len,\n int64_t max_kv_len, int64_t num_pages_in_mem_pool, int64_t num_qo_heads, int64_t num_kv_heads,\n int64_t head_dim_qk, int64_t head_dim_vo, int64_t page_size, int64_t q_stride_tokens,\n int64_t q_stride_heads, int64_t kv_stride_keys_values, int64_t kv_stride_heads,\n int64_t kv_stride_batch, int64_t max_num_blocks_per_seq, double bmm1_scale, double bmm2_scale,\n const float* bmm1_scale_log2_ptr, const float* bmm2_scale_ptr, double o_sf_scale,\n int64_t o_sf_vec_size, int64_t o_sf_start_index, int64_t window_left, int64_t sum_seq_q,\n int64_t sparse_mla_top_k, int64_t sm_count, bool enable_pdl, int64_t workspace_size,\n cudaStream_t stream) {\n if (num_qo_heads % num_kv_heads != 0) {\n std::ostringstream err_msg;\n err_msg << \"num_qo_heads must be a multiple of num_kv_heads, got num_kv_heads: \" << num_kv_heads\n << \" and num_qo_heads: \" << num_qo_heads;\n FLASHINFER_ERROR(err_msg.str());\n }\n\n auto fmha_runner = TllmGenFmhaRunnerCache::get(q_data_type, kv_data_type, o_data_type);\n TllmGenFmhaRunnerParams runner_params;\n\n // Common params\n runner_params.qPtr = query;\n runner_params.kPtr = key_cache;\n runner_params.vPtr = value_cache;\n runner_params.kvPageIdxPtr = block_tables;\n runner_params.seqLensKvPtr = seq_lens;\n runner_params.oPtr = out;\n runner_params.mHeadDimQk = head_dim_qk;\n runner_params.mHeadDimV = head_dim_vo;\n runner_params.mNumHeadsQ = num_qo_heads;\n runner_params.mNumHeadsKv = num_kv_heads;\n runner_params.mNumHeadsQPerKv = num_qo_heads / num_kv_heads;\n runner_params.mBatchSize = batch_size;\n runner_params.mMaxSeqLenKv = max_kv_len;\n runner_params.mMaxNumPagesPerSeqKv = max_num_blocks_per_seq;\n runner_params.mNumTokensPerPage = page_size;\n runner_params.mQkvLayout = QkvLayout::PagedKv;\n runner_params.mMultiProcessorCount = sm_count;\n runner_params.qStrideTokens = q_stride_tokens;\n runner_params.qStrideHeads = q_stride_heads;\n runner_params.kStrideKeysValues = kv_stride_keys_values;\n runner_params.kStrideHeads = kv_stride_heads;\n runner_params.kStrideBatch = kv_stride_batch;\n runner_params.vStrideKeysValues = kv_stride_keys_values;\n runner_params.vStrideHeads = kv_stride_heads;\n runner_params.vStrideBatch = kv_stride_batch;\n runner_params.mNumPagesInMemPool = num_pages_in_mem_pool;\n runner_params.stream = stream;\n // the scaleSoftmaxLog2Ptr and outputScalePtr have higher priority than the scaleSoftmaxLog2 and\n // outputScale. if they are not nullptr, then scaleSoftmaxLog2 and outputScale will be ignored\n runner_params.outputScale = bmm2_scale;\n runner_params.outputScalePtr = bmm2_scale_ptr;\n runner_params.scaleSoftmaxLog2 = bmm1_scale * M_LOG2E;\n runner_params.scaleSoftmaxLog2Ptr = bmm1_scale_log2_ptr;\n runner_params.oSfPtr = out_scale_factor;\n runner_params.mSfStartTokenIdx = o_sf_start_index;\n runner_params.mScaleSfO = o_sf_scale;\n TVM_FFI_ICHECK(o_sf_vec_size == 16 || o_sf_vec_size == -1)\n << \"Only support o_sf_vec_size == 16 or -1(not used)\";\n runner_params.mChunkedAttentionSize = INT_MAX; // disable chunked attention by INT_MAX\n runner_params.mAttentionWindowSize =\n window_left == -1 ? INT_MAX : window_left + 1; // disable window attention by INT_MAX\n runner_params.mMaxSeqLenQ = max_q_len;\n runner_params.mSumOfSeqLensQ = sum_seq_q;\n runner_params.ptrAttentionSinks = attention_sinks;\n runner_params.enable_pdl = enable_pdl;\n\n // The sparse MLA parameters.\n runner_params.mSparseMla = sparse_mla_top_k > 0;\n runner_params.mSparseMlaTopK = sparse_mla_top_k;\n TVM_FFI_ICHECK((head_dim_qk == 576 && head_dim_vo == 512) || sparse_mla_top_k <= 0)\n << \"Only decode MLA supports sparse MLA\";\n\n AlignedAllocator float_allocator(workspace_buffer, workspace_size);\n if (mode == TllmPagedAttentionMode::Context) {\n runner_params.mMaskType = TrtllmGenAttentionMaskType::Causal;\n runner_params.mKernelType = FmhaKernelType::Context;\n runner_params.mTileScheduler = TileScheduler::Persistent;\n runner_params.mMultiCtasKvMode = false;\n\n runner_params.cumSeqLensQPtr = cum_seq_lens_q;\n runner_params.cumSeqLensKvPtr = cum_seq_lens_kv;\n } else {\n // ForGen\n runner_params.mMaskType = TrtllmGenAttentionMaskType::Dense;\n runner_params.mKernelType = FmhaKernelType::Generation;\n bool use_multi_block = true;\n runner_params.mTileScheduler =\n use_multi_block ? TileScheduler::Static : TileScheduler::Persistent;\n runner_params.mMultiCtasKvMode = use_multi_block;\n\n runner_params.cumSeqLensQPtr = cum_seq_lens_q;\n runner_params.cumSeqLensKvPtr = nullptr;\n\n size_t max_batch_size = 8192; // todo(Yingyi): get from dlfw\n size_t max_num_qo_heads = 256; // todo(Yingyi): get from dlfw, in total 8MB\n size_t num_semaphores =\n round_up(max_batch_size * max_num_qo_heads, 8); // max 8MB, should align to 16 bytes\n // semaphores be at the first 8MB of workspace buffer: counter | scratch\n // todo(Yingyi): add softmax buffer later for lse return\n runner_params.multiCtasKvCounterPtr = float_allocator.aligned_alloc<int32_t>(\n num_semaphores * sizeof(uint32_t), 16, \"trtllm_gen_counter_workspace\");\n // scratch takes the rest of the workspace buffer\n runner_params.multiCtasKvScratchPtr =\n float_allocator.aligned_alloc<void>(0, 16, \"trtllm_gen_scratch_workspace\");\n }\n\n auto [foundKernels, kinfo] = fmha_runner->isSupportedWithInfo(runner_params);\n if (!foundKernels) {\n std::ostringstream err_msg;\n err_msg << \"Missing TRTLLM-GEN kernel (\"\n << (mode == TllmPagedAttentionMode::Context ? \"context\" : \"decode\") << \"): \" << kinfo;\n FLASHINFER_ERROR(err_msg.str());\n }\n\n fmha_runner->run(runner_params);\n}\n\ninline Data_type dl_dtype_to_tllm_data_type(const DLDataType dtype) {\n if (dtype == dl_float32) {\n return Data_type::DATA_TYPE_FP32;\n } else if (dtype == dl_float16) {\n return Data_type::DATA_TYPE_FP16;\n } else if (dtype == dl_bfloat16) {\n return Data_type::DATA_TYPE_BF16;\n } else if (dtype == dl_float8_e4m3fn) {\n return Data_type::DATA_TYPE_E4M3;\n } else if (dtype == dl_float8_e5m2) {\n return Data_type::DATA_TYPE_E5M2;\n } else if (dtype == dl_uint8) {\n // fp4 tensor is not supported in torch and use uint8_t as container.\n return Data_type::DATA_TYPE_E2M1;\n }\n return Data_type::DATA_TYPE_UNKNOWN;\n}\n\ninline bool is_4bit(Data_type data_type) { return data_type == Data_type::DATA_TYPE_E2M1; }\n\nvoid trtllm_paged_attention_decode(TensorView out, Optional<TensorView> out_scale_factor,\n TensorView query, TensorView key_cache, TensorView value_cache,\n TensorView workspace_buffer, TensorView block_tables,\n TensorView seq_lens, int64_t max_q_len, int64_t max_kv_len,\n Variant<double, ffi::Tensor> bmm1_scale,\n Variant<double, ffi::Tensor> bmm2_scale, double o_sf_scale,\n int64_t o_sf_vec_size, int64_t o_sf_start_index,\n int64_t batch_size, int64_t window_left,\n int64_t sparse_mla_top_k, int64_t sm_count, bool enable_pdl,\n int64_t workspace_size, Optional<TensorView> attention_sinks,\n Optional<TensorView> cum_seq_lens_q) {\n auto q_data_type = dl_dtype_to_tllm_data_type(query.dtype());\n auto kv_data_type = dl_dtype_to_tllm_data_type(key_cache.dtype());\n TVM_FFI_ICHECK_EQ(key_cache.ndim(), value_cache.ndim());\n for (int i = 0; i < key_cache.ndim(); i++) {\n TVM_FFI_ICHECK_EQ(key_cache.size(i), value_cache.size(i));\n }\n auto o_data_type = dl_dtype_to_tllm_data_type(out.dtype());\n int sum_seq_q = query.size(0);\n int num_qo_heads = query.size(1);\n // the cum_seq_lens_q is optional, and can be nullptr when all sequences have the same query\n // length\n int* cum_seq_lens_q_ptr =\n cum_seq_lens_q.has_value() ? static_cast<int*>(cum_seq_lens_q.value().data_ptr()) : nullptr;\n // Multiply by two for FP4 tensor as it is stored as UINT8 dtype. Assume the dim is even.\n int head_dim_k = is_4bit(kv_data_type) ? key_cache.size(-1) * 2 : key_cache.size(-1);\n int head_dim_q = is_4bit(q_data_type) ? query.size(-1) * 2 : query.size(-1);\n int head_dim_v = is_4bit(kv_data_type) ? value_cache.size(-1) * 2 : value_cache.size(-1);\n int head_dim_o = is_4bit(o_data_type) ? out.size(-1) * 2 : out.size(-1);\n TVM_FFI_ICHECK_EQ(head_dim_k, head_dim_q)\n << \"head_dim_k and head_dim_q must be the same, got \" << std::to_string(head_dim_k) << \" and \"\n << std::to_string(head_dim_q);\n TVM_FFI_ICHECK((head_dim_v == 576 && head_dim_o == 512) || head_dim_v == head_dim_o)\n << \"head_dim_v and head_dim_o must be the same for non-MLA attention, got \"\n << std::to_string(head_dim_v) << \" and \" << std::to_string(head_dim_o);\n int max_num_blocks_per_seq = block_tables.size(-1);\n bool is_shared_kv = key_cache.data_ptr() == value_cache.data_ptr();\n int num_pages_in_mem_pool = is_shared_kv ? key_cache.size(0) : key_cache.size(0) * 2;\n\n // Assume NHD layout: [..., H, N, D]\n int page_size = key_cache.size(-2);\n int num_kv_heads = key_cache.size(-3);\n int kv_stride_keys_values = key_cache.stride(-2); // key/values\n int kv_stride_heads = key_cache.stride(-3); // head\n int kv_stride_batch = key_cache.stride(0); // batch\n\n // Query stride: [num_tokens, num_heads, head_dim]\n int q_stride_tokens = query.stride(0); // stride between tokens\n int q_stride_heads = query.stride(1); // stride between heads\n\n const auto stream = get_stream(query.device());\n void* output_sf_ptr =\n out_scale_factor.has_value() ? out_scale_factor.value().data_ptr() : nullptr;\n\n float* attention_sinks_ptr = nullptr;\n if (attention_sinks.has_value()) {\n TVM_FFI_ICHECK_EQ(attention_sinks.value().dtype(), dl_float32)\n << \"attention_sinks must be a float tensor\";\n attention_sinks_ptr = static_cast<float*>(attention_sinks.value().data_ptr());\n }\n auto maybe_bmm1_scale_value = bmm1_scale.as<double>();\n auto maybe_bmm2_scale_value = bmm2_scale.as<double>();\n auto maybe_bmm1_scale_log2_tensor = bmm1_scale.as<ffi::Tensor>();\n auto maybe_bmm2_scale_tensor = bmm2_scale.as<ffi::Tensor>();\n TVM_FFI_CHECK(maybe_bmm1_scale_value.has_value() || maybe_bmm1_scale_log2_tensor.has_value(),\n \"bmm1_scale must be either a double or a tensor\");\n TVM_FFI_CHECK(maybe_bmm2_scale_value.has_value() || maybe_bmm2_scale_tensor.has_value(),\n \"bmm2_scale must be either a double or a tensor\");\n double bmm1_scale_value =\n maybe_bmm1_scale_value.has_value() ? maybe_bmm1_scale_value.value() : 1.0;\n double bmm2_scale_value =\n maybe_bmm2_scale_value.has_value() ? maybe_bmm2_scale_value.value() : 1.0;\n float* bmm1_scale_log2_ptr =\n maybe_bmm1_scale_log2_tensor.has_value()\n ? static_cast<float*>(maybe_bmm1_scale_log2_tensor.value().data_ptr())\n : nullptr;\n float* bmm2_scale_ptr = maybe_bmm2_scale_tensor.has_value()\n ? static_cast<float*>(maybe_bmm2_scale_tensor.value().data_ptr())\n : nullptr;\n trtllm_paged_attention_launcher(\n out.data_ptr(), output_sf_ptr, query.data_ptr(), key_cache.data_ptr(), value_cache.data_ptr(),\n workspace_buffer.data_ptr(), static_cast<int*>(block_tables.data_ptr()),\n static_cast<int*>(seq_lens.data_ptr()), cum_seq_lens_q_ptr,\n /*cum_seq_lens_kv*/ nullptr, attention_sinks_ptr, q_data_type, kv_data_type, o_data_type,\n TllmPagedAttentionMode::ForGen, batch_size, max_q_len, max_kv_len, num_pages_in_mem_pool,\n num_qo_heads, num_kv_heads, head_dim_q, head_dim_o, page_size, q_stride_tokens,\n q_stride_heads, kv_stride_keys_values, kv_stride_heads, kv_stride_batch,\n max_num_blocks_per_seq, bmm1_scale_value, bmm2_scale_value, bmm1_scale_log2_ptr,\n bmm2_scale_ptr, o_sf_scale, o_sf_vec_size, o_sf_start_index, window_left, sum_seq_q,\n sparse_mla_top_k, sm_count, enable_pdl, workspace_size, stream);\n}\n\nvoid trtllm_paged_attention_context(\n TensorView out, Optional<TensorView> out_scale_factor, TensorView query, TensorView key_cache,\n TensorView value_cache, TensorView workspace_buffer, TensorView block_tables,\n TensorView seq_lens, int64_t max_q_len, int64_t max_kv_len,\n Variant<double, ffi::Tensor> bmm1_scale, Variant<double, ffi::Tensor> bmm2_scale,\n double o_sf_scale, int64_t o_sf_vec_size, int64_t o_sf_start_index, int64_t batch_size,\n int64_t window_left, TensorView cum_seq_lens_q, TensorView cum_seq_lens_kv, int64_t sm_count,\n bool enable_pdl, int64_t workspace_size, Optional<TensorView> attention_sinks) {\n auto q_data_type = dl_dtype_to_tllm_data_type(query.dtype());\n auto kv_data_type = dl_dtype_to_tllm_data_type(key_cache.dtype());\n auto o_data_type = dl_dtype_to_tllm_data_type(out.dtype());\n int num_qo_heads = query.size(1);\n int sum_seq_q = query.size(0);\n // Multiply by two for FP4 tensor as it is stored as UINT8 dtype. Assume the dim is even.\n int head_dim_k = is_4bit(kv_data_type) ? key_cache.size(-1) * 2 : key_cache.size(-1);\n int head_dim_q = is_4bit(q_data_type) ? query.size(-1) * 2 : query.size(-1);\n int head_dim_v = is_4bit(kv_data_type) ? value_cache.size(-1) * 2 : value_cache.size(-1);\n int head_dim_o = is_4bit(o_data_type) ? out.size(-1) * 2 : out.size(-1);\n TVM_FFI_ICHECK_EQ(head_dim_k, head_dim_q)\n << \"head_dim_k and head_dim_q must be the same, got \" << std::to_string(head_dim_k) << \" and \"\n << std::to_string(head_dim_q);\n TVM_FFI_ICHECK_EQ(head_dim_v, head_dim_o)\n << \"head_dim_v and head_dim_o must be the same, got \" << std::to_string(head_dim_v) << \" and \"\n << std::to_string(head_dim_o);\n int max_num_blocks_per_seq = block_tables.size(-1);\n bool is_shared_kv = key_cache.data_ptr() == value_cache.data_ptr();\n int num_pages_in_mem_pool = is_shared_kv ? key_cache.size(0) : key_cache.size(0) * 2;\n\n // Assume NHD layout: [..., H, N, D]\n int page_size = key_cache.size(-2);\n int num_kv_heads = key_cache.size(-3);\n int kv_stride_keys_values = key_cache.stride(-2); // key/values\n int kv_stride_heads = key_cache.stride(-3); // head\n int kv_stride_batch = key_cache.stride(0); // batch\n\n // Query stride: [num_tokens, num_heads, head_dim]\n int q_stride_tokens = query.stride(0); // stride between tokens\n int q_stride_heads = query.stride(1); // stride between heads\n\n const auto stream = get_stream(query.device());\n void* output_sf_ptr =\n out_scale_factor.has_value() ? out_scale_factor.value().data_ptr() : nullptr;\n\n float* attention_sinks_ptr = nullptr;\n if (attention_sinks.has_value()) {\n TVM_FFI_ICHECK_EQ(attention_sinks.value().dtype(), dl_float32)\n << \"attention_sinks must be a float tensor\";\n attention_sinks_ptr = static_cast<float*>(attention_sinks.value().data_ptr());\n }\n\n auto maybe_bmm1_scale_value = bmm1_scale.as<double>();\n auto maybe_bmm2_scale_value = bmm2_scale.as<double>();\n auto maybe_bmm1_scale_log2_tensor = bmm1_scale.as<ffi::Tensor>();\n auto maybe_bmm2_scale_tensor = bmm2_scale.as<ffi::Tensor>();\n TVM_FFI_CHECK(maybe_bmm1_scale_value.has_value() || maybe_bmm1_scale_log2_tensor.has_value(),\n \"bmm1_scale must be either a double or a tensor\");\n TVM_FFI_CHECK(maybe_bmm2_scale_value.has_value() || maybe_bmm2_scale_tensor.has_value(),\n \"bmm2_scale must be either a double or a tensor\");\n double bmm1_scale_value =\n maybe_bmm1_scale_value.has_value() ? maybe_bmm1_scale_value.value() : 1.0;\n double bmm2_scale_value =\n maybe_bmm2_scale_value.has_value() ? maybe_bmm2_scale_value.value() : 1.0;\n float* bmm1_scale_log2_ptr =\n maybe_bmm1_scale_log2_tensor.has_value()\n ? static_cast<float*>(maybe_bmm1_scale_log2_tensor.value().data_ptr())\n : nullptr;\n float* bmm2_scale_ptr = maybe_bmm2_scale_tensor.has_value()\n ? static_cast<float*>(maybe_bmm2_scale_tensor.value().data_ptr())\n : nullptr;\n\n trtllm_paged_attention_launcher(\n out.data_ptr(), output_sf_ptr, query.data_ptr(), key_cache.data_ptr(), value_cache.data_ptr(),\n workspace_buffer.data_ptr(), static_cast<int*>(block_tables.data_ptr()),\n static_cast<int*>(seq_lens.data_ptr()),\n /*cum_seq_lens_q=*/static_cast<int*>(cum_seq_lens_q.data_ptr()),\n /*cum_seq_lens_kv=*/static_cast<int*>(cum_seq_lens_kv.data_ptr()), attention_sinks_ptr,\n q_data_type, kv_data_type, o_data_type, TllmPagedAttentionMode::Context, batch_size,\n max_q_len, max_kv_len, num_pages_in_mem_pool, num_qo_heads, num_kv_heads, head_dim_q,\n head_dim_o, page_size, q_stride_tokens, q_stride_heads, kv_stride_keys_values,\n kv_stride_heads, kv_stride_batch, max_num_blocks_per_seq, bmm1_scale_value, bmm2_scale_value,\n bmm1_scale_log2_ptr, bmm2_scale_ptr, o_sf_scale, o_sf_vec_size, o_sf_start_index, window_left,\n sum_seq_q, /*sparse_mla_top_k=*/0, sm_count, enable_pdl, workspace_size, stream);\n}\n\nvoid trtllm_ragged_attention_launcher(\n void* out, void* query, void* key, void* value, void* workspace_buffer, int* seq_lens,\n int* cum_seq_lens_q, int* cum_seq_lens_kv, float* attention_sinks, float* lse,\n Data_type q_data_type, Data_type kv_data_type, Data_type o_data_type, int64_t max_q_len,\n int64_t max_kv_len, int64_t num_qo_heads, int64_t num_kv_heads, int64_t head_dim_qk,\n int64_t head_dim_v, int64_t sum_seq_q, int64_t sum_seq_kv, double bmm1_scale, double bmm2_scale,\n const float* bmm1_scale_log2_ptr, const float* bmm2_scale_ptr, double o_sf_scale,\n int64_t batch_size, int64_t window_left, int64_t sm_count, bool enable_pdl, bool is_causal,\n int64_t k_stride_keys_values, int64_t k_stride_heads, int64_t k_stride_batch,\n int64_t v_stride_keys_values, int64_t v_stride_heads, int64_t v_stride_batch,\n int64_t workspace_size, cudaStream_t stream) {\n if (num_qo_heads % num_kv_heads != 0) {\n std::ostringstream err_msg;\n err_msg << \"num_qo_heads must be a multiple of num_kv_heads, got num_kv_heads: \" << num_kv_heads\n << \" and num_qo_heads: \" << num_qo_heads;\n FLASHINFER_ERROR(err_msg.str());\n }\n auto fmha_runner = TllmGenFmhaRunnerCache::get(q_data_type, kv_data_type, o_data_type);\n TllmGenFmhaRunnerParams runner_params;\n\n runner_params.qPtr = query;\n runner_params.kPtr = key;\n runner_params.vPtr = value;\n runner_params.kvPageIdxPtr = nullptr;\n runner_params.seqLensKvPtr = seq_lens;\n runner_params.oPtr = out;\n runner_params.mHeadDimQk = head_dim_qk;\n runner_params.mHeadDimV = head_dim_v;\n runner_params.mNumHeadsQ = num_qo_heads;\n runner_params.mNumHeadsKv = num_kv_heads;\n runner_params.mNumHeadsQPerKv = num_qo_heads / num_kv_heads;\n runner_params.mBatchSize = batch_size;\n runner_params.mMaxSeqLenKv = max_kv_len;\n runner_params.mQkvLayout = QkvLayout::SeparateQkv;\n runner_params.mMultiProcessorCount = sm_count;\n runner_params.stream = stream;\n // the scaleSoftmaxLog2Ptr and outputScalePtr have higher priority than the scaleSoftmaxLog2 and\n // outputScale. if they are not nullptr, then scaleSoftmaxLog2 and outputScale will be ignored\n runner_params.outputScale = bmm2_scale;\n runner_params.outputScalePtr = bmm2_scale_ptr;\n runner_params.scaleSoftmaxLog2 = bmm1_scale * M_LOG2E;\n runner_params.scaleSoftmaxLog2Ptr = bmm1_scale_log2_ptr;\n runner_params.mScaleSfO = o_sf_scale;\n runner_params.mChunkedAttentionSize = INT_MAX; // disable chunked attention by INT_MAX\n runner_params.mAttentionWindowSize =\n window_left == -1 ? INT_MAX : window_left + 1; // disable window attention by INT_MAX\n runner_params.mMaxSeqLenQ = max_q_len;\n runner_params.mSumOfSeqLensQ = sum_seq_q;\n runner_params.mSumOfSeqLensKv = sum_seq_kv;\n runner_params.cumSeqLensKvPtr = cum_seq_lens_kv;\n runner_params.cumSeqLensQPtr = cum_seq_lens_q;\n runner_params.ptrAttentionSinks = attention_sinks;\n runner_params.enable_pdl = enable_pdl;\n\n runner_params.kStrideKeysValues = k_stride_keys_values;\n runner_params.kStrideHeads = k_stride_heads;\n runner_params.kStrideBatch = k_stride_batch;\n runner_params.vStrideKeysValues = v_stride_keys_values;\n runner_params.vStrideHeads = v_stride_heads;\n runner_params.vStrideBatch = v_stride_batch;\n\n runner_params.mKernelType = FmhaKernelType::Context;\n runner_params.mTileScheduler = TileScheduler::Persistent;\n runner_params.mMaskType =\n is_causal ? TrtllmGenAttentionMaskType::Causal : TrtllmGenAttentionMaskType::Dense;\n runner_params.lsePtr = lse;\n\n AlignedAllocator float_allocator(workspace_buffer, workspace_size);\n size_t max_batch_size = 8192;\n size_t max_num_qo_heads = 256;\n size_t num_semaphores =\n round_up(max_batch_size * max_num_qo_heads, 8); // max 8MB, should align to 16 bytes\n // semaphores be at the first 8MB of workspace buffer: counter | softmax | scratch\n runner_params.multiCtasKvCounterPtr = float_allocator.aligned_alloc<int32_t>(\n num_semaphores * sizeof(uint32_t), 16, \"trtllm_gen_counter_workspace\");\n runner_params.softmaxStatsPtr = float_allocator.aligned_alloc<float2>(\n sizeof(float2) * num_qo_heads * runner_params.mSumOfSeqLensQ, 16,\n \"trtllm_gen_softmax_workspace\");\n // scratch takes the rest of the workspace buffer\n runner_params.multiCtasKvScratchPtr =\n float_allocator.aligned_alloc<void>(0, 16, \"trtllm_gen_scratch_workspace\");\n\n auto [foundKernels, kinfo] = fmha_runner->isSupportedWithInfo(runner_params);\n if (!foundKernels) {\n std::ostringstream err_msg;\n err_msg << \"Missing TRTLLM-GEN kernel ragged attention: \" << kinfo;\n FLASHINFER_ERROR(err_msg.str());\n }\n\n fmha_runner->run(runner_params);\n}\n\nvoid trtllm_ragged_attention(TensorView out, TensorView query, TensorView key, TensorView value,\n TensorView workspace_buffer, TensorView seq_lens, int64_t max_q_len,\n int64_t max_kv_len, Variant<double, ffi::Tensor> bmm1_scale,\n Variant<double, ffi::Tensor> bmm2_scale, double o_sf_scale,\n int64_t batch_size, int64_t window_left, TensorView cum_seq_lens_q,\n TensorView cum_seq_lens_kv, int64_t sm_count, bool enable_pdl,\n bool is_causal, int64_t workspace_size,\n Optional<TensorView> attention_sinks, Optional<TensorView> lse) {\n float* attention_sinks_ptr = nullptr;\n if (attention_sinks.has_value()) {\n TVM_FFI_ICHECK_EQ(attention_sinks.value().dtype(), dl_float32)\n << \"attention_sinks must be a float tensor\";\n attention_sinks_ptr = static_cast<float*>(attention_sinks.value().data_ptr());\n }\n float* lse_ptr = nullptr;\n if (lse.has_value()) {\n TVM_FFI_ICHECK_EQ(lse.value().dtype(), dl_float32) << \"lse must be a float tensor\";\n lse_ptr = static_cast<float*>(lse.value().data_ptr());\n }\n TVM_FFI_ICHECK_EQ(out.ndim(), 3) << \"out must be a 3D tensor\";\n TVM_FFI_ICHECK_EQ(query.ndim(), 3) << \"query must be a 3D tensor\";\n TVM_FFI_ICHECK_EQ(key.ndim(), 3) << \"key must be a 3D tensor\";\n TVM_FFI_ICHECK_EQ(value.ndim(), 3) << \"value must be a 3D tensor\";\n\n auto q_data_type = dl_dtype_to_tllm_data_type(query.dtype());\n auto kv_data_type = dl_dtype_to_tllm_data_type(key.dtype());\n auto o_data_type = dl_dtype_to_tllm_data_type(out.dtype());\n const auto stream = get_stream(query.device());\n int num_qo_heads = query.size(1);\n int num_kv_heads = key.size(1);\n int sum_seq_q = query.size(0);\n int sum_seq_kv = key.size(0);\n int head_dim_qk = query.size(2);\n int head_dim_v = value.size(2);\n int k_stride_keys_values = key.stride(0);\n int k_stride_heads = key.stride(1);\n int k_stride_batch = key.numel();\n int v_stride_keys_values = value.stride(0);\n int v_stride_heads = value.stride(1);\n int v_stride_batch = value.numel();\n\n auto maybe_bmm1_scale_value = bmm1_scale.as<double>();\n auto maybe_bmm2_scale_value = bmm2_scale.as<double>();\n auto maybe_bmm1_scale_log2_tensor = bmm1_scale.as<ffi::Tensor>();\n auto maybe_bmm2_scale_tensor = bmm2_scale.as<ffi::Tensor>();\n TVM_FFI_CHECK(maybe_bmm1_scale_value.has_value() || maybe_bmm1_scale_log2_tensor.has_value(),\n \"bmm1_scale must be either a double or a tensor\");\n TVM_FFI_CHECK(maybe_bmm2_scale_value.has_value() || maybe_bmm2_scale_tensor.has_value(),\n \"bmm2_scale must be either a double or a tensor\");\n double bmm1_scale_value =\n maybe_bmm1_scale_value.has_value() ? maybe_bmm1_scale_value.value() : 1.0;\n double bmm2_scale_value =\n maybe_bmm2_scale_value.has_value() ? maybe_bmm2_scale_value.value() : 1.0;\n float* bmm1_scale_log2_ptr =\n maybe_bmm1_scale_log2_tensor.has_value()\n ? static_cast<float*>(maybe_bmm1_scale_log2_tensor.value().data_ptr())\n : nullptr;\n float* bmm2_scale_ptr = maybe_bmm2_scale_tensor.has_value()\n ? static_cast<float*>(maybe_bmm2_scale_tensor.value().data_ptr())\n : nullptr;\n trtllm_ragged_attention_launcher(\n out.data_ptr(), query.data_ptr(), key.data_ptr(), value.data_ptr(),\n workspace_buffer.data_ptr(), static_cast<int*>(seq_lens.data_ptr()),\n static_cast<int*>(cum_seq_lens_q.data_ptr()), static_cast<int*>(cum_seq_lens_kv.data_ptr()),\n attention_sinks_ptr, lse_ptr, q_data_type, kv_data_type, o_data_type, max_q_len, max_kv_len,\n num_qo_heads, num_kv_heads, head_dim_qk, head_dim_v, sum_seq_q, sum_seq_kv, bmm1_scale_value,\n bmm2_scale_value, bmm1_scale_log2_ptr, bmm2_scale_ptr, o_sf_scale, batch_size, window_left,\n sm_count, enable_pdl, is_causal, k_stride_keys_values, k_stride_heads, k_stride_batch,\n v_stride_keys_values, v_stride_heads, v_stride_batch, workspace_size, stream);\n}\n\nnamespace trtllm_cubin_loader {\n#include <flashinfer/cubin_loader.h>\n}\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_paged_attention_decode, trtllm_paged_attention_decode);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_paged_attention_context, trtllm_paged_attention_context);\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(trtllm_ragged_attention, trtllm_ragged_attention);\n\n} // namespace flashinfer\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nThis MR adds the optimized decode attention kernels for high throughput (large batch size) + speculative decoding (seqlen_q > 1). \n\nSee below for speedups (collected by `benchmarks/flashinfer_benchmark.py`). The seqlenKv is 16K for all cases. \n\n| test case | median_time_ms | median_time_ms (opt) | speedup |\n|------------------------------------------|----------------|----------------------|----------|\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ2 | 0.057 | 0.046 | 1.24 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ2 | 0.11 | 0.083 | 1.33 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ2 | 0.213 | 0.168 | 1.27 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ2 | 0.266 | 0.241 | 1.10 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ2 | 0.432 | 0.336 | 1.29 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ4 | 0.109 | 0.048 | 2.27 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ4 | 0.212 | 0.083 | 2.55 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ4 | 0.371 | 0.168 | 2.21 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ4 | 0.472 | 0.245 | 1.93 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ4 | 0.736 | 0.348 | 2.11 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ8 | 0.212 | 0.061 | 3.48 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ8 | 0.37 | 0.106 | 3.49 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ8 | 0.732 | 0.239 | 3.06 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ8 | 0.937 | 0.321 | 2.92 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ8 | 1.456 | 0.484 | 3.01 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ2 | 0.051 | 0.03 | 1.70 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ2 | 0.098 | 0.054 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ2 | 0.188 | 0.104 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ2 | 0.234 | 0.15 | 1.56 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ2 | 0.332 | 0.199 | 1.67 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ4 | 0.099 | 0.038 | 2.61 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ4 | 0.188 | 0.07 | 2.69 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ4 | 0.332 | 0.136 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ4 | 0.418 | 0.2 | 2.09 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ4 | 0.647 | 0.265 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ8 | 0.188 | 0.039 | 4.82 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ8 | 0.332 | 0.065 | 5.11 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ8 | 0.647 | 0.126 | 5.13 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ8 | 0.83 | 0.185 | 4.49 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ8 | 1.29 | 0.245 | 5.27 |\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n * Generation attention now enforces causal masking during token generation.\n\n* **Performance / Refactor**\n * Improved kernel selection and on-demand loading for better performance and GPU compatibility.\n * Added finer-grained tuning parameters for tile/grouping, tokens-per-CTA and inflation to enable more optimal kernel choices.\n\n* **Chores**\n * Updated FMHA artifact paths and checksums.\n\n* **Tests**\n * Expanded parameterized tests to cover larger batch decoding scenarios.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1194,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"e079eee48dec413adb66d4a142e3eb66f9f42b6f"},"date":{"kind":"string","value":"2026-01-08T07:48:37+08:00"},"pr_number":{"kind":"number","value":2265,"string":"2,265"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2265"},"title":{"kind":"string","value":"[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265)"},"message":{"kind":"string","value":"[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nThis MR adds the optimized decode attention kernels for high throughput\n(large batch size) + speculative decoding (seqlen_q > 1).\n\nSee below for speedups (collected by\n`benchmarks/flashinfer_benchmark.py`). The seqlenKv is 16K for all\ncases.\n\n| test case | median_time_ms | median_time_ms (opt) | speedup |\n\n|------------------------------------------|----------------|----------------------|----------|\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ2 | 0.057 | 0.046 | 1.24 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ2 | 0.11 | 0.083 | 1.33 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ2 | 0.213 | 0.168 | 1.27 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ2 | 0.266 | 0.241 | 1.10 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ2 | 0.432 | 0.336 | 1.29 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ4 | 0.109 | 0.048 | 2.27 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ4 | 0.212 | 0.083 | 2.55 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ4 | 0.371 | 0.168 | 2.21 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ4 | 0.472 | 0.245 | 1.93 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ4 | 0.736 | 0.348 | 2.11 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ8 | 0.212 | 0.061 | 3.48 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ8 | 0.37 | 0.106 | 3.49 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ8 | 0.732 | 0.239 | 3.06 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ8 | 0.937 | 0.321 | 2.92 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ8 | 1.456 | 0.484 | 3.01 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ2 | 0.051 | 0.03 | 1.70 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ2 | 0.098 | 0.054 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ2 | 0.188 | 0.104 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ2 | 0.234 | 0.15 | 1.56 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ2 | 0.332 | 0.199 | 1.67 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ4 | 0.099 | 0.038 | 2.61 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ4 | 0.188 | 0.07 | 2.69 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ4 | 0.332 | 0.136 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ4 | 0.418 | 0.2 | 2.09 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ4 | 0.647 | 0.265 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ8 | 0.188 | 0.039 | 4.82 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ8 | 0.332 | 0.065 | 5.11 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ8 | 0.647 | 0.126 | 5.13 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ8 | 0.83 | 0.185 | 4.49 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ8 | 1.29 | 0.245 | 5.27 |\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n* Generation attention now enforces causal masking during token\ngeneration.\n\n* **Performance / Refactor**\n* Improved kernel selection and on-demand loading for better performance\nand GPU compatibility.\n* Added finer-grained tuning parameters for tile/grouping,\ntokens-per-CTA and inflation to enable more optimal kernel choices.\n\n* **Chores**\n * Updated FMHA artifact paths and checksums.\n\n* **Tests**\n* Expanded parameterized tests to cover larger batch decoding scenarios.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review\nsettings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: yzh119 <zihaoy@nvidia.com>\nCo-authored-by: Zihao Ye <expye@outlook.com>"},"path":{"kind":"string","value":"include/flashinfer/trtllm/fmha/fmhaKernels.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#pragma once\n\n#include <cuda.h>\n\n#include <cstdint>\n#include <iterator>\n#include <memory>\n#include <mutex>\n#include <unordered_map>\n\n#include \"../../exception.h\"\n#include \"../../utils.cuh\"\n#include \"../common.h\"\n#include \"cuda_runtime_api.h\"\n#include \"flashInferMetaInfo.h\"\n#include \"fmhaReduction.h\"\n#include \"fmhaRunnerParams.h\"\n#include \"kernelParams.h\"\n#include \"lse.cuh\"\n\n#ifdef TLLM_GEN_FMHA_CUBIN_PATH\nstatic const std::string tllm_gen_fmha_cubin_path = std::string(TLLM_GEN_FMHA_CUBIN_PATH);\n#else\nstatic_assert(false, \"TLLM_GEN_FMHA_CUBIN_PATH macro is not defined when compiling\");\n#endif\n\n#ifdef TLLM_GEN_FMHA_METAINFO_HASH\nstatic const std::string tllm_gen_fmha_metainfo_hash = std::string(TLLM_GEN_FMHA_METAINFO_HASH);\n#else\nstatic_assert(false, \"TLLM_GEN_FMHA_METAINFO_HASH macro is not defined when compiling\");\n#endif\n\nnamespace flashinfer::trtllm_cubin_loader {\nstd::string getCubin(const std::string& kernelName, const std::string& sha256);\n} // namespace flashinfer::trtllm_cubin_loader\nusing flashinfer::trtllm_cubin_loader::getCubin;\n\nconstexpr bool isSMCompatible(int gpuSM, int kernelSM) {\n if (gpuSM == kSM_103) {\n return kernelSM == kSM_100f || kernelSM == kSM_103;\n } else if (gpuSM == kSM_100) {\n return kernelSM == kSM_100f || kernelSM == kSM_100;\n }\n\n return gpuSM == kernelSM;\n}\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nclass TllmGenFmhaKernel {\n public:\n using KernelMeta = tensorrt_llm::kernels::TllmGenFmhaKernelMetaInfo;\n using RunnerParams = TllmGenFmhaRunnerParams;\n using SelectKernelParams = TllmGenSelectKernelParams;\n\n // Ctor.\n TllmGenFmhaKernel(KernelMeta const* pMetaStart, unsigned int nMetaCount, Data_type dtypeQ,\n Data_type dtypeKv, Data_type dtypeOut, unsigned int smArch)\n : mDtypeQ(dtypeQ),\n mDtypeKv(dtypeKv),\n mDtypeOut(dtypeOut),\n mKernelMeta(pMetaStart),\n mKernelMetaCount(nMetaCount),\n mSM(smArch) {}\n\n void loadKernels() {\n for (unsigned int i = 0; i < mKernelMetaCount; ++i) {\n auto const& kernelMeta = mKernelMeta[i];\n IKL_LOG_DEBUG(\"Checking tllmgen attention kernel %s\", kernelMeta.mFuncName);\n if (isSMCompatible(mSM, kernelMeta.mSM) && kernelMeta.mDataTypeQ == mDtypeQ &&\n kernelMeta.mDataTypeKv == mDtypeKv && kernelMeta.mDataTypeO == mDtypeOut) {\n // Store metadata for later use.\n IKL_LOG_DEBUG(\"Adding tllmgen attention kernel %s\", kernelMeta.mFuncName);\n mKernelMetaMap[hashID(kernelMeta)] = i;\n }\n }\n }\n\n size_t getNumLoadedKernels() const { return mKernelMetaMap.size(); }\n\n inline uint64_t hashID(int qkvLayout, int maskType, int kernelType, int scheduler,\n int multiCtasKvMode, int headDimPerCtaV, int headDimQk, int headDimV,\n int tileSizeKv, int numTokensPerPage, int maxNumHeadsQPerKvInCta,\n bool reuseSmemKForV, bool uses2CtaMma, bool sparseMla) const {\n FLASHINFER_CHECK((headDimPerCtaV >= 32) && (headDimQk >= 32) && (headDimV >= 32) &&\n (headDimPerCtaV <= 1024) && (headDimQk <= 1024) && (headDimV <= 1024),\n \"Expect (32 <= headDim <= 1024), got headDimPerCtaV=%d, headDimQk=%d, \"\n \"headDimV=%d\",\n headDimPerCtaV, headDimQk, headDimV);\n // The numTokensPerPage must be power of 2.\n FLASHINFER_CHECK((numTokensPerPage & (numTokensPerPage - 1)) == 0,\n \"The numTokensPerPage must be power of 2.\");\n FLASHINFER_CHECK(maxNumHeadsQPerKvInCta <= 128,\n \"The maxNumHeadsQPerKvInCta <= 128 is required.\");\n FLASHINFER_CHECK(tileSizeKv == 64 || tileSizeKv == 128, \"The tileSizeKv must be 64 or 128.\");\n // Format of the hash key:\n // Bit 0 - 3 : qkvLayout.\n // Bit 4 - 7 : maskType.\n // Bit 8 - 11: kernelType.\n // Bit 12 - 15: tileScheduler.\n // Bit 16 - 17: multiCtasKvMode.\n // Bit 18 - 25: (headDimPerCtaV >> 3).\n // Bit 26 - 33: (headDimQk >> 3).\n // Bit 34 - 41: (headDimV >> 3).\n // Bit 42 - 43: (tileSizeKv >> 6).\n // Bit 44 - 48: (log2(numTokensPerPage)).\n // Bit 49 - 56: maxNumHeadsQPerKvInCta.\n // Bit 57 - 57: reuseSmemKForV.\n // Bit 58 - 58: uses2CtaMma.\n // Bit 59 - 59: sparseMla.\n return (static_cast<uint64_t>(qkvLayout) << 0) | (static_cast<uint64_t>(maskType) << 4) |\n (static_cast<uint64_t>(kernelType) << 8) | (static_cast<uint64_t>(scheduler) << 12) |\n (static_cast<uint64_t>(multiCtasKvMode) << 16) |\n (static_cast<uint64_t>(headDimPerCtaV >> 3) << 18) |\n (static_cast<uint64_t>(headDimQk >> 3) << 26) |\n (static_cast<uint64_t>(headDimV >> 3) << 34) |\n (static_cast<uint64_t>(tileSizeKv >> 6) << 42) |\n (static_cast<uint64_t>(log2(numTokensPerPage)) << 44) |\n (static_cast<uint64_t>(maxNumHeadsQPerKvInCta) << 49) |\n (static_cast<uint64_t>(reuseSmemKForV) << 57) |\n (static_cast<uint64_t>(uses2CtaMma) << 58) | (static_cast<uint64_t>(sparseMla) << 59);\n }\n\n uint64_t hashID(KernelMeta const& kernelMeta) const {\n return hashID(kernelMeta.mQkvLayout, kernelMeta.mMaskType, kernelMeta.mKernelType,\n kernelMeta.mTileScheduler, kernelMeta.mMultiCtasKvMode,\n kernelMeta.mHeadDimPerCtaV, kernelMeta.mHeadDimQk, kernelMeta.mHeadDimV,\n kernelMeta.mTileSizeKv, kernelMeta.mNumTokensPerPage,\n kernelMeta.mMaxNumHeadsQPerKvInCta, kernelMeta.mReuseSmemKForV,\n kernelMeta.m2CtaMma, kernelMeta.mSparseMla);\n }\n\n std::pair<bool, std::string> checkIfKernelExist(RunnerParams const& params) const {\n // The selectKernelParams that might be updated.\n SelectKernelParams selectKernelParams{params};\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n return std::make_pair(mKernelMetaMap.find(hashId) != mKernelMetaMap.end(), info);\n }\n // start here\n void run(RunnerParams const& params) const {\n // The selectKernelParams that might be updated.\n SelectKernelParams selectKernelParams{params};\n // The iteration index (used to detect a deadlock of selecting new kernels).\n int selectKernelIter = 0;\n // While loop.\n while (true) {\n // Any value >= 2 should work here, but we set it larger in case that we\n // might have more complicated heuristic in the future.\n FLASHINFER_CHECK(selectKernelIter < 8,\n \"A deadlock is detected when selecting trtllm-gen kernels.\");\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n auto const findMetaIter = mKernelMetaMap.find(hashId);\n\n // Add debug info when kernels are not found.\n FLASHINFER_CHECK(findMetaIter != mKernelMetaMap.end(),\n \"Trtllm-gen kernels not found: \" + info);\n\n // auto const& kernelMeta = mKernelMeta[findIter->second.mMetaInfoIndex];\n auto const findFuncIter = mFunctions.find(hashId);\n if (findFuncIter == mFunctions.end()) {\n // Load the kernel on-demand.\n loadKernel(hashId, findMetaIter->second);\n }\n // Retrieve the loaded kernel.\n auto const& kernelInfo = mFunctions.at(hashId);\n auto const& kernelMeta = mKernelMeta[kernelInfo.mMetaInfoIndex];\n CUfunction func = kernelInfo.mDeviceFunction;\n\n // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension.\n auto [maxNumCtasQ, maxNumCtasKv, numCtasX, numCtasY, numCtasZ, clusterDimX] =\n computeCtaAndClusterConfig(params, kernelMeta, selectKernelParams);\n // Need to select a new kernel if mSelectNewKernel is true.\n if (selectKernelParams.mSelectNewKernel) {\n selectKernelIter++;\n continue;\n }\n\n // Prepare the kernel parameters.\n auto kernelParams =\n KernelParams::setKernelParams(params, kernelMeta, maxNumCtasQ, maxNumCtasKv);\n\n // Prepare kernel parameters list for cuLaunchKernelEx.\n void* kernelParamsList[] = {&kernelParams};\n CUlaunchConfig launch_config;\n launch_config.blockDimX = kernelMeta.mThreadsPerCTA;\n launch_config.blockDimY = 1;\n launch_config.blockDimZ = 1;\n launch_config.gridDimX = numCtasX;\n launch_config.gridDimY = numCtasY;\n launch_config.gridDimZ = numCtasZ;\n launch_config.hStream = params.stream;\n launch_config.sharedMemBytes = kernelMeta.mSharedMemBytes;\n\n // Debug info.\n IKL_LOG_DEBUG(\"TRTLLM-Gen launch info (in TllmGenFmhaKernel %s, %s, %s, %d): kernelName = %s\",\n toStr(mDtypeQ), toStr(mDtypeKv), toStr(mDtypeOut), mSM, kernelMeta.mFuncName);\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: maxSeqLenQ = %d, \"\n \"maxSeqLenKv = %d, \"\n \"numHeadsQ = %d, \"\n \"numHeadsKv = %d, batchSize = %d, kernelType = %d\",\n params.mMaxSeqLenQ, params.mMaxSeqLenKv, params.mNumHeadsQ, params.mNumHeadsKv,\n params.mBatchSize, static_cast<int>(params.mKernelType));\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: numCtasX = %d, numCtasY = %d, numCtasZ = %d, clusterDimX = %d\",\n numCtasX, numCtasY, numCtasZ, clusterDimX);\n\n CUlaunchAttribute launch_attribute[3];\n launch_attribute[0].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION;\n launch_attribute[0].value.clusterDim.x = clusterDimX;\n launch_attribute[0].value.clusterDim.y = 1;\n launch_attribute[0].value.clusterDim.z = 1;\n launch_attribute[1].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE;\n launch_attribute[1].value.clusterSchedulingPolicyPreference =\n clusterDimX > 1 ? CU_CLUSTER_SCHEDULING_POLICY_SPREAD\n : CU_CLUSTER_SCHEDULING_POLICY_DEFAULT;\n launch_attribute[2].id = CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION;\n launch_attribute[2].value.programmaticStreamSerializationAllowed = params.enable_pdl;\n\n launch_config.attrs = launch_attribute;\n launch_config.numAttrs = 3;\n // Add setting for non-portable cluster size.\n if (clusterDimX > 8) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED,\n 1 // Enable non-portable cluster sizes\n ));\n }\n\n // Force using GmemReduction for the multiCtasKvMode if the CgaSmemReduction needs more than\n // one wave (due to the cluster occupancy limit).\n // TODO: find a better heuristic of using CgaSmemReduction.\n if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n // The maximum number of active clusters that could co-exist.\n int maxActiveClusters = 1;\n cuErrCheck(cuOccupancyMaxActiveClusters(&maxActiveClusters, func, &launch_config));\n // Use the GmemReduction instead if it needs more than one wave.\n if (maxActiveClusters * clusterDimX < (numCtasX * numCtasY * numCtasZ)) {\n selectKernelParams.mForceGmemReduction = true;\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReduction;\n // continue to select a new kernel.\n continue;\n }\n }\n cuErrCheck(cuLaunchKernelEx(&launch_config, func, kernelParamsList, nullptr));\n\n // Run the separate reduction kernel if needed.\n tensorrt_llm::kernels::runFmhaReduction(kernelMeta, kernelParams, params.mMultiProcessorCount,\n params.enable_pdl, params.stream);\n\n if (params.lsePtr != nullptr) {\n flashinfer::ComputeLSEFromMD(params.softmaxStatsPtr, params.lsePtr,\n params.mSumOfSeqLensQ * params.mNumHeadsQ, params.enable_pdl,\n params.stream);\n }\n // Break the while op.\n break;\n }\n }\n\n private:\n // Is it MLA generation kernel ?\n inline bool isMlaGenKernel(RunnerParams const& params) const {\n return params.mHeadDimQk == 576 && params.mHeadDimV == 512;\n }\n\n // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension.\n using CtaClusterInfo = std::tuple<int, int, int, int, int, int>;\n\n CtaClusterInfo computeCtaAndClusterConfig(RunnerParams const& params,\n KernelMeta const& kernelMeta,\n SelectKernelParams& selectKernelParams) const {\n bool isDsv3MinLatencyMode = params.mBatchSize == 1 && params.mMaxSeqLenQ >= 1 &&\n params.mMaxSeqLenQ <= 16 && params.mHeadDimQk == 576 &&\n params.mHeadDimV == 512;\n // Do we need to select a new kernel ?\n selectKernelParams.mSelectNewKernel = false;\n\n // The number of Ctas per Q sequence.\n int numCtasPerSeqQ = (params.mMaxSeqLenQ + kernelMeta.mStepQ - 1) / kernelMeta.mStepQ;\n // Each CTA handles one tokenQ by default for spec-decoding generation kernel, which is used to\n // emulate causal masking (like MTP or Eagle3). Note this will be changed later when the\n // high-throughput spec-decoding generation kernels are integrated.\n if (params.mMaxSeqLenQ > 1 && !isContextKernel(params.mKernelType)) {\n numCtasPerSeqQ = params.mMaxSeqLenQ;\n }\n\n // Compute the grid dimension Y.\n int numHeadsPerCta = kernelMeta.mGroupsHeadsQ\n ? std::min(params.mNumHeadsQPerKv, kernelMeta.mMaxNumHeadsQPerKvInCta)\n : 1;\n int numCtasForAllHeadsQ = params.mNumHeadsQ / numHeadsPerCta;\n FLASHINFER_CHECK(numHeadsPerCta * numCtasForAllHeadsQ == params.mNumHeadsQ,\n \"The numHeadsQ/numHeadsKv is not supported.\");\n // Take the number of headDim CTAs.\n FLASHINFER_CHECK(kernelMeta.mHeadDimV % selectKernelParams.mHeadDimPerCtaV == 0,\n \"The headDimPerCtaV is not supported.\");\n int numCtasPerHeadDim = kernelMeta.mHeadDimV / selectKernelParams.mHeadDimPerCtaV;\n // Compute the current numCtasX.\n int numCtasX = numCtasPerSeqQ;\n // Update the numCtasY.\n int numCtasY = numCtasForAllHeadsQ * numCtasPerHeadDim;\n // Compute the grid dimension Z.\n int numCtasZ = params.mBatchSize;\n // The 2CtaMma kernels will use 2 Ctas in the x dimension (only used by MLA generation kernels)\n // for heads, so numCtasPerHeadDim and numCtasForAllHeadsQ will be handled by the 2Ctas in the x\n // dimension.\n if (isMlaGenKernel(params) && selectKernelParams.mUses2CtaMma) {\n FLASHINFER_CHECK(numCtasForAllHeadsQ == 2 && numCtasPerHeadDim == 2,\n \"Internal error: numCtasPerHeadDim should be 2.\");\n numCtasX *= 2;\n numCtasY /= (numCtasForAllHeadsQ * numCtasPerHeadDim);\n }\n\n // First split the seqLenKv into multiple CTAs if the utilization is not full.\n // The number of Ctas per KV sequence.\n int numCtasPerSeqKv = 1;\n // Consider the multiCtasKvMode for better GPU utilization.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n // The maximum attention window (the maximum number of tokensKv that will be attended to).\n int maxAttentionWindow{params.mMaxSeqLenKv};\n // The sparseMla only selects topK tokensKv.\n if (params.mSparseMla) {\n maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mSparseMlaTopK);\n }\n // Some of the tilesKv will be skipped if the sliding window attention or chunked attention is\n // used.\n if (isSlidingOrChunkedCausalMask(selectKernelParams.mMaskType)) {\n if (params.mMaxSeqLenKv > params.mAttentionWindowSize) {\n // Consider that the first tileKv might contain tokensKv that is out of the attention\n // window.\n maxAttentionWindow =\n std::min(params.mMaxSeqLenKv, params.mAttentionWindowSize + kernelMeta.mStepKv - 1);\n } else {\n maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mChunkedAttentionSize);\n }\n }\n\n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n int const maxNumCtasPerSeqKv =\n (maxAttentionWindow + kernelMeta.mStepKv - 1) / kernelMeta.mStepKv;\n // Compute numCtasPerSeqKv.\n numCtasPerSeqKv = std::min(\n maxNumCtasPerSeqKv,\n std::max(1, int32_t(params.mMultiProcessorCount / (numCtasX * numCtasY * numCtasZ))));\n // Update the numCtasX.\n numCtasX *= numCtasPerSeqKv;\n // The current total number of CTAs.\n int totalNumCtas = numCtasX * numCtasZ * numCtasY;\n // Disable the multiCtasKvMode if there is only one CtaKv.\n if (numCtasPerSeqKv <= 1) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::Disabled;\n // Enable the persistent scheduler for better performance.\n selectKernelParams.mTileScheduler = TileScheduler::Persistent;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n } else if (totalNumCtas < params.mMultiProcessorCount && isMlaGenKernel(params) &&\n !params.mSparseMla && selectKernelParams.mTileSizeKv == 128 &&\n getEnvUseTileSizeKv64ForTrtllmGen()) {\n // Use smaller tileSizeKv to fully utilize the SMs.\n selectKernelParams.mTileSizeKv = 64;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n\n // Enable the CgaSmemReduction if the numCtasPerSeqKv <= 16 as the maximum cluster dimension\n // is 16. Only the swapsMmaAbForGeneration kernel supports the CgaSmemReduction for now.\n if (!isDsv3MinLatencyMode && numCtasPerSeqKv > 1 && numCtasPerSeqKv <= 16 &&\n isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType) &&\n isGmemReduction(selectKernelParams.mMultiCtasKvMode) &&\n !selectKernelParams.mForceGmemReduction) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::CgaSmemReduction;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n\n // Add the debug info when multiCtasKvMode is enabled.\n if (numCtasPerSeqKv > 1) {\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: multiCtasKvMode is enabled with tileSizeKv = %d, \"\n \"numCtasPerSeqKv = %d, \"\n \"numCtasPerSeqQ = \"\n \"%d, numCtasY = %d, numCtasZ = %d\",\n selectKernelParams.mTileSizeKv, numCtasPerSeqKv, numCtasPerSeqQ, numCtasY, numCtasZ);\n }\n }\n\n // The cluster size in the X dimension.\n int clusterDimX = selectKernelParams.mUses2CtaMma ? 2 : 1;\n if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n // Note 2CtaMma and CgaSmemReduction cannot be used together currently.\n clusterDimX *= numCtasPerSeqKv;\n }\n\n // Compute the current number of CTAs in total.\n int totalNumCtas = numCtasX * numCtasZ * numCtasY;\n\n // Then split the headDimV into multiple CTAs if there are still unused SMs.\n if (isMlaGenKernel(params) && !selectKernelParams.mReuseSmemKForV &&\n !selectKernelParams.mSelectNewKernel && !selectKernelParams.mUses2CtaMma) {\n // Split the headDimV into multiple CTAs if the utilization is not full.\n // It doesn't work with reuseSmemKForV currently.\n // TODO: find better heuristic of splitting headDimV across multiple CTAs.\n\n int corrFactor = isDsv3MinLatencyMode ? 1 : 2;\n if (selectKernelParams.mHeadDimPerCtaV == 512 &&\n totalNumCtas * corrFactor <= params.mMultiProcessorCount) {\n // Use smaller headDimPerCtaV to fully utilize the SMs.\n selectKernelParams.mHeadDimPerCtaV =\n totalNumCtas * 2 * corrFactor <= params.mMultiProcessorCount ? 128 : 256;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n }\n\n // Return the number of CTAs for X, Y and Z dimension and the cluster size in the X dimension.\n return std::make_tuple(numCtasPerSeqQ, numCtasPerSeqKv, numCtasX, numCtasY, numCtasZ,\n clusterDimX);\n }\n\n // Determine if we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n bool useSwapsMmaAbMlaGenKernel(RunnerParams const& params) const {\n // Use the SwapsMmaAbForGeneration kernel for MLA generation when the following conditions are\n // met:\n // 1. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned\n // later).\n // 2. The numCtas (after splitting the heads across multiple CTAs) <=\n // params.mMultiProcessorCount.\n\n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n // Here we assume the stepKv is 256.\n int const maxNumCtasPerSeqKv = flashinfer::ceil_div(params.mMaxSeqLenKv, 256);\n ;\n // The number of Ctas.\n int const numCtas = static_cast<int32_t>(params.mBatchSize * params.mMaxSeqLenQ *\n divUp(params.mNumHeadsQPerKv, 16));\n // Compute numCtasPerSeqKv.\n int const numCtasPerSeqKv =\n std::min(maxNumCtasPerSeqKv, std::max(1, int32_t(params.mMultiProcessorCount / numCtas)));\n // Compute the seqLenPerCtaKv.\n int const seqLenPerCtaKv = flashinfer::ceil_div(params.mMaxSeqLenKv, numCtasPerSeqKv);\n // Whether we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n return seqLenPerCtaKv <= 1024 && numCtas <= params.mMultiProcessorCount;\n }\n\n std::pair<uint64_t, std::string> hashFromRunnerParams(\n RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n // The updated kernel type.\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n // Generation kernelType will use either SwapsMmaAbForGeneration or KeepsMmaAbForGeneration.\n if (isGenerationKernel(params.mKernelType) && isMlaGenKernel(params)) {\n // We use the low-latency kernel (SwapsMmaAbForGeneration with tileSizeQ = 16) when any of the\n // following conditions are met:\n // 1. The number of headsQPerKv is <= 32.\n // 2. The number of headsQPerKv is < 128 for sparseMla.\n // 3. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned\n // later) and\n // the numCtas (after splitting the heads across multiple CTAs) <=\n // params.mMultiProcessorCount.\n\n // Check the conditions.\n if (params.mNumHeadsQPerKv <= 32 || (params.mSparseMla && params.mNumHeadsQPerKv < 128) ||\n useSwapsMmaAbMlaGenKernel(params)) {\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else {\n // Otherwise, we use the high-throughput kernel.\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n // Always use the separate reduction kernel.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n }\n // The keepsMmaAbForGeneration sparseMla kernels only support numHeadsQPerKv = 128.\n FLASHINFER_CHECK(\n !params.mSparseMla || params.mNumHeadsQPerKv == 128,\n \"The keepsMmaAbForGeneration sparseMla kernels only support numHeadsQPerKv = 128\");\n // The 2CTA keepsMmaAbForGeneration kernel is used when the numHeadsQPerKv is 128.\n if (params.mNumHeadsQPerKv == 128) {\n selectKernelParams.mUses2CtaMma = true;\n // Each Cta only handles 256 headDimV.\n selectKernelParams.mHeadDimPerCtaV = 256;\n }\n }\n } else if (isGenerationKernel(params.mKernelType)) {\n kernelType = (params.mNumHeadsQPerKv <= 16 && params.mHeadDimQk != 32)\n ? FmhaKernelType::SwapsMmaAbForGeneration\n : FmhaKernelType::KeepsMmaAbForGeneration;\n }\n\n // The maximum number of headsQPerKv that the kernel can support in one Cta.\n int maxNumHeadsQPerKvInCta = 1;\n if (isSwapsMmaAbForGenerationKernel(kernelType)) {\n // Set the corresponding maxNumHeadsQPerKvInCta (tileSizeQ) for low-latency generation\n // kernels.\n maxNumHeadsQPerKvInCta = (params.mNumHeadsQPerKv <= 8) ? 8 : 16;\n FLASHINFER_CHECK((maxNumHeadsQPerKvInCta == 8 || maxNumHeadsQPerKvInCta == 16) &&\n (params.mNumHeadsQPerKv < maxNumHeadsQPerKvInCta ||\n params.mNumHeadsQPerKv % maxNumHeadsQPerKvInCta == 0),\n \"Not supported\");\n } else if (isKeepsMmaAbForGenerationKernel(kernelType)) {\n // Use the maxNumHeadsQPerKvInCta (tileSizeQ) = 64 for MLA high-throughput generation kernels.\n maxNumHeadsQPerKvInCta = isMlaGenKernel(params) ? 64 : 32;\n FLASHINFER_CHECK((params.mNumHeadsQPerKv < maxNumHeadsQPerKvInCta ||\n params.mNumHeadsQPerKv % maxNumHeadsQPerKvInCta == 0),\n \"Not supported\");\n } else if (isContextKernel(kernelType)) {\n FLASHINFER_CHECK(maxNumHeadsQPerKvInCta == 1, \"Not supported\");\n }\n\n // The mask type.\n selectKernelParams.mMaskType = params.mMaskType;\n // Enable sliding window or chunked causal if the max kv sequence length exceeds attention\n // window size or chunked attention size. This is supported by causal-mask context kernels and\n // generation-phase kernels.\n if ((selectKernelParams.mMaskType == TrtllmGenAttentionMaskType::Causal ||\n !isContextKernel(params.mKernelType)) &&\n (params.mMaxSeqLenKv > params.mAttentionWindowSize ||\n params.mChunkedAttentionSize != INT_MAX)) {\n FLASHINFER_CHECK(\n params.mMaxSeqLenKv <= params.mAttentionWindowSize ||\n params.mMaxSeqLenKv <= params.mChunkedAttentionSize,\n \"Sliding window attention and chunked attention should not be used together\");\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::SlidingOrChunkedCausal;\n }\n\n // The number of tokens per page.\n int numTokensPerPage = params.mNumTokensPerPage;\n // SparseMla kernels use a fixed numTokensPerPage = 1.\n if (params.mSparseMla) {\n numTokensPerPage = 1;\n } else if (!isPagedKv(params.mQkvLayout)) {\n // NumTokensPerPage is set to 0 when not selecting pagedKv-layout kernels.\n numTokensPerPage = 0;\n }\n\n // Debug info.\n std::string info =\n \"qkvLayout=\" + std::to_string(static_cast<int>(params.mQkvLayout)) +\n \", maskType=\" + std::to_string(static_cast<int>(selectKernelParams.mMaskType)) +\n \", kernelType=\" + std::to_string(static_cast<int>(kernelType)) +\n \", tileScheduler=\" + std::to_string(static_cast<int>(selectKernelParams.mTileScheduler)) +\n \", multiCtasKvMode=\" +\n std::to_string(static_cast<int>(selectKernelParams.mMultiCtasKvMode)) +\n \", headDimPerCtaV=\" + std::to_string(selectKernelParams.mHeadDimPerCtaV) +\n \", headDimQk=\" + std::to_string(params.mHeadDimQk) +\n \", headDimV=\" + std::to_string(params.mHeadDimV) +\n \", tileSizeKv=\" + std::to_string(selectKernelParams.mTileSizeKv) +\n \", numTokensPerPage=\" + std::to_string(numTokensPerPage) +\n \", maxNumHeadsQPerKvInCta=\" + std::to_string(maxNumHeadsQPerKvInCta) +\n \", reuseSmemKForV=\" + std::to_string(selectKernelParams.mReuseSmemKForV) +\n \", uses2CtaMma=\" + std::to_string(selectKernelParams.mUses2CtaMma) +\n \", sparseMla=\" + std::to_string(params.mSparseMla);\n IKL_LOG_DEBUG(\n \"Searching for kernel traits (%d available) in TllmGenFmhaKernel(%s, %s, %s, %d) %s\",\n getNumLoadedKernels(), toStr(mDtypeQ), toStr(mDtypeKv), toStr(mDtypeOut), mSM,\n info.c_str());\n\n return std::make_pair(\n hashID(static_cast<int>(params.mQkvLayout), static_cast<int>(selectKernelParams.mMaskType),\n static_cast<int>(kernelType), static_cast<int>(selectKernelParams.mTileScheduler),\n static_cast<int>(selectKernelParams.mMultiCtasKvMode),\n selectKernelParams.mHeadDimPerCtaV, params.mHeadDimQk, params.mHeadDimV,\n selectKernelParams.mTileSizeKv, numTokensPerPage, maxNumHeadsQPerKvInCta,\n selectKernelParams.mReuseSmemKForV, selectKernelParams.mUses2CtaMma,\n params.mSparseMla),\n info);\n }\n\n // Load a single kernel (called by `run()` when needed).\n void loadKernel(uint64_t hashId, unsigned int metaIndex) const {\n auto const& kernelMeta = mKernelMeta[metaIndex];\n CUmodule hmod{0};\n std::string kernelName(kernelMeta.mFuncName);\n\n // Check if the module is already loaded.\n auto findModuleIter = mModules.find(kernelMeta.mFuncName);\n auto capitalizeFirst = [](std::string str) {\n if (!str.empty()) {\n str[0] = std::toupper(str[0]);\n }\n return str;\n };\n if (findModuleIter == mModules.end()) {\n // Load the module.\n std::string cubin_path = tllm_gen_fmha_cubin_path + \"/\" + kernelMeta.mFuncName + \".cubin\";\n std::string cubin = getCubin(cubin_path, kernelMeta.sha256);\n if (cubin.empty()) {\n throw std::runtime_error(\"Failed to load cubin for \" + kernelName);\n }\n cuErrCheck(cuModuleLoadData(&hmod, cubin.data()));\n mModules[kernelName] = hmod;\n } else {\n hmod = findModuleIter->second;\n }\n\n // Load the function.\n KernelInfo funcInfo;\n funcInfo.mMetaInfoIndex = metaIndex;\n cuErrCheck(cuModuleGetFunction(&funcInfo.mDeviceFunction, hmod, kernelMeta.mFuncName));\n\n if (kernelMeta.mSharedMemBytes >= 48 * 1024) {\n cuErrCheck(cuFuncSetAttribute(funcInfo.mDeviceFunction,\n CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES,\n kernelMeta.mSharedMemBytes));\n }\n\n // Cache the loaded function.\n mFunctions[hashId] = funcInfo;\n }\n\n Data_type mDtypeQ, mDtypeKv, mDtypeOut;\n KernelMeta const* mKernelMeta;\n unsigned int mKernelMetaCount;\n unsigned int mSM;\n mutable std::unordered_map<std::string, CUmodule> mModules;\n\n mutable std::unordered_map<uint64_t, unsigned int> mKernelMetaMap;\n\n struct KernelInfo {\n unsigned int mMetaInfoIndex;\n CUfunction mDeviceFunction;\n };\n\n mutable std::unordered_map<uint64_t, KernelInfo> mFunctions;\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\nclass TllmFmhaKernelFactory {\n public:\n using KernelType = TllmGenFmhaKernel;\n\n KernelType const* getKernels(const typename KernelType::KernelMeta* pKernelList,\n unsigned int nbKernels, Data_type dtypeQ, Data_type dtypeKv,\n Data_type dtypeOut, unsigned int sm) {\n static std::mutex s_mutex;\n std::lock_guard<std::mutex> lg(s_mutex);\n\n auto const id = hashID(dtypeQ, dtypeKv, dtypeOut, sm);\n auto const findIter = mKernels.find(id);\n if (findIter == mKernels.end()) {\n KernelType* newKernel = new KernelType{pKernelList, nbKernels, dtypeQ, dtypeKv, dtypeOut, sm};\n newKernel->loadKernels();\n mKernels.insert(std::make_pair(id, std::unique_ptr<KernelType>(newKernel)));\n IKL_LOG_DEBUG(\n \"Loading new kernel for dtypeQ=%s, dtypeKv=%s, dtypeOut=%s, sm=%d with %d loaded kernels\",\n toStr(dtypeQ), toStr(dtypeKv), toStr(dtypeOut), sm, newKernel->getNumLoadedKernels());\n return newKernel;\n }\n return findIter->second.get();\n }\n\n static TllmFmhaKernelFactory& Get() {\n int deviceId;\n cudaGetDevice(&deviceId);\n static std::unique_ptr<TllmFmhaKernelFactory> sFactory[32] = {nullptr};\n if (sFactory[deviceId] == nullptr) {\n FLASHINFER_CHECK(deviceId < 32, \"Invalid deviceId %d (max is 32 devices)\", deviceId);\n sFactory[deviceId] = std::make_unique<TllmFmhaKernelFactory>(TllmFmhaKernelFactory());\n }\n\n return *(sFactory[deviceId]);\n }\n\n private:\n TllmFmhaKernelFactory() = default;\n\n inline uint64_t hashID(Data_type dtypeQ, Data_type dtypeKv, Data_type dtypeOut,\n unsigned int sm) const {\n return static_cast<uint64_t>(sm) | static_cast<uint64_t>(dtypeQ) << 16 |\n static_cast<uint64_t>(dtypeKv) << 20 | static_cast<uint64_t>(dtypeOut) << 24;\n }\n\n std::unordered_map<uint64_t, const std::unique_ptr<KernelType>> mKernels;\n};\n\ninline TllmGenFmhaKernel const* getTllmFmhaKernels(Data_type dtypeQ, Data_type dtypeKv,\n Data_type dtypeOut, unsigned int sm) {\n#ifndef EXCLUDE_SM_100\n return TllmFmhaKernelFactory::Get().getKernels(\n tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos,\n sizeof(tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos) /\n sizeof(tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos[0]),\n dtypeQ, dtypeKv, dtypeOut, sm);\n#else\n return nullptr;\n#endif // EXCLUDE_SM_100\n}\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#pragma once\n\n#include <cuda.h>\n\n#include <cstdint>\n#include <cuda/std/cfloat>\n#include <iterator>\n#include <memory>\n#include <mutex>\n#include <unordered_map>\n\n#include \"../../exception.h\"\n#include \"../../utils.cuh\"\n#include \"../common.h\"\n#include \"cuda_runtime_api.h\"\n#include \"flashInferMetaInfo.h\"\n#include \"fmhaReduction.h\"\n#include \"fmhaRunnerParams.h\"\n#include \"kernelParams.h\"\n#include \"lse.cuh\"\n\n#ifdef TLLM_GEN_FMHA_CUBIN_PATH\nstatic const std::string tllm_gen_fmha_cubin_path = std::string(TLLM_GEN_FMHA_CUBIN_PATH);\n#else\nstatic_assert(false, \"TLLM_GEN_FMHA_CUBIN_PATH macro is not defined when compiling\");\n#endif\n\n#ifdef TLLM_GEN_FMHA_METAINFO_HASH\nstatic const std::string tllm_gen_fmha_metainfo_hash = std::string(TLLM_GEN_FMHA_METAINFO_HASH);\n#else\nstatic_assert(false, \"TLLM_GEN_FMHA_METAINFO_HASH macro is not defined when compiling\");\n#endif\n\nnamespace flashinfer::trtllm_cubin_loader {\nstd::string getCubin(const std::string& kernelName, const std::string& sha256);\n} // namespace flashinfer::trtllm_cubin_loader\nusing flashinfer::trtllm_cubin_loader::getCubin;\n\n// Check if two SM values are family/specific versions of the same architecture\n// Returns true only if one is a family version and the other is a compatible specific version\nconstexpr bool isFamilySpecificSMPair(int sm1, int sm2) {\n if ((sm1 == kSM_100f && (sm2 == kSM_100 || sm2 == kSM_103)) ||\n (sm2 == kSM_100f && (sm1 == kSM_100 || sm1 == kSM_103))) {\n return true;\n }\n return false;\n}\n\nconstexpr bool isSMCompatible(int gpuSM, int kernelSM) {\n if (gpuSM == kSM_103) {\n return kernelSM == kSM_100f || kernelSM == kSM_103;\n } else if (gpuSM == kSM_100) {\n return kernelSM == kSM_100f || kernelSM == kSM_100;\n }\n\n return gpuSM == kernelSM;\n}\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nclass TllmGenFmhaKernel {\n public:\n // The parameters for launching the kernel.\n // maxNumCtasQ, maxNumCtasKv, numCtasX, numCtasY, numCtasZ, clusterDimX\n struct CtaLaunchParams {\n // The maximum number of CTAs in Q dimension.\n int mMaxNumCtasQ;\n // The maximum number of CTAs in Kv dimension.\n int mMaxNumCtasKv;\n // The number of CTAs in X dimension.\n int mNumCtasX;\n // The number of CTAs in Y dimension.\n int mNumCtasY;\n // The number of CTAs in Z dimension.\n int mNumCtasZ;\n // The cluster size in the X dimension.\n int mClusterDimX;\n };\n\n public:\n using KernelMeta = tensorrt_llm::kernels::TllmGenFmhaKernelMetaInfo;\n using RunnerParams = TllmGenFmhaRunnerParams;\n using SelectKernelParams = TllmGenSelectKernelParams;\n\n // Ctor.\n TllmGenFmhaKernel(KernelMeta const* pMetaStart, unsigned int nMetaCount, Data_type dtypeQ,\n Data_type dtypeKv, Data_type dtypeOut, unsigned int smArch)\n : mDtypeQ(dtypeQ),\n mDtypeKv(dtypeKv),\n mDtypeOut(dtypeOut),\n mKernelMeta(pMetaStart),\n mKernelMetaCount(nMetaCount),\n mSM(smArch) {}\n\n void loadKernels() {\n for (unsigned int i = 0; i < mKernelMetaCount; ++i) {\n auto const& kernelMeta = mKernelMeta[i];\n IKL_LOG_DEBUG(\"Checking tllmgen attention kernel %s\", kernelMeta.mFuncName);\n if (isSMCompatible(mSM, kernelMeta.mSM) && kernelMeta.mDataTypeQ == mDtypeQ &&\n kernelMeta.mDataTypeKv == mDtypeKv && kernelMeta.mDataTypeO == mDtypeOut) {\n // Store metadata for later use.\n IKL_LOG_DEBUG(\"Adding tllmgen attention kernel %s\", kernelMeta.mFuncName);\n // Check for hash conflicts.\n uint64_t hash = hashID(kernelMeta);\n if (mKernelMetaMap.find(hash) != mKernelMetaMap.end()) {\n // The kernelMeta of the existing kernel.\n auto const& existingKernelMeta = mKernelMeta[mKernelMetaMap.at(hash)];\n // Allow conflicts only if they are family/specific versions of the same architecture.\n FLASHINFER_CHECK(isFamilySpecificSMPair(existingKernelMeta.mSM, kernelMeta.mSM),\n \"Hash conflicts exist between %s and %s.\", existingKernelMeta.mFuncName,\n kernelMeta.mFuncName);\n\n // Prefer specific SM version over family version (replace if existing is family).\n if (existingKernelMeta.mSM == kSM_100f) {\n mKernelMetaMap[hash] = i;\n }\n } else {\n mKernelMetaMap[hash] = i;\n }\n }\n }\n }\n\n size_t getNumLoadedKernels() const { return mKernelMetaMap.size(); }\n\n inline uint64_t hashID(int qkvLayout, int maskType, int kernelType, int scheduler,\n int multiCtasKvMode, int headDimPerCtaV, int headDimQk, int headDimV,\n int tileSizeQ, int tileSizeKv, int numTokensPerPage, bool reuseSmemKForV,\n bool uses2CtaMma, bool sparseMla) const {\n FLASHINFER_CHECK((headDimPerCtaV >= 32) && (headDimQk >= 32) && (headDimV >= 32) &&\n (headDimPerCtaV <= 1024) && (headDimQk <= 1024) && (headDimV <= 1024),\n \"Expect (32 <= headDim <= 1024), got headDimPerCtaV=%d, headDimQk=%d, \"\n \"headDimV=%d\",\n headDimPerCtaV, headDimQk, headDimV);\n // The numTokensPerPage must be power of 2.\n FLASHINFER_CHECK((numTokensPerPage & (numTokensPerPage - 1)) == 0,\n \"The numTokensPerPage must be power of 2.\");\n FLASHINFER_CHECK(tileSizeQ <= 128 && tileSizeKv <= 128,\n \"The tileSizeQ and tileSizeKv must be <= 128.\");\n FLASHINFER_CHECK((tileSizeQ & (tileSizeQ - 1)) == 0 && (tileSizeKv & (tileSizeKv - 1)) == 0,\n \"The tileSizeQ and tileSizeKv must be power of 2.\");\n FLASHINFER_CHECK(tileSizeKv == 64 || tileSizeKv == 128, \"The tileSizeKv must be 64 or 128.\");\n // Format of the hash key:\n // Bit 0 - 3 : qkvLayout.\n // Bit 4 - 7 : maskType.\n // Bit 8 - 11: kernelType.\n // Bit 12 - 15: tileScheduler.\n // Bit 16 - 17: multiCtasKvMode.\n // Bit 18 - 25: (headDimPerCtaV >> 3).\n // Bit 26 - 33: (headDimQk >> 3).\n // Bit 34 - 41: (headDimV >> 3).\n // Bit 42 - 43: (tileSizeKv >> 6).\n // Bit 44 - 48: (log2(numTokensPerPage)).\n // Bit 49 - 52: (log2(tileSizeQ)).\n // Bit 53 - 53: reuseSmemKForV.\n // Bit 54 - 54: uses2CtaMma.\n // Bit 55 - 55: sparseMla.\n return (static_cast<uint64_t>(qkvLayout) << 0) | (static_cast<uint64_t>(maskType) << 4) |\n (static_cast<uint64_t>(kernelType) << 8) | (static_cast<uint64_t>(scheduler) << 12) |\n (static_cast<uint64_t>(multiCtasKvMode) << 16) |\n (static_cast<uint64_t>(headDimPerCtaV >> 3) << 18) |\n (static_cast<uint64_t>(headDimQk >> 3) << 26) |\n (static_cast<uint64_t>(headDimV >> 3) << 34) |\n (static_cast<uint64_t>(tileSizeKv >> 6) << 42) |\n (static_cast<uint64_t>(log2(numTokensPerPage)) << 44) |\n (static_cast<uint64_t>(log2(tileSizeQ)) << 49) |\n (static_cast<uint64_t>(reuseSmemKForV) << 53) |\n (static_cast<uint64_t>(uses2CtaMma) << 54) | (static_cast<uint64_t>(sparseMla) << 55);\n }\n\n uint64_t hashID(KernelMeta const& kernelMeta) const {\n return hashID(kernelMeta.mQkvLayout, kernelMeta.mMaskType, kernelMeta.mKernelType,\n kernelMeta.mTileScheduler, kernelMeta.mMultiCtasKvMode,\n kernelMeta.mHeadDimPerCtaV, kernelMeta.mHeadDimQk, kernelMeta.mHeadDimV,\n kernelMeta.mTileSizeQ, kernelMeta.mTileSizeKv, kernelMeta.mNumTokensPerPage,\n kernelMeta.mReuseSmemKForV, kernelMeta.m2CtaMma, kernelMeta.mSparseMla);\n }\n\n std::pair<bool, std::string> checkIfKernelExist(RunnerParams const& params) const {\n // The selectKernelParams that might be updated.\n SelectKernelParams selectKernelParams{params};\n // Select the kernel.\n selectKernel(params, selectKernelParams);\n // Hash the runner params.\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n return std::make_pair(mKernelMetaMap.find(hashId) != mKernelMetaMap.end(), info);\n }\n\n // start here\n void run(RunnerParams const& params) const {\n // The selectKernelParams that might be updated.\n SelectKernelParams selectKernelParams{params};\n // The parameters for launching the kernel.\n CtaLaunchParams ctaLaunchParams;\n // The iteration index (used to detect a deadlock of selecting new kernels).\n int selectKernelIter = 0;\n // While loop.\n while (true) {\n // Any value >= 2 should work here, but we set it larger in case that we\n // might have more complicated heuristic in the future.\n FLASHINFER_CHECK(selectKernelIter < 8,\n \"A deadlock is detected when selecting trtllm-gen kernels.\");\n\n // Select the kernel.\n selectKernel(params, selectKernelParams);\n // Load the kernel.\n auto [func, kernelMeta] = loadKernel(params, selectKernelParams);\n\n // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension.\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParams);\n\n // Need to select a new kernel if mSelectNewKernel is true.\n if (selectKernelParams.mSelectNewKernel) {\n selectKernelIter++;\n continue;\n }\n\n // Prepare the kernel parameters.\n auto kernelParams = KernelParams::setKernelParams(\n params, kernelMeta, ctaLaunchParams.mMaxNumCtasQ, ctaLaunchParams.mMaxNumCtasKv);\n\n // Prepare kernel parameters list for cuLaunchKernelEx.\n void* kernelParamsList[] = {&kernelParams};\n CUlaunchConfig launch_config;\n launch_config.blockDimX = kernelMeta.mThreadsPerCTA;\n launch_config.blockDimY = 1;\n launch_config.blockDimZ = 1;\n launch_config.gridDimX = ctaLaunchParams.mNumCtasX;\n launch_config.gridDimY = ctaLaunchParams.mNumCtasY;\n launch_config.gridDimZ = ctaLaunchParams.mNumCtasZ;\n launch_config.hStream = params.stream;\n launch_config.sharedMemBytes = kernelMeta.mSharedMemBytes;\n\n // Debug info.\n IKL_LOG_DEBUG(\"TRTLLM-Gen launch info (in TllmGenFmhaKernel %s, %s, %s, %d): kernelName = %s\",\n toStr(mDtypeQ), toStr(mDtypeKv), toStr(mDtypeOut), mSM, kernelMeta.mFuncName);\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: maxSeqLenQ = %d, \"\n \"maxSeqLenKv = %d, \"\n \"numHeadsQ = %d, \"\n \"numHeadsKv = %d, batchSize = %d, kernelType = %d\",\n params.mMaxSeqLenQ, params.mMaxSeqLenKv, params.mNumHeadsQ, params.mNumHeadsKv,\n params.mBatchSize, static_cast<int>(params.mKernelType));\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: numCtasX = %d, numCtasY = %d, numCtasZ = %d, clusterDimX = %d\",\n ctaLaunchParams.mNumCtasX, ctaLaunchParams.mNumCtasY, ctaLaunchParams.mNumCtasZ,\n ctaLaunchParams.mClusterDimX);\n\n CUlaunchAttribute launch_attribute[3];\n launch_attribute[0].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION;\n launch_attribute[0].value.clusterDim.x = ctaLaunchParams.mClusterDimX;\n launch_attribute[0].value.clusterDim.y = 1;\n launch_attribute[0].value.clusterDim.z = 1;\n launch_attribute[1].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE;\n launch_attribute[1].value.clusterSchedulingPolicyPreference =\n ctaLaunchParams.mClusterDimX > 1 ? CU_CLUSTER_SCHEDULING_POLICY_SPREAD\n : CU_CLUSTER_SCHEDULING_POLICY_DEFAULT;\n launch_attribute[2].id = CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION;\n launch_attribute[2].value.programmaticStreamSerializationAllowed = params.enable_pdl;\n\n launch_config.attrs = launch_attribute;\n launch_config.numAttrs = 3;\n // Add setting for non-portable cluster size.\n if (ctaLaunchParams.mClusterDimX > 8) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED,\n 1 // Enable non-portable cluster sizes\n ));\n }\n\n // Force using GmemReduction for the multiCtasKvMode if the CgaSmemReduction needs more than\n // one wave (due to the cluster occupancy limit).\n // TODO: find a better heuristic of using CgaSmemReduction.\n if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n // The maximum number of active clusters that could co-exist.\n int maxActiveClusters = 1;\n cuErrCheck(cuOccupancyMaxActiveClusters(&maxActiveClusters, func, &launch_config));\n // Use the GmemReduction instead if it needs more than one wave.\n if (maxActiveClusters * ctaLaunchParams.mClusterDimX <\n (ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ)) {\n selectKernelParams.mForceGmemReduction = true;\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReduction;\n // continue to select a new kernel.\n continue;\n }\n }\n cuErrCheck(cuLaunchKernelEx(&launch_config, func, kernelParamsList, nullptr));\n\n // Run the separate reduction kernel if needed.\n tensorrt_llm::kernels::runFmhaReduction(kernelMeta, kernelParams, params.mMultiProcessorCount,\n params.enable_pdl, params.stream);\n\n if (params.lsePtr != nullptr) {\n flashinfer::ComputeLSEFromMD(params.softmaxStatsPtr, params.lsePtr,\n params.mSumOfSeqLensQ * params.mNumHeadsQ, params.enable_pdl,\n params.stream);\n }\n // Break the while op.\n break;\n }\n }\n\n private:\n // Is it MLA generation kernel ?\n inline bool isMlaGenKernel(RunnerParams const& params) const {\n return params.mHeadDimQk == 576 && params.mHeadDimV == 512;\n }\n\n // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension.\n void computeCtaAndClusterConfig(CtaLaunchParams& ctaLaunchParams, RunnerParams const& params,\n KernelMeta const& kernelMeta,\n SelectKernelParams& selectKernelParams) const {\n bool isDsv3MinLatencyMode = params.mBatchSize == 1 && params.mMaxSeqLenQ >= 1 &&\n params.mMaxSeqLenQ <= 16 && params.mHeadDimQk == 576 &&\n params.mHeadDimV == 512;\n // Do we need to select a new kernel ?\n selectKernelParams.mSelectNewKernel = false;\n\n // The number of Ctas per Q sequence.\n int numCtasPerSeqQ = (params.mMaxSeqLenQ + kernelMeta.mStepQ - 1) / kernelMeta.mStepQ;\n // The generation-phase kernels might need to group both tokensQ and headsQ into one CTA.\n if (params.mMaxSeqLenQ > 1 && !isContextKernel(params.mKernelType)) {\n // Each CTA handles one tokenQ by default for spec-decoding generation kernel.\n if (!kernelMeta.mGroupsTokensHeadsQ) {\n numCtasPerSeqQ = params.mMaxSeqLenQ;\n } else {\n // Compute numTokensPerCtaQ where each CTA must process complete numGroupedHeadsQ.\n // Note that each CTA must process complete numHeadsQPerKv.\n int numTokensPerCtaQ = kernelMeta.mStepQ / params.mNumHeadsQPerKv;\n // Group both headsQ and tokensQ into one CTA.\n numCtasPerSeqQ = flashinfer::ceil_div(params.mMaxSeqLenQ, numTokensPerCtaQ);\n }\n }\n\n // Compute the grid dimension Y.\n int numHeadsPerCta =\n kernelMeta.mGroupsHeadsQ ? std::min(params.mNumHeadsQPerKv, kernelMeta.mStepQ) : 1;\n int numCtasForAllHeadsQ = params.mNumHeadsQ / numHeadsPerCta;\n FLASHINFER_CHECK(numHeadsPerCta * numCtasForAllHeadsQ == params.mNumHeadsQ,\n \"The numHeadsQ/numHeadsKv is not supported.\");\n // Take the number of headDim CTAs.\n FLASHINFER_CHECK(kernelMeta.mHeadDimV % selectKernelParams.mHeadDimPerCtaV == 0,\n \"The headDimPerCtaV is not supported.\");\n int numCtasPerHeadDim = kernelMeta.mHeadDimV / selectKernelParams.mHeadDimPerCtaV;\n // Compute the current numCtasX.\n int numCtasX = numCtasPerSeqQ;\n // Update the numCtasY.\n int numCtasY = numCtasForAllHeadsQ * numCtasPerHeadDim;\n // Compute the grid dimension Z.\n int numCtasZ = params.mBatchSize;\n // The 2CtaMma kernels will use 2 Ctas in the x dimension (only used by MLA generation kernels)\n // for heads, so numCtasPerHeadDim and numCtasForAllHeadsQ will be handled by the 2Ctas in the x\n // dimension.\n if (isMlaGenKernel(params) && selectKernelParams.mUses2CtaMma) {\n FLASHINFER_CHECK(numCtasForAllHeadsQ == 2 && numCtasPerHeadDim == 2,\n \"Internal error: numCtasPerHeadDim should be 2.\");\n numCtasX *= 2;\n numCtasY /= (numCtasForAllHeadsQ * numCtasPerHeadDim);\n }\n\n // First split the seqLenKv into multiple CTAs if the utilization is not full.\n // The number of Ctas per KV sequence.\n int numCtasPerSeqKv = 1;\n // Consider the multiCtasKvMode for better GPU utilization.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n // The maximum attention window (the maximum number of tokensKv that will be attended to).\n int maxAttentionWindow{params.mMaxSeqLenKv};\n // The sparseMla only selects topK tokensKv.\n if (params.mSparseMla) {\n maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mSparseMlaTopK);\n }\n // Some of the tilesKv will be skipped if the sliding window attention or chunked attention is\n // used.\n if (isSlidingOrChunkedCausalMask(selectKernelParams.mMaskType)) {\n if (params.mMaxSeqLenKv > params.mAttentionWindowSize) {\n // Consider that the first tileKv might contain tokensKv that is out of the attention\n // window.\n maxAttentionWindow =\n std::min(params.mMaxSeqLenKv, params.mAttentionWindowSize + kernelMeta.mStepKv - 1);\n } else {\n maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mChunkedAttentionSize);\n }\n }\n\n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n // The factor of 2 is applied here to ensure the reduction overhead does not outweigh the\n // benefits of a shorter mainloop.\n int const maxNumCtasPerSeqKv =\n (maxAttentionWindow + 2 * kernelMeta.mStepKv - 1) / (2 * kernelMeta.mStepKv);\n // Compute numCtasPerSeqKv.\n numCtasPerSeqKv = std::min(\n maxNumCtasPerSeqKv,\n std::max(1, int32_t(params.mMultiProcessorCount / (numCtasX * numCtasY * numCtasZ))));\n // Update the numCtasX.\n numCtasX *= numCtasPerSeqKv;\n // The current total number of CTAs.\n int totalNumCtas = numCtasX * numCtasZ * numCtasY;\n // Disable the multiCtasKvMode if there is only one CtaKv.\n if (numCtasPerSeqKv <= 1) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::Disabled;\n // Enable the persistent scheduler for better performance.\n selectKernelParams.mTileScheduler = TileScheduler::Persistent;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n } else if (totalNumCtas < params.mMultiProcessorCount && isMlaGenKernel(params) &&\n !params.mSparseMla && selectKernelParams.mTileSizeKv == 128 &&\n getEnvUseTileSizeKv64ForTrtllmGen()) {\n // Use smaller tileSizeKv to fully utilize the SMs.\n selectKernelParams.mTileSizeKv = 64;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n\n // Enable the CgaSmemReduction if the numCtasPerSeqKv <= 16 as the maximum cluster dimension\n // is 16. Only the swapsMmaAbForGeneration kernel supports the CgaSmemReduction for now.\n if (!isDsv3MinLatencyMode && numCtasPerSeqKv > 1 && numCtasPerSeqKv <= 16 &&\n isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType) &&\n isGmemReduction(selectKernelParams.mMultiCtasKvMode) &&\n !selectKernelParams.mForceGmemReduction) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::CgaSmemReduction;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n\n // Add the debug info when multiCtasKvMode is enabled.\n if (numCtasPerSeqKv > 1) {\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: multiCtasKvMode is enabled with tileSizeKv = %d, \"\n \"numCtasPerSeqKv = %d, \"\n \"numCtasPerSeqQ = \"\n \"%d, numCtasY = %d, numCtasZ = %d\",\n selectKernelParams.mTileSizeKv, numCtasPerSeqKv, numCtasPerSeqQ, numCtasY, numCtasZ);\n }\n }\n\n // The cluster size in the X dimension.\n int clusterDimX = selectKernelParams.mUses2CtaMma ? 2 : 1;\n if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n // Note 2CtaMma and CgaSmemReduction cannot be used together currently.\n clusterDimX *= numCtasPerSeqKv;\n }\n\n // Compute the current number of CTAs in total.\n int totalNumCtas = numCtasX * numCtasZ * numCtasY;\n\n // Then split the headDimV into multiple CTAs if there are still unused SMs.\n if (isMlaGenKernel(params) && !selectKernelParams.mReuseSmemKForV &&\n !selectKernelParams.mSelectNewKernel && !selectKernelParams.mUses2CtaMma) {\n // Split the headDimV into multiple CTAs if the utilization is not full.\n // It doesn't work with reuseSmemKForV currently.\n // TODO: find better heuristic of splitting headDimV across multiple CTAs.\n\n int corrFactor = isDsv3MinLatencyMode ? 1 : 2;\n if (selectKernelParams.mHeadDimPerCtaV == 512 &&\n totalNumCtas * corrFactor <= params.mMultiProcessorCount) {\n // Use smaller headDimPerCtaV to fully utilize the SMs.\n selectKernelParams.mHeadDimPerCtaV =\n totalNumCtas * 2 * corrFactor <= params.mMultiProcessorCount ? 128 : 256;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n }\n\n // Update the parameters for launching the kernel.\n ctaLaunchParams.mMaxNumCtasQ = numCtasPerSeqQ;\n ctaLaunchParams.mMaxNumCtasKv = numCtasPerSeqKv;\n ctaLaunchParams.mNumCtasX = numCtasX;\n ctaLaunchParams.mNumCtasY = numCtasY;\n ctaLaunchParams.mNumCtasZ = numCtasZ;\n ctaLaunchParams.mClusterDimX = clusterDimX;\n }\n\n // Determine if we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n bool useSwapsMmaAbMlaGenKernel(RunnerParams const& params) const {\n // Use the SwapsMmaAbForGeneration kernel for MLA generation when the following conditions are\n // met:\n // 1. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned\n // later).\n // 2. The numCtas (after splitting the heads across multiple CTAs) <=\n // params.mMultiProcessorCount.\n\n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n // Here we assume the stepKv is 256.\n int const maxNumCtasPerSeqKv = flashinfer::ceil_div(params.mMaxSeqLenKv, 256);\n ;\n // The number of Ctas.\n int const numCtas = static_cast<int32_t>(params.mBatchSize * params.mMaxSeqLenQ *\n flashinfer::ceil_div(params.mNumHeadsQPerKv, 16));\n // Compute numCtasPerSeqKv.\n int const numCtasPerSeqKv =\n std::min(maxNumCtasPerSeqKv, std::max(1, int32_t(params.mMultiProcessorCount / numCtas)));\n // Compute the seqLenPerCtaKv.\n int const seqLenPerCtaKv = flashinfer::ceil_div(params.mMaxSeqLenKv, numCtasPerSeqKv);\n // Whether we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n return seqLenPerCtaKv <= 1024 && numCtas <= params.mMultiProcessorCount;\n }\n\n // Select the MLA generation kernel.\n void selectMlaGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // We use the low-latency kernel (SwapsMmaAbForGeneration with tileSizeQ = 16) when any of the\n // following conditions are met:\n // 1. The number of headsQPerKv is <= 32.\n // 2. The number of headsQPerKv is < 128 for sparseMla.\n // 3. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned later)\n // and\n // the numCtas (after splitting the heads across multiple CTAs) <=\n // params.mMultiProcessorCount.\n // The sparseMla kernel will always use the 2CTA high-throughput kernel.\n\n // The kernel type.\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n // The tile size for Q.\n int& tileSizeQ = selectKernelParams.mTileSizeQ;\n\n // Check the conditions.\n if (params.mNumHeadsQPerKv <= 32 || (params.mSparseMla && params.mNumHeadsQPerKv < 128) ||\n useSwapsMmaAbMlaGenKernel(params)) {\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n // Currently, only tileSizeQ = 8 or 16 are supported.\n tileSizeQ = params.mNumHeadsQPerKv <= 8 ? 8 : 16;\n } else {\n // Otherwise, we use the high-throughput kernel.\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n // Use the tileSizeQ = 64 for MLA high-throughput generation kernels.\n tileSizeQ = 64;\n // Always use the separate reduction kernel.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n }\n // The keepsMmaAbForGeneration sparseMla kernels only support numHeadsQPerKv = 128.\n FLASHINFER_CHECK(\n !params.mSparseMla || params.mNumHeadsQPerKv == 128,\n \"The keepsMmaAbForGeneration sparseMla kernels only support numHeadsQPerKv = 128, got %d\",\n params.mNumHeadsQPerKv);\n // The 2CTA keepsMmaAbForGeneration kernel is used when the numHeadsQPerKv is 128.\n if (params.mNumHeadsQPerKv == 128) {\n selectKernelParams.mUses2CtaMma = true;\n // Each Cta only handles 256 headDimV.\n selectKernelParams.mHeadDimPerCtaV = 256;\n }\n }\n }\n\n // Selects a heuristic tileSizeQ if groupsTokensHeadsQ is true.\n void selectTileSizeQForGqaGeneration(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // Define the per-tile mainloop cost model for different tileSizeQ choices.\n std::unordered_map<int, float> kernelMainloopCost = {\n {128, 2.2}, // Cost factor when tileSizeQ = 128\n {64, 1.68}, // Cost factor when tileSizeQ = 64\n {32, 1.48}, // Cost factor when tileSizeQ = 32\n {16, 1.2}, // Cost factor when tileSizeQ = 16\n {8, 1.0} // Cost factor when tileSizeQ = 8\n };\n\n // Define the per-tile reduction cost model for different tileSizeQ choices.\n std::unordered_map<int, float> kernelReductionCost = {\n {128, 1.32}, // Reduction cost factor when tileSizeQ = 128\n {64, 1.2}, // Reduction cost factor when tileSizeQ = 64\n {32, 1.08}, // Reduction cost factor when tileSizeQ = 32\n {16, 1.03}, // Reduction cost factor when tileSizeQ = 16\n {8, 1.0} // Reduction cost factor when tileSizeQ = 8\n };\n\n // The reduction cost emulated as a sequence length factor.\n float const kernelReductionSeqLenFactor = 128.0f;\n\n // The parameters for launching the kernel.\n CtaLaunchParams ctaLaunchParams;\n // The copy of the selectKernelParams, which makes sure it won't modify the original\n // selectKernelParams when computing the number of CTAs.\n SelectKernelParams selectKernelParamsCopy = selectKernelParams;\n // Load the kernel.\n auto [func, kernelMeta] = loadKernel(params, selectKernelParamsCopy);\n // Compute numCtasX, numCtasY and numCtasZ.\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParamsCopy);\n\n // If there are no free SMs or tileSizeQ is already the smallest one, skip the heuristic\n // selection.\n if (ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ * 2 >\n params.mMultiProcessorCount ||\n selectKernelParamsCopy.mTileSizeQ <= 8) {\n // No need to select the kernel further.\n return;\n }\n\n // Candidate tile sizes for tileSizeQ to explore.\n int const candidateTileSizesQ[] = {128, 64, 32, 16, 8};\n\n // The default tileSizeQ.\n int defaultTileSizeQ = selectKernelParamsCopy.mTileSizeQ;\n // The selected tileSizeQ.\n int selectedTileSizeQ = selectKernelParamsCopy.mTileSizeQ;\n\n // The minimum modeling kernel time.\n float globalModelingKernelTime = FLT_MAX;\n // Loop over each candidate tile size.\n for (int tileSizeQ : candidateTileSizesQ) {\n // Only consider candidates <= default tileSizeQ.\n if (tileSizeQ > defaultTileSizeQ) {\n continue;\n }\n\n selectKernelParamsCopy.mTileSizeQ = tileSizeQ;\n if (tileSizeQ >= 64) {\n selectKernelParamsCopy.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n } else {\n selectKernelParamsCopy.mKernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n }\n\n // Load the kernel.\n std::tie(func, kernelMeta) = loadKernel(params, selectKernelParamsCopy);\n\n // Compute the number of CTAs.\n computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParamsCopy);\n\n // Compute the seqLenPerCtaKv.\n int32_t seqLenPerCtaKv =\n flashinfer::ceil_div(flashinfer::ceil_div(params.mMaxSeqLenKv, kernelMeta.mStepKv),\n ctaLaunchParams.mMaxNumCtasKv) *\n kernelMeta.mStepKv;\n\n // Compute the modeling kernel time = mainloop cost + reduction cost.\n float modelingKernelTime = kernelMainloopCost.at(tileSizeQ) * seqLenPerCtaKv +\n kernelReductionCost.at(tileSizeQ) * kernelReductionSeqLenFactor *\n ctaLaunchParams.mMaxNumCtasKv;\n\n // Compute the total number of CTAs.\n int32_t numCtas =\n ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ;\n // Compute the number of waves.\n int32_t numWaves = flashinfer::ceil_div(numCtas, params.mMultiProcessorCount);\n // Compute the total modeling kernel time.\n modelingKernelTime *= numWaves;\n\n // If this candidate has a lower time than the global minimum, update the global minimum.\n if (modelingKernelTime < globalModelingKernelTime) {\n globalModelingKernelTime = modelingKernelTime;\n selectedTileSizeQ = tileSizeQ;\n }\n }\n\n // Update the tileSizeQ.\n selectKernelParams.mTileSizeQ = selectedTileSizeQ;\n // Update the kernel type.\n if (selectKernelParams.mTileSizeQ >= 64) {\n selectKernelParams.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n } else {\n selectKernelParams.mKernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n }\n }\n\n // Selects a heuristic kernel for GQA generation.\n void selectGqGenerationKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // The kernel type.\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n // The tile size for Q.\n int& tileSizeQ = selectKernelParams.mTileSizeQ;\n\n // Mixed precision kernels don't work with groupsTokensHeadsQ = true for now.\n if (mDtypeQ != mDtypeKv || mDtypeOut == DATA_TYPE_E2M1) {\n tileSizeQ = params.mNumHeadsQPerKv <= 8 ? 8 : 16;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n return;\n }\n\n // The number of tokensQ and headsQ that can be grouped into one CTA.\n int numTokensHeadsQ = params.mNumHeadsQPerKv * params.mMaxSeqLenQ;\n // When numHeadsQPerKv >= 64, use KeepsMmaAbForGeneration kernel.\n if (numTokensHeadsQ <= 8) {\n tileSizeQ = 8;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else if (numTokensHeadsQ <= 16) {\n tileSizeQ = 16;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else if (numTokensHeadsQ <= 32) {\n tileSizeQ = 32;\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else if (numTokensHeadsQ <= 64) {\n tileSizeQ = 64;\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n } else {\n tileSizeQ = 128;\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n }\n\n // When maxSeqLenQ > 1, use an experimental kernel-timing model to select the best kernel that\n // groups both tokensQ and headsQ into one CTA.\n if (params.mMaxSeqLenQ > 1) {\n selectTileSizeQForGqaGeneration(params, selectKernelParams);\n }\n }\n\n // Select a kernel based on the heuristic.\n void selectKernel(RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n // Select the kernel based on the kernel type.\n if (isGenerationKernel(params.mKernelType) && isMlaGenKernel(params)) {\n selectMlaGenerationKernel(params, selectKernelParams);\n } else if (isGenerationKernel(params.mKernelType)) {\n selectGqGenerationKernel(params, selectKernelParams);\n }\n\n // Enable sliding window or chunked causal if the max kv sequence length exceeds attention\n // window size or chunked attention size. This is supported by causal-mask context kernels and\n // generation-phase kernels.\n if ((selectKernelParams.mMaskType == TrtllmGenAttentionMaskType::Causal ||\n !isContextKernel(params.mKernelType)) &&\n (params.mMaxSeqLenKv > params.mAttentionWindowSize ||\n params.mChunkedAttentionSize != INT_MAX)) {\n FLASHINFER_CHECK(\n params.mMaxSeqLenKv <= params.mAttentionWindowSize ||\n params.mMaxSeqLenKv <= params.mChunkedAttentionSize,\n \"Sliding window attention and chunked attention should not be used together\");\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::SlidingOrChunkedCausal;\n }\n\n // SparseMla kernels use a fixed numTokensPerPage = 1.\n if (params.mSparseMla) {\n selectKernelParams.mNumTokensPerPage = 1;\n } else if (!isPagedKv(params.mQkvLayout)) {\n // NumTokensPerPage is set to 0 when not selecting pagedKv-layout kernels.\n selectKernelParams.mNumTokensPerPage = 0;\n }\n }\n\n std::pair<uint64_t, std::string> hashFromRunnerParams(\n RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n // Debug info.\n std::string info =\n \"qkvLayout=\" + std::to_string(static_cast<int>(params.mQkvLayout)) +\n \", maskType=\" + std::to_string(static_cast<int>(selectKernelParams.mMaskType)) +\n \", kernelType=\" + std::to_string(static_cast<int>(selectKernelParams.mKernelType)) +\n \", tileScheduler=\" + std::to_string(static_cast<int>(selectKernelParams.mTileScheduler)) +\n \", multiCtasKvMode=\" +\n std::to_string(static_cast<int>(selectKernelParams.mMultiCtasKvMode)) +\n \", headDimPerCtaV=\" + std::to_string(selectKernelParams.mHeadDimPerCtaV) +\n \", headDimQk=\" + std::to_string(params.mHeadDimQk) +\n \", headDimV=\" + std::to_string(params.mHeadDimV) +\n \", tileSizeQ=\" + std::to_string(selectKernelParams.mTileSizeQ) +\n \", tileSizeKv=\" + std::to_string(selectKernelParams.mTileSizeKv) +\n \", numTokensPerPage=\" + std::to_string(selectKernelParams.mNumTokensPerPage) +\n \", reuseSmemKForV=\" + std::to_string(selectKernelParams.mReuseSmemKForV) +\n \", uses2CtaMma=\" + std::to_string(selectKernelParams.mUses2CtaMma) +\n \", sparseMla=\" + std::to_string(params.mSparseMla);\n IKL_LOG_DEBUG(\n \"Searching for kernel traits (%d available) in TllmGenFmhaKernel(%s, %s, %s, %d) %s\",\n getNumLoadedKernels(), toStr(mDtypeQ), toStr(mDtypeKv), toStr(mDtypeOut), mSM,\n info.c_str());\n\n return std::make_pair(\n hashID(static_cast<int>(params.mQkvLayout), static_cast<int>(selectKernelParams.mMaskType),\n static_cast<int>(selectKernelParams.mKernelType),\n static_cast<int>(selectKernelParams.mTileScheduler),\n static_cast<int>(selectKernelParams.mMultiCtasKvMode),\n selectKernelParams.mHeadDimPerCtaV, params.mHeadDimQk, params.mHeadDimV,\n selectKernelParams.mTileSizeQ, selectKernelParams.mTileSizeKv,\n selectKernelParams.mNumTokensPerPage, selectKernelParams.mReuseSmemKForV,\n selectKernelParams.mUses2CtaMma, params.mSparseMla),\n info);\n }\n\n // Load a single kernel (called by `run()` when needed).\n std::pair<CUfunction, KernelMeta> loadKernel(RunnerParams const& params,\n SelectKernelParams& selectKernelParams) const {\n // Hash the runner params.\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n auto const findMetaIter = mKernelMetaMap.find(hashId);\n // The meta index.\n auto const metaIndex = findMetaIter->second;\n\n // Add debug info when kernels are not found.\n FLASHINFER_CHECK(findMetaIter != mKernelMetaMap.end(), \"Trtllm-gen kernels not found: \" + info);\n\n // Load the function if not found.\n if (mFunctions.find(hashId) == mFunctions.end()) {\n // Load the kernel on-demand.\n auto const& kernelMeta = mKernelMeta[metaIndex];\n CUmodule hmod{0};\n std::string kernelName(kernelMeta.mFuncName);\n\n // Check if the module is already loaded.\n auto findModuleIter = mModules.find(kernelMeta.mFuncName);\n auto capitalizeFirst = [](std::string str) {\n if (!str.empty()) {\n str[0] = std::toupper(str[0]);\n }\n return str;\n };\n if (findModuleIter == mModules.end()) {\n // Load the module.\n std::string cubin_path = tllm_gen_fmha_cubin_path + \"/\" + kernelMeta.mFuncName + \".cubin\";\n std::string cubin = getCubin(cubin_path, kernelMeta.sha256);\n if (cubin.empty()) {\n throw std::runtime_error(\"Failed to load cubin for \" + kernelName);\n }\n cuErrCheck(cuModuleLoadData(&hmod, cubin.data()));\n mModules[kernelName] = hmod;\n } else {\n hmod = findModuleIter->second;\n }\n\n // Load the function.\n KernelInfo funcInfo;\n funcInfo.mMetaInfoIndex = metaIndex;\n cuErrCheck(cuModuleGetFunction(&funcInfo.mDeviceFunction, hmod, kernelMeta.mFuncName));\n\n if (kernelMeta.mSharedMemBytes >= 48 * 1024) {\n cuErrCheck(cuFuncSetAttribute(funcInfo.mDeviceFunction,\n CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES,\n kernelMeta.mSharedMemBytes));\n }\n\n // Cache the loaded function.\n mFunctions[hashId] = funcInfo;\n }\n\n // Retrieve the loaded kernel.\n auto const& kernelInfo = mFunctions.at(hashId);\n auto const& kernelMeta = mKernelMeta[kernelInfo.mMetaInfoIndex];\n CUfunction func = kernelInfo.mDeviceFunction;\n\n // Return the function and kernelMeta.\n return std::make_pair(func, kernelMeta);\n }\n\n Data_type mDtypeQ, mDtypeKv, mDtypeOut;\n KernelMeta const* mKernelMeta;\n unsigned int mKernelMetaCount;\n unsigned int mSM;\n mutable std::unordered_map<std::string, CUmodule> mModules;\n\n mutable std::unordered_map<uint64_t, unsigned int> mKernelMetaMap;\n\n struct KernelInfo {\n unsigned int mMetaInfoIndex;\n CUfunction mDeviceFunction;\n };\n\n mutable std::unordered_map<uint64_t, KernelInfo> mFunctions;\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\nclass TllmFmhaKernelFactory {\n public:\n using KernelType = TllmGenFmhaKernel;\n\n KernelType const* getKernels(const typename KernelType::KernelMeta* pKernelList,\n unsigned int nbKernels, Data_type dtypeQ, Data_type dtypeKv,\n Data_type dtypeOut, unsigned int sm) {\n static std::mutex s_mutex;\n std::lock_guard<std::mutex> lg(s_mutex);\n\n auto const id = hashID(dtypeQ, dtypeKv, dtypeOut, sm);\n auto const findIter = mKernels.find(id);\n if (findIter == mKernels.end()) {\n KernelType* newKernel = new KernelType{pKernelList, nbKernels, dtypeQ, dtypeKv, dtypeOut, sm};\n newKernel->loadKernels();\n mKernels.insert(std::make_pair(id, std::unique_ptr<KernelType>(newKernel)));\n IKL_LOG_DEBUG(\n \"Loading new kernel for dtypeQ=%s, dtypeKv=%s, dtypeOut=%s, sm=%d with %d loaded kernels\",\n toStr(dtypeQ), toStr(dtypeKv), toStr(dtypeOut), sm, newKernel->getNumLoadedKernels());\n return newKernel;\n }\n return findIter->second.get();\n }\n\n static TllmFmhaKernelFactory& Get() {\n int deviceId;\n cudaGetDevice(&deviceId);\n static std::unique_ptr<TllmFmhaKernelFactory> sFactory[32] = {nullptr};\n if (sFactory[deviceId] == nullptr) {\n FLASHINFER_CHECK(deviceId < 32, \"Invalid deviceId %d (max is 32 devices)\", deviceId);\n sFactory[deviceId] = std::make_unique<TllmFmhaKernelFactory>(TllmFmhaKernelFactory());\n }\n\n return *(sFactory[deviceId]);\n }\n\n private:\n TllmFmhaKernelFactory() = default;\n\n inline uint64_t hashID(Data_type dtypeQ, Data_type dtypeKv, Data_type dtypeOut,\n unsigned int sm) const {\n return static_cast<uint64_t>(sm) | static_cast<uint64_t>(dtypeQ) << 16 |\n static_cast<uint64_t>(dtypeKv) << 20 | static_cast<uint64_t>(dtypeOut) << 24;\n }\n\n std::unordered_map<uint64_t, const std::unique_ptr<KernelType>> mKernels;\n};\n\ninline TllmGenFmhaKernel const* getTllmFmhaKernels(Data_type dtypeQ, Data_type dtypeKv,\n Data_type dtypeOut, unsigned int sm) {\n#ifndef EXCLUDE_SM_100\n return TllmFmhaKernelFactory::Get().getKernels(\n tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos,\n sizeof(tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos) /\n sizeof(tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos[0]),\n dtypeQ, dtypeKv, dtypeOut, sm);\n#else\n return nullptr;\n#endif // EXCLUDE_SM_100\n}\n"},"diff":{"kind":"string","value":"--- include/flashinfer/trtllm/fmha/fmhaKernels.cuh\n+++ include/flashinfer/trtllm/fmha/fmhaKernels.cuh\n@@ -19,6 +19,7 @@\n #include <cuda.h>\n \n #include <cstdint>\n+#include <cuda/std/cfloat>\n #include <iterator>\n #include <memory>\n #include <mutex>\n@@ -51,6 +52,16 @@\n } // namespace flashinfer::trtllm_cubin_loader\n using flashinfer::trtllm_cubin_loader::getCubin;\n \n+// Check if two SM values are family/specific versions of the same architecture\n+// Returns true only if one is a family version and the other is a compatible specific version\n+constexpr bool isFamilySpecificSMPair(int sm1, int sm2) {\n+ if ((sm1 == kSM_100f && (sm2 == kSM_100 || sm2 == kSM_103)) ||\n+ (sm2 == kSM_100f && (sm1 == kSM_100 || sm1 == kSM_103))) {\n+ return true;\n+ }\n+ return false;\n+}\n+\n constexpr bool isSMCompatible(int gpuSM, int kernelSM) {\n if (gpuSM == kSM_103) {\n return kernelSM == kSM_100f || kernelSM == kSM_103;\n@@ -63,6 +74,24 @@\n \n ////////////////////////////////////////////////////////////////////////////////////////////////////\n class TllmGenFmhaKernel {\n+ public:\n+ // The parameters for launching the kernel.\n+ // maxNumCtasQ, maxNumCtasKv, numCtasX, numCtasY, numCtasZ, clusterDimX\n+ struct CtaLaunchParams {\n+ // The maximum number of CTAs in Q dimension.\n+ int mMaxNumCtasQ;\n+ // The maximum number of CTAs in Kv dimension.\n+ int mMaxNumCtasKv;\n+ // The number of CTAs in X dimension.\n+ int mNumCtasX;\n+ // The number of CTAs in Y dimension.\n+ int mNumCtasY;\n+ // The number of CTAs in Z dimension.\n+ int mNumCtasZ;\n+ // The cluster size in the X dimension.\n+ int mClusterDimX;\n+ };\n+\n public:\n using KernelMeta = tensorrt_llm::kernels::TllmGenFmhaKernelMetaInfo;\n using RunnerParams = TllmGenFmhaRunnerParams;\n@@ -86,7 +115,23 @@\n kernelMeta.mDataTypeKv == mDtypeKv && kernelMeta.mDataTypeO == mDtypeOut) {\n // Store metadata for later use.\n IKL_LOG_DEBUG(\"Adding tllmgen attention kernel %s\", kernelMeta.mFuncName);\n- mKernelMetaMap[hashID(kernelMeta)] = i;\n+ // Check for hash conflicts.\n+ uint64_t hash = hashID(kernelMeta);\n+ if (mKernelMetaMap.find(hash) != mKernelMetaMap.end()) {\n+ // The kernelMeta of the existing kernel.\n+ auto const& existingKernelMeta = mKernelMeta[mKernelMetaMap.at(hash)];\n+ // Allow conflicts only if they are family/specific versions of the same architecture.\n+ FLASHINFER_CHECK(isFamilySpecificSMPair(existingKernelMeta.mSM, kernelMeta.mSM),\n+ \"Hash conflicts exist between %s and %s.\", existingKernelMeta.mFuncName,\n+ kernelMeta.mFuncName);\n+\n+ // Prefer specific SM version over family version (replace if existing is family).\n+ if (existingKernelMeta.mSM == kSM_100f) {\n+ mKernelMetaMap[hash] = i;\n+ }\n+ } else {\n+ mKernelMetaMap[hash] = i;\n+ }\n }\n }\n }\n@@ -95,8 +140,8 @@\n \n inline uint64_t hashID(int qkvLayout, int maskType, int kernelType, int scheduler,\n int multiCtasKvMode, int headDimPerCtaV, int headDimQk, int headDimV,\n- int tileSizeKv, int numTokensPerPage, int maxNumHeadsQPerKvInCta,\n- bool reuseSmemKForV, bool uses2CtaMma, bool sparseMla) const {\n+ int tileSizeQ, int tileSizeKv, int numTokensPerPage, bool reuseSmemKForV,\n+ bool uses2CtaMma, bool sparseMla) const {\n FLASHINFER_CHECK((headDimPerCtaV >= 32) && (headDimQk >= 32) && (headDimV >= 32) &&\n (headDimPerCtaV <= 1024) && (headDimQk <= 1024) && (headDimV <= 1024),\n \"Expect (32 <= headDim <= 1024), got headDimPerCtaV=%d, headDimQk=%d, \"\n@@ -105,8 +150,10 @@\n // The numTokensPerPage must be power of 2.\n FLASHINFER_CHECK((numTokensPerPage & (numTokensPerPage - 1)) == 0,\n \"The numTokensPerPage must be power of 2.\");\n- FLASHINFER_CHECK(maxNumHeadsQPerKvInCta <= 128,\n- \"The maxNumHeadsQPerKvInCta <= 128 is required.\");\n+ FLASHINFER_CHECK(tileSizeQ <= 128 && tileSizeKv <= 128,\n+ \"The tileSizeQ and tileSizeKv must be <= 128.\");\n+ FLASHINFER_CHECK((tileSizeQ & (tileSizeQ - 1)) == 0 && (tileSizeKv & (tileSizeKv - 1)) == 0,\n+ \"The tileSizeQ and tileSizeKv must be power of 2.\");\n FLASHINFER_CHECK(tileSizeKv == 64 || tileSizeKv == 128, \"The tileSizeKv must be 64 or 128.\");\n // Format of the hash key:\n // Bit 0 - 3 : qkvLayout.\n@@ -119,10 +166,10 @@\n // Bit 34 - 41: (headDimV >> 3).\n // Bit 42 - 43: (tileSizeKv >> 6).\n // Bit 44 - 48: (log2(numTokensPerPage)).\n- // Bit 49 - 56: maxNumHeadsQPerKvInCta.\n- // Bit 57 - 57: reuseSmemKForV.\n- // Bit 58 - 58: uses2CtaMma.\n- // Bit 59 - 59: sparseMla.\n+ // Bit 49 - 52: (log2(tileSizeQ)).\n+ // Bit 53 - 53: reuseSmemKForV.\n+ // Bit 54 - 54: uses2CtaMma.\n+ // Bit 55 - 55: sparseMla.\n return (static_cast<uint64_t>(qkvLayout) << 0) | (static_cast<uint64_t>(maskType) << 4) |\n (static_cast<uint64_t>(kernelType) << 8) | (static_cast<uint64_t>(scheduler) << 12) |\n (static_cast<uint64_t>(multiCtasKvMode) << 16) |\n@@ -131,30 +178,35 @@\n (static_cast<uint64_t>(headDimV >> 3) << 34) |\n (static_cast<uint64_t>(tileSizeKv >> 6) << 42) |\n (static_cast<uint64_t>(log2(numTokensPerPage)) << 44) |\n- (static_cast<uint64_t>(maxNumHeadsQPerKvInCta) << 49) |\n- (static_cast<uint64_t>(reuseSmemKForV) << 57) |\n- (static_cast<uint64_t>(uses2CtaMma) << 58) | (static_cast<uint64_t>(sparseMla) << 59);\n+ (static_cast<uint64_t>(log2(tileSizeQ)) << 49) |\n+ (static_cast<uint64_t>(reuseSmemKForV) << 53) |\n+ (static_cast<uint64_t>(uses2CtaMma) << 54) | (static_cast<uint64_t>(sparseMla) << 55);\n }\n \n uint64_t hashID(KernelMeta const& kernelMeta) const {\n return hashID(kernelMeta.mQkvLayout, kernelMeta.mMaskType, kernelMeta.mKernelType,\n kernelMeta.mTileScheduler, kernelMeta.mMultiCtasKvMode,\n kernelMeta.mHeadDimPerCtaV, kernelMeta.mHeadDimQk, kernelMeta.mHeadDimV,\n- kernelMeta.mTileSizeKv, kernelMeta.mNumTokensPerPage,\n- kernelMeta.mMaxNumHeadsQPerKvInCta, kernelMeta.mReuseSmemKForV,\n- kernelMeta.m2CtaMma, kernelMeta.mSparseMla);\n+ kernelMeta.mTileSizeQ, kernelMeta.mTileSizeKv, kernelMeta.mNumTokensPerPage,\n+ kernelMeta.mReuseSmemKForV, kernelMeta.m2CtaMma, kernelMeta.mSparseMla);\n }\n \n std::pair<bool, std::string> checkIfKernelExist(RunnerParams const& params) const {\n // The selectKernelParams that might be updated.\n SelectKernelParams selectKernelParams{params};\n+ // Select the kernel.\n+ selectKernel(params, selectKernelParams);\n+ // Hash the runner params.\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n return std::make_pair(mKernelMetaMap.find(hashId) != mKernelMetaMap.end(), info);\n }\n+\n // start here\n void run(RunnerParams const& params) const {\n // The selectKernelParams that might be updated.\n SelectKernelParams selectKernelParams{params};\n+ // The parameters for launching the kernel.\n+ CtaLaunchParams ctaLaunchParams;\n // The iteration index (used to detect a deadlock of selecting new kernels).\n int selectKernelIter = 0;\n // While loop.\n@@ -163,27 +215,15 @@\n // might have more complicated heuristic in the future.\n FLASHINFER_CHECK(selectKernelIter < 8,\n \"A deadlock is detected when selecting trtllm-gen kernels.\");\n- auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n- auto const findMetaIter = mKernelMetaMap.find(hashId);\n-\n- // Add debug info when kernels are not found.\n- FLASHINFER_CHECK(findMetaIter != mKernelMetaMap.end(),\n- \"Trtllm-gen kernels not found: \" + info);\n-\n- // auto const& kernelMeta = mKernelMeta[findIter->second.mMetaInfoIndex];\n- auto const findFuncIter = mFunctions.find(hashId);\n- if (findFuncIter == mFunctions.end()) {\n- // Load the kernel on-demand.\n- loadKernel(hashId, findMetaIter->second);\n- }\n- // Retrieve the loaded kernel.\n- auto const& kernelInfo = mFunctions.at(hashId);\n- auto const& kernelMeta = mKernelMeta[kernelInfo.mMetaInfoIndex];\n- CUfunction func = kernelInfo.mDeviceFunction;\n+\n+ // Select the kernel.\n+ selectKernel(params, selectKernelParams);\n+ // Load the kernel.\n+ auto [func, kernelMeta] = loadKernel(params, selectKernelParams);\n \n // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension.\n- auto [maxNumCtasQ, maxNumCtasKv, numCtasX, numCtasY, numCtasZ, clusterDimX] =\n- computeCtaAndClusterConfig(params, kernelMeta, selectKernelParams);\n+ computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParams);\n+\n // Need to select a new kernel if mSelectNewKernel is true.\n if (selectKernelParams.mSelectNewKernel) {\n selectKernelIter++;\n@@ -191,8 +231,8 @@\n }\n \n // Prepare the kernel parameters.\n- auto kernelParams =\n- KernelParams::setKernelParams(params, kernelMeta, maxNumCtasQ, maxNumCtasKv);\n+ auto kernelParams = KernelParams::setKernelParams(\n+ params, kernelMeta, ctaLaunchParams.mMaxNumCtasQ, ctaLaunchParams.mMaxNumCtasKv);\n \n // Prepare kernel parameters list for cuLaunchKernelEx.\n void* kernelParamsList[] = {&kernelParams};\n@@ -200,9 +240,9 @@\n launch_config.blockDimX = kernelMeta.mThreadsPerCTA;\n launch_config.blockDimY = 1;\n launch_config.blockDimZ = 1;\n- launch_config.gridDimX = numCtasX;\n- launch_config.gridDimY = numCtasY;\n- launch_config.gridDimZ = numCtasZ;\n+ launch_config.gridDimX = ctaLaunchParams.mNumCtasX;\n+ launch_config.gridDimY = ctaLaunchParams.mNumCtasY;\n+ launch_config.gridDimZ = ctaLaunchParams.mNumCtasZ;\n launch_config.hStream = params.stream;\n launch_config.sharedMemBytes = kernelMeta.mSharedMemBytes;\n \n@@ -218,24 +258,25 @@\n params.mBatchSize, static_cast<int>(params.mKernelType));\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: numCtasX = %d, numCtasY = %d, numCtasZ = %d, clusterDimX = %d\",\n- numCtasX, numCtasY, numCtasZ, clusterDimX);\n+ ctaLaunchParams.mNumCtasX, ctaLaunchParams.mNumCtasY, ctaLaunchParams.mNumCtasZ,\n+ ctaLaunchParams.mClusterDimX);\n \n CUlaunchAttribute launch_attribute[3];\n launch_attribute[0].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION;\n- launch_attribute[0].value.clusterDim.x = clusterDimX;\n+ launch_attribute[0].value.clusterDim.x = ctaLaunchParams.mClusterDimX;\n launch_attribute[0].value.clusterDim.y = 1;\n launch_attribute[0].value.clusterDim.z = 1;\n launch_attribute[1].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE;\n launch_attribute[1].value.clusterSchedulingPolicyPreference =\n- clusterDimX > 1 ? CU_CLUSTER_SCHEDULING_POLICY_SPREAD\n- : CU_CLUSTER_SCHEDULING_POLICY_DEFAULT;\n+ ctaLaunchParams.mClusterDimX > 1 ? CU_CLUSTER_SCHEDULING_POLICY_SPREAD\n+ : CU_CLUSTER_SCHEDULING_POLICY_DEFAULT;\n launch_attribute[2].id = CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION;\n launch_attribute[2].value.programmaticStreamSerializationAllowed = params.enable_pdl;\n \n launch_config.attrs = launch_attribute;\n launch_config.numAttrs = 3;\n // Add setting for non-portable cluster size.\n- if (clusterDimX > 8) {\n+ if (ctaLaunchParams.mClusterDimX > 8) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED,\n 1 // Enable non-portable cluster sizes\n ));\n@@ -249,7 +290,8 @@\n int maxActiveClusters = 1;\n cuErrCheck(cuOccupancyMaxActiveClusters(&maxActiveClusters, func, &launch_config));\n // Use the GmemReduction instead if it needs more than one wave.\n- if (maxActiveClusters * clusterDimX < (numCtasX * numCtasY * numCtasZ)) {\n+ if (maxActiveClusters * ctaLaunchParams.mClusterDimX <\n+ (ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ)) {\n selectKernelParams.mForceGmemReduction = true;\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReduction;\n // continue to select a new kernel.\n@@ -279,11 +321,9 @@\n }\n \n // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension.\n- using CtaClusterInfo = std::tuple<int, int, int, int, int, int>;\n-\n- CtaClusterInfo computeCtaAndClusterConfig(RunnerParams const& params,\n- KernelMeta const& kernelMeta,\n- SelectKernelParams& selectKernelParams) const {\n+ void computeCtaAndClusterConfig(CtaLaunchParams& ctaLaunchParams, RunnerParams const& params,\n+ KernelMeta const& kernelMeta,\n+ SelectKernelParams& selectKernelParams) const {\n bool isDsv3MinLatencyMode = params.mBatchSize == 1 && params.mMaxSeqLenQ >= 1 &&\n params.mMaxSeqLenQ <= 16 && params.mHeadDimQk == 576 &&\n params.mHeadDimV == 512;\n@@ -292,17 +332,23 @@\n \n // The number of Ctas per Q sequence.\n int numCtasPerSeqQ = (params.mMaxSeqLenQ + kernelMeta.mStepQ - 1) / kernelMeta.mStepQ;\n- // Each CTA handles one tokenQ by default for spec-decoding generation kernel, which is used to\n- // emulate causal masking (like MTP or Eagle3). Note this will be changed later when the\n- // high-throughput spec-decoding generation kernels are integrated.\n+ // The generation-phase kernels might need to group both tokensQ and headsQ into one CTA.\n if (params.mMaxSeqLenQ > 1 && !isContextKernel(params.mKernelType)) {\n- numCtasPerSeqQ = params.mMaxSeqLenQ;\n+ // Each CTA handles one tokenQ by default for spec-decoding generation kernel.\n+ if (!kernelMeta.mGroupsTokensHeadsQ) {\n+ numCtasPerSeqQ = params.mMaxSeqLenQ;\n+ } else {\n+ // Compute numTokensPerCtaQ where each CTA must process complete numGroupedHeadsQ.\n+ // Note that each CTA must process complete numHeadsQPerKv.\n+ int numTokensPerCtaQ = kernelMeta.mStepQ / params.mNumHeadsQPerKv;\n+ // Group both headsQ and tokensQ into one CTA.\n+ numCtasPerSeqQ = flashinfer::ceil_div(params.mMaxSeqLenQ, numTokensPerCtaQ);\n+ }\n }\n \n // Compute the grid dimension Y.\n- int numHeadsPerCta = kernelMeta.mGroupsHeadsQ\n- ? std::min(params.mNumHeadsQPerKv, kernelMeta.mMaxNumHeadsQPerKvInCta)\n- : 1;\n+ int numHeadsPerCta =\n+ kernelMeta.mGroupsHeadsQ ? std::min(params.mNumHeadsQPerKv, kernelMeta.mStepQ) : 1;\n int numCtasForAllHeadsQ = params.mNumHeadsQ / numHeadsPerCta;\n FLASHINFER_CHECK(numHeadsPerCta * numCtasForAllHeadsQ == params.mNumHeadsQ,\n \"The numHeadsQ/numHeadsKv is not supported.\");\n@@ -351,8 +397,10 @@\n }\n \n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n+ // The factor of 2 is applied here to ensure the reduction overhead does not outweigh the\n+ // benefits of a shorter mainloop.\n int const maxNumCtasPerSeqKv =\n- (maxAttentionWindow + kernelMeta.mStepKv - 1) / kernelMeta.mStepKv;\n+ (maxAttentionWindow + 2 * kernelMeta.mStepKv - 1) / (2 * kernelMeta.mStepKv);\n // Compute numCtasPerSeqKv.\n numCtasPerSeqKv = std::min(\n maxNumCtasPerSeqKv,\n@@ -427,9 +475,13 @@\n }\n }\n \n- // Return the number of CTAs for X, Y and Z dimension and the cluster size in the X dimension.\n- return std::make_tuple(numCtasPerSeqQ, numCtasPerSeqKv, numCtasX, numCtasY, numCtasZ,\n- clusterDimX);\n+ // Update the parameters for launching the kernel.\n+ ctaLaunchParams.mMaxNumCtasQ = numCtasPerSeqQ;\n+ ctaLaunchParams.mMaxNumCtasKv = numCtasPerSeqKv;\n+ ctaLaunchParams.mNumCtasX = numCtasX;\n+ ctaLaunchParams.mNumCtasY = numCtasY;\n+ ctaLaunchParams.mNumCtasZ = numCtasZ;\n+ ctaLaunchParams.mClusterDimX = clusterDimX;\n }\n \n // Determine if we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n@@ -447,7 +499,7 @@\n ;\n // The number of Ctas.\n int const numCtas = static_cast<int32_t>(params.mBatchSize * params.mMaxSeqLenQ *\n- divUp(params.mNumHeadsQPerKv, 16));\n+ flashinfer::ceil_div(params.mNumHeadsQPerKv, 16));\n // Compute numCtasPerSeqKv.\n int const numCtasPerSeqKv =\n std::min(maxNumCtasPerSeqKv, std::max(1, int32_t(params.mMultiProcessorCount / numCtas)));\n@@ -457,71 +509,213 @@\n return seqLenPerCtaKv <= 1024 && numCtas <= params.mMultiProcessorCount;\n }\n \n- std::pair<uint64_t, std::string> hashFromRunnerParams(\n- RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n- // The updated kernel type.\n+ // Select the MLA generation kernel.\n+ void selectMlaGenerationKernel(RunnerParams const& params,\n+ SelectKernelParams& selectKernelParams) const {\n+ // We use the low-latency kernel (SwapsMmaAbForGeneration with tileSizeQ = 16) when any of the\n+ // following conditions are met:\n+ // 1. The number of headsQPerKv is <= 32.\n+ // 2. The number of headsQPerKv is < 128 for sparseMla.\n+ // 3. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned later)\n+ // and\n+ // the numCtas (after splitting the heads across multiple CTAs) <=\n+ // params.mMultiProcessorCount.\n+ // The sparseMla kernel will always use the 2CTA high-throughput kernel.\n+\n+ // The kernel type.\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n- // Generation kernelType will use either SwapsMmaAbForGeneration or KeepsMmaAbForGeneration.\n+ // The tile size for Q.\n+ int& tileSizeQ = selectKernelParams.mTileSizeQ;\n+\n+ // Check the conditions.\n+ if (params.mNumHeadsQPerKv <= 32 || (params.mSparseMla && params.mNumHeadsQPerKv < 128) ||\n+ useSwapsMmaAbMlaGenKernel(params)) {\n+ kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n+ // Currently, only tileSizeQ = 8 or 16 are supported.\n+ tileSizeQ = params.mNumHeadsQPerKv <= 8 ? 8 : 16;\n+ } else {\n+ // Otherwise, we use the high-throughput kernel.\n+ kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n+ // Use the tileSizeQ = 64 for MLA high-throughput generation kernels.\n+ tileSizeQ = 64;\n+ // Always use the separate reduction kernel.\n+ if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n+ selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n+ }\n+ // The keepsMmaAbForGeneration sparseMla kernels only support numHeadsQPerKv = 128.\n+ FLASHINFER_CHECK(\n+ !params.mSparseMla || params.mNumHeadsQPerKv == 128,\n+ \"The keepsMmaAbForGeneration sparseMla kernels only support numHeadsQPerKv = 128, got %d\",\n+ params.mNumHeadsQPerKv);\n+ // The 2CTA keepsMmaAbForGeneration kernel is used when the numHeadsQPerKv is 128.\n+ if (params.mNumHeadsQPerKv == 128) {\n+ selectKernelParams.mUses2CtaMma = true;\n+ // Each Cta only handles 256 headDimV.\n+ selectKernelParams.mHeadDimPerCtaV = 256;\n+ }\n+ }\n+ }\n+\n+ // Selects a heuristic tileSizeQ if groupsTokensHeadsQ is true.\n+ void selectTileSizeQForGqaGeneration(RunnerParams const& params,\n+ SelectKernelParams& selectKernelParams) const {\n+ // Define the per-tile mainloop cost model for different tileSizeQ choices.\n+ std::unordered_map<int, float> kernelMainloopCost = {\n+ {128, 2.2}, // Cost factor when tileSizeQ = 128\n+ {64, 1.68}, // Cost factor when tileSizeQ = 64\n+ {32, 1.48}, // Cost factor when tileSizeQ = 32\n+ {16, 1.2}, // Cost factor when tileSizeQ = 16\n+ {8, 1.0} // Cost factor when tileSizeQ = 8\n+ };\n+\n+ // Define the per-tile reduction cost model for different tileSizeQ choices.\n+ std::unordered_map<int, float> kernelReductionCost = {\n+ {128, 1.32}, // Reduction cost factor when tileSizeQ = 128\n+ {64, 1.2}, // Reduction cost factor when tileSizeQ = 64\n+ {32, 1.08}, // Reduction cost factor when tileSizeQ = 32\n+ {16, 1.03}, // Reduction cost factor when tileSizeQ = 16\n+ {8, 1.0} // Reduction cost factor when tileSizeQ = 8\n+ };\n+\n+ // The reduction cost emulated as a sequence length factor.\n+ float const kernelReductionSeqLenFactor = 128.0f;\n+\n+ // The parameters for launching the kernel.\n+ CtaLaunchParams ctaLaunchParams;\n+ // The copy of the selectKernelParams, which makes sure it won't modify the original\n+ // selectKernelParams when computing the number of CTAs.\n+ SelectKernelParams selectKernelParamsCopy = selectKernelParams;\n+ // Load the kernel.\n+ auto [func, kernelMeta] = loadKernel(params, selectKernelParamsCopy);\n+ // Compute numCtasX, numCtasY and numCtasZ.\n+ computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParamsCopy);\n+\n+ // If there are no free SMs or tileSizeQ is already the smallest one, skip the heuristic\n+ // selection.\n+ if (ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ * 2 >\n+ params.mMultiProcessorCount ||\n+ selectKernelParamsCopy.mTileSizeQ <= 8) {\n+ // No need to select the kernel further.\n+ return;\n+ }\n+\n+ // Candidate tile sizes for tileSizeQ to explore.\n+ int const candidateTileSizesQ[] = {128, 64, 32, 16, 8};\n+\n+ // The default tileSizeQ.\n+ int defaultTileSizeQ = selectKernelParamsCopy.mTileSizeQ;\n+ // The selected tileSizeQ.\n+ int selectedTileSizeQ = selectKernelParamsCopy.mTileSizeQ;\n+\n+ // The minimum modeling kernel time.\n+ float globalModelingKernelTime = FLT_MAX;\n+ // Loop over each candidate tile size.\n+ for (int tileSizeQ : candidateTileSizesQ) {\n+ // Only consider candidates <= default tileSizeQ.\n+ if (tileSizeQ > defaultTileSizeQ) {\n+ continue;\n+ }\n+\n+ selectKernelParamsCopy.mTileSizeQ = tileSizeQ;\n+ if (tileSizeQ >= 64) {\n+ selectKernelParamsCopy.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n+ } else {\n+ selectKernelParamsCopy.mKernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n+ }\n+\n+ // Load the kernel.\n+ std::tie(func, kernelMeta) = loadKernel(params, selectKernelParamsCopy);\n+\n+ // Compute the number of CTAs.\n+ computeCtaAndClusterConfig(ctaLaunchParams, params, kernelMeta, selectKernelParamsCopy);\n+\n+ // Compute the seqLenPerCtaKv.\n+ int32_t seqLenPerCtaKv =\n+ flashinfer::ceil_div(flashinfer::ceil_div(params.mMaxSeqLenKv, kernelMeta.mStepKv),\n+ ctaLaunchParams.mMaxNumCtasKv) *\n+ kernelMeta.mStepKv;\n+\n+ // Compute the modeling kernel time = mainloop cost + reduction cost.\n+ float modelingKernelTime = kernelMainloopCost.at(tileSizeQ) * seqLenPerCtaKv +\n+ kernelReductionCost.at(tileSizeQ) * kernelReductionSeqLenFactor *\n+ ctaLaunchParams.mMaxNumCtasKv;\n+\n+ // Compute the total number of CTAs.\n+ int32_t numCtas =\n+ ctaLaunchParams.mNumCtasX * ctaLaunchParams.mNumCtasY * ctaLaunchParams.mNumCtasZ;\n+ // Compute the number of waves.\n+ int32_t numWaves = flashinfer::ceil_div(numCtas, params.mMultiProcessorCount);\n+ // Compute the total modeling kernel time.\n+ modelingKernelTime *= numWaves;\n+\n+ // If this candidate has a lower time than the global minimum, update the global minimum.\n+ if (modelingKernelTime < globalModelingKernelTime) {\n+ globalModelingKernelTime = modelingKernelTime;\n+ selectedTileSizeQ = tileSizeQ;\n+ }\n+ }\n+\n+ // Update the tileSizeQ.\n+ selectKernelParams.mTileSizeQ = selectedTileSizeQ;\n+ // Update the kernel type.\n+ if (selectKernelParams.mTileSizeQ >= 64) {\n+ selectKernelParams.mKernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n+ } else {\n+ selectKernelParams.mKernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n+ }\n+ }\n+\n+ // Selects a heuristic kernel for GQA generation.\n+ void selectGqGenerationKernel(RunnerParams const& params,\n+ SelectKernelParams& selectKernelParams) const {\n+ // The kernel type.\n+ FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n+ // The tile size for Q.\n+ int& tileSizeQ = selectKernelParams.mTileSizeQ;\n+\n+ // Mixed precision kernels don't work with groupsTokensHeadsQ = true for now.\n+ if (mDtypeQ != mDtypeKv || mDtypeOut == DATA_TYPE_E2M1) {\n+ tileSizeQ = params.mNumHeadsQPerKv <= 8 ? 8 : 16;\n+ kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n+ return;\n+ }\n+\n+ // The number of tokensQ and headsQ that can be grouped into one CTA.\n+ int numTokensHeadsQ = params.mNumHeadsQPerKv * params.mMaxSeqLenQ;\n+ // When numHeadsQPerKv >= 64, use KeepsMmaAbForGeneration kernel.\n+ if (numTokensHeadsQ <= 8) {\n+ tileSizeQ = 8;\n+ kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n+ } else if (numTokensHeadsQ <= 16) {\n+ tileSizeQ = 16;\n+ kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n+ } else if (numTokensHeadsQ <= 32) {\n+ tileSizeQ = 32;\n+ kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n+ } else if (numTokensHeadsQ <= 64) {\n+ tileSizeQ = 64;\n+ kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n+ } else {\n+ tileSizeQ = 128;\n+ kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n+ }\n+\n+ // When maxSeqLenQ > 1, use an experimental kernel-timing model to select the best kernel that\n+ // groups both tokensQ and headsQ into one CTA.\n+ if (params.mMaxSeqLenQ > 1) {\n+ selectTileSizeQForGqaGeneration(params, selectKernelParams);\n+ }\n+ }\n+\n+ // Select a kernel based on the heuristic.\n+ void selectKernel(RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n+ // Select the kernel based on the kernel type.\n if (isGenerationKernel(params.mKernelType) && isMlaGenKernel(params)) {\n- // We use the low-latency kernel (SwapsMmaAbForGeneration with tileSizeQ = 16) when any of the\n- // following conditions are met:\n- // 1. The number of headsQPerKv is <= 32.\n- // 2. The number of headsQPerKv is < 128 for sparseMla.\n- // 3. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned\n- // later) and\n- // the numCtas (after splitting the heads across multiple CTAs) <=\n- // params.mMultiProcessorCount.\n-\n- // Check the conditions.\n- if (params.mNumHeadsQPerKv <= 32 || (params.mSparseMla && params.mNumHeadsQPerKv < 128) ||\n- useSwapsMmaAbMlaGenKernel(params)) {\n- kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n- } else {\n- // Otherwise, we use the high-throughput kernel.\n- kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n- // Always use the separate reduction kernel.\n- if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n- selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n- }\n- // The keepsMmaAbForGeneration sparseMla kernels only support numHeadsQPerKv = 128.\n- FLASHINFER_CHECK(\n- !params.mSparseMla || params.mNumHeadsQPerKv == 128,\n- \"The keepsMmaAbForGeneration sparseMla kernels only support numHeadsQPerKv = 128\");\n- // The 2CTA keepsMmaAbForGeneration kernel is used when the numHeadsQPerKv is 128.\n- if (params.mNumHeadsQPerKv == 128) {\n- selectKernelParams.mUses2CtaMma = true;\n- // Each Cta only handles 256 headDimV.\n- selectKernelParams.mHeadDimPerCtaV = 256;\n- }\n- }\n+ selectMlaGenerationKernel(params, selectKernelParams);\n } else if (isGenerationKernel(params.mKernelType)) {\n- kernelType = (params.mNumHeadsQPerKv <= 16 && params.mHeadDimQk != 32)\n- ? FmhaKernelType::SwapsMmaAbForGeneration\n- : FmhaKernelType::KeepsMmaAbForGeneration;\n- }\n-\n- // The maximum number of headsQPerKv that the kernel can support in one Cta.\n- int maxNumHeadsQPerKvInCta = 1;\n- if (isSwapsMmaAbForGenerationKernel(kernelType)) {\n- // Set the corresponding maxNumHeadsQPerKvInCta (tileSizeQ) for low-latency generation\n- // kernels.\n- maxNumHeadsQPerKvInCta = (params.mNumHeadsQPerKv <= 8) ? 8 : 16;\n- FLASHINFER_CHECK((maxNumHeadsQPerKvInCta == 8 || maxNumHeadsQPerKvInCta == 16) &&\n- (params.mNumHeadsQPerKv < maxNumHeadsQPerKvInCta ||\n- params.mNumHeadsQPerKv % maxNumHeadsQPerKvInCta == 0),\n- \"Not supported\");\n- } else if (isKeepsMmaAbForGenerationKernel(kernelType)) {\n- // Use the maxNumHeadsQPerKvInCta (tileSizeQ) = 64 for MLA high-throughput generation kernels.\n- maxNumHeadsQPerKvInCta = isMlaGenKernel(params) ? 64 : 32;\n- FLASHINFER_CHECK((params.mNumHeadsQPerKv < maxNumHeadsQPerKvInCta ||\n- params.mNumHeadsQPerKv % maxNumHeadsQPerKvInCta == 0),\n- \"Not supported\");\n- } else if (isContextKernel(kernelType)) {\n- FLASHINFER_CHECK(maxNumHeadsQPerKvInCta == 1, \"Not supported\");\n- }\n-\n- // The mask type.\n- selectKernelParams.mMaskType = params.mMaskType;\n+ selectGqGenerationKernel(params, selectKernelParams);\n+ }\n+\n // Enable sliding window or chunked causal if the max kv sequence length exceeds attention\n // window size or chunked attention size. This is supported by causal-mask context kernels and\n // generation-phase kernels.\n@@ -536,30 +730,31 @@\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::SlidingOrChunkedCausal;\n }\n \n- // The number of tokens per page.\n- int numTokensPerPage = params.mNumTokensPerPage;\n // SparseMla kernels use a fixed numTokensPerPage = 1.\n if (params.mSparseMla) {\n- numTokensPerPage = 1;\n+ selectKernelParams.mNumTokensPerPage = 1;\n } else if (!isPagedKv(params.mQkvLayout)) {\n // NumTokensPerPage is set to 0 when not selecting pagedKv-layout kernels.\n- numTokensPerPage = 0;\n- }\n-\n+ selectKernelParams.mNumTokensPerPage = 0;\n+ }\n+ }\n+\n+ std::pair<uint64_t, std::string> hashFromRunnerParams(\n+ RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n // Debug info.\n std::string info =\n \"qkvLayout=\" + std::to_string(static_cast<int>(params.mQkvLayout)) +\n \", maskType=\" + std::to_string(static_cast<int>(selectKernelParams.mMaskType)) +\n- \", kernelType=\" + std::to_string(static_cast<int>(kernelType)) +\n+ \", kernelType=\" + std::to_string(static_cast<int>(selectKernelParams.mKernelType)) +\n \", tileScheduler=\" + std::to_string(static_cast<int>(selectKernelParams.mTileScheduler)) +\n \", multiCtasKvMode=\" +\n std::to_string(static_cast<int>(selectKernelParams.mMultiCtasKvMode)) +\n \", headDimPerCtaV=\" + std::to_string(selectKernelParams.mHeadDimPerCtaV) +\n \", headDimQk=\" + std::to_string(params.mHeadDimQk) +\n \", headDimV=\" + std::to_string(params.mHeadDimV) +\n+ \", tileSizeQ=\" + std::to_string(selectKernelParams.mTileSizeQ) +\n \", tileSizeKv=\" + std::to_string(selectKernelParams.mTileSizeKv) +\n- \", numTokensPerPage=\" + std::to_string(numTokensPerPage) +\n- \", maxNumHeadsQPerKvInCta=\" + std::to_string(maxNumHeadsQPerKvInCta) +\n+ \", numTokensPerPage=\" + std::to_string(selectKernelParams.mNumTokensPerPage) +\n \", reuseSmemKForV=\" + std::to_string(selectKernelParams.mReuseSmemKForV) +\n \", uses2CtaMma=\" + std::to_string(selectKernelParams.mUses2CtaMma) +\n \", sparseMla=\" + std::to_string(params.mSparseMla);\n@@ -570,55 +765,78 @@\n \n return std::make_pair(\n hashID(static_cast<int>(params.mQkvLayout), static_cast<int>(selectKernelParams.mMaskType),\n- static_cast<int>(kernelType), static_cast<int>(selectKernelParams.mTileScheduler),\n+ static_cast<int>(selectKernelParams.mKernelType),\n+ static_cast<int>(selectKernelParams.mTileScheduler),\n static_cast<int>(selectKernelParams.mMultiCtasKvMode),\n selectKernelParams.mHeadDimPerCtaV, params.mHeadDimQk, params.mHeadDimV,\n- selectKernelParams.mTileSizeKv, numTokensPerPage, maxNumHeadsQPerKvInCta,\n- selectKernelParams.mReuseSmemKForV, selectKernelParams.mUses2CtaMma,\n- params.mSparseMla),\n+ selectKernelParams.mTileSizeQ, selectKernelParams.mTileSizeKv,\n+ selectKernelParams.mNumTokensPerPage, selectKernelParams.mReuseSmemKForV,\n+ selectKernelParams.mUses2CtaMma, params.mSparseMla),\n info);\n }\n \n // Load a single kernel (called by `run()` when needed).\n- void loadKernel(uint64_t hashId, unsigned int metaIndex) const {\n- auto const& kernelMeta = mKernelMeta[metaIndex];\n- CUmodule hmod{0};\n- std::string kernelName(kernelMeta.mFuncName);\n-\n- // Check if the module is already loaded.\n- auto findModuleIter = mModules.find(kernelMeta.mFuncName);\n- auto capitalizeFirst = [](std::string str) {\n- if (!str.empty()) {\n- str[0] = std::toupper(str[0]);\n- }\n- return str;\n- };\n- if (findModuleIter == mModules.end()) {\n- // Load the module.\n- std::string cubin_path = tllm_gen_fmha_cubin_path + \"/\" + kernelMeta.mFuncName + \".cubin\";\n- std::string cubin = getCubin(cubin_path, kernelMeta.sha256);\n- if (cubin.empty()) {\n- throw std::runtime_error(\"Failed to load cubin for \" + kernelName);\n- }\n- cuErrCheck(cuModuleLoadData(&hmod, cubin.data()));\n- mModules[kernelName] = hmod;\n- } else {\n- hmod = findModuleIter->second;\n- }\n-\n- // Load the function.\n- KernelInfo funcInfo;\n- funcInfo.mMetaInfoIndex = metaIndex;\n- cuErrCheck(cuModuleGetFunction(&funcInfo.mDeviceFunction, hmod, kernelMeta.mFuncName));\n-\n- if (kernelMeta.mSharedMemBytes >= 48 * 1024) {\n- cuErrCheck(cuFuncSetAttribute(funcInfo.mDeviceFunction,\n- CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES,\n- kernelMeta.mSharedMemBytes));\n- }\n-\n- // Cache the loaded function.\n- mFunctions[hashId] = funcInfo;\n+ std::pair<CUfunction, KernelMeta> loadKernel(RunnerParams const& params,\n+ SelectKernelParams& selectKernelParams) const {\n+ // Hash the runner params.\n+ auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n+ auto const findMetaIter = mKernelMetaMap.find(hashId);\n+ // The meta index.\n+ auto const metaIndex = findMetaIter->second;\n+\n+ // Add debug info when kernels are not found.\n+ FLASHINFER_CHECK(findMetaIter != mKernelMetaMap.end(), \"Trtllm-gen kernels not found: \" + info);\n+\n+ // Load the function if not found.\n+ if (mFunctions.find(hashId) == mFunctions.end()) {\n+ // Load the kernel on-demand.\n+ auto const& kernelMeta = mKernelMeta[metaIndex];\n+ CUmodule hmod{0};\n+ std::string kernelName(kernelMeta.mFuncName);\n+\n+ // Check if the module is already loaded.\n+ auto findModuleIter = mModules.find(kernelMeta.mFuncName);\n+ auto capitalizeFirst = [](std::string str) {\n+ if (!str.empty()) {\n+ str[0] = std::toupper(str[0]);\n+ }\n+ return str;\n+ };\n+ if (findModuleIter == mModules.end()) {\n+ // Load the module.\n+ std::string cubin_path = tllm_gen_fmha_cubin_path + \"/\" + kernelMeta.mFuncName + \".cubin\";\n+ std::string cubin = getCubin(cubin_path, kernelMeta.sha256);\n+ if (cubin.empty()) {\n+ throw std::runtime_error(\"Failed to load cubin for \" + kernelName);\n+ }\n+ cuErrCheck(cuModuleLoadData(&hmod, cubin.data()));\n+ mModules[kernelName] = hmod;\n+ } else {\n+ hmod = findModuleIter->second;\n+ }\n+\n+ // Load the function.\n+ KernelInfo funcInfo;\n+ funcInfo.mMetaInfoIndex = metaIndex;\n+ cuErrCheck(cuModuleGetFunction(&funcInfo.mDeviceFunction, hmod, kernelMeta.mFuncName));\n+\n+ if (kernelMeta.mSharedMemBytes >= 48 * 1024) {\n+ cuErrCheck(cuFuncSetAttribute(funcInfo.mDeviceFunction,\n+ CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES,\n+ kernelMeta.mSharedMemBytes));\n+ }\n+\n+ // Cache the loaded function.\n+ mFunctions[hashId] = funcInfo;\n+ }\n+\n+ // Retrieve the loaded kernel.\n+ auto const& kernelInfo = mFunctions.at(hashId);\n+ auto const& kernelMeta = mKernelMeta[kernelInfo.mMetaInfoIndex];\n+ CUfunction func = kernelInfo.mDeviceFunction;\n+\n+ // Return the function and kernelMeta.\n+ return std::make_pair(func, kernelMeta);\n }\n \n Data_type mDtypeQ, mDtypeKv, mDtypeOut;"},"lines_added":{"kind":"number","value":394,"string":"394"},"lines_removed":{"kind":"number","value":176,"string":"176"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":["qwen","gpt-oss"],"string":"[\n \"qwen\",\n \"gpt-oss\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/trtllm/fmha/fmhaKernels.cuh).\n\nGoal: [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding\nTarget hardware: unspecified\nTarget models: qwen, gpt-oss\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#pragma once\n\n#include <cuda.h>\n\n#include <cstdint>\n#include <iterator>\n#include <memory>\n#include <mutex>\n#include <unordered_map>\n\n#include \"../../exception.h\"\n#include \"../../utils.cuh\"\n#include \"../common.h\"\n#include \"cuda_runtime_api.h\"\n#include \"flashInferMetaInfo.h\"\n#include \"fmhaReduction.h\"\n#include \"fmhaRunnerParams.h\"\n#include \"kernelParams.h\"\n#include \"lse.cuh\"\n\n#ifdef TLLM_GEN_FMHA_CUBIN_PATH\nstatic const std::string tllm_gen_fmha_cubin_path = std::string(TLLM_GEN_FMHA_CUBIN_PATH);\n#else\nstatic_assert(false, \"TLLM_GEN_FMHA_CUBIN_PATH macro is not defined when compiling\");\n#endif\n\n#ifdef TLLM_GEN_FMHA_METAINFO_HASH\nstatic const std::string tllm_gen_fmha_metainfo_hash = std::string(TLLM_GEN_FMHA_METAINFO_HASH);\n#else\nstatic_assert(false, \"TLLM_GEN_FMHA_METAINFO_HASH macro is not defined when compiling\");\n#endif\n\nnamespace flashinfer::trtllm_cubin_loader {\nstd::string getCubin(const std::string& kernelName, const std::string& sha256);\n} // namespace flashinfer::trtllm_cubin_loader\nusing flashinfer::trtllm_cubin_loader::getCubin;\n\nconstexpr bool isSMCompatible(int gpuSM, int kernelSM) {\n if (gpuSM == kSM_103) {\n return kernelSM == kSM_100f || kernelSM == kSM_103;\n } else if (gpuSM == kSM_100) {\n return kernelSM == kSM_100f || kernelSM == kSM_100;\n }\n\n return gpuSM == kernelSM;\n}\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nclass TllmGenFmhaKernel {\n public:\n using KernelMeta = tensorrt_llm::kernels::TllmGenFmhaKernelMetaInfo;\n using RunnerParams = TllmGenFmhaRunnerParams;\n using SelectKernelParams = TllmGenSelectKernelParams;\n\n // Ctor.\n TllmGenFmhaKernel(KernelMeta const* pMetaStart, unsigned int nMetaCount, Data_type dtypeQ,\n Data_type dtypeKv, Data_type dtypeOut, unsigned int smArch)\n : mDtypeQ(dtypeQ),\n mDtypeKv(dtypeKv),\n mDtypeOut(dtypeOut),\n mKernelMeta(pMetaStart),\n mKernelMetaCount(nMetaCount),\n mSM(smArch) {}\n\n void loadKernels() {\n for (unsigned int i = 0; i < mKernelMetaCount; ++i) {\n auto const& kernelMeta = mKernelMeta[i];\n IKL_LOG_DEBUG(\"Checking tllmgen attention kernel %s\", kernelMeta.mFuncName);\n if (isSMCompatible(mSM, kernelMeta.mSM) && kernelMeta.mDataTypeQ == mDtypeQ &&\n kernelMeta.mDataTypeKv == mDtypeKv && kernelMeta.mDataTypeO == mDtypeOut) {\n // Store metadata for later use.\n IKL_LOG_DEBUG(\"Adding tllmgen attention kernel %s\", kernelMeta.mFuncName);\n mKernelMetaMap[hashID(kernelMeta)] = i;\n }\n }\n }\n\n size_t getNumLoadedKernels() const { return mKernelMetaMap.size(); }\n\n inline uint64_t hashID(int qkvLayout, int maskType, int kernelType, int scheduler,\n int multiCtasKvMode, int headDimPerCtaV, int headDimQk, int headDimV,\n int tileSizeKv, int numTokensPerPage, int maxNumHeadsQPerKvInCta,\n bool reuseSmemKForV, bool uses2CtaMma, bool sparseMla) const {\n FLASHINFER_CHECK((headDimPerCtaV >= 32) && (headDimQk >= 32) && (headDimV >= 32) &&\n (headDimPerCtaV <= 1024) && (headDimQk <= 1024) && (headDimV <= 1024),\n \"Expect (32 <= headDim <= 1024), got headDimPerCtaV=%d, headDimQk=%d, \"\n \"headDimV=%d\",\n headDimPerCtaV, headDimQk, headDimV);\n // The numTokensPerPage must be power of 2.\n FLASHINFER_CHECK((numTokensPerPage & (numTokensPerPage - 1)) == 0,\n \"The numTokensPerPage must be power of 2.\");\n FLASHINFER_CHECK(maxNumHeadsQPerKvInCta <= 128,\n \"The maxNumHeadsQPerKvInCta <= 128 is required.\");\n FLASHINFER_CHECK(tileSizeKv == 64 || tileSizeKv == 128, \"The tileSizeKv must be 64 or 128.\");\n // Format of the hash key:\n // Bit 0 - 3 : qkvLayout.\n // Bit 4 - 7 : maskType.\n // Bit 8 - 11: kernelType.\n // Bit 12 - 15: tileScheduler.\n // Bit 16 - 17: multiCtasKvMode.\n // Bit 18 - 25: (headDimPerCtaV >> 3).\n // Bit 26 - 33: (headDimQk >> 3).\n // Bit 34 - 41: (headDimV >> 3).\n // Bit 42 - 43: (tileSizeKv >> 6).\n // Bit 44 - 48: (log2(numTokensPerPage)).\n // Bit 49 - 56: maxNumHeadsQPerKvInCta.\n // Bit 57 - 57: reuseSmemKForV.\n // Bit 58 - 58: uses2CtaMma.\n // Bit 59 - 59: sparseMla.\n return (static_cast<uint64_t>(qkvLayout) << 0) | (static_cast<uint64_t>(maskType) << 4) |\n (static_cast<uint64_t>(kernelType) << 8) | (static_cast<uint64_t>(scheduler) << 12) |\n (static_cast<uint64_t>(multiCtasKvMode) << 16) |\n (static_cast<uint64_t>(headDimPerCtaV >> 3) << 18) |\n (static_cast<uint64_t>(headDimQk >> 3) << 26) |\n (static_cast<uint64_t>(headDimV >> 3) << 34) |\n (static_cast<uint64_t>(tileSizeKv >> 6) << 42) |\n (static_cast<uint64_t>(log2(numTokensPerPage)) << 44) |\n (static_cast<uint64_t>(maxNumHeadsQPerKvInCta) << 49) |\n (static_cast<uint64_t>(reuseSmemKForV) << 57) |\n (static_cast<uint64_t>(uses2CtaMma) << 58) | (static_cast<uint64_t>(sparseMla) << 59);\n }\n\n uint64_t hashID(KernelMeta const& kernelMeta) const {\n return hashID(kernelMeta.mQkvLayout, kernelMeta.mMaskType, kernelMeta.mKernelType,\n kernelMeta.mTileScheduler, kernelMeta.mMultiCtasKvMode,\n kernelMeta.mHeadDimPerCtaV, kernelMeta.mHeadDimQk, kernelMeta.mHeadDimV,\n kernelMeta.mTileSizeKv, kernelMeta.mNumTokensPerPage,\n kernelMeta.mMaxNumHeadsQPerKvInCta, kernelMeta.mReuseSmemKForV,\n kernelMeta.m2CtaMma, kernelMeta.mSparseMla);\n }\n\n std::pair<bool, std::string> checkIfKernelExist(RunnerParams const& params) const {\n // The selectKernelParams that might be updated.\n SelectKernelParams selectKernelParams{params};\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n return std::make_pair(mKernelMetaMap.find(hashId) != mKernelMetaMap.end(), info);\n }\n // start here\n void run(RunnerParams const& params) const {\n // The selectKernelParams that might be updated.\n SelectKernelParams selectKernelParams{params};\n // The iteration index (used to detect a deadlock of selecting new kernels).\n int selectKernelIter = 0;\n // While loop.\n while (true) {\n // Any value >= 2 should work here, but we set it larger in case that we\n // might have more complicated heuristic in the future.\n FLASHINFER_CHECK(selectKernelIter < 8,\n \"A deadlock is detected when selecting trtllm-gen kernels.\");\n auto [hashId, info] = hashFromRunnerParams(params, selectKernelParams);\n auto const findMetaIter = mKernelMetaMap.find(hashId);\n\n // Add debug info when kernels are not found.\n FLASHINFER_CHECK(findMetaIter != mKernelMetaMap.end(),\n \"Trtllm-gen kernels not found: \" + info);\n\n // auto const& kernelMeta = mKernelMeta[findIter->second.mMetaInfoIndex];\n auto const findFuncIter = mFunctions.find(hashId);\n if (findFuncIter == mFunctions.end()) {\n // Load the kernel on-demand.\n loadKernel(hashId, findMetaIter->second);\n }\n // Retrieve the loaded kernel.\n auto const& kernelInfo = mFunctions.at(hashId);\n auto const& kernelMeta = mKernelMeta[kernelInfo.mMetaInfoIndex];\n CUfunction func = kernelInfo.mDeviceFunction;\n\n // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension.\n auto [maxNumCtasQ, maxNumCtasKv, numCtasX, numCtasY, numCtasZ, clusterDimX] =\n computeCtaAndClusterConfig(params, kernelMeta, selectKernelParams);\n // Need to select a new kernel if mSelectNewKernel is true.\n if (selectKernelParams.mSelectNewKernel) {\n selectKernelIter++;\n continue;\n }\n\n // Prepare the kernel parameters.\n auto kernelParams =\n KernelParams::setKernelParams(params, kernelMeta, maxNumCtasQ, maxNumCtasKv);\n\n // Prepare kernel parameters list for cuLaunchKernelEx.\n void* kernelParamsList[] = {&kernelParams};\n CUlaunchConfig launch_config;\n launch_config.blockDimX = kernelMeta.mThreadsPerCTA;\n launch_config.blockDimY = 1;\n launch_config.blockDimZ = 1;\n launch_config.gridDimX = numCtasX;\n launch_config.gridDimY = numCtasY;\n launch_config.gridDimZ = numCtasZ;\n launch_config.hStream = params.stream;\n launch_config.sharedMemBytes = kernelMeta.mSharedMemBytes;\n\n // Debug info.\n IKL_LOG_DEBUG(\"TRTLLM-Gen launch info (in TllmGenFmhaKernel %s, %s, %s, %d): kernelName = %s\",\n toStr(mDtypeQ), toStr(mDtypeKv), toStr(mDtypeOut), mSM, kernelMeta.mFuncName);\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: maxSeqLenQ = %d, \"\n \"maxSeqLenKv = %d, \"\n \"numHeadsQ = %d, \"\n \"numHeadsKv = %d, batchSize = %d, kernelType = %d\",\n params.mMaxSeqLenQ, params.mMaxSeqLenKv, params.mNumHeadsQ, params.mNumHeadsKv,\n params.mBatchSize, static_cast<int>(params.mKernelType));\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: numCtasX = %d, numCtasY = %d, numCtasZ = %d, clusterDimX = %d\",\n numCtasX, numCtasY, numCtasZ, clusterDimX);\n\n CUlaunchAttribute launch_attribute[3];\n launch_attribute[0].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION;\n launch_attribute[0].value.clusterDim.x = clusterDimX;\n launch_attribute[0].value.clusterDim.y = 1;\n launch_attribute[0].value.clusterDim.z = 1;\n launch_attribute[1].id = CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE;\n launch_attribute[1].value.clusterSchedulingPolicyPreference =\n clusterDimX > 1 ? CU_CLUSTER_SCHEDULING_POLICY_SPREAD\n : CU_CLUSTER_SCHEDULING_POLICY_DEFAULT;\n launch_attribute[2].id = CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION;\n launch_attribute[2].value.programmaticStreamSerializationAllowed = params.enable_pdl;\n\n launch_config.attrs = launch_attribute;\n launch_config.numAttrs = 3;\n // Add setting for non-portable cluster size.\n if (clusterDimX > 8) {\n cuErrCheck(cuFuncSetAttribute(func, CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED,\n 1 // Enable non-portable cluster sizes\n ));\n }\n\n // Force using GmemReduction for the multiCtasKvMode if the CgaSmemReduction needs more than\n // one wave (due to the cluster occupancy limit).\n // TODO: find a better heuristic of using CgaSmemReduction.\n if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n // The maximum number of active clusters that could co-exist.\n int maxActiveClusters = 1;\n cuErrCheck(cuOccupancyMaxActiveClusters(&maxActiveClusters, func, &launch_config));\n // Use the GmemReduction instead if it needs more than one wave.\n if (maxActiveClusters * clusterDimX < (numCtasX * numCtasY * numCtasZ)) {\n selectKernelParams.mForceGmemReduction = true;\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReduction;\n // continue to select a new kernel.\n continue;\n }\n }\n cuErrCheck(cuLaunchKernelEx(&launch_config, func, kernelParamsList, nullptr));\n\n // Run the separate reduction kernel if needed.\n tensorrt_llm::kernels::runFmhaReduction(kernelMeta, kernelParams, params.mMultiProcessorCount,\n params.enable_pdl, params.stream);\n\n if (params.lsePtr != nullptr) {\n flashinfer::ComputeLSEFromMD(params.softmaxStatsPtr, params.lsePtr,\n params.mSumOfSeqLensQ * params.mNumHeadsQ, params.enable_pdl,\n params.stream);\n }\n // Break the while op.\n break;\n }\n }\n\n private:\n // Is it MLA generation kernel ?\n inline bool isMlaGenKernel(RunnerParams const& params) const {\n return params.mHeadDimQk == 576 && params.mHeadDimV == 512;\n }\n\n // Compute the number of CTAs in X, Y and Z dimension and the cluster size in the X dimension.\n using CtaClusterInfo = std::tuple<int, int, int, int, int, int>;\n\n CtaClusterInfo computeCtaAndClusterConfig(RunnerParams const& params,\n KernelMeta const& kernelMeta,\n SelectKernelParams& selectKernelParams) const {\n bool isDsv3MinLatencyMode = params.mBatchSize == 1 && params.mMaxSeqLenQ >= 1 &&\n params.mMaxSeqLenQ <= 16 && params.mHeadDimQk == 576 &&\n params.mHeadDimV == 512;\n // Do we need to select a new kernel ?\n selectKernelParams.mSelectNewKernel = false;\n\n // The number of Ctas per Q sequence.\n int numCtasPerSeqQ = (params.mMaxSeqLenQ + kernelMeta.mStepQ - 1) / kernelMeta.mStepQ;\n // Each CTA handles one tokenQ by default for spec-decoding generation kernel, which is used to\n // emulate causal masking (like MTP or Eagle3). Note this will be changed later when the\n // high-throughput spec-decoding generation kernels are integrated.\n if (params.mMaxSeqLenQ > 1 && !isContextKernel(params.mKernelType)) {\n numCtasPerSeqQ = params.mMaxSeqLenQ;\n }\n\n // Compute the grid dimension Y.\n int numHeadsPerCta = kernelMeta.mGroupsHeadsQ\n ? std::min(params.mNumHeadsQPerKv, kernelMeta.mMaxNumHeadsQPerKvInCta)\n : 1;\n int numCtasForAllHeadsQ = params.mNumHeadsQ / numHeadsPerCta;\n FLASHINFER_CHECK(numHeadsPerCta * numCtasForAllHeadsQ == params.mNumHeadsQ,\n \"The numHeadsQ/numHeadsKv is not supported.\");\n // Take the number of headDim CTAs.\n FLASHINFER_CHECK(kernelMeta.mHeadDimV % selectKernelParams.mHeadDimPerCtaV == 0,\n \"The headDimPerCtaV is not supported.\");\n int numCtasPerHeadDim = kernelMeta.mHeadDimV / selectKernelParams.mHeadDimPerCtaV;\n // Compute the current numCtasX.\n int numCtasX = numCtasPerSeqQ;\n // Update the numCtasY.\n int numCtasY = numCtasForAllHeadsQ * numCtasPerHeadDim;\n // Compute the grid dimension Z.\n int numCtasZ = params.mBatchSize;\n // The 2CtaMma kernels will use 2 Ctas in the x dimension (only used by MLA generation kernels)\n // for heads, so numCtasPerHeadDim and numCtasForAllHeadsQ will be handled by the 2Ctas in the x\n // dimension.\n if (isMlaGenKernel(params) && selectKernelParams.mUses2CtaMma) {\n FLASHINFER_CHECK(numCtasForAllHeadsQ == 2 && numCtasPerHeadDim == 2,\n \"Internal error: numCtasPerHeadDim should be 2.\");\n numCtasX *= 2;\n numCtasY /= (numCtasForAllHeadsQ * numCtasPerHeadDim);\n }\n\n // First split the seqLenKv into multiple CTAs if the utilization is not full.\n // The number of Ctas per KV sequence.\n int numCtasPerSeqKv = 1;\n // Consider the multiCtasKvMode for better GPU utilization.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n // The maximum attention window (the maximum number of tokensKv that will be attended to).\n int maxAttentionWindow{params.mMaxSeqLenKv};\n // The sparseMla only selects topK tokensKv.\n if (params.mSparseMla) {\n maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mSparseMlaTopK);\n }\n // Some of the tilesKv will be skipped if the sliding window attention or chunked attention is\n // used.\n if (isSlidingOrChunkedCausalMask(selectKernelParams.mMaskType)) {\n if (params.mMaxSeqLenKv > params.mAttentionWindowSize) {\n // Consider that the first tileKv might contain tokensKv that is out of the attention\n // window.\n maxAttentionWindow =\n std::min(params.mMaxSeqLenKv, params.mAttentionWindowSize + kernelMeta.mStepKv - 1);\n } else {\n maxAttentionWindow = std::min(params.mMaxSeqLenKv, params.mChunkedAttentionSize);\n }\n }\n\n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n int const maxNumCtasPerSeqKv =\n (maxAttentionWindow + kernelMeta.mStepKv - 1) / kernelMeta.mStepKv;\n // Compute numCtasPerSeqKv.\n numCtasPerSeqKv = std::min(\n maxNumCtasPerSeqKv,\n std::max(1, int32_t(params.mMultiProcessorCount / (numCtasX * numCtasY * numCtasZ))));\n // Update the numCtasX.\n numCtasX *= numCtasPerSeqKv;\n // The current total number of CTAs.\n int totalNumCtas = numCtasX * numCtasZ * numCtasY;\n // Disable the multiCtasKvMode if there is only one CtaKv.\n if (numCtasPerSeqKv <= 1) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::Disabled;\n // Enable the persistent scheduler for better performance.\n selectKernelParams.mTileScheduler = TileScheduler::Persistent;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n } else if (totalNumCtas < params.mMultiProcessorCount && isMlaGenKernel(params) &&\n !params.mSparseMla && selectKernelParams.mTileSizeKv == 128 &&\n getEnvUseTileSizeKv64ForTrtllmGen()) {\n // Use smaller tileSizeKv to fully utilize the SMs.\n selectKernelParams.mTileSizeKv = 64;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n\n // Enable the CgaSmemReduction if the numCtasPerSeqKv <= 16 as the maximum cluster dimension\n // is 16. Only the swapsMmaAbForGeneration kernel supports the CgaSmemReduction for now.\n if (!isDsv3MinLatencyMode && numCtasPerSeqKv > 1 && numCtasPerSeqKv <= 16 &&\n isSwapsMmaAbForGenerationKernel(selectKernelParams.mKernelType) &&\n isGmemReduction(selectKernelParams.mMultiCtasKvMode) &&\n !selectKernelParams.mForceGmemReduction) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::CgaSmemReduction;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n\n // Add the debug info when multiCtasKvMode is enabled.\n if (numCtasPerSeqKv > 1) {\n IKL_LOG_DEBUG(\n \"TRTLLM-Gen launch info: multiCtasKvMode is enabled with tileSizeKv = %d, \"\n \"numCtasPerSeqKv = %d, \"\n \"numCtasPerSeqQ = \"\n \"%d, numCtasY = %d, numCtasZ = %d\",\n selectKernelParams.mTileSizeKv, numCtasPerSeqKv, numCtasPerSeqQ, numCtasY, numCtasZ);\n }\n }\n\n // The cluster size in the X dimension.\n int clusterDimX = selectKernelParams.mUses2CtaMma ? 2 : 1;\n if (isCgaSmemReduction(selectKernelParams.mMultiCtasKvMode)) {\n // Note 2CtaMma and CgaSmemReduction cannot be used together currently.\n clusterDimX *= numCtasPerSeqKv;\n }\n\n // Compute the current number of CTAs in total.\n int totalNumCtas = numCtasX * numCtasZ * numCtasY;\n\n // Then split the headDimV into multiple CTAs if there are still unused SMs.\n if (isMlaGenKernel(params) && !selectKernelParams.mReuseSmemKForV &&\n !selectKernelParams.mSelectNewKernel && !selectKernelParams.mUses2CtaMma) {\n // Split the headDimV into multiple CTAs if the utilization is not full.\n // It doesn't work with reuseSmemKForV currently.\n // TODO: find better heuristic of splitting headDimV across multiple CTAs.\n\n int corrFactor = isDsv3MinLatencyMode ? 1 : 2;\n if (selectKernelParams.mHeadDimPerCtaV == 512 &&\n totalNumCtas * corrFactor <= params.mMultiProcessorCount) {\n // Use smaller headDimPerCtaV to fully utilize the SMs.\n selectKernelParams.mHeadDimPerCtaV =\n totalNumCtas * 2 * corrFactor <= params.mMultiProcessorCount ? 128 : 256;\n // Need to select a different kernel.\n selectKernelParams.mSelectNewKernel = true;\n }\n }\n\n // Return the number of CTAs for X, Y and Z dimension and the cluster size in the X dimension.\n return std::make_tuple(numCtasPerSeqQ, numCtasPerSeqKv, numCtasX, numCtasY, numCtasZ,\n clusterDimX);\n }\n\n // Determine if we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n bool useSwapsMmaAbMlaGenKernel(RunnerParams const& params) const {\n // Use the SwapsMmaAbForGeneration kernel for MLA generation when the following conditions are\n // met:\n // 1. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned\n // later).\n // 2. The numCtas (after splitting the heads across multiple CTAs) <=\n // params.mMultiProcessorCount.\n\n // The maximum number Ctas per Kv sequence, which makes sure that each CtaKv has work to do.\n // Here we assume the stepKv is 256.\n int const maxNumCtasPerSeqKv = flashinfer::ceil_div(params.mMaxSeqLenKv, 256);\n ;\n // The number of Ctas.\n int const numCtas = static_cast<int32_t>(params.mBatchSize * params.mMaxSeqLenQ *\n divUp(params.mNumHeadsQPerKv, 16));\n // Compute numCtasPerSeqKv.\n int const numCtasPerSeqKv =\n std::min(maxNumCtasPerSeqKv, std::max(1, int32_t(params.mMultiProcessorCount / numCtas)));\n // Compute the seqLenPerCtaKv.\n int const seqLenPerCtaKv = flashinfer::ceil_div(params.mMaxSeqLenKv, numCtasPerSeqKv);\n // Whether we should use the SwapsMmaAbForGeneration kernel for MLA generation.\n return seqLenPerCtaKv <= 1024 && numCtas <= params.mMultiProcessorCount;\n }\n\n std::pair<uint64_t, std::string> hashFromRunnerParams(\n RunnerParams const& params, SelectKernelParams& selectKernelParams) const {\n // The updated kernel type.\n FmhaKernelType& kernelType = selectKernelParams.mKernelType;\n // Generation kernelType will use either SwapsMmaAbForGeneration or KeepsMmaAbForGeneration.\n if (isGenerationKernel(params.mKernelType) && isMlaGenKernel(params)) {\n // We use the low-latency kernel (SwapsMmaAbForGeneration with tileSizeQ = 16) when any of the\n // following conditions are met:\n // 1. The number of headsQPerKv is <= 32.\n // 2. The number of headsQPerKv is < 128 for sparseMla.\n // 3. The seqLenPerCtaKv <= 1024 based on the benchmark results (this might be fine-tuned\n // later) and\n // the numCtas (after splitting the heads across multiple CTAs) <=\n // params.mMultiProcessorCount.\n\n // Check the conditions.\n if (params.mNumHeadsQPerKv <= 32 || (params.mSparseMla && params.mNumHeadsQPerKv < 128) ||\n useSwapsMmaAbMlaGenKernel(params)) {\n kernelType = FmhaKernelType::SwapsMmaAbForGeneration;\n } else {\n // Otherwise, we use the high-throughput kernel.\n kernelType = FmhaKernelType::KeepsMmaAbForGeneration;\n // Always use the separate reduction kernel.\n if (isMultiCtasKvEnabled(selectKernelParams.mMultiCtasKvMode)) {\n selectKernelParams.mMultiCtasKvMode = MultiCtasKvMode::GmemReductionWithSeparateKernel;\n }\n // The keepsMmaAbForGeneration sparseMla kernels only support numHeadsQPerKv = 128.\n FLASHINFER_CHECK(\n !params.mSparseMla || params.mNumHeadsQPerKv == 128,\n \"The keepsMmaAbForGeneration sparseMla kernels only support numHeadsQPerKv = 128\");\n // The 2CTA keepsMmaAbForGeneration kernel is used when the numHeadsQPerKv is 128.\n if (params.mNumHeadsQPerKv == 128) {\n selectKernelParams.mUses2CtaMma = true;\n // Each Cta only handles 256 headDimV.\n selectKernelParams.mHeadDimPerCtaV = 256;\n }\n }\n } else if (isGenerationKernel(params.mKernelType)) {\n kernelType = (params.mNumHeadsQPerKv <= 16 && params.mHeadDimQk != 32)\n ? FmhaKernelType::SwapsMmaAbForGeneration\n : FmhaKernelType::KeepsMmaAbForGeneration;\n }\n\n // The maximum number of headsQPerKv that the kernel can support in one Cta.\n int maxNumHeadsQPerKvInCta = 1;\n if (isSwapsMmaAbForGenerationKernel(kernelType)) {\n // Set the corresponding maxNumHeadsQPerKvInCta (tileSizeQ) for low-latency generation\n // kernels.\n maxNumHeadsQPerKvInCta = (params.mNumHeadsQPerKv <= 8) ? 8 : 16;\n FLASHINFER_CHECK((maxNumHeadsQPerKvInCta == 8 || maxNumHeadsQPerKvInCta == 16) &&\n (params.mNumHeadsQPerKv < maxNumHeadsQPerKvInCta ||\n params.mNumHeadsQPerKv % maxNumHeadsQPerKvInCta == 0),\n \"Not supported\");\n } else if (isKeepsMmaAbForGenerationKernel(kernelType)) {\n // Use the maxNumHeadsQPerKvInCta (tileSizeQ) = 64 for MLA high-throughput generation kernels.\n maxNumHeadsQPerKvInCta = isMlaGenKernel(params) ? 64 : 32;\n FLASHINFER_CHECK((params.mNumHeadsQPerKv < maxNumHeadsQPerKvInCta ||\n params.mNumHeadsQPerKv % maxNumHeadsQPerKvInCta == 0),\n \"Not supported\");\n } else if (isContextKernel(kernelType)) {\n FLASHINFER_CHECK(maxNumHeadsQPerKvInCta == 1, \"Not supported\");\n }\n\n // The mask type.\n selectKernelParams.mMaskType = params.mMaskType;\n // Enable sliding window or chunked causal if the max kv sequence length exceeds attention\n // window size or chunked attention size. This is supported by causal-mask context kernels and\n // generation-phase kernels.\n if ((selectKernelParams.mMaskType == TrtllmGenAttentionMaskType::Causal ||\n !isContextKernel(params.mKernelType)) &&\n (params.mMaxSeqLenKv > params.mAttentionWindowSize ||\n params.mChunkedAttentionSize != INT_MAX)) {\n FLASHINFER_CHECK(\n params.mMaxSeqLenKv <= params.mAttentionWindowSize ||\n params.mMaxSeqLenKv <= params.mChunkedAttentionSize,\n \"Sliding window attention and chunked attention should not be used together\");\n selectKernelParams.mMaskType = TrtllmGenAttentionMaskType::SlidingOrChunkedCausal;\n }\n\n // The number of tokens per page.\n int numTokensPerPage = params.mNumTokensPerPage;\n // SparseMla kernels use a fixed numTokensPerPage = 1.\n if (params.mSparseMla) {\n numTokensPerPage = 1;\n } else if (!isPagedKv(params.mQkvLayout)) {\n // NumTokensPerPage is set to 0 when not selecting pagedKv-layout kernels.\n numTokensPerPage = 0;\n }\n\n // Debug info.\n std::string info =\n \"qkvLayout=\" + std::to_string(static_cast<int>(params.mQkvLayout)) +\n \", maskType=\" + std::to_string(static_cast<int>(selectKernelParams.mMaskType)) +\n \", kernelType=\" + std::to_string(static_cast<int>(kernelType)) +\n \", tileScheduler=\" + std::to_string(static_cast<int>(selectKernelParams.mTileScheduler)) +\n \", multiCtasKvMode=\" +\n std::to_string(static_cast<int>(selectKernelParams.mMultiCtasKvMode)) +\n \", headDimPerCtaV=\" + std::to_string(selectKernelParams.mHeadDimPerCtaV) +\n \", headDimQk=\" + std::to_string(params.mHeadDimQk) +\n \", headDimV=\" + std::to_string(params.mHeadDimV) +\n \", tileSizeKv=\" + std::to_string(selectKernelParams.mTileSizeKv) +\n \", numTokensPerPage=\" + std::to_string(numTokensPerPage) +\n \", maxNumHeadsQPerKvInCta=\" + std::to_string(maxNumHeadsQPerKvInCta) +\n \", reuseSmemKForV=\" + std::to_string(selectKernelParams.mReuseSmemKForV) +\n \", uses2CtaMma=\" + std::to_string(selectKernelParams.mUses2CtaMma) +\n \", sparseMla=\" + std::to_string(params.mSparseMla);\n IKL_LOG_DEBUG(\n \"Searching for kernel traits (%d available) in TllmGenFmhaKernel(%s, %s, %s, %d) %s\",\n getNumLoadedKernels(), toStr(mDtypeQ), toStr(mDtypeKv), toStr(mDtypeOut), mSM,\n info.c_str());\n\n return std::make_pair(\n hashID(static_cast<int>(params.mQkvLayout), static_cast<int>(selectKernelParams.mMaskType),\n static_cast<int>(kernelType), static_cast<int>(selectKernelParams.mTileScheduler),\n static_cast<int>(selectKernelParams.mMultiCtasKvMode),\n selectKernelParams.mHeadDimPerCtaV, params.mHeadDimQk, params.mHeadDimV,\n selectKernelParams.mTileSizeKv, numTokensPerPage, maxNumHeadsQPerKvInCta,\n selectKernelParams.mReuseSmemKForV, selectKernelParams.mUses2CtaMma,\n params.mSparseMla),\n info);\n }\n\n // Load a single kernel (called by `run()` when needed).\n void loadKernel(uint64_t hashId, unsigned int metaIndex) const {\n auto const& kernelMeta = mKernelMeta[metaIndex];\n CUmodule hmod{0};\n std::string kernelName(kernelMeta.mFuncName);\n\n // Check if the module is already loaded.\n auto findModuleIter = mModules.find(kernelMeta.mFuncName);\n auto capitalizeFirst = [](std::string str) {\n if (!str.empty()) {\n str[0] = std::toupper(str[0]);\n }\n return str;\n };\n if (findModuleIter == mModules.end()) {\n // Load the module.\n std::string cubin_path = tllm_gen_fmha_cubin_path + \"/\" + kernelMeta.mFuncName + \".cubin\";\n std::string cubin = getCubin(cubin_path, kernelMeta.sha256);\n if (cubin.empty()) {\n throw std::runtime_error(\"Failed to load cubin for \" + kernelName);\n }\n cuErrCheck(cuModuleLoadData(&hmod, cubin.data()));\n mModules[kernelName] = hmod;\n } else {\n hmod = findModuleIter->second;\n }\n\n // Load the function.\n KernelInfo funcInfo;\n funcInfo.mMetaInfoIndex = metaIndex;\n cuErrCheck(cuModuleGetFunction(&funcInfo.mDeviceFunction, hmod, kernelMeta.mFuncName));\n\n if (kernelMeta.mSharedMemBytes >= 48 * 1024) {\n cuErrCheck(cuFuncSetAttribute(funcInfo.mDeviceFunction,\n CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES,\n kernelMeta.mSharedMemBytes));\n }\n\n // Cache the loaded function.\n mFunctions[hashId] = funcInfo;\n }\n\n Data_type mDtypeQ, mDtypeKv, mDtypeOut;\n KernelMeta const* mKernelMeta;\n unsigned int mKernelMetaCount;\n unsigned int mSM;\n mutable std::unordered_map<std::string, CUmodule> mModules;\n\n mutable std::unordered_map<uint64_t, unsigned int> mKernelMetaMap;\n\n struct KernelInfo {\n unsigned int mMetaInfoIndex;\n CUfunction mDeviceFunction;\n };\n\n mutable std::unordered_map<uint64_t, KernelInfo> mFunctions;\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\nclass TllmFmhaKernelFactory {\n public:\n using KernelType = TllmGenFmhaKernel;\n\n KernelType const* getKernels(const typename KernelType::KernelMeta* pKernelList,\n unsigned int nbKernels, Data_type dtypeQ, Data_type dtypeKv,\n Data_type dtypeOut, unsigned int sm) {\n static std::mutex s_mutex;\n std::lock_guard<std::mutex> lg(s_mutex);\n\n auto const id = hashID(dtypeQ, dtypeKv, dtypeOut, sm);\n auto const findIter = mKernels.find(id);\n if (findIter == mKernels.end()) {\n KernelType* newKernel = new KernelType{pKernelList, nbKernels, dtypeQ, dtypeKv, dtypeOut, sm};\n newKernel->loadKernels();\n mKernels.insert(std::make_pair(id, std::unique_ptr<KernelType>(newKernel)));\n IKL_LOG_DEBUG(\n \"Loading new kernel for dtypeQ=%s, dtypeKv=%s, dtypeOut=%s, sm=%d with %d loaded kernels\",\n toStr(dtypeQ), toStr(dtypeKv), toStr(dtypeOut), sm, newKernel->getNumLoadedKernels());\n return newKernel;\n }\n return findIter->second.get();\n }\n\n static TllmFmhaKernelFactory& Get() {\n int deviceId;\n cudaGetDevice(&deviceId);\n static std::unique_ptr<TllmFmhaKernelFactory> sFactory[32] = {nullptr};\n if (sFactory[deviceId] == nullptr) {\n FLASHINFER_CHECK(deviceId < 32, \"Invalid deviceId %d (max is 32 devices)\", deviceId);\n sFactory[deviceId] = std::make_unique<TllmFmhaKernelFactory>(TllmFmhaKernelFactory());\n }\n\n return *(sFactory[deviceId]);\n }\n\n private:\n TllmFmhaKernelFactory() = default;\n\n inline uint64_t hashID(Data_type dtypeQ, Data_type dtypeKv, Data_type dtypeOut,\n unsigned int sm) const {\n return static_cast<uint64_t>(sm) | static_cast<uint64_t>(dtypeQ) << 16 |\n static_cast<uint64_t>(dtypeKv) << 20 | static_cast<uint64_t>(dtypeOut) << 24;\n }\n\n std::unordered_map<uint64_t, const std::unique_ptr<KernelType>> mKernels;\n};\n\ninline TllmGenFmhaKernel const* getTllmFmhaKernels(Data_type dtypeQ, Data_type dtypeKv,\n Data_type dtypeOut, unsigned int sm) {\n#ifndef EXCLUDE_SM_100\n return TllmFmhaKernelFactory::Get().getKernels(\n tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos,\n sizeof(tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos) /\n sizeof(tensorrt_llm::kernels::sTllmGenFmhaKernelMetaInfos[0]),\n dtypeQ, dtypeKv, dtypeOut, sm);\n#else\n return nullptr;\n#endif // EXCLUDE_SM_100\n}\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nThis MR adds the optimized decode attention kernels for high throughput (large batch size) + speculative decoding (seqlen_q > 1). \n\nSee below for speedups (collected by `benchmarks/flashinfer_benchmark.py`). The seqlenKv is 16K for all cases. \n\n| test case | median_time_ms | median_time_ms (opt) | speedup |\n|------------------------------------------|----------------|----------------------|----------|\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ2 | 0.057 | 0.046 | 1.24 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ2 | 0.11 | 0.083 | 1.33 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ2 | 0.213 | 0.168 | 1.27 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ2 | 0.266 | 0.241 | 1.10 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ2 | 0.432 | 0.336 | 1.29 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ4 | 0.109 | 0.048 | 2.27 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ4 | 0.212 | 0.083 | 2.55 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ4 | 0.371 | 0.168 | 2.21 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ4 | 0.472 | 0.245 | 1.93 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ4 | 0.736 | 0.348 | 2.11 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ8 | 0.212 | 0.061 | 3.48 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ8 | 0.37 | 0.106 | 3.49 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ8 | 0.732 | 0.239 | 3.06 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ8 | 0.937 | 0.321 | 2.92 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ8 | 1.456 | 0.484 | 3.01 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ2 | 0.051 | 0.03 | 1.70 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ2 | 0.098 | 0.054 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ2 | 0.188 | 0.104 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ2 | 0.234 | 0.15 | 1.56 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ2 | 0.332 | 0.199 | 1.67 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ4 | 0.099 | 0.038 | 2.61 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ4 | 0.188 | 0.07 | 2.69 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ4 | 0.332 | 0.136 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ4 | 0.418 | 0.2 | 2.09 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ4 | 0.647 | 0.265 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ8 | 0.188 | 0.039 | 4.82 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ8 | 0.332 | 0.065 | 5.11 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ8 | 0.647 | 0.126 | 5.13 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ8 | 0.83 | 0.185 | 4.49 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ8 | 1.29 | 0.245 | 5.27 |\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n * Generation attention now enforces causal masking during token generation.\n\n* **Performance / Refactor**\n * Improved kernel selection and on-demand loading for better performance and GPU compatibility.\n * Added finer-grained tuning parameters for tile/grouping, tokens-per-CTA and inflation to enable more optimal kernel choices.\n\n* **Chores**\n * Updated FMHA artifact paths and checksums.\n\n* **Tests**\n * Expanded parameterized tests to cover larger batch decoding scenarios.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1195,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"e079eee48dec413adb66d4a142e3eb66f9f42b6f"},"date":{"kind":"string","value":"2026-01-08T07:48:37+08:00"},"pr_number":{"kind":"number","value":2265,"string":"2,265"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2265"},"title":{"kind":"string","value":"[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265)"},"message":{"kind":"string","value":"[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nThis MR adds the optimized decode attention kernels for high throughput\n(large batch size) + speculative decoding (seqlen_q > 1).\n\nSee below for speedups (collected by\n`benchmarks/flashinfer_benchmark.py`). The seqlenKv is 16K for all\ncases.\n\n| test case | median_time_ms | median_time_ms (opt) | speedup |\n\n|------------------------------------------|----------------|----------------------|----------|\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ2 | 0.057 | 0.046 | 1.24 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ2 | 0.11 | 0.083 | 1.33 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ2 | 0.213 | 0.168 | 1.27 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ2 | 0.266 | 0.241 | 1.10 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ2 | 0.432 | 0.336 | 1.29 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ4 | 0.109 | 0.048 | 2.27 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ4 | 0.212 | 0.083 | 2.55 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ4 | 0.371 | 0.168 | 2.21 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ4 | 0.472 | 0.245 | 1.93 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ4 | 0.736 | 0.348 | 2.11 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ8 | 0.212 | 0.061 | 3.48 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ8 | 0.37 | 0.106 | 3.49 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ8 | 0.732 | 0.239 | 3.06 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ8 | 0.937 | 0.321 | 2.92 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ8 | 1.456 | 0.484 | 3.01 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ2 | 0.051 | 0.03 | 1.70 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ2 | 0.098 | 0.054 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ2 | 0.188 | 0.104 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ2 | 0.234 | 0.15 | 1.56 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ2 | 0.332 | 0.199 | 1.67 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ4 | 0.099 | 0.038 | 2.61 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ4 | 0.188 | 0.07 | 2.69 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ4 | 0.332 | 0.136 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ4 | 0.418 | 0.2 | 2.09 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ4 | 0.647 | 0.265 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ8 | 0.188 | 0.039 | 4.82 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ8 | 0.332 | 0.065 | 5.11 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ8 | 0.647 | 0.126 | 5.13 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ8 | 0.83 | 0.185 | 4.49 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ8 | 1.29 | 0.245 | 5.27 |\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n* Generation attention now enforces causal masking during token\ngeneration.\n\n* **Performance / Refactor**\n* Improved kernel selection and on-demand loading for better performance\nand GPU compatibility.\n* Added finer-grained tuning parameters for tile/grouping,\ntokens-per-CTA and inflation to enable more optimal kernel choices.\n\n* **Chores**\n * Updated FMHA artifact paths and checksums.\n\n* **Tests**\n* Expanded parameterized tests to cover larger batch decoding scenarios.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review\nsettings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: yzh119 <zihaoy@nvidia.com>\nCo-authored-by: Zihao Ye <expye@outlook.com>"},"path":{"kind":"string","value":"include/flashinfer/trtllm/fmha/fmhaRunnerParams.h"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#pragma once\n\n#include <cuda_runtime.h>\n\n#include <cstdint>\n#include <cstdio>\n#include <cstring>\n\n#include \"flashinfer/exception.h\"\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// The attention mask types.\nenum class TrtllmGenAttentionMaskType {\n // Dense mask.\n Dense = 0,\n // Causal mask.\n Causal,\n // Sliding window or chunked causal mask.\n SlidingOrChunkedCausal,\n // Custom mask.\n Custom\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// Helper functions to check the mask type.\n\n#define ATTENTION_MASK_TYPE_FUNCTION(MaskType) \\\n inline bool is##MaskType##Mask(TrtllmGenAttentionMaskType maskType) { \\\n return (maskType == TrtllmGenAttentionMaskType::MaskType); \\\n }\n\nATTENTION_MASK_TYPE_FUNCTION(Dense)\nATTENTION_MASK_TYPE_FUNCTION(Causal)\nATTENTION_MASK_TYPE_FUNCTION(SlidingOrChunkedCausal)\nATTENTION_MASK_TYPE_FUNCTION(Custom)\n\n#undef ATTENTION_MASK_TYPE_FUNCTION\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\nenum class FmhaKernelType {\n // The context-phase kernels.\n Context = 0,\n // Choose the best generation kernel based on the heuristic:\n // use SwapsMmaAbForGeneration kernels when numHeadsQPerKv <= 16, otherwise\n // KeepsMmaAbForGeneration.\n Generation = 1,\n // Swap tensor A and tensor B of Mma, which only supports numHeadsQPerKv <= 16.\n SwapsMmaAbForGeneration,\n // Keep tensor A and tensor B of Mma.\n KeepsMmaAbForGeneration,\n // Speculative decoding (Medusa and Eagle) generation-phase attention kernels, where seqLenQ > 1.\n SpecDecodingGeneration\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// Helper functions to check the fmha kernel type.\n\n#define FMHA_KERNEL_TYPE_FUNCTION(KernelType) \\\n inline bool is##KernelType##Kernel(FmhaKernelType kernelType) { \\\n return (kernelType == FmhaKernelType::KernelType); \\\n }\n\nFMHA_KERNEL_TYPE_FUNCTION(Context)\nFMHA_KERNEL_TYPE_FUNCTION(Generation)\nFMHA_KERNEL_TYPE_FUNCTION(SwapsMmaAbForGeneration)\nFMHA_KERNEL_TYPE_FUNCTION(KeepsMmaAbForGeneration)\nFMHA_KERNEL_TYPE_FUNCTION(SpecDecodingGeneration)\n\n#undef QKV_LAYOUT_FUNCTION\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// Note that (batchSize, seqLen) dimensions will be packed as sumOfSeqLens without paddings for\n// variable sequence lengths.\nenum class QkvLayout {\n // SeparateQkv: separate Q, K and V buffers.\n // Each has the shape: [batchSize, seqLen, numHeads, headDim].\n SeparateQkv = 0,\n // PackedQkv: single buffer for Q, K and V.\n // Shape: [batchSize, seqLen, numHeadsQ + 2*numHeadsKv, headDim].\n PackedQkv,\n // Paged buffer for K and V. Its shape is [batchSize, 2, maxNumPagesPerSeq]. The 2 corresponds to\n // K\n // and V. That buffer stores the logical page index of the paged-KV memory pool. Each \"page\" of\n // that\n // pool is a contiguous buffer of shape [numHeadsKv, pageSize, headDim].\n PagedKv,\n // ContiguousKv:\n // Contiguous buffer for Q with shape [batchSize, seqLen, numHeads, headDim].\n // Contiguous buffer for Kv with shape [batchSize, seqLen, 2 * numHeads, headDim].\n ContiguousKv,\n};\n\n// Helper functions to check the QkvLayout type.\n\n#define QKV_LAYOUT_FUNCTION(LayoutType) \\\n inline bool is##LayoutType(QkvLayout qkvLayout) { return (qkvLayout == QkvLayout::LayoutType); }\n\nQKV_LAYOUT_FUNCTION(SeparateQkv)\nQKV_LAYOUT_FUNCTION(PackedQkv)\nQKV_LAYOUT_FUNCTION(PagedKv)\nQKV_LAYOUT_FUNCTION(ContiguousKv)\n\n#undef QKV_LAYOUT_FUNCTION\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\nenum class TileScheduler {\n // Static scheduler (Non-persistent).\n Static = 0,\n // Persistent scheduler.\n Persistent\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nenum class MultiCtasKvMode {\n // Disable the multiCtasKvMode.\n Disabled = 0,\n // Do the reduction through the global memory and atomic counters.\n GmemReduction,\n // Same as GmemReduction, but use a separate kernel for the reduction.\n // It is only supported/needed for 2-CTA or 1-CTA keepsMmaAbForGeneration MLA kernels with large\n // reduction tiles.\n GmemReductionWithSeparateKernel,\n // Do the reduction through the CGA remote shared memory.\n CgaSmemReduction\n};\n\n// Helper function to check if the multiCtasKv is enabled.\ninline bool isMultiCtasKvEnabled(MultiCtasKvMode multiCtasKvMode) {\n return multiCtasKvMode != MultiCtasKvMode::Disabled;\n}\n\n// Helper function to check the multiCtasKvMode type.\n\n#define MULTI_CTAS_KV_MODE_FUNCTION(Type) \\\n inline bool is##Type(MultiCtasKvMode multiCtasKvMode) { \\\n return (multiCtasKvMode == MultiCtasKvMode::Type); \\\n }\n\nMULTI_CTAS_KV_MODE_FUNCTION(Disabled)\nMULTI_CTAS_KV_MODE_FUNCTION(GmemReduction)\nMULTI_CTAS_KV_MODE_FUNCTION(GmemReductionWithSeparateKernel)\nMULTI_CTAS_KV_MODE_FUNCTION(CgaSmemReduction)\n\n#undef MULTI_CTAS_KV_MODE_FUNCTION\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nstruct TllmGenFmhaRunnerParams {\n // Input layout.\n QkvLayout mQkvLayout;\n // Attention mask type.\n TrtllmGenAttentionMaskType mMaskType;\n // The kernel type.\n FmhaKernelType mKernelType;\n // The tile scheduler.\n TileScheduler mTileScheduler;\n // The multiCtasKvMode (i.e. multiBlockMode).\n bool mMultiCtasKvMode;\n\n // Input QKV buffers.\n void const* qPtr;\n void const* kPtr;\n void const* vPtr;\n // Packed KV buffer\n void const* kvPtr;\n // Packed QKV buffer\n void const* qkvPtr;\n // The scaling factor pointer of K.\n void const* kSfBasePtr;\n // The scaling factor pointer of V.\n void const* vSfBasePtr;\n // The custom mask ptr.\n uint32_t const* customMaskPtr;\n // The packed custom mask's offsets of each sequence.\n int64_t const* customMaskOffsetsPtr;\n // The first sparseMask offsets in the Kv sequence dimension.\n int32_t const* firstSparseMaskOffsetsKvPtr;\n // The counter for the multiCtasKv mode.\n int32_t* multiCtasKvCounterPtr;\n // The sequence length buffer for K/V.\n int const* seqLensKvPtr;\n // The cumulative sequence length buffer for Q and K/V\n int const* cumSeqLensQPtr;\n int const* cumSeqLensKvPtr;\n // The kv page idx\n int const* kvPageIdxPtr;\n bool useGmemScale;\n // The device output scale for FP8 quantization.\n float const* outputScalePtr;\n float outputScale;\n // The device scaling factor for softmax (multiplied by log2 to use faster exp2)\n float const* scaleSoftmaxLog2Ptr;\n float scaleSoftmaxLog2;\n // The device scale for KV scaling factor.\n float const* kvSfScalePtr;\n // The device scale for O scaling factor.\n float const* oSfScalePtr;\n // The scratch space for each CtaKv when the multiCtasKv mode is enabled.\n // PartialO, partialMax and partialSum will be stored to the scratch space.\n void* multiCtasKvScratchPtr;\n // The softmax stats buffer.\n // The softmax max/sum values will be stored to the buffer if it is not nullptr.\n float2* softmaxStatsPtr;\n // The LSE buffer.\n float* lsePtr;\n\n // Attention sink\n float const* ptrAttentionSinks{nullptr};\n // The output buffer.\n void* oPtr;\n // The output scaling factor buffer.\n void* oSfPtr;\n\n // The stride between different tokens for Q.\n int qStrideTokens;\n // The stride between different heads for Q.\n int qStrideHeads;\n\n // The stride between different keys.\n int kStrideKeysValues;\n // The stride between different heads for K.\n int kStrideHeads;\n // The stride between different batches for K.\n int kStrideBatch;\n\n // The stride between different values.\n int vStrideKeysValues;\n // The stride between different heads for V.\n int vStrideHeads;\n // The stride between different batches for V.\n int vStrideBatch;\n\n // Head dimension for Q and K.\n int mHeadDimQk;\n // Head dimension for V.\n int mHeadDimV;\n // Number of heads for Q and K/V.\n int mNumHeadsQ, mNumHeadsKv, mNumHeadsQPerKv;\n // The batch size.\n int mBatchSize;\n // The max sequence length in the contiguous Kv cache.\n int mMaxSeqLenCacheKv;\n // The max q sequence length.\n int mMaxSeqLenQ;\n // The max kv sequence length.\n int mMaxSeqLenKv;\n // The attention window size for sliding window attention (sliding-window-attention is enabled\n // when seqLenKv > mAttentionWindowSize).\n int mAttentionWindowSize;\n // The chunked attention size (chunked-context is enabled when seqLenKv > mChunkedAttentionSize).\n int mChunkedAttentionSize;\n // The sum of sequence lengths for Q and K/V. (Only used when mSupportsVarSeqLens = true)\n int mSumOfSeqLensQ;\n int mSumOfSeqLensKv;\n // The maximum number of pages per sequence in the paged-kv buffer.\n int mMaxNumPagesPerSeqKv;\n // The number of tokens per pageKv.\n int mNumTokensPerPage;\n // The number of pages in memory pool.\n int mNumPagesInMemPool;\n // The number of multiProcessor for the GPU.\n int mMultiProcessorCount;\n // Scaling factor for Q.\n float mScaleQ;\n // Scaling factor for output.\n float mScaleOutput;\n // The start token index in SF tensor. Used for FP4 SF offset calculation in generation phase\n // kernel when inflight batching is enabled.\n int mSfStartTokenIdx;\n // The SF scale for Kv.\n float mScaleSfKv;\n // The SF scale for output.\n float mScaleSfO;\n // Whether to use sparse MLA.\n bool mSparseMla;\n // The top k value for sparse MLA.\n int mSparseMlaTopK;\n // The cuda stream.\n cudaStream_t stream;\n // Whether to enable PDL (Programmatic Dependent Launch).\n bool enable_pdl;\n\n // set the attention mask type\n TllmGenFmhaRunnerParams& setAttentionMaskType(std::int8_t maskType) {\n // maskType is the enum of tensorrt_llm::kernels::ContextAttentionMaskType\n // convert ContextAttentionMaskType to TrtllmGenAttentionMaskType\n switch (maskType) {\n case 0: // tensorrt_llm::kernels::ContextAttentionMaskType::PADDING\n mMaskType = TrtllmGenAttentionMaskType::Dense;\n break;\n case 1: // tensorrt_llm::kernels::ContextAttentionMaskType::CAUSAL\n mMaskType = TrtllmGenAttentionMaskType::Causal;\n break;\n case 2: // tensorrt_llm::kernels::ContextAttentionMaskType::SLIDING_OR_CHUNKED_CAUSAL\n mMaskType = TrtllmGenAttentionMaskType::SlidingOrChunkedCausal;\n break;\n case 3: // tensorrt_llm::kernels::ContextAttentionMaskType::CUSTOM_MASK\n mMaskType = TrtllmGenAttentionMaskType::Custom;\n break;\n default:\n FLASHINFER_ERROR(\"Invalid attention mask type\");\n }\n return *this;\n }\n\n TllmGenFmhaRunnerParams() {\n // NOTE(Zihao): all fields are POD types, so we can use memset to initialize them to zero\n static_assert(std::is_standard_layout<TllmGenFmhaRunnerParams>::value,\n \"TllmGenFmhaRunnerParams must be a POD type (standard layout) for memset to be \"\n \"safe.\");\n memset(this, 0, sizeof(TllmGenFmhaRunnerParams));\n }\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// Parameters that might be updated when selecting kernels.\n\nstruct TllmGenSelectKernelParams {\n // The FMHA kernel type.\n FmhaKernelType mKernelType;\n // The headDimV per CTA, which is only used by MLA generation kernels currently.\n int mHeadDimPerCtaV;\n // The multiCtasKvMode.\n MultiCtasKvMode mMultiCtasKvMode;\n // Force using GmemRedution for the multiCtasKvMode.\n bool mForceGmemReduction;\n // The mask type.\n TrtllmGenAttentionMaskType mMaskType;\n // Reuse smemK for V or not (only work with MLA generation kernels).\n bool mReuseSmemKForV;\n // Do we need to select a new kernel as the parameters have been updated.\n bool mSelectNewKernel;\n // The tile scheduler.\n TileScheduler mTileScheduler;\n // The tile size for Kv.\n int mTileSizeKv;\n // Use 2 CTA MMA or not.\n bool mUses2CtaMma;\n\n // The constructor.\n TllmGenSelectKernelParams(TllmGenFmhaRunnerParams params)\n : mKernelType(params.mKernelType),\n mHeadDimPerCtaV(params.mHeadDimV)\n // Note the CgaSmemReduction will be enabled based on the heuristic.\n ,\n mMultiCtasKvMode(params.mMultiCtasKvMode ? MultiCtasKvMode::GmemReduction\n : MultiCtasKvMode::Disabled),\n mForceGmemReduction(false),\n mMaskType(params.mMaskType),\n mReuseSmemKForV(false),\n mSelectNewKernel(false),\n mTileScheduler(params.mTileScheduler),\n mTileSizeKv(128),\n mUses2CtaMma(false) {};\n};\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#pragma once\n\n#include <cuda_runtime.h>\n\n#include <cstdint>\n#include <cstdio>\n#include <cstring>\n\n#include \"flashinfer/exception.h\"\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// The attention mask types.\nenum class TrtllmGenAttentionMaskType {\n // Dense mask.\n Dense = 0,\n // Causal mask.\n Causal,\n // Sliding window or chunked causal mask.\n SlidingOrChunkedCausal,\n // Custom mask.\n Custom\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// Helper functions to check the mask type.\n\n#define ATTENTION_MASK_TYPE_FUNCTION(MaskType) \\\n inline bool is##MaskType##Mask(TrtllmGenAttentionMaskType maskType) { \\\n return (maskType == TrtllmGenAttentionMaskType::MaskType); \\\n }\n\nATTENTION_MASK_TYPE_FUNCTION(Dense)\nATTENTION_MASK_TYPE_FUNCTION(Causal)\nATTENTION_MASK_TYPE_FUNCTION(SlidingOrChunkedCausal)\nATTENTION_MASK_TYPE_FUNCTION(Custom)\n\n#undef ATTENTION_MASK_TYPE_FUNCTION\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\nenum class FmhaKernelType {\n // The context-phase kernels.\n Context = 0,\n // Choose the best generation kernel based on the heuristic:\n // use SwapsMmaAbForGeneration kernels when numHeadsQPerKv <= 16, otherwise\n // KeepsMmaAbForGeneration.\n Generation = 1,\n // Swap tensor A and tensor B of Mma, which only supports numHeadsQPerKv <= 16.\n SwapsMmaAbForGeneration,\n // Keep tensor A and tensor B of Mma.\n KeepsMmaAbForGeneration,\n // Speculative decoding (Medusa and Eagle) generation-phase attention kernels, where seqLenQ > 1.\n SpecDecodingGeneration\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// Helper functions to check the fmha kernel type.\n\n#define FMHA_KERNEL_TYPE_FUNCTION(KernelType) \\\n inline bool is##KernelType##Kernel(FmhaKernelType kernelType) { \\\n return (kernelType == FmhaKernelType::KernelType); \\\n }\n\nFMHA_KERNEL_TYPE_FUNCTION(Context)\nFMHA_KERNEL_TYPE_FUNCTION(Generation)\nFMHA_KERNEL_TYPE_FUNCTION(SwapsMmaAbForGeneration)\nFMHA_KERNEL_TYPE_FUNCTION(KeepsMmaAbForGeneration)\nFMHA_KERNEL_TYPE_FUNCTION(SpecDecodingGeneration)\n\n#undef QKV_LAYOUT_FUNCTION\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// Note that (batchSize, seqLen) dimensions will be packed as sumOfSeqLens without paddings for\n// variable sequence lengths.\nenum class QkvLayout {\n // SeparateQkv: separate Q, K and V buffers.\n // Each has the shape: [batchSize, seqLen, numHeads, headDim].\n SeparateQkv = 0,\n // PackedQkv: single buffer for Q, K and V.\n // Shape: [batchSize, seqLen, numHeadsQ + 2*numHeadsKv, headDim].\n PackedQkv,\n // Paged buffer for K and V. Its shape is [batchSize, 2, maxNumPagesPerSeq]. The 2 corresponds to\n // K\n // and V. That buffer stores the logical page index of the paged-KV memory pool. Each \"page\" of\n // that\n // pool is a contiguous buffer of shape [numHeadsKv, pageSize, headDim].\n PagedKv,\n // ContiguousKv:\n // Contiguous buffer for Q with shape [batchSize, seqLen, numHeads, headDim].\n // Contiguous buffer for Kv with shape [batchSize, seqLen, 2 * numHeads, headDim].\n ContiguousKv,\n};\n\n// Helper functions to check the QkvLayout type.\n\n#define QKV_LAYOUT_FUNCTION(LayoutType) \\\n inline bool is##LayoutType(QkvLayout qkvLayout) { return (qkvLayout == QkvLayout::LayoutType); }\n\nQKV_LAYOUT_FUNCTION(SeparateQkv)\nQKV_LAYOUT_FUNCTION(PackedQkv)\nQKV_LAYOUT_FUNCTION(PagedKv)\nQKV_LAYOUT_FUNCTION(ContiguousKv)\n\n#undef QKV_LAYOUT_FUNCTION\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\nenum class TileScheduler {\n // Static scheduler (Non-persistent).\n Static = 0,\n // Persistent scheduler.\n Persistent\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nenum class MultiCtasKvMode {\n // Disable the multiCtasKvMode.\n Disabled = 0,\n // Do the reduction through the global memory and atomic counters.\n GmemReduction,\n // Same as GmemReduction, but use a separate kernel for the reduction.\n // It is only supported/needed for 2-CTA or 1-CTA keepsMmaAbForGeneration MLA kernels with large\n // reduction tiles.\n GmemReductionWithSeparateKernel,\n // Do the reduction through the CGA remote shared memory.\n CgaSmemReduction\n};\n\n// Helper function to check if the multiCtasKv is enabled.\ninline bool isMultiCtasKvEnabled(MultiCtasKvMode multiCtasKvMode) {\n return multiCtasKvMode != MultiCtasKvMode::Disabled;\n}\n\n// Helper function to check the multiCtasKvMode type.\n\n#define MULTI_CTAS_KV_MODE_FUNCTION(Type) \\\n inline bool is##Type(MultiCtasKvMode multiCtasKvMode) { \\\n return (multiCtasKvMode == MultiCtasKvMode::Type); \\\n }\n\nMULTI_CTAS_KV_MODE_FUNCTION(Disabled)\nMULTI_CTAS_KV_MODE_FUNCTION(GmemReduction)\nMULTI_CTAS_KV_MODE_FUNCTION(GmemReductionWithSeparateKernel)\nMULTI_CTAS_KV_MODE_FUNCTION(CgaSmemReduction)\n\n#undef MULTI_CTAS_KV_MODE_FUNCTION\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nstruct TllmGenFmhaRunnerParams {\n // Input layout.\n QkvLayout mQkvLayout;\n // Attention mask type.\n TrtllmGenAttentionMaskType mMaskType;\n // The kernel type.\n FmhaKernelType mKernelType;\n // The tile scheduler.\n TileScheduler mTileScheduler;\n // The multiCtasKvMode (i.e. multiBlockMode).\n bool mMultiCtasKvMode;\n\n // Input QKV buffers.\n void const* qPtr;\n void const* kPtr;\n void const* vPtr;\n // Packed KV buffer\n void const* kvPtr;\n // Packed QKV buffer\n void const* qkvPtr;\n // The scaling factor pointer of K.\n void const* kSfBasePtr;\n // The scaling factor pointer of V.\n void const* vSfBasePtr;\n // The custom mask ptr.\n uint32_t const* customMaskPtr;\n // The packed custom mask's offsets of each sequence.\n int64_t const* customMaskOffsetsPtr;\n // The first sparseMask offsets in the Kv sequence dimension.\n int32_t const* firstSparseMaskOffsetsKvPtr;\n // The counter for the multiCtasKv mode.\n int32_t* multiCtasKvCounterPtr;\n // The sequence length buffer for K/V.\n int const* seqLensKvPtr;\n // The cumulative sequence length buffer for Q and K/V\n int const* cumSeqLensQPtr;\n int const* cumSeqLensKvPtr;\n // The kv page idx\n int const* kvPageIdxPtr;\n bool useGmemScale;\n // The device output scale for FP8 quantization.\n float const* outputScalePtr;\n float outputScale;\n // The device scaling factor for softmax (multiplied by log2 to use faster exp2)\n float const* scaleSoftmaxLog2Ptr;\n float scaleSoftmaxLog2;\n // The device scale for KV scaling factor.\n float const* kvSfScalePtr;\n // The device scale for O scaling factor.\n float const* oSfScalePtr;\n // The scratch space for each CtaKv when the multiCtasKv mode is enabled.\n // PartialO, partialMax and partialSum will be stored to the scratch space.\n void* multiCtasKvScratchPtr;\n // The softmax stats buffer.\n // The softmax max/sum values will be stored to the buffer if it is not nullptr.\n float2* softmaxStatsPtr;\n // The LSE buffer.\n float* lsePtr;\n\n // Attention sink\n float const* ptrAttentionSinks{nullptr};\n // The output buffer.\n void* oPtr;\n // The output scaling factor buffer.\n void* oSfPtr;\n\n // The stride between different tokens for Q.\n int qStrideTokens;\n // The stride between different heads for Q.\n int qStrideHeads;\n\n // The stride between different keys.\n int kStrideKeysValues;\n // The stride between different heads for K.\n int kStrideHeads;\n // The stride between different batches for K.\n int kStrideBatch;\n\n // The stride between different values.\n int vStrideKeysValues;\n // The stride between different heads for V.\n int vStrideHeads;\n // The stride between different batches for V.\n int vStrideBatch;\n\n // Head dimension for Q and K.\n int mHeadDimQk;\n // Head dimension for V.\n int mHeadDimV;\n // Number of heads for Q and K/V.\n int mNumHeadsQ, mNumHeadsKv, mNumHeadsQPerKv;\n // The batch size.\n int mBatchSize;\n // The max sequence length in the contiguous Kv cache.\n int mMaxSeqLenCacheKv;\n // The max q sequence length.\n int mMaxSeqLenQ;\n // The max kv sequence length.\n int mMaxSeqLenKv;\n // The attention window size for sliding window attention (sliding-window-attention is enabled\n // when seqLenKv > mAttentionWindowSize).\n int mAttentionWindowSize;\n // The chunked attention size (chunked-context is enabled when seqLenKv > mChunkedAttentionSize).\n int mChunkedAttentionSize;\n // The sum of sequence lengths for Q and K/V. (Only used when mSupportsVarSeqLens = true)\n int mSumOfSeqLensQ;\n int mSumOfSeqLensKv;\n // The maximum number of pages per sequence in the paged-kv buffer.\n int mMaxNumPagesPerSeqKv;\n // The number of tokens per pageKv.\n int mNumTokensPerPage;\n // The number of pages in memory pool.\n int mNumPagesInMemPool;\n // The number of multiProcessor for the GPU.\n int mMultiProcessorCount;\n // Scaling factor for Q.\n float mScaleQ;\n // Scaling factor for output.\n float mScaleOutput;\n // The start token index in SF tensor. Used for FP4 SF offset calculation in generation phase\n // kernel when inflight batching is enabled.\n int mSfStartTokenIdx;\n // The SF scale for Kv.\n float mScaleSfKv;\n // The SF scale for output.\n float mScaleSfO;\n // Whether to use sparse MLA.\n bool mSparseMla;\n // The top k value for sparse MLA.\n int mSparseMlaTopK;\n // The cuda stream.\n cudaStream_t stream;\n // Whether to enable PDL (Programmatic Dependent Launch).\n bool enable_pdl;\n\n // set the attention mask type\n TllmGenFmhaRunnerParams& setAttentionMaskType(std::int8_t maskType) {\n // maskType is the enum of tensorrt_llm::kernels::ContextAttentionMaskType\n // convert ContextAttentionMaskType to TrtllmGenAttentionMaskType\n switch (maskType) {\n case 0: // tensorrt_llm::kernels::ContextAttentionMaskType::PADDING\n mMaskType = TrtllmGenAttentionMaskType::Dense;\n break;\n case 1: // tensorrt_llm::kernels::ContextAttentionMaskType::CAUSAL\n mMaskType = TrtllmGenAttentionMaskType::Causal;\n break;\n case 2: // tensorrt_llm::kernels::ContextAttentionMaskType::SLIDING_OR_CHUNKED_CAUSAL\n mMaskType = TrtllmGenAttentionMaskType::SlidingOrChunkedCausal;\n break;\n case 3: // tensorrt_llm::kernels::ContextAttentionMaskType::CUSTOM_MASK\n mMaskType = TrtllmGenAttentionMaskType::Custom;\n break;\n default:\n FLASHINFER_ERROR(\"Invalid attention mask type\");\n }\n return *this;\n }\n\n TllmGenFmhaRunnerParams() {\n // NOTE(Zihao): all fields are POD types, so we can use memset to initialize them to zero\n static_assert(std::is_standard_layout<TllmGenFmhaRunnerParams>::value,\n \"TllmGenFmhaRunnerParams must be a POD type (standard layout) for memset to be \"\n \"safe.\");\n memset(this, 0, sizeof(TllmGenFmhaRunnerParams));\n }\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// Parameters that might be updated when selecting kernels.\n\nstruct TllmGenSelectKernelParams {\n // The FMHA kernel type.\n FmhaKernelType mKernelType;\n // The headDimV per CTA, which is only used by MLA generation kernels currently.\n int mHeadDimPerCtaV;\n // The multiCtasKvMode.\n MultiCtasKvMode mMultiCtasKvMode;\n // Force using GmemRedution for the multiCtasKvMode.\n bool mForceGmemReduction;\n // The mask type.\n TrtllmGenAttentionMaskType mMaskType;\n // The number of tokens per page.\n int mNumTokensPerPage;\n // Reuse smemK for V or not (only work with MLA generation kernels).\n bool mReuseSmemKForV;\n // Do we need to select a new kernel as the parameters have been updated.\n bool mSelectNewKernel;\n // The tile scheduler.\n TileScheduler mTileScheduler;\n // The tile size for Q.\n int mTileSizeQ;\n // The tile size for Kv.\n int mTileSizeKv;\n // Use 2 CTA MMA or not.\n bool mUses2CtaMma;\n\n // The constructor.\n TllmGenSelectKernelParams(TllmGenFmhaRunnerParams params)\n : mKernelType(params.mKernelType),\n mHeadDimPerCtaV(params.mHeadDimV)\n // Note the CgaSmemReduction will be enabled based on the heuristic.\n ,\n mMultiCtasKvMode(params.mMultiCtasKvMode ? MultiCtasKvMode::GmemReduction\n : MultiCtasKvMode::Disabled),\n mForceGmemReduction(false),\n mMaskType(params.mMaskType),\n mNumTokensPerPage(params.mNumTokensPerPage),\n mReuseSmemKForV(false),\n mSelectNewKernel(false),\n mTileScheduler(params.mTileScheduler),\n mTileSizeQ(128),\n mTileSizeKv(128),\n mUses2CtaMma(false) {};\n};\n"},"diff":{"kind":"string","value":"--- include/flashinfer/trtllm/fmha/fmhaRunnerParams.h\n+++ include/flashinfer/trtllm/fmha/fmhaRunnerParams.h\n@@ -348,12 +348,16 @@\n bool mForceGmemReduction;\n // The mask type.\n TrtllmGenAttentionMaskType mMaskType;\n+ // The number of tokens per page.\n+ int mNumTokensPerPage;\n // Reuse smemK for V or not (only work with MLA generation kernels).\n bool mReuseSmemKForV;\n // Do we need to select a new kernel as the parameters have been updated.\n bool mSelectNewKernel;\n // The tile scheduler.\n TileScheduler mTileScheduler;\n+ // The tile size for Q.\n+ int mTileSizeQ;\n // The tile size for Kv.\n int mTileSizeKv;\n // Use 2 CTA MMA or not.\n@@ -369,9 +373,11 @@\n : MultiCtasKvMode::Disabled),\n mForceGmemReduction(false),\n mMaskType(params.mMaskType),\n+ mNumTokensPerPage(params.mNumTokensPerPage),\n mReuseSmemKForV(false),\n mSelectNewKernel(false),\n mTileScheduler(params.mTileScheduler),\n+ mTileSizeQ(128),\n mTileSizeKv(128),\n mUses2CtaMma(false) {};\n };"},"lines_added":{"kind":"number","value":6,"string":"6"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":["qwen","gpt-oss"],"string":"[\n \"qwen\",\n \"gpt-oss\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/fmha/fmhaRunnerParams.h).\n\nGoal: [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding\nTarget hardware: unspecified\nTarget models: qwen, gpt-oss\n\nCurrent file:\n```cpp\n/*\n * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#pragma once\n\n#include <cuda_runtime.h>\n\n#include <cstdint>\n#include <cstdio>\n#include <cstring>\n\n#include \"flashinfer/exception.h\"\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// The attention mask types.\nenum class TrtllmGenAttentionMaskType {\n // Dense mask.\n Dense = 0,\n // Causal mask.\n Causal,\n // Sliding window or chunked causal mask.\n SlidingOrChunkedCausal,\n // Custom mask.\n Custom\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// Helper functions to check the mask type.\n\n#define ATTENTION_MASK_TYPE_FUNCTION(MaskType) \\\n inline bool is##MaskType##Mask(TrtllmGenAttentionMaskType maskType) { \\\n return (maskType == TrtllmGenAttentionMaskType::MaskType); \\\n }\n\nATTENTION_MASK_TYPE_FUNCTION(Dense)\nATTENTION_MASK_TYPE_FUNCTION(Causal)\nATTENTION_MASK_TYPE_FUNCTION(SlidingOrChunkedCausal)\nATTENTION_MASK_TYPE_FUNCTION(Custom)\n\n#undef ATTENTION_MASK_TYPE_FUNCTION\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\nenum class FmhaKernelType {\n // The context-phase kernels.\n Context = 0,\n // Choose the best generation kernel based on the heuristic:\n // use SwapsMmaAbForGeneration kernels when numHeadsQPerKv <= 16, otherwise\n // KeepsMmaAbForGeneration.\n Generation = 1,\n // Swap tensor A and tensor B of Mma, which only supports numHeadsQPerKv <= 16.\n SwapsMmaAbForGeneration,\n // Keep tensor A and tensor B of Mma.\n KeepsMmaAbForGeneration,\n // Speculative decoding (Medusa and Eagle) generation-phase attention kernels, where seqLenQ > 1.\n SpecDecodingGeneration\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// Helper functions to check the fmha kernel type.\n\n#define FMHA_KERNEL_TYPE_FUNCTION(KernelType) \\\n inline bool is##KernelType##Kernel(FmhaKernelType kernelType) { \\\n return (kernelType == FmhaKernelType::KernelType); \\\n }\n\nFMHA_KERNEL_TYPE_FUNCTION(Context)\nFMHA_KERNEL_TYPE_FUNCTION(Generation)\nFMHA_KERNEL_TYPE_FUNCTION(SwapsMmaAbForGeneration)\nFMHA_KERNEL_TYPE_FUNCTION(KeepsMmaAbForGeneration)\nFMHA_KERNEL_TYPE_FUNCTION(SpecDecodingGeneration)\n\n#undef QKV_LAYOUT_FUNCTION\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// Note that (batchSize, seqLen) dimensions will be packed as sumOfSeqLens without paddings for\n// variable sequence lengths.\nenum class QkvLayout {\n // SeparateQkv: separate Q, K and V buffers.\n // Each has the shape: [batchSize, seqLen, numHeads, headDim].\n SeparateQkv = 0,\n // PackedQkv: single buffer for Q, K and V.\n // Shape: [batchSize, seqLen, numHeadsQ + 2*numHeadsKv, headDim].\n PackedQkv,\n // Paged buffer for K and V. Its shape is [batchSize, 2, maxNumPagesPerSeq]. The 2 corresponds to\n // K\n // and V. That buffer stores the logical page index of the paged-KV memory pool. Each \"page\" of\n // that\n // pool is a contiguous buffer of shape [numHeadsKv, pageSize, headDim].\n PagedKv,\n // ContiguousKv:\n // Contiguous buffer for Q with shape [batchSize, seqLen, numHeads, headDim].\n // Contiguous buffer for Kv with shape [batchSize, seqLen, 2 * numHeads, headDim].\n ContiguousKv,\n};\n\n// Helper functions to check the QkvLayout type.\n\n#define QKV_LAYOUT_FUNCTION(LayoutType) \\\n inline bool is##LayoutType(QkvLayout qkvLayout) { return (qkvLayout == QkvLayout::LayoutType); }\n\nQKV_LAYOUT_FUNCTION(SeparateQkv)\nQKV_LAYOUT_FUNCTION(PackedQkv)\nQKV_LAYOUT_FUNCTION(PagedKv)\nQKV_LAYOUT_FUNCTION(ContiguousKv)\n\n#undef QKV_LAYOUT_FUNCTION\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\nenum class TileScheduler {\n // Static scheduler (Non-persistent).\n Static = 0,\n // Persistent scheduler.\n Persistent\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nenum class MultiCtasKvMode {\n // Disable the multiCtasKvMode.\n Disabled = 0,\n // Do the reduction through the global memory and atomic counters.\n GmemReduction,\n // Same as GmemReduction, but use a separate kernel for the reduction.\n // It is only supported/needed for 2-CTA or 1-CTA keepsMmaAbForGeneration MLA kernels with large\n // reduction tiles.\n GmemReductionWithSeparateKernel,\n // Do the reduction through the CGA remote shared memory.\n CgaSmemReduction\n};\n\n// Helper function to check if the multiCtasKv is enabled.\ninline bool isMultiCtasKvEnabled(MultiCtasKvMode multiCtasKvMode) {\n return multiCtasKvMode != MultiCtasKvMode::Disabled;\n}\n\n// Helper function to check the multiCtasKvMode type.\n\n#define MULTI_CTAS_KV_MODE_FUNCTION(Type) \\\n inline bool is##Type(MultiCtasKvMode multiCtasKvMode) { \\\n return (multiCtasKvMode == MultiCtasKvMode::Type); \\\n }\n\nMULTI_CTAS_KV_MODE_FUNCTION(Disabled)\nMULTI_CTAS_KV_MODE_FUNCTION(GmemReduction)\nMULTI_CTAS_KV_MODE_FUNCTION(GmemReductionWithSeparateKernel)\nMULTI_CTAS_KV_MODE_FUNCTION(CgaSmemReduction)\n\n#undef MULTI_CTAS_KV_MODE_FUNCTION\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nstruct TllmGenFmhaRunnerParams {\n // Input layout.\n QkvLayout mQkvLayout;\n // Attention mask type.\n TrtllmGenAttentionMaskType mMaskType;\n // The kernel type.\n FmhaKernelType mKernelType;\n // The tile scheduler.\n TileScheduler mTileScheduler;\n // The multiCtasKvMode (i.e. multiBlockMode).\n bool mMultiCtasKvMode;\n\n // Input QKV buffers.\n void const* qPtr;\n void const* kPtr;\n void const* vPtr;\n // Packed KV buffer\n void const* kvPtr;\n // Packed QKV buffer\n void const* qkvPtr;\n // The scaling factor pointer of K.\n void const* kSfBasePtr;\n // The scaling factor pointer of V.\n void const* vSfBasePtr;\n // The custom mask ptr.\n uint32_t const* customMaskPtr;\n // The packed custom mask's offsets of each sequence.\n int64_t const* customMaskOffsetsPtr;\n // The first sparseMask offsets in the Kv sequence dimension.\n int32_t const* firstSparseMaskOffsetsKvPtr;\n // The counter for the multiCtasKv mode.\n int32_t* multiCtasKvCounterPtr;\n // The sequence length buffer for K/V.\n int const* seqLensKvPtr;\n // The cumulative sequence length buffer for Q and K/V\n int const* cumSeqLensQPtr;\n int const* cumSeqLensKvPtr;\n // The kv page idx\n int const* kvPageIdxPtr;\n bool useGmemScale;\n // The device output scale for FP8 quantization.\n float const* outputScalePtr;\n float outputScale;\n // The device scaling factor for softmax (multiplied by log2 to use faster exp2)\n float const* scaleSoftmaxLog2Ptr;\n float scaleSoftmaxLog2;\n // The device scale for KV scaling factor.\n float const* kvSfScalePtr;\n // The device scale for O scaling factor.\n float const* oSfScalePtr;\n // The scratch space for each CtaKv when the multiCtasKv mode is enabled.\n // PartialO, partialMax and partialSum will be stored to the scratch space.\n void* multiCtasKvScratchPtr;\n // The softmax stats buffer.\n // The softmax max/sum values will be stored to the buffer if it is not nullptr.\n float2* softmaxStatsPtr;\n // The LSE buffer.\n float* lsePtr;\n\n // Attention sink\n float const* ptrAttentionSinks{nullptr};\n // The output buffer.\n void* oPtr;\n // The output scaling factor buffer.\n void* oSfPtr;\n\n // The stride between different tokens for Q.\n int qStrideTokens;\n // The stride between different heads for Q.\n int qStrideHeads;\n\n // The stride between different keys.\n int kStrideKeysValues;\n // The stride between different heads for K.\n int kStrideHeads;\n // The stride between different batches for K.\n int kStrideBatch;\n\n // The stride between different values.\n int vStrideKeysValues;\n // The stride between different heads for V.\n int vStrideHeads;\n // The stride between different batches for V.\n int vStrideBatch;\n\n // Head dimension for Q and K.\n int mHeadDimQk;\n // Head dimension for V.\n int mHeadDimV;\n // Number of heads for Q and K/V.\n int mNumHeadsQ, mNumHeadsKv, mNumHeadsQPerKv;\n // The batch size.\n int mBatchSize;\n // The max sequence length in the contiguous Kv cache.\n int mMaxSeqLenCacheKv;\n // The max q sequence length.\n int mMaxSeqLenQ;\n // The max kv sequence length.\n int mMaxSeqLenKv;\n // The attention window size for sliding window attention (sliding-window-attention is enabled\n // when seqLenKv > mAttentionWindowSize).\n int mAttentionWindowSize;\n // The chunked attention size (chunked-context is enabled when seqLenKv > mChunkedAttentionSize).\n int mChunkedAttentionSize;\n // The sum of sequence lengths for Q and K/V. (Only used when mSupportsVarSeqLens = true)\n int mSumOfSeqLensQ;\n int mSumOfSeqLensKv;\n // The maximum number of pages per sequence in the paged-kv buffer.\n int mMaxNumPagesPerSeqKv;\n // The number of tokens per pageKv.\n int mNumTokensPerPage;\n // The number of pages in memory pool.\n int mNumPagesInMemPool;\n // The number of multiProcessor for the GPU.\n int mMultiProcessorCount;\n // Scaling factor for Q.\n float mScaleQ;\n // Scaling factor for output.\n float mScaleOutput;\n // The start token index in SF tensor. Used for FP4 SF offset calculation in generation phase\n // kernel when inflight batching is enabled.\n int mSfStartTokenIdx;\n // The SF scale for Kv.\n float mScaleSfKv;\n // The SF scale for output.\n float mScaleSfO;\n // Whether to use sparse MLA.\n bool mSparseMla;\n // The top k value for sparse MLA.\n int mSparseMlaTopK;\n // The cuda stream.\n cudaStream_t stream;\n // Whether to enable PDL (Programmatic Dependent Launch).\n bool enable_pdl;\n\n // set the attention mask type\n TllmGenFmhaRunnerParams& setAttentionMaskType(std::int8_t maskType) {\n // maskType is the enum of tensorrt_llm::kernels::ContextAttentionMaskType\n // convert ContextAttentionMaskType to TrtllmGenAttentionMaskType\n switch (maskType) {\n case 0: // tensorrt_llm::kernels::ContextAttentionMaskType::PADDING\n mMaskType = TrtllmGenAttentionMaskType::Dense;\n break;\n case 1: // tensorrt_llm::kernels::ContextAttentionMaskType::CAUSAL\n mMaskType = TrtllmGenAttentionMaskType::Causal;\n break;\n case 2: // tensorrt_llm::kernels::ContextAttentionMaskType::SLIDING_OR_CHUNKED_CAUSAL\n mMaskType = TrtllmGenAttentionMaskType::SlidingOrChunkedCausal;\n break;\n case 3: // tensorrt_llm::kernels::ContextAttentionMaskType::CUSTOM_MASK\n mMaskType = TrtllmGenAttentionMaskType::Custom;\n break;\n default:\n FLASHINFER_ERROR(\"Invalid attention mask type\");\n }\n return *this;\n }\n\n TllmGenFmhaRunnerParams() {\n // NOTE(Zihao): all fields are POD types, so we can use memset to initialize them to zero\n static_assert(std::is_standard_layout<TllmGenFmhaRunnerParams>::value,\n \"TllmGenFmhaRunnerParams must be a POD type (standard layout) for memset to be \"\n \"safe.\");\n memset(this, 0, sizeof(TllmGenFmhaRunnerParams));\n }\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// Parameters that might be updated when selecting kernels.\n\nstruct TllmGenSelectKernelParams {\n // The FMHA kernel type.\n FmhaKernelType mKernelType;\n // The headDimV per CTA, which is only used by MLA generation kernels currently.\n int mHeadDimPerCtaV;\n // The multiCtasKvMode.\n MultiCtasKvMode mMultiCtasKvMode;\n // Force using GmemRedution for the multiCtasKvMode.\n bool mForceGmemReduction;\n // The mask type.\n TrtllmGenAttentionMaskType mMaskType;\n // Reuse smemK for V or not (only work with MLA generation kernels).\n bool mReuseSmemKForV;\n // Do we need to select a new kernel as the parameters have been updated.\n bool mSelectNewKernel;\n // The tile scheduler.\n TileScheduler mTileScheduler;\n // The tile size for Kv.\n int mTileSizeKv;\n // Use 2 CTA MMA or not.\n bool mUses2CtaMma;\n\n // The constructor.\n TllmGenSelectKernelParams(TllmGenFmhaRunnerParams params)\n : mKernelType(params.mKernelType),\n mHeadDimPerCtaV(params.mHeadDimV)\n // Note the CgaSmemReduction will be enabled based on the heuristic.\n ,\n mMultiCtasKvMode(params.mMultiCtasKvMode ? MultiCtasKvMode::GmemReduction\n : MultiCtasKvMode::Disabled),\n mForceGmemReduction(false),\n mMaskType(params.mMaskType),\n mReuseSmemKForV(false),\n mSelectNewKernel(false),\n mTileScheduler(params.mTileScheduler),\n mTileSizeKv(128),\n mUses2CtaMma(false) {};\n};\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nThis MR adds the optimized decode attention kernels for high throughput (large batch size) + speculative decoding (seqlen_q > 1). \n\nSee below for speedups (collected by `benchmarks/flashinfer_benchmark.py`). The seqlenKv is 16K for all cases. \n\n| test case | median_time_ms | median_time_ms (opt) | speedup |\n|------------------------------------------|----------------|----------------------|----------|\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ2 | 0.057 | 0.046 | 1.24 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ2 | 0.11 | 0.083 | 1.33 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ2 | 0.213 | 0.168 | 1.27 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ2 | 0.266 | 0.241 | 1.10 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ2 | 0.432 | 0.336 | 1.29 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ4 | 0.109 | 0.048 | 2.27 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ4 | 0.212 | 0.083 | 2.55 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ4 | 0.371 | 0.168 | 2.21 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ4 | 0.472 | 0.245 | 1.93 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ4 | 0.736 | 0.348 | 2.11 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ8 | 0.212 | 0.061 | 3.48 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ8 | 0.37 | 0.106 | 3.49 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ8 | 0.732 | 0.239 | 3.06 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ8 | 0.937 | 0.321 | 2.92 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ8 | 1.456 | 0.484 | 3.01 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ2 | 0.051 | 0.03 | 1.70 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ2 | 0.098 | 0.054 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ2 | 0.188 | 0.104 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ2 | 0.234 | 0.15 | 1.56 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ2 | 0.332 | 0.199 | 1.67 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ4 | 0.099 | 0.038 | 2.61 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ4 | 0.188 | 0.07 | 2.69 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ4 | 0.332 | 0.136 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ4 | 0.418 | 0.2 | 2.09 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ4 | 0.647 | 0.265 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ8 | 0.188 | 0.039 | 4.82 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ8 | 0.332 | 0.065 | 5.11 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ8 | 0.647 | 0.126 | 5.13 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ8 | 0.83 | 0.185 | 4.49 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ8 | 1.29 | 0.245 | 5.27 |\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n * Generation attention now enforces causal masking during token generation.\n\n* **Performance / Refactor**\n * Improved kernel selection and on-demand loading for better performance and GPU compatibility.\n * Added finer-grained tuning parameters for tile/grouping, tokens-per-CTA and inflation to enable more optimal kernel choices.\n\n* **Chores**\n * Updated FMHA artifact paths and checksums.\n\n* **Tests**\n * Expanded parameterized tests to cover larger batch decoding scenarios.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1196,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"e079eee48dec413adb66d4a142e3eb66f9f42b6f"},"date":{"kind":"string","value":"2026-01-08T07:48:37+08:00"},"pr_number":{"kind":"number","value":2265,"string":"2,265"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2265"},"title":{"kind":"string","value":"[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265)"},"message":{"kind":"string","value":"[TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nThis MR adds the optimized decode attention kernels for high throughput\n(large batch size) + speculative decoding (seqlen_q > 1).\n\nSee below for speedups (collected by\n`benchmarks/flashinfer_benchmark.py`). The seqlenKv is 16K for all\ncases.\n\n| test case | median_time_ms | median_time_ms (opt) | speedup |\n\n|------------------------------------------|----------------|----------------------|----------|\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ2 | 0.057 | 0.046 | 1.24 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ2 | 0.11 | 0.083 | 1.33 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ2 | 0.213 | 0.168 | 1.27 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ2 | 0.266 | 0.241 | 1.10 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ2 | 0.432 | 0.336 | 1.29 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ4 | 0.109 | 0.048 | 2.27 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ4 | 0.212 | 0.083 | 2.55 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ4 | 0.371 | 0.168 | 2.21 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ4 | 0.472 | 0.245 | 1.93 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ4 | 0.736 | 0.348 | 2.11 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ8 | 0.212 | 0.061 | 3.48 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ8 | 0.37 | 0.106 | 3.49 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ8 | 0.732 | 0.239 | 3.06 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ8 | 0.937 | 0.321 | 2.92 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ8 | 1.456 | 0.484 | 3.01 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ2 | 0.051 | 0.03 | 1.70 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ2 | 0.098 | 0.054 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ2 | 0.188 | 0.104 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ2 | 0.234 | 0.15 | 1.56 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ2 | 0.332 | 0.199 | 1.67 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ4 | 0.099 | 0.038 | 2.61 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ4 | 0.188 | 0.07 | 2.69 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ4 | 0.332 | 0.136 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ4 | 0.418 | 0.2 | 2.09 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ4 | 0.647 | 0.265 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ8 | 0.188 | 0.039 | 4.82 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ8 | 0.332 | 0.065 | 5.11 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ8 | 0.647 | 0.126 | 5.13 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ8 | 0.83 | 0.185 | 4.49 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ8 | 1.29 | 0.245 | 5.27 |\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n* Generation attention now enforces causal masking during token\ngeneration.\n\n* **Performance / Refactor**\n* Improved kernel selection and on-demand loading for better performance\nand GPU compatibility.\n* Added finer-grained tuning parameters for tile/grouping,\ntokens-per-CTA and inflation to enable more optimal kernel choices.\n\n* **Chores**\n * Updated FMHA artifact paths and checksums.\n\n* **Tests**\n* Expanded parameterized tests to cover larger batch decoding scenarios.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review\nsettings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n---------\n\nCo-authored-by: yzh119 <zihaoy@nvidia.com>\nCo-authored-by: Zihao Ye <expye@outlook.com>"},"path":{"kind":"string","value":"include/flashinfer/trtllm/fmha/kernelParams.h"},"language":{"kind":"string","value":"cpp"},"license":{"kind":"string","value":"BSD"},"before_code":{"kind":"string","value":"/***************************************************************************************************\n * Copyright (c) 2011-2024, NVIDIA CORPORATION. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without modification, are not permit-\n * ted.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND\n * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n **************************************************************************************************/\n#pragma once\n\n#ifdef _WIN32\n#define _USE_MATH_DEFINES\n#include <math.h>\n#endif\n\n#include <cutlass/cutlass.h>\n\n#include <cmath>\n#include <cstdint>\n#include <cute/tensor.hpp>\n\n#include \"../../utils.cuh\"\n#include \"../common.h\"\n#include \"fmhaRunnerParams.h\"\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nusing Dtype = Data_type;\n\nstruct KernelParams {\n // TMA descriptor for Q.\n CUtensorMap tmaQ_;\n // TMA descriptor for K.\n CUtensorMap tmaK_;\n // TMA descriptor for V.\n CUtensorMap tmaV_;\n // The descriptor for O.\n CUtensorMap tmaO_;\n\n // For FP4 KV cache, additional scaling factors are needed.\n // TMA descriptor for K scaling factor.\n CUtensorMap tmaKSf_;\n // TMA descriptor for V scaling factor.\n CUtensorMap tmaVSf_;\n\n // grid dimensions, these might differ from actual grid the kernel is launched with\n // for persistent kernels on Hopper GPUs.\n int32_t logicalGridDimX, logicalGridDimY, logicalGridDimZ;\n\n // The output pointer (used by STG for last tile).\n void* ptrO;\n // The output SF pointer (used for FP4 output).\n void* ptrSfO;\n // The attention sinks pointer (additional value per head in the denominator of the softmax).\n float const* ptrAttentionSinks;\n\n // The cumulative sequence lengths for Q.\n int32_t const* ptrCumSeqLensQ;\n // The cumulative sequence lengths for K/V.\n int32_t const* ptrCumSeqLensKv;\n // The packed custom mask.\n uint32_t const* ptrCustomMask;\n // The packed custom mask's offsets of each sequence.\n int64_t const* ptrCustomMaskOffsets;\n // The debug output matrix O\n float* ptrDebugO;\n // The first sparseMask offsets in the Kv sequence dimension.\n int32_t const* ptrFirstSparseMaskOffsetsKv;\n // The counter for the multiCtasKv mode.\n int32_t* ptrMultiCtasKvCounter;\n // The device output scale for FP8 quantization. Only needed by trt-llm fp8 kernels as the sca-\n // les have to be on the device currently.\n float const* ptrOutputScale;\n // The page indexes of the paged-kv buffer with shape of [batchSize, 2, maxNumPagesPerSeq].\n int32_t const* ptrPageIdxKv;\n // The partial matrix O for each CtaKv when the multiCtasKv mode is enabled.\n void* ptrPartialO;\n // The partial softmax stats (max/sum)for each CtaKv when the multiCtasKv mode is enabled.\n float2* ptrPartialStats;\n // The scaling factors for K.\n float const* ptrSageAttnSfsK;\n // The scaling factors for P.\n float const* ptrSageAttnSfsP;\n // The scaling factors for Q.\n float const* ptrSageAttnSfsQ;\n // The scaling factors for V.\n float const* ptrSageAttnSfsV;\n // The device scaling factor for softmax (multiplied by log2 to use faster exp2). Only needed by\n // trt-llm fp8 kernels as the scales have to be on the device currently.\n float const* ptrScaleSoftmaxLog2;\n // The SF scale for Kv on device. Only needed by trt-llm kernels as the scales have to be on the\n // device currently.\n float const* ptrScaleSfKv;\n // The SF scale for O on device. Only needed by trt-llm kernels as the scales have to be on the\n // device currently.\n float const* ptrScaleSfO;\n // The sequence lengths for K/V. Required by pagedKv kernels to avoid unnecessary computation\n // based on (ptrCumSeqLensKv[batchIdx + 1] - ptrCumSeqLensKv[batchIdx]).\n int32_t const* ptrSeqLensKv;\n // The reserved memory buffer.\n int32_t* ptrReservedMem;\n // The softmax stats buffer.\n float2* ptrSoftmaxStats;\n\n // The attention window size for sliding window attention.\n int32_t mAttentionWindowSize;\n // The batch size\n int32_t mBatchSize;\n // The chunked attention size in log2.\n int32_t mChunkedAttentionSizeLog2;\n // The log of the Sage Attention block size for K.\n int32_t mLogNumEltsPerSageAttnBlkK;\n // The log of the Sage Attention block size for P.\n int32_t mLogNumEltsPerSageAttnBlkP;\n // The log of the Sage Attention block size for Q.\n int32_t mLogNumEltsPerSageAttnBlkQ;\n // The log of the Sage Attention block size for V.\n int32_t mLogNumEltsPerSageAttnBlkV;\n // The sequence lengths for Q and K/V.\n int32_t mMaxSeqLenQ, mMaxSeqLenKv;\n // The maximum number of CTAs for Q.\n int32_t mMaxNumCtasQ;\n // The maximum number of CTAs for K/V.\n int32_t mMaxNumCtasKv;\n // The maximum number of pages per sequence for paged-kv buffer.\n int32_t mMaxNumPagesPerSeqKv;\n // The number of heads for K/V.\n int32_t mNumHeadsKv;\n // The number of heads for Q.\n int32_t mNumHeadsQ;\n // The number of Q heads per K/V head (i.e. mNumHeadsQ / mNumHeadsKv).\n int32_t mNumHeadsQPerKv;\n // The hidden size of O.\n int64_t mNumHiddenEltsO;\n // The total number of pages in the paged-kv memory pool.\n int32_t mNumPagesInMemPool;\n // The number of tokens per page (used if dynamic numTokensPerPage is enabled).\n int32_t mNumTokensPerPageLog2;\n // The output scale for FP8 quantization.\n float mOutputScale;\n // The scaling factor for softmax (multiplied by log2 to use faster exp2).\n float mScaleSoftmaxLog2;\n // The SF scale for Kv.\n float mScaleSfKv;\n // The SF scale for O.\n float mScaleSfO;\n // The reserved parameter.\n float mReservedParam;\n // The start token index in SF tensor. Used for FP4 SF offset calculation in generation phase\n // kernel when inflight batching is enabled in TRT-LLM.\n int32_t mStartTokenIdxSfO;\n // The sum of sequence lengths for Q and K/V.\n int32_t mSumOfSeqLensQ, mSumOfSeqLensKv;\n // The sparseMla topK value.\n int32_t mSparseMlaTopK;\n // The flag to use block sparse attention.\n bool mUseBlockSparseAttention;\n\n // Create the TMA shape/stride for Q.\n template <class FmhaOptions>\n static auto makeTmaShapeStrideQ(FmhaOptions const& options, bool groupsHeadsQ, int32_t tileSizeQ,\n int32_t numEltsInClampedHeadDimQ) {\n //\n // The Q has shape of [numTokens * numHeadsQPerKv, numHeadsKv * 1, headDim]\n // when grouping headsQ, otherwise it would be [numTokens, numHeadsQPerKv * numHeadsKv,\n // headDim].\n\n // The number of grouped heads for the A matrix of MMA.\n int32_t numGroupedHeads{1};\n if (groupsHeadsQ) {\n numGroupedHeads = std::min(tileSizeQ, options.mNumHeadsQPerKv);\n }\n\n // The number of heads.\n int32_t numHeads{options.mNumHeadsQ};\n if (groupsHeadsQ) {\n numHeads /= numGroupedHeads;\n }\n // Make sure the math works.\n FLASHINFER_CHECK(numHeads * numGroupedHeads == options.mNumHeadsQ, \"internal error\");\n\n // The number of tokens.\n int32_t numTokens{options.mSumOfSeqLensQ};\n\n // This maps to flattened TMA shape for Q: (headDim, numTokens, numHeads).\n auto shape = std::vector<uint64_t>{\n static_cast<uint64_t>(options.mHeadDimQk), static_cast<uint64_t>(numGroupedHeads),\n static_cast<uint64_t>(numHeads), static_cast<uint64_t>(numTokens)};\n\n // The stride between tokens.\n // Use user-provided stride if available, otherwise compute from layout.\n int32_t strideTokens{options.qStrideTokens};\n if (strideTokens == 0) {\n // The hidden dimension when the tensor contains only Q (i.e. not QKV packed).\n int32_t const hiddenDimQ{options.mNumHeadsQ * options.mHeadDimQk};\n // The hidden dimension when the Q, K and V tensors are packed.\n int32_t hiddenDimQkv{hiddenDimQ};\n if (isPackedQkv(options.mQkvLayout)) {\n FLASHINFER_CHECK(!groupsHeadsQ, \"internal error\");\n hiddenDimQkv += options.mNumHeadsKv * (options.mHeadDimQk + options.mHeadDimV);\n }\n strideTokens = hiddenDimQkv;\n }\n\n // The stride between heads.\n // Use user-provided stride if available, otherwise compute from layout.\n int32_t strideHeads{options.qStrideHeads};\n if (strideHeads == 0) {\n strideHeads = options.mHeadDimQk;\n }\n // The stride between grouped heads (consecutive heads within a GQA group).\n // Use user-provided stride if available, otherwise use headDimQk.\n int32_t strideGroupedHeads{options.qStrideHeads};\n if (strideGroupedHeads == 0) {\n strideGroupedHeads = options.mHeadDimQk;\n }\n\n // For GQA, the TMA iterates over groups of heads, so we need to multiply by numGroupedHeads.\n if (groupsHeadsQ) {\n strideHeads = numGroupedHeads * strideHeads;\n }\n\n // Assemble the stride (1, strideTokens, strideHeads).\n // Swap the first two dimension as mentioned before.\n auto stride = std::vector<uint64_t>{1, static_cast<uint64_t>(strideGroupedHeads),\n static_cast<uint64_t>(strideHeads),\n static_cast<uint64_t>(strideTokens)};\n\n // The tile shape for TMA.\n auto tileShapes = std::vector<uint32_t>{static_cast<uint32_t>(numEltsInClampedHeadDimQ), 1, 1,\n static_cast<uint32_t>(tileSizeQ)};\n if (groupsHeadsQ) {\n if (isSpecDecodingGenerationKernel(options.mKernelType)) {\n FLASHINFER_CHECK((tileSizeQ % numGroupedHeads == 0), \"internal error\");\n tileShapes = std::vector<uint32_t>{static_cast<uint32_t>(numEltsInClampedHeadDimQ),\n static_cast<uint32_t>(numGroupedHeads), 1,\n static_cast<uint32_t>(tileSizeQ / numGroupedHeads)};\n } else {\n tileShapes = std::vector<uint32_t>{static_cast<uint32_t>(numEltsInClampedHeadDimQ),\n static_cast<uint32_t>(tileSizeQ), 1, 1};\n }\n }\n\n return std::make_tuple(shape, stride, tileShapes);\n }\n\n // Create the TMA shape/stride for O.\n template <class FmhaOptions>\n static auto makeTmaShapeStrideO(FmhaOptions const& options) {\n //\n // TODO: refactor this as makeTmaShapeStrideQ when removing cutlass tma copy.\n //\n\n // The number of tokens.\n int32_t numTokens{options.mSumOfSeqLensQ};\n\n // The number of heads per K/V head.\n int32_t numHeadsQPerKv{options.mNumHeadsQPerKv};\n\n // The batch dimension.\n int32_t batchSize{1};\n\n // The cute tensor shape for Q/O: (numTokens, headDim, ((numHeadsKv, numHeadsQPerKv),\n // batchSize)). This maps to flattened TMA shape for Q/O: (headDim, numTokens, numHeadsKv.\n // numHeadsQPerKv, batchSize). Note that TMA descriptor expects the first dimension's stride to\n // be 1, so swap the first two dimension so that the headDim dimension comes first.\n auto shape = std::vector<uint64_t>{\n static_cast<uint64_t>(options.mHeadDimV), static_cast<uint64_t>(numTokens),\n static_cast<uint64_t>(options.mNumHeadsKv), static_cast<uint64_t>(numHeadsQPerKv),\n static_cast<uint64_t>(batchSize)};\n\n // The hidden dimension.\n int32_t const hiddenDimO{options.mNumHeadsQ * options.mHeadDimV};\n\n // The stride between tokens.\n int32_t strideTokens{hiddenDimO};\n\n // The stride between Q heads.\n int32_t strideHeadsQ{options.mNumHeadsKv * options.mHeadDimV};\n\n // The stride between sequences.\n int32_t strideBatch{0};\n\n // The stride in between K/V heads.\n int32_t strideHeadsKv{options.mHeadDimV};\n // Assemble the stride (strideTokens, 1, ((strideHeadsKv, strideHeadsQ), strideBatch)).\n // Swap the first two dimension as mentioned before.\n auto stride = std::vector<uint64_t>{\n 1, static_cast<uint64_t>(strideTokens), static_cast<uint64_t>(strideHeadsKv),\n static_cast<uint64_t>(strideHeadsQ), static_cast<uint64_t>(strideBatch)};\n\n return std::make_tuple(shape, stride);\n }\n\n // Create the shape for K and V.\n template <class FmhaOptions>\n static auto makeShapeKv(FmhaOptions const& options, KernelParams const& params) {\n // The number of keys/vals. WARNING: The if/else-if are sorted by priority.\n int32_t numKeysVals{options.mMaxSeqLenKv};\n if (isPagedKv(options.mQkvLayout)) {\n numKeysVals = options.mNumTokensPerPage;\n } else if (isContiguousKv(options.mQkvLayout)) {\n numKeysVals = options.mMaxSeqLenCacheKv;\n } else {\n numKeysVals = options.mSumOfSeqLensKv;\n }\n\n // The number of heads per K/V head (packed in the sequence length for mGroupsHeadsQ).\n int32_t numHeadsKv{options.mNumHeadsKv};\n\n // The batch dimension. WARNING: The if/else-if are sorted by priority.\n int32_t batchSize{options.mBatchSize};\n if (isPagedKv(options.mQkvLayout)) {\n batchSize = params.mNumPagesInMemPool;\n } else if (isContiguousKv(options.mQkvLayout)) {\n batchSize = options.mBatchSize;\n } else {\n batchSize = 1;\n }\n\n // Return the number of keys and batch.\n return std::make_tuple(numKeysVals, numHeadsKv, batchSize);\n }\n\n // Compute the strides for K and V.\n template <class FmhaOptions>\n static auto makeStrideKv(FmhaOptions const& options, bool isK) {\n int strideKeysVals = 0;\n int strideHeads = 0;\n int strideBatch = 0;\n\n if (isK) {\n strideKeysVals = options.kStrideKeysValues;\n strideHeads = options.kStrideHeads;\n strideBatch = options.kStrideBatch;\n } else {\n strideKeysVals = options.vStrideKeysValues;\n strideHeads = options.vStrideHeads;\n strideBatch = options.vStrideBatch;\n }\n\n // Ragged layout has no batch stride; reset negative overflow to 0 for TMA descriptor.\n if (!isPagedKv(options.mQkvLayout) && !isContiguousKv(options.mQkvLayout) && strideBatch < 0) {\n strideBatch = 0;\n }\n\n // The 3 strides (the other ones are 1 and 0).\n return std::make_tuple(strideKeysVals, strideHeads, strideBatch);\n }\n\n // Create the TMA shape/stride for K.\n template <class FmhaOptions>\n static auto makeTmaShapeStrideKv(FmhaOptions const& options, KernelParams const& params,\n Data_type dtypeKv, bool isK) {\n // The shape elements.\n auto [numKeys, numHeadsQPerKv, batchSize] = makeShapeKv(options, params);\n // The stride elements.\n auto [strideKeys, strideHeads, strideBatch] = makeStrideKv(options, isK);\n\n // The headDim.\n // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv.\n int32_t headDim = isK ? options.mHeadDimQk : options.mHeadDimV;\n if (isPagedKv(options.mQkvLayout) || isContiguousKv(options.mQkvLayout)) {\n headDim = std::max(options.mHeadDimQk, options.mHeadDimV);\n }\n\n // For K, the cute layout: (numKeys, headDim, ((numHeadsQPerKv, numHeadsKv),\n // batchSize)):(strideKeys, _1, _0, strideHeads, strideBatch). Cute swaps the first two\n // dimension (to make sure stride of first dimension is 1) and ignores the numHeadsQPerKv\n // dimension (it's stride is always 0). For V, the headDim dimension is already the first\n // dimension so no swapping is needed.\n\n // Therefore, the resulting TMA layout is 4D: (headDim, numKeys, numHeadsKv, batchSize):(1,\n // strideKeys, strideHeads, strideBatch)\n\n // Note that for FP4 KV input, elements are stored as uint8_t, each packs 2 FP4 elements.\n // The column index and strides needs to divide by 2.\n auto const colIdxDivisor = dtypeKv == DATA_TYPE_E2M1 ? 2 : 1;\n auto shape = std::vector<uint64_t>{\n static_cast<uint64_t>(headDim / colIdxDivisor), static_cast<uint64_t>(numKeys),\n static_cast<uint64_t>(options.mNumHeadsKv), static_cast<uint64_t>(batchSize)};\n auto stride = std::vector<uint64_t>{1, static_cast<uint64_t>(strideKeys / colIdxDivisor),\n static_cast<uint64_t>(strideHeads / colIdxDivisor),\n static_cast<uint64_t>(strideBatch / colIdxDivisor)};\n\n return std::make_tuple(shape, stride);\n }\n\n // Create the TMA shape/stride for KV scaling factors.\n template <class FmhaOptions>\n static auto makeTmaShapeStrideKvSf(FmhaOptions const& options, KernelParams const& params,\n bool isK) {\n // The shape elements.\n auto [numKeys, numHeadsQPerKv, batchSize] = makeShapeKv(options, params);\n // The stride elements.\n auto [strideKeys, strideHeads, strideBatch] = makeStrideKv(options, isK);\n\n // The headDim.\n // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv.\n int32_t headDim = isK ? options.mHeadDimQk : options.mHeadDimV;\n if (isPagedKv(options.mQkvLayout) || isContiguousKv(options.mQkvLayout)) {\n headDim = std::max(options.mHeadDimQk, options.mHeadDimV);\n }\n // The number of elements per SF.\n int32_t NumEltsPerSf = 16;\n\n // The KV shape is: (headDim, numKeys, numHeadsKv, batchSize)\n // Therefore, the KV SF shape should be (headDim / NumEltsPerSf, numKeys, numHeadsKv,\n // batchSize). Considering the TMA requires box width to be multiple of 16B, without changing\n // the underlying layout, we reshape into (16, numKeys * headDim / NumEltsPerSf / 16,\n // numHeadsKv, batchSize)\n\n // Note that it only works for pagedKv layout.\n FLASHINFER_CHECK(isPagedKv(options.mQkvLayout), \"The qkvLayout is not supported.\");\n\n auto shape = std::vector<uint64_t>{\n 16, static_cast<uint64_t>(numKeys * headDim / NumEltsPerSf / 16),\n static_cast<uint64_t>(options.mNumHeadsKv), static_cast<uint64_t>(batchSize)};\n auto stride = std::vector<uint64_t>{1, 16, static_cast<uint64_t>(strideHeads / NumEltsPerSf),\n static_cast<uint64_t>(strideBatch / NumEltsPerSf)};\n\n return std::make_tuple(shape, stride);\n }\n\n // Prepare pointers for TMA descriptors.\n static std::tuple<void const*, void const*, void const*> getDevicePtrs(\n TllmGenFmhaRunnerParams const& runnerParams, int32_t bytesPerElt) {\n // Declare the q, k, v ptrs.\n void const *qPtr{runnerParams.qPtr}, *kPtr{runnerParams.kPtr}, *vPtr{runnerParams.vPtr};\n\n // Set Q, K and V pointer from packed QKV tensor.\n if (isPackedQkv(runnerParams.mQkvLayout)) {\n qPtr = runnerParams.qkvPtr;\n kPtr = reinterpret_cast<void const*>(reinterpret_cast<char const*>(runnerParams.qkvPtr) +\n runnerParams.mNumHeadsQ * runnerParams.mHeadDimQk *\n bytesPerElt);\n vPtr = reinterpret_cast<void const*>(reinterpret_cast<char const*>(runnerParams.qkvPtr) +\n (runnerParams.mNumHeadsQ + runnerParams.mNumHeadsKv) *\n runnerParams.mHeadDimQk * bytesPerElt);\n }\n // Set K and V pointer from pagedKv tensor.\n else if (isPagedKv(runnerParams.mQkvLayout)) {\n // Note that the offsets will be fully handled by the pageIdx buffer.\n kPtr = runnerParams.kPtr;\n vPtr = runnerParams.vPtr;\n }\n // Set K and V pointer from contiguousQAnddKv tensor.\n else if (isContiguousKv(runnerParams.mQkvLayout)) {\n kPtr = runnerParams.kvPtr;\n // The maximum headDim of K and V.\n // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv.\n int32_t const maxHeadDimKv{std::max(runnerParams.mHeadDimQk, runnerParams.mHeadDimV)};\n vPtr = reinterpret_cast<void const*>(\n reinterpret_cast<char const*>(runnerParams.kvPtr) +\n runnerParams.mNumHeadsKv * runnerParams.mMaxSeqLenCacheKv * maxHeadDimKv * bytesPerElt);\n }\n\n // Return the pointers.\n return std::make_tuple(qPtr, kPtr, vPtr);\n }\n\n // Build tma descriptors.\n template <class FmhaOptions>\n static CUtensorMap buildNdTmaDescriptor(FmhaOptions const& options, Data_type dtypeElt,\n std::vector<uint64_t> const& shapes,\n std::vector<uint64_t> const& strides,\n std::vector<uint32_t> const& tileShapes, void* gmemAddr,\n bool swizzled = true) {\n CUtensorMap desc{};\n // The data type.\n CUtensorMapDataType tmaDataFormat;\n if (dtypeElt == DATA_TYPE_E2M1 || dtypeElt == DATA_TYPE_E4M3) {\n tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_UINT8;\n } else if (dtypeElt == DATA_TYPE_FP16) {\n tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_FLOAT16;\n } else if (dtypeElt == DATA_TYPE_BF16) {\n tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_BFLOAT16;\n } else {\n FLASHINFER_CHECK(false, \"Unexpected dtype %d\", static_cast<int32_t>(dtypeElt));\n }\n\n // The swizzle type.\n CUtensorMapSwizzle swizzleType;\n int32_t numBytesInLeadingDim = tileShapes[0] * get_size_in_bits(dtypeElt) / 8 /*bits*/;\n if (!swizzled) {\n swizzleType = CU_TENSOR_MAP_SWIZZLE_NONE;\n } else if ((numBytesInLeadingDim % 128) == 0) {\n swizzleType = CU_TENSOR_MAP_SWIZZLE_128B;\n } else if ((numBytesInLeadingDim % 64) == 0) {\n swizzleType = CU_TENSOR_MAP_SWIZZLE_64B;\n } else if ((numBytesInLeadingDim % 32) == 0) {\n swizzleType = CU_TENSOR_MAP_SWIZZLE_32B;\n } else {\n FLASHINFER_CHECK(false, \"Unexpected numBytesInLeadingDim %d\", numBytesInLeadingDim);\n }\n\n // Check gmem address must be 16B-aligned\n FLASHINFER_CHECK((reinterpret_cast<uint64_t>(gmemAddr) & 0b1111) == 0);\n\n // Check shape must be in range [1, 2^32]\n int32_t dim = shapes.size();\n // Max five dimension and min 2 dimension.\n FLASHINFER_CHECK((dim <= 5) && (dim >= 2));\n // Check shape range.\n for (int32_t ii = 0; ii < dim; ++ii) {\n FLASHINFER_CHECK(shapes[ii] >= (uint64_t(1))); // Size must be min 1\n FLASHINFER_CHECK(shapes[ii] <= (uint64_t(1) << 32)); // Size must be max 2^32\n }\n\n // TMA descriptor does not store the zeroth stride and assumes it is 1.\n FLASHINFER_CHECK(static_cast<int32_t>(strides.size()) == dim);\n FLASHINFER_CHECK(strides[0] == 1);\n\n // Build strides in bytes.\n // cuTensorMapEncodeTiled ignores the stride of the first dimension (implicitly 1).\n std::vector<uint64_t> stridesInBytes(dim - 1);\n for (int32_t ii = 0; ii < dim - 1; ++ii) {\n stridesInBytes[ii] = strides[ii + 1] *\n std::max(get_size_in_bits(dtypeElt), static_cast<size_t>(8)) / 8 /*bit*/;\n }\n\n // Set tile strides to 0;\n std::vector<uint32_t> tileStrides(dim, 1);\n\n // Build the descriptor.\n CUresult result =\n cuTensorMapEncodeTiled(&desc, tmaDataFormat,\n /*tensorRank=*/dim, gmemAddr, shapes.data(), stridesInBytes.data(),\n tileShapes.data(), tileStrides.data(),\n /*interleave=*/CU_TENSOR_MAP_INTERLEAVE_NONE, swizzleType,\n /*l2Promotion=*/CU_TENSOR_MAP_L2_PROMOTION_L2_128B,\n /*oobFill=*/CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE);\n\n if (result != CUDA_SUCCESS) {\n char const* err_str;\n cuGetErrorString(result, &err_str);\n std::cerr << \"Error: Failed to initialize the TMA descriptor due to \" << err_str << std::endl;\n std::cerr << \"tmaFormat: \" << static_cast<int>(tmaDataFormat) << \" dim: \" << dim\n << \" gmem: \" << gmemAddr << std::endl;\n std::cerr << \"Shape: \" << shapes[0] << \" \" << shapes[1] << \" \" << shapes[2] << \" \"\n << shapes[3] << \" \" << shapes[4] << std::endl;\n std::cerr << \"Stride: \" << stridesInBytes[0] << \" \" << stridesInBytes[1] << \" \"\n << stridesInBytes[2] << \" \" << stridesInBytes[3] << std::endl;\n std::cerr << \"tileShapes: \" << tileShapes[0] << \" \" << tileShapes[1] << \" \" << tileShapes[2]\n << \" \" << tileShapes[3] << \" \" << tileShapes[4] << std::endl;\n std::cerr << \"tileStrides: \" << tileStrides[0] << \" \" << tileStrides[1] << \" \"\n << tileStrides[2] << \" \" << tileStrides[3] << \" \" << tileStrides[4] << std::endl;\n std::cerr << \"swizzleType: \" << int(swizzleType) << std::endl;\n FLASHINFER_CHECK(false);\n }\n\n return desc;\n }\n\n // Setup the kernel parameters.\n template <class FmhaOptions_, class KernelMeta>\n static KernelParams setKernelParams(FmhaOptions_ const& options, KernelMeta const& kernelMeta,\n int32_t maxNumCtasQ, int32_t maxNumCtasKv) {\n // Create the return struct.\n KernelParams params;\n // Memset the kernel parameters to 0.\n memset(¶ms, 0, sizeof(KernelParams));\n\n // Get the device pointers for TMA descriptors.\n auto [qPtr, kPtr, vPtr] = getDevicePtrs(options, get_size_in_bytes(kernelMeta.mDataTypeKv));\n\n // The maximum headDim of K and V.\n // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv.\n int32_t const maxHeadDimKv{std::max(options.mHeadDimQk, options.mHeadDimV)};\n\n // Set the number of pages in the memory pool for paged K/V cache.\n if (isPagedKv(options.mQkvLayout)) {\n params.mNumPagesInMemPool = options.mNumPagesInMemPool == 0\n ? options.mMaxNumPagesPerSeqKv * 2 * options.mBatchSize\n : options.mNumPagesInMemPool;\n }\n\n // The number of elements in 128B for Q.\n int32_t numEltsIn128BQ = (128 * 8) / get_size_in_bits(kernelMeta.mDataTypeQ);\n // The number of head elts (per token) in each block of shared memory.\n int32_t numEltsInClampedHeadDimQ = std::min(numEltsIn128BQ, options.mHeadDimQk);\n\n // Shape/stride for gmem tensor Q.\n auto [shapeQ, strideQ, tileShapeQ] = makeTmaShapeStrideQ(\n options, kernelMeta.mGroupsHeadsQ, kernelMeta.mTileSizeQ, numEltsInClampedHeadDimQ);\n // Build tma descriptor for Q.\n params.tmaQ_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeQ, shapeQ, strideQ, tileShapeQ,\n const_cast<void*>(qPtr));\n\n // The number of keys per tile.\n int32_t numKeysPerTile = isPagedKv(options.mQkvLayout)\n ? std::min(options.mNumTokensPerPage, kernelMeta.mTileSizeKv)\n : kernelMeta.mTileSizeKv;\n // The number of elements in 128B for Q.\n int32_t numEltsIn128BKv = (128 * 8) / get_size_in_bits(kernelMeta.mDataTypeKv);\n // The number of head elts (per token) in each block of shared memory (see above explanation).\n int32_t numEltsInClampedHeadDimKv = std::min(numEltsIn128BKv, maxHeadDimKv);\n\n // Shape/stride for gmem tensor Kv.\n auto [shapeK, strideK] =\n makeTmaShapeStrideKv(options, params, kernelMeta.mDataTypeKv, /*isK*/ true);\n auto [shapeV, strideV] =\n makeTmaShapeStrideKv(options, params, kernelMeta.mDataTypeKv, /*isK*/ false);\n // Build tma descriptor for K.\n // Do we have to transform K/V before MMA?\n bool const transformsKv{kernelMeta.mDataTypeKv != kernelMeta.mDataTypeQ};\n // Note that for FP4 KV input, elements are stored as uint8_t, each packs 2 FP4 elements.\n auto const numEltsDivisor = kernelMeta.mDataTypeKv == DATA_TYPE_E2M1 ? 2 : 1;\n // The tileShapes for K/V.\n std::vector<uint32_t> tileShapeKv(shapeK.size(), 1);\n tileShapeKv[0] = numEltsInClampedHeadDimKv / numEltsDivisor;\n tileShapeKv[1] = numKeysPerTile;\n\n // If sparse MLA is enabled, the shape and stride for K need to be updated for 2D layout\n // (numTokensKvInPagedKv, headDimQk).\n if (options.mSparseMla) {\n shapeK = std::vector<uint64_t>{static_cast<uint64_t>(options.mHeadDimQk),\n static_cast<uint64_t>(INT_MAX)};\n strideK = std::vector<uint64_t>{1, static_cast<uint64_t>(options.mHeadDimQk)};\n tileShapeKv[1] = 1;\n }\n\n // Build tma descriptor for K.\n params.tmaK_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeKv, shapeK, strideK,\n tileShapeKv, const_cast<void*>(kPtr),\n /*swizzled = */ !transformsKv);\n // Build tma descriptor for V.\n params.tmaV_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeKv, shapeV, strideV,\n tileShapeKv, const_cast<void*>(vPtr),\n /*swizzled = */ !transformsKv);\n\n // If the KV dtype is E2m1, additional scaling factors are needed for dequant.\n if (kernelMeta.mDataTypeKv == DATA_TYPE_E2M1) {\n // The number of elements per SF.\n int32_t NumEltsPerSf = 16;\n // Compute the shape and stride for SF tensor.\n // FIXME: assume K and V uses the same shape.\n auto [shapeKvSf, strideKvSf] = makeTmaShapeStrideKvSf(options, params, /*isK*/ true);\n\n // The tileShapes for K/V.\n std::vector<uint32_t> tileShapeKvSf(shapeKvSf.size(), 1);\n tileShapeKvSf[0] = 16;\n tileShapeKvSf[1] = numKeysPerTile * maxHeadDimKv / NumEltsPerSf / 16;\n\n // The tile box is reshaped from (headDim / NumEltsPerSf, tileSizeKv) into (16, tileSizeKv *\n // headDim / NumEltsPerSf / 16). See makeTmaShapeStrideKvSf for details. Build tma descriptor\n // for K SF.\n params.tmaKSf_ = buildNdTmaDescriptor(options, DATA_TYPE_E4M3, shapeKvSf, strideKvSf,\n tileShapeKvSf, const_cast<void*>(options.kSfBasePtr),\n /*swizzled = */ false);\n\n // Build tma descriptor for V SF.\n params.tmaVSf_ = buildNdTmaDescriptor(options, DATA_TYPE_E4M3, shapeKvSf, strideKvSf,\n tileShapeKvSf, const_cast<void*>(options.vSfBasePtr),\n /*swizzled = */ false);\n }\n\n // Shape/stride for gmem tensor O.\n auto [shapeO, strideO] = makeTmaShapeStrideO(options);\n // The tileShapes for O.\n std::vector<uint32_t> tileShapeO(shapeO.size(), 1);\n tileShapeO[0] = numEltsInClampedHeadDimQ;\n tileShapeO[1] = kernelMeta.mTileSizeQ;\n // Build tma descriptor for O.\n params.tmaO_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeQ, shapeO, strideO, tileShapeO,\n const_cast<void*>(options.oPtr));\n\n // Set the other kernel parameters.\n params.ptrCumSeqLensQ = options.cumSeqLensQPtr;\n params.ptrCumSeqLensKv = options.cumSeqLensKvPtr;\n\n // The packed custom mask.\n params.ptrCustomMask = options.customMaskPtr;\n // The packed custom mask's offsets of each sequence.\n params.ptrCustomMaskOffsets = options.customMaskOffsetsPtr;\n // The first sparseMask offsets in the Kv sequence dimension.\n params.ptrFirstSparseMaskOffsetsKv = options.firstSparseMaskOffsetsKvPtr;\n\n // The output buffer.\n params.ptrO = options.oPtr;\n // The output scaling factor buffer.\n params.ptrSfO = options.oSfPtr;\n\n // TRT-LLM restrictions: the quantization scales must be on the device.\n params.ptrOutputScale = options.outputScalePtr;\n\n // The sequence lengths for Kv.\n params.ptrSeqLensKv = options.seqLensKvPtr;\n\n // Attention sink\n params.ptrAttentionSinks = options.ptrAttentionSinks;\n\n // The partial buffers' pointers when the multiCtasKv mode is enabled.\n int64_t partialStatsBufferSize = options.mMultiProcessorCount * kernelMeta.mStepQ;\n params.ptrMultiCtasKvCounter = options.multiCtasKvCounterPtr;\n params.ptrPartialStats = reinterpret_cast<float2*>(options.multiCtasKvScratchPtr);\n params.ptrPartialO = params.ptrPartialStats + partialStatsBufferSize;\n\n params.ptrPageIdxKv = options.kvPageIdxPtr;\n params.ptrScaleSoftmaxLog2 = options.scaleSoftmaxLog2Ptr;\n\n params.ptrScaleSfKv = options.kvSfScalePtr;\n params.ptrScaleSfO = options.oSfScalePtr;\n params.mScaleSfO = options.mScaleSfO;\n\n params.mAttentionWindowSize = options.mAttentionWindowSize;\n if (isSlidingOrChunkedCausalMask(\n static_cast<TrtllmGenAttentionMaskType>(kernelMeta.mMaskType)) &&\n options.mChunkedAttentionSize != INT_MAX) {\n FLASHINFER_CHECK((options.mChunkedAttentionSize & (options.mChunkedAttentionSize - 1)) == 0,\n \"Chunked attention size must be a power of 2\");\n params.mChunkedAttentionSizeLog2 = std::log2(options.mChunkedAttentionSize);\n } else {\n // Default 0 means that chunked attention is disabled.\n params.mChunkedAttentionSizeLog2 = 0;\n }\n\n // Compute the log of numTokensPerPage\n int32_t numTokensPerPageLog2{-1};\n if (isPagedKv(options.mQkvLayout)) {\n FLASHINFER_CHECK((options.mNumTokensPerPage & (options.mNumTokensPerPage - 1)) == 0,\n \"NumTokensPerPage must be power of 2\");\n numTokensPerPageLog2 = (int)log2f((float)options.mNumTokensPerPage);\n }\n params.mNumTokensPerPageLog2 = numTokensPerPageLog2;\n\n params.mMaxSeqLenQ = options.mMaxSeqLenQ;\n params.mMaxSeqLenKv = options.mMaxSeqLenKv;\n params.mMaxNumCtasQ = maxNumCtasQ;\n params.mMaxNumCtasKv = maxNumCtasKv;\n params.mMaxNumPagesPerSeqKv = options.mMaxNumPagesPerSeqKv;\n // TODO: just use mMaxSeqLenQ for number of MTP tokens.\n params.mSumOfSeqLensQ = options.mSumOfSeqLensQ;\n params.mSumOfSeqLensKv = options.mSumOfSeqLensKv;\n params.mBatchSize = options.mBatchSize;\n params.mChunkedAttentionSizeLog2 = 0;\n params.mNumHeadsQ = options.mNumHeadsQ;\n params.mNumHeadsKv = options.mNumHeadsKv;\n params.mNumHeadsQPerKv = options.mNumHeadsQPerKv;\n params.mNumHiddenEltsO = options.mNumHeadsQ * options.mHeadDimQk;\n params.mOutputScale = options.outputScale;\n params.mScaleSoftmaxLog2 = options.scaleSoftmaxLog2;\n params.mStartTokenIdxSfO = options.mSfStartTokenIdx;\n params.mScaleSfKv = options.mScaleSfKv;\n params.ptrSoftmaxStats = options.softmaxStatsPtr;\n // The sparseMlaTopK needs to be a multiple of 4 as we use 16B cpAsync instructions for the\n // indices.\n FLASHINFER_CHECK(!options.mSparseMla || (options.mSparseMlaTopK % 4) == 0,\n \"SparseMlaTopK must be a multiple of 4\");\n params.mSparseMlaTopK = options.mSparseMlaTopK;\n // TODO: Integrate trtllm block-sparse attention kernels when needed.\n params.mUseBlockSparseAttention = false;\n return params;\n }\n};\n"},"after_code":{"kind":"string","value":"/***************************************************************************************************\n * Copyright (c) 2011-2024, NVIDIA CORPORATION. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without modification, are not permit-\n * ted.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND\n * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n **************************************************************************************************/\n#pragma once\n\n#ifdef _WIN32\n#define _USE_MATH_DEFINES\n#include <math.h>\n#endif\n\n#include <cutlass/cutlass.h>\n\n#include <cmath>\n#include <cstdint>\n#include <cute/tensor.hpp>\n\n#include \"../../utils.cuh\"\n#include \"../common.h\"\n#include \"fmhaRunnerParams.h\"\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n\n//\n// CCCL >= 3.1.0 (CUDA CTK 13.1) introduces the fast_mod_div math operations.\n// The following code makes sure that the host initialization works with older CUDA CTK versions.\n//\n\n// Refer to\n// https://github.com/NVIDIA/cccl/blob/main/libcudacxx/include/cuda/__cmath/fast_modulo_division.h#L76-L81\n// about how to compute the fast modulo division.\nstruct FastModDivInt32 {\n public:\n FastModDivInt32(int32_t divisor) : mDivisor(divisor) {\n mShift = std::max(ceilLog2(mDivisor) - 1, 0);\n mMultiplier = static_cast<uint32_t>(\n flashinfer::ceil_div(uint64_t(1) << (32 + mShift), static_cast<uint64_t>(mDivisor)));\n }\n\n private:\n int32_t ceilLog2(int32_t value) const {\n return static_cast<int32_t>(std::ceil(std::log2(value)));\n }\n\n private:\n int32_t mDivisor = 1;\n uint32_t mMultiplier = 0;\n uint32_t mAdd = 0;\n int32_t mShift = 0;\n};\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nusing Dtype = Data_type;\n\nstruct KernelParams {\n // TMA descriptor for Q.\n CUtensorMap tmaQ_;\n // TMA descriptor for K.\n CUtensorMap tmaK_;\n // TMA descriptor for V.\n CUtensorMap tmaV_;\n // The descriptor for O.\n CUtensorMap tmaO_;\n\n // For FP4 KV cache, additional scaling factors are needed.\n // TMA descriptor for K scaling factor.\n CUtensorMap tmaKSf_;\n // TMA descriptor for V scaling factor.\n CUtensorMap tmaVSf_;\n\n // grid dimensions, these might differ from actual grid the kernel is launched with\n // for persistent kernels on Hopper GPUs.\n int32_t logicalGridDimX, logicalGridDimY, logicalGridDimZ;\n\n // The output pointer (used by STG for last tile).\n void* ptrO;\n // The output SF pointer (used for FP4 output).\n void* ptrSfO;\n // The attention sinks pointer (additional value per head in the denominator of the softmax).\n float const* ptrAttentionSinks;\n\n // The cumulative sequence lengths for Q.\n int32_t const* ptrCumSeqLensQ;\n // The cumulative sequence lengths for K/V.\n int32_t const* ptrCumSeqLensKv;\n // The packed custom mask.\n uint32_t const* ptrCustomMask;\n // The packed custom mask's offsets of each sequence.\n int64_t const* ptrCustomMaskOffsets;\n // The debug output matrix O\n float* ptrDebugO;\n // The first sparseMask offsets in the Kv sequence dimension.\n int32_t const* ptrFirstSparseMaskOffsetsKv;\n // The counter for the multiCtasKv mode.\n int32_t* ptrMultiCtasKvCounter;\n // The device output scale for FP8 quantization. Only needed by trt-llm fp8 kernels as the sca-\n // les have to be on the device currently.\n float const* ptrOutputScale;\n // The page indexes of the paged-kv buffer with shape of [batchSize, 2, maxNumPagesPerSeq].\n int32_t const* ptrPageIdxKv;\n // The partial matrix O for each CtaKv when the multiCtasKv mode is enabled.\n void* ptrPartialO;\n // The partial softmax stats (max/sum)for each CtaKv when the multiCtasKv mode is enabled.\n float2* ptrPartialStats;\n // The scaling factors for K.\n float const* ptrSageAttnSfsK;\n // The scaling factors for P.\n float const* ptrSageAttnSfsP;\n // The scaling factors for Q.\n float const* ptrSageAttnSfsQ;\n // The scaling factors for V.\n float const* ptrSageAttnSfsV;\n // The device scaling factor for softmax (multiplied by log2 to use faster exp2). Only needed by\n // trt-llm fp8 kernels as the scales have to be on the device currently.\n float const* ptrScaleSoftmaxLog2;\n // The SF scale for Kv on device. Only needed by trt-llm kernels as the scales have to be on the\n // device currently.\n float const* ptrScaleSfKv;\n // The SF scale for O on device. Only needed by trt-llm kernels as the scales have to be on the\n // device currently.\n float const* ptrScaleSfO;\n // The sequence lengths for K/V. Required by pagedKv kernels to avoid unnecessary computation\n // based on (ptrCumSeqLensKv[batchIdx + 1] - ptrCumSeqLensKv[batchIdx]).\n int32_t const* ptrSeqLensKv;\n // The reserved memory buffer.\n int32_t* ptrReservedMem;\n // The softmax stats buffer.\n float2* ptrSoftmaxStats;\n\n // The attention window size for sliding window attention.\n int32_t mAttentionWindowSize;\n // The batch size\n int32_t mBatchSize;\n // The chunked attention size in log2.\n int32_t mChunkedAttentionSizeLog2;\n // The factor to add to the maximum value to increase the probability\n // of skip correction during next iterations.\n float mInflateMax;\n // The log of the Sage Attention block size for K.\n int32_t mLogNumEltsPerSageAttnBlkK;\n // The log of the Sage Attention block size for P.\n int32_t mLogNumEltsPerSageAttnBlkP;\n // The log of the Sage Attention block size for Q.\n int32_t mLogNumEltsPerSageAttnBlkQ;\n // The log of the Sage Attention block size for V.\n int32_t mLogNumEltsPerSageAttnBlkV;\n // The sequence lengths for Q and K/V.\n int32_t mMaxSeqLenQ, mMaxSeqLenKv;\n // The maximum number of CTAs for Q.\n int32_t mMaxNumCtasQ;\n // The maximum number of CTAs for K/V.\n int32_t mMaxNumCtasKv;\n // The maximum number of pages per sequence for paged-kv buffer.\n int32_t mMaxNumPagesPerSeqKv;\n // The number of heads for K/V.\n int32_t mNumHeadsKv;\n // The number of heads for Q.\n int32_t mNumHeadsQ;\n // The number of Q heads per K/V head (i.e. mNumHeadsQ / mNumHeadsKv).\n int32_t mNumHeadsQPerKv;\n // The number of headsQ per K/V head as a fast_mod_div divisor.\n FastModDivInt32 mNumHeadsQPerKvDivisor{1};\n // The hidden size of O.\n int64_t mNumHiddenEltsO;\n // The total number of pages in the paged-kv memory pool.\n int32_t mNumPagesInMemPool;\n // The number of tokensQ per CTA (used for groupsHeadsTokensQ generation kernel).\n int32_t mNumTokensPerCtaQ;\n // The number of tokens per page (used if dynamic numTokensPerPage is enabled).\n int32_t mNumTokensPerPageLog2;\n // The output scale for FP8 quantization.\n float mOutputScale;\n // The scaling factor for softmax (multiplied by log2 to use faster exp2).\n float mScaleSoftmaxLog2;\n // The SF scale for Kv.\n float mScaleSfKv;\n // The SF scale for O.\n float mScaleSfO;\n // The reserved parameter.\n float mReservedParam;\n // The start token index in SF tensor. Used for FP4 SF offset calculation in generation phase\n // kernel when inflight batching is enabled in TRT-LLM.\n int32_t mStartTokenIdxSfO;\n // The sum of sequence lengths for Q and K/V.\n int32_t mSumOfSeqLensQ, mSumOfSeqLensKv;\n // The sparseMla topK value.\n int32_t mSparseMlaTopK;\n // The flag to use block sparse attention.\n bool mUseBlockSparseAttention;\n\n // Create the TMA shape/stride for Q.\n template <class FmhaOptions>\n static auto makeTmaShapeStrideQ(FmhaOptions const& options, bool groupsHeadsQ,\n bool groupsTokensHeadsQ, int32_t tileSizeQ,\n int32_t numEltsInClampedHeadDimQ) {\n //\n // The Q has shape of [numTokens * numHeadsQPerKv, numHeadsKv * 1, headDim]\n // when grouping headsQ, otherwise it would be [numTokens, numHeadsQPerKv * numHeadsKv,\n // headDim].\n\n // The number of grouped heads for the A matrix of MMA.\n int32_t numGroupedHeads{1};\n if (groupsHeadsQ) {\n numGroupedHeads = std::min(tileSizeQ, options.mNumHeadsQPerKv);\n }\n\n // The number of heads.\n int32_t numHeads{options.mNumHeadsQ};\n if (groupsHeadsQ) {\n numHeads /= numGroupedHeads;\n }\n // Make sure the math works.\n FLASHINFER_CHECK(numHeads * numGroupedHeads == options.mNumHeadsQ, \"internal error\");\n\n // The number of tokens.\n int32_t numTokens{options.mSumOfSeqLensQ};\n\n // This maps to flattened TMA shape for Q: (headDim, numTokens, numHeads).\n auto shape = std::vector<uint64_t>{\n static_cast<uint64_t>(options.mHeadDimQk), static_cast<uint64_t>(numGroupedHeads),\n static_cast<uint64_t>(numHeads), static_cast<uint64_t>(numTokens)};\n\n // The stride between tokens.\n // Use user-provided stride if available, otherwise compute from layout.\n int32_t strideTokens{options.qStrideTokens};\n if (strideTokens == 0) {\n // The hidden dimension when the tensor contains only Q (i.e. not QKV packed).\n int32_t const hiddenDimQ{options.mNumHeadsQ * options.mHeadDimQk};\n // The hidden dimension when the Q, K and V tensors are packed.\n int32_t hiddenDimQkv{hiddenDimQ};\n if (isPackedQkv(options.mQkvLayout)) {\n FLASHINFER_CHECK(!groupsHeadsQ, \"internal error\");\n hiddenDimQkv += options.mNumHeadsKv * (options.mHeadDimQk + options.mHeadDimV);\n }\n strideTokens = hiddenDimQkv;\n }\n\n // The stride between heads.\n // Use user-provided stride if available, otherwise compute from layout.\n int32_t strideHeads{options.qStrideHeads};\n if (strideHeads == 0) {\n strideHeads = options.mHeadDimQk;\n }\n // The stride between grouped heads (consecutive heads within a GQA group).\n // Use user-provided stride if available, otherwise use headDimQk.\n int32_t strideGroupedHeads{options.qStrideHeads};\n if (strideGroupedHeads == 0) {\n strideGroupedHeads = options.mHeadDimQk;\n }\n\n // For GQA, the TMA iterates over groups of heads, so we need to multiply by numGroupedHeads.\n if (groupsHeadsQ) {\n strideHeads = numGroupedHeads * strideHeads;\n }\n\n // Assemble the stride (1, strideTokens, strideHeads).\n // Swap the first two dimension as mentioned before.\n auto stride = std::vector<uint64_t>{1, static_cast<uint64_t>(strideGroupedHeads),\n static_cast<uint64_t>(strideHeads),\n static_cast<uint64_t>(strideTokens)};\n\n // The tile shape for TMA.\n auto tileShapes = std::vector<uint32_t>{static_cast<uint32_t>(numEltsInClampedHeadDimQ), 1, 1,\n static_cast<uint32_t>(tileSizeQ)};\n // The number of tokensQ per CTA.\n int32_t numTokensPerCtaQ{tileSizeQ};\n // Re-compute the number of tokensQ per CTA if groupsHeadsQ is enabled.\n if (groupsHeadsQ) {\n if (groupsTokensHeadsQ) {\n // Currently, it requires each CTA to process complete headsQ (i.e. numGroupedHeads) at a\n // time, so it allows paddings in the end. Removing paddings needs re-organizing the Q\n // tensor to [numTokensQ, numGroupedHeads, numHeads, headDimQ] and we might want to revisit\n // this in the future.\n numTokensPerCtaQ = static_cast<int32_t>(numTokensPerCtaQ / numGroupedHeads);\n } else {\n numGroupedHeads = tileSizeQ;\n numTokensPerCtaQ = 1;\n }\n tileShapes = std::vector<uint32_t>{static_cast<uint32_t>(numEltsInClampedHeadDimQ),\n static_cast<uint32_t>(numGroupedHeads), 1,\n static_cast<uint32_t>(numTokensPerCtaQ)};\n }\n\n return std::make_tuple(shape, stride, tileShapes, numTokensPerCtaQ);\n }\n\n // Create the TMA shape/stride for O.\n template <class FmhaOptions>\n static auto makeTmaShapeStrideO(FmhaOptions const& options) {\n //\n // TODO: refactor this as makeTmaShapeStrideQ when removing cutlass tma copy.\n //\n\n // The number of tokens.\n int32_t numTokens{options.mSumOfSeqLensQ};\n\n // The number of heads per K/V head.\n int32_t numHeadsQPerKv{options.mNumHeadsQPerKv};\n\n // The batch dimension.\n int32_t batchSize{1};\n\n // The cute tensor shape for Q/O: (numTokens, headDim, ((numHeadsKv, numHeadsQPerKv),\n // batchSize)). This maps to flattened TMA shape for Q/O: (headDim, numTokens, numHeadsKv.\n // numHeadsQPerKv, batchSize). Note that TMA descriptor expects the first dimension's stride to\n // be 1, so swap the first two dimension so that the headDim dimension comes first.\n auto shape = std::vector<uint64_t>{\n static_cast<uint64_t>(options.mHeadDimV), static_cast<uint64_t>(numTokens),\n static_cast<uint64_t>(options.mNumHeadsKv), static_cast<uint64_t>(numHeadsQPerKv),\n static_cast<uint64_t>(batchSize)};\n\n // The hidden dimension.\n int32_t const hiddenDimO{options.mNumHeadsQ * options.mHeadDimV};\n\n // The stride between tokens.\n int32_t strideTokens{hiddenDimO};\n\n // The stride between Q heads.\n int32_t strideHeadsQ{options.mNumHeadsKv * options.mHeadDimV};\n\n // The stride between sequences.\n int32_t strideBatch{0};\n\n // The stride in between K/V heads.\n int32_t strideHeadsKv{options.mHeadDimV};\n // Assemble the stride (strideTokens, 1, ((strideHeadsKv, strideHeadsQ), strideBatch)).\n // Swap the first two dimension as mentioned before.\n auto stride = std::vector<uint64_t>{\n 1, static_cast<uint64_t>(strideTokens), static_cast<uint64_t>(strideHeadsKv),\n static_cast<uint64_t>(strideHeadsQ), static_cast<uint64_t>(strideBatch)};\n\n return std::make_tuple(shape, stride);\n }\n\n // Create the shape for K and V.\n template <class FmhaOptions>\n static auto makeShapeKv(FmhaOptions const& options, KernelParams const& params) {\n // The number of keys/vals. WARNING: The if/else-if are sorted by priority.\n int32_t numKeysVals{options.mMaxSeqLenKv};\n if (isPagedKv(options.mQkvLayout)) {\n numKeysVals = options.mNumTokensPerPage;\n } else if (isContiguousKv(options.mQkvLayout)) {\n numKeysVals = options.mMaxSeqLenCacheKv;\n } else {\n numKeysVals = options.mSumOfSeqLensKv;\n }\n\n // The number of heads per K/V head (packed in the sequence length for mGroupsHeadsQ).\n int32_t numHeadsKv{options.mNumHeadsKv};\n\n // The batch dimension. WARNING: The if/else-if are sorted by priority.\n int32_t batchSize{options.mBatchSize};\n if (isPagedKv(options.mQkvLayout)) {\n batchSize = params.mNumPagesInMemPool;\n } else if (isContiguousKv(options.mQkvLayout)) {\n batchSize = options.mBatchSize;\n } else {\n batchSize = 1;\n }\n\n // Return the number of keys and batch.\n return std::make_tuple(numKeysVals, numHeadsKv, batchSize);\n }\n\n // Compute the strides for K and V.\n template <class FmhaOptions>\n static auto makeStrideKv(FmhaOptions const& options, bool isK) {\n int strideKeysVals = 0;\n int strideHeads = 0;\n int strideBatch = 0;\n\n if (isK) {\n strideKeysVals = options.kStrideKeysValues;\n strideHeads = options.kStrideHeads;\n strideBatch = options.kStrideBatch;\n } else {\n strideKeysVals = options.vStrideKeysValues;\n strideHeads = options.vStrideHeads;\n strideBatch = options.vStrideBatch;\n }\n\n // Ragged layout has no batch stride; reset negative overflow to 0 for TMA descriptor.\n if (!isPagedKv(options.mQkvLayout) && !isContiguousKv(options.mQkvLayout) && strideBatch < 0) {\n strideBatch = 0;\n }\n\n // The 3 strides (the other ones are 1 and 0).\n return std::make_tuple(strideKeysVals, strideHeads, strideBatch);\n }\n\n // Create the TMA shape/stride for K.\n template <class FmhaOptions>\n static auto makeTmaShapeStrideKv(FmhaOptions const& options, KernelParams const& params,\n Data_type dtypeKv, bool isK) {\n // The shape elements.\n auto [numKeys, numHeadsQPerKv, batchSize] = makeShapeKv(options, params);\n // The stride elements.\n auto [strideKeys, strideHeads, strideBatch] = makeStrideKv(options, isK);\n\n // The headDim.\n // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv.\n int32_t headDim = isK ? options.mHeadDimQk : options.mHeadDimV;\n if (isPagedKv(options.mQkvLayout) || isContiguousKv(options.mQkvLayout)) {\n headDim = std::max(options.mHeadDimQk, options.mHeadDimV);\n }\n\n // For K, the cute layout: (numKeys, headDim, ((numHeadsQPerKv, numHeadsKv),\n // batchSize)):(strideKeys, _1, _0, strideHeads, strideBatch). Cute swaps the first two\n // dimension (to make sure stride of first dimension is 1) and ignores the numHeadsQPerKv\n // dimension (it's stride is always 0). For V, the headDim dimension is already the first\n // dimension so no swapping is needed.\n\n // Therefore, the resulting TMA layout is 4D: (headDim, numKeys, numHeadsKv, batchSize):(1,\n // strideKeys, strideHeads, strideBatch)\n\n // Note that for FP4 KV input, elements are stored as uint8_t, each packs 2 FP4 elements.\n // The column index and strides needs to divide by 2.\n auto const colIdxDivisor = dtypeKv == DATA_TYPE_E2M1 ? 2 : 1;\n auto shape = std::vector<uint64_t>{\n static_cast<uint64_t>(headDim / colIdxDivisor), static_cast<uint64_t>(numKeys),\n static_cast<uint64_t>(options.mNumHeadsKv), static_cast<uint64_t>(batchSize)};\n auto stride = std::vector<uint64_t>{1, static_cast<uint64_t>(strideKeys / colIdxDivisor),\n static_cast<uint64_t>(strideHeads / colIdxDivisor),\n static_cast<uint64_t>(strideBatch / colIdxDivisor)};\n\n return std::make_tuple(shape, stride);\n }\n\n // Create the TMA shape/stride for KV scaling factors.\n template <class FmhaOptions>\n static auto makeTmaShapeStrideKvSf(FmhaOptions const& options, KernelParams const& params,\n bool isK) {\n // The shape elements.\n auto [numKeys, numHeadsQPerKv, batchSize] = makeShapeKv(options, params);\n // The stride elements.\n auto [strideKeys, strideHeads, strideBatch] = makeStrideKv(options, isK);\n\n // The headDim.\n // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv.\n int32_t headDim = isK ? options.mHeadDimQk : options.mHeadDimV;\n if (isPagedKv(options.mQkvLayout) || isContiguousKv(options.mQkvLayout)) {\n headDim = std::max(options.mHeadDimQk, options.mHeadDimV);\n }\n // The number of elements per SF.\n int32_t NumEltsPerSf = 16;\n\n // The KV shape is: (headDim, numKeys, numHeadsKv, batchSize)\n // Therefore, the KV SF shape should be (headDim / NumEltsPerSf, numKeys, numHeadsKv,\n // batchSize). Considering the TMA requires box width to be multiple of 16B, without changing\n // the underlying layout, we reshape into (16, numKeys * headDim / NumEltsPerSf / 16,\n // numHeadsKv, batchSize)\n\n // Note that it only works for pagedKv layout.\n FLASHINFER_CHECK(isPagedKv(options.mQkvLayout), \"The qkvLayout is not supported.\");\n\n auto shape = std::vector<uint64_t>{\n 16, static_cast<uint64_t>(numKeys * headDim / NumEltsPerSf / 16),\n static_cast<uint64_t>(options.mNumHeadsKv), static_cast<uint64_t>(batchSize)};\n auto stride = std::vector<uint64_t>{1, 16, static_cast<uint64_t>(strideHeads / NumEltsPerSf),\n static_cast<uint64_t>(strideBatch / NumEltsPerSf)};\n\n return std::make_tuple(shape, stride);\n }\n\n // Prepare pointers for TMA descriptors.\n static std::tuple<void const*, void const*, void const*> getDevicePtrs(\n TllmGenFmhaRunnerParams const& runnerParams, int32_t bytesPerElt) {\n // Declare the q, k, v ptrs.\n void const *qPtr{runnerParams.qPtr}, *kPtr{runnerParams.kPtr}, *vPtr{runnerParams.vPtr};\n\n // Set Q, K and V pointer from packed QKV tensor.\n if (isPackedQkv(runnerParams.mQkvLayout)) {\n qPtr = runnerParams.qkvPtr;\n kPtr = reinterpret_cast<void const*>(reinterpret_cast<char const*>(runnerParams.qkvPtr) +\n runnerParams.mNumHeadsQ * runnerParams.mHeadDimQk *\n bytesPerElt);\n vPtr = reinterpret_cast<void const*>(reinterpret_cast<char const*>(runnerParams.qkvPtr) +\n (runnerParams.mNumHeadsQ + runnerParams.mNumHeadsKv) *\n runnerParams.mHeadDimQk * bytesPerElt);\n }\n // Set K and V pointer from pagedKv tensor.\n else if (isPagedKv(runnerParams.mQkvLayout)) {\n // Note that the offsets will be fully handled by the pageIdx buffer.\n kPtr = runnerParams.kPtr;\n vPtr = runnerParams.vPtr;\n }\n // Set K and V pointer from contiguousQAnddKv tensor.\n else if (isContiguousKv(runnerParams.mQkvLayout)) {\n kPtr = runnerParams.kvPtr;\n // The maximum headDim of K and V.\n // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv.\n int32_t const maxHeadDimKv{std::max(runnerParams.mHeadDimQk, runnerParams.mHeadDimV)};\n vPtr = reinterpret_cast<void const*>(\n reinterpret_cast<char const*>(runnerParams.kvPtr) +\n runnerParams.mNumHeadsKv * runnerParams.mMaxSeqLenCacheKv * maxHeadDimKv * bytesPerElt);\n }\n\n // Return the pointers.\n return std::make_tuple(qPtr, kPtr, vPtr);\n }\n\n // Build tma descriptors.\n template <class FmhaOptions>\n static CUtensorMap buildNdTmaDescriptor(FmhaOptions const& options, Data_type dtypeElt,\n std::vector<uint64_t> const& shapes,\n std::vector<uint64_t> const& strides,\n std::vector<uint32_t> const& tileShapes, void* gmemAddr,\n bool swizzled = true) {\n CUtensorMap desc{};\n // The data type.\n CUtensorMapDataType tmaDataFormat;\n if (dtypeElt == DATA_TYPE_E2M1 || dtypeElt == DATA_TYPE_E4M3) {\n tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_UINT8;\n } else if (dtypeElt == DATA_TYPE_FP16) {\n tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_FLOAT16;\n } else if (dtypeElt == DATA_TYPE_BF16) {\n tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_BFLOAT16;\n } else {\n FLASHINFER_CHECK(false, \"Unexpected dtype %d\", static_cast<int32_t>(dtypeElt));\n }\n\n // The swizzle type.\n CUtensorMapSwizzle swizzleType;\n int32_t numBytesInLeadingDim = tileShapes[0] * get_size_in_bits(dtypeElt) / 8 /*bits*/;\n if (!swizzled) {\n swizzleType = CU_TENSOR_MAP_SWIZZLE_NONE;\n } else if ((numBytesInLeadingDim % 128) == 0) {\n swizzleType = CU_TENSOR_MAP_SWIZZLE_128B;\n } else if ((numBytesInLeadingDim % 64) == 0) {\n swizzleType = CU_TENSOR_MAP_SWIZZLE_64B;\n } else if ((numBytesInLeadingDim % 32) == 0) {\n swizzleType = CU_TENSOR_MAP_SWIZZLE_32B;\n } else {\n FLASHINFER_CHECK(false, \"Unexpected numBytesInLeadingDim %d\", numBytesInLeadingDim);\n }\n\n // Check gmem address must be 16B-aligned\n FLASHINFER_CHECK((reinterpret_cast<uint64_t>(gmemAddr) & 0b1111) == 0);\n\n // Check shape must be in range [1, 2^32]\n int32_t dim = shapes.size();\n // Max five dimension and min 2 dimension.\n FLASHINFER_CHECK((dim <= 5) && (dim >= 2));\n // Check shape range.\n for (int32_t ii = 0; ii < dim; ++ii) {\n FLASHINFER_CHECK(shapes[ii] >= (uint64_t(1))); // Size must be min 1\n FLASHINFER_CHECK(shapes[ii] <= (uint64_t(1) << 32)); // Size must be max 2^32\n }\n\n // TMA descriptor does not store the zeroth stride and assumes it is 1.\n FLASHINFER_CHECK(static_cast<int32_t>(strides.size()) == dim);\n FLASHINFER_CHECK(strides[0] == 1);\n\n // Build strides in bytes.\n // cuTensorMapEncodeTiled ignores the stride of the first dimension (implicitly 1).\n std::vector<uint64_t> stridesInBytes(dim - 1);\n for (int32_t ii = 0; ii < dim - 1; ++ii) {\n stridesInBytes[ii] = strides[ii + 1] *\n std::max(get_size_in_bits(dtypeElt), static_cast<size_t>(8)) / 8 /*bit*/;\n }\n\n // Set tile strides to 0;\n std::vector<uint32_t> tileStrides(dim, 1);\n\n // Build the descriptor.\n CUresult result =\n cuTensorMapEncodeTiled(&desc, tmaDataFormat,\n /*tensorRank=*/dim, gmemAddr, shapes.data(), stridesInBytes.data(),\n tileShapes.data(), tileStrides.data(),\n /*interleave=*/CU_TENSOR_MAP_INTERLEAVE_NONE, swizzleType,\n /*l2Promotion=*/CU_TENSOR_MAP_L2_PROMOTION_L2_128B,\n /*oobFill=*/CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE);\n\n if (result != CUDA_SUCCESS) {\n char const* err_str;\n cuGetErrorString(result, &err_str);\n // Note that the error is thrown out before launching fmha kernels, so it is highly possible\n // that the errors are broadcasted by previous kernels. Please enable CUDA_LAUNCH_BLOCKING or\n // use cuda-gdb for more details.\n std::cerr << \"Error: Failed to initialize the TMA descriptor due to \" << err_str << std::endl;\n std::cerr << \"tmaFormat: \" << static_cast<int>(tmaDataFormat) << \" dim: \" << dim\n << \" gmem: \" << gmemAddr << std::endl;\n std::cerr << \"Shape: \" << shapes[0] << \" \" << shapes[1] << \" \" << shapes[2] << \" \"\n << shapes[3] << \" \" << shapes[4] << std::endl;\n std::cerr << \"Stride: \" << stridesInBytes[0] << \" \" << stridesInBytes[1] << \" \"\n << stridesInBytes[2] << \" \" << stridesInBytes[3] << std::endl;\n std::cerr << \"tileShapes: \" << tileShapes[0] << \" \" << tileShapes[1] << \" \" << tileShapes[2]\n << \" \" << tileShapes[3] << \" \" << tileShapes[4] << std::endl;\n std::cerr << \"tileStrides: \" << tileStrides[0] << \" \" << tileStrides[1] << \" \"\n << tileStrides[2] << \" \" << tileStrides[3] << \" \" << tileStrides[4] << std::endl;\n std::cerr << \"swizzleType: \" << int(swizzleType) << std::endl;\n FLASHINFER_CHECK(false);\n }\n\n return desc;\n }\n\n // Setup the kernel parameters.\n template <class FmhaOptions_, class KernelMeta>\n static KernelParams setKernelParams(FmhaOptions_ const& options, KernelMeta const& kernelMeta,\n int32_t maxNumCtasQ, int32_t maxNumCtasKv) {\n // Create the return struct.\n KernelParams params;\n // Memset the kernel parameters to 0.\n memset(¶ms, 0, sizeof(KernelParams));\n\n // Get the device pointers for TMA descriptors.\n auto [qPtr, kPtr, vPtr] = getDevicePtrs(options, get_size_in_bytes(kernelMeta.mDataTypeKv));\n\n // The maximum headDim of K and V.\n // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv.\n int32_t const maxHeadDimKv{std::max(options.mHeadDimQk, options.mHeadDimV)};\n\n // Set the number of pages in the memory pool for paged K/V cache.\n if (isPagedKv(options.mQkvLayout)) {\n params.mNumPagesInMemPool = options.mNumPagesInMemPool == 0\n ? options.mMaxNumPagesPerSeqKv * 2 * options.mBatchSize\n : options.mNumPagesInMemPool;\n }\n\n // The number of elements in 128B for Q.\n int32_t numEltsIn128BQ = (128 * 8) / get_size_in_bits(kernelMeta.mDataTypeQ);\n // The number of head elts (per token) in each block of shared memory.\n int32_t numEltsInClampedHeadDimQ = std::min(numEltsIn128BQ, options.mHeadDimQk);\n\n // Shape/stride for gmem tensor Q.\n auto [shapeQ, strideQ, tileShapeQ, numTokensPerCtaQ] =\n makeTmaShapeStrideQ(options, kernelMeta.mGroupsHeadsQ, kernelMeta.mGroupsTokensHeadsQ,\n kernelMeta.mTileSizeQ, numEltsInClampedHeadDimQ);\n // Build tma descriptor for Q.\n params.tmaQ_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeQ, shapeQ, strideQ, tileShapeQ,\n const_cast<void*>(qPtr));\n\n // The number of keys per tile.\n int32_t numKeysPerTile = isPagedKv(options.mQkvLayout)\n ? std::min(options.mNumTokensPerPage, kernelMeta.mTileSizeKv)\n : kernelMeta.mTileSizeKv;\n // The number of elements in 128B for Q.\n int32_t numEltsIn128BKv = (128 * 8) / get_size_in_bits(kernelMeta.mDataTypeKv);\n // The number of head elts (per token) in each block of shared memory (see above explanation).\n int32_t numEltsInClampedHeadDimKv = std::min(numEltsIn128BKv, maxHeadDimKv);\n\n // Shape/stride for gmem tensor Kv.\n auto [shapeK, strideK] =\n makeTmaShapeStrideKv(options, params, kernelMeta.mDataTypeKv, /*isK*/ true);\n auto [shapeV, strideV] =\n makeTmaShapeStrideKv(options, params, kernelMeta.mDataTypeKv, /*isK*/ false);\n // Build tma descriptor for K.\n // Do we have to transform K/V before MMA?\n bool const transformsKv{kernelMeta.mDataTypeKv != kernelMeta.mDataTypeQ};\n // Note that for FP4 KV input, elements are stored as uint8_t, each packs 2 FP4 elements.\n auto const numEltsDivisor = kernelMeta.mDataTypeKv == DATA_TYPE_E2M1 ? 2 : 1;\n // The tileShapes for K/V.\n std::vector<uint32_t> tileShapeKv(shapeK.size(), 1);\n tileShapeKv[0] = numEltsInClampedHeadDimKv / numEltsDivisor;\n tileShapeKv[1] = numKeysPerTile;\n\n // If sparse MLA is enabled, the shape and stride for K need to be updated for 2D layout\n // (numTokensKvInPagedKv, headDimQk).\n if (options.mSparseMla) {\n shapeK = std::vector<uint64_t>{static_cast<uint64_t>(options.mHeadDimQk),\n static_cast<uint64_t>(INT_MAX)};\n strideK = std::vector<uint64_t>{1, static_cast<uint64_t>(options.mHeadDimQk)};\n tileShapeKv[1] = 1;\n }\n\n // Build tma descriptor for K.\n params.tmaK_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeKv, shapeK, strideK,\n tileShapeKv, const_cast<void*>(kPtr),\n /*swizzled = */ !transformsKv);\n // Build tma descriptor for V.\n params.tmaV_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeKv, shapeV, strideV,\n tileShapeKv, const_cast<void*>(vPtr),\n /*swizzled = */ !transformsKv);\n\n // If the KV dtype is E2m1, additional scaling factors are needed for dequant.\n if (kernelMeta.mDataTypeKv == DATA_TYPE_E2M1) {\n // The number of elements per SF.\n int32_t NumEltsPerSf = 16;\n // Compute the shape and stride for SF tensor.\n // FIXME: assume K and V uses the same shape.\n auto [shapeKvSf, strideKvSf] = makeTmaShapeStrideKvSf(options, params, /*isK*/ true);\n\n // The tileShapes for K/V.\n std::vector<uint32_t> tileShapeKvSf(shapeKvSf.size(), 1);\n tileShapeKvSf[0] = 16;\n tileShapeKvSf[1] = numKeysPerTile * maxHeadDimKv / NumEltsPerSf / 16;\n\n // The tile box is reshaped from (headDim / NumEltsPerSf, tileSizeKv) into (16, tileSizeKv *\n // headDim / NumEltsPerSf / 16). See makeTmaShapeStrideKvSf for details. Build tma descriptor\n // for K SF.\n params.tmaKSf_ = buildNdTmaDescriptor(options, DATA_TYPE_E4M3, shapeKvSf, strideKvSf,\n tileShapeKvSf, const_cast<void*>(options.kSfBasePtr),\n /*swizzled = */ false);\n\n // Build tma descriptor for V SF.\n params.tmaVSf_ = buildNdTmaDescriptor(options, DATA_TYPE_E4M3, shapeKvSf, strideKvSf,\n tileShapeKvSf, const_cast<void*>(options.vSfBasePtr),\n /*swizzled = */ false);\n }\n\n // Shape/stride for gmem tensor O.\n auto [shapeO, strideO] = makeTmaShapeStrideO(options);\n // The tileShapes for O.\n std::vector<uint32_t> tileShapeO(shapeO.size(), 1);\n tileShapeO[0] = numEltsInClampedHeadDimQ;\n tileShapeO[1] = kernelMeta.mTileSizeQ;\n // Build tma descriptor for O.\n params.tmaO_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeQ, shapeO, strideO, tileShapeO,\n const_cast<void*>(options.oPtr));\n\n // Set the other kernel parameters.\n params.ptrCumSeqLensQ = options.cumSeqLensQPtr;\n params.ptrCumSeqLensKv = options.cumSeqLensKvPtr;\n\n // The packed custom mask.\n params.ptrCustomMask = options.customMaskPtr;\n // The packed custom mask's offsets of each sequence.\n params.ptrCustomMaskOffsets = options.customMaskOffsetsPtr;\n // The first sparseMask offsets in the Kv sequence dimension.\n params.ptrFirstSparseMaskOffsetsKv = options.firstSparseMaskOffsetsKvPtr;\n\n // The output buffer.\n params.ptrO = options.oPtr;\n // The output scaling factor buffer.\n params.ptrSfO = options.oSfPtr;\n\n // TRT-LLM restrictions: the quantization scales must be on the device.\n params.ptrOutputScale = options.outputScalePtr;\n\n // The sequence lengths for Kv.\n params.ptrSeqLensKv = options.seqLensKvPtr;\n\n // Attention sink\n params.ptrAttentionSinks = options.ptrAttentionSinks;\n\n // The partial buffers' pointers when the multiCtasKv mode is enabled.\n int64_t partialStatsBufferSize = options.mMultiProcessorCount * kernelMeta.mStepQ;\n params.ptrMultiCtasKvCounter = options.multiCtasKvCounterPtr;\n params.ptrPartialStats = reinterpret_cast<float2*>(options.multiCtasKvScratchPtr);\n params.ptrPartialO = params.ptrPartialStats + partialStatsBufferSize;\n\n params.ptrPageIdxKv = options.kvPageIdxPtr;\n params.ptrScaleSoftmaxLog2 = options.scaleSoftmaxLog2Ptr;\n\n params.ptrScaleSfKv = options.kvSfScalePtr;\n params.ptrScaleSfO = options.oSfScalePtr;\n params.mScaleSfO = options.mScaleSfO;\n\n params.mAttentionWindowSize = options.mAttentionWindowSize;\n if (isSlidingOrChunkedCausalMask(\n static_cast<TrtllmGenAttentionMaskType>(kernelMeta.mMaskType)) &&\n options.mChunkedAttentionSize != INT_MAX) {\n FLASHINFER_CHECK((options.mChunkedAttentionSize & (options.mChunkedAttentionSize - 1)) == 0,\n \"Chunked attention size must be a power of 2\");\n params.mChunkedAttentionSizeLog2 = std::log2(options.mChunkedAttentionSize);\n } else {\n // Default 0 means that chunked attention is disabled.\n params.mChunkedAttentionSizeLog2 = 0;\n }\n\n // Compute the log of numTokensPerPage\n int32_t numTokensPerPageLog2{-1};\n if (isPagedKv(options.mQkvLayout)) {\n FLASHINFER_CHECK((options.mNumTokensPerPage & (options.mNumTokensPerPage - 1)) == 0,\n \"NumTokensPerPage must be power of 2\");\n numTokensPerPageLog2 = (int)log2f((float)options.mNumTokensPerPage);\n }\n params.mNumTokensPerPageLog2 = numTokensPerPageLog2;\n\n params.mMaxSeqLenQ = options.mMaxSeqLenQ;\n params.mMaxSeqLenKv = options.mMaxSeqLenKv;\n params.mMaxNumCtasQ = maxNumCtasQ;\n params.mMaxNumCtasKv = maxNumCtasKv;\n params.mMaxNumPagesPerSeqKv = options.mMaxNumPagesPerSeqKv;\n // TODO: just use mMaxSeqLenQ for number of MTP tokens.\n params.mSumOfSeqLensQ = options.mSumOfSeqLensQ;\n params.mSumOfSeqLensKv = options.mSumOfSeqLensKv;\n params.mBatchSize = options.mBatchSize;\n params.mChunkedAttentionSizeLog2 = 0;\n params.mNumHeadsQ = options.mNumHeadsQ;\n params.mNumHeadsKv = options.mNumHeadsKv;\n params.mNumHeadsQPerKv = options.mNumHeadsQPerKv;\n params.mNumHeadsQPerKvDivisor = FastModDivInt32(options.mNumHeadsQPerKv);\n params.mNumHiddenEltsO = options.mNumHeadsQ * options.mHeadDimQk;\n params.mNumTokensPerCtaQ = numTokensPerCtaQ;\n params.mOutputScale = options.outputScale;\n params.mScaleSoftmaxLog2 = options.scaleSoftmaxLog2;\n params.mStartTokenIdxSfO = options.mSfStartTokenIdx;\n params.mScaleSfKv = options.mScaleSfKv;\n params.ptrSoftmaxStats = options.softmaxStatsPtr;\n // The sparseMlaTopK needs to be a multiple of 4 as we use 16B cpAsync instructions for the\n // indices.\n FLASHINFER_CHECK(!options.mSparseMla || (options.mSparseMlaTopK % 4) == 0,\n \"SparseMlaTopK must be a multiple of 4\");\n params.mSparseMlaTopK = options.mSparseMlaTopK;\n // TODO: Integrate trtllm block-sparse attention kernels when needed.\n params.mUseBlockSparseAttention = false;\n return params;\n }\n};\n"},"diff":{"kind":"string","value":"--- include/flashinfer/trtllm/fmha/kernelParams.h\n+++ include/flashinfer/trtllm/fmha/kernelParams.h\n@@ -30,6 +30,36 @@\n #include \"../../utils.cuh\"\n #include \"../common.h\"\n #include \"fmhaRunnerParams.h\"\n+\n+////////////////////////////////////////////////////////////////////////////////////////////////////\n+\n+//\n+// CCCL >= 3.1.0 (CUDA CTK 13.1) introduces the fast_mod_div math operations.\n+// The following code makes sure that the host initialization works with older CUDA CTK versions.\n+//\n+\n+// Refer to\n+// https://github.com/NVIDIA/cccl/blob/main/libcudacxx/include/cuda/__cmath/fast_modulo_division.h#L76-L81\n+// about how to compute the fast modulo division.\n+struct FastModDivInt32 {\n+ public:\n+ FastModDivInt32(int32_t divisor) : mDivisor(divisor) {\n+ mShift = std::max(ceilLog2(mDivisor) - 1, 0);\n+ mMultiplier = static_cast<uint32_t>(\n+ flashinfer::ceil_div(uint64_t(1) << (32 + mShift), static_cast<uint64_t>(mDivisor)));\n+ }\n+\n+ private:\n+ int32_t ceilLog2(int32_t value) const {\n+ return static_cast<int32_t>(std::ceil(std::log2(value)));\n+ }\n+\n+ private:\n+ int32_t mDivisor = 1;\n+ uint32_t mMultiplier = 0;\n+ uint32_t mAdd = 0;\n+ int32_t mShift = 0;\n+};\n \n ////////////////////////////////////////////////////////////////////////////////////////////////////\n using Dtype = Data_type;\n@@ -115,6 +145,9 @@\n int32_t mBatchSize;\n // The chunked attention size in log2.\n int32_t mChunkedAttentionSizeLog2;\n+ // The factor to add to the maximum value to increase the probability\n+ // of skip correction during next iterations.\n+ float mInflateMax;\n // The log of the Sage Attention block size for K.\n int32_t mLogNumEltsPerSageAttnBlkK;\n // The log of the Sage Attention block size for P.\n@@ -137,10 +170,14 @@\n int32_t mNumHeadsQ;\n // The number of Q heads per K/V head (i.e. mNumHeadsQ / mNumHeadsKv).\n int32_t mNumHeadsQPerKv;\n+ // The number of headsQ per K/V head as a fast_mod_div divisor.\n+ FastModDivInt32 mNumHeadsQPerKvDivisor{1};\n // The hidden size of O.\n int64_t mNumHiddenEltsO;\n // The total number of pages in the paged-kv memory pool.\n int32_t mNumPagesInMemPool;\n+ // The number of tokensQ per CTA (used for groupsHeadsTokensQ generation kernel).\n+ int32_t mNumTokensPerCtaQ;\n // The number of tokens per page (used if dynamic numTokensPerPage is enabled).\n int32_t mNumTokensPerPageLog2;\n // The output scale for FP8 quantization.\n@@ -165,7 +202,8 @@\n \n // Create the TMA shape/stride for Q.\n template <class FmhaOptions>\n- static auto makeTmaShapeStrideQ(FmhaOptions const& options, bool groupsHeadsQ, int32_t tileSizeQ,\n+ static auto makeTmaShapeStrideQ(FmhaOptions const& options, bool groupsHeadsQ,\n+ bool groupsTokensHeadsQ, int32_t tileSizeQ,\n int32_t numEltsInClampedHeadDimQ) {\n //\n // The Q has shape of [numTokens * numHeadsQPerKv, numHeadsKv * 1, headDim]\n@@ -236,19 +274,26 @@\n // The tile shape for TMA.\n auto tileShapes = std::vector<uint32_t>{static_cast<uint32_t>(numEltsInClampedHeadDimQ), 1, 1,\n static_cast<uint32_t>(tileSizeQ)};\n+ // The number of tokensQ per CTA.\n+ int32_t numTokensPerCtaQ{tileSizeQ};\n+ // Re-compute the number of tokensQ per CTA if groupsHeadsQ is enabled.\n if (groupsHeadsQ) {\n- if (isSpecDecodingGenerationKernel(options.mKernelType)) {\n- FLASHINFER_CHECK((tileSizeQ % numGroupedHeads == 0), \"internal error\");\n- tileShapes = std::vector<uint32_t>{static_cast<uint32_t>(numEltsInClampedHeadDimQ),\n- static_cast<uint32_t>(numGroupedHeads), 1,\n- static_cast<uint32_t>(tileSizeQ / numGroupedHeads)};\n+ if (groupsTokensHeadsQ) {\n+ // Currently, it requires each CTA to process complete headsQ (i.e. numGroupedHeads) at a\n+ // time, so it allows paddings in the end. Removing paddings needs re-organizing the Q\n+ // tensor to [numTokensQ, numGroupedHeads, numHeads, headDimQ] and we might want to revisit\n+ // this in the future.\n+ numTokensPerCtaQ = static_cast<int32_t>(numTokensPerCtaQ / numGroupedHeads);\n } else {\n- tileShapes = std::vector<uint32_t>{static_cast<uint32_t>(numEltsInClampedHeadDimQ),\n- static_cast<uint32_t>(tileSizeQ), 1, 1};\n+ numGroupedHeads = tileSizeQ;\n+ numTokensPerCtaQ = 1;\n }\n- }\n-\n- return std::make_tuple(shape, stride, tileShapes);\n+ tileShapes = std::vector<uint32_t>{static_cast<uint32_t>(numEltsInClampedHeadDimQ),\n+ static_cast<uint32_t>(numGroupedHeads), 1,\n+ static_cast<uint32_t>(numTokensPerCtaQ)};\n+ }\n+\n+ return std::make_tuple(shape, stride, tileShapes, numTokensPerCtaQ);\n }\n \n // Create the TMA shape/stride for O.\n@@ -541,6 +586,9 @@\n if (result != CUDA_SUCCESS) {\n char const* err_str;\n cuGetErrorString(result, &err_str);\n+ // Note that the error is thrown out before launching fmha kernels, so it is highly possible\n+ // that the errors are broadcasted by previous kernels. Please enable CUDA_LAUNCH_BLOCKING or\n+ // use cuda-gdb for more details.\n std::cerr << \"Error: Failed to initialize the TMA descriptor due to \" << err_str << std::endl;\n std::cerr << \"tmaFormat: \" << static_cast<int>(tmaDataFormat) << \" dim: \" << dim\n << \" gmem: \" << gmemAddr << std::endl;\n@@ -588,8 +636,9 @@\n int32_t numEltsInClampedHeadDimQ = std::min(numEltsIn128BQ, options.mHeadDimQk);\n \n // Shape/stride for gmem tensor Q.\n- auto [shapeQ, strideQ, tileShapeQ] = makeTmaShapeStrideQ(\n- options, kernelMeta.mGroupsHeadsQ, kernelMeta.mTileSizeQ, numEltsInClampedHeadDimQ);\n+ auto [shapeQ, strideQ, tileShapeQ, numTokensPerCtaQ] =\n+ makeTmaShapeStrideQ(options, kernelMeta.mGroupsHeadsQ, kernelMeta.mGroupsTokensHeadsQ,\n+ kernelMeta.mTileSizeQ, numEltsInClampedHeadDimQ);\n // Build tma descriptor for Q.\n params.tmaQ_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeQ, shapeQ, strideQ, tileShapeQ,\n const_cast<void*>(qPtr));\n@@ -744,7 +793,9 @@\n params.mNumHeadsQ = options.mNumHeadsQ;\n params.mNumHeadsKv = options.mNumHeadsKv;\n params.mNumHeadsQPerKv = options.mNumHeadsQPerKv;\n+ params.mNumHeadsQPerKvDivisor = FastModDivInt32(options.mNumHeadsQPerKv);\n params.mNumHiddenEltsO = options.mNumHeadsQ * options.mHeadDimQk;\n+ params.mNumTokensPerCtaQ = numTokensPerCtaQ;\n params.mOutputScale = options.outputScale;\n params.mScaleSoftmaxLog2 = options.scaleSoftmaxLog2;\n params.mStartTokenIdxSfO = options.mSfStartTokenIdx;"},"lines_added":{"kind":"number","value":64,"string":"64"},"lines_removed":{"kind":"number","value":13,"string":"13"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":["qwen","gpt-oss"],"string":"[\n \"qwen\",\n \"gpt-oss\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/fmha/kernelParams.h).\n\nGoal: [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding\nTarget hardware: unspecified\nTarget models: qwen, gpt-oss\n\nCurrent file:\n```cpp\n/***************************************************************************************************\n * Copyright (c) 2011-2024, NVIDIA CORPORATION. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without modification, are not permit-\n * ted.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND\n * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n **************************************************************************************************/\n#pragma once\n\n#ifdef _WIN32\n#define _USE_MATH_DEFINES\n#include <math.h>\n#endif\n\n#include <cutlass/cutlass.h>\n\n#include <cmath>\n#include <cstdint>\n#include <cute/tensor.hpp>\n\n#include \"../../utils.cuh\"\n#include \"../common.h\"\n#include \"fmhaRunnerParams.h\"\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\nusing Dtype = Data_type;\n\nstruct KernelParams {\n // TMA descriptor for Q.\n CUtensorMap tmaQ_;\n // TMA descriptor for K.\n CUtensorMap tmaK_;\n // TMA descriptor for V.\n CUtensorMap tmaV_;\n // The descriptor for O.\n CUtensorMap tmaO_;\n\n // For FP4 KV cache, additional scaling factors are needed.\n // TMA descriptor for K scaling factor.\n CUtensorMap tmaKSf_;\n // TMA descriptor for V scaling factor.\n CUtensorMap tmaVSf_;\n\n // grid dimensions, these might differ from actual grid the kernel is launched with\n // for persistent kernels on Hopper GPUs.\n int32_t logicalGridDimX, logicalGridDimY, logicalGridDimZ;\n\n // The output pointer (used by STG for last tile).\n void* ptrO;\n // The output SF pointer (used for FP4 output).\n void* ptrSfO;\n // The attention sinks pointer (additional value per head in the denominator of the softmax).\n float const* ptrAttentionSinks;\n\n // The cumulative sequence lengths for Q.\n int32_t const* ptrCumSeqLensQ;\n // The cumulative sequence lengths for K/V.\n int32_t const* ptrCumSeqLensKv;\n // The packed custom mask.\n uint32_t const* ptrCustomMask;\n // The packed custom mask's offsets of each sequence.\n int64_t const* ptrCustomMaskOffsets;\n // The debug output matrix O\n float* ptrDebugO;\n // The first sparseMask offsets in the Kv sequence dimension.\n int32_t const* ptrFirstSparseMaskOffsetsKv;\n // The counter for the multiCtasKv mode.\n int32_t* ptrMultiCtasKvCounter;\n // The device output scale for FP8 quantization. Only needed by trt-llm fp8 kernels as the sca-\n // les have to be on the device currently.\n float const* ptrOutputScale;\n // The page indexes of the paged-kv buffer with shape of [batchSize, 2, maxNumPagesPerSeq].\n int32_t const* ptrPageIdxKv;\n // The partial matrix O for each CtaKv when the multiCtasKv mode is enabled.\n void* ptrPartialO;\n // The partial softmax stats (max/sum)for each CtaKv when the multiCtasKv mode is enabled.\n float2* ptrPartialStats;\n // The scaling factors for K.\n float const* ptrSageAttnSfsK;\n // The scaling factors for P.\n float const* ptrSageAttnSfsP;\n // The scaling factors for Q.\n float const* ptrSageAttnSfsQ;\n // The scaling factors for V.\n float const* ptrSageAttnSfsV;\n // The device scaling factor for softmax (multiplied by log2 to use faster exp2). Only needed by\n // trt-llm fp8 kernels as the scales have to be on the device currently.\n float const* ptrScaleSoftmaxLog2;\n // The SF scale for Kv on device. Only needed by trt-llm kernels as the scales have to be on the\n // device currently.\n float const* ptrScaleSfKv;\n // The SF scale for O on device. Only needed by trt-llm kernels as the scales have to be on the\n // device currently.\n float const* ptrScaleSfO;\n // The sequence lengths for K/V. Required by pagedKv kernels to avoid unnecessary computation\n // based on (ptrCumSeqLensKv[batchIdx + 1] - ptrCumSeqLensKv[batchIdx]).\n int32_t const* ptrSeqLensKv;\n // The reserved memory buffer.\n int32_t* ptrReservedMem;\n // The softmax stats buffer.\n float2* ptrSoftmaxStats;\n\n // The attention window size for sliding window attention.\n int32_t mAttentionWindowSize;\n // The batch size\n int32_t mBatchSize;\n // The chunked attention size in log2.\n int32_t mChunkedAttentionSizeLog2;\n // The log of the Sage Attention block size for K.\n int32_t mLogNumEltsPerSageAttnBlkK;\n // The log of the Sage Attention block size for P.\n int32_t mLogNumEltsPerSageAttnBlkP;\n // The log of the Sage Attention block size for Q.\n int32_t mLogNumEltsPerSageAttnBlkQ;\n // The log of the Sage Attention block size for V.\n int32_t mLogNumEltsPerSageAttnBlkV;\n // The sequence lengths for Q and K/V.\n int32_t mMaxSeqLenQ, mMaxSeqLenKv;\n // The maximum number of CTAs for Q.\n int32_t mMaxNumCtasQ;\n // The maximum number of CTAs for K/V.\n int32_t mMaxNumCtasKv;\n // The maximum number of pages per sequence for paged-kv buffer.\n int32_t mMaxNumPagesPerSeqKv;\n // The number of heads for K/V.\n int32_t mNumHeadsKv;\n // The number of heads for Q.\n int32_t mNumHeadsQ;\n // The number of Q heads per K/V head (i.e. mNumHeadsQ / mNumHeadsKv).\n int32_t mNumHeadsQPerKv;\n // The hidden size of O.\n int64_t mNumHiddenEltsO;\n // The total number of pages in the paged-kv memory pool.\n int32_t mNumPagesInMemPool;\n // The number of tokens per page (used if dynamic numTokensPerPage is enabled).\n int32_t mNumTokensPerPageLog2;\n // The output scale for FP8 quantization.\n float mOutputScale;\n // The scaling factor for softmax (multiplied by log2 to use faster exp2).\n float mScaleSoftmaxLog2;\n // The SF scale for Kv.\n float mScaleSfKv;\n // The SF scale for O.\n float mScaleSfO;\n // The reserved parameter.\n float mReservedParam;\n // The start token index in SF tensor. Used for FP4 SF offset calculation in generation phase\n // kernel when inflight batching is enabled in TRT-LLM.\n int32_t mStartTokenIdxSfO;\n // The sum of sequence lengths for Q and K/V.\n int32_t mSumOfSeqLensQ, mSumOfSeqLensKv;\n // The sparseMla topK value.\n int32_t mSparseMlaTopK;\n // The flag to use block sparse attention.\n bool mUseBlockSparseAttention;\n\n // Create the TMA shape/stride for Q.\n template <class FmhaOptions>\n static auto makeTmaShapeStrideQ(FmhaOptions const& options, bool groupsHeadsQ, int32_t tileSizeQ,\n int32_t numEltsInClampedHeadDimQ) {\n //\n // The Q has shape of [numTokens * numHeadsQPerKv, numHeadsKv * 1, headDim]\n // when grouping headsQ, otherwise it would be [numTokens, numHeadsQPerKv * numHeadsKv,\n // headDim].\n\n // The number of grouped heads for the A matrix of MMA.\n int32_t numGroupedHeads{1};\n if (groupsHeadsQ) {\n numGroupedHeads = std::min(tileSizeQ, options.mNumHeadsQPerKv);\n }\n\n // The number of heads.\n int32_t numHeads{options.mNumHeadsQ};\n if (groupsHeadsQ) {\n numHeads /= numGroupedHeads;\n }\n // Make sure the math works.\n FLASHINFER_CHECK(numHeads * numGroupedHeads == options.mNumHeadsQ, \"internal error\");\n\n // The number of tokens.\n int32_t numTokens{options.mSumOfSeqLensQ};\n\n // This maps to flattened TMA shape for Q: (headDim, numTokens, numHeads).\n auto shape = std::vector<uint64_t>{\n static_cast<uint64_t>(options.mHeadDimQk), static_cast<uint64_t>(numGroupedHeads),\n static_cast<uint64_t>(numHeads), static_cast<uint64_t>(numTokens)};\n\n // The stride between tokens.\n // Use user-provided stride if available, otherwise compute from layout.\n int32_t strideTokens{options.qStrideTokens};\n if (strideTokens == 0) {\n // The hidden dimension when the tensor contains only Q (i.e. not QKV packed).\n int32_t const hiddenDimQ{options.mNumHeadsQ * options.mHeadDimQk};\n // The hidden dimension when the Q, K and V tensors are packed.\n int32_t hiddenDimQkv{hiddenDimQ};\n if (isPackedQkv(options.mQkvLayout)) {\n FLASHINFER_CHECK(!groupsHeadsQ, \"internal error\");\n hiddenDimQkv += options.mNumHeadsKv * (options.mHeadDimQk + options.mHeadDimV);\n }\n strideTokens = hiddenDimQkv;\n }\n\n // The stride between heads.\n // Use user-provided stride if available, otherwise compute from layout.\n int32_t strideHeads{options.qStrideHeads};\n if (strideHeads == 0) {\n strideHeads = options.mHeadDimQk;\n }\n // The stride between grouped heads (consecutive heads within a GQA group).\n // Use user-provided stride if available, otherwise use headDimQk.\n int32_t strideGroupedHeads{options.qStrideHeads};\n if (strideGroupedHeads == 0) {\n strideGroupedHeads = options.mHeadDimQk;\n }\n\n // For GQA, the TMA iterates over groups of heads, so we need to multiply by numGroupedHeads.\n if (groupsHeadsQ) {\n strideHeads = numGroupedHeads * strideHeads;\n }\n\n // Assemble the stride (1, strideTokens, strideHeads).\n // Swap the first two dimension as mentioned before.\n auto stride = std::vector<uint64_t>{1, static_cast<uint64_t>(strideGroupedHeads),\n static_cast<uint64_t>(strideHeads),\n static_cast<uint64_t>(strideTokens)};\n\n // The tile shape for TMA.\n auto tileShapes = std::vector<uint32_t>{static_cast<uint32_t>(numEltsInClampedHeadDimQ), 1, 1,\n static_cast<uint32_t>(tileSizeQ)};\n if (groupsHeadsQ) {\n if (isSpecDecodingGenerationKernel(options.mKernelType)) {\n FLASHINFER_CHECK((tileSizeQ % numGroupedHeads == 0), \"internal error\");\n tileShapes = std::vector<uint32_t>{static_cast<uint32_t>(numEltsInClampedHeadDimQ),\n static_cast<uint32_t>(numGroupedHeads), 1,\n static_cast<uint32_t>(tileSizeQ / numGroupedHeads)};\n } else {\n tileShapes = std::vector<uint32_t>{static_cast<uint32_t>(numEltsInClampedHeadDimQ),\n static_cast<uint32_t>(tileSizeQ), 1, 1};\n }\n }\n\n return std::make_tuple(shape, stride, tileShapes);\n }\n\n // Create the TMA shape/stride for O.\n template <class FmhaOptions>\n static auto makeTmaShapeStrideO(FmhaOptions const& options) {\n //\n // TODO: refactor this as makeTmaShapeStrideQ when removing cutlass tma copy.\n //\n\n // The number of tokens.\n int32_t numTokens{options.mSumOfSeqLensQ};\n\n // The number of heads per K/V head.\n int32_t numHeadsQPerKv{options.mNumHeadsQPerKv};\n\n // The batch dimension.\n int32_t batchSize{1};\n\n // The cute tensor shape for Q/O: (numTokens, headDim, ((numHeadsKv, numHeadsQPerKv),\n // batchSize)). This maps to flattened TMA shape for Q/O: (headDim, numTokens, numHeadsKv.\n // numHeadsQPerKv, batchSize). Note that TMA descriptor expects the first dimension's stride to\n // be 1, so swap the first two dimension so that the headDim dimension comes first.\n auto shape = std::vector<uint64_t>{\n static_cast<uint64_t>(options.mHeadDimV), static_cast<uint64_t>(numTokens),\n static_cast<uint64_t>(options.mNumHeadsKv), static_cast<uint64_t>(numHeadsQPerKv),\n static_cast<uint64_t>(batchSize)};\n\n // The hidden dimension.\n int32_t const hiddenDimO{options.mNumHeadsQ * options.mHeadDimV};\n\n // The stride between tokens.\n int32_t strideTokens{hiddenDimO};\n\n // The stride between Q heads.\n int32_t strideHeadsQ{options.mNumHeadsKv * options.mHeadDimV};\n\n // The stride between sequences.\n int32_t strideBatch{0};\n\n // The stride in between K/V heads.\n int32_t strideHeadsKv{options.mHeadDimV};\n // Assemble the stride (strideTokens, 1, ((strideHeadsKv, strideHeadsQ), strideBatch)).\n // Swap the first two dimension as mentioned before.\n auto stride = std::vector<uint64_t>{\n 1, static_cast<uint64_t>(strideTokens), static_cast<uint64_t>(strideHeadsKv),\n static_cast<uint64_t>(strideHeadsQ), static_cast<uint64_t>(strideBatch)};\n\n return std::make_tuple(shape, stride);\n }\n\n // Create the shape for K and V.\n template <class FmhaOptions>\n static auto makeShapeKv(FmhaOptions const& options, KernelParams const& params) {\n // The number of keys/vals. WARNING: The if/else-if are sorted by priority.\n int32_t numKeysVals{options.mMaxSeqLenKv};\n if (isPagedKv(options.mQkvLayout)) {\n numKeysVals = options.mNumTokensPerPage;\n } else if (isContiguousKv(options.mQkvLayout)) {\n numKeysVals = options.mMaxSeqLenCacheKv;\n } else {\n numKeysVals = options.mSumOfSeqLensKv;\n }\n\n // The number of heads per K/V head (packed in the sequence length for mGroupsHeadsQ).\n int32_t numHeadsKv{options.mNumHeadsKv};\n\n // The batch dimension. WARNING: The if/else-if are sorted by priority.\n int32_t batchSize{options.mBatchSize};\n if (isPagedKv(options.mQkvLayout)) {\n batchSize = params.mNumPagesInMemPool;\n } else if (isContiguousKv(options.mQkvLayout)) {\n batchSize = options.mBatchSize;\n } else {\n batchSize = 1;\n }\n\n // Return the number of keys and batch.\n return std::make_tuple(numKeysVals, numHeadsKv, batchSize);\n }\n\n // Compute the strides for K and V.\n template <class FmhaOptions>\n static auto makeStrideKv(FmhaOptions const& options, bool isK) {\n int strideKeysVals = 0;\n int strideHeads = 0;\n int strideBatch = 0;\n\n if (isK) {\n strideKeysVals = options.kStrideKeysValues;\n strideHeads = options.kStrideHeads;\n strideBatch = options.kStrideBatch;\n } else {\n strideKeysVals = options.vStrideKeysValues;\n strideHeads = options.vStrideHeads;\n strideBatch = options.vStrideBatch;\n }\n\n // Ragged layout has no batch stride; reset negative overflow to 0 for TMA descriptor.\n if (!isPagedKv(options.mQkvLayout) && !isContiguousKv(options.mQkvLayout) && strideBatch < 0) {\n strideBatch = 0;\n }\n\n // The 3 strides (the other ones are 1 and 0).\n return std::make_tuple(strideKeysVals, strideHeads, strideBatch);\n }\n\n // Create the TMA shape/stride for K.\n template <class FmhaOptions>\n static auto makeTmaShapeStrideKv(FmhaOptions const& options, KernelParams const& params,\n Data_type dtypeKv, bool isK) {\n // The shape elements.\n auto [numKeys, numHeadsQPerKv, batchSize] = makeShapeKv(options, params);\n // The stride elements.\n auto [strideKeys, strideHeads, strideBatch] = makeStrideKv(options, isK);\n\n // The headDim.\n // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv.\n int32_t headDim = isK ? options.mHeadDimQk : options.mHeadDimV;\n if (isPagedKv(options.mQkvLayout) || isContiguousKv(options.mQkvLayout)) {\n headDim = std::max(options.mHeadDimQk, options.mHeadDimV);\n }\n\n // For K, the cute layout: (numKeys, headDim, ((numHeadsQPerKv, numHeadsKv),\n // batchSize)):(strideKeys, _1, _0, strideHeads, strideBatch). Cute swaps the first two\n // dimension (to make sure stride of first dimension is 1) and ignores the numHeadsQPerKv\n // dimension (it's stride is always 0). For V, the headDim dimension is already the first\n // dimension so no swapping is needed.\n\n // Therefore, the resulting TMA layout is 4D: (headDim, numKeys, numHeadsKv, batchSize):(1,\n // strideKeys, strideHeads, strideBatch)\n\n // Note that for FP4 KV input, elements are stored as uint8_t, each packs 2 FP4 elements.\n // The column index and strides needs to divide by 2.\n auto const colIdxDivisor = dtypeKv == DATA_TYPE_E2M1 ? 2 : 1;\n auto shape = std::vector<uint64_t>{\n static_cast<uint64_t>(headDim / colIdxDivisor), static_cast<uint64_t>(numKeys),\n static_cast<uint64_t>(options.mNumHeadsKv), static_cast<uint64_t>(batchSize)};\n auto stride = std::vector<uint64_t>{1, static_cast<uint64_t>(strideKeys / colIdxDivisor),\n static_cast<uint64_t>(strideHeads / colIdxDivisor),\n static_cast<uint64_t>(strideBatch / colIdxDivisor)};\n\n return std::make_tuple(shape, stride);\n }\n\n // Create the TMA shape/stride for KV scaling factors.\n template <class FmhaOptions>\n static auto makeTmaShapeStrideKvSf(FmhaOptions const& options, KernelParams const& params,\n bool isK) {\n // The shape elements.\n auto [numKeys, numHeadsQPerKv, batchSize] = makeShapeKv(options, params);\n // The stride elements.\n auto [strideKeys, strideHeads, strideBatch] = makeStrideKv(options, isK);\n\n // The headDim.\n // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv.\n int32_t headDim = isK ? options.mHeadDimQk : options.mHeadDimV;\n if (isPagedKv(options.mQkvLayout) || isContiguousKv(options.mQkvLayout)) {\n headDim = std::max(options.mHeadDimQk, options.mHeadDimV);\n }\n // The number of elements per SF.\n int32_t NumEltsPerSf = 16;\n\n // The KV shape is: (headDim, numKeys, numHeadsKv, batchSize)\n // Therefore, the KV SF shape should be (headDim / NumEltsPerSf, numKeys, numHeadsKv,\n // batchSize). Considering the TMA requires box width to be multiple of 16B, without changing\n // the underlying layout, we reshape into (16, numKeys * headDim / NumEltsPerSf / 16,\n // numHeadsKv, batchSize)\n\n // Note that it only works for pagedKv layout.\n FLASHINFER_CHECK(isPagedKv(options.mQkvLayout), \"The qkvLayout is not supported.\");\n\n auto shape = std::vector<uint64_t>{\n 16, static_cast<uint64_t>(numKeys * headDim / NumEltsPerSf / 16),\n static_cast<uint64_t>(options.mNumHeadsKv), static_cast<uint64_t>(batchSize)};\n auto stride = std::vector<uint64_t>{1, 16, static_cast<uint64_t>(strideHeads / NumEltsPerSf),\n static_cast<uint64_t>(strideBatch / NumEltsPerSf)};\n\n return std::make_tuple(shape, stride);\n }\n\n // Prepare pointers for TMA descriptors.\n static std::tuple<void const*, void const*, void const*> getDevicePtrs(\n TllmGenFmhaRunnerParams const& runnerParams, int32_t bytesPerElt) {\n // Declare the q, k, v ptrs.\n void const *qPtr{runnerParams.qPtr}, *kPtr{runnerParams.kPtr}, *vPtr{runnerParams.vPtr};\n\n // Set Q, K and V pointer from packed QKV tensor.\n if (isPackedQkv(runnerParams.mQkvLayout)) {\n qPtr = runnerParams.qkvPtr;\n kPtr = reinterpret_cast<void const*>(reinterpret_cast<char const*>(runnerParams.qkvPtr) +\n runnerParams.mNumHeadsQ * runnerParams.mHeadDimQk *\n bytesPerElt);\n vPtr = reinterpret_cast<void const*>(reinterpret_cast<char const*>(runnerParams.qkvPtr) +\n (runnerParams.mNumHeadsQ + runnerParams.mNumHeadsKv) *\n runnerParams.mHeadDimQk * bytesPerElt);\n }\n // Set K and V pointer from pagedKv tensor.\n else if (isPagedKv(runnerParams.mQkvLayout)) {\n // Note that the offsets will be fully handled by the pageIdx buffer.\n kPtr = runnerParams.kPtr;\n vPtr = runnerParams.vPtr;\n }\n // Set K and V pointer from contiguousQAnddKv tensor.\n else if (isContiguousKv(runnerParams.mQkvLayout)) {\n kPtr = runnerParams.kvPtr;\n // The maximum headDim of K and V.\n // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv.\n int32_t const maxHeadDimKv{std::max(runnerParams.mHeadDimQk, runnerParams.mHeadDimV)};\n vPtr = reinterpret_cast<void const*>(\n reinterpret_cast<char const*>(runnerParams.kvPtr) +\n runnerParams.mNumHeadsKv * runnerParams.mMaxSeqLenCacheKv * maxHeadDimKv * bytesPerElt);\n }\n\n // Return the pointers.\n return std::make_tuple(qPtr, kPtr, vPtr);\n }\n\n // Build tma descriptors.\n template <class FmhaOptions>\n static CUtensorMap buildNdTmaDescriptor(FmhaOptions const& options, Data_type dtypeElt,\n std::vector<uint64_t> const& shapes,\n std::vector<uint64_t> const& strides,\n std::vector<uint32_t> const& tileShapes, void* gmemAddr,\n bool swizzled = true) {\n CUtensorMap desc{};\n // The data type.\n CUtensorMapDataType tmaDataFormat;\n if (dtypeElt == DATA_TYPE_E2M1 || dtypeElt == DATA_TYPE_E4M3) {\n tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_UINT8;\n } else if (dtypeElt == DATA_TYPE_FP16) {\n tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_FLOAT16;\n } else if (dtypeElt == DATA_TYPE_BF16) {\n tmaDataFormat = CU_TENSOR_MAP_DATA_TYPE_BFLOAT16;\n } else {\n FLASHINFER_CHECK(false, \"Unexpected dtype %d\", static_cast<int32_t>(dtypeElt));\n }\n\n // The swizzle type.\n CUtensorMapSwizzle swizzleType;\n int32_t numBytesInLeadingDim = tileShapes[0] * get_size_in_bits(dtypeElt) / 8 /*bits*/;\n if (!swizzled) {\n swizzleType = CU_TENSOR_MAP_SWIZZLE_NONE;\n } else if ((numBytesInLeadingDim % 128) == 0) {\n swizzleType = CU_TENSOR_MAP_SWIZZLE_128B;\n } else if ((numBytesInLeadingDim % 64) == 0) {\n swizzleType = CU_TENSOR_MAP_SWIZZLE_64B;\n } else if ((numBytesInLeadingDim % 32) == 0) {\n swizzleType = CU_TENSOR_MAP_SWIZZLE_32B;\n } else {\n FLASHINFER_CHECK(false, \"Unexpected numBytesInLeadingDim %d\", numBytesInLeadingDim);\n }\n\n // Check gmem address must be 16B-aligned\n FLASHINFER_CHECK((reinterpret_cast<uint64_t>(gmemAddr) & 0b1111) == 0);\n\n // Check shape must be in range [1, 2^32]\n int32_t dim = shapes.size();\n // Max five dimension and min 2 dimension.\n FLASHINFER_CHECK((dim <= 5) && (dim >= 2));\n // Check shape range.\n for (int32_t ii = 0; ii < dim; ++ii) {\n FLASHINFER_CHECK(shapes[ii] >= (uint64_t(1))); // Size must be min 1\n FLASHINFER_CHECK(shapes[ii] <= (uint64_t(1) << 32)); // Size must be max 2^32\n }\n\n // TMA descriptor does not store the zeroth stride and assumes it is 1.\n FLASHINFER_CHECK(static_cast<int32_t>(strides.size()) == dim);\n FLASHINFER_CHECK(strides[0] == 1);\n\n // Build strides in bytes.\n // cuTensorMapEncodeTiled ignores the stride of the first dimension (implicitly 1).\n std::vector<uint64_t> stridesInBytes(dim - 1);\n for (int32_t ii = 0; ii < dim - 1; ++ii) {\n stridesInBytes[ii] = strides[ii + 1] *\n std::max(get_size_in_bits(dtypeElt), static_cast<size_t>(8)) / 8 /*bit*/;\n }\n\n // Set tile strides to 0;\n std::vector<uint32_t> tileStrides(dim, 1);\n\n // Build the descriptor.\n CUresult result =\n cuTensorMapEncodeTiled(&desc, tmaDataFormat,\n /*tensorRank=*/dim, gmemAddr, shapes.data(), stridesInBytes.data(),\n tileShapes.data(), tileStrides.data(),\n /*interleave=*/CU_TENSOR_MAP_INTERLEAVE_NONE, swizzleType,\n /*l2Promotion=*/CU_TENSOR_MAP_L2_PROMOTION_L2_128B,\n /*oobFill=*/CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE);\n\n if (result != CUDA_SUCCESS) {\n char const* err_str;\n cuGetErrorString(result, &err_str);\n std::cerr << \"Error: Failed to initialize the TMA descriptor due to \" << err_str << std::endl;\n std::cerr << \"tmaFormat: \" << static_cast<int>(tmaDataFormat) << \" dim: \" << dim\n << \" gmem: \" << gmemAddr << std::endl;\n std::cerr << \"Shape: \" << shapes[0] << \" \" << shapes[1] << \" \" << shapes[2] << \" \"\n << shapes[3] << \" \" << shapes[4] << std::endl;\n std::cerr << \"Stride: \" << stridesInBytes[0] << \" \" << stridesInBytes[1] << \" \"\n << stridesInBytes[2] << \" \" << stridesInBytes[3] << std::endl;\n std::cerr << \"tileShapes: \" << tileShapes[0] << \" \" << tileShapes[1] << \" \" << tileShapes[2]\n << \" \" << tileShapes[3] << \" \" << tileShapes[4] << std::endl;\n std::cerr << \"tileStrides: \" << tileStrides[0] << \" \" << tileStrides[1] << \" \"\n << tileStrides[2] << \" \" << tileStrides[3] << \" \" << tileStrides[4] << std::endl;\n std::cerr << \"swizzleType: \" << int(swizzleType) << std::endl;\n FLASHINFER_CHECK(false);\n }\n\n return desc;\n }\n\n // Setup the kernel parameters.\n template <class FmhaOptions_, class KernelMeta>\n static KernelParams setKernelParams(FmhaOptions_ const& options, KernelMeta const& kernelMeta,\n int32_t maxNumCtasQ, int32_t maxNumCtasKv) {\n // Create the return struct.\n KernelParams params;\n // Memset the kernel parameters to 0.\n memset(¶ms, 0, sizeof(KernelParams));\n\n // Get the device pointers for TMA descriptors.\n auto [qPtr, kPtr, vPtr] = getDevicePtrs(options, get_size_in_bytes(kernelMeta.mDataTypeKv));\n\n // The maximum headDim of K and V.\n // Note that contiguousKv or pagedKv will pad K and V to maxHeadDimKv.\n int32_t const maxHeadDimKv{std::max(options.mHeadDimQk, options.mHeadDimV)};\n\n // Set the number of pages in the memory pool for paged K/V cache.\n if (isPagedKv(options.mQkvLayout)) {\n params.mNumPagesInMemPool = options.mNumPagesInMemPool == 0\n ? options.mMaxNumPagesPerSeqKv * 2 * options.mBatchSize\n : options.mNumPagesInMemPool;\n }\n\n // The number of elements in 128B for Q.\n int32_t numEltsIn128BQ = (128 * 8) / get_size_in_bits(kernelMeta.mDataTypeQ);\n // The number of head elts (per token) in each block of shared memory.\n int32_t numEltsInClampedHeadDimQ = std::min(numEltsIn128BQ, options.mHeadDimQk);\n\n // Shape/stride for gmem tensor Q.\n auto [shapeQ, strideQ, tileShapeQ] = makeTmaShapeStrideQ(\n options, kernelMeta.mGroupsHeadsQ, kernelMeta.mTileSizeQ, numEltsInClampedHeadDimQ);\n // Build tma descriptor for Q.\n params.tmaQ_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeQ, shapeQ, strideQ, tileShapeQ,\n const_cast<void*>(qPtr));\n\n // The number of keys per tile.\n int32_t numKeysPerTile = isPagedKv(options.mQkvLayout)\n ? std::min(options.mNumTokensPerPage, kernelMeta.mTileSizeKv)\n : kernelMeta.mTileSizeKv;\n // The number of elements in 128B for Q.\n int32_t numEltsIn128BKv = (128 * 8) / get_size_in_bits(kernelMeta.mDataTypeKv);\n // The number of head elts (per token) in each block of shared memory (see above explanation).\n int32_t numEltsInClampedHeadDimKv = std::min(numEltsIn128BKv, maxHeadDimKv);\n\n // Shape/stride for gmem tensor Kv.\n auto [shapeK, strideK] =\n makeTmaShapeStrideKv(options, params, kernelMeta.mDataTypeKv, /*isK*/ true);\n auto [shapeV, strideV] =\n makeTmaShapeStrideKv(options, params, kernelMeta.mDataTypeKv, /*isK*/ false);\n // Build tma descriptor for K.\n // Do we have to transform K/V before MMA?\n bool const transformsKv{kernelMeta.mDataTypeKv != kernelMeta.mDataTypeQ};\n // Note that for FP4 KV input, elements are stored as uint8_t, each packs 2 FP4 elements.\n auto const numEltsDivisor = kernelMeta.mDataTypeKv == DATA_TYPE_E2M1 ? 2 : 1;\n // The tileShapes for K/V.\n std::vector<uint32_t> tileShapeKv(shapeK.size(), 1);\n tileShapeKv[0] = numEltsInClampedHeadDimKv / numEltsDivisor;\n tileShapeKv[1] = numKeysPerTile;\n\n // If sparse MLA is enabled, the shape and stride for K need to be updated for 2D layout\n // (numTokensKvInPagedKv, headDimQk).\n if (options.mSparseMla) {\n shapeK = std::vector<uint64_t>{static_cast<uint64_t>(options.mHeadDimQk),\n static_cast<uint64_t>(INT_MAX)};\n strideK = std::vector<uint64_t>{1, static_cast<uint64_t>(options.mHeadDimQk)};\n tileShapeKv[1] = 1;\n }\n\n // Build tma descriptor for K.\n params.tmaK_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeKv, shapeK, strideK,\n tileShapeKv, const_cast<void*>(kPtr),\n /*swizzled = */ !transformsKv);\n // Build tma descriptor for V.\n params.tmaV_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeKv, shapeV, strideV,\n tileShapeKv, const_cast<void*>(vPtr),\n /*swizzled = */ !transformsKv);\n\n // If the KV dtype is E2m1, additional scaling factors are needed for dequant.\n if (kernelMeta.mDataTypeKv == DATA_TYPE_E2M1) {\n // The number of elements per SF.\n int32_t NumEltsPerSf = 16;\n // Compute the shape and stride for SF tensor.\n // FIXME: assume K and V uses the same shape.\n auto [shapeKvSf, strideKvSf] = makeTmaShapeStrideKvSf(options, params, /*isK*/ true);\n\n // The tileShapes for K/V.\n std::vector<uint32_t> tileShapeKvSf(shapeKvSf.size(), 1);\n tileShapeKvSf[0] = 16;\n tileShapeKvSf[1] = numKeysPerTile * maxHeadDimKv / NumEltsPerSf / 16;\n\n // The tile box is reshaped from (headDim / NumEltsPerSf, tileSizeKv) into (16, tileSizeKv *\n // headDim / NumEltsPerSf / 16). See makeTmaShapeStrideKvSf for details. Build tma descriptor\n // for K SF.\n params.tmaKSf_ = buildNdTmaDescriptor(options, DATA_TYPE_E4M3, shapeKvSf, strideKvSf,\n tileShapeKvSf, const_cast<void*>(options.kSfBasePtr),\n /*swizzled = */ false);\n\n // Build tma descriptor for V SF.\n params.tmaVSf_ = buildNdTmaDescriptor(options, DATA_TYPE_E4M3, shapeKvSf, strideKvSf,\n tileShapeKvSf, const_cast<void*>(options.vSfBasePtr),\n /*swizzled = */ false);\n }\n\n // Shape/stride for gmem tensor O.\n auto [shapeO, strideO] = makeTmaShapeStrideO(options);\n // The tileShapes for O.\n std::vector<uint32_t> tileShapeO(shapeO.size(), 1);\n tileShapeO[0] = numEltsInClampedHeadDimQ;\n tileShapeO[1] = kernelMeta.mTileSizeQ;\n // Build tma descriptor for O.\n params.tmaO_ = buildNdTmaDescriptor(options, kernelMeta.mDataTypeQ, shapeO, strideO, tileShapeO,\n const_cast<void*>(options.oPtr));\n\n // Set the other kernel parameters.\n params.ptrCumSeqLensQ = options.cumSeqLensQPtr;\n params.ptrCumSeqLensKv = options.cumSeqLensKvPtr;\n\n // The packed custom mask.\n params.ptrCustomMask = options.customMaskPtr;\n // The packed custom mask's offsets of each sequence.\n params.ptrCustomMaskOffsets = options.customMaskOffsetsPtr;\n // The first sparseMask offsets in the Kv sequence dimension.\n params.ptrFirstSparseMaskOffsetsKv = options.firstSparseMaskOffsetsKvPtr;\n\n // The output buffer.\n params.ptrO = options.oPtr;\n // The output scaling factor buffer.\n params.ptrSfO = options.oSfPtr;\n\n // TRT-LLM restrictions: the quantization scales must be on the device.\n params.ptrOutputScale = options.outputScalePtr;\n\n // The sequence lengths for Kv.\n params.ptrSeqLensKv = options.seqLensKvPtr;\n\n // Attention sink\n params.ptrAttentionSinks = options.ptrAttentionSinks;\n\n // The partial buffers' pointers when the multiCtasKv mode is enabled.\n int64_t partialStatsBufferSize = options.mMultiProcessorCount * kernelMeta.mStepQ;\n params.ptrMultiCtasKvCounter = options.multiCtasKvCounterPtr;\n params.ptrPartialStats = reinterpret_cast<float2*>(options.multiCtasKvScratchPtr);\n params.ptrPartialO = params.ptrPartialStats + partialStatsBufferSize;\n\n params.ptrPageIdxKv = options.kvPageIdxPtr;\n params.ptrScaleSoftmaxLog2 = options.scaleSoftmaxLog2Ptr;\n\n params.ptrScaleSfKv = options.kvSfScalePtr;\n params.ptrScaleSfO = options.oSfScalePtr;\n params.mScaleSfO = options.mScaleSfO;\n\n params.mAttentionWindowSize = options.mAttentionWindowSize;\n if (isSlidingOrChunkedCausalMask(\n static_cast<TrtllmGenAttentionMaskType>(kernelMeta.mMaskType)) &&\n options.mChunkedAttentionSize != INT_MAX) {\n FLASHINFER_CHECK((options.mChunkedAttentionSize & (options.mChunkedAttentionSize - 1)) == 0,\n \"Chunked attention size must be a power of 2\");\n params.mChunkedAttentionSizeLog2 = std::log2(options.mChunkedAttentionSize);\n } else {\n // Default 0 means that chunked attention is disabled.\n params.mChunkedAttentionSizeLog2 = 0;\n }\n\n // Compute the log of numTokensPerPage\n int32_t numTokensPerPageLog2{-1};\n if (isPagedKv(options.mQkvLayout)) {\n FLASHINFER_CHECK((options.mNumTokensPerPage & (options.mNumTokensPerPage - 1)) == 0,\n \"NumTokensPerPage must be power of 2\");\n numTokensPerPageLog2 = (int)log2f((float)options.mNumTokensPerPage);\n }\n params.mNumTokensPerPageLog2 = numTokensPerPageLog2;\n\n params.mMaxSeqLenQ = options.mMaxSeqLenQ;\n params.mMaxSeqLenKv = options.mMaxSeqLenKv;\n params.mMaxNumCtasQ = maxNumCtasQ;\n params.mMaxNumCtasKv = maxNumCtasKv;\n params.mMaxNumPagesPerSeqKv = options.mMaxNumPagesPerSeqKv;\n // TODO: just use mMaxSeqLenQ for number of MTP tokens.\n params.mSumOfSeqLensQ = options.mSumOfSeqLensQ;\n params.mSumOfSeqLensKv = options.mSumOfSeqLensKv;\n params.mBatchSize = options.mBatchSize;\n params.mChunkedAttentionSizeLog2 = 0;\n params.mNumHeadsQ = options.mNumHeadsQ;\n params.mNumHeadsKv = options.mNumHeadsKv;\n params.mNumHeadsQPerKv = options.mNumHeadsQPerKv;\n params.mNumHiddenEltsO = options.mNumHeadsQ * options.mHeadDimQk;\n params.mOutputScale = options.outputScale;\n params.mScaleSoftmaxLog2 = options.scaleSoftmaxLog2;\n params.mStartTokenIdxSfO = options.mSfStartTokenIdx;\n params.mScaleSfKv = options.mScaleSfKv;\n params.ptrSoftmaxStats = options.softmaxStatsPtr;\n // The sparseMlaTopK needs to be a multiple of 4 as we use 16B cpAsync instructions for the\n // indices.\n FLASHINFER_CHECK(!options.mSparseMla || (options.mSparseMlaTopK % 4) == 0,\n \"SparseMlaTopK must be a multiple of 4\");\n params.mSparseMlaTopK = options.mSparseMlaTopK;\n // TODO: Integrate trtllm block-sparse attention kernels when needed.\n params.mUseBlockSparseAttention = false;\n return params;\n }\n};\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nThis MR adds the optimized decode attention kernels for high throughput (large batch size) + speculative decoding (seqlen_q > 1). \n\nSee below for speedups (collected by `benchmarks/flashinfer_benchmark.py`). The seqlenKv is 16K for all cases. \n\n| test case | median_time_ms | median_time_ms (opt) | speedup |\n|------------------------------------------|----------------|----------------------|----------|\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ2 | 0.057 | 0.046 | 1.24 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ2 | 0.11 | 0.083 | 1.33 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ2 | 0.213 | 0.168 | 1.27 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ2 | 0.266 | 0.241 | 1.10 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ2 | 0.432 | 0.336 | 1.29 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ4 | 0.109 | 0.048 | 2.27 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ4 | 0.212 | 0.083 | 2.55 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ4 | 0.371 | 0.168 | 2.21 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ4 | 0.472 | 0.245 | 1.93 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ4 | 0.736 | 0.348 | 2.11 |\n| Qwen3-480B-fp8_e4m3-batchSize8-seqLenQ8 | 0.212 | 0.061 | 3.48 |\n| Qwen3-480B-fp8_e4m3-batchSize16-seqLenQ8 | 0.37 | 0.106 | 3.49 |\n| Qwen3-480B-fp8_e4m3-batchSize32-seqLenQ8 | 0.732 | 0.239 | 3.06 |\n| Qwen3-480B-fp8_e4m3-batchSize40-seqLenQ8 | 0.937 | 0.321 | 2.92 |\n| Qwen3-480B-fp8_e4m3-batchSize64-seqLenQ8 | 1.456 | 0.484 | 3.01 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ2 | 0.051 | 0.03 | 1.70 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ2 | 0.098 | 0.054 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ2 | 0.188 | 0.104 | 1.81 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ2 | 0.234 | 0.15 | 1.56 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ2 | 0.332 | 0.199 | 1.67 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ4 | 0.099 | 0.038 | 2.61 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ4 | 0.188 | 0.07 | 2.69 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ4 | 0.332 | 0.136 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ4 | 0.418 | 0.2 | 2.09 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ4 | 0.647 | 0.265 | 2.44 |\n| GPT-OSS-fp8_e4m3-batchSize8-seqLenQ8 | 0.188 | 0.039 | 4.82 |\n| GPT-OSS-fp8_e4m3-batchSize16-seqLenQ8 | 0.332 | 0.065 | 5.11 |\n| GPT-OSS-fp8_e4m3-batchSize32-seqLenQ8 | 0.647 | 0.126 | 5.13 |\n| GPT-OSS-fp8_e4m3-batchSize40-seqLenQ8 | 0.83 | 0.185 | 4.49 |\n| GPT-OSS-fp8_e4m3-batchSize64-seqLenQ8 | 1.29 | 0.245 | 5.27 |\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **Bug Fixes**\n * Generation attention now enforces causal masking during token generation.\n\n* **Performance / Refactor**\n * Improved kernel selection and on-demand loading for better performance and GPU compatibility.\n * Added finer-grained tuning parameters for tile/grouping, tokens-per-CTA and inflation to enable more optimal kernel choices.\n\n* **Chores**\n * Updated FMHA artifact paths and checksums.\n\n* **Tests**\n * Expanded parameterized tests to cover larger batch decoding scenarios.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1197,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"4de2a45a5d38da7487ec37b694c644d8906551a6"},"date":{"kind":"string","value":"2025-12-27T15:53:00+08:00"},"pr_number":{"kind":"number","value":2268,"string":"2,268"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2268"},"title":{"kind":"string","value":"[performance]optimize for nvfp4 (#2268)"},"message":{"kind":"string","value":"[performance]optimize for nvfp4 (#2268)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nI find the nvfp4 implemantation could only 1.3-1.4x speedup compared to\nfp8 in deepseek-v3-0324 model .\nand as the fp4 pflops is twice that of fp8, I think there should be some\npoints that could be optimization.\n\nnow after applying this pr, we can get an extra 10-15% speedup on fp4.\n1369.89/1192.91=1.148 ~= 15% speedup\n\ntest cmd\n```\npython3 -m sglang.bench_serving --backend sglang --dataset-name random --num-prompts 1000 --random-input 1000 --random-output 1000 --max-concurrency 60 --port 30000 --host 0.0.0.0\n```\n\naccuracy\n```\n+------------------+-----------+----------+----------+-------+---------+---------+\n| Model | Dataset | Metric | Subset | Num | Score | Cat.0 |\n+==================+===========+==========+==========+=======+=========+=========+\n| DeepSeek-V3-0324 | aime24 | mean_acc | default | 300 | 0.5467 | default |\n+------------------+-----------+----------+----------+-------+---------+---------+ \n```\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the\npre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.\n-->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n\n## Summary by CodeRabbit\n\n* **Refactor**\n* Optimized FP4/FP8 quantization paths with improved register efficiency\n* Enhanced kernel launch configuration to improve GPU occupancy and\nperformance\n * Streamlined accumulation processes to reduce memory footprint\n\n<sub>✏️ Tip: You can customize this high-level summary in your review\nsettings.</sub>\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\nSigned-off-by: bruce.xu <bruce.xu@gmicloud.ai>\nCo-authored-by: bruce.xu <bruce.xu@gmicloud.ai>"},"path":{"kind":"string","value":"include/flashinfer/comm/trtllm_allreduce_fusion.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"#include <cooperative_groups.h>\n#include <cuda.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n\n#if CUDA_VERSION >= 12080\n#include <cuda_fp4.h>\n#endif\n\n#include <cuda/std/optional>\n#include <tuple>\n#include <type_traits>\n\n#include \"../exception.h\"\n#include \"../fp4_layout.cuh\"\n#include \"../logging.h\"\n#include \"../utils.cuh\"\n#include \"../vec_dtypes.cuh\"\n\nnamespace flashinfer {\n\nnamespace trtllm_allreduce_fusion {\n\nusing flashinfer::QuantizationSFLayout;\n\nnamespace details {\n\nstatic constexpr int CVT_FP4_ELTS_PER_THREAD = 8;\nstatic constexpr int CVT_FP4_SF_VEC_SIZE = 16;\nstatic constexpr int kBytesPerAccess = 16;\nstatic constexpr int kOneShotMaxToken = 128;\nstatic constexpr int kBarrierFlagCount = 256;\n\n} // namespace details\n\nnamespace maths {\n// // ============================== Cast ==============================\ntemplate <typename T_OUT, typename T_IN>\n__device__ inline T_OUT cuda_cast(T_IN val) {\n return val;\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, int2>(int2 val) {\n return make_float2(val.x, val.y);\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, float>(float val) {\n return make_float2(val, val);\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, half2>(half2 val) {\n return __half22float2(val);\n}\n\ntemplate <>\n__device__ inline half2 cuda_cast<half2, float2>(float2 val) {\n return __float22half2_rn(val);\n}\n\ntemplate <>\n__device__ inline half2 cuda_cast<half2, float>(float val) {\n return __float2half2_rn(val);\n}\n\ntemplate <>\n__device__ inline half2 cuda_cast<half2, half>(half val) {\n return __half2half2(val);\n}\n\ntemplate <>\n__device__ inline int8_t cuda_cast<int8_t, half>(half val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n union {\n half fp16;\n int16_t int16_in;\n };\n\n fp16 = val;\n asm volatile(\"cvt.rni.sat.s8.f16 %0, %1;\" : \"=h\"(int16) : \"h\"(int16_in));\n return int8[0];\n}\n\ntemplate <>\n__device__ inline int16_t cuda_cast<int16_t, half2>(half2 val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int8[0] = cuda_cast<int8_t>(val.x);\n int8[1] = cuda_cast<int8_t>(val.y);\n return int16;\n}\n\ntemplate <>\n__device__ inline int8_t cuda_cast<int8_t, float>(float val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n asm volatile(\"cvt.rni.sat.s8.f32 %0, %1;\" : \"=h\"(int16) : \"f\"(val));\n return int8[0];\n}\n\ntemplate <>\n__device__ inline int16_t cuda_cast<int16_t, float2>(float2 val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int8[0] = cuda_cast<int8_t>(val.x);\n int8[1] = cuda_cast<int8_t>(val.y);\n return int16;\n}\n\ntemplate <>\n__device__ inline half2 cuda_cast<half2, int16_t>(int16_t val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int16 = val;\n return make_half2(int8[0], int8[1]);\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, int16_t>(int16_t val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int16 = val;\n return make_float2(int8[0], int8[1]);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_cast(int32_t val) {\n return static_cast<float>(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_cast(int8_t val) {\n return static_cast<float>(val);\n}\n\ntemplate <>\n__device__ inline int8_t cuda_cast(__nv_bfloat16 val) {\n return static_cast<float>(val);\n}\n\ntemplate <>\n__device__ inline float cuda_cast<float, __nv_bfloat16>(__nv_bfloat16 val) {\n return __bfloat162float(val);\n}\n\ninline __device__ float2 bf1622float2(const __nv_bfloat162 val) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800\n float2 f_val;\n f_val.x = __low2float(val);\n f_val.y = __high2float(val);\n return f_val;\n#else\n return __bfloat1622float2(val);\n#endif\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, __nv_bfloat162>(__nv_bfloat162 val) {\n return bf1622float2(val);\n}\n\ntemplate <>\n__device__ inline half cuda_cast<half, __nv_bfloat16>(__nv_bfloat16 val) {\n return __float2half(__bfloat162float(val));\n}\n\ninline __device__ int16_t bf1622int16(__nv_bfloat162 val) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800\n float2 f_val;\n f_val.x = max(min(__low2float(val), 127.f), -128.f);\n f_val.y = max(min(__high2float(val), 127.f), -128.f);\n\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int8[0] = static_cast<int8_t>(static_cast<short>(f_val.x));\n int8[1] = static_cast<int8_t>(static_cast<short>(f_val.y));\n return int16;\n#else\n val = __hmin2(val, make_bfloat162(127., 127.));\n val = __hmax2(val, make_bfloat162(-128., -128.));\n\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int8[0] = static_cast<int8_t>(static_cast<short>(val.x));\n int8[1] = static_cast<int8_t>(static_cast<short>(val.y));\n return int16;\n#endif\n}\n\ntemplate <>\n__device__ inline int16_t cuda_cast<int16_t, __nv_bfloat162>(__nv_bfloat162 val) {\n return bf1622int16(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_cast<__nv_bfloat16, float>(float val) {\n return __float2bfloat16(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_cast<__nv_bfloat16, half>(half val) {\n return __float2bfloat16(__half2float(val));\n}\n\ninline __device__ __nv_bfloat162 bf162bf162(const __nv_bfloat16 val) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800\n __nv_bfloat162 val2;\n val2.x = val;\n val2.y = val;\n return val2;\n#else\n return __bfloat162bfloat162(val);\n#endif\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, __nv_bfloat16>(__nv_bfloat16 val) {\n return bf162bf162(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, float>(float val) {\n return __float2bfloat162_rn(val);\n}\n\ninline __device__ __nv_bfloat162 float22bf162(const float2 val) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800\n return __floats2bfloat162_rn(val.x, val.y);\n#else\n return __float22bfloat162_rn(val);\n#endif\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, float2>(float2 val) {\n return float22bf162(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, int16_t>(int16_t val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int16 = val;\n __nv_bfloat162 res;\n res.x = cuda_cast<__nv_bfloat16>(int8[0]);\n res.y = cuda_cast<__nv_bfloat16>(int8[1]);\n return res;\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, half2>(half2 val) {\n return float22bf162(__half22float2(val));\n}\n\n// // ============================== Abs ==============================\ntemplate <typename T>\n__device__ inline T cuda_abs(T val) {\n assert(false);\n return {};\n}\n\ntemplate <>\n__device__ inline float cuda_abs(float val) {\n return fabs(val);\n}\n\ntemplate <>\n__device__ inline float2 cuda_abs(float2 val) {\n return make_float2(fabs(val.x), fabs(val.y));\n}\n\ntemplate <>\n__device__ inline half cuda_abs(half val) {\n return __habs(val);\n}\n\ntemplate <>\n__device__ inline half2 cuda_abs(half2 val) {\n return __habs2(val);\n}\n\n#if __CUDA_ARCH__ >= 800 || !defined(__CUDA_ARCH__)\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_abs(__nv_bfloat16 val) {\n return __habs(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_abs(__nv_bfloat162 val) {\n return __habs2(val);\n}\n#endif\n\n// // ============================== Max ==============================\ntemplate <typename To, typename Ti>\n__device__ inline To cuda_max(Ti val) {\n return cuda_cast<To>(val);\n};\n\ntemplate <>\n__device__ inline float cuda_max(float2 val) {\n return fmaxf(val.x, val.y);\n}\n\ntemplate <>\n__device__ inline half cuda_max(half2 val) {\n return __hmax(val.x, val.y);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_max(__nv_bfloat162 val) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n return __hmax(val.x, val.y);\n#else\n assert(0);\n asm volatile(\"brkpt;\\n\" ::);\n return __nv_bfloat16(0);\n#endif\n}\n\n// Binary maximum: compute the max of two values.\ntemplate <typename T>\n__device__ inline T cuda_max(T val1, T val2) {\n return (val1 > val2) ? val1 : val2;\n}\n\ntemplate <>\n__device__ inline float2 cuda_max(float2 val1, float2 val2) {\n float2 out;\n out.x = fmaxf(val1.x, val2.x);\n out.y = fmaxf(val1.y, val2.y);\n return out;\n}\n\ntemplate <>\n__device__ inline half2 cuda_max(half2 val1, half2 val2) {\n return __hmax2(val1, val2);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_max(__nv_bfloat162 val1, __nv_bfloat162 val2) {\n return __hmax2(val1, val2);\n}\n\n// // ============================== Reciprocal ==============================\n// Fast reciprocal.\ninline __device__ float reciprocal_approximate_ftz(float a) {\n float b;\n asm volatile(\"rcp.approx.ftz.f32 %0, %1;\\n\" : \"=f\"(b) : \"f\"(a));\n return b;\n}\n} // namespace maths\n\nnamespace utils {\n\n#define FINAL_MASK 0xffffffff\n\ntemplate <typename T, int NUM>\n__inline__ __device__ T warpReduceSumV2(T* val) {\n#pragma unroll\n for (int i = 0; i < NUM; i++) {\n#pragma unroll\n for (int mask = 16; mask > 0; mask >>= 1)\n val[i] += __shfl_xor_sync(FINAL_MASK, val[i], mask, 32);\n }\n return (T)(0.0f);\n}\n\ntemplate <typename T, int NUM>\n__inline__ __device__ T blockReduceSumV2(T* val) {\n static __shared__ T shared[NUM][33];\n int lane = threadIdx.x & 0x1f;\n int wid = threadIdx.x >> 5;\n\n warpReduceSumV2<T, NUM>(val);\n\n if (lane == 0) {\n#pragma unroll\n for (int i = 0; i < NUM; i++) {\n shared[i][wid] = val[i];\n }\n }\n\n __syncthreads();\n\n bool is_mask = threadIdx.x < (blockDim.x / 32.f);\n#pragma unroll\n for (int i = 0; i < NUM; i++) {\n val[i] = is_mask ? shared[i][lane] : (T)(0.0f);\n }\n warpReduceSumV2<T, NUM>(val);\n return (T)0.0f;\n}\n\ninline int getSMVersion() {\n int device{-1};\n FLASHINFER_CUDA_CALL(cudaGetDevice(&device));\n int sm_major = 0;\n int sm_minor = 0;\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&sm_major, cudaDevAttrComputeCapabilityMajor, device));\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&sm_minor, cudaDevAttrComputeCapabilityMinor, device));\n return sm_major * 10 + sm_minor;\n}\n\ninline int getSMRegisters() {\n int device{-1};\n FLASHINFER_CUDA_CALL(cudaGetDevice(&device));\n int regs_per_block;\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(®s_per_block, cudaDevAttrMaxRegistersPerBlock, device));\n return regs_per_block;\n}\n\ninline __device__ int64_t get_sf_out_offset_128x4(std::optional<int> batchIdx, int mIdx, int kIdx,\n std::optional<int> numRows, int numCols) {\n // SF layout [numMTiles, numKTiles, 32 (mTile), 4 (mTile), 4(kTile)]\n // --> index [mTileIdx, kTileIdx, outerMIdx, innerMIdx, innerKIdx]\n\n // batched tensor\n // SF layout [numBTiles, numMTiles, numKTiles, 32 (mTile), 4 (mTile), 4(kTile)]\n // --> index [bTileIdx, mTileIdx, kTileIdx, outerMIdx, innerMIdx, innerKIdx]\n\n int32_t innerKIdx = (kIdx % 4);\n int64_t innerKStride = 1;\n\n int32_t innerMIdx = (mIdx % (32 * 4)) / 32;\n int64_t innerMStride = 4 * innerKStride; // 4\n\n // M tile layout [32, 4] is column-major.\n int32_t outerMIdx = (mIdx % 32);\n int64_t outerMStride = 4 * innerMStride; // 16\n\n int32_t kTileIdx = (kIdx / 4);\n int64_t kTileStride = 32 * outerMStride; // 512\n\n // SF vector size 16. We round the \"numCols\" up to a multiple of 64.\n int factor = details::CVT_FP4_SF_VEC_SIZE * 4;\n int32_t numKTiles = (numCols + factor - 1) / factor;\n int32_t mTileIdx = mIdx / (32 * 4);\n int64_t mTileStride = numKTiles * kTileStride;\n\n // Each SF block has 128 rows so pad rows to the multiple of 128.\n int32_t numMTiles = (numRows.value_or(0) + 128 - 1) / 128;\n int64_t bTileStride = numMTiles * mTileStride;\n\n // Compute the global offset.\n int64_t SFOffset = batchIdx.value_or(0) * bTileStride + mTileIdx * mTileStride +\n kTileIdx * kTileStride + outerMIdx * outerMStride + innerMIdx * innerMStride +\n innerKIdx * innerKStride;\n\n return SFOffset;\n}\n\ntemplate <class SFType, int CVT_FP4_NUM_THREADS_PER_SF>\n__device__ uint8_t* cvt_quant_to_fp4_get_sf_out_offset(std::optional<int> batchIdx, int rowIdx,\n int colIdx, std::optional<int> numRows,\n int numCols, SFType* SFout,\n QuantizationSFLayout layout) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n static_assert(CVT_FP4_NUM_THREADS_PER_SF == 1 || CVT_FP4_NUM_THREADS_PER_SF == 2);\n\n // One pair of threads write one SF to global memory.\n // TODO: stage through smem for packed STG.32\n // is it better than STG.8 from 4 threads ?\n if (threadIdx.x % CVT_FP4_NUM_THREADS_PER_SF == 0) {\n if (layout == QuantizationSFLayout::SWIZZLED_128x4) {\n // SF vector index (16 elements share one SF in the K dimension).\n // numRows and numCols are unpadded.\n int32_t kIdx = colIdx / CVT_FP4_NUM_THREADS_PER_SF;\n int32_t mIdx = rowIdx;\n\n auto SFOffset = get_sf_out_offset_128x4(batchIdx, mIdx, kIdx, numRows, numCols);\n return reinterpret_cast<uint8_t*>(SFout) + SFOffset;\n } else if (layout == QuantizationSFLayout::LINEAR) {\n // Linear row-major layout, no padding required.\n int32_t KTileIdx = colIdx / CVT_FP4_NUM_THREADS_PER_SF;\n\n int32_t numKTiles = numCols / details::CVT_FP4_SF_VEC_SIZE;\n int64_t mTileStride = numKTiles;\n\n int64_t BTileStride = numRows.value_or(0) * mTileStride;\n\n int64_t SFOffset = batchIdx.value_or(0) * BTileStride + rowIdx * mTileStride + KTileIdx;\n return reinterpret_cast<uint8_t*>(SFout) + SFOffset;\n } else {\n return nullptr;\n }\n }\n#endif\n return nullptr;\n}\n\n__forceinline__ __device__ uint32_t pack_bytes(uint8_t c0, uint8_t c1, uint8_t c2, uint8_t c3) {\n uint32_t val0 = c0;\n uint32_t val1 = c1;\n uint32_t val2 = c2;\n uint32_t val3 = c3;\n\n return (val3 << 24) | (val2 << 16) | (val1 << 8) | val0;\n}\n\n#if CUDA_VERSION >= 12080\n// Convert 8 float32 values into 8 e2m1 values (represented as one uint32_t).\n// NOTE: bypass sm_100 requirement by __nv_cvt_float2_to_fp4x2\ninline __device__ uint32_t fp32_vec_to_e2m1(float (&array)[8]) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n uint32_t val;\n asm volatile(\n \"{\\n\"\n \".reg .b8 byte0;\\n\"\n \".reg .b8 byte1;\\n\"\n \".reg .b8 byte2;\\n\"\n \".reg .b8 byte3;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte0, %2, %1;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte1, %4, %3;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte2, %6, %5;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte3, %8, %7;\\n\"\n \"mov.b32 %0, {byte0, byte1, byte2, byte3};\\n\"\n \"}\"\n : \"=r\"(val)\n : \"f\"(array[0]), \"f\"(array[1]), \"f\"(array[2]), \"f\"(array[3]), \"f\"(array[4]), \"f\"(array[5]),\n \"f\"(array[6]), \"f\"(array[7]));\n return val;\n#else\n uint32_t val;\n __nv_fp4x2_storage_t vals[4];\n#pragma unroll\n for (int i = 0; i < 4; i++) {\n vals[i] = __nv_cvt_float2_to_fp4x2(*(((float2*)array) + i), __NV_E2M1, cudaRoundNearest);\n }\n val = pack_bytes(vals[0], vals[1], vals[2], vals[3]);\n return val;\n#endif\n}\n\n// Convert 4 float2 values into 8 e2m1 values (represented as one uint32_t).\ninline __device__ uint32_t fp32_vec_to_e2m1(float2 (&array)[4]) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n uint32_t val;\n asm volatile(\n \"{\\n\"\n \".reg .b8 byte0;\\n\"\n \".reg .b8 byte1;\\n\"\n \".reg .b8 byte2;\\n\"\n \".reg .b8 byte3;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte0, %2, %1;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte1, %4, %3;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte2, %6, %5;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte3, %8, %7;\\n\"\n \"mov.b32 %0, {byte0, byte1, byte2, byte3};\\n\"\n \"}\"\n : \"=r\"(val)\n : \"f\"(array[0].x), \"f\"(array[0].y), \"f\"(array[1].x), \"f\"(array[1].y), \"f\"(array[2].x),\n \"f\"(array[2].y), \"f\"(array[3].x), \"f\"(array[3].y));\n return val;\n#else\n uint32_t val;\n __nv_fp4x2_storage_t vals[4];\n#pragma unroll\n for (int i = 0; i < 4; i++) {\n vals[i] = __nv_cvt_float2_to_fp4x2(array[i], __NV_E2M1, cudaRoundNearest);\n }\n val = pack_bytes(vals[0], vals[1], vals[2], vals[3]);\n return val;\n#endif\n}\n\n// Quantizes the provided PackedVec into the uint32_t output\ntemplate <typename T, uint32_t VEC_SIZE, bool UE8M0_SF = false>\n__device__ uint32_t cvt_warp_fp16_to_fp4(vec_t<T, VEC_SIZE>& vec, float SFScaleVal,\n uint8_t* SFout) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n // Get absolute maximum values among the local 8 values.\n auto localMax = maths::cuda_abs(get_vec2_element(vec, 0));\n\n#pragma unroll\n for (int i = 1; i < details::CVT_FP4_ELTS_PER_THREAD / 2; i++) {\n localMax = maths::cuda_max(localMax, maths::cuda_abs(get_vec2_element(vec, i)));\n }\n\n // Get the absolute maximum among all 16 values (two threads).\n localMax = maths::cuda_max(__shfl_xor_sync(uint32_t(-1), localMax, 1), localMax);\n // Get the final absolute maximum values.\n float vecMax = float(maths::cuda_max(localMax.x, localMax.y));\n\n // Get the SF (max value of the vector / max value of e2m1).\n // maximum value of e2m1 = 6.0.\n // TODO: use half as compute data type.\n float SFValue = SFScaleVal * (vecMax * maths::reciprocal_approximate_ftz(6.0f));\n // 8 bits representation of the SF.\n uint8_t fp8SFVal;\n // Write the SF to global memory (STG.8).\n if constexpr (UE8M0_SF) {\n#if (__CUDACC_VER_MAJOR__ * 1000 + __CUDACC_VER_MINOR__ * 10 >= 12080)\n __nv_fp8_e8m0 tmp;\n tmp.__x = __nv_cvt_float_to_e8m0(SFValue, __NV_SATFINITE, cudaRoundPosInf);\n SFValue = static_cast<float>(tmp);\n fp8SFVal = tmp.__x;\n#else\n#error \"FP8 E8M0 support requires CUDA 12.8 or newer.\"\n#endif\n } else {\n // Here SFValue is always positive, so E4M3 is the same as UE4M3.\n __nv_fp8_e4m3 tmp = __nv_fp8_e4m3(SFValue);\n fp8SFVal = tmp.__x;\n SFValue = static_cast<float>(tmp);\n }\n // Get the output scale.\n // Recipe: final_scale = reciprocal(fp32(fp8(SFValue * SFScaleVal))) * reciprocal(SFScaleVal))\n float outputScale = SFValue != 0 ? maths::reciprocal_approximate_ftz(\n SFValue * maths::reciprocal_approximate_ftz(SFScaleVal))\n : 0.0f;\n\n if (SFout) {\n // Write the SF to global memory (STG.8).\n *SFout = fp8SFVal;\n }\n\n // Convert the input to float.\n float2 fp2Vals[details::CVT_FP4_ELTS_PER_THREAD / 2];\n\n#pragma unroll\n for (int i = 0; i < details::CVT_FP4_ELTS_PER_THREAD / 2; i++) {\n if constexpr (std::is_same_v<T, half>) {\n fp2Vals[i] = __half22float2(get_vec2_element(vec, i));\n } else {\n fp2Vals[i] = __bfloat1622float2(get_vec2_element(vec, i));\n }\n fp2Vals[i].x *= outputScale;\n fp2Vals[i].y *= outputScale;\n }\n\n // Convert to e2m1 values.\n uint32_t e2m1Vec = fp32_vec_to_e2m1(fp2Vals);\n\n // Write the e2m1 values to global memory.\n return e2m1Vec;\n#else\n return 0;\n#endif\n}\n\n#endif\n\n} // namespace utils\n\ntemplate <typename T, uint32_t VEC_SIZE>\n__device__ __forceinline__ vec_t<T, VEC_SIZE> vec_add(const vec_t<T, VEC_SIZE>& a,\n const vec_t<T, VEC_SIZE>& b) {\n vec_t<T, VEC_SIZE> ret;\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n ret[i] = static_cast<float>(a[i]) + static_cast<float>(b[i]);\n }\n return ret;\n}\n\nenum class AllReduceFusionPattern : int {\n kAllReduce = 0,\n kARResidualRMSNorm = 1,\n kARResidualRMSNormFP8Quant = 2,\n kARResidualRMSNormFP4Quant = 3,\n // The difference between these two and the standard version is that the NormOut version outputs\n // the result of the norm.\n kARResidualRMSNormOutFP8Quant = 4,\n kARResidualRMSNormOutFP4Quant = 5\n};\n\nenum class QuantType : int {\n kNone = 0,\n kFP8 = 1,\n kFP4 = 2,\n};\n\ntemplate <AllReduceFusionPattern Pattern>\nstruct FusionPatternTraits;\n\n#define DEFINE_FUSION_PATTERN_TRAITS(pattern, hasAllReduceOut, hasResidual, hasResidualOut, \\\n hasRMSNorm, hasNormOut, quantType) \\\n template <> \\\n struct FusionPatternTraits<pattern> { \\\n static constexpr bool kHasAllReduceOut = hasAllReduceOut; \\\n static constexpr bool kHasResidual = hasResidual; \\\n static constexpr bool kHasResidualOut = hasResidualOut; \\\n static constexpr bool kHasRMSNorm = hasRMSNorm; \\\n static constexpr bool kHasNormOut = hasNormOut; \\\n static constexpr QuantType kQuantType = quantType; \\\n };\n\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kAllReduce, true, false, false, false, false,\n QuantType::kNone);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNorm, false, true, true, true,\n true, QuantType::kNone);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNormFP8Quant, false, true, true,\n true, false, QuantType::kFP8);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNormFP4Quant, false, true, true,\n true, false, QuantType::kFP4);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNormOutFP8Quant, false, true,\n true, true, true, QuantType::kFP8);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNormOutFP4Quant, false, true,\n true, true, true, QuantType::kFP4);\n#undef DEFINE_FUSION_PATTERN_TRAITS\n\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasResidual = FusionPatternTraits<Pattern>::kHasResidual;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasRMSNorm = FusionPatternTraits<Pattern>::kHasRMSNorm;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasAllReduceOut = FusionPatternTraits<Pattern>::kHasAllReduceOut;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasResidualOut = FusionPatternTraits<Pattern>::kHasResidualOut;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasNormOut = FusionPatternTraits<Pattern>::kHasNormOut;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr QuantType GetQuantType = FusionPatternTraits<Pattern>::kQuantType;\n\ntemplate <typename T>\nstruct AllReduceFusionParams {\n int nranks;\n int rank;\n int size;\n int hidden_dim;\n void** workspace;\n void* allreduce_in;\n void* allreduce_out;\n void* residual_in;\n void* residual_out;\n void* norm_out;\n void* quant_out;\n void* scale_out;\n void* rms_gamma;\n float rms_eps;\n float* scale_factor;\n bool use_oneshot;\n QuantizationSFLayout layout = QuantizationSFLayout::SWIZZLED_128x4;\n cudaStream_t stream;\n AllReduceFusionPattern pattern;\n bool trigger_completion_at_end = true;\n};\n\ntemplate <int NRanks>\nstruct SyncComm {\n __device__ __forceinline__ SyncComm(void** workspace) {\n counter_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[0];\n flag_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[1];\n flag_value = *flag_ptr;\n for (int r = 0; r < NRanks; ++r) {\n comm_bufs[r] = workspace[r];\n barrier_flags[r] = workspace[NRanks + r];\n }\n __syncthreads();\n if (threadIdx.x == 0) {\n atomicAdd(counter_ptr, 1);\n }\n }\n\n __device__ __forceinline__ void update(int new_flag_value) {\n if (blockIdx.x == 0 && threadIdx.x == 0) {\n while (*reinterpret_cast<int volatile*>(counter_ptr) != gridDim.x) {\n }\n *flag_ptr = new_flag_value;\n *counter_ptr = 0;\n }\n }\n\n int* counter_ptr;\n int* flag_ptr;\n void* comm_bufs[NRanks];\n void* barrier_flags[NRanks];\n int flag_value;\n};\n\ntemplate <int NRanks>\nstruct LamportComm {\n __device__ __forceinline__ LamportComm(void** workspace, int rank) {\n counter_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[0];\n flag_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[2];\n clear_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[4];\n flag_value = *flag_ptr;\n int comm_size = reinterpret_cast<int*>(workspace[NRanks * 3])[3];\n clear_size = *clear_ptr;\n int data_offset = flag_value % 3;\n int clear_offset = (flag_value + 2) % 3;\n for (int r = 0; r < NRanks; ++r) {\n data_bufs[r] = reinterpret_cast<uint8_t*>(workspace[2 * NRanks + r]) +\n static_cast<int64_t>(data_offset) * comm_size;\n }\n clear_buf = reinterpret_cast<uint8_t*>(workspace[2 * NRanks + rank]) + clear_offset * comm_size;\n __syncthreads();\n if (threadIdx.x == 0) {\n atomicAdd(counter_ptr, 1);\n }\n }\n\n __device__ __forceinline__ void update(int new_clear_size) {\n if (blockIdx.x == 0 && threadIdx.x == 0) {\n while (*reinterpret_cast<int volatile*>(counter_ptr) != gridDim.x) {\n }\n *flag_ptr = (flag_value + 1) % 3;\n *clear_ptr = new_clear_size;\n *counter_ptr = 0;\n }\n }\n\n int* counter_ptr;\n int* flag_ptr;\n int* clear_ptr;\n uint8_t* data_bufs[NRanks];\n uint8_t* clear_buf;\n int clear_size;\n int flag_value;\n};\n\ntemplate <int NRanks>\nclass Barrier {\n public:\n __device__ __forceinline__ Barrier(int rank, SyncComm<NRanks> const& comm) {\n if (threadIdx.x < NRanks) {\n m_flag_value = comm.flag_value;\n int current_rank = rank;\n int target_rank = threadIdx.x;\n m_target_flag = reinterpret_cast<int*>(comm.barrier_flags[target_rank]) + current_rank;\n m_current_flag = reinterpret_cast<int*>(comm.barrier_flags[current_rank]) +\n blockIdx.x * NRanks + target_rank;\n }\n }\n\n __device__ __forceinline__ void sync() {\n __syncthreads();\n if (threadIdx.x < NRanks) {\n m_flag_value = next_flag(m_flag_value);\n // To avoid the ABA problem, we need to synchronize the correct flag value to all\n // barrier_flags, even if the corresponding CTA has not been launched.\n for (int flag_idx = blockIdx.x; flag_idx < details::kBarrierFlagCount;\n flag_idx += gridDim.x) {\n st_flag(m_target_flag + flag_idx * NRanks, m_flag_value);\n }\n while (ld_flag(m_current_flag) == prev_flag(m_flag_value)) {\n }\n }\n __syncthreads();\n }\n\n protected:\n __device__ __forceinline__ void st_flag(int* addr, int flag) {\n asm volatile(\"st.global.release.sys.b32 [%1], %0;\" ::\"r\"(flag), \"l\"(addr));\n }\n\n __device__ __forceinline__ int ld_flag(int* addr) {\n int flag;\n asm volatile(\"ld.global.acquire.sys.b32 %0, [%1];\" : \"=r\"(flag) : \"l\"(addr));\n return flag;\n }\n\n __device__ __forceinline__ int next_flag(int flag) { return flag == 2 ? 0 : flag + 1; }\n\n __device__ __forceinline__ int prev_flag(int flag) { return flag == 0 ? 2 : flag - 1; }\n\n public:\n int m_flag_value;\n\n private:\n int* m_target_flag;\n int* m_current_flag;\n};\n\ntemplate <AllReduceFusionPattern Pattern, typename T>\nclass FusedOp {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n\n public:\n __device__ __forceinline__ FusedOp(AllReduceFusionParams<T> const& params, int access_id,\n int access_id_in_token)\n : m_params(params), m_access_id(access_id), m_access_id_in_token(access_id_in_token) {\n if constexpr (HasRMSNorm<Pattern>) {\n m_gamma_val.load(reinterpret_cast<T*>(params.rms_gamma) + m_access_id_in_token * VEC_SIZE);\n }\n if constexpr (HasResidual<Pattern>) {\n m_residual_val.load(reinterpret_cast<T*>(params.residual_in) + m_access_id * VEC_SIZE);\n }\n if constexpr (GetQuantType<Pattern> == QuantType::kFP8) {\n m_scale_factor = 1.f / *(params.scale_factor);\n } else if constexpr (GetQuantType<Pattern> == QuantType::kFP4) {\n m_scale_factor = *(params.scale_factor);\n }\n }\n\n // template <typename T>\n __device__ __forceinline__ void update(int access_id) {\n if (m_access_id != access_id) {\n m_access_id = access_id;\n if constexpr (HasResidual<Pattern>) {\n m_residual_val.load(reinterpret_cast<T*>(m_params.residual_in) + m_access_id * VEC_SIZE);\n }\n }\n }\n\n // template <typename T, uint32_t VEC_SIZE>\n __device__ __forceinline__ void operator()(vec_t<T, VEC_SIZE> val, int token_id) {\n if constexpr (HasAllReduceOut<Pattern>) {\n val.store(reinterpret_cast<T*>(m_params.allreduce_out) + m_access_id * VEC_SIZE);\n }\n if constexpr (HasResidual<Pattern>) {\n val = vec_add<T, VEC_SIZE>(val, m_residual_val);\n if constexpr (HasResidualOut<Pattern>) {\n val.store(reinterpret_cast<T*>(m_params.residual_out) + m_access_id * VEC_SIZE);\n }\n }\n if constexpr (HasRMSNorm<Pattern>) {\n val = rms_norm(val, m_gamma_val);\n if constexpr (HasNormOut<Pattern>) {\n val.store(reinterpret_cast<T*>(m_params.norm_out) + m_access_id * VEC_SIZE);\n }\n }\n\n#if CUDA_VERSION >= 12080\n if constexpr (GetQuantType<Pattern> == QuantType::kFP4) {\n // NOTE(Yingyi): might update later\n auto sf_out = utils::cvt_quant_to_fp4_get_sf_out_offset<uint32_t, 2>(\n std::nullopt /* batchIdx */, token_id, m_access_id_in_token, std::nullopt /* numRows */,\n m_params.hidden_dim, reinterpret_cast<uint32_t*>(m_params.scale_out), m_params.layout);\n reinterpret_cast<uint32_t*>(m_params.quant_out)[m_access_id] =\n utils::cvt_warp_fp16_to_fp4<T, VEC_SIZE>(val, m_scale_factor, sf_out);\n } else\n#endif\n if constexpr (GetQuantType<Pattern> == QuantType::kFP8) {\n using PackedQuantizedType = std::conditional_t<std::is_same_v<T, float>, float, float2>;\n PackedQuantizedType ret;\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n reinterpret_cast<__nv_fp8_e4m3*>(&ret)[i] = static_cast<__nv_fp8_e4m3>(\n static_cast<float>(reinterpret_cast<T*>(&val)[i]) * m_scale_factor);\n }\n reinterpret_cast<PackedQuantizedType*>(m_params.quant_out)[m_access_id] = ret;\n } else {\n static_assert(GetQuantType<Pattern> == QuantType::kNone, \"Invalid quant type\");\n }\n }\n\n protected:\n __device__ __forceinline__ vec_t<T, VEC_SIZE> rms_norm(vec_t<T, VEC_SIZE> const& residual,\n vec_t<T, VEC_SIZE> const& gamma) {\n __shared__ float s_val;\n vec_t<T, VEC_SIZE> norm_out;\n float acc = 0.f;\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n float v = static_cast<float>(reinterpret_cast<T const*>(&residual)[i]);\n acc += v * v;\n }\n utils::blockReduceSumV2<float, 1>(&acc);\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n namespace cg = cooperative_groups;\n cg::cluster_group cluster = cg::this_cluster();\n if (cluster.num_blocks() > 1) {\n if (threadIdx.x == 0) {\n s_val = acc;\n acc = 0.f;\n }\n cluster.sync();\n if (threadIdx.x == 0) {\n for (int i = 0; i < cluster.num_blocks(); ++i) {\n acc += *cluster.map_shared_rank(&s_val, i);\n }\n }\n cluster.sync();\n }\n#endif\n if (threadIdx.x == 0) {\n s_val = rsqrtf(acc / m_params.hidden_dim + m_params.rms_eps);\n }\n __syncthreads();\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n reinterpret_cast<T*>(&norm_out)[i] =\n static_cast<T>(static_cast<float>(reinterpret_cast<T const*>(&residual)[i]) * s_val *\n static_cast<float>(reinterpret_cast<T const*>(&gamma)[i]));\n }\n return norm_out;\n }\n\n private:\n AllReduceFusionParams<T> const& m_params;\n int m_access_id;\n int m_access_id_in_token;\n float m_scale_factor;\n vec_t<T, VEC_SIZE> m_residual_val;\n vec_t<T, VEC_SIZE> m_gamma_val;\n};\n\ntemplate <typename T>\nstruct neg_zero {\n static constexpr T value = -T(0);\n};\n\ntemplate <>\nstruct neg_zero<half> {\n static constexpr unsigned short neg_zero_bits = 0x8000U;\n static constexpr __half value = __half_raw{neg_zero_bits};\n};\n\ntemplate <>\nstruct neg_zero<nv_bfloat16> {\n static constexpr unsigned short neg_zero_bits = 0x8000U;\n static constexpr __nv_bfloat16 value = __nv_bfloat16_raw{neg_zero_bits};\n};\n\ntemplate <>\nstruct neg_zero<float> {\n static constexpr unsigned int neg_zero_bits = 0x80000000U;\n static constexpr float value = -0.0f;\n};\n\ntemplate <typename T>\n__device__ static constexpr T neg_zero_v = neg_zero<T>::value;\n\ntemplate <typename T>\n__device__ bool is_negative_zero(T) {\n return false;\n}\n\n// float specialization\ntemplate <>\n__device__ bool is_negative_zero<float>(float x) {\n return (__float_as_int(x) == 0x80000000);\n}\n\n// double specialization\ntemplate <>\n__device__ bool is_negative_zero<double>(double x) {\n return (__double_as_longlong(x) == 0x8000000000000000ULL);\n}\n\n// __half specialization\ntemplate <>\n__device__ bool is_negative_zero<__half>(__half x) {\n return (__half_as_ushort(x) == 0x8000);\n}\n\n// __nv_bfloat16 specialization\ntemplate <>\n__device__ bool is_negative_zero<__nv_bfloat16>(__nv_bfloat16 x) {\n return (__bfloat16_as_ushort(x) == 0x8000);\n}\n\ntemplate <typename T, uint32_t VEC_SIZE>\n__device__ __forceinline__ bool has_neg_zero(const vec_t<T, VEC_SIZE>& vec) {\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n if (is_negative_zero(vec[i])) {\n return true;\n }\n }\n return false;\n}\n\ntemplate <typename T, uint32_t VEC_SIZE>\n__device__ __forceinline__ void remove_neg_zero(vec_t<T, VEC_SIZE>& vec) {\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n vec[i] = (is_negative_zero(vec[i])) ? static_cast<T>(0.f) : vec[i];\n }\n}\n\ntemplate <typename T>\n__device__ __forceinline__ void set_neg_zero(T* addr) {\n vec_t<T, details::kBytesPerAccess / sizeof(T)> val;\n val.fill(neg_zero_v<T>);\n val.store_global_volatile(addr);\n}\n\ntemplate <typename T, uint32_t VEC_SIZE, int NRanks, bool Fp32Acc>\n__device__ __forceinline__ vec_t<T, VEC_SIZE> allreduce_sum(vec_t<T, VEC_SIZE>* vals) {\n if constexpr (Fp32Acc) {\n static_assert(!std::is_same_v<T, float>);\n float acc_f32[VEC_SIZE];\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n acc_f32[i] = static_cast<float>(reinterpret_cast<T*>(&vals[0])[i]);\n }\n#pragma unroll\n for (int r = 1; r < NRanks; ++r) {\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n acc_f32[i] += static_cast<float>(reinterpret_cast<T*>(&vals[r])[i]);\n }\n }\n vec_t<T, VEC_SIZE> acc;\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n acc[i] = static_cast<T>(acc_f32[i]);\n }\n return acc;\n } else {\n vec_t<T, VEC_SIZE> acc = vals[0];\n#pragma unroll\n for (int r = 1; r < NRanks; ++r) {\n acc = vec_add<T, VEC_SIZE>(acc, vals[r]);\n }\n return acc;\n }\n}\n\ntemplate <typename T>\nclass IndexHelper {\n public:\n __device__ __forceinline__ IndexHelper(AllReduceFusionParams<T> const& params) {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n namespace cg = cooperative_groups;\n cg::cluster_group cluster = cg::this_cluster();\n cg::grid_group grid = cg::this_grid();\n token_id = grid.cluster_rank();\n access_id_in_token = cluster.thread_rank();\n token_stride = grid.num_clusters();\n#else\n token_id = blockIdx.x;\n access_id_in_token = threadIdx.x;\n token_stride = gridDim.x;\n#endif\n access_id = token_id * params.hidden_dim / VEC_SIZE + access_id_in_token;\n access_stride = token_stride * params.hidden_dim / VEC_SIZE;\n tot_access = params.size / VEC_SIZE;\n }\n\n int token_id;\n int access_id_in_token;\n int token_stride;\n int access_id;\n int access_stride;\n int tot_access;\n};\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc,\n bool TriggerCompletionAtEnd = true>\n__global__ void allreduce_fusion_kernel_oneshot_lamport(AllReduceFusionParams<T> params) {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n IndexHelper<T> index_helper(params);\n int token_id = index_helper.token_id;\n int access_id_in_token = index_helper.access_id_in_token;\n int token_stride = index_helper.token_stride;\n int access_id = index_helper.access_id;\n int access_stride = index_helper.access_stride;\n int tot_access = index_helper.tot_access;\n vec_t<T, VEC_SIZE> clear_vec;\n clear_vec.fill(neg_zero_v<T>);\n FusedOp<Pattern, T> fused_op(params, access_id, access_id_in_token);\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n cudaGridDependencySynchronize();\n if constexpr (!TriggerCompletionAtEnd) {\n cudaTriggerProgrammaticLaunchCompletion();\n }\n#endif\n LamportComm<NRanks> comm(params.workspace, params.rank);\n int clear_access = comm.clear_size / VEC_SIZE;\n\n for (int idx = access_id; idx < tot_access; idx += access_stride) {\n vec_t<T, VEC_SIZE> val;\n val.load(reinterpret_cast<T*>(params.allreduce_in) + idx * VEC_SIZE);\n remove_neg_zero<T, VEC_SIZE>(val);\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n // Push data to other ranks\n val.store(reinterpret_cast<T*>(comm.data_bufs[r]) +\n (params.rank * tot_access + idx) * VEC_SIZE);\n }\n }\n for (int idx = access_id; idx < clear_access; idx += access_stride) {\n // Clear comm buffer that previous kernel used\n clear_vec.store(reinterpret_cast<T*>(comm.clear_buf) + idx * VEC_SIZE);\n }\n\n for (int idx = access_id, tidx = token_id; idx < tot_access;\n idx += access_stride, tidx += token_stride) {\n fused_op.update(idx);\n vec_t<T, VEC_SIZE> vals[NRanks];\n bool done = false;\n\n while (!done) {\n done = true;\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n // LDG.128 from local rank\n vals[r].load_global_volatile(reinterpret_cast<T*>(comm.data_bufs[params.rank]) +\n (r * tot_access + idx) * VEC_SIZE);\n done &= !has_neg_zero<T, VEC_SIZE>(vals[r]);\n }\n }\n vec_t<T, VEC_SIZE> sum_val = allreduce_sum<T, VEC_SIZE, NRanks, Fp32Acc>(vals);\n fused_op(sum_val, tidx);\n }\n\n comm.update(params.size * NRanks);\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if constexpr (TriggerCompletionAtEnd) {\n cudaTriggerProgrammaticLaunchCompletion();\n }\n#endif\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc>\n__global__ void allreduce_fusion_kernel_twoshot_sync(AllReduceFusionParams<T> params,\n std::array<int, NRanks> begin_tokens,\n std::array<int, NRanks> token_num_per_ranks) {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n IndexHelper<T> index_helper(params);\n int token_id = index_helper.token_id;\n int access_id_in_token = index_helper.access_id_in_token;\n int token_stride = index_helper.token_stride;\n int access_id = index_helper.access_id;\n int access_stride = index_helper.access_stride;\n int tot_access = index_helper.tot_access;\n FusedOp<Pattern, T> fused_op(params, access_id, access_id_in_token);\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n cudaGridDependencySynchronize();\n#endif\n SyncComm<NRanks> comm(params.workspace);\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n int comm_access_id = access_id + begin_tokens[r] * params.hidden_dim / VEC_SIZE;\n int comm_tot_access = (begin_tokens[r] + token_num_per_ranks[r]) * params.hidden_dim / VEC_SIZE;\n for (int idx = comm_access_id; idx < comm_tot_access; idx += access_stride) {\n reinterpret_cast<float4*>(comm.comm_bufs[params.rank])[idx] =\n reinterpret_cast<float4*>(params.allreduce_in)[idx];\n }\n }\n Barrier<NRanks> barrier(params.rank, comm);\n barrier.sync();\n int comm_access_id = access_id + begin_tokens[params.rank] * params.hidden_dim / VEC_SIZE;\n int comm_tot_access =\n (begin_tokens[params.rank] + token_num_per_ranks[params.rank]) * params.hidden_dim / VEC_SIZE;\n for (int idx = comm_access_id; idx < comm_tot_access; idx += access_stride) {\n vec_t<T, VEC_SIZE> vals[NRanks];\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n vals[r].load(reinterpret_cast<T*>(comm.comm_bufs[r]) + idx * VEC_SIZE);\n }\n vec_t<T, VEC_SIZE> sum_val = allreduce_sum<T, VEC_SIZE, NRanks, Fp32Acc>(vals);\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n sum_val.store(reinterpret_cast<T*>(comm.comm_bufs[r]) + (tot_access + idx) * VEC_SIZE);\n }\n }\n barrier.sync();\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n int comm_access_id = access_id + begin_tokens[r] * params.hidden_dim / VEC_SIZE;\n int comm_token_id = token_id + begin_tokens[r];\n int comm_tot_access = (begin_tokens[r] + token_num_per_ranks[r]) * params.hidden_dim / VEC_SIZE;\n for (int idx = comm_access_id, tidx = comm_token_id; idx < comm_tot_access;\n idx += access_stride, tidx += token_stride) {\n fused_op.update(idx);\n vec_t<T, VEC_SIZE> sum_val;\n sum_val.load(reinterpret_cast<T*>(comm.comm_bufs[params.rank]) +\n (tot_access + idx) * VEC_SIZE);\n fused_op(sum_val, tidx);\n }\n }\n comm.update(barrier.m_flag_value);\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n}\n\nint get_sm_count() {\n static int sm_count = 0;\n if (sm_count == 0) {\n int device_id;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&device_id));\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&sm_count, cudaDevAttrMultiProcessorCount, device_id));\n }\n return sm_count;\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc,\n bool TriggerCompletionAtEnd = true>\ncudaError_t launch_oneshot_lamport(AllReduceFusionParams<T> const& params,\n cudaLaunchConfig_t& cfg) {\n FLASHINFER_CUDA_CALL(cudaLaunchKernelEx(\n &cfg,\n allreduce_fusion_kernel_oneshot_lamport<Pattern, T, NRanks, Fp32Acc, TriggerCompletionAtEnd>,\n params));\n return cudaSuccess;\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc,\n bool TriggerCompletionAtEnd = true>\nint get_registers_per_thread_oneshot() {\n auto kernel =\n allreduce_fusion_kernel_oneshot_lamport<Pattern, T, NRanks, Fp32Acc, TriggerCompletionAtEnd>;\n cudaFuncAttributes attr;\n cudaFuncGetAttributes(&attr, kernel);\n return attr.numRegs;\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc>\ncudaError_t launch_twoshot_sync(AllReduceFusionParams<T> const& params, cudaLaunchConfig_t& cfg,\n std::array<int, NRanks> begin_tokens,\n std::array<int, NRanks> token_num_per_ranks) {\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernelEx(&cfg, allreduce_fusion_kernel_twoshot_sync<Pattern, T, NRanks, Fp32Acc>,\n params, begin_tokens, token_num_per_ranks));\n return cudaSuccess;\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc>\nint get_registers_per_thread_twoshot() {\n auto kernel = allreduce_fusion_kernel_twoshot_sync<Pattern, T, NRanks, Fp32Acc>;\n cudaFuncAttributes attr;\n cudaFuncGetAttributes(&attr, kernel);\n return attr.numRegs;\n}\n\nbool use_oneshot(int token_num) { return token_num <= details::kOneShotMaxToken; }\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc>\ncudaError_t allreduce_fusion_kernel_launcher(AllReduceFusionParams<T> const& params,\n bool launch_with_pdl) {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n FLASHINFER_CHECK(params.size % params.hidden_dim == 0, \"params.size % params.hidden_dim != 0\");\n FLASHINFER_CHECK(params.hidden_dim % VEC_SIZE == 0, \"params.hidden_dim % VEC_SIZE != 0\");\n static int SM = utils::getSMVersion();\n int token_num = params.size / params.hidden_dim;\n bool oneshot = params.use_oneshot;\n int cluster_num = token_num;\n std::array<int, NRanks> begin_tokens, token_num_per_ranks;\n if (!oneshot) {\n int remaining_token = token_num % NRanks;\n int token_num_per_rank = token_num / NRanks;\n cluster_num = token_num_per_rank;\n if (remaining_token) {\n cluster_num++;\n }\n for (int r = 0; r < NRanks; ++r) {\n begin_tokens[r] = r * token_num_per_rank + (remaining_token > r ? r : remaining_token);\n token_num_per_ranks[r] = token_num_per_rank + (remaining_token > r ? 1 : 0);\n }\n }\n int threads_per_token = params.hidden_dim / VEC_SIZE;\n int cluster_size;\n if (SM >= 90) {\n cluster_size = 8;\n } else {\n cluster_size = 1;\n }\n while (threads_per_token % cluster_size != 0 && cluster_size > 1) {\n cluster_size /= 2;\n }\n int threads_per_block = threads_per_token / cluster_size;\n while (threads_per_block < 128 && cluster_size >= 2) {\n threads_per_block *= 2;\n cluster_size /= 2;\n }\n int sm_count = get_sm_count();\n int registers_per_thread;\n if (oneshot) {\n if (params.trigger_completion_at_end) {\n registers_per_thread = get_registers_per_thread_oneshot<Pattern, T, NRanks, Fp32Acc, true>();\n } else {\n registers_per_thread = get_registers_per_thread_oneshot<Pattern, T, NRanks, Fp32Acc, false>();\n }\n } else {\n registers_per_thread = get_registers_per_thread_twoshot<Pattern, T, NRanks, Fp32Acc>();\n }\n static int max_registers = -1;\n if (max_registers < 0) {\n max_registers = utils::getSMRegisters();\n }\n int max_threads_per_block = min(max_registers / registers_per_thread, 1024);\n while (cluster_num * cluster_size > sm_count && cluster_size > 1 &&\n threads_per_block <= max_threads_per_block / 2) {\n threads_per_block *= 2;\n cluster_size /= 2;\n }\n FLASHINFER_CHECK(oneshot || threads_per_block >= params.nranks,\n \"not oneshot, or threads_per_block < nranks\");\n int block_size = threads_per_block;\n FLASHINFER_CHECK(block_size <= 1024 && cluster_size > 0,\n \"block_size > 1024 or cluster_size <= 0\");\n int grid_size = (std::min(sm_count, cluster_num * cluster_size) / cluster_size) * cluster_size;\n cudaLaunchConfig_t cfg;\n cudaLaunchAttribute attribute[2];\n cfg.gridDim = grid_size;\n cfg.blockDim = block_size;\n cfg.dynamicSmemBytes = 0;\n cfg.stream = params.stream;\n attribute[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attribute[0].val.programmaticStreamSerializationAllowed = launch_with_pdl ? 1 : 0;\n attribute[1].id = cudaLaunchAttributeClusterDimension;\n attribute[1].val.clusterDim.x = cluster_size;\n attribute[1].val.clusterDim.y = 1;\n attribute[1].val.clusterDim.z = 1;\n cfg.attrs = attribute;\n cfg.numAttrs = SM >= 90 ? 2 : 0;\n if (oneshot) {\n bool trigger_completion_at_end = params.trigger_completion_at_end;\n if (trigger_completion_at_end) {\n FLASHINFER_CUDA_CALL(\n (launch_oneshot_lamport<Pattern, T, NRanks, Fp32Acc, true>(params, cfg)));\n } else {\n FLASHINFER_CUDA_CALL(\n (launch_oneshot_lamport<Pattern, T, NRanks, Fp32Acc, false>(params, cfg)));\n }\n } else {\n FLASHINFER_CUDA_CALL((launch_twoshot_sync<Pattern, T, NRanks, Fp32Acc>(\n params, cfg, begin_tokens, token_num_per_ranks)));\n }\n return cudaSuccess;\n}\n\ntemplate <typename T>\ncudaError_t allreduce_fusion_op(AllReduceFusionParams<T> const& params, bool launch_with_pdl,\n bool fp32_acc) {\n#define DISPATCH_ACC_TYPE(T, Pattern, NRanks) \\\n if constexpr (std::is_same_v<T, float>) { \\\n return allreduce_fusion_kernel_launcher<Pattern, T, NRanks, false>(params, launch_with_pdl); \\\n } else { \\\n if (fp32_acc) { \\\n return allreduce_fusion_kernel_launcher<Pattern, T, NRanks, true>(params, launch_with_pdl); \\\n } else { \\\n return allreduce_fusion_kernel_launcher<Pattern, T, NRanks, false>(params, launch_with_pdl); \\\n } \\\n }\n\n#define DISPATCH_PATTERN(T, NRanks) \\\n switch (params.pattern) { \\\n case AllReduceFusionPattern::kAllReduce: \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kAllReduce, NRanks); \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNorm: \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNorm, NRanks); \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNormFP8Quant: \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNormFP8Quant, NRanks); \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNormFP4Quant: \\\n if constexpr (!std::is_same_v<T, float> && CUDA_VERSION >= 12080) { \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNormFP4Quant, NRanks); \\\n } else { \\\n FLASHINFER_CHECK(CUDA_VERSION >= 12080, \"FP4Quant requires CUDA 12.8 or higher\"); \\\n FLASHINFER_CHECK(false, \"FP4Quant pattern cannot work with DType=float\"); \\\n } \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNormOutFP8Quant: \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNormOutFP8Quant, NRanks); \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNormOutFP4Quant: \\\n if constexpr (!std::is_same_v<T, float> && CUDA_VERSION >= 12080) { \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNormOutFP4Quant, NRanks); \\\n } else { \\\n FLASHINFER_CHECK(CUDA_VERSION >= 12080, \"OutFP4Quant requires CUDA 12.8 or higher\"); \\\n FLASHINFER_CHECK(false, \"OutFP4Quant pattern cannot work with DType=float\"); \\\n } \\\n break; \\\n default: \\\n FLASHINFER_CHECK(false, \"Unsupported allreduce fusion pattern\"); \\\n }\n\n switch (params.nranks) {\n case 2:\n DISPATCH_PATTERN(T, 2);\n break;\n case 4:\n DISPATCH_PATTERN(T, 4);\n break;\n case 8:\n DISPATCH_PATTERN(T, 8);\n break;\n case 16:\n DISPATCH_PATTERN(T, 16);\n break;\n default:\n FLASHINFER_ERROR(\n \"allreduce_fusion_kernel: unsupported ranks number! Supported ranks: 2, 4, 8, 16.\");\n }\n}\n\n} // namespace trtllm_allreduce_fusion\n\n} // namespace flashinfer\n"},"after_code":{"kind":"string","value":"#include <cooperative_groups.h>\n#include <cuda.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n\n#if CUDA_VERSION >= 12080\n#include <cuda_fp4.h>\n#endif\n\n#include <cuda/std/optional>\n#include <tuple>\n#include <type_traits>\n\n#include \"../exception.h\"\n#include \"../fp4_layout.cuh\"\n#include \"../logging.h\"\n#include \"../utils.cuh\"\n#include \"../vec_dtypes.cuh\"\n\nnamespace flashinfer {\n\nnamespace trtllm_allreduce_fusion {\n\nusing flashinfer::QuantizationSFLayout;\n\nnamespace details {\n\nstatic constexpr int CVT_FP4_ELTS_PER_THREAD = 8;\nstatic constexpr int CVT_FP4_SF_VEC_SIZE = 16;\nstatic constexpr int kBytesPerAccess = 16;\nstatic constexpr int kOneShotMaxToken = 128;\nstatic constexpr int kBarrierFlagCount = 256;\n\n} // namespace details\n\nnamespace maths {\n// // ============================== Cast ==============================\ntemplate <typename T_OUT, typename T_IN>\n__device__ inline T_OUT cuda_cast(T_IN val) {\n return val;\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, int2>(int2 val) {\n return make_float2(val.x, val.y);\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, float>(float val) {\n return make_float2(val, val);\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, half2>(half2 val) {\n return __half22float2(val);\n}\n\ntemplate <>\n__device__ inline half2 cuda_cast<half2, float2>(float2 val) {\n return __float22half2_rn(val);\n}\n\ntemplate <>\n__device__ inline half2 cuda_cast<half2, float>(float val) {\n return __float2half2_rn(val);\n}\n\ntemplate <>\n__device__ inline half2 cuda_cast<half2, half>(half val) {\n return __half2half2(val);\n}\n\ntemplate <>\n__device__ inline int8_t cuda_cast<int8_t, half>(half val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n union {\n half fp16;\n int16_t int16_in;\n };\n\n fp16 = val;\n asm volatile(\"cvt.rni.sat.s8.f16 %0, %1;\" : \"=h\"(int16) : \"h\"(int16_in));\n return int8[0];\n}\n\ntemplate <>\n__device__ inline int16_t cuda_cast<int16_t, half2>(half2 val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int8[0] = cuda_cast<int8_t>(val.x);\n int8[1] = cuda_cast<int8_t>(val.y);\n return int16;\n}\n\ntemplate <>\n__device__ inline int8_t cuda_cast<int8_t, float>(float val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n asm volatile(\"cvt.rni.sat.s8.f32 %0, %1;\" : \"=h\"(int16) : \"f\"(val));\n return int8[0];\n}\n\ntemplate <>\n__device__ inline int16_t cuda_cast<int16_t, float2>(float2 val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int8[0] = cuda_cast<int8_t>(val.x);\n int8[1] = cuda_cast<int8_t>(val.y);\n return int16;\n}\n\ntemplate <>\n__device__ inline half2 cuda_cast<half2, int16_t>(int16_t val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int16 = val;\n return make_half2(int8[0], int8[1]);\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, int16_t>(int16_t val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int16 = val;\n return make_float2(int8[0], int8[1]);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_cast(int32_t val) {\n return static_cast<float>(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_cast(int8_t val) {\n return static_cast<float>(val);\n}\n\ntemplate <>\n__device__ inline int8_t cuda_cast(__nv_bfloat16 val) {\n return static_cast<float>(val);\n}\n\ntemplate <>\n__device__ inline float cuda_cast<float, __nv_bfloat16>(__nv_bfloat16 val) {\n return __bfloat162float(val);\n}\n\ninline __device__ float2 bf1622float2(const __nv_bfloat162 val) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800\n float2 f_val;\n f_val.x = __low2float(val);\n f_val.y = __high2float(val);\n return f_val;\n#else\n return __bfloat1622float2(val);\n#endif\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, __nv_bfloat162>(__nv_bfloat162 val) {\n return bf1622float2(val);\n}\n\ntemplate <>\n__device__ inline half cuda_cast<half, __nv_bfloat16>(__nv_bfloat16 val) {\n return __float2half(__bfloat162float(val));\n}\n\ninline __device__ int16_t bf1622int16(__nv_bfloat162 val) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800\n float2 f_val;\n f_val.x = max(min(__low2float(val), 127.f), -128.f);\n f_val.y = max(min(__high2float(val), 127.f), -128.f);\n\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int8[0] = static_cast<int8_t>(static_cast<short>(f_val.x));\n int8[1] = static_cast<int8_t>(static_cast<short>(f_val.y));\n return int16;\n#else\n val = __hmin2(val, make_bfloat162(127., 127.));\n val = __hmax2(val, make_bfloat162(-128., -128.));\n\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int8[0] = static_cast<int8_t>(static_cast<short>(val.x));\n int8[1] = static_cast<int8_t>(static_cast<short>(val.y));\n return int16;\n#endif\n}\n\ntemplate <>\n__device__ inline int16_t cuda_cast<int16_t, __nv_bfloat162>(__nv_bfloat162 val) {\n return bf1622int16(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_cast<__nv_bfloat16, float>(float val) {\n return __float2bfloat16(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_cast<__nv_bfloat16, half>(half val) {\n return __float2bfloat16(__half2float(val));\n}\n\ninline __device__ __nv_bfloat162 bf162bf162(const __nv_bfloat16 val) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800\n __nv_bfloat162 val2;\n val2.x = val;\n val2.y = val;\n return val2;\n#else\n return __bfloat162bfloat162(val);\n#endif\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, __nv_bfloat16>(__nv_bfloat16 val) {\n return bf162bf162(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, float>(float val) {\n return __float2bfloat162_rn(val);\n}\n\ninline __device__ __nv_bfloat162 float22bf162(const float2 val) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800\n return __floats2bfloat162_rn(val.x, val.y);\n#else\n return __float22bfloat162_rn(val);\n#endif\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, float2>(float2 val) {\n return float22bf162(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, int16_t>(int16_t val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int16 = val;\n __nv_bfloat162 res;\n res.x = cuda_cast<__nv_bfloat16>(int8[0]);\n res.y = cuda_cast<__nv_bfloat16>(int8[1]);\n return res;\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, half2>(half2 val) {\n return float22bf162(__half22float2(val));\n}\n\n// // ============================== Abs ==============================\ntemplate <typename T>\n__device__ inline T cuda_abs(T val) {\n assert(false);\n return {};\n}\n\ntemplate <>\n__device__ inline float cuda_abs(float val) {\n return fabs(val);\n}\n\ntemplate <>\n__device__ inline float2 cuda_abs(float2 val) {\n return make_float2(fabs(val.x), fabs(val.y));\n}\n\ntemplate <>\n__device__ inline half cuda_abs(half val) {\n return __habs(val);\n}\n\ntemplate <>\n__device__ inline half2 cuda_abs(half2 val) {\n return __habs2(val);\n}\n\n#if __CUDA_ARCH__ >= 800 || !defined(__CUDA_ARCH__)\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_abs(__nv_bfloat16 val) {\n return __habs(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_abs(__nv_bfloat162 val) {\n return __habs2(val);\n}\n#endif\n\n// // ============================== Max ==============================\ntemplate <typename To, typename Ti>\n__device__ inline To cuda_max(Ti val) {\n return cuda_cast<To>(val);\n};\n\ntemplate <>\n__device__ inline float cuda_max(float2 val) {\n return fmaxf(val.x, val.y);\n}\n\ntemplate <>\n__device__ inline half cuda_max(half2 val) {\n return __hmax(val.x, val.y);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_max(__nv_bfloat162 val) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n return __hmax(val.x, val.y);\n#else\n assert(0);\n asm volatile(\"brkpt;\\n\" ::);\n return __nv_bfloat16(0);\n#endif\n}\n\n// Binary maximum: compute the max of two values.\ntemplate <typename T>\n__device__ inline T cuda_max(T val1, T val2) {\n return (val1 > val2) ? val1 : val2;\n}\n\ntemplate <>\n__device__ inline float2 cuda_max(float2 val1, float2 val2) {\n float2 out;\n out.x = fmaxf(val1.x, val2.x);\n out.y = fmaxf(val1.y, val2.y);\n return out;\n}\n\ntemplate <>\n__device__ inline half2 cuda_max(half2 val1, half2 val2) {\n return __hmax2(val1, val2);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_max(__nv_bfloat162 val1, __nv_bfloat162 val2) {\n return __hmax2(val1, val2);\n}\n\n// // ============================== Reciprocal ==============================\n// Fast reciprocal.\ninline __device__ float reciprocal_approximate_ftz(float a) {\n float b;\n asm volatile(\"rcp.approx.ftz.f32 %0, %1;\\n\" : \"=f\"(b) : \"f\"(a));\n return b;\n}\n} // namespace maths\n\nnamespace utils {\n\n#define FINAL_MASK 0xffffffff\n\ntemplate <typename T, int NUM>\n__inline__ __device__ T warpReduceSumV2(T* val) {\n#pragma unroll\n for (int i = 0; i < NUM; i++) {\n#pragma unroll\n for (int mask = 16; mask > 0; mask >>= 1)\n val[i] += __shfl_xor_sync(FINAL_MASK, val[i], mask, 32);\n }\n return (T)(0.0f);\n}\n\ntemplate <typename T, int NUM>\n__inline__ __device__ T blockReduceSumV2(T* val) {\n static __shared__ T shared[NUM][33];\n int lane = threadIdx.x & 0x1f;\n int wid = threadIdx.x >> 5;\n\n warpReduceSumV2<T, NUM>(val);\n\n if (lane == 0) {\n#pragma unroll\n for (int i = 0; i < NUM; i++) {\n shared[i][wid] = val[i];\n }\n }\n\n __syncthreads();\n\n bool is_mask = threadIdx.x < (blockDim.x / 32.f);\n#pragma unroll\n for (int i = 0; i < NUM; i++) {\n val[i] = is_mask ? shared[i][lane] : (T)(0.0f);\n }\n warpReduceSumV2<T, NUM>(val);\n return (T)0.0f;\n}\n\ninline int getSMVersion() {\n int device{-1};\n FLASHINFER_CUDA_CALL(cudaGetDevice(&device));\n int sm_major = 0;\n int sm_minor = 0;\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&sm_major, cudaDevAttrComputeCapabilityMajor, device));\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&sm_minor, cudaDevAttrComputeCapabilityMinor, device));\n return sm_major * 10 + sm_minor;\n}\n\ninline int getSMRegisters() {\n int device{-1};\n FLASHINFER_CUDA_CALL(cudaGetDevice(&device));\n int regs_per_block;\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(®s_per_block, cudaDevAttrMaxRegistersPerBlock, device));\n return regs_per_block;\n}\n\ninline __device__ int64_t get_sf_out_offset_128x4(std::optional<int> batchIdx, int mIdx, int kIdx,\n std::optional<int> numRows, int numCols) {\n // SF layout [numMTiles, numKTiles, 32 (mTile), 4 (mTile), 4(kTile)]\n // --> index [mTileIdx, kTileIdx, outerMIdx, innerMIdx, innerKIdx]\n\n // batched tensor\n // SF layout [numBTiles, numMTiles, numKTiles, 32 (mTile), 4 (mTile), 4(kTile)]\n // --> index [bTileIdx, mTileIdx, kTileIdx, outerMIdx, innerMIdx, innerKIdx]\n\n int32_t innerKIdx = (kIdx % 4);\n int64_t innerKStride = 1;\n\n int32_t innerMIdx = (mIdx % (32 * 4)) / 32;\n int64_t innerMStride = 4 * innerKStride; // 4\n\n // M tile layout [32, 4] is column-major.\n int32_t outerMIdx = (mIdx % 32);\n int64_t outerMStride = 4 * innerMStride; // 16\n\n int32_t kTileIdx = (kIdx / 4);\n int64_t kTileStride = 32 * outerMStride; // 512\n\n // SF vector size 16. We round the \"numCols\" up to a multiple of 64.\n int factor = details::CVT_FP4_SF_VEC_SIZE * 4;\n int32_t numKTiles = (numCols + factor - 1) / factor;\n int32_t mTileIdx = mIdx / (32 * 4);\n int64_t mTileStride = numKTiles * kTileStride;\n\n // Each SF block has 128 rows so pad rows to the multiple of 128.\n int32_t numMTiles = (numRows.value_or(0) + 128 - 1) / 128;\n int64_t bTileStride = numMTiles * mTileStride;\n\n // Compute the global offset.\n int64_t SFOffset = batchIdx.value_or(0) * bTileStride + mTileIdx * mTileStride +\n kTileIdx * kTileStride + outerMIdx * outerMStride + innerMIdx * innerMStride +\n innerKIdx * innerKStride;\n\n return SFOffset;\n}\n\ntemplate <class SFType, int CVT_FP4_NUM_THREADS_PER_SF>\n__device__ uint8_t* cvt_quant_to_fp4_get_sf_out_offset(std::optional<int> batchIdx, int rowIdx,\n int colIdx, std::optional<int> numRows,\n int numCols, SFType* SFout,\n QuantizationSFLayout layout) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n static_assert(CVT_FP4_NUM_THREADS_PER_SF == 1 || CVT_FP4_NUM_THREADS_PER_SF == 2);\n\n // One pair of threads write one SF to global memory.\n // TODO: stage through smem for packed STG.32\n // is it better than STG.8 from 4 threads ?\n if (threadIdx.x % CVT_FP4_NUM_THREADS_PER_SF == 0) {\n if (layout == QuantizationSFLayout::SWIZZLED_128x4) {\n // SF vector index (16 elements share one SF in the K dimension).\n // numRows and numCols are unpadded.\n int32_t kIdx = colIdx / CVT_FP4_NUM_THREADS_PER_SF;\n int32_t mIdx = rowIdx;\n\n auto SFOffset = get_sf_out_offset_128x4(batchIdx, mIdx, kIdx, numRows, numCols);\n return reinterpret_cast<uint8_t*>(SFout) + SFOffset;\n } else if (layout == QuantizationSFLayout::LINEAR) {\n // Linear row-major layout, no padding required.\n int32_t KTileIdx = colIdx / CVT_FP4_NUM_THREADS_PER_SF;\n\n int32_t numKTiles = numCols / details::CVT_FP4_SF_VEC_SIZE;\n int64_t mTileStride = numKTiles;\n\n int64_t BTileStride = numRows.value_or(0) * mTileStride;\n\n int64_t SFOffset = batchIdx.value_or(0) * BTileStride + rowIdx * mTileStride + KTileIdx;\n return reinterpret_cast<uint8_t*>(SFout) + SFOffset;\n } else {\n return nullptr;\n }\n }\n#endif\n return nullptr;\n}\n\n__forceinline__ __device__ uint32_t pack_bytes(uint8_t c0, uint8_t c1, uint8_t c2, uint8_t c3) {\n uint32_t val0 = c0;\n uint32_t val1 = c1;\n uint32_t val2 = c2;\n uint32_t val3 = c3;\n\n return (val3 << 24) | (val2 << 16) | (val1 << 8) | val0;\n}\n\n// Convert single float2 pair to e2m1 (2 float32 -> 2 e2m1, returns uint8_t)\n// Optimization: allows pipelined processing to reduce register usage\n// Note: \"=r\" constraint always allocates 32-bit register regardless of variable type\ninline __device__ uint8_t fp32_pair_to_e2m1(float2 pair) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n uint32_t val32;\n asm volatile(\n \"{\\n\"\n \".reg .b8 byte0;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte0, %2, %1;\\n\"\n \"mov.b32 %0, {byte0, 0, 0, 0};\\n\"\n \"}\"\n : \"=r\"(val32)\n : \"f\"(pair.x), \"f\"(pair.y));\n return static_cast<uint8_t>(val32 & 0xFF); // Extract low 8 bits\n#else\n return 0;\n#endif\n}\n\n#if CUDA_VERSION >= 12080\n// Convert 8 float32 values into 8 e2m1 values (represented as one uint32_t).\n// NOTE: bypass sm_100 requirement by __nv_cvt_float2_to_fp4x2\ninline __device__ uint32_t fp32_vec_to_e2m1(float (&array)[8]) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n uint32_t val;\n asm volatile(\n \"{\\n\"\n \".reg .b8 byte0;\\n\"\n \".reg .b8 byte1;\\n\"\n \".reg .b8 byte2;\\n\"\n \".reg .b8 byte3;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte0, %2, %1;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte1, %4, %3;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte2, %6, %5;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte3, %8, %7;\\n\"\n \"mov.b32 %0, {byte0, byte1, byte2, byte3};\\n\"\n \"}\"\n : \"=r\"(val)\n : \"f\"(array[0]), \"f\"(array[1]), \"f\"(array[2]), \"f\"(array[3]), \"f\"(array[4]), \"f\"(array[5]),\n \"f\"(array[6]), \"f\"(array[7]));\n return val;\n#else\n uint32_t val;\n __nv_fp4x2_storage_t vals[4];\n#pragma unroll\n for (int i = 0; i < 4; i++) {\n vals[i] = __nv_cvt_float2_to_fp4x2(*(((float2*)array) + i), __NV_E2M1, cudaRoundNearest);\n }\n val = pack_bytes(vals[0], vals[1], vals[2], vals[3]);\n return val;\n#endif\n}\n\n// Convert 4 float2 values into 8 e2m1 values (represented as one uint32_t).\ninline __device__ uint32_t fp32_vec_to_e2m1(float2 (&array)[4]) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n uint32_t val;\n asm volatile(\n \"{\\n\"\n \".reg .b8 byte0;\\n\"\n \".reg .b8 byte1;\\n\"\n \".reg .b8 byte2;\\n\"\n \".reg .b8 byte3;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte0, %2, %1;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte1, %4, %3;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte2, %6, %5;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte3, %8, %7;\\n\"\n \"mov.b32 %0, {byte0, byte1, byte2, byte3};\\n\"\n \"}\"\n : \"=r\"(val)\n : \"f\"(array[0].x), \"f\"(array[0].y), \"f\"(array[1].x), \"f\"(array[1].y), \"f\"(array[2].x),\n \"f\"(array[2].y), \"f\"(array[3].x), \"f\"(array[3].y));\n return val;\n#else\n uint32_t val;\n __nv_fp4x2_storage_t vals[4];\n#pragma unroll\n for (int i = 0; i < 4; i++) {\n vals[i] = __nv_cvt_float2_to_fp4x2(array[i], __NV_E2M1, cudaRoundNearest);\n }\n val = pack_bytes(vals[0], vals[1], vals[2], vals[3]);\n return val;\n#endif\n}\n\n// Quantizes the provided PackedVec into the uint32_t output\ntemplate <typename T, uint32_t VEC_SIZE, bool UE8M0_SF = false>\n__device__ uint32_t cvt_warp_fp16_to_fp4(vec_t<T, VEC_SIZE>& vec, float SFScaleVal,\n uint8_t* SFout) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n // Pre-compute constant: reciprocal of 6.0 (maximum value of e2m1)\n static constexpr float RECIPROCAL_6 = 1.0f / 6.0f;\n\n // Get absolute maximum values among the local 8 values.\n auto localMax = maths::cuda_abs(get_vec2_element(vec, 0));\n\n#pragma unroll\n for (int i = 1; i < details::CVT_FP4_ELTS_PER_THREAD / 2; i++) {\n localMax = maths::cuda_max(localMax, maths::cuda_abs(get_vec2_element(vec, i)));\n }\n\n // Get the absolute maximum among all 16 values (two threads).\n localMax = maths::cuda_max(__shfl_xor_sync(uint32_t(-1), localMax, 1), localMax);\n // Get the final absolute maximum values.\n // Optimization: compute vecMax and reuse localMax space (localMax no longer needed)\n float vecMax = float(maths::cuda_max(localMax.x, localMax.y));\n\n // Get the SF (max value of the vector / max value of e2m1).\n // maximum value of e2m1 = 6.0.\n // Optimization: compute quantized SF directly, avoid storing intermediate SFValue\n uint8_t fp8SFVal;\n float quantized_sf;\n if constexpr (UE8M0_SF) {\n#if (__CUDACC_VER_MAJOR__ * 1000 + __CUDACC_VER_MINOR__ * 10 >= 12080)\n __nv_fp8_e8m0 tmp;\n float sf_value = SFScaleVal * (vecMax * RECIPROCAL_6);\n tmp.__x = __nv_cvt_float_to_e8m0(sf_value, __NV_SATFINITE, cudaRoundPosInf);\n quantized_sf = static_cast<float>(tmp);\n fp8SFVal = tmp.__x;\n#else\n#error \"FP8 E8M0 support requires CUDA 12.8 or newer.\"\n#endif\n } else {\n // Here SFValue is always positive, so E4M3 is the same as UE4M3.\n __nv_fp8_e4m3 tmp = __nv_fp8_e4m3(SFScaleVal * (vecMax * RECIPROCAL_6));\n fp8SFVal = tmp.__x;\n quantized_sf = static_cast<float>(tmp);\n }\n // Get the output scale directly (optimization: avoid storing intermediate SFValue)\n // Recipe: final_scale = reciprocal(fp32(fp8(SFValue * SFScaleVal))) * reciprocal(SFScaleVal))\n // Optimization: mathematically equivalent to SFScaleVal / quantized_sf, but more efficient\n // (reduces 1 reciprocal call and 1 multiply operation)\n float outputScale = quantized_sf != 0 ? SFScaleVal / quantized_sf : 0.0f;\n\n if (SFout) {\n // Write the SF to global memory (STG.8).\n *SFout = fp8SFVal;\n }\n\n // Convert the input to float and quantize (pipelined to reduce register usage).\n // Optimization: use single float2 instead of array to reduce register pressure from 32 bytes to 8\n // bytes\n uint32_t e2m1Vec = 0;\n\n#pragma unroll\n for (int i = 0; i < details::CVT_FP4_ELTS_PER_THREAD / 2; i++) {\n // Reuse single float2 register instead of array\n float2 fp2Val;\n if constexpr (std::is_same_v<T, half>) {\n fp2Val = __half22float2(get_vec2_element(vec, i));\n } else {\n fp2Val = __bfloat1622float2(get_vec2_element(vec, i));\n }\n fp2Val.x *= outputScale;\n fp2Val.y *= outputScale;\n\n // Convert pair immediately and pack into result\n uint8_t e2m1Pair = fp32_pair_to_e2m1(fp2Val);\n e2m1Vec |= (static_cast<uint32_t>(e2m1Pair) << (i * 8));\n }\n\n // Write the e2m1 values to global memory.\n return e2m1Vec;\n#else\n return 0;\n#endif\n}\n\n#endif\n\n} // namespace utils\n\ntemplate <typename T, uint32_t VEC_SIZE>\n__device__ __forceinline__ vec_t<T, VEC_SIZE> vec_add(const vec_t<T, VEC_SIZE>& a,\n const vec_t<T, VEC_SIZE>& b) {\n vec_t<T, VEC_SIZE> ret;\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n ret[i] = static_cast<float>(a[i]) + static_cast<float>(b[i]);\n }\n return ret;\n}\n\nenum class AllReduceFusionPattern : int {\n kAllReduce = 0,\n kARResidualRMSNorm = 1,\n kARResidualRMSNormFP8Quant = 2,\n kARResidualRMSNormFP4Quant = 3,\n // The difference between these two and the standard version is that the NormOut version outputs\n // the result of the norm.\n kARResidualRMSNormOutFP8Quant = 4,\n kARResidualRMSNormOutFP4Quant = 5\n};\n\nenum class QuantType : int {\n kNone = 0,\n kFP8 = 1,\n kFP4 = 2,\n};\n\ntemplate <AllReduceFusionPattern Pattern>\nstruct FusionPatternTraits;\n\n#define DEFINE_FUSION_PATTERN_TRAITS(pattern, hasAllReduceOut, hasResidual, hasResidualOut, \\\n hasRMSNorm, hasNormOut, quantType) \\\n template <> \\\n struct FusionPatternTraits<pattern> { \\\n static constexpr bool kHasAllReduceOut = hasAllReduceOut; \\\n static constexpr bool kHasResidual = hasResidual; \\\n static constexpr bool kHasResidualOut = hasResidualOut; \\\n static constexpr bool kHasRMSNorm = hasRMSNorm; \\\n static constexpr bool kHasNormOut = hasNormOut; \\\n static constexpr QuantType kQuantType = quantType; \\\n };\n\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kAllReduce, true, false, false, false, false,\n QuantType::kNone);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNorm, false, true, true, true,\n true, QuantType::kNone);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNormFP8Quant, false, true, true,\n true, false, QuantType::kFP8);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNormFP4Quant, false, true, true,\n true, false, QuantType::kFP4);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNormOutFP8Quant, false, true,\n true, true, true, QuantType::kFP8);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNormOutFP4Quant, false, true,\n true, true, true, QuantType::kFP4);\n#undef DEFINE_FUSION_PATTERN_TRAITS\n\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasResidual = FusionPatternTraits<Pattern>::kHasResidual;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasRMSNorm = FusionPatternTraits<Pattern>::kHasRMSNorm;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasAllReduceOut = FusionPatternTraits<Pattern>::kHasAllReduceOut;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasResidualOut = FusionPatternTraits<Pattern>::kHasResidualOut;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasNormOut = FusionPatternTraits<Pattern>::kHasNormOut;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr QuantType GetQuantType = FusionPatternTraits<Pattern>::kQuantType;\n\ntemplate <typename T>\nstruct AllReduceFusionParams {\n int nranks;\n int rank;\n int size;\n int hidden_dim;\n void** workspace;\n void* allreduce_in;\n void* allreduce_out;\n void* residual_in;\n void* residual_out;\n void* norm_out;\n void* quant_out;\n void* scale_out;\n void* rms_gamma;\n float rms_eps;\n float* scale_factor;\n bool use_oneshot;\n QuantizationSFLayout layout = QuantizationSFLayout::SWIZZLED_128x4;\n cudaStream_t stream;\n AllReduceFusionPattern pattern;\n bool trigger_completion_at_end = true;\n};\n\ntemplate <int NRanks>\nstruct SyncComm {\n __device__ __forceinline__ SyncComm(void** workspace) {\n counter_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[0];\n flag_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[1];\n flag_value = *flag_ptr;\n for (int r = 0; r < NRanks; ++r) {\n comm_bufs[r] = workspace[r];\n barrier_flags[r] = workspace[NRanks + r];\n }\n __syncthreads();\n if (threadIdx.x == 0) {\n atomicAdd(counter_ptr, 1);\n }\n }\n\n __device__ __forceinline__ void update(int new_flag_value) {\n if (blockIdx.x == 0 && threadIdx.x == 0) {\n while (*reinterpret_cast<int volatile*>(counter_ptr) != gridDim.x) {\n }\n *flag_ptr = new_flag_value;\n *counter_ptr = 0;\n }\n }\n\n int* counter_ptr;\n int* flag_ptr;\n void* comm_bufs[NRanks];\n void* barrier_flags[NRanks];\n int flag_value;\n};\n\ntemplate <int NRanks>\nstruct LamportComm {\n __device__ __forceinline__ LamportComm(void** workspace, int rank) {\n counter_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[0];\n flag_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[2];\n clear_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[4];\n flag_value = *flag_ptr;\n int comm_size = reinterpret_cast<int*>(workspace[NRanks * 3])[3];\n clear_size = *clear_ptr;\n int data_offset = flag_value % 3;\n int clear_offset = (flag_value + 2) % 3;\n for (int r = 0; r < NRanks; ++r) {\n data_bufs[r] = reinterpret_cast<uint8_t*>(workspace[2 * NRanks + r]) +\n static_cast<int64_t>(data_offset) * comm_size;\n }\n clear_buf = reinterpret_cast<uint8_t*>(workspace[2 * NRanks + rank]) + clear_offset * comm_size;\n __syncthreads();\n if (threadIdx.x == 0) {\n atomicAdd(counter_ptr, 1);\n }\n }\n\n __device__ __forceinline__ void update(int new_clear_size) {\n if (blockIdx.x == 0 && threadIdx.x == 0) {\n while (*reinterpret_cast<int volatile*>(counter_ptr) != gridDim.x) {\n }\n *flag_ptr = (flag_value + 1) % 3;\n *clear_ptr = new_clear_size;\n *counter_ptr = 0;\n }\n }\n\n int* counter_ptr;\n int* flag_ptr;\n int* clear_ptr;\n uint8_t* data_bufs[NRanks];\n uint8_t* clear_buf;\n int clear_size;\n int flag_value;\n};\n\ntemplate <int NRanks>\nclass Barrier {\n public:\n __device__ __forceinline__ Barrier(int rank, SyncComm<NRanks> const& comm) {\n if (threadIdx.x < NRanks) {\n m_flag_value = comm.flag_value;\n int current_rank = rank;\n int target_rank = threadIdx.x;\n m_target_flag = reinterpret_cast<int*>(comm.barrier_flags[target_rank]) + current_rank;\n m_current_flag = reinterpret_cast<int*>(comm.barrier_flags[current_rank]) +\n blockIdx.x * NRanks + target_rank;\n }\n }\n\n __device__ __forceinline__ void sync() {\n __syncthreads();\n if (threadIdx.x < NRanks) {\n m_flag_value = next_flag(m_flag_value);\n // To avoid the ABA problem, we need to synchronize the correct flag value to all\n // barrier_flags, even if the corresponding CTA has not been launched.\n for (int flag_idx = blockIdx.x; flag_idx < details::kBarrierFlagCount;\n flag_idx += gridDim.x) {\n st_flag(m_target_flag + flag_idx * NRanks, m_flag_value);\n }\n while (ld_flag(m_current_flag) == prev_flag(m_flag_value)) {\n }\n }\n __syncthreads();\n }\n\n protected:\n __device__ __forceinline__ void st_flag(int* addr, int flag) {\n asm volatile(\"st.global.release.sys.b32 [%1], %0;\" ::\"r\"(flag), \"l\"(addr));\n }\n\n __device__ __forceinline__ int ld_flag(int* addr) {\n int flag;\n asm volatile(\"ld.global.acquire.sys.b32 %0, [%1];\" : \"=r\"(flag) : \"l\"(addr));\n return flag;\n }\n\n __device__ __forceinline__ int next_flag(int flag) { return flag == 2 ? 0 : flag + 1; }\n\n __device__ __forceinline__ int prev_flag(int flag) { return flag == 0 ? 2 : flag - 1; }\n\n public:\n int m_flag_value;\n\n private:\n int* m_target_flag;\n int* m_current_flag;\n};\n\ntemplate <AllReduceFusionPattern Pattern, typename T>\nclass FusedOp {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n\n public:\n __device__ __forceinline__ FusedOp(AllReduceFusionParams<T> const& params, int access_id,\n int access_id_in_token)\n : m_params(params), m_access_id(access_id), m_access_id_in_token(access_id_in_token) {\n if constexpr (HasRMSNorm<Pattern>) {\n m_gamma_val.load(reinterpret_cast<T*>(params.rms_gamma) + m_access_id_in_token * VEC_SIZE);\n }\n if constexpr (HasResidual<Pattern>) {\n m_residual_val.load(reinterpret_cast<T*>(params.residual_in) + m_access_id * VEC_SIZE);\n }\n if constexpr (GetQuantType<Pattern> == QuantType::kFP8) {\n m_scale_factor = 1.f / *(params.scale_factor);\n } else if constexpr (GetQuantType<Pattern> == QuantType::kFP4) {\n m_scale_factor = *(params.scale_factor);\n }\n }\n\n // template <typename T>\n __device__ __forceinline__ void update(int access_id) {\n if (m_access_id != access_id) {\n m_access_id = access_id;\n if constexpr (HasResidual<Pattern>) {\n m_residual_val.load(reinterpret_cast<T*>(m_params.residual_in) + m_access_id * VEC_SIZE);\n }\n }\n }\n\n // template <typename T, uint32_t VEC_SIZE>\n __device__ __forceinline__ void operator()(vec_t<T, VEC_SIZE> val, int token_id) {\n if constexpr (HasAllReduceOut<Pattern>) {\n val.store(reinterpret_cast<T*>(m_params.allreduce_out) + m_access_id * VEC_SIZE);\n }\n if constexpr (HasResidual<Pattern>) {\n val = vec_add<T, VEC_SIZE>(val, m_residual_val);\n if constexpr (HasResidualOut<Pattern>) {\n val.store(reinterpret_cast<T*>(m_params.residual_out) + m_access_id * VEC_SIZE);\n }\n }\n if constexpr (HasRMSNorm<Pattern>) {\n val = rms_norm(val, m_gamma_val);\n if constexpr (HasNormOut<Pattern>) {\n val.store(reinterpret_cast<T*>(m_params.norm_out) + m_access_id * VEC_SIZE);\n }\n }\n\n#if CUDA_VERSION >= 12080\n if constexpr (GetQuantType<Pattern> == QuantType::kFP4) {\n // NOTE(Yingyi): might update later\n auto sf_out = utils::cvt_quant_to_fp4_get_sf_out_offset<uint32_t, 2>(\n std::nullopt /* batchIdx */, token_id, m_access_id_in_token, std::nullopt /* numRows */,\n m_params.hidden_dim, reinterpret_cast<uint32_t*>(m_params.scale_out), m_params.layout);\n reinterpret_cast<uint32_t*>(m_params.quant_out)[m_access_id] =\n utils::cvt_warp_fp16_to_fp4<T, VEC_SIZE>(val, m_scale_factor, sf_out);\n } else\n#endif\n if constexpr (GetQuantType<Pattern> == QuantType::kFP8) {\n using PackedQuantizedType = std::conditional_t<std::is_same_v<T, float>, float, float2>;\n PackedQuantizedType ret;\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n reinterpret_cast<__nv_fp8_e4m3*>(&ret)[i] = static_cast<__nv_fp8_e4m3>(\n static_cast<float>(reinterpret_cast<T*>(&val)[i]) * m_scale_factor);\n }\n reinterpret_cast<PackedQuantizedType*>(m_params.quant_out)[m_access_id] = ret;\n } else {\n static_assert(GetQuantType<Pattern> == QuantType::kNone, \"Invalid quant type\");\n }\n }\n\n protected:\n __device__ __forceinline__ vec_t<T, VEC_SIZE> rms_norm(vec_t<T, VEC_SIZE> const& residual,\n vec_t<T, VEC_SIZE> const& gamma) {\n __shared__ float s_val;\n vec_t<T, VEC_SIZE> norm_out;\n float acc = 0.f;\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n float v = static_cast<float>(reinterpret_cast<T const*>(&residual)[i]);\n acc += v * v;\n }\n utils::blockReduceSumV2<float, 1>(&acc);\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n namespace cg = cooperative_groups;\n cg::cluster_group cluster = cg::this_cluster();\n if (cluster.num_blocks() > 1) {\n if (threadIdx.x == 0) {\n s_val = acc;\n acc = 0.f;\n }\n cluster.sync();\n if (threadIdx.x == 0) {\n for (int i = 0; i < cluster.num_blocks(); ++i) {\n acc += *cluster.map_shared_rank(&s_val, i);\n }\n }\n cluster.sync();\n }\n#endif\n if (threadIdx.x == 0) {\n s_val = rsqrtf(acc / m_params.hidden_dim + m_params.rms_eps);\n }\n __syncthreads();\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n reinterpret_cast<T*>(&norm_out)[i] =\n static_cast<T>(static_cast<float>(reinterpret_cast<T const*>(&residual)[i]) * s_val *\n static_cast<float>(reinterpret_cast<T const*>(&gamma)[i]));\n }\n return norm_out;\n }\n\n private:\n AllReduceFusionParams<T> const& m_params;\n int m_access_id;\n int m_access_id_in_token;\n float m_scale_factor;\n vec_t<T, VEC_SIZE> m_residual_val;\n vec_t<T, VEC_SIZE> m_gamma_val;\n};\n\ntemplate <typename T>\nstruct neg_zero {\n static constexpr T value = -T(0);\n};\n\ntemplate <>\nstruct neg_zero<half> {\n static constexpr unsigned short neg_zero_bits = 0x8000U;\n static constexpr __half value = __half_raw{neg_zero_bits};\n};\n\ntemplate <>\nstruct neg_zero<nv_bfloat16> {\n static constexpr unsigned short neg_zero_bits = 0x8000U;\n static constexpr __nv_bfloat16 value = __nv_bfloat16_raw{neg_zero_bits};\n};\n\ntemplate <>\nstruct neg_zero<float> {\n static constexpr unsigned int neg_zero_bits = 0x80000000U;\n static constexpr float value = -0.0f;\n};\n\ntemplate <typename T>\n__device__ static constexpr T neg_zero_v = neg_zero<T>::value;\n\ntemplate <typename T>\n__device__ bool is_negative_zero(T) {\n return false;\n}\n\n// float specialization\ntemplate <>\n__device__ bool is_negative_zero<float>(float x) {\n return (__float_as_int(x) == 0x80000000);\n}\n\n// double specialization\ntemplate <>\n__device__ bool is_negative_zero<double>(double x) {\n return (__double_as_longlong(x) == 0x8000000000000000ULL);\n}\n\n// __half specialization\ntemplate <>\n__device__ bool is_negative_zero<__half>(__half x) {\n return (__half_as_ushort(x) == 0x8000);\n}\n\n// __nv_bfloat16 specialization\ntemplate <>\n__device__ bool is_negative_zero<__nv_bfloat16>(__nv_bfloat16 x) {\n return (__bfloat16_as_ushort(x) == 0x8000);\n}\n\ntemplate <typename T, uint32_t VEC_SIZE>\n__device__ __forceinline__ bool has_neg_zero(const vec_t<T, VEC_SIZE>& vec) {\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n if (is_negative_zero(vec[i])) {\n return true;\n }\n }\n return false;\n}\n\ntemplate <typename T, uint32_t VEC_SIZE>\n__device__ __forceinline__ void remove_neg_zero(vec_t<T, VEC_SIZE>& vec) {\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n vec[i] = (is_negative_zero(vec[i])) ? static_cast<T>(0.f) : vec[i];\n }\n}\n\ntemplate <typename T>\n__device__ __forceinline__ void set_neg_zero(T* addr) {\n vec_t<T, details::kBytesPerAccess / sizeof(T)> val;\n val.fill(neg_zero_v<T>);\n val.store_global_volatile(addr);\n}\n\ntemplate <typename T, uint32_t VEC_SIZE, int NRanks, bool Fp32Acc>\n__device__ __forceinline__ vec_t<T, VEC_SIZE> allreduce_sum(vec_t<T, VEC_SIZE>* vals) {\n if constexpr (Fp32Acc) {\n static_assert(!std::is_same_v<T, float>);\n // Optimization: process one element at a time to reduce register usage\n // Instead of storing acc_f32[VEC_SIZE] (32 bytes), process and convert immediately\n vec_t<T, VEC_SIZE> acc;\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n float acc_f32 = static_cast<float>(reinterpret_cast<T*>(&vals[0])[i]);\n#pragma unroll\n for (int r = 1; r < NRanks; ++r) {\n acc_f32 += static_cast<float>(reinterpret_cast<T*>(&vals[r])[i]);\n }\n acc[i] = static_cast<T>(acc_f32);\n }\n return acc;\n } else {\n vec_t<T, VEC_SIZE> acc = vals[0];\n#pragma unroll\n for (int r = 1; r < NRanks; ++r) {\n acc = vec_add<T, VEC_SIZE>(acc, vals[r]);\n }\n return acc;\n }\n}\n\ntemplate <typename T>\nclass IndexHelper {\n public:\n __device__ __forceinline__ IndexHelper(AllReduceFusionParams<T> const& params) {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n namespace cg = cooperative_groups;\n cg::cluster_group cluster = cg::this_cluster();\n cg::grid_group grid = cg::this_grid();\n token_id = grid.cluster_rank();\n access_id_in_token = cluster.thread_rank();\n token_stride = grid.num_clusters();\n#else\n token_id = blockIdx.x;\n access_id_in_token = threadIdx.x;\n token_stride = gridDim.x;\n#endif\n access_id = token_id * params.hidden_dim / VEC_SIZE + access_id_in_token;\n access_stride = token_stride * params.hidden_dim / VEC_SIZE;\n tot_access = params.size / VEC_SIZE;\n }\n\n int token_id;\n int access_id_in_token;\n int token_stride;\n int access_id;\n int access_stride;\n int tot_access;\n};\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc,\n bool TriggerCompletionAtEnd = true>\n__global__ void allreduce_fusion_kernel_oneshot_lamport(AllReduceFusionParams<T> params) {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n IndexHelper<T> index_helper(params);\n int token_id = index_helper.token_id;\n int access_id_in_token = index_helper.access_id_in_token;\n int token_stride = index_helper.token_stride;\n int access_id = index_helper.access_id;\n int access_stride = index_helper.access_stride;\n int tot_access = index_helper.tot_access;\n vec_t<T, VEC_SIZE> clear_vec;\n clear_vec.fill(neg_zero_v<T>);\n FusedOp<Pattern, T> fused_op(params, access_id, access_id_in_token);\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n cudaGridDependencySynchronize();\n if constexpr (!TriggerCompletionAtEnd) {\n cudaTriggerProgrammaticLaunchCompletion();\n }\n#endif\n LamportComm<NRanks> comm(params.workspace, params.rank);\n int clear_access = comm.clear_size / VEC_SIZE;\n\n for (int idx = access_id; idx < tot_access; idx += access_stride) {\n vec_t<T, VEC_SIZE> val;\n val.load(reinterpret_cast<T*>(params.allreduce_in) + idx * VEC_SIZE);\n remove_neg_zero<T, VEC_SIZE>(val);\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n // Push data to other ranks\n val.store(reinterpret_cast<T*>(comm.data_bufs[r]) +\n (params.rank * tot_access + idx) * VEC_SIZE);\n }\n }\n for (int idx = access_id; idx < clear_access; idx += access_stride) {\n // Clear comm buffer that previous kernel used\n clear_vec.store(reinterpret_cast<T*>(comm.clear_buf) + idx * VEC_SIZE);\n }\n\n for (int idx = access_id, tidx = token_id; idx < tot_access;\n idx += access_stride, tidx += token_stride) {\n fused_op.update(idx);\n vec_t<T, VEC_SIZE> vals[NRanks];\n bool done = false;\n\n while (!done) {\n done = true;\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n // LDG.128 from local rank\n vals[r].load_global_volatile(reinterpret_cast<T*>(comm.data_bufs[params.rank]) +\n (r * tot_access + idx) * VEC_SIZE);\n done &= !has_neg_zero<T, VEC_SIZE>(vals[r]);\n }\n }\n vec_t<T, VEC_SIZE> sum_val = allreduce_sum<T, VEC_SIZE, NRanks, Fp32Acc>(vals);\n fused_op(sum_val, tidx);\n }\n\n comm.update(params.size * NRanks);\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if constexpr (TriggerCompletionAtEnd) {\n cudaTriggerProgrammaticLaunchCompletion();\n }\n#endif\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc>\n__global__ void allreduce_fusion_kernel_twoshot_sync(AllReduceFusionParams<T> params,\n std::array<int, NRanks> begin_tokens,\n std::array<int, NRanks> token_num_per_ranks) {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n IndexHelper<T> index_helper(params);\n int token_id = index_helper.token_id;\n int access_id_in_token = index_helper.access_id_in_token;\n int token_stride = index_helper.token_stride;\n int access_id = index_helper.access_id;\n int access_stride = index_helper.access_stride;\n int tot_access = index_helper.tot_access;\n FusedOp<Pattern, T> fused_op(params, access_id, access_id_in_token);\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n cudaGridDependencySynchronize();\n#endif\n SyncComm<NRanks> comm(params.workspace);\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n int comm_access_id = access_id + begin_tokens[r] * params.hidden_dim / VEC_SIZE;\n int comm_tot_access = (begin_tokens[r] + token_num_per_ranks[r]) * params.hidden_dim / VEC_SIZE;\n for (int idx = comm_access_id; idx < comm_tot_access; idx += access_stride) {\n reinterpret_cast<float4*>(comm.comm_bufs[params.rank])[idx] =\n reinterpret_cast<float4*>(params.allreduce_in)[idx];\n }\n }\n Barrier<NRanks> barrier(params.rank, comm);\n barrier.sync();\n int comm_access_id = access_id + begin_tokens[params.rank] * params.hidden_dim / VEC_SIZE;\n int comm_tot_access =\n (begin_tokens[params.rank] + token_num_per_ranks[params.rank]) * params.hidden_dim / VEC_SIZE;\n for (int idx = comm_access_id; idx < comm_tot_access; idx += access_stride) {\n vec_t<T, VEC_SIZE> vals[NRanks];\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n vals[r].load(reinterpret_cast<T*>(comm.comm_bufs[r]) + idx * VEC_SIZE);\n }\n vec_t<T, VEC_SIZE> sum_val = allreduce_sum<T, VEC_SIZE, NRanks, Fp32Acc>(vals);\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n sum_val.store(reinterpret_cast<T*>(comm.comm_bufs[r]) + (tot_access + idx) * VEC_SIZE);\n }\n }\n barrier.sync();\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n int comm_access_id = access_id + begin_tokens[r] * params.hidden_dim / VEC_SIZE;\n int comm_token_id = token_id + begin_tokens[r];\n int comm_tot_access = (begin_tokens[r] + token_num_per_ranks[r]) * params.hidden_dim / VEC_SIZE;\n for (int idx = comm_access_id, tidx = comm_token_id; idx < comm_tot_access;\n idx += access_stride, tidx += token_stride) {\n fused_op.update(idx);\n vec_t<T, VEC_SIZE> sum_val;\n sum_val.load(reinterpret_cast<T*>(comm.comm_bufs[params.rank]) +\n (tot_access + idx) * VEC_SIZE);\n fused_op(sum_val, tidx);\n }\n }\n comm.update(barrier.m_flag_value);\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n}\n\nint get_sm_count() {\n static int sm_count = 0;\n if (sm_count == 0) {\n int device_id;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&device_id));\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&sm_count, cudaDevAttrMultiProcessorCount, device_id));\n }\n return sm_count;\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc,\n bool TriggerCompletionAtEnd = true>\ncudaError_t launch_oneshot_lamport(AllReduceFusionParams<T> const& params,\n cudaLaunchConfig_t& cfg) {\n FLASHINFER_CUDA_CALL(cudaLaunchKernelEx(\n &cfg,\n allreduce_fusion_kernel_oneshot_lamport<Pattern, T, NRanks, Fp32Acc, TriggerCompletionAtEnd>,\n params));\n return cudaSuccess;\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc,\n bool TriggerCompletionAtEnd = true>\nint get_registers_per_thread_oneshot() {\n auto kernel =\n allreduce_fusion_kernel_oneshot_lamport<Pattern, T, NRanks, Fp32Acc, TriggerCompletionAtEnd>;\n cudaFuncAttributes attr;\n cudaFuncGetAttributes(&attr, kernel);\n return attr.numRegs;\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc>\ncudaError_t launch_twoshot_sync(AllReduceFusionParams<T> const& params, cudaLaunchConfig_t& cfg,\n std::array<int, NRanks> begin_tokens,\n std::array<int, NRanks> token_num_per_ranks) {\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernelEx(&cfg, allreduce_fusion_kernel_twoshot_sync<Pattern, T, NRanks, Fp32Acc>,\n params, begin_tokens, token_num_per_ranks));\n return cudaSuccess;\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc>\nint get_registers_per_thread_twoshot() {\n auto kernel = allreduce_fusion_kernel_twoshot_sync<Pattern, T, NRanks, Fp32Acc>;\n cudaFuncAttributes attr;\n cudaFuncGetAttributes(&attr, kernel);\n return attr.numRegs;\n}\n\nbool use_oneshot(int token_num) { return token_num <= details::kOneShotMaxToken; }\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc>\ncudaError_t allreduce_fusion_kernel_launcher(AllReduceFusionParams<T> const& params,\n bool launch_with_pdl) {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n FLASHINFER_CHECK(params.size % params.hidden_dim == 0, \"params.size % params.hidden_dim != 0\");\n FLASHINFER_CHECK(params.hidden_dim % VEC_SIZE == 0, \"params.hidden_dim % VEC_SIZE != 0\");\n static int SM = utils::getSMVersion();\n int token_num = params.size / params.hidden_dim;\n bool oneshot = params.use_oneshot;\n int cluster_num = token_num;\n std::array<int, NRanks> begin_tokens, token_num_per_ranks;\n if (!oneshot) {\n int remaining_token = token_num % NRanks;\n int token_num_per_rank = token_num / NRanks;\n cluster_num = token_num_per_rank;\n if (remaining_token) {\n cluster_num++;\n }\n for (int r = 0; r < NRanks; ++r) {\n begin_tokens[r] = r * token_num_per_rank + (remaining_token > r ? r : remaining_token);\n token_num_per_ranks[r] = token_num_per_rank + (remaining_token > r ? 1 : 0);\n }\n }\n int threads_per_token = params.hidden_dim / VEC_SIZE;\n int cluster_size;\n if (SM >= 90) {\n cluster_size = 8;\n } else {\n cluster_size = 1;\n }\n while (threads_per_token % cluster_size != 0 && cluster_size > 1) {\n cluster_size /= 2;\n }\n int threads_per_block = threads_per_token / cluster_size;\n while (threads_per_block < 128 && cluster_size >= 2) {\n threads_per_block *= 2;\n cluster_size /= 2;\n }\n int sm_count = get_sm_count();\n int registers_per_thread;\n if (oneshot) {\n if (params.trigger_completion_at_end) {\n registers_per_thread = get_registers_per_thread_oneshot<Pattern, T, NRanks, Fp32Acc, true>();\n } else {\n registers_per_thread = get_registers_per_thread_oneshot<Pattern, T, NRanks, Fp32Acc, false>();\n }\n } else {\n registers_per_thread = get_registers_per_thread_twoshot<Pattern, T, NRanks, Fp32Acc>();\n }\n static int max_registers = -1;\n if (max_registers < 0) {\n max_registers = utils::getSMRegisters();\n }\n int max_threads_per_block = min(max_registers / registers_per_thread, 1024);\n\n int block_size = threads_per_block;\n\n // FP4 optimization: apply BEFORE SM count check to avoid being overridden\n // This allows FP4 to use smaller block_size even when cluster_num is large\n if constexpr (GetQuantType<Pattern> == QuantType::kFP4) {\n // Try to use 160 as block_size if possible (better occupancy for FP4)\n if (threads_per_token % 160 == 0 && 160 <= max_threads_per_block && 160 >= 128) {\n block_size = 160;\n cluster_size = threads_per_token / 160;\n if (cluster_size > 8) cluster_size = 8;\n }\n // Fallback: try 192, 128 if 160 doesn't work\n else if (threads_per_token % 192 == 0 && 192 <= max_threads_per_block && 192 >= 128) {\n block_size = 192;\n cluster_size = threads_per_token / 192;\n if (cluster_size > 8) cluster_size = 8;\n } else if (threads_per_token % 128 == 0 && 128 <= max_threads_per_block) {\n block_size = 128;\n cluster_size = threads_per_token / 128;\n if (cluster_size > 8) cluster_size = 8;\n }\n // Update threads_per_block to match block_size for SM count check\n threads_per_block = block_size;\n }\n\n // SM count check: adjust if cluster_num * cluster_size > sm_count\n // But respect FP4 optimization if already applied\n while (cluster_num * cluster_size > sm_count && cluster_size > 1 &&\n threads_per_block <= max_threads_per_block / 2) {\n threads_per_block *= 2;\n cluster_size /= 2;\n // If FP4 optimization was applied, update block_size to match\n if constexpr (GetQuantType<Pattern> == QuantType::kFP4) {\n block_size = threads_per_block;\n }\n }\n\n // Update block_size if not FP4 (FP4 already set it above)\n if constexpr (GetQuantType<Pattern> != QuantType::kFP4) {\n block_size = threads_per_block;\n }\n\n // Check conditions using the final block_size (not threads_per_block)\n FLASHINFER_CHECK(oneshot || block_size >= params.nranks, \"not oneshot, or block_size < nranks\");\n FLASHINFER_CHECK(block_size <= 1024 && cluster_size > 0,\n \"block_size > 1024 or cluster_size <= 0\");\n\n int grid_size = (std::min(sm_count, cluster_num * cluster_size) / cluster_size) * cluster_size;\n cudaLaunchConfig_t cfg;\n cudaLaunchAttribute attribute[2];\n cfg.gridDim = grid_size;\n cfg.blockDim = block_size;\n cfg.dynamicSmemBytes = 0;\n cfg.stream = params.stream;\n attribute[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attribute[0].val.programmaticStreamSerializationAllowed = launch_with_pdl ? 1 : 0;\n attribute[1].id = cudaLaunchAttributeClusterDimension;\n attribute[1].val.clusterDim.x = cluster_size;\n attribute[1].val.clusterDim.y = 1;\n attribute[1].val.clusterDim.z = 1;\n cfg.attrs = attribute;\n cfg.numAttrs = SM >= 90 ? 2 : 0;\n if (oneshot) {\n bool trigger_completion_at_end = params.trigger_completion_at_end;\n if (trigger_completion_at_end) {\n FLASHINFER_CUDA_CALL(\n (launch_oneshot_lamport<Pattern, T, NRanks, Fp32Acc, true>(params, cfg)));\n } else {\n FLASHINFER_CUDA_CALL(\n (launch_oneshot_lamport<Pattern, T, NRanks, Fp32Acc, false>(params, cfg)));\n }\n } else {\n FLASHINFER_CUDA_CALL((launch_twoshot_sync<Pattern, T, NRanks, Fp32Acc>(\n params, cfg, begin_tokens, token_num_per_ranks)));\n }\n return cudaSuccess;\n}\n\ntemplate <typename T>\ncudaError_t allreduce_fusion_op(AllReduceFusionParams<T> const& params, bool launch_with_pdl,\n bool fp32_acc) {\n#define DISPATCH_ACC_TYPE(T, Pattern, NRanks) \\\n if constexpr (std::is_same_v<T, float>) { \\\n return allreduce_fusion_kernel_launcher<Pattern, T, NRanks, false>(params, launch_with_pdl); \\\n } else { \\\n if (fp32_acc) { \\\n return allreduce_fusion_kernel_launcher<Pattern, T, NRanks, true>(params, launch_with_pdl); \\\n } else { \\\n return allreduce_fusion_kernel_launcher<Pattern, T, NRanks, false>(params, launch_with_pdl); \\\n } \\\n }\n\n#define DISPATCH_PATTERN(T, NRanks) \\\n switch (params.pattern) { \\\n case AllReduceFusionPattern::kAllReduce: \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kAllReduce, NRanks); \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNorm: \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNorm, NRanks); \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNormFP8Quant: \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNormFP8Quant, NRanks); \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNormFP4Quant: \\\n if constexpr (!std::is_same_v<T, float> && CUDA_VERSION >= 12080) { \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNormFP4Quant, NRanks); \\\n } else { \\\n FLASHINFER_CHECK(CUDA_VERSION >= 12080, \"FP4Quant requires CUDA 12.8 or higher\"); \\\n FLASHINFER_CHECK(false, \"FP4Quant pattern cannot work with DType=float\"); \\\n } \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNormOutFP8Quant: \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNormOutFP8Quant, NRanks); \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNormOutFP4Quant: \\\n if constexpr (!std::is_same_v<T, float> && CUDA_VERSION >= 12080) { \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNormOutFP4Quant, NRanks); \\\n } else { \\\n FLASHINFER_CHECK(CUDA_VERSION >= 12080, \"OutFP4Quant requires CUDA 12.8 or higher\"); \\\n FLASHINFER_CHECK(false, \"OutFP4Quant pattern cannot work with DType=float\"); \\\n } \\\n break; \\\n default: \\\n FLASHINFER_CHECK(false, \"Unsupported allreduce fusion pattern\"); \\\n }\n\n switch (params.nranks) {\n case 2:\n DISPATCH_PATTERN(T, 2);\n break;\n case 4:\n DISPATCH_PATTERN(T, 4);\n break;\n case 8:\n DISPATCH_PATTERN(T, 8);\n break;\n case 16:\n DISPATCH_PATTERN(T, 16);\n break;\n default:\n FLASHINFER_ERROR(\n \"allreduce_fusion_kernel: unsupported ranks number! Supported ranks: 2, 4, 8, 16.\");\n }\n}\n\n} // namespace trtllm_allreduce_fusion\n\n} // namespace flashinfer\n"},"diff":{"kind":"string","value":"--- include/flashinfer/comm/trtllm_allreduce_fusion.cuh\n+++ include/flashinfer/comm/trtllm_allreduce_fusion.cuh\n@@ -529,6 +529,26 @@\n uint32_t val3 = c3;\n \n return (val3 << 24) | (val2 << 16) | (val1 << 8) | val0;\n+}\n+\n+// Convert single float2 pair to e2m1 (2 float32 -> 2 e2m1, returns uint8_t)\n+// Optimization: allows pipelined processing to reduce register usage\n+// Note: \"=r\" constraint always allocates 32-bit register regardless of variable type\n+inline __device__ uint8_t fp32_pair_to_e2m1(float2 pair) {\n+#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n+ uint32_t val32;\n+ asm volatile(\n+ \"{\\n\"\n+ \".reg .b8 byte0;\\n\"\n+ \"cvt.rn.satfinite.e2m1x2.f32 byte0, %2, %1;\\n\"\n+ \"mov.b32 %0, {byte0, 0, 0, 0};\\n\"\n+ \"}\"\n+ : \"=r\"(val32)\n+ : \"f\"(pair.x), \"f\"(pair.y));\n+ return static_cast<uint8_t>(val32 & 0xFF); // Extract low 8 bits\n+#else\n+ return 0;\n+#endif\n }\n \n #if CUDA_VERSION >= 12080\n@@ -602,6 +622,9 @@\n __device__ uint32_t cvt_warp_fp16_to_fp4(vec_t<T, VEC_SIZE>& vec, float SFScaleVal,\n uint8_t* SFout) {\n #if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n+ // Pre-compute constant: reciprocal of 6.0 (maximum value of e2m1)\n+ static constexpr float RECIPROCAL_6 = 1.0f / 6.0f;\n+\n // Get absolute maximum values among the local 8 values.\n auto localMax = maths::cuda_abs(get_vec2_element(vec, 0));\n \n@@ -613,57 +636,62 @@\n // Get the absolute maximum among all 16 values (two threads).\n localMax = maths::cuda_max(__shfl_xor_sync(uint32_t(-1), localMax, 1), localMax);\n // Get the final absolute maximum values.\n+ // Optimization: compute vecMax and reuse localMax space (localMax no longer needed)\n float vecMax = float(maths::cuda_max(localMax.x, localMax.y));\n \n // Get the SF (max value of the vector / max value of e2m1).\n // maximum value of e2m1 = 6.0.\n- // TODO: use half as compute data type.\n- float SFValue = SFScaleVal * (vecMax * maths::reciprocal_approximate_ftz(6.0f));\n- // 8 bits representation of the SF.\n+ // Optimization: compute quantized SF directly, avoid storing intermediate SFValue\n uint8_t fp8SFVal;\n- // Write the SF to global memory (STG.8).\n+ float quantized_sf;\n if constexpr (UE8M0_SF) {\n #if (__CUDACC_VER_MAJOR__ * 1000 + __CUDACC_VER_MINOR__ * 10 >= 12080)\n __nv_fp8_e8m0 tmp;\n- tmp.__x = __nv_cvt_float_to_e8m0(SFValue, __NV_SATFINITE, cudaRoundPosInf);\n- SFValue = static_cast<float>(tmp);\n+ float sf_value = SFScaleVal * (vecMax * RECIPROCAL_6);\n+ tmp.__x = __nv_cvt_float_to_e8m0(sf_value, __NV_SATFINITE, cudaRoundPosInf);\n+ quantized_sf = static_cast<float>(tmp);\n fp8SFVal = tmp.__x;\n #else\n #error \"FP8 E8M0 support requires CUDA 12.8 or newer.\"\n #endif\n } else {\n // Here SFValue is always positive, so E4M3 is the same as UE4M3.\n- __nv_fp8_e4m3 tmp = __nv_fp8_e4m3(SFValue);\n+ __nv_fp8_e4m3 tmp = __nv_fp8_e4m3(SFScaleVal * (vecMax * RECIPROCAL_6));\n fp8SFVal = tmp.__x;\n- SFValue = static_cast<float>(tmp);\n- }\n- // Get the output scale.\n+ quantized_sf = static_cast<float>(tmp);\n+ }\n+ // Get the output scale directly (optimization: avoid storing intermediate SFValue)\n // Recipe: final_scale = reciprocal(fp32(fp8(SFValue * SFScaleVal))) * reciprocal(SFScaleVal))\n- float outputScale = SFValue != 0 ? maths::reciprocal_approximate_ftz(\n- SFValue * maths::reciprocal_approximate_ftz(SFScaleVal))\n- : 0.0f;\n+ // Optimization: mathematically equivalent to SFScaleVal / quantized_sf, but more efficient\n+ // (reduces 1 reciprocal call and 1 multiply operation)\n+ float outputScale = quantized_sf != 0 ? SFScaleVal / quantized_sf : 0.0f;\n \n if (SFout) {\n // Write the SF to global memory (STG.8).\n *SFout = fp8SFVal;\n }\n \n- // Convert the input to float.\n- float2 fp2Vals[details::CVT_FP4_ELTS_PER_THREAD / 2];\n+ // Convert the input to float and quantize (pipelined to reduce register usage).\n+ // Optimization: use single float2 instead of array to reduce register pressure from 32 bytes to 8\n+ // bytes\n+ uint32_t e2m1Vec = 0;\n \n #pragma unroll\n for (int i = 0; i < details::CVT_FP4_ELTS_PER_THREAD / 2; i++) {\n+ // Reuse single float2 register instead of array\n+ float2 fp2Val;\n if constexpr (std::is_same_v<T, half>) {\n- fp2Vals[i] = __half22float2(get_vec2_element(vec, i));\n+ fp2Val = __half22float2(get_vec2_element(vec, i));\n } else {\n- fp2Vals[i] = __bfloat1622float2(get_vec2_element(vec, i));\n- }\n- fp2Vals[i].x *= outputScale;\n- fp2Vals[i].y *= outputScale;\n- }\n-\n- // Convert to e2m1 values.\n- uint32_t e2m1Vec = fp32_vec_to_e2m1(fp2Vals);\n+ fp2Val = __bfloat1622float2(get_vec2_element(vec, i));\n+ }\n+ fp2Val.x *= outputScale;\n+ fp2Val.y *= outputScale;\n+\n+ // Convert pair immediately and pack into result\n+ uint8_t e2m1Pair = fp32_pair_to_e2m1(fp2Val);\n+ e2m1Vec |= (static_cast<uint32_t>(e2m1Pair) << (i * 8));\n+ }\n \n // Write the e2m1 values to global memory.\n return e2m1Vec;\n@@ -1105,22 +1133,17 @@\n __device__ __forceinline__ vec_t<T, VEC_SIZE> allreduce_sum(vec_t<T, VEC_SIZE>* vals) {\n if constexpr (Fp32Acc) {\n static_assert(!std::is_same_v<T, float>);\n- float acc_f32[VEC_SIZE];\n+ // Optimization: process one element at a time to reduce register usage\n+ // Instead of storing acc_f32[VEC_SIZE] (32 bytes), process and convert immediately\n+ vec_t<T, VEC_SIZE> acc;\n #pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n- acc_f32[i] = static_cast<float>(reinterpret_cast<T*>(&vals[0])[i]);\n- }\n-#pragma unroll\n- for (int r = 1; r < NRanks; ++r) {\n-#pragma unroll\n- for (int i = 0; i < VEC_SIZE; ++i) {\n- acc_f32[i] += static_cast<float>(reinterpret_cast<T*>(&vals[r])[i]);\n+ float acc_f32 = static_cast<float>(reinterpret_cast<T*>(&vals[0])[i]);\n+#pragma unroll\n+ for (int r = 1; r < NRanks; ++r) {\n+ acc_f32 += static_cast<float>(reinterpret_cast<T*>(&vals[r])[i]);\n }\n- }\n- vec_t<T, VEC_SIZE> acc;\n-#pragma unroll\n- for (int i = 0; i < VEC_SIZE; ++i) {\n- acc[i] = static_cast<T>(acc_f32[i]);\n+ acc[i] = static_cast<T>(acc_f32);\n }\n return acc;\n } else {\n@@ -1402,16 +1425,54 @@\n max_registers = utils::getSMRegisters();\n }\n int max_threads_per_block = min(max_registers / registers_per_thread, 1024);\n+\n+ int block_size = threads_per_block;\n+\n+ // FP4 optimization: apply BEFORE SM count check to avoid being overridden\n+ // This allows FP4 to use smaller block_size even when cluster_num is large\n+ if constexpr (GetQuantType<Pattern> == QuantType::kFP4) {\n+ // Try to use 160 as block_size if possible (better occupancy for FP4)\n+ if (threads_per_token % 160 == 0 && 160 <= max_threads_per_block && 160 >= 128) {\n+ block_size = 160;\n+ cluster_size = threads_per_token / 160;\n+ if (cluster_size > 8) cluster_size = 8;\n+ }\n+ // Fallback: try 192, 128 if 160 doesn't work\n+ else if (threads_per_token % 192 == 0 && 192 <= max_threads_per_block && 192 >= 128) {\n+ block_size = 192;\n+ cluster_size = threads_per_token / 192;\n+ if (cluster_size > 8) cluster_size = 8;\n+ } else if (threads_per_token % 128 == 0 && 128 <= max_threads_per_block) {\n+ block_size = 128;\n+ cluster_size = threads_per_token / 128;\n+ if (cluster_size > 8) cluster_size = 8;\n+ }\n+ // Update threads_per_block to match block_size for SM count check\n+ threads_per_block = block_size;\n+ }\n+\n+ // SM count check: adjust if cluster_num * cluster_size > sm_count\n+ // But respect FP4 optimization if already applied\n while (cluster_num * cluster_size > sm_count && cluster_size > 1 &&\n threads_per_block <= max_threads_per_block / 2) {\n threads_per_block *= 2;\n cluster_size /= 2;\n- }\n- FLASHINFER_CHECK(oneshot || threads_per_block >= params.nranks,\n- \"not oneshot, or threads_per_block < nranks\");\n- int block_size = threads_per_block;\n+ // If FP4 optimization was applied, update block_size to match\n+ if constexpr (GetQuantType<Pattern> == QuantType::kFP4) {\n+ block_size = threads_per_block;\n+ }\n+ }\n+\n+ // Update block_size if not FP4 (FP4 already set it above)\n+ if constexpr (GetQuantType<Pattern> != QuantType::kFP4) {\n+ block_size = threads_per_block;\n+ }\n+\n+ // Check conditions using the final block_size (not threads_per_block)\n+ FLASHINFER_CHECK(oneshot || block_size >= params.nranks, \"not oneshot, or block_size < nranks\");\n FLASHINFER_CHECK(block_size <= 1024 && cluster_size > 0,\n \"block_size > 1024 or cluster_size <= 0\");\n+\n int grid_size = (std::min(sm_count, cluster_num * cluster_size) / cluster_size) * cluster_size;\n cudaLaunchConfig_t cfg;\n cudaLaunchAttribute attribute[2];"},"lines_added":{"kind":"number","value":102,"string":"102"},"lines_removed":{"kind":"number","value":41,"string":"41"},"files_in_commit":{"kind":"number","value":1,"string":"1"},"models_mentioned":{"kind":"list like","value":["deepseek"],"string":"[\n \"deepseek\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.4x"],"string":"[\n \"1.4x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/comm/trtllm_allreduce_fusion.cuh).\n\nGoal: [performance]optimize for nvfp4\nTarget hardware: unspecified\nTarget models: deepseek\n\nCurrent file:\n```cuda\n#include <cooperative_groups.h>\n#include <cuda.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n\n#if CUDA_VERSION >= 12080\n#include <cuda_fp4.h>\n#endif\n\n#include <cuda/std/optional>\n#include <tuple>\n#include <type_traits>\n\n#include \"../exception.h\"\n#include \"../fp4_layout.cuh\"\n#include \"../logging.h\"\n#include \"../utils.cuh\"\n#include \"../vec_dtypes.cuh\"\n\nnamespace flashinfer {\n\nnamespace trtllm_allreduce_fusion {\n\nusing flashinfer::QuantizationSFLayout;\n\nnamespace details {\n\nstatic constexpr int CVT_FP4_ELTS_PER_THREAD = 8;\nstatic constexpr int CVT_FP4_SF_VEC_SIZE = 16;\nstatic constexpr int kBytesPerAccess = 16;\nstatic constexpr int kOneShotMaxToken = 128;\nstatic constexpr int kBarrierFlagCount = 256;\n\n} // namespace details\n\nnamespace maths {\n// // ============================== Cast ==============================\ntemplate <typename T_OUT, typename T_IN>\n__device__ inline T_OUT cuda_cast(T_IN val) {\n return val;\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, int2>(int2 val) {\n return make_float2(val.x, val.y);\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, float>(float val) {\n return make_float2(val, val);\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, half2>(half2 val) {\n return __half22float2(val);\n}\n\ntemplate <>\n__device__ inline half2 cuda_cast<half2, float2>(float2 val) {\n return __float22half2_rn(val);\n}\n\ntemplate <>\n__device__ inline half2 cuda_cast<half2, float>(float val) {\n return __float2half2_rn(val);\n}\n\ntemplate <>\n__device__ inline half2 cuda_cast<half2, half>(half val) {\n return __half2half2(val);\n}\n\ntemplate <>\n__device__ inline int8_t cuda_cast<int8_t, half>(half val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n union {\n half fp16;\n int16_t int16_in;\n };\n\n fp16 = val;\n asm volatile(\"cvt.rni.sat.s8.f16 %0, %1;\" : \"=h\"(int16) : \"h\"(int16_in));\n return int8[0];\n}\n\ntemplate <>\n__device__ inline int16_t cuda_cast<int16_t, half2>(half2 val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int8[0] = cuda_cast<int8_t>(val.x);\n int8[1] = cuda_cast<int8_t>(val.y);\n return int16;\n}\n\ntemplate <>\n__device__ inline int8_t cuda_cast<int8_t, float>(float val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n asm volatile(\"cvt.rni.sat.s8.f32 %0, %1;\" : \"=h\"(int16) : \"f\"(val));\n return int8[0];\n}\n\ntemplate <>\n__device__ inline int16_t cuda_cast<int16_t, float2>(float2 val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int8[0] = cuda_cast<int8_t>(val.x);\n int8[1] = cuda_cast<int8_t>(val.y);\n return int16;\n}\n\ntemplate <>\n__device__ inline half2 cuda_cast<half2, int16_t>(int16_t val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int16 = val;\n return make_half2(int8[0], int8[1]);\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, int16_t>(int16_t val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int16 = val;\n return make_float2(int8[0], int8[1]);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_cast(int32_t val) {\n return static_cast<float>(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_cast(int8_t val) {\n return static_cast<float>(val);\n}\n\ntemplate <>\n__device__ inline int8_t cuda_cast(__nv_bfloat16 val) {\n return static_cast<float>(val);\n}\n\ntemplate <>\n__device__ inline float cuda_cast<float, __nv_bfloat16>(__nv_bfloat16 val) {\n return __bfloat162float(val);\n}\n\ninline __device__ float2 bf1622float2(const __nv_bfloat162 val) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800\n float2 f_val;\n f_val.x = __low2float(val);\n f_val.y = __high2float(val);\n return f_val;\n#else\n return __bfloat1622float2(val);\n#endif\n}\n\ntemplate <>\n__device__ inline float2 cuda_cast<float2, __nv_bfloat162>(__nv_bfloat162 val) {\n return bf1622float2(val);\n}\n\ntemplate <>\n__device__ inline half cuda_cast<half, __nv_bfloat16>(__nv_bfloat16 val) {\n return __float2half(__bfloat162float(val));\n}\n\ninline __device__ int16_t bf1622int16(__nv_bfloat162 val) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800\n float2 f_val;\n f_val.x = max(min(__low2float(val), 127.f), -128.f);\n f_val.y = max(min(__high2float(val), 127.f), -128.f);\n\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int8[0] = static_cast<int8_t>(static_cast<short>(f_val.x));\n int8[1] = static_cast<int8_t>(static_cast<short>(f_val.y));\n return int16;\n#else\n val = __hmin2(val, make_bfloat162(127., 127.));\n val = __hmax2(val, make_bfloat162(-128., -128.));\n\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int8[0] = static_cast<int8_t>(static_cast<short>(val.x));\n int8[1] = static_cast<int8_t>(static_cast<short>(val.y));\n return int16;\n#endif\n}\n\ntemplate <>\n__device__ inline int16_t cuda_cast<int16_t, __nv_bfloat162>(__nv_bfloat162 val) {\n return bf1622int16(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_cast<__nv_bfloat16, float>(float val) {\n return __float2bfloat16(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_cast<__nv_bfloat16, half>(half val) {\n return __float2bfloat16(__half2float(val));\n}\n\ninline __device__ __nv_bfloat162 bf162bf162(const __nv_bfloat16 val) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800\n __nv_bfloat162 val2;\n val2.x = val;\n val2.y = val;\n return val2;\n#else\n return __bfloat162bfloat162(val);\n#endif\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, __nv_bfloat16>(__nv_bfloat16 val) {\n return bf162bf162(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, float>(float val) {\n return __float2bfloat162_rn(val);\n}\n\ninline __device__ __nv_bfloat162 float22bf162(const float2 val) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ < 800\n return __floats2bfloat162_rn(val.x, val.y);\n#else\n return __float22bfloat162_rn(val);\n#endif\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, float2>(float2 val) {\n return float22bf162(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, int16_t>(int16_t val) {\n union {\n int8_t int8[2];\n int16_t int16;\n };\n\n int16 = val;\n __nv_bfloat162 res;\n res.x = cuda_cast<__nv_bfloat16>(int8[0]);\n res.y = cuda_cast<__nv_bfloat16>(int8[1]);\n return res;\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_cast<__nv_bfloat162, half2>(half2 val) {\n return float22bf162(__half22float2(val));\n}\n\n// // ============================== Abs ==============================\ntemplate <typename T>\n__device__ inline T cuda_abs(T val) {\n assert(false);\n return {};\n}\n\ntemplate <>\n__device__ inline float cuda_abs(float val) {\n return fabs(val);\n}\n\ntemplate <>\n__device__ inline float2 cuda_abs(float2 val) {\n return make_float2(fabs(val.x), fabs(val.y));\n}\n\ntemplate <>\n__device__ inline half cuda_abs(half val) {\n return __habs(val);\n}\n\ntemplate <>\n__device__ inline half2 cuda_abs(half2 val) {\n return __habs2(val);\n}\n\n#if __CUDA_ARCH__ >= 800 || !defined(__CUDA_ARCH__)\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_abs(__nv_bfloat16 val) {\n return __habs(val);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_abs(__nv_bfloat162 val) {\n return __habs2(val);\n}\n#endif\n\n// // ============================== Max ==============================\ntemplate <typename To, typename Ti>\n__device__ inline To cuda_max(Ti val) {\n return cuda_cast<To>(val);\n};\n\ntemplate <>\n__device__ inline float cuda_max(float2 val) {\n return fmaxf(val.x, val.y);\n}\n\ntemplate <>\n__device__ inline half cuda_max(half2 val) {\n return __hmax(val.x, val.y);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat16 cuda_max(__nv_bfloat162 val) {\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800))\n return __hmax(val.x, val.y);\n#else\n assert(0);\n asm volatile(\"brkpt;\\n\" ::);\n return __nv_bfloat16(0);\n#endif\n}\n\n// Binary maximum: compute the max of two values.\ntemplate <typename T>\n__device__ inline T cuda_max(T val1, T val2) {\n return (val1 > val2) ? val1 : val2;\n}\n\ntemplate <>\n__device__ inline float2 cuda_max(float2 val1, float2 val2) {\n float2 out;\n out.x = fmaxf(val1.x, val2.x);\n out.y = fmaxf(val1.y, val2.y);\n return out;\n}\n\ntemplate <>\n__device__ inline half2 cuda_max(half2 val1, half2 val2) {\n return __hmax2(val1, val2);\n}\n\ntemplate <>\n__device__ inline __nv_bfloat162 cuda_max(__nv_bfloat162 val1, __nv_bfloat162 val2) {\n return __hmax2(val1, val2);\n}\n\n// // ============================== Reciprocal ==============================\n// Fast reciprocal.\ninline __device__ float reciprocal_approximate_ftz(float a) {\n float b;\n asm volatile(\"rcp.approx.ftz.f32 %0, %1;\\n\" : \"=f\"(b) : \"f\"(a));\n return b;\n}\n} // namespace maths\n\nnamespace utils {\n\n#define FINAL_MASK 0xffffffff\n\ntemplate <typename T, int NUM>\n__inline__ __device__ T warpReduceSumV2(T* val) {\n#pragma unroll\n for (int i = 0; i < NUM; i++) {\n#pragma unroll\n for (int mask = 16; mask > 0; mask >>= 1)\n val[i] += __shfl_xor_sync(FINAL_MASK, val[i], mask, 32);\n }\n return (T)(0.0f);\n}\n\ntemplate <typename T, int NUM>\n__inline__ __device__ T blockReduceSumV2(T* val) {\n static __shared__ T shared[NUM][33];\n int lane = threadIdx.x & 0x1f;\n int wid = threadIdx.x >> 5;\n\n warpReduceSumV2<T, NUM>(val);\n\n if (lane == 0) {\n#pragma unroll\n for (int i = 0; i < NUM; i++) {\n shared[i][wid] = val[i];\n }\n }\n\n __syncthreads();\n\n bool is_mask = threadIdx.x < (blockDim.x / 32.f);\n#pragma unroll\n for (int i = 0; i < NUM; i++) {\n val[i] = is_mask ? shared[i][lane] : (T)(0.0f);\n }\n warpReduceSumV2<T, NUM>(val);\n return (T)0.0f;\n}\n\ninline int getSMVersion() {\n int device{-1};\n FLASHINFER_CUDA_CALL(cudaGetDevice(&device));\n int sm_major = 0;\n int sm_minor = 0;\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&sm_major, cudaDevAttrComputeCapabilityMajor, device));\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&sm_minor, cudaDevAttrComputeCapabilityMinor, device));\n return sm_major * 10 + sm_minor;\n}\n\ninline int getSMRegisters() {\n int device{-1};\n FLASHINFER_CUDA_CALL(cudaGetDevice(&device));\n int regs_per_block;\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(®s_per_block, cudaDevAttrMaxRegistersPerBlock, device));\n return regs_per_block;\n}\n\ninline __device__ int64_t get_sf_out_offset_128x4(std::optional<int> batchIdx, int mIdx, int kIdx,\n std::optional<int> numRows, int numCols) {\n // SF layout [numMTiles, numKTiles, 32 (mTile), 4 (mTile), 4(kTile)]\n // --> index [mTileIdx, kTileIdx, outerMIdx, innerMIdx, innerKIdx]\n\n // batched tensor\n // SF layout [numBTiles, numMTiles, numKTiles, 32 (mTile), 4 (mTile), 4(kTile)]\n // --> index [bTileIdx, mTileIdx, kTileIdx, outerMIdx, innerMIdx, innerKIdx]\n\n int32_t innerKIdx = (kIdx % 4);\n int64_t innerKStride = 1;\n\n int32_t innerMIdx = (mIdx % (32 * 4)) / 32;\n int64_t innerMStride = 4 * innerKStride; // 4\n\n // M tile layout [32, 4] is column-major.\n int32_t outerMIdx = (mIdx % 32);\n int64_t outerMStride = 4 * innerMStride; // 16\n\n int32_t kTileIdx = (kIdx / 4);\n int64_t kTileStride = 32 * outerMStride; // 512\n\n // SF vector size 16. We round the \"numCols\" up to a multiple of 64.\n int factor = details::CVT_FP4_SF_VEC_SIZE * 4;\n int32_t numKTiles = (numCols + factor - 1) / factor;\n int32_t mTileIdx = mIdx / (32 * 4);\n int64_t mTileStride = numKTiles * kTileStride;\n\n // Each SF block has 128 rows so pad rows to the multiple of 128.\n int32_t numMTiles = (numRows.value_or(0) + 128 - 1) / 128;\n int64_t bTileStride = numMTiles * mTileStride;\n\n // Compute the global offset.\n int64_t SFOffset = batchIdx.value_or(0) * bTileStride + mTileIdx * mTileStride +\n kTileIdx * kTileStride + outerMIdx * outerMStride + innerMIdx * innerMStride +\n innerKIdx * innerKStride;\n\n return SFOffset;\n}\n\ntemplate <class SFType, int CVT_FP4_NUM_THREADS_PER_SF>\n__device__ uint8_t* cvt_quant_to_fp4_get_sf_out_offset(std::optional<int> batchIdx, int rowIdx,\n int colIdx, std::optional<int> numRows,\n int numCols, SFType* SFout,\n QuantizationSFLayout layout) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n static_assert(CVT_FP4_NUM_THREADS_PER_SF == 1 || CVT_FP4_NUM_THREADS_PER_SF == 2);\n\n // One pair of threads write one SF to global memory.\n // TODO: stage through smem for packed STG.32\n // is it better than STG.8 from 4 threads ?\n if (threadIdx.x % CVT_FP4_NUM_THREADS_PER_SF == 0) {\n if (layout == QuantizationSFLayout::SWIZZLED_128x4) {\n // SF vector index (16 elements share one SF in the K dimension).\n // numRows and numCols are unpadded.\n int32_t kIdx = colIdx / CVT_FP4_NUM_THREADS_PER_SF;\n int32_t mIdx = rowIdx;\n\n auto SFOffset = get_sf_out_offset_128x4(batchIdx, mIdx, kIdx, numRows, numCols);\n return reinterpret_cast<uint8_t*>(SFout) + SFOffset;\n } else if (layout == QuantizationSFLayout::LINEAR) {\n // Linear row-major layout, no padding required.\n int32_t KTileIdx = colIdx / CVT_FP4_NUM_THREADS_PER_SF;\n\n int32_t numKTiles = numCols / details::CVT_FP4_SF_VEC_SIZE;\n int64_t mTileStride = numKTiles;\n\n int64_t BTileStride = numRows.value_or(0) * mTileStride;\n\n int64_t SFOffset = batchIdx.value_or(0) * BTileStride + rowIdx * mTileStride + KTileIdx;\n return reinterpret_cast<uint8_t*>(SFout) + SFOffset;\n } else {\n return nullptr;\n }\n }\n#endif\n return nullptr;\n}\n\n__forceinline__ __device__ uint32_t pack_bytes(uint8_t c0, uint8_t c1, uint8_t c2, uint8_t c3) {\n uint32_t val0 = c0;\n uint32_t val1 = c1;\n uint32_t val2 = c2;\n uint32_t val3 = c3;\n\n return (val3 << 24) | (val2 << 16) | (val1 << 8) | val0;\n}\n\n#if CUDA_VERSION >= 12080\n// Convert 8 float32 values into 8 e2m1 values (represented as one uint32_t).\n// NOTE: bypass sm_100 requirement by __nv_cvt_float2_to_fp4x2\ninline __device__ uint32_t fp32_vec_to_e2m1(float (&array)[8]) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n uint32_t val;\n asm volatile(\n \"{\\n\"\n \".reg .b8 byte0;\\n\"\n \".reg .b8 byte1;\\n\"\n \".reg .b8 byte2;\\n\"\n \".reg .b8 byte3;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte0, %2, %1;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte1, %4, %3;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte2, %6, %5;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte3, %8, %7;\\n\"\n \"mov.b32 %0, {byte0, byte1, byte2, byte3};\\n\"\n \"}\"\n : \"=r\"(val)\n : \"f\"(array[0]), \"f\"(array[1]), \"f\"(array[2]), \"f\"(array[3]), \"f\"(array[4]), \"f\"(array[5]),\n \"f\"(array[6]), \"f\"(array[7]));\n return val;\n#else\n uint32_t val;\n __nv_fp4x2_storage_t vals[4];\n#pragma unroll\n for (int i = 0; i < 4; i++) {\n vals[i] = __nv_cvt_float2_to_fp4x2(*(((float2*)array) + i), __NV_E2M1, cudaRoundNearest);\n }\n val = pack_bytes(vals[0], vals[1], vals[2], vals[3]);\n return val;\n#endif\n}\n\n// Convert 4 float2 values into 8 e2m1 values (represented as one uint32_t).\ninline __device__ uint32_t fp32_vec_to_e2m1(float2 (&array)[4]) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n uint32_t val;\n asm volatile(\n \"{\\n\"\n \".reg .b8 byte0;\\n\"\n \".reg .b8 byte1;\\n\"\n \".reg .b8 byte2;\\n\"\n \".reg .b8 byte3;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte0, %2, %1;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte1, %4, %3;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte2, %6, %5;\\n\"\n \"cvt.rn.satfinite.e2m1x2.f32 byte3, %8, %7;\\n\"\n \"mov.b32 %0, {byte0, byte1, byte2, byte3};\\n\"\n \"}\"\n : \"=r\"(val)\n : \"f\"(array[0].x), \"f\"(array[0].y), \"f\"(array[1].x), \"f\"(array[1].y), \"f\"(array[2].x),\n \"f\"(array[2].y), \"f\"(array[3].x), \"f\"(array[3].y));\n return val;\n#else\n uint32_t val;\n __nv_fp4x2_storage_t vals[4];\n#pragma unroll\n for (int i = 0; i < 4; i++) {\n vals[i] = __nv_cvt_float2_to_fp4x2(array[i], __NV_E2M1, cudaRoundNearest);\n }\n val = pack_bytes(vals[0], vals[1], vals[2], vals[3]);\n return val;\n#endif\n}\n\n// Quantizes the provided PackedVec into the uint32_t output\ntemplate <typename T, uint32_t VEC_SIZE, bool UE8M0_SF = false>\n__device__ uint32_t cvt_warp_fp16_to_fp4(vec_t<T, VEC_SIZE>& vec, float SFScaleVal,\n uint8_t* SFout) {\n#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)\n // Get absolute maximum values among the local 8 values.\n auto localMax = maths::cuda_abs(get_vec2_element(vec, 0));\n\n#pragma unroll\n for (int i = 1; i < details::CVT_FP4_ELTS_PER_THREAD / 2; i++) {\n localMax = maths::cuda_max(localMax, maths::cuda_abs(get_vec2_element(vec, i)));\n }\n\n // Get the absolute maximum among all 16 values (two threads).\n localMax = maths::cuda_max(__shfl_xor_sync(uint32_t(-1), localMax, 1), localMax);\n // Get the final absolute maximum values.\n float vecMax = float(maths::cuda_max(localMax.x, localMax.y));\n\n // Get the SF (max value of the vector / max value of e2m1).\n // maximum value of e2m1 = 6.0.\n // TODO: use half as compute data type.\n float SFValue = SFScaleVal * (vecMax * maths::reciprocal_approximate_ftz(6.0f));\n // 8 bits representation of the SF.\n uint8_t fp8SFVal;\n // Write the SF to global memory (STG.8).\n if constexpr (UE8M0_SF) {\n#if (__CUDACC_VER_MAJOR__ * 1000 + __CUDACC_VER_MINOR__ * 10 >= 12080)\n __nv_fp8_e8m0 tmp;\n tmp.__x = __nv_cvt_float_to_e8m0(SFValue, __NV_SATFINITE, cudaRoundPosInf);\n SFValue = static_cast<float>(tmp);\n fp8SFVal = tmp.__x;\n#else\n#error \"FP8 E8M0 support requires CUDA 12.8 or newer.\"\n#endif\n } else {\n // Here SFValue is always positive, so E4M3 is the same as UE4M3.\n __nv_fp8_e4m3 tmp = __nv_fp8_e4m3(SFValue);\n fp8SFVal = tmp.__x;\n SFValue = static_cast<float>(tmp);\n }\n // Get the output scale.\n // Recipe: final_scale = reciprocal(fp32(fp8(SFValue * SFScaleVal))) * reciprocal(SFScaleVal))\n float outputScale = SFValue != 0 ? maths::reciprocal_approximate_ftz(\n SFValue * maths::reciprocal_approximate_ftz(SFScaleVal))\n : 0.0f;\n\n if (SFout) {\n // Write the SF to global memory (STG.8).\n *SFout = fp8SFVal;\n }\n\n // Convert the input to float.\n float2 fp2Vals[details::CVT_FP4_ELTS_PER_THREAD / 2];\n\n#pragma unroll\n for (int i = 0; i < details::CVT_FP4_ELTS_PER_THREAD / 2; i++) {\n if constexpr (std::is_same_v<T, half>) {\n fp2Vals[i] = __half22float2(get_vec2_element(vec, i));\n } else {\n fp2Vals[i] = __bfloat1622float2(get_vec2_element(vec, i));\n }\n fp2Vals[i].x *= outputScale;\n fp2Vals[i].y *= outputScale;\n }\n\n // Convert to e2m1 values.\n uint32_t e2m1Vec = fp32_vec_to_e2m1(fp2Vals);\n\n // Write the e2m1 values to global memory.\n return e2m1Vec;\n#else\n return 0;\n#endif\n}\n\n#endif\n\n} // namespace utils\n\ntemplate <typename T, uint32_t VEC_SIZE>\n__device__ __forceinline__ vec_t<T, VEC_SIZE> vec_add(const vec_t<T, VEC_SIZE>& a,\n const vec_t<T, VEC_SIZE>& b) {\n vec_t<T, VEC_SIZE> ret;\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n ret[i] = static_cast<float>(a[i]) + static_cast<float>(b[i]);\n }\n return ret;\n}\n\nenum class AllReduceFusionPattern : int {\n kAllReduce = 0,\n kARResidualRMSNorm = 1,\n kARResidualRMSNormFP8Quant = 2,\n kARResidualRMSNormFP4Quant = 3,\n // The difference between these two and the standard version is that the NormOut version outputs\n // the result of the norm.\n kARResidualRMSNormOutFP8Quant = 4,\n kARResidualRMSNormOutFP4Quant = 5\n};\n\nenum class QuantType : int {\n kNone = 0,\n kFP8 = 1,\n kFP4 = 2,\n};\n\ntemplate <AllReduceFusionPattern Pattern>\nstruct FusionPatternTraits;\n\n#define DEFINE_FUSION_PATTERN_TRAITS(pattern, hasAllReduceOut, hasResidual, hasResidualOut, \\\n hasRMSNorm, hasNormOut, quantType) \\\n template <> \\\n struct FusionPatternTraits<pattern> { \\\n static constexpr bool kHasAllReduceOut = hasAllReduceOut; \\\n static constexpr bool kHasResidual = hasResidual; \\\n static constexpr bool kHasResidualOut = hasResidualOut; \\\n static constexpr bool kHasRMSNorm = hasRMSNorm; \\\n static constexpr bool kHasNormOut = hasNormOut; \\\n static constexpr QuantType kQuantType = quantType; \\\n };\n\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kAllReduce, true, false, false, false, false,\n QuantType::kNone);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNorm, false, true, true, true,\n true, QuantType::kNone);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNormFP8Quant, false, true, true,\n true, false, QuantType::kFP8);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNormFP4Quant, false, true, true,\n true, false, QuantType::kFP4);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNormOutFP8Quant, false, true,\n true, true, true, QuantType::kFP8);\nDEFINE_FUSION_PATTERN_TRAITS(AllReduceFusionPattern::kARResidualRMSNormOutFP4Quant, false, true,\n true, true, true, QuantType::kFP4);\n#undef DEFINE_FUSION_PATTERN_TRAITS\n\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasResidual = FusionPatternTraits<Pattern>::kHasResidual;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasRMSNorm = FusionPatternTraits<Pattern>::kHasRMSNorm;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasAllReduceOut = FusionPatternTraits<Pattern>::kHasAllReduceOut;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasResidualOut = FusionPatternTraits<Pattern>::kHasResidualOut;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr bool HasNormOut = FusionPatternTraits<Pattern>::kHasNormOut;\ntemplate <AllReduceFusionPattern Pattern>\nconstexpr QuantType GetQuantType = FusionPatternTraits<Pattern>::kQuantType;\n\ntemplate <typename T>\nstruct AllReduceFusionParams {\n int nranks;\n int rank;\n int size;\n int hidden_dim;\n void** workspace;\n void* allreduce_in;\n void* allreduce_out;\n void* residual_in;\n void* residual_out;\n void* norm_out;\n void* quant_out;\n void* scale_out;\n void* rms_gamma;\n float rms_eps;\n float* scale_factor;\n bool use_oneshot;\n QuantizationSFLayout layout = QuantizationSFLayout::SWIZZLED_128x4;\n cudaStream_t stream;\n AllReduceFusionPattern pattern;\n bool trigger_completion_at_end = true;\n};\n\ntemplate <int NRanks>\nstruct SyncComm {\n __device__ __forceinline__ SyncComm(void** workspace) {\n counter_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[0];\n flag_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[1];\n flag_value = *flag_ptr;\n for (int r = 0; r < NRanks; ++r) {\n comm_bufs[r] = workspace[r];\n barrier_flags[r] = workspace[NRanks + r];\n }\n __syncthreads();\n if (threadIdx.x == 0) {\n atomicAdd(counter_ptr, 1);\n }\n }\n\n __device__ __forceinline__ void update(int new_flag_value) {\n if (blockIdx.x == 0 && threadIdx.x == 0) {\n while (*reinterpret_cast<int volatile*>(counter_ptr) != gridDim.x) {\n }\n *flag_ptr = new_flag_value;\n *counter_ptr = 0;\n }\n }\n\n int* counter_ptr;\n int* flag_ptr;\n void* comm_bufs[NRanks];\n void* barrier_flags[NRanks];\n int flag_value;\n};\n\ntemplate <int NRanks>\nstruct LamportComm {\n __device__ __forceinline__ LamportComm(void** workspace, int rank) {\n counter_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[0];\n flag_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[2];\n clear_ptr = &reinterpret_cast<int*>(workspace[NRanks * 3])[4];\n flag_value = *flag_ptr;\n int comm_size = reinterpret_cast<int*>(workspace[NRanks * 3])[3];\n clear_size = *clear_ptr;\n int data_offset = flag_value % 3;\n int clear_offset = (flag_value + 2) % 3;\n for (int r = 0; r < NRanks; ++r) {\n data_bufs[r] = reinterpret_cast<uint8_t*>(workspace[2 * NRanks + r]) +\n static_cast<int64_t>(data_offset) * comm_size;\n }\n clear_buf = reinterpret_cast<uint8_t*>(workspace[2 * NRanks + rank]) + clear_offset * comm_size;\n __syncthreads();\n if (threadIdx.x == 0) {\n atomicAdd(counter_ptr, 1);\n }\n }\n\n __device__ __forceinline__ void update(int new_clear_size) {\n if (blockIdx.x == 0 && threadIdx.x == 0) {\n while (*reinterpret_cast<int volatile*>(counter_ptr) != gridDim.x) {\n }\n *flag_ptr = (flag_value + 1) % 3;\n *clear_ptr = new_clear_size;\n *counter_ptr = 0;\n }\n }\n\n int* counter_ptr;\n int* flag_ptr;\n int* clear_ptr;\n uint8_t* data_bufs[NRanks];\n uint8_t* clear_buf;\n int clear_size;\n int flag_value;\n};\n\ntemplate <int NRanks>\nclass Barrier {\n public:\n __device__ __forceinline__ Barrier(int rank, SyncComm<NRanks> const& comm) {\n if (threadIdx.x < NRanks) {\n m_flag_value = comm.flag_value;\n int current_rank = rank;\n int target_rank = threadIdx.x;\n m_target_flag = reinterpret_cast<int*>(comm.barrier_flags[target_rank]) + current_rank;\n m_current_flag = reinterpret_cast<int*>(comm.barrier_flags[current_rank]) +\n blockIdx.x * NRanks + target_rank;\n }\n }\n\n __device__ __forceinline__ void sync() {\n __syncthreads();\n if (threadIdx.x < NRanks) {\n m_flag_value = next_flag(m_flag_value);\n // To avoid the ABA problem, we need to synchronize the correct flag value to all\n // barrier_flags, even if the corresponding CTA has not been launched.\n for (int flag_idx = blockIdx.x; flag_idx < details::kBarrierFlagCount;\n flag_idx += gridDim.x) {\n st_flag(m_target_flag + flag_idx * NRanks, m_flag_value);\n }\n while (ld_flag(m_current_flag) == prev_flag(m_flag_value)) {\n }\n }\n __syncthreads();\n }\n\n protected:\n __device__ __forceinline__ void st_flag(int* addr, int flag) {\n asm volatile(\"st.global.release.sys.b32 [%1], %0;\" ::\"r\"(flag), \"l\"(addr));\n }\n\n __device__ __forceinline__ int ld_flag(int* addr) {\n int flag;\n asm volatile(\"ld.global.acquire.sys.b32 %0, [%1];\" : \"=r\"(flag) : \"l\"(addr));\n return flag;\n }\n\n __device__ __forceinline__ int next_flag(int flag) { return flag == 2 ? 0 : flag + 1; }\n\n __device__ __forceinline__ int prev_flag(int flag) { return flag == 0 ? 2 : flag - 1; }\n\n public:\n int m_flag_value;\n\n private:\n int* m_target_flag;\n int* m_current_flag;\n};\n\ntemplate <AllReduceFusionPattern Pattern, typename T>\nclass FusedOp {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n\n public:\n __device__ __forceinline__ FusedOp(AllReduceFusionParams<T> const& params, int access_id,\n int access_id_in_token)\n : m_params(params), m_access_id(access_id), m_access_id_in_token(access_id_in_token) {\n if constexpr (HasRMSNorm<Pattern>) {\n m_gamma_val.load(reinterpret_cast<T*>(params.rms_gamma) + m_access_id_in_token * VEC_SIZE);\n }\n if constexpr (HasResidual<Pattern>) {\n m_residual_val.load(reinterpret_cast<T*>(params.residual_in) + m_access_id * VEC_SIZE);\n }\n if constexpr (GetQuantType<Pattern> == QuantType::kFP8) {\n m_scale_factor = 1.f / *(params.scale_factor);\n } else if constexpr (GetQuantType<Pattern> == QuantType::kFP4) {\n m_scale_factor = *(params.scale_factor);\n }\n }\n\n // template <typename T>\n __device__ __forceinline__ void update(int access_id) {\n if (m_access_id != access_id) {\n m_access_id = access_id;\n if constexpr (HasResidual<Pattern>) {\n m_residual_val.load(reinterpret_cast<T*>(m_params.residual_in) + m_access_id * VEC_SIZE);\n }\n }\n }\n\n // template <typename T, uint32_t VEC_SIZE>\n __device__ __forceinline__ void operator()(vec_t<T, VEC_SIZE> val, int token_id) {\n if constexpr (HasAllReduceOut<Pattern>) {\n val.store(reinterpret_cast<T*>(m_params.allreduce_out) + m_access_id * VEC_SIZE);\n }\n if constexpr (HasResidual<Pattern>) {\n val = vec_add<T, VEC_SIZE>(val, m_residual_val);\n if constexpr (HasResidualOut<Pattern>) {\n val.store(reinterpret_cast<T*>(m_params.residual_out) + m_access_id * VEC_SIZE);\n }\n }\n if constexpr (HasRMSNorm<Pattern>) {\n val = rms_norm(val, m_gamma_val);\n if constexpr (HasNormOut<Pattern>) {\n val.store(reinterpret_cast<T*>(m_params.norm_out) + m_access_id * VEC_SIZE);\n }\n }\n\n#if CUDA_VERSION >= 12080\n if constexpr (GetQuantType<Pattern> == QuantType::kFP4) {\n // NOTE(Yingyi): might update later\n auto sf_out = utils::cvt_quant_to_fp4_get_sf_out_offset<uint32_t, 2>(\n std::nullopt /* batchIdx */, token_id, m_access_id_in_token, std::nullopt /* numRows */,\n m_params.hidden_dim, reinterpret_cast<uint32_t*>(m_params.scale_out), m_params.layout);\n reinterpret_cast<uint32_t*>(m_params.quant_out)[m_access_id] =\n utils::cvt_warp_fp16_to_fp4<T, VEC_SIZE>(val, m_scale_factor, sf_out);\n } else\n#endif\n if constexpr (GetQuantType<Pattern> == QuantType::kFP8) {\n using PackedQuantizedType = std::conditional_t<std::is_same_v<T, float>, float, float2>;\n PackedQuantizedType ret;\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n reinterpret_cast<__nv_fp8_e4m3*>(&ret)[i] = static_cast<__nv_fp8_e4m3>(\n static_cast<float>(reinterpret_cast<T*>(&val)[i]) * m_scale_factor);\n }\n reinterpret_cast<PackedQuantizedType*>(m_params.quant_out)[m_access_id] = ret;\n } else {\n static_assert(GetQuantType<Pattern> == QuantType::kNone, \"Invalid quant type\");\n }\n }\n\n protected:\n __device__ __forceinline__ vec_t<T, VEC_SIZE> rms_norm(vec_t<T, VEC_SIZE> const& residual,\n vec_t<T, VEC_SIZE> const& gamma) {\n __shared__ float s_val;\n vec_t<T, VEC_SIZE> norm_out;\n float acc = 0.f;\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n float v = static_cast<float>(reinterpret_cast<T const*>(&residual)[i]);\n acc += v * v;\n }\n utils::blockReduceSumV2<float, 1>(&acc);\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n namespace cg = cooperative_groups;\n cg::cluster_group cluster = cg::this_cluster();\n if (cluster.num_blocks() > 1) {\n if (threadIdx.x == 0) {\n s_val = acc;\n acc = 0.f;\n }\n cluster.sync();\n if (threadIdx.x == 0) {\n for (int i = 0; i < cluster.num_blocks(); ++i) {\n acc += *cluster.map_shared_rank(&s_val, i);\n }\n }\n cluster.sync();\n }\n#endif\n if (threadIdx.x == 0) {\n s_val = rsqrtf(acc / m_params.hidden_dim + m_params.rms_eps);\n }\n __syncthreads();\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n reinterpret_cast<T*>(&norm_out)[i] =\n static_cast<T>(static_cast<float>(reinterpret_cast<T const*>(&residual)[i]) * s_val *\n static_cast<float>(reinterpret_cast<T const*>(&gamma)[i]));\n }\n return norm_out;\n }\n\n private:\n AllReduceFusionParams<T> const& m_params;\n int m_access_id;\n int m_access_id_in_token;\n float m_scale_factor;\n vec_t<T, VEC_SIZE> m_residual_val;\n vec_t<T, VEC_SIZE> m_gamma_val;\n};\n\ntemplate <typename T>\nstruct neg_zero {\n static constexpr T value = -T(0);\n};\n\ntemplate <>\nstruct neg_zero<half> {\n static constexpr unsigned short neg_zero_bits = 0x8000U;\n static constexpr __half value = __half_raw{neg_zero_bits};\n};\n\ntemplate <>\nstruct neg_zero<nv_bfloat16> {\n static constexpr unsigned short neg_zero_bits = 0x8000U;\n static constexpr __nv_bfloat16 value = __nv_bfloat16_raw{neg_zero_bits};\n};\n\ntemplate <>\nstruct neg_zero<float> {\n static constexpr unsigned int neg_zero_bits = 0x80000000U;\n static constexpr float value = -0.0f;\n};\n\ntemplate <typename T>\n__device__ static constexpr T neg_zero_v = neg_zero<T>::value;\n\ntemplate <typename T>\n__device__ bool is_negative_zero(T) {\n return false;\n}\n\n// float specialization\ntemplate <>\n__device__ bool is_negative_zero<float>(float x) {\n return (__float_as_int(x) == 0x80000000);\n}\n\n// double specialization\ntemplate <>\n__device__ bool is_negative_zero<double>(double x) {\n return (__double_as_longlong(x) == 0x8000000000000000ULL);\n}\n\n// __half specialization\ntemplate <>\n__device__ bool is_negative_zero<__half>(__half x) {\n return (__half_as_ushort(x) == 0x8000);\n}\n\n// __nv_bfloat16 specialization\ntemplate <>\n__device__ bool is_negative_zero<__nv_bfloat16>(__nv_bfloat16 x) {\n return (__bfloat16_as_ushort(x) == 0x8000);\n}\n\ntemplate <typename T, uint32_t VEC_SIZE>\n__device__ __forceinline__ bool has_neg_zero(const vec_t<T, VEC_SIZE>& vec) {\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n if (is_negative_zero(vec[i])) {\n return true;\n }\n }\n return false;\n}\n\ntemplate <typename T, uint32_t VEC_SIZE>\n__device__ __forceinline__ void remove_neg_zero(vec_t<T, VEC_SIZE>& vec) {\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n vec[i] = (is_negative_zero(vec[i])) ? static_cast<T>(0.f) : vec[i];\n }\n}\n\ntemplate <typename T>\n__device__ __forceinline__ void set_neg_zero(T* addr) {\n vec_t<T, details::kBytesPerAccess / sizeof(T)> val;\n val.fill(neg_zero_v<T>);\n val.store_global_volatile(addr);\n}\n\ntemplate <typename T, uint32_t VEC_SIZE, int NRanks, bool Fp32Acc>\n__device__ __forceinline__ vec_t<T, VEC_SIZE> allreduce_sum(vec_t<T, VEC_SIZE>* vals) {\n if constexpr (Fp32Acc) {\n static_assert(!std::is_same_v<T, float>);\n float acc_f32[VEC_SIZE];\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n acc_f32[i] = static_cast<float>(reinterpret_cast<T*>(&vals[0])[i]);\n }\n#pragma unroll\n for (int r = 1; r < NRanks; ++r) {\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n acc_f32[i] += static_cast<float>(reinterpret_cast<T*>(&vals[r])[i]);\n }\n }\n vec_t<T, VEC_SIZE> acc;\n#pragma unroll\n for (int i = 0; i < VEC_SIZE; ++i) {\n acc[i] = static_cast<T>(acc_f32[i]);\n }\n return acc;\n } else {\n vec_t<T, VEC_SIZE> acc = vals[0];\n#pragma unroll\n for (int r = 1; r < NRanks; ++r) {\n acc = vec_add<T, VEC_SIZE>(acc, vals[r]);\n }\n return acc;\n }\n}\n\ntemplate <typename T>\nclass IndexHelper {\n public:\n __device__ __forceinline__ IndexHelper(AllReduceFusionParams<T> const& params) {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n namespace cg = cooperative_groups;\n cg::cluster_group cluster = cg::this_cluster();\n cg::grid_group grid = cg::this_grid();\n token_id = grid.cluster_rank();\n access_id_in_token = cluster.thread_rank();\n token_stride = grid.num_clusters();\n#else\n token_id = blockIdx.x;\n access_id_in_token = threadIdx.x;\n token_stride = gridDim.x;\n#endif\n access_id = token_id * params.hidden_dim / VEC_SIZE + access_id_in_token;\n access_stride = token_stride * params.hidden_dim / VEC_SIZE;\n tot_access = params.size / VEC_SIZE;\n }\n\n int token_id;\n int access_id_in_token;\n int token_stride;\n int access_id;\n int access_stride;\n int tot_access;\n};\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc,\n bool TriggerCompletionAtEnd = true>\n__global__ void allreduce_fusion_kernel_oneshot_lamport(AllReduceFusionParams<T> params) {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n IndexHelper<T> index_helper(params);\n int token_id = index_helper.token_id;\n int access_id_in_token = index_helper.access_id_in_token;\n int token_stride = index_helper.token_stride;\n int access_id = index_helper.access_id;\n int access_stride = index_helper.access_stride;\n int tot_access = index_helper.tot_access;\n vec_t<T, VEC_SIZE> clear_vec;\n clear_vec.fill(neg_zero_v<T>);\n FusedOp<Pattern, T> fused_op(params, access_id, access_id_in_token);\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n cudaGridDependencySynchronize();\n if constexpr (!TriggerCompletionAtEnd) {\n cudaTriggerProgrammaticLaunchCompletion();\n }\n#endif\n LamportComm<NRanks> comm(params.workspace, params.rank);\n int clear_access = comm.clear_size / VEC_SIZE;\n\n for (int idx = access_id; idx < tot_access; idx += access_stride) {\n vec_t<T, VEC_SIZE> val;\n val.load(reinterpret_cast<T*>(params.allreduce_in) + idx * VEC_SIZE);\n remove_neg_zero<T, VEC_SIZE>(val);\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n // Push data to other ranks\n val.store(reinterpret_cast<T*>(comm.data_bufs[r]) +\n (params.rank * tot_access + idx) * VEC_SIZE);\n }\n }\n for (int idx = access_id; idx < clear_access; idx += access_stride) {\n // Clear comm buffer that previous kernel used\n clear_vec.store(reinterpret_cast<T*>(comm.clear_buf) + idx * VEC_SIZE);\n }\n\n for (int idx = access_id, tidx = token_id; idx < tot_access;\n idx += access_stride, tidx += token_stride) {\n fused_op.update(idx);\n vec_t<T, VEC_SIZE> vals[NRanks];\n bool done = false;\n\n while (!done) {\n done = true;\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n // LDG.128 from local rank\n vals[r].load_global_volatile(reinterpret_cast<T*>(comm.data_bufs[params.rank]) +\n (r * tot_access + idx) * VEC_SIZE);\n done &= !has_neg_zero<T, VEC_SIZE>(vals[r]);\n }\n }\n vec_t<T, VEC_SIZE> sum_val = allreduce_sum<T, VEC_SIZE, NRanks, Fp32Acc>(vals);\n fused_op(sum_val, tidx);\n }\n\n comm.update(params.size * NRanks);\n\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n if constexpr (TriggerCompletionAtEnd) {\n cudaTriggerProgrammaticLaunchCompletion();\n }\n#endif\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc>\n__global__ void allreduce_fusion_kernel_twoshot_sync(AllReduceFusionParams<T> params,\n std::array<int, NRanks> begin_tokens,\n std::array<int, NRanks> token_num_per_ranks) {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n IndexHelper<T> index_helper(params);\n int token_id = index_helper.token_id;\n int access_id_in_token = index_helper.access_id_in_token;\n int token_stride = index_helper.token_stride;\n int access_id = index_helper.access_id;\n int access_stride = index_helper.access_stride;\n int tot_access = index_helper.tot_access;\n FusedOp<Pattern, T> fused_op(params, access_id, access_id_in_token);\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n cudaGridDependencySynchronize();\n#endif\n SyncComm<NRanks> comm(params.workspace);\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n int comm_access_id = access_id + begin_tokens[r] * params.hidden_dim / VEC_SIZE;\n int comm_tot_access = (begin_tokens[r] + token_num_per_ranks[r]) * params.hidden_dim / VEC_SIZE;\n for (int idx = comm_access_id; idx < comm_tot_access; idx += access_stride) {\n reinterpret_cast<float4*>(comm.comm_bufs[params.rank])[idx] =\n reinterpret_cast<float4*>(params.allreduce_in)[idx];\n }\n }\n Barrier<NRanks> barrier(params.rank, comm);\n barrier.sync();\n int comm_access_id = access_id + begin_tokens[params.rank] * params.hidden_dim / VEC_SIZE;\n int comm_tot_access =\n (begin_tokens[params.rank] + token_num_per_ranks[params.rank]) * params.hidden_dim / VEC_SIZE;\n for (int idx = comm_access_id; idx < comm_tot_access; idx += access_stride) {\n vec_t<T, VEC_SIZE> vals[NRanks];\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n vals[r].load(reinterpret_cast<T*>(comm.comm_bufs[r]) + idx * VEC_SIZE);\n }\n vec_t<T, VEC_SIZE> sum_val = allreduce_sum<T, VEC_SIZE, NRanks, Fp32Acc>(vals);\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n sum_val.store(reinterpret_cast<T*>(comm.comm_bufs[r]) + (tot_access + idx) * VEC_SIZE);\n }\n }\n barrier.sync();\n#pragma unroll\n for (int r = 0; r < NRanks; ++r) {\n int comm_access_id = access_id + begin_tokens[r] * params.hidden_dim / VEC_SIZE;\n int comm_token_id = token_id + begin_tokens[r];\n int comm_tot_access = (begin_tokens[r] + token_num_per_ranks[r]) * params.hidden_dim / VEC_SIZE;\n for (int idx = comm_access_id, tidx = comm_token_id; idx < comm_tot_access;\n idx += access_stride, tidx += token_stride) {\n fused_op.update(idx);\n vec_t<T, VEC_SIZE> sum_val;\n sum_val.load(reinterpret_cast<T*>(comm.comm_bufs[params.rank]) +\n (tot_access + idx) * VEC_SIZE);\n fused_op(sum_val, tidx);\n }\n }\n comm.update(barrier.m_flag_value);\n#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 900))\n cudaTriggerProgrammaticLaunchCompletion();\n#endif\n}\n\nint get_sm_count() {\n static int sm_count = 0;\n if (sm_count == 0) {\n int device_id;\n FLASHINFER_CUDA_CALL(cudaGetDevice(&device_id));\n FLASHINFER_CUDA_CALL(\n cudaDeviceGetAttribute(&sm_count, cudaDevAttrMultiProcessorCount, device_id));\n }\n return sm_count;\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc,\n bool TriggerCompletionAtEnd = true>\ncudaError_t launch_oneshot_lamport(AllReduceFusionParams<T> const& params,\n cudaLaunchConfig_t& cfg) {\n FLASHINFER_CUDA_CALL(cudaLaunchKernelEx(\n &cfg,\n allreduce_fusion_kernel_oneshot_lamport<Pattern, T, NRanks, Fp32Acc, TriggerCompletionAtEnd>,\n params));\n return cudaSuccess;\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc,\n bool TriggerCompletionAtEnd = true>\nint get_registers_per_thread_oneshot() {\n auto kernel =\n allreduce_fusion_kernel_oneshot_lamport<Pattern, T, NRanks, Fp32Acc, TriggerCompletionAtEnd>;\n cudaFuncAttributes attr;\n cudaFuncGetAttributes(&attr, kernel);\n return attr.numRegs;\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc>\ncudaError_t launch_twoshot_sync(AllReduceFusionParams<T> const& params, cudaLaunchConfig_t& cfg,\n std::array<int, NRanks> begin_tokens,\n std::array<int, NRanks> token_num_per_ranks) {\n FLASHINFER_CUDA_CALL(\n cudaLaunchKernelEx(&cfg, allreduce_fusion_kernel_twoshot_sync<Pattern, T, NRanks, Fp32Acc>,\n params, begin_tokens, token_num_per_ranks));\n return cudaSuccess;\n}\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc>\nint get_registers_per_thread_twoshot() {\n auto kernel = allreduce_fusion_kernel_twoshot_sync<Pattern, T, NRanks, Fp32Acc>;\n cudaFuncAttributes attr;\n cudaFuncGetAttributes(&attr, kernel);\n return attr.numRegs;\n}\n\nbool use_oneshot(int token_num) { return token_num <= details::kOneShotMaxToken; }\n\ntemplate <AllReduceFusionPattern Pattern, typename T, int NRanks, bool Fp32Acc>\ncudaError_t allreduce_fusion_kernel_launcher(AllReduceFusionParams<T> const& params,\n bool launch_with_pdl) {\n static constexpr int VEC_SIZE = details::kBytesPerAccess / sizeof(T);\n FLASHINFER_CHECK(params.size % params.hidden_dim == 0, \"params.size % params.hidden_dim != 0\");\n FLASHINFER_CHECK(params.hidden_dim % VEC_SIZE == 0, \"params.hidden_dim % VEC_SIZE != 0\");\n static int SM = utils::getSMVersion();\n int token_num = params.size / params.hidden_dim;\n bool oneshot = params.use_oneshot;\n int cluster_num = token_num;\n std::array<int, NRanks> begin_tokens, token_num_per_ranks;\n if (!oneshot) {\n int remaining_token = token_num % NRanks;\n int token_num_per_rank = token_num / NRanks;\n cluster_num = token_num_per_rank;\n if (remaining_token) {\n cluster_num++;\n }\n for (int r = 0; r < NRanks; ++r) {\n begin_tokens[r] = r * token_num_per_rank + (remaining_token > r ? r : remaining_token);\n token_num_per_ranks[r] = token_num_per_rank + (remaining_token > r ? 1 : 0);\n }\n }\n int threads_per_token = params.hidden_dim / VEC_SIZE;\n int cluster_size;\n if (SM >= 90) {\n cluster_size = 8;\n } else {\n cluster_size = 1;\n }\n while (threads_per_token % cluster_size != 0 && cluster_size > 1) {\n cluster_size /= 2;\n }\n int threads_per_block = threads_per_token / cluster_size;\n while (threads_per_block < 128 && cluster_size >= 2) {\n threads_per_block *= 2;\n cluster_size /= 2;\n }\n int sm_count = get_sm_count();\n int registers_per_thread;\n if (oneshot) {\n if (params.trigger_completion_at_end) {\n registers_per_thread = get_registers_per_thread_oneshot<Pattern, T, NRanks, Fp32Acc, true>();\n } else {\n registers_per_thread = get_registers_per_thread_oneshot<Pattern, T, NRanks, Fp32Acc, false>();\n }\n } else {\n registers_per_thread = get_registers_per_thread_twoshot<Pattern, T, NRanks, Fp32Acc>();\n }\n static int max_registers = -1;\n if (max_registers < 0) {\n max_registers = utils::getSMRegisters();\n }\n int max_threads_per_block = min(max_registers / registers_per_thread, 1024);\n while (cluster_num * cluster_size > sm_count && cluster_size > 1 &&\n threads_per_block <= max_threads_per_block / 2) {\n threads_per_block *= 2;\n cluster_size /= 2;\n }\n FLASHINFER_CHECK(oneshot || threads_per_block >= params.nranks,\n \"not oneshot, or threads_per_block < nranks\");\n int block_size = threads_per_block;\n FLASHINFER_CHECK(block_size <= 1024 && cluster_size > 0,\n \"block_size > 1024 or cluster_size <= 0\");\n int grid_size = (std::min(sm_count, cluster_num * cluster_size) / cluster_size) * cluster_size;\n cudaLaunchConfig_t cfg;\n cudaLaunchAttribute attribute[2];\n cfg.gridDim = grid_size;\n cfg.blockDim = block_size;\n cfg.dynamicSmemBytes = 0;\n cfg.stream = params.stream;\n attribute[0].id = cudaLaunchAttributeProgrammaticStreamSerialization;\n attribute[0].val.programmaticStreamSerializationAllowed = launch_with_pdl ? 1 : 0;\n attribute[1].id = cudaLaunchAttributeClusterDimension;\n attribute[1].val.clusterDim.x = cluster_size;\n attribute[1].val.clusterDim.y = 1;\n attribute[1].val.clusterDim.z = 1;\n cfg.attrs = attribute;\n cfg.numAttrs = SM >= 90 ? 2 : 0;\n if (oneshot) {\n bool trigger_completion_at_end = params.trigger_completion_at_end;\n if (trigger_completion_at_end) {\n FLASHINFER_CUDA_CALL(\n (launch_oneshot_lamport<Pattern, T, NRanks, Fp32Acc, true>(params, cfg)));\n } else {\n FLASHINFER_CUDA_CALL(\n (launch_oneshot_lamport<Pattern, T, NRanks, Fp32Acc, false>(params, cfg)));\n }\n } else {\n FLASHINFER_CUDA_CALL((launch_twoshot_sync<Pattern, T, NRanks, Fp32Acc>(\n params, cfg, begin_tokens, token_num_per_ranks)));\n }\n return cudaSuccess;\n}\n\ntemplate <typename T>\ncudaError_t allreduce_fusion_op(AllReduceFusionParams<T> const& params, bool launch_with_pdl,\n bool fp32_acc) {\n#define DISPATCH_ACC_TYPE(T, Pattern, NRanks) \\\n if constexpr (std::is_same_v<T, float>) { \\\n return allreduce_fusion_kernel_launcher<Pattern, T, NRanks, false>(params, launch_with_pdl); \\\n } else { \\\n if (fp32_acc) { \\\n return allreduce_fusion_kernel_launcher<Pattern, T, NRanks, true>(params, launch_with_pdl); \\\n } else { \\\n return allreduce_fusion_kernel_launcher<Pattern, T, NRanks, false>(params, launch_with_pdl); \\\n } \\\n }\n\n#define DISPATCH_PATTERN(T, NRanks) \\\n switch (params.pattern) { \\\n case AllReduceFusionPattern::kAllReduce: \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kAllReduce, NRanks); \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNorm: \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNorm, NRanks); \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNormFP8Quant: \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNormFP8Quant, NRanks); \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNormFP4Quant: \\\n if constexpr (!std::is_same_v<T, float> && CUDA_VERSION >= 12080) { \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNormFP4Quant, NRanks); \\\n } else { \\\n FLASHINFER_CHECK(CUDA_VERSION >= 12080, \"FP4Quant requires CUDA 12.8 or higher\"); \\\n FLASHINFER_CHECK(false, \"FP4Quant pattern cannot work with DType=float\"); \\\n } \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNormOutFP8Quant: \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNormOutFP8Quant, NRanks); \\\n break; \\\n case AllReduceFusionPattern::kARResidualRMSNormOutFP4Quant: \\\n if constexpr (!std::is_same_v<T, float> && CUDA_VERSION >= 12080) { \\\n DISPATCH_ACC_TYPE(T, AllReduceFusionPattern::kARResidualRMSNormOutFP4Quant, NRanks); \\\n } else { \\\n FLASHINFER_CHECK(CUDA_VERSION >= 12080, \"OutFP4Quant requires CUDA 12.8 or higher\"); \\\n FLASHINFER_CHECK(false, \"OutFP4Quant pattern cannot work with DType=float\"); \\\n } \\\n break; \\\n default: \\\n FLASHINFER_CHECK(false, \"Unsupported allreduce fusion pattern\"); \\\n }\n\n switch (params.nranks) {\n case 2:\n DISPATCH_PATTERN(T, 2);\n break;\n case 4:\n DISPATCH_PATTERN(T, 4);\n break;\n case 8:\n DISPATCH_PATTERN(T, 8);\n break;\n case 16:\n DISPATCH_PATTERN(T, 16);\n break;\n default:\n FLASHINFER_ERROR(\n \"allreduce_fusion_kernel: unsupported ranks number! Supported ranks: 2, 4, 8, 16.\");\n }\n}\n\n} // namespace trtllm_allreduce_fusion\n\n} // namespace flashinfer\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nI find the nvfp4 implemantation could only 1.3-1.4x speedup compared to fp8 in deepseek-v3-0324 model .\nand as the fp4 pflops is twice that of fp8, I think there should be some points that could be optimization.\n\nnow after applying this pr, we can get an extra 10-15% speedup on fp4.\n1369.89/1192.91=1.148 ~= 15% speedup\n\ntest cmd\n```\npython3 -m sglang.bench_serving --backend sglang --dataset-name random --num-prompts 1000 --random-input 1000 --random-output 1000 --max-concurrency 60 --port 30000 --host 0.0.0.0\n```\n\naccuracy\n```\n+------------------+-----------+----------+----------+-------+---------+---------+\n| Model | Dataset | Metric | Subset | Num | Score | Cat.0 |\n+==================+===========+==========+==========+=======+=========+=========+\n| DeepSeek-V3-0324 | aime24 | mean_acc | default | 300 | 0.5467 | default |\n+------------------+-----------+----------+----------+-------+---------+---------+ \n```\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [ ] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n\n## Summary by CodeRabbit\n\n* **Refactor**\n * Optimized FP4/FP8 quantization paths with improved register efficiency\n * Enhanced kernel launch configuration to improve GPU occupancy and performance\n * Streamlined accumulation processes to reduce memory footprint\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"e2e\", \"hardware\": null, \"model\": \"DeepSeek-V3-0324\", \"shape\": null, \"batch_size\": 60, \"metric\": \"throughput\", \"unit\": \"tok/s\", \"higher_is_better\": true, \"baseline\": 1192.91, \"optimized\": 1369.89, \"stated_speedup\": 1.148, \"speedup\": 1.1484}]"},"kernel_speedup":{"kind":"null"},"e2e_speedup":{"kind":"number","value":1.1484,"string":"1.1484"}}},{"rowIdx":1198,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"3a301a102c6a2ba7b52030910899a405bad156b0"},"date":{"kind":"string","value":"2025-12-18T21:45:15-08:00"},"pr_number":{"kind":"number","value":2215,"string":"2,215"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2215"},"title":{"kind":"string","value":"feat: further optimize top-k and add fused top-k page construction kernels for DSA (#2215)"},"message":{"kind":"string","value":"feat: further optimize top-k and add fused top-k page construction kernels for DSA (#2215)"},"path":{"kind":"string","value":"csrc/flashinfer_topk_binding.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"tvm_ffi_utils.h\"\n\nusing tvm::ffi::Optional;\n\nvoid radix_topk(TensorView input, TensorView output_indices, TensorView output_values,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k);\n\n// Radix-based Top-K selection\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(radix_topk, radix_topk);\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"tvm_ffi_utils.h\"\n\nusing tvm::ffi::Optional;\n\nvoid radix_topk(TensorView input, TensorView output_indices, TensorView output_values,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k);\n\nvoid radix_topk_page_table_transform(TensorView input, TensorView output_page_table,\n TensorView src_page_table,\n Optional<TensorView> maybe_row_to_batch, TensorView lengths,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k);\n\nvoid radix_topk_ragged_transform(TensorView input, TensorView output_indices, TensorView offsets,\n TensorView lengths, Optional<TensorView> maybe_row_states_buffer,\n int64_t top_k);\n\nbool can_implement_filtered_topk();\n\n// Radix-based Top-K selection\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(radix_topk, radix_topk);\n\n// Fused Top-K + Page Table Transform for sparse attention\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(radix_topk_page_table_transform, radix_topk_page_table_transform);\n\n// Fused Top-K + Ragged Index Transform for sparse attention\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(radix_topk_ragged_transform, radix_topk_ragged_transform);\n\n// Check if GPU supports FilteredTopK algorithm\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(can_implement_filtered_topk, can_implement_filtered_topk);\n"},"diff":{"kind":"string","value":"--- csrc/flashinfer_topk_binding.cu\n+++ csrc/flashinfer_topk_binding.cu\n@@ -20,5 +20,25 @@\n void radix_topk(TensorView input, TensorView output_indices, TensorView output_values,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k);\n \n+void radix_topk_page_table_transform(TensorView input, TensorView output_page_table,\n+ TensorView src_page_table,\n+ Optional<TensorView> maybe_row_to_batch, TensorView lengths,\n+ Optional<TensorView> maybe_row_states_buffer, int64_t top_k);\n+\n+void radix_topk_ragged_transform(TensorView input, TensorView output_indices, TensorView offsets,\n+ TensorView lengths, Optional<TensorView> maybe_row_states_buffer,\n+ int64_t top_k);\n+\n+bool can_implement_filtered_topk();\n+\n // Radix-based Top-K selection\n TVM_FFI_DLL_EXPORT_TYPED_FUNC(radix_topk, radix_topk);\n+\n+// Fused Top-K + Page Table Transform for sparse attention\n+TVM_FFI_DLL_EXPORT_TYPED_FUNC(radix_topk_page_table_transform, radix_topk_page_table_transform);\n+\n+// Fused Top-K + Ragged Index Transform for sparse attention\n+TVM_FFI_DLL_EXPORT_TYPED_FUNC(radix_topk_ragged_transform, radix_topk_ragged_transform);\n+\n+// Check if GPU supports FilteredTopK algorithm\n+TVM_FFI_DLL_EXPORT_TYPED_FUNC(can_implement_filtered_topk, can_implement_filtered_topk);"},"lines_added":{"kind":"number","value":20,"string":"20"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/flashinfer_topk_binding.cu).\n\nGoal: feat: further optimize top-k and add fused top-k page construction kernels for DSA\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include \"tvm_ffi_utils.h\"\n\nusing tvm::ffi::Optional;\n\nvoid radix_topk(TensorView input, TensorView output_indices, TensorView output_values,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k);\n\n// Radix-based Top-K selection\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(radix_topk, radix_topk);\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nFollow up of #2119 , this PR implements `top_k_page_table_transform` and `top_k_ragged_transform` function required for dsa in sglang. (fp16/bf16/fp32 are supported), as requested in #2221 .\n\nThis PR also adds the more top-k algorithm to choose from:\n1. filtered top-k (used in tilelang and sgl-kernel): store top-k candidates to shared memory, can be used for small-k\n2. multi-cta top-k (implemented in #2119): cache input at shared memory, works for any K.\n\nand add heuristics to choose between algorthms.\n\nBesides new features, this PR also moves the Top-K related functions outside of sampling.cuh (because they are not only used for sampling).\n\nBenchmark on B200 for fp32 input:\n```\n====================================================================================================\ntop_k_page_table_transform: Fused top-k + page table gather (dtype=FP32)\nNOTE: SGLang only supports k=2048 and float32\n====================================================================================================\n batch seq_len k | FlashInfer SGLang Speedup\n------------------------------------------------------------------------------------------\n 1 4096 256 | 8.13us\n 1 4096 512 | 8.32us\n 1 4096 1024 | 8.35us\n 1 4096 2048 | 8.06us 8.03us 1.00x\n 1 4096 4096 | 4.03us\n 1 16384 256 | 11.78us\n 1 16384 512 | 12.51us\n 1 16384 1024 | 13.63us\n 1 16384 2048 | 14.67us 14.85us 1.01x\n 1 16384 4096 | 20.48us\n 1 65536 256 | 31.14us\n 1 65536 512 | 31.68us\n 1 65536 1024 | 32.32us\n 1 65536 2048 | 33.63us 40.03us 1.19x\n 1 65536 4096 | 35.04us\n 1 131072 256 | 35.90us\n 1 131072 512 | 36.37us\n 1 131072 1024 | 37.09us\n 1 131072 2048 | 38.11us 68.02us 1.78x\n 1 131072 4096 | 40.67us\n 1 262144 256 | 40.56us\n 1 262144 512 | 40.77us\n 1 262144 1024 | 41.33us\n 1 262144 2048 | 42.67us 123.57us 2.90x\n 1 262144 4096 | 44.99us\n 1 524288 256 | 40.58us\n 1 524288 512 | 40.86us\n 1 524288 1024 | 41.04us\n 1 524288 2048 | 41.66us 208.86us 5.01x\n 1 524288 4096 | 43.17us\n 16 4096 256 | 8.51us\n 16 4096 512 | 8.67us\n 16 4096 1024 | 8.70us\n 16 4096 2048 | 8.32us 8.16us 0.98x\n 16 4096 4096 | 4.38us\n 16 16384 256 | 12.13us\n 16 16384 512 | 12.77us\n 16 16384 1024 | 13.86us\n 16 16384 2048 | 15.84us 15.90us 1.00x\n 16 16384 4096 | 20.93us\n 16 65536 256 | 24.19us\n 16 65536 512 | 29.63us\n 16 65536 1024 | 31.18us\n 16 65536 2048 | 33.54us 41.60us 1.24x\n 16 65536 4096 | 39.62us\n 16 131072 256 | 40.62us\n 16 131072 512 | 40.96us\n 16 131072 1024 | 50.69us\n 16 131072 2048 | 52.48us 69.63us 1.33x\n 16 131072 4096 | 45.50us\n 16 262144 256 | 45.28us\n 16 262144 512 | 45.57us\n 16 262144 1024 | 46.06us\n 16 262144 2048 | 47.30us 125.23us 2.65x\n 16 262144 4096 | 49.63us\n 16 524288 256 | 87.14us\n 16 524288 512 | 87.30us\n 16 524288 1024 | 87.97us\n 16 524288 2048 | 89.41us 211.57us 2.37x\n 16 524288 4096 | 91.90us\n 64 4096 256 | 8.74us\n 64 4096 512 | 9.60us\n 64 4096 1024 | 9.70us\n 64 4096 2048 | 8.26us 8.26us 1.00x\n 64 4096 4096 | 4.67us\n 64 16384 256 | 13.15us\n 64 16384 512 | 13.25us\n 64 16384 1024 | 14.62us\n 64 16384 2048 | 15.97us 16.35us 1.02x\n 64 16384 4096 | 21.57us\n 64 65536 256 | 24.96us\n 64 65536 512 | 30.86us\n 64 65536 1024 | 31.07us\n 64 65536 2048 | 34.66us 43.15us 1.25x\n 64 65536 4096 | 41.34us\n 64 131072 256 | 41.54us\n 64 131072 512 | 42.26us\n 64 131072 1024 | 51.71us\n 64 131072 2048 | 53.38us 71.25us 1.33x\n 64 131072 4096 | 90.32us\n 64 262144 256 | 72.61us\n 64 262144 512 | 78.94us\n 64 262144 1024 | 80.22us\n 64 262144 2048 | 96.06us 147.15us 1.53x\n 64 262144 4096 | 146.43us\n 64 524288 256 | 157.69us\n 64 524288 512 | 158.27us\n 64 524288 1024 | 170.81us\n 64 524288 2048 | 171.42us 353.32us 2.06x\n 64 524288 4096 | 229.28us\n 256 4096 256 | 16.53us\n 256 4096 512 | 17.15us\n 256 4096 1024 | 17.82us\n 256 4096 2048 | 15.87us 15.68us 0.99x\n 256 4096 4096 | 7.36us\n 256 16384 256 | 25.34us\n 256 16384 512 | 26.98us\n 256 16384 1024 | 29.22us\n 256 16384 2048 | 32.32us 33.34us 1.03x\n 256 16384 4096 | 41.86us\n 256 65536 256 | 51.73us\n 256 65536 512 | 62.02us\n 256 65536 1024 | 64.50us\n 256 65536 2048 | 72.64us 89.60us 1.23x\n 256 65536 4096 | 153.09us\n 256 131072 256 | 88.58us\n 256 131072 512 | 89.98us\n 256 131072 1024 | 108.46us\n 256 131072 2048 | 112.22us 152.14us 1.36x\n 256 131072 4096 | 260.67us\n 256 262144 256 | 173.65us\n 256 262144 512 | 186.22us\n 256 262144 1024 | 188.06us\n 256 262144 2048 | 226.05us 396.01us 1.75x\n 256 262144 4096 | 420.38us\n 256 524288 256 | 322.33us\n 256 524288 512 | 323.42us\n 256 524288 1024 | 349.85us\n 256 524288 2048 | 353.49us 709.18us 2.01x\n 256 524288 4096 | 837.13us\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Fused Top‑K transforms (page‑table and ragged) exposed in the public API, plus a public capability check for filtered Top‑K and new benchmarking CLI with algorithm and optional SGLang comparisons.\n\n* **Tests**\n * Extensive fused Top‑K test suite covering dtypes, lengths, mappings, ragged/prefill modes, algorithm modes, and SGLang comparisons.\n\n* **Documentation**\n * New Top‑K API docs and cross‑references added.\n\n* **Chores**\n * Removed legacy multi‑CTA Radix Top‑K implementation.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=4096,k=2048\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 8.06, \"optimized\": 8.03, \"stated_speedup\": 1.0, \"speedup\": 1.0037}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=16384,k=2048\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 14.67, \"optimized\": 14.85, \"stated_speedup\": 1.01, \"speedup\": 0.9879}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=65536,k=2048\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 33.63, \"optimized\": 40.03, \"stated_speedup\": 1.19, \"speedup\": 0.8401}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=131072,k=2048\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 38.11, \"optimized\": 68.02, \"stated_speedup\": 1.78, \"speedup\": 0.5603}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=262144,k=2048\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 42.67, \"optimized\": 123.57, \"stated_speedup\": 2.9, \"speedup\": 0.3453}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=524288,k=2048\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 41.66, \"optimized\": 208.86, \"stated_speedup\": 5.01, \"speedup\": 0.1995}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=4096,k=2048\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 8.32, \"optimized\": 8.16, \"stated_speedup\": 0.98, \"speedup\": 1.0196}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=16384,k=2048\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 15.84, \"optimized\": 15.9, \"stated_speedup\": 1.0, \"speedup\": 0.9962}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=65536,k=2048\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 33.54, \"optimized\": 41.6, \"stated_speedup\": 1.24, \"speedup\": 0.8062}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=131072,k=2048\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 52.48, \"optimized\": 69.63, \"stated_speedup\": 1.33, \"speedup\": 0.7537}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=262144,k=2048\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 47.3, \"optimized\": 125.23, \"stated_speedup\": 2.65, \"speedup\": 0.3777}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=524288,k=2048\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 89.41, \"optimized\": 211.57, \"stated_speedup\": 2.37, \"speedup\": 0.4226}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=4096,k=2048\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 8.26, \"optimized\": 8.26, \"stated_speedup\": 1.0, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=16384,k=2048\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 15.97, \"optimized\": 16.35, \"stated_speedup\": 1.02, \"speedup\": 0.9768}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=65536,k=2048\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 34.66, \"optimized\": 43.15, \"stated_speedup\": 1.25, \"speedup\": 0.8032}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=131072,k=2048\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 53.38, \"optimized\": 71.25, \"stated_speedup\": 1.33, \"speedup\": 0.7492}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=262144,k=2048\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 96.06, \"optimized\": 147.15, \"stated_speedup\": 1.53, \"speedup\": 0.6528}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=524288,k=2048\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 171.42, \"optimized\": 353.32, \"stated_speedup\": 2.06, \"speedup\": 0.4852}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=4096,k=2048\", \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 15.87, \"optimized\": 15.68, \"stated_speedup\": 0.99, \"speedup\": 1.0121}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=16384,k=2048\", \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 32.32, \"optimized\": 33.34, \"stated_speedup\": 1.03, \"speedup\": 0.9694}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=65536,k=2048\", \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 72.64, \"optimized\": 89.6, \"stated_speedup\": 1.23, \"speedup\": 0.8107}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=131072,k=2048\", \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 112.22, \"optimized\": 152.14, \"stated_speedup\": 1.36, \"speedup\": 0.7376}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=262144,k=2048\", \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 226.05, \"optimized\": 396.01, \"stated_speedup\": 1.75, \"speedup\": 0.5708}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=524288,k=2048\", \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 353.49, \"optimized\": 709.18, \"stated_speedup\": 2.01, \"speedup\": 0.4984}]"},"kernel_speedup":{"kind":"number","value":0.7785,"string":"0.7785"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":1199,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"3a301a102c6a2ba7b52030910899a405bad156b0"},"date":{"kind":"string","value":"2025-12-18T21:45:15-08:00"},"pr_number":{"kind":"number","value":2215,"string":"2,215"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/2215"},"title":{"kind":"string","value":"feat: further optimize top-k and add fused top-k page construction kernels for DSA (#2215)"},"message":{"kind":"string","value":"feat: further optimize top-k and add fused top-k page construction kernels for DSA (#2215)"},"path":{"kind":"string","value":"csrc/topk.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <flashinfer/sampling.cuh>\n\n#include \"tvm_ffi_utils.h\"\n\nusing namespace flashinfer;\n\nusing tvm::ffi::Optional;\n\nvoid radix_topk(TensorView input, TensorView output_indices, TensorView output_values,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_indices);\n CHECK_INPUT(output_values);\n CHECK_DIM(2, input); // input: (batch_size, d)\n CHECK_DIM(2, output_indices); // output_indices: (batch_size, top_k)\n CHECK_DIM(2, output_values); // output_values: (batch_size, top_k)\n\n unsigned int batch_size = input.size(0);\n unsigned int d = input.size(1);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n\n // Get row_states_buffer if provided (for multi-CTA path)\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::RadixTopKMultiCTA<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_indices.data_ptr()),\n static_cast<c_type*>(output_values.data_ptr()),\n nullptr, // top_k_arr\n batch_size, static_cast<uint32_t>(top_k), d, row_states_ptr, stream);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"RadixTopK failed with error code \" << cudaGetErrorString(status);\n}\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <flashinfer/sampling.cuh>\n#include <flashinfer/topk.cuh>\n\n#include \"tvm_ffi_utils.h\"\n\nusing namespace flashinfer;\n\nusing tvm::ffi::Optional;\n\nvoid radix_topk(TensorView input, TensorView output_indices, TensorView output_values,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_indices);\n CHECK_INPUT(output_values);\n CHECK_DIM(2, input); // input: (batch_size, d)\n CHECK_DIM(2, output_indices); // output_indices: (batch_size, top_k)\n CHECK_DIM(2, output_values); // output_values: (batch_size, top_k)\n\n unsigned int batch_size = input.size(0);\n unsigned int d = input.size(1);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n\n // Get row_states_buffer if provided (for multi-CTA path)\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n\n // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::TopKDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_indices.data_ptr()),\n static_cast<c_type*>(output_values.data_ptr()), batch_size, static_cast<uint32_t>(top_k), d,\n row_states_ptr, stream);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"TopK failed with error code \" << cudaGetErrorString(status);\n}\n\nvoid radix_topk_page_table_transform(TensorView input, TensorView output_page_table,\n TensorView src_page_table,\n Optional<TensorView> maybe_row_to_batch, TensorView lengths,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_page_table);\n CHECK_INPUT(src_page_table);\n CHECK_INPUT(lengths);\n CHECK_DIM(2, input); // input: (num_rows, max_len)\n CHECK_DIM(2, output_page_table); // output_page_table: (num_rows, top_k)\n CHECK_DIM(2, src_page_table); // src_page_table: (batch_size, max_len)\n CHECK_DIM(1, lengths); // lengths: (num_rows,)\n\n unsigned int num_rows = input.size(0);\n unsigned int max_len = input.size(1);\n int64_t src_stride = src_page_table.stride(0);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n\n int32_t* row_to_batch_ptr = nullptr;\n if (maybe_row_to_batch.has_value()) {\n row_to_batch_ptr = static_cast<int32_t*>(maybe_row_to_batch.value().data_ptr());\n }\n\n // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::TopKPageTableTransformDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_page_table.data_ptr()),\n static_cast<const int32_t*>(src_page_table.data_ptr()), src_stride, row_to_batch_ptr,\n static_cast<int32_t*>(lengths.data_ptr()), num_rows, static_cast<uint32_t>(top_k), max_len,\n row_states_ptr, stream);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"TopKPageTableTransform failed with error code \" << cudaGetErrorString(status);\n}\n\nvoid radix_topk_ragged_transform(TensorView input, TensorView output_indices, TensorView offsets,\n TensorView lengths, Optional<TensorView> maybe_row_states_buffer,\n int64_t top_k) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_indices);\n CHECK_INPUT(offsets);\n CHECK_INPUT(lengths);\n CHECK_DIM(2, input); // input: (num_rows, max_len)\n CHECK_DIM(2, output_indices); // output_indices: (num_rows, top_k)\n CHECK_DIM(1, offsets); // offsets: (num_rows,)\n CHECK_DIM(1, lengths); // lengths: (num_rows,)\n\n unsigned int num_rows = input.size(0);\n unsigned int max_len = input.size(1);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n\n // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::TopKRaggedTransformDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_indices.data_ptr()),\n static_cast<const int32_t*>(offsets.data_ptr()), static_cast<int32_t*>(lengths.data_ptr()),\n num_rows, static_cast<uint32_t>(top_k), max_len, row_states_ptr, stream);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"TopKRaggedTransform failed with error code \" << cudaGetErrorString(status);\n}\n\nbool can_implement_filtered_topk() { return sampling::CanImplementFilteredTopK(); }\n"},"diff":{"kind":"string","value":"--- csrc/topk.cu\n+++ csrc/topk.cu\n@@ -14,6 +14,7 @@\n * limitations under the License.\n */\n #include <flashinfer/sampling.cuh>\n+#include <flashinfer/topk.cuh>\n \n #include \"tvm_ffi_utils.h\"\n \n@@ -46,15 +47,105 @@\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n \n+ // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n- status = sampling::RadixTopKMultiCTA<c_type, int32_t>(\n+ status = sampling::TopKDispatch<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_indices.data_ptr()),\n- static_cast<c_type*>(output_values.data_ptr()),\n- nullptr, // top_k_arr\n- batch_size, static_cast<uint32_t>(top_k), d, row_states_ptr, stream);\n+ static_cast<c_type*>(output_values.data_ptr()), batch_size, static_cast<uint32_t>(top_k), d,\n+ row_states_ptr, stream);\n return true;\n });\n \n TVM_FFI_ICHECK(status == cudaSuccess)\n- << \"RadixTopK failed with error code \" << cudaGetErrorString(status);\n+ << \"TopK failed with error code \" << cudaGetErrorString(status);\n }\n+\n+void radix_topk_page_table_transform(TensorView input, TensorView output_page_table,\n+ TensorView src_page_table,\n+ Optional<TensorView> maybe_row_to_batch, TensorView lengths,\n+ Optional<TensorView> maybe_row_states_buffer, int64_t top_k) {\n+ CHECK_INPUT(input);\n+ CHECK_INPUT(output_page_table);\n+ CHECK_INPUT(src_page_table);\n+ CHECK_INPUT(lengths);\n+ CHECK_DIM(2, input); // input: (num_rows, max_len)\n+ CHECK_DIM(2, output_page_table); // output_page_table: (num_rows, top_k)\n+ CHECK_DIM(2, src_page_table); // src_page_table: (batch_size, max_len)\n+ CHECK_DIM(1, lengths); // lengths: (num_rows,)\n+\n+ unsigned int num_rows = input.size(0);\n+ unsigned int max_len = input.size(1);\n+ int64_t src_stride = src_page_table.stride(0);\n+\n+ cudaSetDevice(input.device().device_id);\n+ auto stream = get_stream(input.device());\n+\n+ cudaError_t status;\n+ auto dtype = input.dtype();\n+\n+ sampling::RadixRowState* row_states_ptr = nullptr;\n+ if (maybe_row_states_buffer.has_value()) {\n+ row_states_ptr =\n+ static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n+ }\n+\n+ int32_t* row_to_batch_ptr = nullptr;\n+ if (maybe_row_to_batch.has_value()) {\n+ row_to_batch_ptr = static_cast<int32_t*>(maybe_row_to_batch.value().data_ptr());\n+ }\n+\n+ // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n+ DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n+ status = sampling::TopKPageTableTransformDispatch<c_type, int32_t>(\n+ static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_page_table.data_ptr()),\n+ static_cast<const int32_t*>(src_page_table.data_ptr()), src_stride, row_to_batch_ptr,\n+ static_cast<int32_t*>(lengths.data_ptr()), num_rows, static_cast<uint32_t>(top_k), max_len,\n+ row_states_ptr, stream);\n+ return true;\n+ });\n+\n+ TVM_FFI_ICHECK(status == cudaSuccess)\n+ << \"TopKPageTableTransform failed with error code \" << cudaGetErrorString(status);\n+}\n+\n+void radix_topk_ragged_transform(TensorView input, TensorView output_indices, TensorView offsets,\n+ TensorView lengths, Optional<TensorView> maybe_row_states_buffer,\n+ int64_t top_k) {\n+ CHECK_INPUT(input);\n+ CHECK_INPUT(output_indices);\n+ CHECK_INPUT(offsets);\n+ CHECK_INPUT(lengths);\n+ CHECK_DIM(2, input); // input: (num_rows, max_len)\n+ CHECK_DIM(2, output_indices); // output_indices: (num_rows, top_k)\n+ CHECK_DIM(1, offsets); // offsets: (num_rows,)\n+ CHECK_DIM(1, lengths); // lengths: (num_rows,)\n+\n+ unsigned int num_rows = input.size(0);\n+ unsigned int max_len = input.size(1);\n+\n+ cudaSetDevice(input.device().device_id);\n+ auto stream = get_stream(input.device());\n+\n+ cudaError_t status;\n+ auto dtype = input.dtype();\n+\n+ sampling::RadixRowState* row_states_ptr = nullptr;\n+ if (maybe_row_states_buffer.has_value()) {\n+ row_states_ptr =\n+ static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n+ }\n+\n+ // Use unified dispatch with heuristics to choose between FilteredTopK and RadixTopK\n+ DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n+ status = sampling::TopKRaggedTransformDispatch<c_type, int32_t>(\n+ static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_indices.data_ptr()),\n+ static_cast<const int32_t*>(offsets.data_ptr()), static_cast<int32_t*>(lengths.data_ptr()),\n+ num_rows, static_cast<uint32_t>(top_k), max_len, row_states_ptr, stream);\n+ return true;\n+ });\n+\n+ TVM_FFI_ICHECK(status == cudaSuccess)\n+ << \"TopKRaggedTransform failed with error code \" << cudaGetErrorString(status);\n+}\n+\n+bool can_implement_filtered_topk() { return sampling::CanImplementFilteredTopK(); }"},"lines_added":{"kind":"number","value":96,"string":"96"},"lines_removed":{"kind":"number","value":5,"string":"5"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":[],"string":"[]","isConversational":false},"speedup_claims":{"kind":"list like","value":[],"string":"[]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/topk.cu).\n\nGoal: feat: further optimize top-k and add fused top-k page construction kernels for DSA\nTarget hardware: unspecified\nTarget models: unspecified\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2024 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <flashinfer/sampling.cuh>\n\n#include \"tvm_ffi_utils.h\"\n\nusing namespace flashinfer;\n\nusing tvm::ffi::Optional;\n\nvoid radix_topk(TensorView input, TensorView output_indices, TensorView output_values,\n Optional<TensorView> maybe_row_states_buffer, int64_t top_k) {\n CHECK_INPUT(input);\n CHECK_INPUT(output_indices);\n CHECK_INPUT(output_values);\n CHECK_DIM(2, input); // input: (batch_size, d)\n CHECK_DIM(2, output_indices); // output_indices: (batch_size, top_k)\n CHECK_DIM(2, output_values); // output_values: (batch_size, top_k)\n\n unsigned int batch_size = input.size(0);\n unsigned int d = input.size(1);\n\n cudaSetDevice(input.device().device_id);\n auto stream = get_stream(input.device());\n\n cudaError_t status;\n auto dtype = input.dtype();\n\n // Get row_states_buffer if provided (for multi-CTA path)\n sampling::RadixRowState* row_states_ptr = nullptr;\n if (maybe_row_states_buffer.has_value()) {\n row_states_ptr =\n static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());\n }\n\n DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP32_FP16(dtype, c_type, [&] {\n status = sampling::RadixTopKMultiCTA<c_type, int32_t>(\n static_cast<c_type*>(input.data_ptr()), static_cast<int32_t*>(output_indices.data_ptr()),\n static_cast<c_type*>(output_values.data_ptr()),\n nullptr, // top_k_arr\n batch_size, static_cast<uint32_t>(top_k), d, row_states_ptr, stream);\n return true;\n });\n\n TVM_FFI_ICHECK(status == cudaSuccess)\n << \"RadixTopK failed with error code \" << cudaGetErrorString(status);\n}\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nFollow up of #2119 , this PR implements `top_k_page_table_transform` and `top_k_ragged_transform` function required for dsa in sglang. (fp16/bf16/fp32 are supported), as requested in #2221 .\n\nThis PR also adds the more top-k algorithm to choose from:\n1. filtered top-k (used in tilelang and sgl-kernel): store top-k candidates to shared memory, can be used for small-k\n2. multi-cta top-k (implemented in #2119): cache input at shared memory, works for any K.\n\nand add heuristics to choose between algorthms.\n\nBesides new features, this PR also moves the Top-K related functions outside of sampling.cuh (because they are not only used for sampling).\n\nBenchmark on B200 for fp32 input:\n```\n====================================================================================================\ntop_k_page_table_transform: Fused top-k + page table gather (dtype=FP32)\nNOTE: SGLang only supports k=2048 and float32\n====================================================================================================\n batch seq_len k | FlashInfer SGLang Speedup\n------------------------------------------------------------------------------------------\n 1 4096 256 | 8.13us\n 1 4096 512 | 8.32us\n 1 4096 1024 | 8.35us\n 1 4096 2048 | 8.06us 8.03us 1.00x\n 1 4096 4096 | 4.03us\n 1 16384 256 | 11.78us\n 1 16384 512 | 12.51us\n 1 16384 1024 | 13.63us\n 1 16384 2048 | 14.67us 14.85us 1.01x\n 1 16384 4096 | 20.48us\n 1 65536 256 | 31.14us\n 1 65536 512 | 31.68us\n 1 65536 1024 | 32.32us\n 1 65536 2048 | 33.63us 40.03us 1.19x\n 1 65536 4096 | 35.04us\n 1 131072 256 | 35.90us\n 1 131072 512 | 36.37us\n 1 131072 1024 | 37.09us\n 1 131072 2048 | 38.11us 68.02us 1.78x\n 1 131072 4096 | 40.67us\n 1 262144 256 | 40.56us\n 1 262144 512 | 40.77us\n 1 262144 1024 | 41.33us\n 1 262144 2048 | 42.67us 123.57us 2.90x\n 1 262144 4096 | 44.99us\n 1 524288 256 | 40.58us\n 1 524288 512 | 40.86us\n 1 524288 1024 | 41.04us\n 1 524288 2048 | 41.66us 208.86us 5.01x\n 1 524288 4096 | 43.17us\n 16 4096 256 | 8.51us\n 16 4096 512 | 8.67us\n 16 4096 1024 | 8.70us\n 16 4096 2048 | 8.32us 8.16us 0.98x\n 16 4096 4096 | 4.38us\n 16 16384 256 | 12.13us\n 16 16384 512 | 12.77us\n 16 16384 1024 | 13.86us\n 16 16384 2048 | 15.84us 15.90us 1.00x\n 16 16384 4096 | 20.93us\n 16 65536 256 | 24.19us\n 16 65536 512 | 29.63us\n 16 65536 1024 | 31.18us\n 16 65536 2048 | 33.54us 41.60us 1.24x\n 16 65536 4096 | 39.62us\n 16 131072 256 | 40.62us\n 16 131072 512 | 40.96us\n 16 131072 1024 | 50.69us\n 16 131072 2048 | 52.48us 69.63us 1.33x\n 16 131072 4096 | 45.50us\n 16 262144 256 | 45.28us\n 16 262144 512 | 45.57us\n 16 262144 1024 | 46.06us\n 16 262144 2048 | 47.30us 125.23us 2.65x\n 16 262144 4096 | 49.63us\n 16 524288 256 | 87.14us\n 16 524288 512 | 87.30us\n 16 524288 1024 | 87.97us\n 16 524288 2048 | 89.41us 211.57us 2.37x\n 16 524288 4096 | 91.90us\n 64 4096 256 | 8.74us\n 64 4096 512 | 9.60us\n 64 4096 1024 | 9.70us\n 64 4096 2048 | 8.26us 8.26us 1.00x\n 64 4096 4096 | 4.67us\n 64 16384 256 | 13.15us\n 64 16384 512 | 13.25us\n 64 16384 1024 | 14.62us\n 64 16384 2048 | 15.97us 16.35us 1.02x\n 64 16384 4096 | 21.57us\n 64 65536 256 | 24.96us\n 64 65536 512 | 30.86us\n 64 65536 1024 | 31.07us\n 64 65536 2048 | 34.66us 43.15us 1.25x\n 64 65536 4096 | 41.34us\n 64 131072 256 | 41.54us\n 64 131072 512 | 42.26us\n 64 131072 1024 | 51.71us\n 64 131072 2048 | 53.38us 71.25us 1.33x\n 64 131072 4096 | 90.32us\n 64 262144 256 | 72.61us\n 64 262144 512 | 78.94us\n 64 262144 1024 | 80.22us\n 64 262144 2048 | 96.06us 147.15us 1.53x\n 64 262144 4096 | 146.43us\n 64 524288 256 | 157.69us\n 64 524288 512 | 158.27us\n 64 524288 1024 | 170.81us\n 64 524288 2048 | 171.42us 353.32us 2.06x\n 64 524288 4096 | 229.28us\n 256 4096 256 | 16.53us\n 256 4096 512 | 17.15us\n 256 4096 1024 | 17.82us\n 256 4096 2048 | 15.87us 15.68us 0.99x\n 256 4096 4096 | 7.36us\n 256 16384 256 | 25.34us\n 256 16384 512 | 26.98us\n 256 16384 1024 | 29.22us\n 256 16384 2048 | 32.32us 33.34us 1.03x\n 256 16384 4096 | 41.86us\n 256 65536 256 | 51.73us\n 256 65536 512 | 62.02us\n 256 65536 1024 | 64.50us\n 256 65536 2048 | 72.64us 89.60us 1.23x\n 256 65536 4096 | 153.09us\n 256 131072 256 | 88.58us\n 256 131072 512 | 89.98us\n 256 131072 1024 | 108.46us\n 256 131072 2048 | 112.22us 152.14us 1.36x\n 256 131072 4096 | 260.67us\n 256 262144 256 | 173.65us\n 256 262144 512 | 186.22us\n 256 262144 1024 | 188.06us\n 256 262144 2048 | 226.05us 396.01us 1.75x\n 256 262144 4096 | 420.38us\n 256 524288 256 | 322.33us\n 256 524288 512 | 323.42us\n 256 524288 1024 | 349.85us\n 256 524288 2048 | 353.49us 709.18us 2.01x\n 256 524288 4096 | 837.13us\n```\n\n## 🔍 Related Issues\n\n<!-- Link any related issues here -->\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n> If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/).\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n## Reviewer Notes\n\n<!-- Optional: anything you'd like reviewers to focus on, concerns, etc. -->\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Fused Top‑K transforms (page‑table and ragged) exposed in the public API, plus a public capability check for filtered Top‑K and new benchmarking CLI with algorithm and optional SGLang comparisons.\n\n* **Tests**\n * Extensive fused Top‑K test suite covering dtypes, lengths, mappings, ragged/prefill modes, algorithm modes, and SGLang comparisons.\n\n* **Documentation**\n * New Top‑K API docs and cross‑references added.\n\n* **Chores**\n * Removed legacy multi‑CTA Radix Top‑K implementation.\n\n<sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub>\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=4096,k=2048\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 8.06, \"optimized\": 8.03, \"stated_speedup\": 1.0, \"speedup\": 1.0037}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=16384,k=2048\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 14.67, \"optimized\": 14.85, \"stated_speedup\": 1.01, \"speedup\": 0.9879}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=65536,k=2048\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 33.63, \"optimized\": 40.03, \"stated_speedup\": 1.19, \"speedup\": 0.8401}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=131072,k=2048\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 38.11, \"optimized\": 68.02, \"stated_speedup\": 1.78, \"speedup\": 0.5603}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=262144,k=2048\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 42.67, \"optimized\": 123.57, \"stated_speedup\": 2.9, \"speedup\": 0.3453}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=524288,k=2048\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 41.66, \"optimized\": 208.86, \"stated_speedup\": 5.01, \"speedup\": 0.1995}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=4096,k=2048\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 8.32, \"optimized\": 8.16, \"stated_speedup\": 0.98, \"speedup\": 1.0196}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=16384,k=2048\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 15.84, \"optimized\": 15.9, \"stated_speedup\": 1.0, \"speedup\": 0.9962}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=65536,k=2048\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 33.54, \"optimized\": 41.6, \"stated_speedup\": 1.24, \"speedup\": 0.8062}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=131072,k=2048\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 52.48, \"optimized\": 69.63, \"stated_speedup\": 1.33, \"speedup\": 0.7537}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=262144,k=2048\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 47.3, \"optimized\": 125.23, \"stated_speedup\": 2.65, \"speedup\": 0.3777}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"seq_len=524288,k=2048\", \"batch_size\": 16, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 89.41, \"optimized\": 211.57, \"stated_speedup\": 2.37, \"speedup\": 0.4226}, {\"scope\": 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repo stringclasses 3
values | commit stringlengths 40 40 | date stringdate 2023-04-02 02:30:17-0500 2026-10-18 07:42:16-0500 | pr_number int64 20 61.9k ⌀ | pr_url stringlengths 44 53 ⌀ | title stringlengths 8 263 | message stringlengths 8 8k | path stringlengths 10 155 | language stringclasses 4
values | license stringclasses 4
values | before_code stringlengths 160 118k | after_code stringlengths 340 120k | diff stringlengths 149 51k | lines_added int64 0 729 | lines_removed int64 0 488 | files_in_commit int64 1 10 | models_mentioned listlengths 0 4 | hardware_mentioned listlengths 0 16 | speedup_claims listlengths 0 10 | prompt stringlengths 569 119k | pr_body stringlengths 0 24k | gains stringlengths 2 197k | kernel_speedup float64 0.78 150 ⌀ | e2e_speedup float64 0.76 136 ⌀ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
flashinfer | 5a4b54bed1dfe6f112cd4ec9bc196da517369f46 | 2026-08-03T14:43:37-07:00 | 4,285 | https://github.com/flashinfer-ai/flashinfer/pull/4285 | perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285) | perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285)
## 📌 Description
Syncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe`
and `B12xMoEWrapper` with upstream
[b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`,
reaching backend parity.
The module now has four kerne... | flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_micro_kernel.py | cute_dsl | Apache-2.0 | """
MoEMicroKernel — micro-scheduled routed NVFP4 MoE kernel for SM120/SM121 (Blackwell).
Ported from the b12x kernel library to FlashInfer.
This is the micro control-plane fusion step for decode workloads: keep the
proven FC1/FC2 compute body, but pull the route/pack frontend into the same
resident kernel, using pre... | """
MoEMicroKernel — micro-scheduled routed NVFP4 MoE kernel for SM120/SM121 (Blackwell).
Ported from the b12x kernel library to FlashInfer.
This is the micro control-plane fusion step for decode workloads: keep the
proven FC1/FC2 compute body, but pull the route/pack frontend into the same
resident kernel, using pre... | --- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_micro_kernel.py
+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_micro_kernel.py
@@ -380,9 +380,10 @@
self.acc_dtype = cutlass.Float32
self.sf_vec_size = sf_vec_size
self.input_scales_are_reciprocal = input_scales_are_reciprocal
- ... | 6 | 2 | 8 | [] | [
"RTX5080",
"SM121"
] | [
"1.06x",
"1.30x",
"1.40x",
"1.00x",
"1.00x",
"1.00x",
"1.10x",
"1.10x",
"1.09x",
"1.00x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_micro_kernel.py).
Goal: perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD
Target hardware: RTX5080, SM121
Target models: unspecified
Current file:
```python
"""
MoEMicroKernel — micro-scheduled routed NVFP4 ... | ## 📌 Description
Syncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe` and `B12xMoEWrapper` with upstream [b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`, reaching backend parity.
The module now has four kernels. `MoEDirectMicroKernel` takes the smallest decode batches, `MoEMi... | [{"scope": "e2e", "hardware": "DGX Spark", "model": null, "shape": "decode, batch 1-2", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.06, "speedup": 1.06}, {"scope": "e2e", "hardware": "RTX 5080", "model": null, "shape": "decode... | null | 1.03 |
flashinfer | 5a4b54bed1dfe6f112cd4ec9bc196da517369f46 | 2026-08-03T14:43:37-07:00 | 4,285 | https://github.com/flashinfer-ai/flashinfer/pull/4285 | perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285) | perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD (#4285)
## 📌 Description
Syncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe`
and `B12xMoEWrapper` with upstream
[b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`,
reaching backend parity.
The module now has four kerne... | flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_static_kernel.py | cute_dsl | Apache-2.0 | """
MoEStaticKernel — static-scheduled routed NVFP4 MoE kernel for SM120/SM121 (Blackwell).
Ported from the b12x kernel library to FlashInfer.
This is the current static control-plane fusion step: keep the proven FC1/FC2
compute body, but pull the route/pack frontend into the same resident kernel.
The result is still... | """
MoEStaticKernel — static-scheduled routed NVFP4 MoE kernel for SM120/SM121 (Blackwell).
Ported from the b12x kernel library to FlashInfer.
This is the current static control-plane fusion step: keep the proven FC1/FC2
compute body, but pull the route/pack frontend into the same resident kernel.
The result is still... | --- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_static_kernel.py
+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_static_kernel.py
@@ -113,12 +113,13 @@
quantize_block_fp4,
quantize_block_fp4_fast,
get_ptr_as_int64,
+ ld_shared_i32_relaxed,
st_global_f32,
st_global_i32,
share... | 78 | 34 | 8 | [] | [
"RTX5080",
"SM121"
] | [
"1.06x",
"1.30x",
"1.40x",
"1.00x",
"1.00x",
"1.00x",
"1.10x",
"1.10x",
"1.09x",
"1.00x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_static_kernel.py).
Goal: perf(moe): sync SM12x NVFP4 fused-MoE kernels to b12x HEAD
Target hardware: RTX5080, SM121
Target models: unspecified
Current file:
```python
"""
MoEStaticKernel — static-scheduled routed NVF... | ## 📌 Description
Syncs the SM12x NVFP4 (W4A4) fused-MoE kernels behind `b12x_fused_moe` and `B12xMoEWrapper` with upstream [b12x](https://github.com/local-inference-lab/sparkinfer) at `f9be272`, reaching backend parity.
The module now has four kernels. `MoEDirectMicroKernel` takes the smallest decode batches, `MoEMi... | [{"scope": "e2e", "hardware": "DGX Spark", "model": null, "shape": "decode, batch 1-2", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.06, "speedup": 1.06}, {"scope": "e2e", "hardware": "RTX 5080", "model": null, "shape": "decode... | null | 1.03 |
flashinfer | 4433996e45def64146c3aaf71341c4090a00c4fa | 2026-08-03T05:39:45-07:00 | 4,279 | https://github.com/flashinfer-ai/flashinfer/pull/4279 | feat(cake_kda): add optimized B200 recurrent decode backend (#4279) | feat(cake_kda): add optimized B200 recurrent decode backend (#4279)
## 📌 Description
This PR exports the CAKE internal recurrent-KDA decode family as 23
frozen CUDA
modules behind the existing public
`flashinfer.kda_decode.recurrent_kda` API. The export covers the exact
B200
(`sm_100a`) BF16 D128 contracts for `T=1.... | flashinfer/kda_kernels/recurrent_kda.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/kda_kernels/recurrent_kda.py
+++ flashinfer/kda_kernels/recurrent_kda.py
@@ -36,7 +36,7 @@
import functools
import math
-from typing import Callable, Optional
+from typing import Callable, Literal, Optional, cast
import cutlass
import cutlass.cute as cute
@@ -47,6 +47,12 @@
from cutlass.cute.run... | 428 | 1 | 4 | [] | [
"B200",
"CPU",
"SM100"
] | [
"1.0923x",
"1.0922x",
"1.0905x",
"1.0869x",
"1.0689x",
"1.0705x",
"1.0710x",
"1.0709x",
"1.1470x",
"1.1622x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/kda_kernels/recurrent_kda.py).
Goal: feat(cake_kda): add optimized B200 recurrent decode backend
Target hardware: B200, CPU, SM100
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache Lic... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## 📌 Description
This PR exports the CAKE internal recurrent-KDA decode family as 23 frozen CUDA
modules behind... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "T=1,H=16,HV=32", "batch_size": 8, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 7.008, "optimized": 6.336, "stated_speedup": 1.1061, "speedup": 1.1061}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "T=1,H=16... | 1.1349 | null |
flashinfer | dca55465f65ddd8513f79007b3482e9f348e62b3 | 2026-07-31T00:26:24-07:00 | 3,575 | https://github.com/flashinfer-ai/flashinfer/pull/3575 | perf: optimize trtllm_fmha_v2 fp8 causal attention q-tile scheduling & decoding for uniform seqlen (#3575) | perf: optimize trtllm_fmha_v2 fp8 causal attention q-tile scheduling & decoding for uniform seqlen (#3575)
<!-- .github/pull_request_template.md -->
## 📌 Description
The default logical order q-tile scheduling computes the heaviest (most
work) tiles last in the case of causal attention (these tiles have the
longest... | csrc/fmha_v2_run.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023-2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | /*
* Copyright (c) 2023-2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | --- csrc/fmha_v2_run.cu
+++ csrc/fmha_v2_run.cu
@@ -630,6 +630,11 @@
scale_softmax, scale_bmm2, softcapping_scale_bmm1, false, false, false, has_alibi,
skip_softmax_threshold_scale_factor);
+ // All Q lengths are equal iff they sum to b * max_q_len (each one is <= max_q_len).
+ // Padded batches decom... | 8 | 0 | 5 | [
"qwen"
] | [
"H200"
] | [
"1.28x",
"0.99x",
"1.20x",
"0.99x",
"1.08x",
"1.06x",
"1.04x",
"1.04x",
"1.00x",
"1.00x"
] | Optimize this cuda kernel file from flashinfer (csrc/fmha_v2_run.cu).
Goal: perf: optimize trtllm_fmha_v2 fp8 causal attention q-tile scheduling & decoding for uniform seqlen
Target hardware: H200
Target models: qwen
Current file:
```cuda
/*
* Copyright (c) 2023-2025 by FlashInfer team.
*
* Licensed under the Apac... | <!-- .github/pull_request_template.md -->
## 📌 Description
The default logical order q-tile scheduling computes the heaviest (most work) tiles last in the case of causal attention (these tiles have the longest KV to attend to). We currently enable reverse q-tile scheduling within heads. However, if we know the input... | [{"scope": "kernel", "hardware": "H200", "model": "qwen3-8b", "shape": null, "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 29.54, "optimized": 23.05, "stated_speedup": null, "speedup": 1.2816}, {"scope": "kernel", "hardware": "H200", "model": "qwen3-8b", "shape": null, "batc... | 1.0362 | null |
flashinfer | dca55465f65ddd8513f79007b3482e9f348e62b3 | 2026-07-31T00:26:24-07:00 | 3,575 | https://github.com/flashinfer-ai/flashinfer/pull/3575 | perf: optimize trtllm_fmha_v2 fp8 causal attention q-tile scheduling & decoding for uniform seqlen (#3575) | perf: optimize trtllm_fmha_v2 fp8 causal attention q-tile scheduling & decoding for uniform seqlen (#3575)
<!-- .github/pull_request_template.md -->
## 📌 Description
The default logical order q-tile scheduling computes the heaviest (most
work) tiles last in the case of causal attention (these tiles have the
longest... | csrc/trtllm_fmha_v2_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023-2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | /*
* Copyright (c) 2023-2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | --- csrc/trtllm_fmha_v2_binding.cu
+++ csrc/trtllm_fmha_v2_binding.cu
@@ -409,6 +409,9 @@
false, // is_s_padded
false); // has_alibi
+ // cu_seqlens is built above as i * q_seqlen, so the batch is uniform by construction.
+ params.is_uniform_q = batch_size > 0;
+
if (... | 3 | 0 | 5 | [
"qwen"
] | [
"H200"
] | [
"1.28x",
"0.99x",
"1.20x",
"0.99x",
"1.08x",
"1.06x",
"1.04x",
"1.04x",
"1.00x",
"1.00x"
] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_fmha_v2_binding.cu).
Goal: perf: optimize trtllm_fmha_v2 fp8 causal attention q-tile scheduling & decoding for uniform seqlen
Target hardware: H200
Target models: qwen
Current file:
```cuda
/*
* Copyright (c) 2023-2025 by FlashInfer team.
*
* Licensed und... | <!-- .github/pull_request_template.md -->
## 📌 Description
The default logical order q-tile scheduling computes the heaviest (most work) tiles last in the case of causal attention (these tiles have the longest KV to attend to). We currently enable reverse q-tile scheduling within heads. However, if we know the input... | [{"scope": "kernel", "hardware": "H200", "model": "qwen3-8b", "shape": null, "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 29.54, "optimized": 23.05, "stated_speedup": null, "speedup": 1.2816}, {"scope": "kernel", "hardware": "H200", "model": "qwen3-8b", "shape": null, "batc... | 1.0362 | null |
flashinfer | cd1342af6f633afaf8f1c6e1286c1e5027cae4e6 | 2026-07-28T09:03:48+08:00 | 4,152 | https://github.com/flashinfer-ai/flashinfer/pull/4152 | [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads (#4152) | [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads (#4152)
<!-- .github/pull_request_template.md -->
## 📌 Description
- Add Tier<896, 16> to the routing and post-TopK policy tables, avoiding
fallback to Tier<1024, 32>. Static-block dimensions now follow the
selected policy tier.
- Add `reduceTo... | csrc/fused_moe/trtllm_backend/trtllm_fused_moe_routing_common.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/fused_moe/trtllm_backend/trtllm_fused_moe_routing_common.cu
+++ csrc/fused_moe/trtllm_backend/trtllm_fused_moe_routing_common.cu
@@ -23,7 +23,7 @@
// and the kernel was actually launched; the definitions live in
// trtllm_fused_moe_routing_custom.cu. Keep these signatures in sync (the return
// type is not ... | 2 | 2 | 5 | [] | [
"SM90"
] | [
"1.1253x",
"1.0008x",
"1.1909x",
"1.1623x",
"1.1545x",
"1.0012x",
"1.1711x",
"1.0673x",
"1.1250x",
"1.0169x"
] | Optimize this cuda kernel file from flashinfer (csrc/fused_moe/trtllm_backend/trtllm_fused_moe_routing_common.cu).
Goal: [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads
Target hardware: SM90
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All... | <!-- .github/pull_request_template.md -->
## 📌 Description
- Add Tier<896, 16> to the routing and post-TopK policy tables, avoiding fallback to Tier<1024, 32>. Static-block dimensions now follow the selected policy tier.
- Add `reduceTopKForLane`, where each lane retains only its assigned TopK rank instead of mater... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "E=256,K=8", "batch_size": 1024, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 9.219, "optimized": 8.192, "stated_speedup": 1.1253, "speedup": 1.1254}, {"scope": "kernel", "hardware": null, "model": null, "shape": "E=256,K=8", "b... | 1.0769 | null |
flashinfer | cd1342af6f633afaf8f1c6e1286c1e5027cae4e6 | 2026-07-28T09:03:48+08:00 | 4,152 | https://github.com/flashinfer-ai/flashinfer/pull/4152 | [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads (#4152) | [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads (#4152)
<!-- .github/pull_request_template.md -->
## 📌 Description
- Add Tier<896, 16> to the routing and post-TopK policy tables, avoiding
fallback to Tier<1024, 32>. Static-block dimensions now follow the
selected policy tier.
- Add `reduceTo... | csrc/fused_moe/trtllm_backend/trtllm_fused_moe_routing_custom.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/fused_moe/trtllm_backend/trtllm_fused_moe_routing_custom.cu
+++ csrc/fused_moe/trtllm_backend/trtllm_fused_moe_routing_custom.cu
@@ -300,8 +300,10 @@
// Returns whether a compiled tier covered the runtime (numExperts, topK) and the
// kernel was actually launched. A false return means no routing output was w... | 214 | 73 | 5 | [] | [
"SM90"
] | [
"1.1253x",
"1.0008x",
"1.1909x",
"1.1623x",
"1.1545x",
"1.0012x",
"1.1711x",
"1.0673x",
"1.1250x",
"1.0169x"
] | Optimize this cuda kernel file from flashinfer (csrc/fused_moe/trtllm_backend/trtllm_fused_moe_routing_custom.cu).
Goal: [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads
Target hardware: SM90
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All... | <!-- .github/pull_request_template.md -->
## 📌 Description
- Add Tier<896, 16> to the routing and post-TopK policy tables, avoiding fallback to Tier<1024, 32>. Static-block dimensions now follow the selected policy tier.
- Add `reduceTopKForLane`, where each lane retains only its assigned TopK rank instead of mater... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "E=256,K=8", "batch_size": 1024, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 9.219, "optimized": 8.192, "stated_speedup": 1.1253, "speedup": 1.1254}, {"scope": "kernel", "hardware": null, "model": null, "shape": "E=256,K=8", "b... | 1.0769 | null |
flashinfer | cd1342af6f633afaf8f1c6e1286c1e5027cae4e6 | 2026-07-28T09:03:48+08:00 | 4,152 | https://github.com/flashinfer-ai/flashinfer/pull/4152 | [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads (#4152) | [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads (#4152)
<!-- .github/pull_request_template.md -->
## 📌 Description
- Add Tier<896, 16> to the routing and post-TopK policy tables, avoiding
fallback to Tier<1024, 32>. Static-block dimensions now follow the
selected policy tier.
- Add `reduceTo... | include/flashinfer/trtllm/fused_moe/RoutingCustomPolicy.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/trtllm/fused_moe/RoutingCustomPolicy.cuh
+++ include/flashinfer/trtllm/fused_moe/RoutingCustomPolicy.cuh
@@ -393,6 +393,7 @@
struct ScaledSumNormalizePostprocess {
/// Opts into the block-per-token kernel (provides applyWithAux below).
static constexpr bool kSupportsBlockPerToken = true;
+... | 87 | 2 | 5 | [] | [
"SM90"
] | [
"1.1253x",
"1.0008x",
"1.1909x",
"1.1623x",
"1.1545x",
"1.0012x",
"1.1711x",
"1.0673x",
"1.1250x",
"1.0169x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/trtllm/fused_moe/RoutingCustomPolicy.cuh).
Goal: [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads
Target hardware: SM90
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All righ... | <!-- .github/pull_request_template.md -->
## 📌 Description
- Add Tier<896, 16> to the routing and post-TopK policy tables, avoiding fallback to Tier<1024, 32>. Static-block dimensions now follow the selected policy tier.
- Add `reduceTopKForLane`, where each lane retains only its assigned TopK rank instead of mater... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "E=256,K=8", "batch_size": 1024, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 9.219, "optimized": 8.192, "stated_speedup": 1.1253, "speedup": 1.1254}, {"scope": "kernel", "hardware": null, "model": null, "shape": "E=256,K=8", "b... | 1.0769 | null |
flashinfer | cd1342af6f633afaf8f1c6e1286c1e5027cae4e6 | 2026-07-28T09:03:48+08:00 | 4,152 | https://github.com/flashinfer-ai/flashinfer/pull/4152 | [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads (#4152) | [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads (#4152)
<!-- .github/pull_request_template.md -->
## 📌 Description
- Add Tier<896, 16> to the routing and post-TopK policy tables, avoiding
fallback to Tier<1024, 32>. Static-block dimensions now follow the
selected policy tier.
- Add `reduceTo... | include/flashinfer/trtllm/fused_moe/RoutingKernel.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/trtllm/fused_moe/RoutingKernel.cuh
+++ include/flashinfer/trtllm/fused_moe/RoutingKernel.cuh
@@ -267,12 +267,16 @@
using OutputT = typename KernelParams::OutputT;
using TypePacked = PackedScoreIdx<BaseType>;
- // When MaxNumExperts > NumThreads, each thread handles multiple experts.
+ /... | 15 | 6 | 5 | [] | [
"SM90"
] | [
"1.1253x",
"1.0008x",
"1.1909x",
"1.1623x",
"1.1545x",
"1.0012x",
"1.1711x",
"1.0673x",
"1.1250x",
"1.0169x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/trtllm/fused_moe/RoutingKernel.cuh).
Goal: [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads
Target hardware: SM90
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights res... | <!-- .github/pull_request_template.md -->
## 📌 Description
- Add Tier<896, 16> to the routing and post-TopK policy tables, avoiding fallback to Tier<1024, 32>. Static-block dimensions now follow the selected policy tier.
- Add `reduceTopKForLane`, where each lane retains only its assigned TopK rank instead of mater... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "E=256,K=8", "batch_size": 1024, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 9.219, "optimized": 8.192, "stated_speedup": 1.1253, "speedup": 1.1254}, {"scope": "kernel", "hardware": null, "model": null, "shape": "E=256,K=8", "b... | 1.0769 | null |
flashinfer | cd1342af6f633afaf8f1c6e1286c1e5027cae4e6 | 2026-07-28T09:03:48+08:00 | 4,152 | https://github.com/flashinfer-ai/flashinfer/pull/4152 | [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads (#4152) | [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads (#4152)
<!-- .github/pull_request_template.md -->
## 📌 Description
- Add Tier<896, 16> to the routing and post-TopK policy tables, avoiding
fallback to Tier<1024, 32>. Static-block dimensions now follow the
selected policy tier.
- Add `reduceTo... | include/flashinfer/trtllm/fused_moe/RoutingKernelTopK.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/trtllm/fused_moe/RoutingKernelTopK.cuh
+++ include/flashinfer/trtllm/fused_moe/RoutingKernelTopK.cuh
@@ -320,6 +320,70 @@
}
};
+/// Capability envelope for the high-expert lane-owned routing specialization.
+/// This predicate is shared by compile-time tier selection and runtime dispatch;
+... | 64 | 0 | 5 | [] | [
"SM90"
] | [
"1.1253x",
"1.0008x",
"1.1909x",
"1.1623x",
"1.1545x",
"1.0012x",
"1.1711x",
"1.0673x",
"1.1250x",
"1.0169x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/trtllm/fused_moe/RoutingKernelTopK.cuh).
Goal: [perf] Optimize TRT-LLM routing for high-expert, high-top-k workloads
Target hardware: SM90
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights... | <!-- .github/pull_request_template.md -->
## 📌 Description
- Add Tier<896, 16> to the routing and post-TopK policy tables, avoiding fallback to Tier<1024, 32>. Static-block dimensions now follow the selected policy tier.
- Add `reduceTopKForLane`, where each lane retains only its assigned TopK rank instead of mater... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "E=256,K=8", "batch_size": 1024, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 9.219, "optimized": 8.192, "stated_speedup": 1.1253, "speedup": 1.1254}, {"scope": "kernel", "hardware": null, "model": null, "shape": "E=256,K=8", "b... | 1.0769 | null |
flashinfer | f057e15bdf8285509f86bac3004adf25a274f121 | 2026-07-28T03:03:54+08:00 | 4,133 | https://github.com/flashinfer-ai/flashinfer/pull/4133 | [GDN] improve sm100 GDN performance (#4133) | [GDN] improve sm100 GDN performance (#4133)
## What
Optimizes the Blackwell SM100 chunk-stream Gated Delta Net (GDN) prefill
kernel.
Coauthored by @guangyunh-nv @jhjpark
## Test environment
- **GPU:** NVIDIA B300 SXM6 AC — Blackwell (SM100)
- **Compile:** `--enable-tvm-ffi --opt-level 3`
- **Dtype:** bf16 in/out, ... | flashinfer/gdn_kernels/blackwell/gdn_prefill.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/gdn_kernels/blackwell/gdn_prefill.py
+++ flashinfer/gdn_kernels/blackwell/gdn_prefill.py
@@ -207,6 +207,10 @@
gdn = GatedDeltaNetChunkedKernel(
io_dtype=io_dtype,
+ # The kernel requires the triangular-inverse dtype to match io_dtype
+ # (asserted in its __in... | 5 | 1 | 2 | [] | [
"B300",
"BLACKWELL",
"SM100"
] | [
"1.25x",
"1.07x",
"1.32x",
"1.29x",
"1.28x",
"1.28x",
"1.28x",
"1.28x",
"1.31x",
"1.27x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/blackwell/gdn_prefill.py).
Goal: [GDN] improve sm100 GDN performance
Target hardware: B300, BLACKWELL, SM100
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Vers... | ## What
Optimizes the Blackwell SM100 chunk-stream Gated Delta Net (GDN) prefill kernel.
Coauthored by @guangyunh-nv @jhjpark
## Test environment
- **GPU:** NVIDIA B300 SXM6 AC — Blackwell (SM100)
- **Compile:** `--enable-tvm-ffi --opt-level 3`
- **Dtype:** bf16 in/out, fp32 state + accumulation
- **Benchmark:** `b... | [{"scope": "kernel", "hardware": "B300 SXM6 AC", "model": null, "shape": "h_qk/h_v=2/8, seqlen=1x65536", "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 2.352, "optimized": 1.827, "stated_speedup": 1.29, "speedup": 1.2874}, {"scope": "kernel", "hardware": "B300 SXM6 AC", "m... | 1.264 | null |
flashinfer | 0f5bb82457f3c79c1747c951eecab9f658cea351 | 2026-07-23T21:48:03+08:00 | 4,063 | https://github.com/flashinfer-ai/flashinfer/pull/4063 | perf(sm103): optimize NVFP4 epilogue stores and scaling (#4063) | perf(sm103): optimize NVFP4 epilogue stores and scaling (#4063)
## 📌 Description
This PR optimizes the native SM103 (`CTA_K=768`) CUTLASS NVFP4 GEMM
epilogue:
- Keeps the source/C alignment at 128 bits and raises the D/output
alignment to 256 bits, enabling 256-bit global stores in the native
SM103 no-smem epilogue... | csrc/fp4_gemm_cutlass_sm103.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/fp4_gemm_cutlass_sm103.cu
+++ csrc/fp4_gemm_cutlass_sm103.cu
@@ -99,6 +99,7 @@
int64_t tactic) {
CHECK_INPUT_AND_TYPE(mat1, FLOAT4_E2M1X2);
CHECK_INPUT_AND_TYPE(mat2, FLOAT4_E2M1X2);
+ CHECK_INPUT(out);
int mat2_k_scale = 1;
| 1 | 0 | 6 | [] | [
"B300",
"SM100",
"SM103"
] | [
"1.115×",
"1.120×",
"1.157×",
"1.161×"
] | Optimize this cuda kernel file from flashinfer (csrc/fp4_gemm_cutlass_sm103.cu).
Goal: perf(sm103): optimize NVFP4 epilogue stores and scaling
Target hardware: B300, SM100, SM103
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed un... | ## 📌 Description
This PR optimizes the native SM103 (`CTA_K=768`) CUTLASS NVFP4 GEMM epilogue:
- Keeps the source/C alignment at 128 bits and raises the D/output alignment to 256 bits, enabling 256-bit global stores in the native SM103 no-smem epilogue.
- Adds a local CUTLASS fusion callback that evaluates `alpha * ... | [{"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.115, "speedup": 1.115}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "me... | null | 1.1385 |
flashinfer | 0f5bb82457f3c79c1747c951eecab9f658cea351 | 2026-07-23T21:48:03+08:00 | 4,063 | https://github.com/flashinfer-ai/flashinfer/pull/4063 | perf(sm103): optimize NVFP4 epilogue stores and scaling (#4063) | perf(sm103): optimize NVFP4 epilogue stores and scaling (#4063)
## 📌 Description
This PR optimizes the native SM103 (`CTA_K=768`) CUTLASS NVFP4 GEMM
epilogue:
- Keeps the source/C alignment at 128 bits and raises the D/output
alignment to 256 bits, enabling 256-bit global stores in the native
SM103 no-smem epilogue... | include/flashinfer/gemm/fp4_gemm_cutlass_template_sm103.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/fp4_gemm_cutlass_template_sm103.h
+++ include/flashinfer/gemm/fp4_gemm_cutlass_template_sm103.h
@@ -17,6 +17,9 @@
#ifndef FLASHINFER_FP4_GEMM_CUTLASS_TEMPLATE_H_
#define FLASHINFER_FP4_GEMM_CUTLASS_TEMPLATE_H_
+#include <algorithm>
+#include <cstdint>
+
#ifndef _WIN32
#pragma GCC diagn... | 98 | 18 | 6 | [] | [
"B300",
"SM100",
"SM103"
] | [
"1.115×",
"1.120×",
"1.157×",
"1.161×"
] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp4_gemm_cutlass_template_sm103.h).
Goal: perf(sm103): optimize NVFP4 epilogue stores and scaling
Target hardware: B300, SM100, SM103
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights re... | ## 📌 Description
This PR optimizes the native SM103 (`CTA_K=768`) CUTLASS NVFP4 GEMM epilogue:
- Keeps the source/C alignment at 128 bits and raises the D/output alignment to 256 bits, enabling 256-bit global stores in the native SM103 no-smem epilogue.
- Adds a local CUTLASS fusion callback that evaluates `alpha * ... | [{"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.115, "speedup": 1.115}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "me... | null | 1.1385 |
flashinfer | 0f5bb82457f3c79c1747c951eecab9f658cea351 | 2026-07-23T21:48:03+08:00 | 4,063 | https://github.com/flashinfer-ai/flashinfer/pull/4063 | perf(sm103): optimize NVFP4 epilogue stores and scaling (#4063) | perf(sm103): optimize NVFP4 epilogue stores and scaling (#4063)
## 📌 Description
This PR optimizes the native SM103 (`CTA_K=768`) CUTLASS NVFP4 GEMM
epilogue:
- Keeps the source/C alignment at 128 bits and raises the D/output
alignment to 256 bits, enabling 256-bit global stores in the native
SM103 no-smem epilogue... | include/flashinfer/gemm/fp4_gemm_template_sm100.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/fp4_gemm_template_sm100.h
+++ include/flashinfer/gemm/fp4_gemm_template_sm100.h
@@ -36,6 +36,9 @@
namespace flashinfer {
namespace gemm {
+#if defined(FLASHINFER_SM103_GENERIC_STORE256_NAMESPACE)
+namespace sm103_generic_store256 {
+#endif
using namespace cute;
#ifdef ENABLE_BF16
@@ ... | 30 | 4 | 6 | [] | [
"B300",
"SM100",
"SM103"
] | [
"1.115×",
"1.120×",
"1.157×",
"1.161×"
] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp4_gemm_template_sm100.h).
Goal: perf(sm103): optimize NVFP4 epilogue stores and scaling
Target hardware: B300, SM100, SM103
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
... | ## 📌 Description
This PR optimizes the native SM103 (`CTA_K=768`) CUTLASS NVFP4 GEMM epilogue:
- Keeps the source/C alignment at 128 bits and raises the D/output alignment to 256 bits, enabling 256-bit global stores in the native SM103 no-smem epilogue.
- Adds a local CUTLASS fusion callback that evaluates `alpha * ... | [{"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.115, "speedup": 1.115}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "me... | null | 1.1385 |
flashinfer | 0f5bb82457f3c79c1747c951eecab9f658cea351 | 2026-07-23T21:48:03+08:00 | 4,063 | https://github.com/flashinfer-ai/flashinfer/pull/4063 | perf(sm103): optimize NVFP4 epilogue stores and scaling (#4063) | perf(sm103): optimize NVFP4 epilogue stores and scaling (#4063)
## 📌 Description
This PR optimizes the native SM103 (`CTA_K=768`) CUTLASS NVFP4 GEMM
epilogue:
- Keeps the source/C alignment at 128 bits and raises the D/output
alignment to 256 bits, enabling 256-bit global stores in the native
SM103 no-smem epilogue... | include/flashinfer/gemm/fp4_gemm_template_sm103.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/fp4_gemm_template_sm103.h
+++ include/flashinfer/gemm/fp4_gemm_template_sm103.h
@@ -29,6 +29,7 @@
#include "cutlass/gemm/gemm.h"
#include "flashinfer/arch_condition.h"
#include "flashinfer/cutlass_utils.cuh"
+#include "flashinfer/gemm/fp4_gemm_epilogue_sm103.h"
#ifndef _WIN32
#pragma ... | 7 | 4 | 6 | [] | [
"B300",
"SM100",
"SM103"
] | [
"1.115×",
"1.120×",
"1.157×",
"1.161×"
] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp4_gemm_template_sm103.h).
Goal: perf(sm103): optimize NVFP4 epilogue stores and scaling
Target hardware: B300, SM100, SM103
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
... | ## 📌 Description
This PR optimizes the native SM103 (`CTA_K=768`) CUTLASS NVFP4 GEMM epilogue:
- Keeps the source/C alignment at 128 bits and raises the D/output alignment to 256 bits, enabling 256-bit global stores in the native SM103 no-smem epilogue.
- Adds a local CUTLASS fusion callback that evaluates `alpha * ... | [{"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.115, "speedup": 1.115}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "me... | null | 1.1385 |
flashinfer | 5e891c6bbde7e02eaedbda92760e30185e6d6f55 | 2026-07-21T18:53:27-07:00 | 3,697 | https://github.com/flashinfer-ai/flashinfer/pull/3697 | Port the TensorRT-LLM one-sided A2A optimizations to Flashinfer (#3697) | Port the TensorRT-LLM one-sided A2A optimizations to Flashinfer (#3697)
<!-- .github/pull_request_template.md -->
## 📌 Description
Needs testing and comparison to TRTLLM ToT
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Related Issues
<!-- Link any related issues here ... | csrc/nv_internal/tensorrt_llm/common/envUtils.h | cpp | Apache-2.0 | /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights
* reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights
* reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | --- csrc/nv_internal/tensorrt_llm/common/envUtils.h
+++ csrc/nv_internal/tensorrt_llm/common/envUtils.h
@@ -16,10 +16,14 @@
*/
#pragma once
+#include <cuda_runtime_api.h>
+
#include <cstdint>
#include <optional>
#include <string>
+#include <utility>
+#include "flashinfer/exception.h"
#include "tensorrt_llm/c... | 23 | 0 | 7 | [] | [
"B300"
] | [] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/common/envUtils.h).
Goal: Port the TensorRT-LLM one-sided A2A optimizations to Flashinfer
Target hardware: B300
Target models: unspecified
Current file:
```cpp
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILI... | <!-- .github/pull_request_template.md -->
## 📌 Description
Needs testing and comparison to TRTLLM ToT
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInf... | [] | null | null |
flashinfer | 5e891c6bbde7e02eaedbda92760e30185e6d6f55 | 2026-07-21T18:53:27-07:00 | 3,697 | https://github.com/flashinfer-ai/flashinfer/pull/3697 | Port the TensorRT-LLM one-sided A2A optimizations to Flashinfer (#3697) | Port the TensorRT-LLM one-sided A2A optimizations to Flashinfer (#3697)
<!-- .github/pull_request_template.md -->
## 📌 Description
Needs testing and comparison to TRTLLM ToT
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Related Issues
<!-- Link any related issues here ... | csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.h | cpp | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.h
+++ csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.h
@@ -24,6 +24,9 @@
static constexpr int kMaxTopK = 22; // Maximum supported top-k experts per token
static constexpr int kMaxPayloads = 6; // Maxi... | 59 | 4 | 7 | [] | [
"B300"
] | [] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.h).
Goal: Port the TensorRT-LLM one-sided A2A optimizations to Flashinfer
Target hardware: B300
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2025, NVIDIA CORPORATION. Al... | <!-- .github/pull_request_template.md -->
## 📌 Description
Needs testing and comparison to TRTLLM ToT
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInf... | [] | null | null |
flashinfer | 5e891c6bbde7e02eaedbda92760e30185e6d6f55 | 2026-07-21T18:53:27-07:00 | 3,697 | https://github.com/flashinfer-ai/flashinfer/pull/3697 | Port the TensorRT-LLM one-sided A2A optimizations to Flashinfer (#3697) | Port the TensorRT-LLM one-sided A2A optimizations to Flashinfer (#3697)
<!-- .github/pull_request_template.md -->
## 📌 Description
Needs testing and comparison to TRTLLM ToT
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Related Issues
<!-- Link any related issues here ... | csrc/nv_internal/tensorrt_llm/thop/moeAlltoAllMeta.h | cpp | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/nv_internal/tensorrt_llm/thop/moeAlltoAllMeta.h
+++ csrc/nv_internal/tensorrt_llm/thop/moeAlltoAllMeta.h
@@ -36,8 +36,9 @@
COMBINE_COMPLETION_FLAGS_OFFSET_INDEX = 5,
TOPK_TARGET_RANKS_OFFSET_INDEX = 6,
TOPK_SEND_INDICES_OFFSET_INDEX = 7,
- PAYLOAD_DATA_OFFSET_INDEX = 8,
- NUM_METAINFO_FIELDS = 9
+ ... | 4 | 2 | 7 | [] | [
"B300"
] | [] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/thop/moeAlltoAllMeta.h).
Goal: Port the TensorRT-LLM one-sided A2A optimizations to Flashinfer
Target hardware: B300
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Li... | <!-- .github/pull_request_template.md -->
## 📌 Description
Needs testing and comparison to TRTLLM ToT
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInf... | [] | null | null |
flashinfer | 5e891c6bbde7e02eaedbda92760e30185e6d6f55 | 2026-07-21T18:53:27-07:00 | 3,697 | https://github.com/flashinfer-ai/flashinfer/pull/3697 | Port the TensorRT-LLM one-sided A2A optimizations to Flashinfer (#3697) | Port the TensorRT-LLM one-sided A2A optimizations to Flashinfer (#3697)
<!-- .github/pull_request_template.md -->
## 📌 Description
Needs testing and comparison to TRTLLM ToT
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Related Issues
<!-- Link any related issues here ... | csrc/trtllm_moe_alltoall.cu | cuda | Apache-2.0 | /*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the ... | /*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the ... | --- csrc/trtllm_moe_alltoall.cu
+++ csrc/trtllm_moe_alltoall.cu
@@ -52,7 +52,40 @@
return (offset + alignment - 1) & ~(alignment - 1);
}
-fi_throughput::MoeA2ADataOffsets calculateOffsets(int epSize, int maxNumTokens) {
+inline bool hasActiveRankMask(Optional<TensorView> const& maskTensor) {
+ return maskTensor.... | 153 | 26 | 7 | [] | [
"B300"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_moe_alltoall.cu).
Goal: Port the TensorRT-LLM one-sided A2A optimizations to Flashinfer
Target hardware: B300
Target models: unspecified
Current file:
```cuda
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION &
* AFFILIATES. All right... | <!-- .github/pull_request_template.md -->
## 📌 Description
Needs testing and comparison to TRTLLM ToT
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInf... | [] | null | null |
flashinfer | 97f3b035a1f2bfaa94b5f636b169d8fd35bcf2b7 | 2026-07-18T00:43:03+02:00 | 3,846 | https://github.com/flashinfer-ai/flashinfer/pull/3846 | perf(moe): optimize one-sided EP4 NVFP4 dispatch (#3846) | perf(moe): optimize one-sided EP4 NVFP4 dispatch (#3846)
## Summary
Optimize one-sided MoE dispatch by:
- constructing routing metadata cooperatively across a warp instead of
using a
serial thread-0 loop;
- retaining one compact destination per rank when `ep_size == 4` and
`top_k > 4`;
- using a 128-thread CTA f... | csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | /*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requi... | --- csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu
+++ csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu
@@ -30,6 +30,10 @@
#define ENABLE_DEBUG_PRINT 0
#define DISABLE_SYNC_FOR_PROFILING 0
+
+constexpr int kEp4Size = 4;
+constexpr int kCompactDispatc... | 101 | 52 | 1 | [
"nemotron"
] | [
"GB200"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu).
Goal: perf(moe): optimize one-sided EP4 NVFP4 dispatch
Target hardware: GB200
Target models: nemotron
Current file:
```cuda
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reser... | ## Summary
Optimize one-sided MoE dispatch by:
- constructing routing metadata cooperatively across a warp instead of using a
serial thread-0 loop;
- retaining one compact destination per rank when `ep_size == 4` and
`top_k > 4`;
- using a 128-thread CTA for that compact path when every payload is at most
1,024... | [{"scope": "kernel", "hardware": "GB200", "model": "H2048 NVFP4", "shape": "EP4, top-k22", "batch_size": 4, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 19.68, "optimized": 13.79, "stated_speedup": null, "speedup": 1.4271}, {"scope": "kernel", "hardware": "GB200", "model": "H2048 NVFP4", "s... | 1.589 | 1.0551 |
flashinfer | 37ce0366fd324c6b026f190aba7123be8ca3eb95 | 2026-07-18T02:22:31+05:30 | 3,908 | https://github.com/flashinfer-ai/flashinfer/pull/3908 | Ameyn/gdn wy perf followup (#3908) | Ameyn/gdn wy perf followup (#3908)
## 📌 Stacked on #3720
This branch builds on #3720's head (`00a655e`); the diff will show its
commits until it merges. **Review only the 5 commits listed below.**
Once #3720 lands, the diff collapses to just these changes (one rebase
needed only if #3720 is squash-merged).
## What
... | flashinfer/gdn_kernels/gdn_decode_bf16_wy_output_only.py | cute_dsl | Apache-2.0 | """CuTeDSL GDN MTP Decode Kernel — WY-parallel, NOPREPACK variant.
v6 (TMA + SW128 swizzle on H tile):
- Replaces v5's 4-stage staggered cp.async H load with a single
`cp.async.bulk.tensor.4d.shared.cluster.global` TMA issued once per CTA.
- sH SMEM tile is allocated as a SW128-swizzled tensor (mandatory for the
T... | """CuTeDSL GDN MTP Decode Kernel — WY-parallel, NOPREPACK variant.
v6 (TMA + SW128 swizzle on H tile):
- Replaces v5's 4-stage staggered cp.async H load with a single
`cp.async.bulk.tensor.4d.shared.cluster.global` TMA issued once per CTA.
- sH SMEM tile is allocated as a SW128-swizzled tensor (mandatory for the
T... | --- flashinfer/gdn_kernels/gdn_decode_bf16_wy_output_only.py
+++ flashinfer/gdn_kernels/gdn_decode_bf16_wy_output_only.py
@@ -305,28 +305,6 @@
return Int32(r)
-def _st_global_bf16x2_f32(base_addr_i64, bf16_elem_offset, lo_f32, hi_f32):
- r = llvm.inline_asm(
- mlir_T.i32(),
- [
- ba... | 113 | 48 | 1 | [] | [
"B200",
"SM100"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/gdn_decode_bf16_wy_output_only.py).
Goal: Ameyn/gdn wy perf followup
Target hardware: B200, SM100
Target models: unspecified
Current file:
```python
"""CuTeDSL GDN MTP Decode Kernel — WY-parallel, NOPREPACK variant.
v6 (TMA + SW128 swizzle on... | ## 📌 Stacked on #3720
This branch builds on #3720's head (`00a655e`); the diff will show its commits until it merges. **Review only the 5 commits listed below.** Once #3720 lands, the diff collapses to just these changes (one rebase needed only if #3720 is squash-merged).
## What
Performance and correctness follow-... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "T=4", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 5.28, "optimized": 5.12, "stated_speedup": null, "speedup": 1.0312}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "T=8", "batch_size": 1, ... | 1.0589 | null |
flashinfer | c27cb0e5b06818cffb609bd53b204560ec27d281 | 2026-07-16T13:31:45-07:00 | 3,524 | https://github.com/flashinfer-ai/flashinfer/pull/3524 | perf: vectorize AppendPagedKVMlaCache to 128-bit access (#3524) | perf: vectorize AppendPagedKVMlaCache to 128-bit access (#3524)
<!-- .github/pull_request_template.md -->
## 📌 Description
`AppendPagedKVMlaCache` (the MLA paged-KV append used by DeepSeek-V3/R1
MLA serving) hard-coded `vec_size = 2`, i.e. 4-byte (2× bf16) global
loads/stores. With `head_dim_ckv=512` this leaves th... | include/flashinfer/page.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/page.cuh
+++ include/flashinfer/page.cuh
@@ -851,7 +851,8 @@
constexpr uint32_t HEAD_KPE_DIM = 64;
FLASHINFER_CHECK(head_dim_ckv == HEAD_CKV_DIM, "head_dim_ckv must be equal to 512");
FLASHINFER_CHECK(head_dim_kpe == HEAD_KPE_DIM, "head_dim_kpe must be equal to 64");
- constexpr uint32_... | 2 | 1 | 1 | [
"deepseek"
] | [
"H200"
] | [
"2×",
"4×",
"1.80×",
"1.80×",
"1.87×"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/page.cuh).
Goal: perf: vectorize AppendPagedKVMlaCache to 128-bit access
Target hardware: H200
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "Licens... | <!-- .github/pull_request_template.md -->
## 📌 Description
`AppendPagedKVMlaCache` (the MLA paged-KV append used by DeepSeek-V3/R1 MLA serving) hard-coded `vec_size = 2`, i.e. 4-byte (2× bf16) global loads/stores. With `head_dim_ckv=512` this leaves the memory subsystem 4× under-utilized per transaction.
This sets ... | [{"scope": "kernel", "hardware": "H200", "model": "DeepSeek-V3", "shape": "head_dim_ckv=512,head_dim_kpe=64,page_size=64", "batch_size": 16384, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 15.7, "optimized": 8.8, "stated_speedup": 1.8, "speedup": 1.7841}, {"scope": "kernel", "hardware": "H2... | 1.8051 | null |
flashinfer | a85d020f48ca00faf81aae0f6bf1b54c351eb736 | 2026-07-11T10:50:29+08:00 | 3,756 | https://github.com/flashinfer-ai/flashinfer/pull/3756 | [CuTe DSL][MoE] Optimize PDL startup and balance GEMM2 partial-tile stores (#3756) | [CuTe DSL][MoE] Optimize PDL startup and balance GEMM2 partial-tile stores (#3756)
<!-- .github/pull_request_template.md -->
## 📌 Description
1. PDL optimization: Move TMEM allocation and scheduling of the first
tile earlier, while reducing thread usage and barrier overhead in the
GEMM1 scheduler.
2. Balanced store... | flashinfer/fused_moe/cute_dsl/blackwell/blockscaled_contiguous_grouped_gemm_finalize_fusion.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | --- flashinfer/fused_moe/cute_dsl/blackwell/blockscaled_contiguous_grouped_gemm_finalize_fusion.py
+++ flashinfer/fused_moe/cute_dsl/blackwell/blockscaled_contiguous_grouped_gemm_finalize_fusion.py
@@ -1156,6 +1156,7 @@
is_two_cta=use_2cta_instrs,
two_cta_tmem_dealloc_mbar_ptr=storage.tmem_dea... | 76 | 25 | 1 | [] | [
"BLACKWELL"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell/blockscaled_contiguous_grouped_gemm_finalize_fusion.py).
Goal: [CuTe DSL][MoE] Optimize PDL startup and balance GEMM2 partial-tile stores
Target hardware: BLACKWELL
Target models: unspecified
Current file:
```python
# Copyrigh... | <!-- .github/pull_request_template.md -->
## 📌 Description
1. PDL optimization: Move TMEM allocation and scheduling of the first tile earlier, while reducing thread usage and barrier overhead in the GEMM1 scheduler.
2. Balanced store: Distribute the GEMM2 partial-tile epilogue stores across warps in an interleaved ... | [{"scope": "e2e", "hardware": null, "model": null, "shape": "hidden=4096", "batch_size": 64, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.067951, "optimized": 0.065088, "stated_speedup": 1.044, "speedup": 1.044}, {"scope": "e2e", "hardware": null, "model": null, "shape": "hidden=4096", "b... | null | 1.015 |
flashinfer | d527621951244b8be4dd412b1a6729295697f3a7 | 2026-07-10T20:38:34+02:00 | 3,776 | https://github.com/flashinfer-ai/flashinfer/pull/3776 | perf(moe): support caller-provided combine output (#3776) | perf(moe): support caller-provided combine output (#3776)
## Summary
Allow `MoeAlltoAll.combine()` to write into an optional caller-provided
output tensor. The existing allocating API remains unchanged, and the
output-buffer path uses the same communication and combine kernels.
Related vLLM integration:
https://gith... | csrc/trtllm_moe_alltoall.cu | cuda | Apache-2.0 | /*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the ... | /*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the ... | --- csrc/trtllm_moe_alltoall.cu
+++ csrc/trtllm_moe_alltoall.cu
@@ -273,12 +273,12 @@
return nvinfer1::DataType::kFLOAT;
}
-Tensor moeA2ACombineOp(TensorView payload, int64_t localNumTokens, TensorView workspace,
- TensorView metainfo, int64_t runtimeMaxTokensPerRank, int64_t epRank,
- ... | 36 | 8 | 2 | [] | [
"CPU",
"GB200"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_moe_alltoall.cu).
Goal: perf(moe): support caller-provided combine output
Target hardware: CPU, GB200
Target models: unspecified
Current file:
```cuda
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION &
* AFFILIATES. All rights reserv... | ## Summary
Allow `MoeAlltoAll.combine()` to write into an optional caller-provided output tensor. The existing allocating API remains unchanged, and the output-buffer path uses the same communication and combine kernels.
Related vLLM integration: https://github.com/vllm-project/vllm/pull/47156
## Rationale
vLLM alr... | [{"scope": "e2e", "hardware": "GB200", "model": null, "shape": "hidden=8192,top_k=22,num_experts=512", "batch_size": 8192, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 817.648, "optimized": 777.528, "stated_speedup": null, "speedup": 1.0516}, {"scope": "e2e", "hardware": "GB200", "model": n... | null | 1.0392 |
flashinfer | 59b1c4d7c6f2e2d246becd7a0e0d36ebd33dc820 | 2026-07-10T03:04:40+08:00 | 3,614 | https://github.com/flashinfer-ai/flashinfer/pull/3614 | fix: make the cutlass MoE gemm profiler MXFP8-aware (autotune crash on MXFP8xMXFP8) (#3614) | fix: make the cutlass MoE gemm profiler MXFP8-aware (autotune crash on MXFP8xMXFP8) (#3614)
## Description
Fixes the original-report half of #3558: the autotuner tuning pass
crashes for `cutlass_fused_moe` with MXFP8 activation scaling (CUDA
illegal instruction / null TMA SF buffer on the reporter's SM121 build;
`!us... | csrc/fused_moe/cutlass_backend/flashinfer_cutlass_fused_moe_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/fused_moe/cutlass_backend/flashinfer_cutlass_fused_moe_binding.cu
+++ csrc/fused_moe/cutlass_backend/flashinfer_cutlass_fused_moe_binding.cu
@@ -679,12 +679,12 @@
activation_dtype = isNvfp4Quant() ? dl_int64 : activation_dtype;
int64_t const unpadded_hidden_size_profiler = hidden_size; // HACK n... | 6 | 6 | 3 | [] | [
"SM100",
"SM120",
"SM121",
"SM80",
"SM89"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/fused_moe/cutlass_backend/flashinfer_cutlass_fused_moe_binding.cu).
Goal: fix: make the cutlass MoE gemm profiler MXFP8-aware (autotune crash on MXFP8xMXFP8)
Target hardware: SM100, SM120, SM121, SM80, SM89
Target models: unspecified
Current file:
```cuda
/*
* Cop... | ## Description
Fixes the original-report half of #3558: the autotuner tuning pass crashes for `cutlass_fused_moe` with MXFP8 activation scaling (CUDA illegal instruction / null TMA SF buffer on the reporter's SM121 build; `!use_block_scaling` kernel assert on current main).
**Root cause** (one level deeper than my sc... | [] | null | null |
flashinfer | 59b1c4d7c6f2e2d246becd7a0e0d36ebd33dc820 | 2026-07-10T03:04:40+08:00 | 3,614 | https://github.com/flashinfer-ai/flashinfer/pull/3614 | fix: make the cutlass MoE gemm profiler MXFP8-aware (autotune crash on MXFP8xMXFP8) (#3614) | fix: make the cutlass MoE gemm profiler MXFP8-aware (autotune crash on MXFP8xMXFP8) (#3614)
## Description
Fixes the original-report half of #3558: the autotuner tuning pass
crashes for `cutlass_fused_moe` with MXFP8 activation scaling (CUDA
illegal instruction / null TMA SF buffer on the reporter's SM121 build;
`!us... | csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/include/moe_kernels.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/include/moe_kernels.h
+++ csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/include/moe_kernels.h
@@ -15,6 +15,7 @@
*/
#pragma once
+#include <algorithm>
#include <cstdint>
#include "cutlass/gemm/gemm.h"
@@ -635,7 +636,8 @@
}
std::vector<cut... | 32 | 4 | 3 | [] | [
"SM100",
"SM120",
"SM121",
"SM80",
"SM89"
] | [] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/include/moe_kernels.h).
Goal: fix: make the cutlass MoE gemm profiler MXFP8-aware (autotune crash on MXFP8xMXFP8)
Target hardware: SM100, SM120, SM121, SM80, SM89
Target models: unspecified
Current file:
```cpp
/*
* ... | ## Description
Fixes the original-report half of #3558: the autotuner tuning pass crashes for `cutlass_fused_moe` with MXFP8 activation scaling (CUDA illegal instruction / null TMA SF buffer on the reporter's SM121 build; `!use_block_scaling` kernel assert on current main).
**Root cause** (one level deeper than my sc... | [] | null | null |
flashinfer | d76162a78d5876188e82b81c1c96ccd6b2decd83 | 2026-07-08T09:32:34+08:00 | 3,866 | https://github.com/flashinfer-ai/flashinfer/pull/3866 | perf(gdn): optimize delta rule cp prefill for ultra low parallelism case (#3866) | perf(gdn): optimize delta rule cp prefill for ultra low parallelism case (#3866)
## 📌 Description
This PR updated CP chunking heuristics and implemented a SIMT kernel for
CP Fixup, target for ultralow parallelism performance.
## 🔍 Related Issues
#3491
## 🚀 Pull Request Checklist
### ✅ Pre-commit Checks
- [x]... | flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py | cute_dsl | Apache-2.0 | import torch
import cutlass
import cutlass.cute as cute
CP_CHUNK_LEN_GRANULARITY = 512
CP_HBM_PARALLELISM_THRESHOLD_NUMERATOR = 1
CP_HBM_PARALLELISM_THRESHOLD_DENOMINATOR = 2
CP_GDDR_PARALLELISM_THRESHOLD_NUMERATOR = 1
CP_GDDR_PARALLELISM_THRESHOLD_DENOMINATOR = 3
def chunk_bound_host(num_items: int, total: int, ch... | import math
import torch
import cutlass
import cutlass.cute as cute
BLK = 64
CP_CHUNK_LEN_GRANULARITY = 512
CP_DEFAULT_SHORT_FIXUP_TO_PREFILL_WORKLOAD_RATIO_NUMERATOR = 1
CP_DEFAULT_SHORT_FIXUP_TO_PREFILL_WORKLOAD_RATIO_DENOMINATOR = 1
CP_SM120_SHORT_FIXUP_TO_PREFILL_WORKLOAD_RATIO_NUMERATOR = 1
CP_SM120_SHORT_FIXUP... | --- flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py
+++ flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py
@@ -1,13 +1,29 @@
+import math
+
import torch
import cutlass
import cutlass.cute as cute
+BLK = 64
CP_CHUNK_LEN_GRANULARITY = 512
+CP_DEFAULT_SHORT_FIXUP_TO_PREFILL_WORKLOAD_RATIO_NUMERATOR = 1
... | 64 | 19 | 3 | [
"qwen"
] | [
"BLACKWELL",
"H100",
"HOPPER",
"SM120",
"SM90"
] | [
"4.90x",
"4.18x",
"3.26x",
"2.27x",
"1.81x",
"1.40x",
"1.94x",
"1.59x",
"1.91x",
"2.06x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/delta_rule_dsl/varlen_helper.py).
Goal: perf(gdn): optimize delta rule cp prefill for ultra low parallelism case
Target hardware: BLACKWELL, H100, HOPPER, SM120, SM90
Target models: qwen
Current file:
```python
import torch
import cutlass
impo... | ## 📌 Description
This PR updated CP chunking heuristics and implemented a SIMT kernel for CP Fixup, target for ultralow parallelism performance.
## 🔍 Related Issues
#3491
## 🚀 Pull Request Checklist
### ✅ Pre-commit Checks
- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your p... | [{"scope": "kernel", "hardware": "NVIDIA H100 80GB HBM3 [Hopper (SM90)]", "model": "Qwen3.5-397B/122B", "shape": "Seqlen=65536,h_qk=2,h_v=8", "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 1.954, "optimized": 0.399, "stated_speedup": 4.9, "speedup": 4.8972}, {"scope": "kernel... | 2.1827 | null |
flashinfer | 2e5ef6bb695ddb69729c4d36b6906196dea32d7b | 2026-07-07T13:19:27-07:00 | 3,766 | https://github.com/flashinfer-ai/flashinfer/pull/3766 | perf(kda): optimize recurrent decode kernels (#3766) | perf(kda): optimize recurrent decode kernels (#3766)
## Summary
Improve recurrent KDA decode performance across both low- and high-batch
multi-token workloads.
- Distribute D=128 Q/K/V/G asynchronous copies across all four warps.
- Double-buffer raw Q/K/V/G shared-memory staging for multi-token
decode.
- Prefetch to... | flashinfer/kda_kernels/recurrent_kda.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/kda_kernels/recurrent_kda.py
+++ flashinfer/kda_kernels/recurrent_kda.py
@@ -234,12 +234,19 @@
val_layout = cute.make_layout((copy_elems,))
tiled_copy = cute.make_tiled_copy_tv(atom_async, thr_layout, val_layout)
- # Gate the upper half of the block out of the issue. The split is
- # wa... | 317 | 54 | 1 | [] | [] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/kda_kernels/recurrent_kda.py).
Goal: perf(kda): optimize recurrent decode kernels
Target hardware: unspecified
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (t... | ## Summary
Improve recurrent KDA decode performance across both low- and high-batch
multi-token workloads.
- Distribute D=128 Q/K/V/G asynchronous copies across all four warps.
- Double-buffer raw Q/K/V/G shared-memory staging for multi-token decode.
- Prefetch token `t+1` while token `t` is being computed.
- Remove ... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "head_dim=64", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 2.3712, "optimized": 2.3514, "stated_speedup": null, "speedup": 1.0084}, {"scope": "kernel", "hardware": null, "model": null, "shape": "head_dim=64", "... | 1.0348 | null |
flashinfer | 8fc7f079203cfa6242d1fe250ef7028b22c5efd2 | 2026-07-01T22:44:27+08:00 | 3,788 | https://github.com/flashinfer-ai/flashinfer/pull/3788 | perf: optimize sm90 cp delta rule (#3788) | perf: optimize sm90 cp delta rule (#3788)
## 📌 Description
1. Fused qk and inversion epilogue.
2. Removed unnecessary intermediate buffer zeroing.
## 🔍 Related Issues
Similar optimization has been integrated in
e9ad55ce884e5d87c15a3a0e853b11b42ff5d245
93050535021a9421781f7b5b85259527da4d762e and
171e5edbcc2ac1573... | flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm90.py | cute_dsl | Apache-2.0 | from enum import IntEnum
import torch
import cutlass
import cutlass.cute as cute
import cutlass.pipeline as pipeline
from cutlass.cute.nvgpu import warp, warpgroup, cpasync
from ...utils import get_device_sm_count, _get_cache_buf
from .alpha import AlphaProcessor
from .collective_store_tma import CollectiveStoreTma
fr... | from enum import IntEnum
import torch
import cutlass
import cutlass.cute as cute
import cutlass.pipeline as pipeline
from cutlass.cute.nvgpu import warp, warpgroup, cpasync
from ...utils import get_device_sm_count, _get_cache_buf
from .alpha import AlphaProcessor
from .collective_store_tma import CollectiveStoreTma
fr... | --- flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm90.py
+++ flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm90.py
@@ -320,7 +320,7 @@
tQKrQK[i] = tQKrQK[i] if pred else cutlass.Float32(0.0)
tKKrKK[i] = tKKrKK[i] if pred else cutlass.Float32(0.0)
if cutlass.const_expr(is_fi... | 1 | 1 | 2 | [
"qwen"
] | [
"H100",
"HOPPER",
"SM90"
] | [
"4.47x",
"3.52x",
"2.56x",
"1.69x",
"1.40x",
"1.07x",
"1.63x",
"1.53x",
"1.63x",
"1.65x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_kernels/delta_rule_dsl/delta_rule_sm90.py).
Goal: perf: optimize sm90 cp delta rule
Target hardware: H100, HOPPER, SM90
Target models: qwen
Current file:
```python
from enum import IntEnum
import torch
import cutlass
import cutlass.cute as cute
impor... | ## 📌 Description
1. Fused qk and inversion epilogue.
2. Removed unnecessary intermediate buffer zeroing.
## 🔍 Related Issues
Similar optimization has been integrated in e9ad55ce884e5d87c15a3a0e853b11b42ff5d245 93050535021a9421781f7b5b85259527da4d762e and 171e5edbcc2ac1573a14dc5ffea7f13590d646c8
## 🚀 Pull Request... | [{"scope": "kernel", "hardware": "H100", "model": "Qwen3.5 family", "shape": "TP8 1x65536 h_qk=2 h_v=8", "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 2.006, "optimized": 0.449, "stated_speedup": 4.47, "speedup": 4.4677}, {"scope": "kernel", "hardware": "H100", "model": "... | 2.5668 | 1.1 |
flashinfer | 2594b958fa0f2e24bc1a4dc15921571f0761744d | 2026-06-29T17:28:29+08:00 | 3,751 | https://github.com/flashinfer-ai/flashinfer/pull/3751 | [feat] Optimize TRTLLMGEN MoE routing (#3751) | [feat] Optimize TRTLLMGEN MoE routing (#3751)
<!-- .github/pull_request_template.md -->
## 📌 Description
Optimize TRTLLM-Gen MoE routing to reduce register pressure and avoid
heavy spilling in high-expert routing cases.
- Add templated cluster routing kernels for 256/512/1024 thread block
sizes while preserving th... | csrc/fused_moe/trtllm_backend/trtllm_fused_moe_routing_custom.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/fused_moe/trtllm_backend/trtllm_fused_moe_routing_custom.cu
+++ csrc/fused_moe/trtllm_backend/trtllm_fused_moe_routing_custom.cu
@@ -28,6 +28,7 @@
#include <cstdlib>
#include <string>
+#include <type_traits>
#include "flashinfer/trtllm/common/cudaUtils.h"
#include "flashinfer/trtllm/fused_moe/RoutingCu... | 234 | 26 | 2 | [] | [] | [
"1.00x",
"0.98x",
"1.22x",
"1.39x",
"1.19x",
"0.96x",
"0.99x",
"1.00x",
"0.97x",
"1.00x"
] | Optimize this cuda kernel file from flashinfer (csrc/fused_moe/trtllm_backend/trtllm_fused_moe_routing_custom.cu).
Goal: [feat] Optimize TRTLLMGEN MoE routing
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Li... |
<!-- .github/pull_request_template.md -->
## 📌 Description
Optimize TRTLLM-Gen MoE routing to reduce register pressure and avoid heavy spilling in high-expert routing cases.
- Add templated cluster routing kernels for 256/512/1024 thread block sizes while preserving the original default kernel path.
- Apply the u... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "E=256,K=8,tokens=8", "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.009216, "optimized": 0.009184, "stated_speedup": 1.0, "speedup": 1.0035}, {"scope": "kernel", "hardware": null, "model": null, "shape": "E=... | 1.218 | null |
flashinfer | 2594b958fa0f2e24bc1a4dc15921571f0761744d | 2026-06-29T17:28:29+08:00 | 3,751 | https://github.com/flashinfer-ai/flashinfer/pull/3751 | [feat] Optimize TRTLLMGEN MoE routing (#3751) | [feat] Optimize TRTLLMGEN MoE routing (#3751)
<!-- .github/pull_request_template.md -->
## 📌 Description
Optimize TRTLLM-Gen MoE routing to reduce register pressure and avoid
heavy spilling in high-expert routing cases.
- Add templated cluster routing kernels for 256/512/1024 thread block
sizes while preserving th... | include/flashinfer/trtllm/fused_moe/RoutingCustomPolicy.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/trtllm/fused_moe/RoutingCustomPolicy.cuh
+++ include/flashinfer/trtllm/fused_moe/RoutingCustomPolicy.cuh
@@ -697,17 +697,20 @@
/// None + Softmax (Renormalize): many model configs.
template <>
struct PolicyTraits<NoOpPreprocess, SoftmaxPostprocess> {
- using Pairs = TierList<Tier<128, 4>, /... | 59 | 26 | 2 | [] | [] | [
"1.00x",
"0.98x",
"1.22x",
"1.39x",
"1.19x",
"0.96x",
"0.99x",
"1.00x",
"0.97x",
"1.00x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/trtllm/fused_moe/RoutingCustomPolicy.cuh).
Goal: [feat] Optimize TRTLLMGEN MoE routing
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
*
* License... |
<!-- .github/pull_request_template.md -->
## 📌 Description
Optimize TRTLLM-Gen MoE routing to reduce register pressure and avoid heavy spilling in high-expert routing cases.
- Add templated cluster routing kernels for 256/512/1024 thread block sizes while preserving the original default kernel path.
- Apply the u... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "E=256,K=8,tokens=8", "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.009216, "optimized": 0.009184, "stated_speedup": 1.0, "speedup": 1.0035}, {"scope": "kernel", "hardware": null, "model": null, "shape": "E=... | 1.218 | null |
flashinfer | 22ad42062922b2f9c780eb8b013197f5b4df0fb7 | 2026-06-26T06:38:11+08:00 | 3,564 | https://github.com/flashinfer-ai/flashinfer/pull/3564 | perf(moe): Enhance CuteDSL NVF4 MOE Perf (#3564) | perf(moe): Enhance CuteDSL NVF4 MOE Perf (#3564)
## 📌 Description
Cherry pick perf optimization changes from TRTLLM PR
https://github.com/NVIDIA/TensorRT-LLM/pull/15092.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInfer! Before we rev... | flashinfer/fused_moe/cute_dsl/blackwell/blockscaled_contiguous_grouped_gemm_finalize_fusion.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | --- flashinfer/fused_moe/cute_dsl/blackwell/blockscaled_contiguous_grouped_gemm_finalize_fusion.py
+++ flashinfer/fused_moe/cute_dsl/blackwell/blockscaled_contiguous_grouped_gemm_finalize_fusion.py
@@ -39,15 +39,12 @@
from cutlass.cute.nvgpu import cpasync, tcgen05
from .utils import (
- atomic_add_func,
bl... | 237 | 171 | 4 | [] | [
"BLACKWELL"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell/blockscaled_contiguous_grouped_gemm_finalize_fusion.py).
Goal: perf(moe): Enhance CuteDSL NVF4 MOE Perf
Target hardware: BLACKWELL
Target models: unspecified
Current file:
```python
# Copyright (c) 2025 NVIDIA CORPORATION & AF... | ## 📌 Description
Cherry pick perf optimization changes from TRTLLM PR https://github.com/NVIDIA/TensorRT-LLM/pull/15092.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInfer! Before we review your pull request, please make sure the follow... | [] | null | null |
flashinfer | 22ad42062922b2f9c780eb8b013197f5b4df0fb7 | 2026-06-26T06:38:11+08:00 | 3,564 | https://github.com/flashinfer-ai/flashinfer/pull/3564 | perf(moe): Enhance CuteDSL NVF4 MOE Perf (#3564) | perf(moe): Enhance CuteDSL NVF4 MOE Perf (#3564)
## 📌 Description
Cherry pick perf optimization changes from TRTLLM PR
https://github.com/NVIDIA/TensorRT-LLM/pull/15092.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInfer! Before we rev... | flashinfer/fused_moe/cute_dsl/blockscaled_contiguous_grouped_gemm_finalize_fusion.py | cute_dsl | Apache-2.0 | # Copyright (c) 2025 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | # Copyright (c) 2025 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | --- flashinfer/fused_moe/cute_dsl/blockscaled_contiguous_grouped_gemm_finalize_fusion.py
+++ flashinfer/fused_moe/cute_dsl/blockscaled_contiguous_grouped_gemm_finalize_fusion.py
@@ -216,7 +216,6 @@
sf_vec_size=sf_vec_size,
mma_tiler_mn=mma_tiler_mn,
cluster_shape_mn=cluster_shape_... | 12 | 10 | 4 | [] | [] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blockscaled_contiguous_grouped_gemm_finalize_fusion.py).
Goal: perf(moe): Enhance CuteDSL NVF4 MOE Perf
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# Copyright (c) 2025 by FlashInfer team.
#
# License... | ## 📌 Description
Cherry pick perf optimization changes from TRTLLM PR https://github.com/NVIDIA/TensorRT-LLM/pull/15092.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInfer! Before we review your pull request, please make sure the follow... | [] | null | null |
flashinfer | 28406af5b9134757acbd6bc44647fd00261d163f | 2026-06-10T21:35:00-07:00 | 3,560 | https://github.com/flashinfer-ai/flashinfer/pull/3560 | perf(gemm): update mm_fp4 b12x SM120 NVFP4 dense GEMM kernel (#3560) | perf(gemm): update mm_fp4 b12x SM120 NVFP4 dense GEMM kernel (#3560)
<!-- .github/pull_request_template.md -->
## 📌 Description
### Summary
This PR refreshes the `b12x` dense FP4 GEMM kernel to match the latest
upstream for better performance.
**No public API change.** The `auto` routing heuristic
(`_heuristic_fun... | flashinfer/cute_dsl/utils.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/cute_dsl/utils.py
+++ flashinfer/cute_dsl/utils.py
@@ -585,8 +585,8 @@
assert sf_vec_size == 16 or sf_vec_size == 32, "sf_vec_size must be 16 or 32"
- assert tile_shape_mnk[1] % (blk_mn // 2) == 0, (
- "tile_shape_mnk[1] must be divisible by 64"
+ assert tile_shape_mnk[1] % (blk_mn ... | 2 | 2 | 3 | [
"deepseek",
"llama"
] | [
"RTX5080",
"SM100",
"SM103",
"SM120",
"SM121"
] | [
"1.003×",
"1.019×",
"1.003×",
"0.991×",
"1.021×",
"1.060×",
"1.010×",
"1.000×",
"1.024×",
"1.021×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/utils.py).
Goal: perf(gemm): update mm_fp4 b12x SM120 NVFP4 dense GEMM kernel
Target hardware: RTX5080, SM100, SM103, SM120, SM121
Target models: deepseek, llama
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under t... | <!-- .github/pull_request_template.md -->
## 📌 Description
### Summary
This PR refreshes the `b12x` dense FP4 GEMM kernel to match the latest upstream for better performance.
**No public API change.** The `auto` routing heuristic (`_heuristic_func_mm_fp4`) is **unchanged** — b12x is preferred only at SM120, not SM1... | [{"scope": "e2e", "hardware": "RTX 5080 (SM120)", "model": "DeepSeek-R1,Llama-3", "shape": null, "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.003, "speedup": 1.003}, {"scope": "e2e", "hardware": "RTX 5080 (SM120)", "model": "De... | 1 | 1.023 |
flashinfer | e00c306070f30b6af5da89ed877e8d2ab49c1565 | 2026-06-04T21:55:05+08:00 | 3,476 | https://github.com/flashinfer-ai/flashinfer/pull/3476 | Optimize MoE routing top-k reduction and non-power-of-two sorting (#3476) | Optimize MoE routing top-k reduction and non-power-of-two sorting (#3476)
<!-- .github/pull_request_template.md -->
## 📌 Description
Improves TRT-LLM MoE routing top-k performance by using a two-step fast
warp reduction for 64-bit packed FP32 keys on SM100+, and replacing
non-power-of-two odd-even transposition sor... | csrc/fused_moe/moeTopKFuncs.cuh | cuda | Apache-2.0 |
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requ... |
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless requ... | --- csrc/fused_moe/moeTopKFuncs.cuh
+++ csrc/fused_moe/moeTopKFuncs.cuh
@@ -73,11 +73,25 @@
__host__ __device__ operator TypeCmp() const noexcept { return compValIdx; }
__device__ inline TypeCmp reduce(cg::thread_block_tile<kWARP_SIZE> const& warp) {
- if constexpr (!kTLLM_GEN_HAS_FAST_REDUX || sizeof(TypeCm... | 16 | 2 | 2 | [] | [
"SM100"
] | [
"1.001x",
"1.498x",
"1.500x",
"1.666x",
"2.000x",
"2.125x"
] | Optimize this cuda kernel file from flashinfer (csrc/fused_moe/moeTopKFuncs.cuh).
Goal: Optimize MoE routing top-k reduction and non-power-of-two sorting
Target hardware: SM100
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under th... | <!-- .github/pull_request_template.md -->
## 📌 Description
Improves TRT-LLM MoE routing top-k performance by using a two-step fast warp reduction for 64-bit packed FP32 keys on SM100+, and replacing non-power-of-two odd-even transposition sorting with a padded Batcher odd-even merge network. The new sort path prese... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "K=10,N=2048,T=512", "batch_size": 512, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 6.151, "optimized": 6.144, "stated_speedup": 1.001, "speedup": 1.0011}, {"scope": "kernel", "hardware": null, "model": null, "shape": "K=10,N=2... | 1.5832 | null |
flashinfer | e00c306070f30b6af5da89ed877e8d2ab49c1565 | 2026-06-04T21:55:05+08:00 | 3,476 | https://github.com/flashinfer-ai/flashinfer/pull/3476 | Optimize MoE routing top-k reduction and non-power-of-two sorting (#3476) | Optimize MoE routing top-k reduction and non-power-of-two sorting (#3476)
<!-- .github/pull_request_template.md -->
## 📌 Description
Improves TRT-LLM MoE routing top-k performance by using a two-step fast
warp reduction for 64-bit packed FP32 keys on SM100+, and replacing
non-power-of-two odd-even transposition sor... | include/flashinfer/trtllm/fused_moe/RoutingKernelTopK.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/trtllm/fused_moe/RoutingKernelTopK.cuh
+++ include/flashinfer/trtllm/fused_moe/RoutingKernelTopK.cuh
@@ -77,18 +77,30 @@
__host__ __device__ operator TypeCmp() const noexcept { return compVal; }
__device__ inline TypeCmp reduce(cg::thread_block_tile<WarpSize> const& warp) {
- // Use fa... | 92 | 24 | 2 | [] | [
"SM100"
] | [
"1.001x",
"1.498x",
"1.500x",
"1.666x",
"2.000x",
"2.125x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/trtllm/fused_moe/RoutingKernelTopK.cuh).
Goal: Optimize MoE routing top-k reduction and non-power-of-two sorting
Target hardware: SM100
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights res... | <!-- .github/pull_request_template.md -->
## 📌 Description
Improves TRT-LLM MoE routing top-k performance by using a two-step fast warp reduction for 64-bit packed FP32 keys on SM100+, and replacing non-power-of-two odd-even transposition sorting with a padded Batcher odd-even merge network. The new sort path prese... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "K=10,N=2048,T=512", "batch_size": 512, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 6.151, "optimized": 6.144, "stated_speedup": 1.001, "speedup": 1.0011}, {"scope": "kernel", "hardware": null, "model": null, "shape": "K=10,N=2... | 1.5832 | null |
flashinfer | 1d61b2ad4c683685c44f02085bff5a910b9fa815 | 2026-06-02T17:50:25-07:00 | 3,289 | https://github.com/flashinfer-ai/flashinfer/pull/3289 | Optimize mxfp8 quantization on sm100 (#3289) | Optimize mxfp8 quantization on sm100 (#3289)
<!-- .github/pull_request_template.md -->
## 📌 Description
Apply the optimizations from (per-token) fp4 quantization kernel to
mxfp8 quantization kernel:
- use block size 128
- enable 256bit when using sm100f
## 🔍 Related Issues
<!-- Link any related issues here -->... | csrc/nv_internal/cpp/kernels/quantization.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/cpp/kernels/quantization.cu
+++ csrc/nv_internal/cpp/kernels/quantization.cu
@@ -213,8 +213,8 @@
static constexpr int SF_VEC_SIZE = 32;
// Grid, Block size.
- // Each thread converts 8 values.
- dim3 block(std::min(int(padded_n / CVT_FP16_TO_MXFP8_ELTS_PER_THREAD), 512));
+ // Each threa... | 3 | 2 | 3 | [] | [
"SM100"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/nv_internal/cpp/kernels/quantization.cu).
Goal: Optimize mxfp8 quantization on sm100
Target hardware: SM100
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache Lic... | <!-- .github/pull_request_template.md -->
## 📌 Description
Apply the optimizations from (per-token) fp4 quantization kernel to mxfp8 quantization kernel:
- use block size 128
- enable 256bit when using sm100f
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for ... | [] | null | null |
flashinfer | 1d61b2ad4c683685c44f02085bff5a910b9fa815 | 2026-06-02T17:50:25-07:00 | 3,289 | https://github.com/flashinfer-ai/flashinfer/pull/3289 | Optimize mxfp8 quantization on sm100 (#3289) | Optimize mxfp8 quantization on sm100 (#3289)
<!-- .github/pull_request_template.md -->
## 📌 Description
Apply the optimizations from (per-token) fp4 quantization kernel to
mxfp8 quantization kernel:
- use block size 128
- enable 256bit when using sm100f
## 🔍 Related Issues
<!-- Link any related issues here -->... | csrc/nv_internal/tensorrt_llm/kernels/quantization.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/kernels/quantization.cuh
+++ csrc/nv_internal/tensorrt_llm/kernels/quantization.cuh
@@ -55,8 +55,10 @@
defined(__CUDACC_VER_MINOR__) && \
((__CUDACC_VER_MAJOR__ == 12 && __CUDACC_VER_MINOR__ >= 9) || (__CUDACC_VER_MAJOR__ >... | 9 | 4 | 3 | [] | [
"SM100"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/quantization.cuh).
Goal: Optimize mxfp8 quantization on sm100
Target hardware: SM100
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the ... | <!-- .github/pull_request_template.md -->
## 📌 Description
Apply the optimizations from (per-token) fp4 quantization kernel to mxfp8 quantization kernel:
- use block size 128
- enable 256bit when using sm100f
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for ... | [] | null | null |
flashinfer | 1d61b2ad4c683685c44f02085bff5a910b9fa815 | 2026-06-02T17:50:25-07:00 | 3,289 | https://github.com/flashinfer-ai/flashinfer/pull/3289 | Optimize mxfp8 quantization on sm100 (#3289) | Optimize mxfp8 quantization on sm100 (#3289)
<!-- .github/pull_request_template.md -->
## 📌 Description
Apply the optimizations from (per-token) fp4 quantization kernel to
mxfp8 quantization kernel:
- use block size 128
- enable 256bit when using sm100f
## 🔍 Related Issues
<!-- Link any related issues here -->... | csrc/nv_internal/tensorrt_llm/kernels/quantization_utils.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/kernels/quantization_utils.cuh
+++ csrc/nv_internal/tensorrt_llm/kernels/quantization_utils.cuh
@@ -235,6 +235,26 @@
return u.val;
}
+// Convert 8 float2 values into 16 e4m3 values (represented as one uint4).
+inline __device__ uint4 fp32_vec_to_e4m3(float2 (&array)[8]) {
+ unio... | 31 | 7 | 3 | [] | [
"SM100"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/quantization_utils.cuh).
Goal: Optimize mxfp8 quantization on sm100
Target hardware: SM100
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed unde... | <!-- .github/pull_request_template.md -->
## 📌 Description
Apply the optimizations from (per-token) fp4 quantization kernel to mxfp8 quantization kernel:
- use block size 128
- enable 256bit when using sm100f
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for ... | [] | null | null |
flashinfer | d53f10682cfdc13c12d3463b2559355b9eb1671d | 2026-05-26T10:24:42-07:00 | 3,385 | https://github.com/flashinfer-ai/flashinfer/pull/3385 | feat: MNNVL Allreduce quant fusion and performance optimization (#3385) | feat: MNNVL Allreduce quant fusion and performance optimization (#3385)
<!-- .github/pull_request_template.md -->
## 📌 Description
- Use named barrier and cluster barrier instead of a sync.
- Avoid loading local buffer again in oneshot, use template-based fash
path for world size <= 8.
- Adjust grid dispatch policy... | csrc/trtllm_mnnvl_allreduce.cu | cuda | Apache-2.0 | #include "flashinfer/comm/trtllm_mnnvl_allreduce.cuh"
#include "tvm_ffi_utils.h"
using namespace flashinfer::trtllm_mnnvl_allreduce;
using tvm::ffi::Optional;
#define DISPATCH_FLOATING_TYPES_FOR_MNNVL_ALLREDUCE(dtype, c_type, ...) \
[&] { ... | #include "flashinfer/comm/trtllm_mnnvl_allreduce.cuh"
#include "tvm_ffi_utils.h"
using namespace flashinfer::trtllm_mnnvl_allreduce;
using flashinfer::QuantizationSFLayout;
using tvm::ffi::Optional;
#define DISPATCH_FLOATING_TYPES_FOR_MNNVL_ALLREDUCE(dtype, c_type, ...) \
[&] { ... | --- csrc/trtllm_mnnvl_allreduce.cu
+++ csrc/trtllm_mnnvl_allreduce.cu
@@ -3,6 +3,7 @@
using namespace flashinfer::trtllm_mnnvl_allreduce;
+using flashinfer::QuantizationSFLayout;
using tvm::ffi::Optional;
#define DISPATCH_FLOATING_TYPES_FOR_MNNVL_ALLREDUCE(dtype, c_type, ...) \
@@ -30,9 +31,12 @@
... | 80 | 6 | 5 | [] | [
"BLACKWELL",
"HOPPER"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_mnnvl_allreduce.cu).
Goal: feat: MNNVL Allreduce quant fusion and performance optimization
Target hardware: BLACKWELL, HOPPER
Target models: unspecified
Current file:
```cuda
#include "flashinfer/comm/trtllm_mnnvl_allreduce.cuh"
#include "tvm_ffi_utils.h"
u... | <!-- .github/pull_request_template.md -->
## 📌 Description
- Use named barrier and cluster barrier instead of a sync.
- Avoid loading local buffer again in oneshot, use template-based fash path for world size <= 8.
- Adjust grid dispatch policy to use more SMs at the cost of single SM occupancy for small batch sizes.... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "M <= 8", "batch_size": null, "metric": "latency", "unit": "%", "higher_is_better": false, "baseline": null, "optimized": null, "stated_speedup": 1.0624, "speedup": 1.0624}, {"scope": "kernel", "hardware": null, "model": null, "shape": "M <= 8", "batch_size... | 1.0525 | null |
flashinfer | 202af00dff85c1d5b50d15eab59d936365042af3 | 2026-05-07T20:58:39-07:00 | 3,237 | https://github.com/flashinfer-ai/flashinfer/pull/3237 | perf: optimize per-token nvfp4 quantization kernel. (#3237) | perf: optimize per-token nvfp4 quantization kernel. (#3237)
<!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the performance of the per-token nvfp4 quantization kernel
introduced by #3027.
1. default block size to 128.
2. default to fast math path. rename `TE_EXACT_FP4` to
`TRTLLM_DISABLE_FP4_QU... | csrc/nv_internal/cpp/common/envUtils.cpp | cpp | Apache-2.0 | /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights
* reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights
* reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | --- csrc/nv_internal/cpp/common/envUtils.cpp
+++ csrc/nv_internal/cpp/common/envUtils.cpp
@@ -354,6 +354,14 @@
return kBlock;
}
-bool getEnvEplbForceGdrcopy() { return getBoolEnv("TRTLLM_EPLB_FORCE_GDRCOPY"); }
+bool getEnvEplbForceGdrcopy() {
+ static bool const forceGdrcopy = getBoolEnv("TRTLLM_EPLB_FORCE_GDRC... | 9 | 1 | 6 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/cpp/common/envUtils.cpp).
Goal: perf: optimize per-token nvfp4 quantization kernel.
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All ri... | <!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the performance of the per-token nvfp4 quantization kernel introduced by #3027.
1. default block size to 128.
2. default to fast math path. rename `TE_EXACT_FP4` to `TRTLLM_DISABLE_FP4_QUANT_FAST_MATH` and controlled by environmental variable.
3. ... | [] | null | null |
flashinfer | 202af00dff85c1d5b50d15eab59d936365042af3 | 2026-05-07T20:58:39-07:00 | 3,237 | https://github.com/flashinfer-ai/flashinfer/pull/3237 | perf: optimize per-token nvfp4 quantization kernel. (#3237) | perf: optimize per-token nvfp4 quantization kernel. (#3237)
<!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the performance of the per-token nvfp4 quantization kernel
introduced by #3027.
1. default block size to 128.
2. default to fast math path. rename `TE_EXACT_FP4` to
`TRTLLM_DISABLE_FP4_QU... | csrc/nv_internal/cpp/kernels/quantization.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/cpp/kernels/quantization.cu
+++ csrc/nv_internal/cpp/kernels/quantization.cu
@@ -236,17 +236,18 @@
////////////////////////////////////////////////////////////////////////////////////////////////////
// Per-token Nvfp4 kernel
-#define DISPATCH_NVP4_QUANT_AND_PER_TOKEN_SCALE_KERNEL(SF_LAYOUT) ... | 37 | 28 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/nv_internal/cpp/kernels/quantization.cu).
Goal: perf: optimize per-token nvfp4 quantization kernel.
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed... | <!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the performance of the per-token nvfp4 quantization kernel introduced by #3027.
1. default block size to 128.
2. default to fast math path. rename `TE_EXACT_FP4` to `TRTLLM_DISABLE_FP4_QUANT_FAST_MATH` and controlled by environmental variable.
3. ... | [] | null | null |
flashinfer | 202af00dff85c1d5b50d15eab59d936365042af3 | 2026-05-07T20:58:39-07:00 | 3,237 | https://github.com/flashinfer-ai/flashinfer/pull/3237 | perf: optimize per-token nvfp4 quantization kernel. (#3237) | perf: optimize per-token nvfp4 quantization kernel. (#3237)
<!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the performance of the per-token nvfp4 quantization kernel
introduced by #3027.
1. default block size to 128.
2. default to fast math path. rename `TE_EXACT_FP4` to
`TRTLLM_DISABLE_FP4_QU... | csrc/nv_internal/tensorrt_llm/common/envUtils.h | cpp | Apache-2.0 | /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights
* reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights
* reserved. SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the Lic... | --- csrc/nv_internal/tensorrt_llm/common/envUtils.h
+++ csrc/nv_internal/tensorrt_llm/common/envUtils.h
@@ -101,4 +101,7 @@
// Block size (threads per block) for MoE A2A Combine kernels (default 256 if unset or invalid)
int getEnvMoeA2ACombineBlockSize();
+// Disable the fast fp4 quantization math and align with th... | 3 | 0 | 6 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/common/envUtils.h).
Goal: perf: optimize per-token nvfp4 quantization kernel.
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES.... | <!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the performance of the per-token nvfp4 quantization kernel introduced by #3027.
1. default block size to 128.
2. default to fast math path. rename `TE_EXACT_FP4` to `TRTLLM_DISABLE_FP4_QUANT_FAST_MATH` and controlled by environmental variable.
3. ... | [] | null | null |
flashinfer | 202af00dff85c1d5b50d15eab59d936365042af3 | 2026-05-07T20:58:39-07:00 | 3,237 | https://github.com/flashinfer-ai/flashinfer/pull/3237 | perf: optimize per-token nvfp4 quantization kernel. (#3237) | perf: optimize per-token nvfp4 quantization kernel. (#3237)
<!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the performance of the per-token nvfp4 quantization kernel
introduced by #3027.
1. default block size to 128.
2. default to fast math path. rename `TE_EXACT_FP4` to
`TRTLLM_DISABLE_FP4_QU... | csrc/nv_internal/tensorrt_llm/kernels/quantization.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/kernels/quantization.cuh
+++ csrc/nv_internal/tensorrt_llm/kernels/quantization.cuh
@@ -686,49 +686,55 @@
__global__ void block_scale_interleave_kernel(int numbatches, int numRows, int numCols,
uint8_t const* SFIn, uint8_t* SFOutput);
-... | 70 | 60 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/quantization.cuh).
Goal: perf: optimize per-token nvfp4 quantization kernel.
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
... | <!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the performance of the per-token nvfp4 quantization kernel introduced by #3027.
1. default block size to 128.
2. default to fast math path. rename `TE_EXACT_FP4` to `TRTLLM_DISABLE_FP4_QUANT_FAST_MATH` and controlled by environmental variable.
3. ... | [] | null | null |
flashinfer | 202af00dff85c1d5b50d15eab59d936365042af3 | 2026-05-07T20:58:39-07:00 | 3,237 | https://github.com/flashinfer-ai/flashinfer/pull/3237 | perf: optimize per-token nvfp4 quantization kernel. (#3237) | perf: optimize per-token nvfp4 quantization kernel. (#3237)
<!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the performance of the per-token nvfp4 quantization kernel
introduced by #3027.
1. default block size to 128.
2. default to fast math path. rename `TE_EXACT_FP4` to
`TRTLLM_DISABLE_FP4_QU... | csrc/nv_internal/tensorrt_llm/kernels/quantization.h | cpp | Apache-2.0 | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/kernels/quantization.h
+++ csrc/nv_internal/tensorrt_llm/kernels/quantization.h
@@ -76,7 +76,7 @@
void invokeNvfp4QuantAndPerTokenScale(uint32_t m, uint32_t n, T const* input, float globalScaleInv,
int32_t* expanded_idx_to_permuted_idx, uint8_t* ... | 1 | 1 | 6 | [] | [] | [] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/quantization.h).
Goal: perf: optimize per-token nvfp4 quantization kernel.
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Li... | <!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the performance of the per-token nvfp4 quantization kernel introduced by #3027.
1. default block size to 128.
2. default to fast math path. rename `TE_EXACT_FP4` to `TRTLLM_DISABLE_FP4_QUANT_FAST_MATH` and controlled by environmental variable.
3. ... | [] | null | null |
flashinfer | 202af00dff85c1d5b50d15eab59d936365042af3 | 2026-05-07T20:58:39-07:00 | 3,237 | https://github.com/flashinfer-ai/flashinfer/pull/3237 | perf: optimize per-token nvfp4 quantization kernel. (#3237) | perf: optimize per-token nvfp4 quantization kernel. (#3237)
<!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the performance of the per-token nvfp4 quantization kernel
introduced by #3027.
1. default block size to 128.
2. default to fast math path. rename `TE_EXACT_FP4` to
`TRTLLM_DISABLE_FP4_QU... | csrc/nv_internal/tensorrt_llm/kernels/quantization_utils.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/kernels/quantization_utils.cuh
+++ csrc/nv_internal/tensorrt_llm/kernels/quantization_utils.cuh
@@ -290,7 +290,7 @@
// Quantizes the provided PackedVec into the uint32_t or uint64_t output
template <class Type, int SF_VEC_SIZE, int CVT_ELTS_PER_THREAD, bool UE8M0_SF,
- boo... | 88 | 36 | 6 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/quantization_utils.cuh).
Goal: perf: optimize per-token nvfp4 quantization kernel.
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved... | <!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the performance of the per-token nvfp4 quantization kernel introduced by #3027.
1. default block size to 128.
2. default to fast math path. rename `TE_EXACT_FP4` to `TRTLLM_DISABLE_FP4_QUANT_FAST_MATH` and controlled by environmental variable.
3. ... | [] | null | null |
flashinfer | 2fe28ca941911e79f517af618c2ad52ee377cd79 | 2026-05-07T17:51:51-07:00 | 3,239 | https://github.com/flashinfer-ai/flashinfer/pull/3239 | perf: Update moe gemm (#3239) | perf: Update moe gemm (#3239)
<!-- .github/pull_request_template.md -->
## 📌 Description
Update the trtllm-gen cubin to improve mxfp4 moe, DeepSeek-V3 MoE, and
mxfp8 gemm performance.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInfer... | csrc/trtllm_batched_gemm_runner.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_batched_gemm_runner.cu
+++ csrc/trtllm_batched_gemm_runner.cu
@@ -91,9 +91,11 @@
auto const configs = bmm.getBatchedGemmConfigs();
mPassingConfigIndices.clear();
+ auto sm_version = getSMVersion();
for (size_t i = 0; i < bmm.getNumBatchedGemmConfigs(); ++i) {
- auto const options = conf... | 10 | 2 | 4 | [
"deepseek"
] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_batched_gemm_runner.cu).
Goal: perf: Update moe gemm
Target hardware: unspecified
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the... | <!-- .github/pull_request_template.md -->
## 📌 Description
Update the trtllm-gen cubin to improve mxfp4 moe, DeepSeek-V3 MoE, and mxfp8 gemm performance.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInfer! Before we review your pull re... | [] | null | null |
flashinfer | 2fe28ca941911e79f517af618c2ad52ee377cd79 | 2026-05-07T17:51:51-07:00 | 3,239 | https://github.com/flashinfer-ai/flashinfer/pull/3239 | perf: Update moe gemm (#3239) | perf: Update moe gemm (#3239)
<!-- .github/pull_request_template.md -->
## 📌 Description
Update the trtllm-gen cubin to improve mxfp4 moe, DeepSeek-V3 MoE, and
mxfp8 gemm performance.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInfer... | csrc/trtllm_gemm_runner.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_gemm_runner.cu
+++ csrc/trtllm_gemm_runner.cu
@@ -44,21 +44,21 @@
int64_t select_kernel_fp8(int32_t M, int32_t N, int32_t K,
const gemm::gemm::GemmInterface& interface) {
static constexpr const char* KERNEL_NAME_HIGH_N_K_RATIO =
- "gemm_Bfloat16_E4m3E4m3_Fp32_t128x8x1... | 8 | 8 | 4 | [
"deepseek"
] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_gemm_runner.cu).
Goal: perf: Update moe gemm
Target hardware: unspecified
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "Licens... | <!-- .github/pull_request_template.md -->
## 📌 Description
Update the trtllm-gen cubin to improve mxfp4 moe, DeepSeek-V3 MoE, and mxfp8 gemm performance.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInfer! Before we review your pull re... | [] | null | null |
flashinfer | 2fe28ca941911e79f517af618c2ad52ee377cd79 | 2026-05-07T17:51:51-07:00 | 3,239 | https://github.com/flashinfer-ai/flashinfer/pull/3239 | perf: Update moe gemm (#3239) | perf: Update moe gemm (#3239)
<!-- .github/pull_request_template.md -->
## 📌 Description
Update the trtllm-gen cubin to improve mxfp4 moe, DeepSeek-V3 MoE, and
mxfp8 gemm performance.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInfer... | csrc/trtllm_low_latency_gemm_runner.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_low_latency_gemm_runner.cu
+++ csrc/trtllm_low_latency_gemm_runner.cu
@@ -63,28 +63,28 @@
*/
int64_t select_kernel(int32_t m, int32_t n, int32_t k, const gemm::gemm::GemmInterface& interface) {
static constexpr const char* KERNEL_MMAN_8_TILEK_128 =
- "gemm_Bfloat16_E4m3E4m3_Fp32_t128x8x128_s7... | 8 | 8 | 4 | [
"deepseek"
] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_low_latency_gemm_runner.cu).
Goal: perf: Update moe gemm
Target hardware: unspecified
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 ... | <!-- .github/pull_request_template.md -->
## 📌 Description
Update the trtllm-gen cubin to improve mxfp4 moe, DeepSeek-V3 MoE, and mxfp8 gemm performance.
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInfer! Before we review your pull re... | [] | null | null |
flashinfer | 8d1b69b2b4b73a04895dacc7486bec25416e93c4 | 2026-05-06T21:49:53-07:00 | 3,129 | https://github.com/flashinfer-ai/flashinfer/pull/3129 | feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16 (#3129) | feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16 (#3129)
## Summary
Enable FP8 (E4M3/E5M2) support in `concat_mla_k`, fixing a crash that
blocks FP8 chunked prefill for all MLA models (DeepSeek-V2/V3/R1) on
long-context workloads.
## ... | csrc/concat_mla.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/concat_mla.cu
+++ csrc/concat_mla.cu
@@ -84,7 +84,7 @@
ffi::CUDADeviceGuard device_guard(k.device().device_id);
const cudaStream_t stream = get_stream(k.device());
- bool success = DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP16(k.dtype(), c_type, [&] {
+ bool success = DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP16_FP8(k.... | 1 | 1 | 5 | [
"deepseek"
] | [
"GB300"
] | [
"1.35x"
] | Optimize this cuda kernel file from flashinfer (csrc/concat_mla.cu).
Goal: feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16
Target hardware: GB300
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer tea... | ## Summary
Enable FP8 (E4M3/E5M2) support in `concat_mla_k`, fixing a crash that blocks FP8 chunked prefill for all MLA models (DeepSeek-V2/V3/R1) on long-context workloads.
## Motivation
For long-context inference (ISL >= 4K) in vLLM, chunked prefill + FP8 quantization (`use_prefill_query_quantization: true`) is cr... | [{"scope": "e2e", "hardware": "GB300", "model": "DeepSeek-R1-0528-FP4", "shape": "ISL=128K", "batch_size": 16, "metric": "Median TTFT", "unit": "s", "higher_is_better": false, "baseline": 42.0, "optimized": 30.1, "stated_speedup": null, "speedup": 1.3953}, {"scope": "e2e", "hardware": "GB300", "model": "DeepSeek-R1-052... | null | 1.3681 |
flashinfer | 8d1b69b2b4b73a04895dacc7486bec25416e93c4 | 2026-05-06T21:49:53-07:00 | 3,129 | https://github.com/flashinfer-ai/flashinfer/pull/3129 | feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16 (#3129) | feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16 (#3129)
## Summary
Enable FP8 (E4M3/E5M2) support in `concat_mla_k`, fixing a crash that
blocks FP8 chunked prefill for all MLA models (DeepSeek-V2/V3/R1) on
long-context workloads.
## ... | csrc/tvm_ffi_utils.h | cpp | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/tvm_ffi_utils.h
+++ csrc/tvm_ffi_utils.h
@@ -166,6 +166,20 @@
} \
}()
+#define DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP16_FP8(dlpack_dtype, c_type, ...) \
+ [&]() -> bool { ... | 14 | 0 | 5 | [
"deepseek"
] | [
"GB300"
] | [
"1.35x"
] | Optimize this cpp kernel file from flashinfer (csrc/tvm_ffi_utils.h).
Goal: feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16
Target hardware: GB300
Target models: deepseek
Current file:
```cpp
/*
* Copyright (c) 2023 by FlashInfer tea... | ## Summary
Enable FP8 (E4M3/E5M2) support in `concat_mla_k`, fixing a crash that blocks FP8 chunked prefill for all MLA models (DeepSeek-V2/V3/R1) on long-context workloads.
## Motivation
For long-context inference (ISL >= 4K) in vLLM, chunked prefill + FP8 quantization (`use_prefill_query_quantization: true`) is cr... | [{"scope": "e2e", "hardware": "GB300", "model": "DeepSeek-R1-0528-FP4", "shape": "ISL=128K", "batch_size": 16, "metric": "Median TTFT", "unit": "s", "higher_is_better": false, "baseline": 42.0, "optimized": 30.1, "stated_speedup": null, "speedup": 1.3953}, {"scope": "e2e", "hardware": "GB300", "model": "DeepSeek-R1-052... | null | 1.3681 |
flashinfer | 8d1b69b2b4b73a04895dacc7486bec25416e93c4 | 2026-05-06T21:49:53-07:00 | 3,129 | https://github.com/flashinfer-ai/flashinfer/pull/3129 | feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16 (#3129) | feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16 (#3129)
## Summary
Enable FP8 (E4M3/E5M2) support in `concat_mla_k`, fixing a crash that
blocks FP8 chunked prefill for all MLA models (DeepSeek-V2/V3/R1) on
long-context workloads.
## ... | include/flashinfer/concat_mla.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/concat_mla.cuh
+++ include/flashinfer/concat_mla.cuh
@@ -18,6 +18,7 @@
#include <cuda_bf16.h>
#include <cuda_fp16.h>
+#include <cuda_fp8.h>
#include <cuda_runtime.h>
#include "utils.cuh"
@@ -33,6 +34,91 @@
constexpr int MLA_HEAD_CHUNK_SIZE = 16;
constexpr int MLA_NUM_HEAD_CHUNKS = MLA_N... | 115 | 35 | 5 | [
"deepseek"
] | [
"GB300"
] | [
"1.35x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/concat_mla.cuh).
Goal: feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16
Target hardware: GB300
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2025 by... | ## Summary
Enable FP8 (E4M3/E5M2) support in `concat_mla_k`, fixing a crash that blocks FP8 chunked prefill for all MLA models (DeepSeek-V2/V3/R1) on long-context workloads.
## Motivation
For long-context inference (ISL >= 4K) in vLLM, chunked prefill + FP8 quantization (`use_prefill_query_quantization: true`) is cr... | [{"scope": "e2e", "hardware": "GB300", "model": "DeepSeek-R1-0528-FP4", "shape": "ISL=128K", "batch_size": 16, "metric": "Median TTFT", "unit": "s", "higher_is_better": false, "baseline": 42.0, "optimized": 30.1, "stated_speedup": null, "speedup": 1.3953}, {"scope": "e2e", "hardware": "GB300", "model": "DeepSeek-R1-052... | null | 1.3681 |
flashinfer | 8d1b69b2b4b73a04895dacc7486bec25416e93c4 | 2026-05-06T21:49:53-07:00 | 3,129 | https://github.com/flashinfer-ai/flashinfer/pull/3129 | feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16 (#3129) | feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16 (#3129)
## Summary
Enable FP8 (E4M3/E5M2) support in `concat_mla_k`, fixing a crash that
blocks FP8 chunked prefill for all MLA models (DeepSeek-V2/V3/R1) on
long-context workloads.
## ... | include/flashinfer/utils.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/utils.cuh
+++ include/flashinfer/utils.cuh
@@ -447,6 +447,22 @@
}
/*!
+ * \brief Non-atomic global load for short (2 bytes) with cache streaming hint
+ */
+__forceinline__ __device__ short ld_na_global_s16(const short* addr) {
+ short val;
+ asm volatile("ld.global.cs.b16 %0, [%1];" : "=h"(... | 16 | 0 | 5 | [
"deepseek"
] | [
"GB300"
] | [
"1.35x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/utils.cuh).
Goal: feat: Enable FP8 (E4M3/E5M2) in concat_mla_k for optimize long-context prefill performance and refactor type dispatch for BF16/FP16
Target hardware: GB300
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2023 by Flas... | ## Summary
Enable FP8 (E4M3/E5M2) support in `concat_mla_k`, fixing a crash that blocks FP8 chunked prefill for all MLA models (DeepSeek-V2/V3/R1) on long-context workloads.
## Motivation
For long-context inference (ISL >= 4K) in vLLM, chunked prefill + FP8 quantization (`use_prefill_query_quantization: true`) is cr... | [{"scope": "e2e", "hardware": "GB300", "model": "DeepSeek-R1-0528-FP4", "shape": "ISL=128K", "batch_size": 16, "metric": "Median TTFT", "unit": "s", "higher_is_better": false, "baseline": 42.0, "optimized": 30.1, "stated_speedup": null, "speedup": 1.3953}, {"scope": "e2e", "hardware": "GB300", "model": "DeepSeek-R1-052... | null | 1.3681 |
flashinfer | f684dd537a3609f0261f00d555321c8cbc7fc9b5 | 2026-05-06T20:22:06-07:00 | 3,193 | https://github.com/flashinfer-ai/flashinfer/pull/3193 | perf(moe): optimize SM120 b12x MoE short decode (#3193) | perf(moe): optimize SM120 b12x MoE short decode (#3193)
Synchronize the SM120 b12x MoE implementation from the upstream b12x
kernels, including the short-decode dispatch and micro-kernel fixes.
## 📌 Description
Synchronizes the SM120 B12x MoE implementation with the upstream b12x
kernel changes.
This PR updates ... | flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py | cute_dsl | Apache-2.0 | """SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.
Ported from b12x's integration/tp_moe.py. Supports micro (tiny decode),
static (decode), and dynamic (prefill) backends with token-count-based
selection.
"""
from __future__ import annotations
import os
from dataclasses import dataclass
from typ... | """SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.
Ported from b12x's integration/tp_moe.py. Supports micro (tiny decode),
static (decode), and dynamic (prefill) backends with token-count-based
selection.
"""
from __future__ import annotations
import os
from dataclasses import dataclass
from typ... | --- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py
+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py
@@ -557,6 +557,8 @@
input_scales_are_reciprocal: bool = False,
fast_math: bool = True,
share_input_across_experts: bool = False,
+ share_expert_scales: bool = False,
+ ... | 33 | 18 | 2 | [] | [
"SM120"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_dispatch.py).
Goal: perf(moe): optimize SM120 b12x MoE short decode
Target hardware: SM120
Target models: unspecified
Current file:
```python
"""SM120/SM121 MoE dispatch layer — workspace, compilation, and launch.
P... | Synchronize the SM120 b12x MoE implementation from the upstream b12x
kernels, including the short-decode dispatch and micro-kernel fixes.
## 📌 Description
Synchronizes the SM120 B12x MoE implementation with the upstream b12x kernel changes.
This PR updates the short-decode path for B12x fused MoE, including:
... | [] | null | null |
flashinfer | f684dd537a3609f0261f00d555321c8cbc7fc9b5 | 2026-05-06T20:22:06-07:00 | 3,193 | https://github.com/flashinfer-ai/flashinfer/pull/3193 | perf(moe): optimize SM120 b12x MoE short decode (#3193) | perf(moe): optimize SM120 b12x MoE short decode (#3193)
Synchronize the SM120 b12x MoE implementation from the upstream b12x
kernels, including the short-decode dispatch and micro-kernel fixes.
## 📌 Description
Synchronizes the SM120 B12x MoE implementation with the upstream b12x
kernel changes.
This PR updates ... | flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_micro_kernel.py | cute_dsl | Apache-2.0 | """
MoEMicroKernel — micro-scheduled routed NVFP4 MoE kernel for SM120/SM121 (Blackwell).
Ported from the b12x kernel library to FlashInfer.
This is the micro control-plane fusion step for decode workloads: keep the
proven FC1/FC2 compute body, but pull the route/pack frontend into the same
resident kernel, using pre... | """
MoEMicroKernel — micro-scheduled routed NVFP4 MoE kernel for SM120/SM121 (Blackwell).
Ported from the b12x kernel library to FlashInfer.
This is the micro control-plane fusion step for decode workloads: keep the
proven FC1/FC2 compute body, but pull the route/pack frontend into the same
resident kernel, using pre... | --- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_micro_kernel.py
+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_micro_kernel.py
@@ -33,8 +33,8 @@
What changes relative to the static kernel:
- topk_ids contains LOCAL expert IDs (pre-compacted by Triton pre-pass)
- global expert IDs looked up via weigh... | 78 | 48 | 2 | [] | [
"SM120"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_micro_kernel.py).
Goal: perf(moe): optimize SM120 b12x MoE short decode
Target hardware: SM120
Target models: unspecified
Current file:
```python
"""
MoEMicroKernel — micro-scheduled routed NVFP4 MoE kernel for SM120... | Synchronize the SM120 b12x MoE implementation from the upstream b12x
kernels, including the short-decode dispatch and micro-kernel fixes.
## 📌 Description
Synchronizes the SM120 B12x MoE implementation with the upstream b12x kernel changes.
This PR updates the short-decode path for B12x fused MoE, including:
... | [] | null | null |
flashinfer | 2bb1f857f0467f47b7ed5c0fc2e104a710ae89fa | 2026-05-06T06:11:01-04:00 | 3,227 | https://github.com/flashinfer-ai/flashinfer/pull/3227 | fix: fused MoE autotuning correctness issues by filtering clusterDimZ (#3227) | fix: fused MoE autotuning correctness issues by filtering clusterDimZ (#3227)
## 📌 Description
There has been correctness issues observed using fused MoE autotuning.
Investigating shows tactics using `clusterDimZ >= 1` produces incorrect
outputs. See https://github.com/flashinfer-ai/flashinfer/issues/3197
This PR ch... | csrc/trtllm_batched_gemm_runner.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_batched_gemm_runner.cu
+++ csrc/trtllm_batched_gemm_runner.cu
@@ -121,6 +121,9 @@
}
if (mOptions.transposeMmaOutput && options.mEpilogueTileM == mOptions.epilogueTileM) {
+ // Skip cubins with clusterZ > 1 due to correctness issues described in
+ // https://github.com/flash... | 3 | 0 | 2 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_batched_gemm_runner.cu).
Goal: fix: fused MoE autotuning correctness issues by filtering clusterDimZ
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* ... | ## 📌 Description
There has been correctness issues observed using fused MoE autotuning. Investigating shows tactics using `clusterDimZ >= 1` produces incorrect outputs. See https://github.com/flashinfer-ai/flashinfer/issues/3197
This PR changes the following:
- only allow tactics with `clusterDimZ == 1`
- add test th... | [] | null | null |
flashinfer | 955ddc9599288e7fcb9b26d2cb3960e6451959d5 | 2026-05-06T01:46:39-04:00 | 2,841 | https://github.com/flashinfer-ai/flashinfer/pull/2841 | [Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D (#2841) | [Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D (#2841)
## 📌 Description
This PR wires `trtllm_fmha_v2_prefill` into the `flashinfer_benchmark`
harness and fixes several CUDA-graph-incompatible allocations on the
FMHAv2 prefill hot path.
### Benchmark integration
- Add `trtllm-fmha-v2` a... | csrc/fmha_v2_jit_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023-2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | /*
* Copyright (c) 2023-2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | --- csrc/fmha_v2_jit_binding.cu
+++ csrc/fmha_v2_jit_binding.cu
@@ -32,8 +32,8 @@
int max_q_len, int max_kv_len, int batch_size, const std::string& mask_mode_str,
float scale_softmax, float scale_bmm1, float scale_bmm2, int window_left,
int chunked_attention_size, b... | 2 | 2 | 7 | [] | [
"AMPERE",
"BLACKWELL",
"HOPPER",
"SM120",
"SM80",
"SM90"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/fmha_v2_jit_binding.cu).
Goal: [Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D
Target hardware: AMPERE, BLACKWELL, HOPPER, SM120, SM80, SM90
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023-2025 by FlashInfer team... | ## 📌 Description
This PR wires `trtllm_fmha_v2_prefill` into the `flashinfer_benchmark` harness and fixes several CUDA-graph-incompatible allocations on the FMHAv2 prefill hot path.
### Benchmark integration
- Add `trtllm-fmha-v2` as a backend option for `BatchPrefillWithPagedKVCacheWrapper` and `BatchPrefillWithRa... | [] | null | null |
flashinfer | 955ddc9599288e7fcb9b26d2cb3960e6451959d5 | 2026-05-06T01:46:39-04:00 | 2,841 | https://github.com/flashinfer-ai/flashinfer/pull/2841 | [Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D (#2841) | [Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D (#2841)
## 📌 Description
This PR wires `trtllm_fmha_v2_prefill` into the `flashinfer_benchmark`
harness and fixes several CUDA-graph-incompatible allocations on the
FMHAv2 prefill hot path.
### Benchmark integration
- Add `trtllm-fmha-v2` a... | csrc/fmha_v2_run.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023-2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | /*
* Copyright (c) 2023-2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... | --- csrc/fmha_v2_run.cu
+++ csrc/fmha_v2_run.cu
@@ -211,8 +211,6 @@
}
set_alpha(params.scale_softmax, scale_softmax, scale_softmax_type);
set_alpha(params.scale_bmm2, scale_bmm2, scale_type2);
- // NOTE: scale_bmm2_d is now pre-populated from Python to avoid cudaMemcpy synchronization.
- // The Python side c... | 13 | 19 | 7 | [] | [
"AMPERE",
"BLACKWELL",
"HOPPER",
"SM120",
"SM80",
"SM90"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/fmha_v2_run.cu).
Goal: [Perf] Add FMHAv2 to flashinfer_benchmark.py and eliminate unnecessary H2D
Target hardware: AMPERE, BLACKWELL, HOPPER, SM120, SM80, SM90
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023-2025 by FlashInfer team.
*
* ... | ## 📌 Description
This PR wires `trtllm_fmha_v2_prefill` into the `flashinfer_benchmark` harness and fixes several CUDA-graph-incompatible allocations on the FMHAv2 prefill hot path.
### Benchmark integration
- Add `trtllm-fmha-v2` as a backend option for `BatchPrefillWithPagedKVCacheWrapper` and `BatchPrefillWithRa... | [] | null | null |
flashinfer | 770609920b31b120f74453cf6baf93c4f2a48cc0 | 2026-05-01T20:19:24+04:00 | 2,914 | https://github.com/flashinfer-ai/flashinfer/pull/2914 | feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners (#2914) | feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners (#2914)
## Summary
- **Add cuBLASLt backend for `mm_bf16`**: new `backend="cublaslt"`
option (gated to SM100/SM103). Autotuning across all available cuBLASLt
algorithms via `get_valid_tactics()`.
- **Enable multi-tactic ... | csrc/bmm_fp8.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/bmm_fp8.cu
+++ csrc/bmm_fp8.cu
@@ -49,7 +49,8 @@
auto stream = get_stream(A.device());
auto status = flashinfer::bmm_fp8::bmm_fp8_internal_cublaslt(
- workspace_buffer.data_ptr(), workspace_buffer.numel(),
+ workspace_buffer.data_ptr(),
+ workspace_buffer.nu... | 90 | 1 | 8 | [] | [
"SM100",
"SM103"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/bmm_fp8.cu).
Goal: feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners
Target hardware: SM100, SM103
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the... | ## Summary
- **Add cuBLASLt backend for `mm_bf16`**: new `backend="cublaslt"` option (gated to SM100/SM103). Autotuning across all available cuBLASLt algorithms via `get_valid_tactics()`.
- **Enable multi-tactic autotuning for single-tactic GEMM runners**: `CublasFp8GemmRunner`, `CudnnFp8GemmRunner`, and `CudnnMxfp8G... | [] | null | null |
flashinfer | 770609920b31b120f74453cf6baf93c4f2a48cc0 | 2026-05-01T20:19:24+04:00 | 2,914 | https://github.com/flashinfer-ai/flashinfer/pull/2914 | feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners (#2914) | feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners (#2914)
## Summary
- **Add cuBLASLt backend for `mm_bf16`**: new `backend="cublaslt"`
option (gated to SM100/SM103). Autotuning across all available cuBLASLt
algorithms via `get_valid_tactics()`.
- **Enable multi-tactic ... | csrc/flashinfer_gemm_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/flashinfer_gemm_binding.cu
+++ csrc/flashinfer_gemm_binding.cu
@@ -19,9 +19,19 @@
void bmm_fp8(TensorView A, TensorView B, TensorView D, TensorView A_scale, TensorView B_scale,
TensorView workspace_buffer, int64_t cublas_handle);
+int64_t bmm_fp8_get_algos(TensorView A, TensorView B, TensorVie... | 10 | 0 | 8 | [] | [
"SM100",
"SM103"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/flashinfer_gemm_binding.cu).
Goal: feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners
Target hardware: SM100, SM103
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2023 by FlashInfer team.
*
* Li... | ## Summary
- **Add cuBLASLt backend for `mm_bf16`**: new `backend="cublaslt"` option (gated to SM100/SM103). Autotuning across all available cuBLASLt algorithms via `get_valid_tactics()`.
- **Enable multi-tactic autotuning for single-tactic GEMM runners**: `CublasFp8GemmRunner`, `CudnnFp8GemmRunner`, and `CudnnMxfp8G... | [] | null | null |
flashinfer | 770609920b31b120f74453cf6baf93c4f2a48cc0 | 2026-05-01T20:19:24+04:00 | 2,914 | https://github.com/flashinfer-ai/flashinfer/pull/2914 | feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners (#2914) | feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners (#2914)
## Summary
- **Add cuBLASLt backend for `mm_bf16`**: new `backend="cublaslt"`
option (gated to SM100/SM103). Autotuning across all available cuBLASLt
algorithms via `get_valid_tactics()`.
- **Enable multi-tactic ... | include/flashinfer/gemm/bmm_fp8.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/gemm/bmm_fp8.cuh
+++ include/flashinfer/gemm/bmm_fp8.cuh
@@ -19,6 +19,8 @@
#include <cublasLt.h>
#include <cuda_fp8.h>
+#include <array>
+#include <cstring>
#include <iostream>
#include <memory>
#include <type_traits>
@@ -137,6 +139,107 @@
}
}
+static constexpr int kMaxFp8Algorithms ... | 103 | 0 | 8 | [] | [
"SM100",
"SM103"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/gemm/bmm_fp8.cuh).
Goal: feat: Add cuBLASLt backend for `mm_bf16` and enable multi-tactic autotuning for FP8/MXFP8 runners
Target hardware: SM100, SM103
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
... | ## Summary
- **Add cuBLASLt backend for `mm_bf16`**: new `backend="cublaslt"` option (gated to SM100/SM103). Autotuning across all available cuBLASLt algorithms via `get_valid_tactics()`.
- **Enable multi-tactic autotuning for single-tactic GEMM runners**: `CublasFp8GemmRunner`, `CudnnFp8GemmRunner`, and `CudnnMxfp8G... | [] | null | null |
flashinfer | cc682da57a11534a957f5a40b67533435e724b6c | 2026-04-24T01:53:23-07:00 | 3,151 | https://github.com/flashinfer-ai/flashinfer/pull/3151 | perf: Add no-bias path for tinygemm_bf16 (#3151) | perf: Add no-bias path for tinygemm_bf16 (#3151)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
This PR updates tinygemm_bf16 to use a dedicated no-bias kernel path
when `bias=None`, **avoiding the previous zero-bias ma... | csrc/tinygemm2.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2025-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/tinygemm2.cu
+++ csrc/tinygemm2.cu
@@ -141,7 +141,7 @@
// ============================================================================
template <int WARP_TILE_M, int TILE_M, int TILE_N, int TILE_K, int STAGES, int STAGE_UNROLL,
- bool USE_PDL = false>
+ bool USE_PDL = false, bool HAS_BIAS... | 51 | 26 | 2 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/tinygemm2.cu).
Goal: perf: Add no-bias path for tinygemm_bf16
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
This PR updates tinygemm_bf16 to use a dedicated no-bias kernel path when `bias=None`, **avoiding the previous zero-bias materialization in the Python wrapper**. It also add... | [] | null | null |
flashinfer | d4544921ca2abee84077679988bfc91f69acd5e8 | 2026-04-24T00:26:57+08:00 | 3,084 | https://github.com/flashinfer-ai/flashinfer/pull/3084 | perf: optimize MXFP4xBF16 & INT4xFP8 CUTLASS MoE backend for SM90 (#3084) | perf: optimize MXFP4xBF16 & INT4xFP8 CUTLASS MoE backend for SM90 (#3084)
## Summary
Port [TensorRT-LLM PR
#12451](https://github.com/NVIDIA/TensorRT-LLM/pull/12451) to
FlashInfer's `cutlass_fused_moe` SM90 path. Adds an LDSM +
interleaved-LUT weight-load pipeline for 4-bit weights × 16/8-bit
activations, plus the tw... | csrc/fused_moe/cutlass_backend/flashinfer_cutlass_fused_moe_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/fused_moe/cutlass_backend/flashinfer_cutlass_fused_moe_binding.cu
+++ csrc/fused_moe/cutlass_backend/flashinfer_cutlass_fused_moe_binding.cu
@@ -29,6 +29,7 @@
#include "moe_gemm_kernels.h"
#include "tensorrt_llm/common/workspace.h"
#include "tensorrt_llm/kernels/cutlass_kernels/fp8_blockscale_gemm/fp8_block... | 45 | 0 | 7 | [] | [
"H200",
"SM90"
] | [
"2.66×",
"3.02×",
"3.11×"
] | Optimize this cuda kernel file from flashinfer (csrc/fused_moe/cutlass_backend/flashinfer_cutlass_fused_moe_binding.cu).
Goal: perf: optimize MXFP4xBF16 & INT4xFP8 CUTLASS MoE backend for SM90
Target hardware: H200, SM90
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2022-2024, NVIDIA CORPORATIO... | ## Summary
Port [TensorRT-LLM PR #12451](https://github.com/NVIDIA/TensorRT-LLM/pull/12451) to FlashInfer's `cutlass_fused_moe` SM90 path. Adds an LDSM + interleaved-LUT weight-load pipeline for 4-bit weights × 16/8-bit activations, plus the two preprocessing helpers the new kernel layout requires.
## Changes
### Ke... | [{"scope": "e2e", "hardware": "H200", "model": null, "shape": "hidden=4096,intermediate=2048,experts=256,topk=6", "batch_size": 4, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.513, "optimized": 0.193, "stated_speedup": 2.66, "speedup": 2.658}, {"scope": "e2e", "hardware": "H200", "model":... | null | 3.0207 |
flashinfer | d4544921ca2abee84077679988bfc91f69acd5e8 | 2026-04-24T00:26:57+08:00 | 3,084 | https://github.com/flashinfer-ai/flashinfer/pull/3084 | perf: optimize MXFP4xBF16 & INT4xFP8 CUTLASS MoE backend for SM90 (#3084) | perf: optimize MXFP4xBF16 & INT4xFP8 CUTLASS MoE backend for SM90 (#3084)
## Summary
Port [TensorRT-LLM PR
#12451](https://github.com/NVIDIA/TensorRT-LLM/pull/12451) to
FlashInfer's `cutlass_fused_moe` SM90 path. Adds an LDSM +
interleaved-LUT weight-load pipeline for 4-bit weights × 16/8-bit
activations, plus the tw... | csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/detail/collective/mixed_input_utils.hpp | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/detail/collective/mixed_input_utils.hpp
+++ csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/detail/collective/mixed_input_utils.hpp
@@ -29,6 +29,8 @@
typedef uint32_t __nv_fp4x8_storage_t;
typedef uint32_t __... | 331 | 34 | 7 | [] | [
"H200",
"SM90"
] | [
"2.66×",
"3.02×",
"3.11×"
] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/detail/collective/mixed_input_utils.hpp).
Goal: perf: optimize MXFP4xBF16 & INT4xFP8 CUTLASS MoE backend for SM90
Target hardware: H200, SM90
Target models: unspecified
Current file:
```cpp
/*
*... | ## Summary
Port [TensorRT-LLM PR #12451](https://github.com/NVIDIA/TensorRT-LLM/pull/12451) to FlashInfer's `cutlass_fused_moe` SM90 path. Adds an LDSM + interleaved-LUT weight-load pipeline for 4-bit weights × 16/8-bit activations, plus the two preprocessing helpers the new kernel layout requires.
## Changes
### Ke... | [{"scope": "e2e", "hardware": "H200", "model": null, "shape": "hidden=4096,intermediate=2048,experts=256,topk=6", "batch_size": 4, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.513, "optimized": 0.193, "stated_speedup": 2.66, "speedup": 2.658}, {"scope": "e2e", "hardware": "H200", "model":... | null | 3.0207 |
flashinfer | d4544921ca2abee84077679988bfc91f69acd5e8 | 2026-04-24T00:26:57+08:00 | 3,084 | https://github.com/flashinfer-ai/flashinfer/pull/3084 | perf: optimize MXFP4xBF16 & INT4xFP8 CUTLASS MoE backend for SM90 (#3084) | perf: optimize MXFP4xBF16 & INT4xFP8 CUTLASS MoE backend for SM90 (#3084)
## Summary
Port [TensorRT-LLM PR
#12451](https://github.com/NVIDIA/TensorRT-LLM/pull/12451) to
FlashInfer's `cutlass_fused_moe` SM90 path. Adds an LDSM +
interleaved-LUT weight-load pipeline for 4-bit weights × 16/8-bit
activations, plus the tw... | csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm/collective/sm90_mma_array_tma_gmma_rs_warpspecialized_mixed_input_.hpp | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm/collective/sm90_mma_array_tma_gmma_rs_warpspecialized_mixed_input_.hpp
+++ csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm/collective/sm90_mma_array_tma_gmma_rs_warpspecialized_mixed_input_.hpp
@@ -246,... | 291 | 162 | 7 | [] | [
"H200",
"SM90"
] | [
"2.66×",
"3.02×",
"3.11×"
] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm/collective/sm90_mma_array_tma_gmma_rs_warpspecialized_mixed_input_.hpp).
Goal: perf: optimize MXFP4xBF16 & INT4xFP8 CUTLASS MoE backend for SM90
Target hardware: H200, SM90
Target models: uns... | ## Summary
Port [TensorRT-LLM PR #12451](https://github.com/NVIDIA/TensorRT-LLM/pull/12451) to FlashInfer's `cutlass_fused_moe` SM90 path. Adds an LDSM + interleaved-LUT weight-load pipeline for 4-bit weights × 16/8-bit activations, plus the two preprocessing helpers the new kernel layout requires.
## Changes
### Ke... | [{"scope": "e2e", "hardware": "H200", "model": null, "shape": "hidden=4096,intermediate=2048,experts=256,topk=6", "batch_size": 4, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.513, "optimized": 0.193, "stated_speedup": 2.66, "speedup": 2.658}, {"scope": "e2e", "hardware": "H200", "model":... | null | 3.0207 |
flashinfer | d4544921ca2abee84077679988bfc91f69acd5e8 | 2026-04-24T00:26:57+08:00 | 3,084 | https://github.com/flashinfer-ai/flashinfer/pull/3084 | perf: optimize MXFP4xBF16 & INT4xFP8 CUTLASS MoE backend for SM90 (#3084) | perf: optimize MXFP4xBF16 & INT4xFP8 CUTLASS MoE backend for SM90 (#3084)
## Summary
Port [TensorRT-LLM PR
#12451](https://github.com/NVIDIA/TensorRT-LLM/pull/12451) to
FlashInfer's `cutlass_fused_moe` SM90 path. Adds an LDSM +
interleaved-LUT weight-load pipeline for 4-bit weights × 16/8-bit
activations, plus the tw... | csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/cutlass_heuristic.cpp | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/cutlass_heuristic.cpp
+++ csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/cutlass_heuristic.cpp
@@ -389,9 +389,16 @@
(config & CutlassGemmConfig::WEIGHT_ONLY) && (config & CutlassGemmConfig::GROUPED_GEMM);
if (has_w4afp8) {
bool const ... | 8 | 1 | 7 | [] | [
"H200",
"SM90"
] | [
"2.66×",
"3.02×",
"3.11×"
] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/cutlass_heuristic.cpp).
Goal: perf: optimize MXFP4xBF16 & INT4xFP8 CUTLASS MoE backend for SM90
Target hardware: H200, SM90
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORA... | ## Summary
Port [TensorRT-LLM PR #12451](https://github.com/NVIDIA/TensorRT-LLM/pull/12451) to FlashInfer's `cutlass_fused_moe` SM90 path. Adds an LDSM + interleaved-LUT weight-load pipeline for 4-bit weights × 16/8-bit activations, plus the two preprocessing helpers the new kernel layout requires.
## Changes
### Ke... | [{"scope": "e2e", "hardware": "H200", "model": null, "shape": "hidden=4096,intermediate=2048,experts=256,topk=6", "batch_size": 4, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.513, "optimized": 0.193, "stated_speedup": 2.66, "speedup": 2.658}, {"scope": "e2e", "hardware": "H200", "model":... | null | 3.0207 |
flashinfer | 57c37bf2c4fcebd6f1a70cc6f62a68e20b530d60 | 2026-04-14T07:20:41+03:00 | 2,882 | https://github.com/flashinfer-ai/flashinfer/pull/2882 | perf: Fix silent bug with FP8 per tensor non-gated MoE (#2882) | perf: Fix silent bug with FP8 per tensor non-gated MoE (#2882)
<!-- .github/pull_request_template.md -->
## 📌 Description
This PR fixed a **silent bug** that forces fallback tactic with _TRTLLM
MoE FP8 and non-gated models_ (Nemotron).
```
[Autotuner]: Failed to get valid tactics for ... Error occurred: FP8 per-ten... | csrc/trtllm_fused_moe_kernel_launcher.cu | cuda | Apache-2.0 | /*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distribut... | /*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distribut... | --- csrc/trtllm_fused_moe_kernel_launcher.cu
+++ csrc/trtllm_fused_moe_kernel_launcher.cu
@@ -2268,12 +2268,6 @@
} else if ((quantization_type == Fp8QuantizationType::PerTensorFp8 ||
quantization_type == Fp8QuantizationType::NoneFp8) &&
dtype_weights == btg::Dtype::E4m3) {
- // FP8 pe... | 0 | 6 | 1 | [
"deepseek",
"nemotron"
] | [
"GB200"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_fused_moe_kernel_launcher.cu).
Goal: perf: Fix silent bug with FP8 per tensor non-gated MoE
Target hardware: GB200
Target models: deepseek, nemotron
Current file:
```cuda
/*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not us... | <!-- .github/pull_request_template.md -->
## 📌 Description
This PR fixed a **silent bug** that forces fallback tactic with _TRTLLM MoE FP8 and non-gated models_ (Nemotron).
```
[Autotuner]: Failed to get valid tactics for ... Error occurred: FP8 per-tensor currently supports gated activations only, got act_type=6
``... | [] | null | null |
flashinfer | c0adda7d866084326d8e4d81e173767a76634d85 | 2026-04-10T08:46:31-07:00 | 3,026 | https://github.com/flashinfer-ai/flashinfer/pull/3026 | perf: Port TRT-LLM SM120/SM121 FP4 CUTLASS GEMM optimizations. Add PDL (#3026) | perf: Port TRT-LLM SM120/SM121 FP4 CUTLASS GEMM optimizations. Add PDL (#3026)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
### Summary
- Port TRT-LLM's SM120 CUTLASS FP4 GEMM template parameters for better
kernel pe... | include/flashinfer/gemm/fp4_gemm_template_sm120.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/fp4_gemm_template_sm120.h
+++ include/flashinfer/gemm/fp4_gemm_template_sm120.h
@@ -185,8 +185,8 @@
std::string(cutlass::cutlassGetStatusString(initStatus)));
}
- // Disable PDL since GDC flag is not set
- auto runStatus = gemm.run(args, workspace, stream... | 23 | 23 | 1 | [] | [
"RTX5090",
"SM100",
"SM120",
"SM121"
] | [
"1.38x",
"1.24x",
"1.18x",
"1.05x",
"1.39x",
"1.08x",
"1.42x",
"1.01x",
"1.43x",
"1.13x"
] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp4_gemm_template_sm120.h).
Goal: perf: Port TRT-LLM SM120/SM121 FP4 CUTLASS GEMM optimizations. Add PDL
Target hardware: RTX5090, SM100, SM120, SM121
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATIO... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
### Summary
- Port TRT-LLM's SM120 CUTLASS FP4 GEMM template parameters for better kernel performance
- [TRT-LLM reference file: nvfp4_nvfp4_gemm_template_sm120.h](https:... | [] | null | null |
flashinfer | ee3ca012e6be1a3361b23e218b649c74a6ee3b98 | 2026-04-04T01:39:31+02:00 | 2,927 | https://github.com/flashinfer-ai/flashinfer/pull/2927 | feat: SM121 (GB10) tile filtering and autotuner robustness (#2927) | feat: SM121 (GB10) tile filtering and autotuner robustness (#2927)
## Summary
- **Unified SMEM tile filter** — extracted `tile_fits_smem(sm, m, n,
k_elem, config, stages=2)` helper that encodes the per-architecture SMEM
limit (102,400 B for SM 8.6/8.9/12.x, per CUDA Programming Guide) and is
shared by both the SM12x ... | csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/cutlass_heuristic.cpp | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/cutlass_heuristic.cpp
+++ csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/cutlass_heuristic.cpp
@@ -61,6 +61,7 @@
case CutlassTileConfig::CtaShape64x128x64_WarpShape64x32x64:
return TileShape{64, 128};
case CutlassTileConfig::CtaShape128x6... | 21 | 43 | 3 | [
"mamba",
"nemotron"
] | [
"AMPERE",
"BLACKWELL",
"GB200",
"SM100",
"SM12",
"SM120",
"SM121"
] | [
"2×"
] | Optimize this cpp kernel file from flashinfer (csrc/nv_internal/tensorrt_llm/kernels/cutlass_kernels/cutlass_heuristic.cpp).
Goal: feat: SM121 (GB10) tile filtering and autotuner robustness
Target hardware: AMPERE, BLACKWELL, GB200, SM100, SM12, SM120, SM121
Target models: mamba, nemotron
Current file:
```cpp
/*
* C... | ## Summary
- **Unified SMEM tile filter** — extracted `tile_fits_smem(sm, m, n, k_elem, config, stages=2)` helper that encodes the per-architecture SMEM limit (102,400 B for SM 8.6/8.9/12.x, per CUDA Programming Guide) and is shared by both the SM12x TMA WS path and the Ampere mainloop path.
- **SM12x FP4 tile filteri... | [] | null | null |
flashinfer | 5758837a8594c15aaae14e4e638fa4e634632c53 | 2026-04-04T07:00:26+08:00 | 2,956 | https://github.com/flashinfer-ai/flashinfer/pull/2956 | fix: [Fmha] revert blackwell ultra optimization that causes deadlocks. (#2956) | fix: [Fmha] revert blackwell ultra optimization that causes deadlocks. (#2956)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Th... | include/flashinfer/trtllm/fmha/kernelParams.h | cpp | BSD | /***************************************************************************************************
* Copyright (c) 2011-2024, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are not permit-
* ted.
*
* THIS SOFTWARE IS PROVIDED BY THE... | /***************************************************************************************************
* Copyright (c) 2011-2024, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are not permit-
* ted.
*
* THIS SOFTWARE IS PROVIDED BY THE... | --- include/flashinfer/trtllm/fmha/kernelParams.h
+++ include/flashinfer/trtllm/fmha/kernelParams.h
@@ -416,7 +416,8 @@
// strides are read from the tensor and passed to the TMA descriptor.
template <class FmhaOptions>
static auto makeTmaShapeStrideKv(FmhaOptions const& options, KernelParams const& params,... | 63 | 31 | 2 | [] | [
"BLACKWELL"
] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/fmha/kernelParams.h).
Goal: fix: [Fmha] revert blackwell ultra optimization that causes deadlocks.
Target hardware: BLACKWELL
Target models: unspecified
Current file:
```cpp
/**********************************************************************... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull Request Checklist
Thank you for contributing to FlashInfer! Before we review your pull request, plea... | [] | null | null |
flashinfer | d476c61c3f8bcbbca30755b330a0c10b141dede3 | 2026-04-01T12:08:51-07:00 | 2,904 | https://github.com/flashinfer-ai/flashinfer/pull/2904 | perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904) | perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904)
<!-- .github/pull_request_template.md -->
## 📌 Description
**Summary**
- Adopt dual-path kernel architecture (linear flat + swizzled row-based)
for MXFP4 and NVFP4 CuTe-DSL quantization kernels.
- Architecture chanes to MXFP8 quantization for better p... | flashinfer/cute_dsl/fp4_common.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/cute_dsl/fp4_common.py
+++ flashinfer/cute_dsl/fp4_common.py
@@ -190,6 +190,23 @@
],
"st.global.u64 [$0], $1;",
"l,l",
+ has_side_effects=True,
+ is_align_stack=False,
+ asm_dialect=llvm.AsmDialect.AD_ATT,
+ )
+
+
+@dsl_user_op
+def st_global_u32(base_pt... | 17 | 0 | 6 | [] | [
"B200"
] | [
"5x",
"1.42x",
"1.37x",
"1.41x",
"1.39x",
"1.34x",
"1.32x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/fp4_common.py).
Goal: perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels
Target hardware: B200
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (th... | <!-- .github/pull_request_template.md -->
## 📌 Description
**Summary**
- Adopt dual-path kernel architecture (linear flat + swizzled row-based) for MXFP4 and NVFP4 CuTe-DSL quantization kernels.
- Architecture chanes to MXFP8 quantization for better perf.
- Expand benchmark scripts and test coverage across all three... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "Linear", "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.42, "speedup": 1.42}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "Swizzled", "batc... | 1.38 | null |
flashinfer | d476c61c3f8bcbbca30755b330a0c10b141dede3 | 2026-04-01T12:08:51-07:00 | 2,904 | https://github.com/flashinfer-ai/flashinfer/pull/2904 | perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904) | perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904)
<!-- .github/pull_request_template.md -->
## 📌 Description
**Summary**
- Adopt dual-path kernel architecture (linear flat + swizzled row-based)
for MXFP4 and NVFP4 CuTe-DSL quantization kernels.
- Architecture chanes to MXFP8 quantization for better p... | flashinfer/quantization/kernels/mxfp8_quantize.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/quantization/kernels/mxfp8_quantize.py
+++ flashinfer/quantization/kernels/mxfp8_quantize.py
@@ -50,17 +50,24 @@
ELTS_PER_THREAD,
THREADS_PER_SF,
SF_BLOCKS_PER_WARP,
+ ELTS_PER_THREAD_SMALL,
+ THREADS_PER_SF_SMALL,
+ SF_BLOCKS_PER_WARP_SMALL,
+ MXFP8_2T_SF_THRESHOLD,
ROW_T... | 311 | 130 | 6 | [] | [
"B200"
] | [
"5x",
"1.42x",
"1.37x",
"1.41x",
"1.39x",
"1.34x",
"1.32x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/quantization/kernels/mxfp8_quantize.py).
Goal: perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels
Target hardware: B200
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License,... | <!-- .github/pull_request_template.md -->
## 📌 Description
**Summary**
- Adopt dual-path kernel architecture (linear flat + swizzled row-based) for MXFP4 and NVFP4 CuTe-DSL quantization kernels.
- Architecture chanes to MXFP8 quantization for better perf.
- Expand benchmark scripts and test coverage across all three... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "Linear", "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.42, "speedup": 1.42}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "Swizzled", "batc... | 1.38 | null |
flashinfer | d476c61c3f8bcbbca30755b330a0c10b141dede3 | 2026-04-01T12:08:51-07:00 | 2,904 | https://github.com/flashinfer-ai/flashinfer/pull/2904 | perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904) | perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904)
<!-- .github/pull_request_template.md -->
## 📌 Description
**Summary**
- Adopt dual-path kernel architecture (linear flat + swizzled row-based)
for MXFP4 and NVFP4 CuTe-DSL quantization kernels.
- Architecture chanes to MXFP8 quantization for better p... | flashinfer/quantization/kernels/nvfp4_quantize.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/quantization/kernels/nvfp4_quantize.py
+++ flashinfer/quantization/kernels/nvfp4_quantize.py
@@ -19,10 +19,15 @@
NVFP4 quantization kernel using CuTe-DSL.
Supports multiple scale factor layouts: swizzled 128x4, swizzled 8x4, and linear.
+Dual-path optimization following the MXFP4 pattern:
+- Linear l... | 417 | 221 | 6 | [] | [
"B200"
] | [
"5x",
"1.42x",
"1.37x",
"1.41x",
"1.39x",
"1.34x",
"1.32x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/quantization/kernels/nvfp4_quantize.py).
Goal: perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels
Target hardware: B200
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License,... | <!-- .github/pull_request_template.md -->
## 📌 Description
**Summary**
- Adopt dual-path kernel architecture (linear flat + swizzled row-based) for MXFP4 and NVFP4 CuTe-DSL quantization kernels.
- Architecture chanes to MXFP8 quantization for better perf.
- Expand benchmark scripts and test coverage across all three... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "Linear", "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.42, "speedup": 1.42}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "Swizzled", "batc... | 1.38 | null |
flashinfer | d476c61c3f8bcbbca30755b330a0c10b141dede3 | 2026-04-01T12:08:51-07:00 | 2,904 | https://github.com/flashinfer-ai/flashinfer/pull/2904 | perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904) | perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels (#2904)
<!-- .github/pull_request_template.md -->
## 📌 Description
**Summary**
- Adopt dual-path kernel architecture (linear flat + swizzled row-based)
for MXFP4 and NVFP4 CuTe-DSL quantization kernels.
- Architecture chanes to MXFP8 quantization for better p... | flashinfer/quantization/quantization_cute_dsl_utils.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/quantization/quantization_cute_dsl_utils.py
+++ flashinfer/quantization/quantization_cute_dsl_utils.py
@@ -39,9 +39,19 @@
# Thread organization constants
WARP_SIZE = 32
-ELTS_PER_THREAD = 8 # Each thread handles 8 FP16 elements (128 bits)
-THREADS_PER_SF = SF_VEC_SIZE // ELTS_PER_THREAD # 32 / 8 = ... | 43 | 13 | 6 | [] | [
"B200"
] | [
"5x",
"1.42x",
"1.37x",
"1.41x",
"1.39x",
"1.34x",
"1.32x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/quantization/quantization_cute_dsl_utils.py).
Goal: perf: Optimize CuTe-DSL fp4 and fp8 quantization kernels
Target hardware: B200
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache Lic... | <!-- .github/pull_request_template.md -->
## 📌 Description
**Summary**
- Adopt dual-path kernel architecture (linear flat + swizzled row-based) for MXFP4 and NVFP4 CuTe-DSL quantization kernels.
- Architecture chanes to MXFP8 quantization for better perf.
- Expand benchmark scripts and test coverage across all three... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "Linear", "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.42, "speedup": 1.42}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "Swizzled", "batc... | 1.38 | null |
flashinfer | e679e45383d2621681a06c39670448be59a817c9 | 2026-03-20T21:38:48+02:00 | 2,821 | https://github.com/flashinfer-ai/flashinfer/pull/2821 | fix: Autotuner _find_nearest_profile non-power-of-2 num_tokens, create launchers for all supported tileN in trtllm fused MoE (#2821) | fix: Autotuner _find_nearest_profile non-power-of-2 num_tokens, create launchers for all supported tileN in trtllm fused MoE (#2821)
## 📌 Description
It fixes two autotuner related bugs:
1. Revert back the autotuner fix that was reverted in
https://github.com/flashinfer-ai/flashinfer/pull/2697
2. Fix the issue that
... | csrc/trtllm_fused_moe_kernel_launcher.cu | cuda | Apache-2.0 | /*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distribut... | /*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distribut... | --- csrc/trtllm_fused_moe_kernel_launcher.cu
+++ csrc/trtllm_fused_moe_kernel_launcher.cu
@@ -91,12 +91,26 @@
std::set<int32_t> computeSelectedTileN(std::vector<int32_t> const& supported_tile_nums,
int64_t const num_tokens, int64_t const top_k,
... | 88 | 63 | 2 | [
"nemotron"
] | [
"SM100"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_fused_moe_kernel_launcher.cu).
Goal: fix: Autotuner _find_nearest_profile non-power-of-2 num_tokens, create launchers for all supported tileN in trtllm fused MoE
Target hardware: SM100
Target models: nemotron
Current file:
```cuda
/*
* Licensed under the Ap... | ## 📌 Description
It fixes two autotuner related bugs:
1. Revert back the autotuner fix that was reverted in https://github.com/flashinfer-ai/flashinfer/pull/2697
2. Fix the issue that https://github.com/flashinfer-ai/flashinfer/pull/2697 revealed, which is trtllm fused MoE kernel launcher crash when it receives tileN... | [] | null | null |
flashinfer | f7322d91610cf20b30f1c60422fb038dcc3858d5 | 2026-03-17T15:08:21-07:00 | 2,777 | https://github.com/flashinfer-ai/flashinfer/pull/2777 | perf: Performance tune cute dsl RMSNorm variants (#2777) | perf: Performance tune cute dsl RMSNorm variants (#2777)
<!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
Rewrites all CuTe-DSL RMSNorm kernel variants (`rmsnorm`,
`gemma_rmsnorm`, `fused_add_rmsnorm`, `gemma_fused_add_rm... | flashinfer/norm/utils.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/norm/utils.py
+++ flashinfer/norm/utils.py
@@ -25,6 +25,7 @@
- Type conversion utilities
"""
+import functools
import math
import operator
from typing import Callable
@@ -183,6 +184,124 @@
)
+@dsl_user_op
+def cvt_and_store_8xf32_to_e4m3_hw(
+ v0: Float32,
+ v1: Float32,
+ v2: Fl... | 323 | 0 | 3 | [
"gemma"
] | [
"B200",
"H200",
"SM90"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/norm/utils.py).
Goal: perf: Performance tune cute dsl RMSNorm variants
Target hardware: B200, H200, SM90
Target models: gemma
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License"... | <!-- .github/pull_request_template.md -->
## 📌 Description
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
Rewrites all CuTe-DSL RMSNorm kernel variants (`rmsnorm`, `gemma_rmsnorm`, `fused_add_rmsnorm`, `gemma_fused_add_rmsnorm`, `rmsnorm_quant`, `fused_add_rmsnorm_quant`, `qk_rm... | [] | null | null |
flashinfer | 4f422f5b4783d73041d9dda8fecc6a17c9d21603 | 2026-03-03T11:18:05+02:00 | 2,667 | https://github.com/flashinfer-ai/flashinfer/pull/2667 | perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act (#2667) | perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act (#2667)
## 📌 Description
Updates the trtllm-gen batched GEMM kernel hashes and
`include/flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export` directory
for:
* Faster batched GEMM kernels
* Additional NVFP4 tile dims kern... | csrc/trtllm_batched_gemm_runner.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/trtllm_batched_gemm_runner.cu
+++ csrc/trtllm_batched_gemm_runner.cu
@@ -258,8 +258,9 @@
// FIXME once we start using all-reduce in the epilogue of the bmm this can be moved elsewhere
bmm.runInitBeforeWorldSync(config, gemmData, static_cast<void*>(stream));
- auto const err = bmm.run(config, workspace... | 3 | 2 | 2 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_batched_gemm_runner.cu).
Goal: perf: Update trtllm-gen batched GEMM kernels - faster, more NVFP4 tile dims, MXFP8 with relu2 act
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2020-2025, NVIDIA CORPORATION. ... | ## 📌 Description
Updates the trtllm-gen batched GEMM kernel hashes and `include/flashinfer/trtllm/batched_gemm/trtllmGen_bmm_export` directory for:
* Faster batched GEMM kernels
* Additional NVFP4 tile dims kernels
* Additional MXFP8 with Relu^2 non-gated activation kernels
## 🔍 Related Issues
<!-- Link any relate... | [] | null | null |
flashinfer | 1589ebb405b437dab5a3b0ca3b77097da0959071 | 2026-02-26T11:08:00-08:00 | 2,588 | https://github.com/flashinfer-ai/flashinfer/pull/2588 | Perf: Optimize GDN decode pretranspose kernel for all batch sizes (#2588) | Perf: Optimize GDN decode pretranspose kernel for all batch sizes (#2588)
Two optimizations:
1. Early gate reads: Move gate GMEM reads (r_A_log, r_a, r_dt_bias, r_b)
to immediately before the barrier, hiding memory latency during sync.
2. Always use 8-CTA architecture: Remove batch size conditional that
switched to ... | flashinfer/gdn_decode.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/gdn_decode.py
+++ flashinfer/gdn_decode.py
@@ -186,47 +186,48 @@
i_h = i_hv // (HV // H)
i_t = 0
+ smem = cutlass.utils.SmemAllocator()
+
+ # ===================================================================
+ # Allocate shared memory (using passed-in layout)
+ # ===============... | 40 | 42 | 1 | [] | [] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_decode.py).
Goal: Perf: Optimize GDN decode pretranspose kernel for all batch sizes
Target hardware: unspecified
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version ... | Two optimizations:
1. Early gate reads: Move gate GMEM reads (r_A_log, r_a, r_dt_bias, r_b) to immediately before the barrier, hiding memory latency during sync.
2. Always use 8-CTA architecture: Remove batch size conditional that switched to big_batch (1 CTA) for B > 32. The 8-CTA small_batch kernel performs better ... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "q_heads=16,k_heads=16,v_heads=32,head_size=128", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 3.74, "optimized": 3.74, "stated_speedup": null, "speedup": 1.0}, {"scope": "kernel", "hardware": null, "model": nul... | 1.0019 | null |
flashinfer | 58128d1218979256e7fd487473758dd906f6f853 | 2026-02-24T01:30:22+09:00 | 2,609 | https://github.com/flashinfer-ai/flashinfer/pull/2609 | docs: resolve TODO by documenting log2f vs logf performance rationale in sampling (#2609) | docs: resolve TODO by documenting log2f vs logf performance rationale in sampling (#2609)
## Summary
Resolved the TODO comment in `sampling.cuh` regarding `log2f` vs `logf`
performance comparison.
## Changes
- Removed `// TODO: compare the speed of log2 and log`
- Added documentation explaining why `log2f` is preferr... | include/flashinfer/sampling.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/sampling.cuh
+++ include/flashinfer/sampling.cuh
@@ -664,9 +664,11 @@
// and including 1.0. kSCALE is used to exclude 1.0, s.t.
// 1.18e-38 <= x * kSCALE <= 1.0f - epsilon
// => -4.47 <= -log(-log(...)) <= 15.9
+ // log2f maps to a single PTX LG2 instru... | 3 | 1 | 1 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/sampling.cuh).
Goal: docs: resolve TODO by documenting log2f vs logf performance rationale in sampling
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the ... | ## Summary
Resolved the TODO comment in `sampling.cuh` regarding `log2f` vs `logf` performance comparison.
## Changes
- Removed `// TODO: compare the speed of log2 and log`
- Added documentation explaining why `log2f` is preferred:
- `log2f` maps to a single PTX `LG2` instruction on NVIDIA GPUs
- `logf` internally... | [] | null | null |
flashinfer | 30bf78e1a05d18aaebd484aa6f3c1db8e4c0b1b4 | 2026-02-10T06:38:50+08:00 | 2,509 | https://github.com/flashinfer-ai/flashinfer/pull/2509 | perf: cache cudaGetDeviceProperties in gdn_prefill to avoid per-call overhead (#2509) | perf: cache cudaGetDeviceProperties in gdn_prefill to avoid per-call overhead (#2509)
## Summary
- Cache `device_properties.major` and
`device_properties.multiProcessorCount` using
`static thread_local` variables in `gdn_prefill_launcher()` and
`gdn_prefill()`
respectively, instead of calling `cudaGetDeviceProperties`... | csrc/gdn_prefill_launcher.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law o... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law o... | --- csrc/gdn_prefill_launcher.cu
+++ csrc/gdn_prefill_launcher.cu
@@ -42,11 +42,11 @@
DISPATCH_DLPACK_DTYPE_TO_CTYPE_FP16(dtype, DType, [&] {
int dev_id;
cudaGetDevice(&dev_id);
- cudaDeviceProp device_properties;
- cudaGetDeviceProperties(&device_properties, dev_id);
+ int device_major;
+ cuda... | 7 | 8 | 1 | [] | [
"CPU"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/gdn_prefill_launcher.cu).
Goal: perf: cache cudaGetDeviceProperties in gdn_prefill to avoid per-call overhead
Target hardware: CPU
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License,... | ## Summary
- Cache `device_properties.major` and `device_properties.multiProcessorCount` using
`static thread_local` variables in `gdn_prefill_launcher()` and `gdn_prefill()`
respectively, instead of calling `cudaGetDeviceProperties` on every invocation.
- Each `cudaGetDeviceProperties` call adds ~1ms of synchronou... | [] | null | null |
flashinfer | 99562e5eeaa26b08ba5e514bfe22d84404390ca6 | 2026-02-06T16:01:50-08:00 | 2,398 | https://github.com/flashinfer-ai/flashinfer/pull/2398 | feat: cuteDSL fp4 moe for better DSR1 performance. (#2398) | feat: cuteDSL fp4 moe for better DSR1 performance. (#2398)
<!-- .github/pull_request_template.md -->
## 📌 Description
cuteDSL fp4 moe from TRTLLM with fusion. issue #2259
The collective fusion performance improvement collected from TRTLLM [PR
8880](https://github.com/NVIDIA/TensorRT-LLM/pull/8880), [PR
9288](https:... | flashinfer/cute_dsl/utils.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/cute_dsl/utils.py
+++ flashinfer/cute_dsl/utils.py
@@ -17,13 +17,18 @@
import ctypes
import functools
import importlib.util
-from typing import Union
+from typing import Union, Tuple
import cutlass
import cutlass._mlir.dialects.cute as _cute_ir
import torch
from cutlass._mlir import ir
from cut... | 174 | 1 | 6 | [
"deepseek"
] | [
"BLACKWELL"
] | [
"1.53x",
"0.83x",
"1.40x",
"0.83x",
"1.35x",
"0.88x",
"1.36x",
"0.94x",
"1.35x",
"1.02x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/utils.py).
Goal: feat: cuteDSL fp4 moe for better DSR1 performance.
Target hardware: BLACKWELL
Target models: deepseek
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "Licens... | <!-- .github/pull_request_template.md -->
## 📌 Description
cuteDSL fp4 moe from TRTLLM with fusion. issue #2259
The collective fusion performance improvement collected from TRTLLM [PR 8880](https://github.com/NVIDIA/TensorRT-LLM/pull/8880), [PR 9288](https://github.com/NVIDIA/TensorRT-LLM/pull/9288), [PR 9618](htt... | [{"scope": "kernel", "hardware": null, "model": "DeepSeek-V3", "shape": null, "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.098, "optimized": 0.064, "stated_speedup": 1.53, "speedup": 1.5312}, {"scope": "kernel", "hardware": null, "model": "DeepSeek-V3", "shape": null, "ba... | 1.245 | null |
flashinfer | 99562e5eeaa26b08ba5e514bfe22d84404390ca6 | 2026-02-06T16:01:50-08:00 | 2,398 | https://github.com/flashinfer-ai/flashinfer/pull/2398 | feat: cuteDSL fp4 moe for better DSR1 performance. (#2398) | feat: cuteDSL fp4 moe for better DSR1 performance. (#2398)
<!-- .github/pull_request_template.md -->
## 📌 Description
cuteDSL fp4 moe from TRTLLM with fusion. issue #2259
The collective fusion performance improvement collected from TRTLLM [PR
8880](https://github.com/NVIDIA/TensorRT-LLM/pull/8880), [PR
9288](https:... | flashinfer/gemm/kernels/grouped_gemm_masked_blackwell.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | # Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the abov... | --- flashinfer/gemm/kernels/grouped_gemm_masked_blackwell.py
+++ flashinfer/gemm/kernels/grouped_gemm_masked_blackwell.py
@@ -61,6 +61,7 @@
get_cutlass_dtype,
cutlass_to_torch_dtype,
get_num_sm,
+ get_max_active_clusters,
make_ptr,
)
from typing import Callable, List
@@ -2621,10 +2622,9 @@
... | 3 | 3 | 6 | [
"deepseek"
] | [
"BLACKWELL"
] | [
"1.53x",
"0.83x",
"1.40x",
"0.83x",
"1.35x",
"0.88x",
"1.36x",
"0.94x",
"1.35x",
"1.02x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gemm/kernels/grouped_gemm_masked_blackwell.py).
Goal: feat: cuteDSL fp4 moe for better DSR1 performance.
Target hardware: BLACKWELL
Target models: deepseek
Current file:
```python
# Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
... | <!-- .github/pull_request_template.md -->
## 📌 Description
cuteDSL fp4 moe from TRTLLM with fusion. issue #2259
The collective fusion performance improvement collected from TRTLLM [PR 8880](https://github.com/NVIDIA/TensorRT-LLM/pull/8880), [PR 9288](https://github.com/NVIDIA/TensorRT-LLM/pull/9288), [PR 9618](htt... | [{"scope": "kernel", "hardware": null, "model": "DeepSeek-V3", "shape": null, "batch_size": 1, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.098, "optimized": 0.064, "stated_speedup": 1.53, "speedup": 1.5312}, {"scope": "kernel", "hardware": null, "model": "DeepSeek-V3", "shape": null, "ba... | 1.245 | null |
flashinfer | 57ef44b9d7ada00cb50ca26310f9c3a3bfbc0dd2 | 2026-02-06T14:55:45+08:00 | 2,460 | https://github.com/flashinfer-ai/flashinfer/pull/2460 | perf: add fp4 GEMM tile configs and streamK scheduler for SM120 (#2460) | perf: add fp4 GEMM tile configs and streamK scheduler for SM120 (#2460)
<!-- .github/pull_request_template.md -->
## 📌 Description
Add SM120 FP4 GEMM tile configs and enable streamK scheduler for configs
that can be selected by autotuner.
Take the problem size m=32, n=5120, k=25600 as an example. After adding
these... | include/flashinfer/gemm/cutlass_gemm_configs.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/cutlass_gemm_configs.h
+++ include/flashinfer/gemm/cutlass_gemm_configs.h
@@ -348,6 +348,7 @@
bool enableCudaKernel = false;
int sm_version = 80; // Use 80 as a catch all for <90
bool is_tma_warp_specialized = false;
+ bool use_stream_k = false; // SM120: false = DP scheduler (de... | 10 | 2 | 4 | [] | [
"SM120"
] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/cutlass_gemm_configs.h).
Goal: perf: add fp4 GEMM tile configs and streamK scheduler for SM120
Target hardware: SM120
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Li... | <!-- .github/pull_request_template.md -->
## 📌 Description
Add SM120 FP4 GEMM tile configs and enable streamK scheduler for configs that can be selected by autotuner.
Take the problem size m=32, n=5120, k=25600 as an example. After adding these configs, the latency of mm_fp4 kernel reduced from 0.124ms to 0.069ms on... | [{"scope": "kernel", "hardware": "RTX PRO 6000", "model": null, "shape": "m=32,n=5120,k=25600", "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.124, "optimized": 0.069, "stated_speedup": null, "speedup": 1.7971}, {"scope": "kernel", "hardware": "RTX PRO 6000", "model": nu... | 1.7993 | null |
flashinfer | 57ef44b9d7ada00cb50ca26310f9c3a3bfbc0dd2 | 2026-02-06T14:55:45+08:00 | 2,460 | https://github.com/flashinfer-ai/flashinfer/pull/2460 | perf: add fp4 GEMM tile configs and streamK scheduler for SM120 (#2460) | perf: add fp4 GEMM tile configs and streamK scheduler for SM120 (#2460)
<!-- .github/pull_request_template.md -->
## 📌 Description
Add SM120 FP4 GEMM tile configs and enable streamK scheduler for configs
that can be selected by autotuner.
Take the problem size m=32, n=5120, k=25600 as an example. After adding
these... | include/flashinfer/gemm/fp4_gemm_cutlass_template_sm120.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/fp4_gemm_cutlass_template_sm120.h
+++ include/flashinfer/gemm/fp4_gemm_cutlass_template_sm120.h
@@ -44,7 +44,8 @@
namespace gemm {
using namespace cute;
-template <typename T, typename CTA_M_, typename CTA_N_, typename CTA_K_>
+// UseStreamK: false = DP scheduler (default), true = Stream... | 61 | 28 | 4 | [] | [
"SM120"
] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp4_gemm_cutlass_template_sm120.h).
Goal: perf: add fp4 GEMM tile configs and streamK scheduler for SM120
Target hardware: SM120
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserve... | <!-- .github/pull_request_template.md -->
## 📌 Description
Add SM120 FP4 GEMM tile configs and enable streamK scheduler for configs that can be selected by autotuner.
Take the problem size m=32, n=5120, k=25600 as an example. After adding these configs, the latency of mm_fp4 kernel reduced from 0.124ms to 0.069ms on... | [{"scope": "kernel", "hardware": "RTX PRO 6000", "model": null, "shape": "m=32,n=5120,k=25600", "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.124, "optimized": 0.069, "stated_speedup": null, "speedup": 1.7971}, {"scope": "kernel", "hardware": "RTX PRO 6000", "model": nu... | 1.7993 | null |
flashinfer | 57ef44b9d7ada00cb50ca26310f9c3a3bfbc0dd2 | 2026-02-06T14:55:45+08:00 | 2,460 | https://github.com/flashinfer-ai/flashinfer/pull/2460 | perf: add fp4 GEMM tile configs and streamK scheduler for SM120 (#2460) | perf: add fp4 GEMM tile configs and streamK scheduler for SM120 (#2460)
<!-- .github/pull_request_template.md -->
## 📌 Description
Add SM120 FP4 GEMM tile configs and enable streamK scheduler for configs
that can be selected by autotuner.
Take the problem size m=32, n=5120, k=25600 as an example. After adding
these... | include/flashinfer/gemm/fp4_gemm_template_sm120.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/fp4_gemm_template_sm120.h
+++ include/flashinfer/gemm/fp4_gemm_template_sm120.h
@@ -31,6 +31,7 @@
#include "cutlass/gemm/collective/collective_builder.hpp"
#include "cutlass/gemm/device/gemm_universal_adapter.h"
#include "cutlass/gemm/gemm.h"
+#include "cutlass/gemm/kernel/tile_scheduler.... | 153 | 105 | 4 | [] | [
"SM120"
] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/fp4_gemm_template_sm120.h).
Goal: perf: add fp4 GEMM tile configs and streamK scheduler for SM120
Target hardware: SM120
Target models: unspecified
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
*... | <!-- .github/pull_request_template.md -->
## 📌 Description
Add SM120 FP4 GEMM tile configs and enable streamK scheduler for configs that can be selected by autotuner.
Take the problem size m=32, n=5120, k=25600 as an example. After adding these configs, the latency of mm_fp4 kernel reduced from 0.124ms to 0.069ms on... | [{"scope": "kernel", "hardware": "RTX PRO 6000", "model": null, "shape": "m=32,n=5120,k=25600", "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.124, "optimized": 0.069, "stated_speedup": null, "speedup": 1.7971}, {"scope": "kernel", "hardware": "RTX PRO 6000", "model": nu... | 1.7993 | null |
flashinfer | 5e5a8668bede32d86035dba98f460a278332e366 | 2026-02-03T04:42:54-08:00 | 2,405 | https://github.com/flashinfer-ai/flashinfer/pull/2405 | perf: improve gdn decode cute-dsl kernels (#2405) | perf: improve gdn decode cute-dsl kernels (#2405)
<!-- .github/pull_request_template.md -->
## 📌 Description
Follow up of #2370 , this PR improves the benchmark scripts and add
comparison with baselines:
* benchmark using cupti with l2 flush
* compare with sglang's `fused_sigmoid_gating_delta_rule_update`
function ... | flashinfer/gdn_decode.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/gdn_decode.py
+++ flashinfer/gdn_decode.py
@@ -90,10 +90,43 @@
# ============================================================================
# Global configuration for MTP (Multiple Token Processing) version
# ============================================================================
-TILE_V_MTP = ... | 438 | 343 | 1 | [] | [
"B200"
] | [
"1.59x",
"0.86x",
"1.35x",
"0.73x",
"1.49x",
"0.85x",
"1.37x",
"0.79x",
"1.40x",
"0.86x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/gdn_decode.py).
Goal: perf: improve gdn decode cute-dsl kernels
Target hardware: B200
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may no... | <!-- .github/pull_request_template.md -->
## 📌 Description
Follow up of #2370 , this PR improves the benchmark scripts and add comparison with baselines:
* benchmark using cupti with l2 flush
* compare with sglang's `fused_sigmoid_gating_delta_rule_update` function (with tile size optimization mentioned by @ vadikly... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "q_heads=16,k_heads=16,v_heads=32,head_size=128,dtype=bfloat16", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 5.95, "optimized": 3.74, "stated_speedup": null, "speedup": 1.5909}, {"scope": "kernel", "hardware"... | 1.1332 | null |
flashinfer | c7761add6e6b7703ce5f12b03be387e78048f36b | 2026-02-03T05:57:24+01:00 | 2,303 | https://github.com/flashinfer-ai/flashinfer/pull/2303 | [Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels (#2303) | [Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels (#2303)
## Summary
This PR adds new template specializations for SM103 NVFP4 CUTLASS GEMM
kernels using architecture-specific tile shapes, cluster shapes, and
schedulers.
## Motivation
SM103 specifications show a higher NVFP4-over-BF16 speedup ... | include/flashinfer/gemm/cutlass_gemm_configs.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/cutlass_gemm_configs.h
+++ include/flashinfer/gemm/cutlass_gemm_configs.h
@@ -133,6 +133,11 @@
CtaShape256x64x128B,
CtaShape256x128x128B,
CtaShape256x256x128B,
+
+ // SM103
+ CtaShape128x128x768B,
+ CtaShape128x192x768B,
+ CtaShape128x256x768B,
};
enum class CutlassTileConfi... | 28 | 2 | 4 | [
"llama"
] | [
"B200",
"SM100",
"SM103"
] | [
"6×",
"4×"
] | Optimize this cpp kernel file from flashinfer (include/flashinfer/gemm/cutlass_gemm_configs.h).
Goal: [Perf][Feature] Add SM103-specific schedulers for NVFP4 CUTLASS kernels
Target hardware: B200, SM100, SM103
Target models: llama
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights res... | ## Summary
This PR adds new template specializations for SM103 NVFP4 CUTLASS GEMM kernels using architecture-specific tile shapes, cluster shapes, and schedulers.
## Motivation
SM103 specifications show a higher NVFP4-over-BF16 speedup ratio than B200 (6× vs. 4×), but current kernels remain far from this limit.
Th... | [{"scope": "e2e", "hardware": "SM103", "model": "Llama-3.1-70B", "shape": "N=8192,K=28672", "batch_size": 8, "metric": "TFLOPS", "unit": "TFLOP/s", "higher_is_better": true, "baseline": 110.598008, "optimized": 124.005817, "stated_speedup": null, "speedup": 1.1212}, {"scope": "e2e", "hardware": "SM103", "model": "Llama... | null | 1.0674 |
flashinfer | aa8af8534579653a8006be47a6517c103dfb761d | 2026-01-23T17:23:57+08:00 | 2,343 | https://github.com/flashinfer-ai/flashinfer/pull/2343 | Optimize quantization function in large problem size (#2343) | Optimize quantization function in large problem size (#2343)
<!-- .github/pull_request_template.md -->
## 📌 Description
Optimize quantization function in large problem size by using TMA and
warp specialized programming.
<!-- What does this PR do? Briefly describe the changes and why they’re
needed. -->
## 🔍 Relat... | csrc/nv_internal/cpp/kernels/quantization.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- csrc/nv_internal/cpp/kernels/quantization.cu
+++ csrc/nv_internal/cpp/kernels/quantization.cu
@@ -14,6 +14,8 @@
* limitations under the License.
*/
+#include <cuda.h>
+#include <cudaTypedefs.h>
#include <float.h>
#include "tensorrt_llm/common/assert.h"
@@ -93,6 +95,7 @@
int32... | 154 | 1 | 3 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/nv_internal/cpp/kernels/quantization.cu).
Goal: Optimize quantization function in large problem size
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* License... | <!-- .github/pull_request_template.md -->
## 📌 Description
Optimize quantization function in large problem size by using TMA and warp specialized programming.
<!-- What does this PR do? Briefly describe the changes and why they’re needed. -->
## 🔍 Related Issues
<!-- Link any related issues here -->
## 🚀 Pull ... | [] | null | null |
flashinfer | 18804cd51734cccf807356d017733bc757677f15 | 2026-01-21T22:28:56-08:00 | 2,387 | https://github.com/flashinfer-ai/flashinfer/pull/2387 | A Blackwell-optimized version of selective_state_update (mamba) (#2387) | A Blackwell-optimized version of selective_state_update (mamba) (#2387)
<!-- .github/pull_request_template.md -->
## 📌 Description
This contributes a `selective_state_update` kernel that has been
manually optimized for sm100.
<img width="3000" height="3000" alt="runtime_vs_batch_size_NVIDIA_B200"
src="https://gith... | include/flashinfer/mamba/selective_state_update.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/mamba/selective_state_update.cuh
+++ include/flashinfer/mamba/selective_state_update.cuh
@@ -33,6 +33,8 @@
using namespace conversion;
+constexpr unsigned warpSize = 32;
+
struct SelectiveStateUpdateParams {
uint32_t batch{}, nheads{}, dim{}, dstate{}, ngroups{}, state_cache_size{};
i... | 478 | 8 | 5 | [
"mamba"
] | [
"BLACKWELL",
"HOPPER",
"SM100",
"SM90"
] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/mamba/selective_state_update.cuh).
Goal: A Blackwell-optimized version of selective_state_update (mamba)
Target hardware: BLACKWELL, HOPPER, SM100, SM90
Target models: mamba
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Lice... | <!-- .github/pull_request_template.md -->
## 📌 Description
This contributes a `selective_state_update` kernel that has been manually optimized for sm100.
<img width="3000" height="3000" alt="runtime_vs_batch_size_NVIDIA_B200" src="https://github.com/user-attachments/assets/2718d992-1066-4385-b120-d22eccd3a941" />
... | [] | null | null |
flashinfer | 2bf87713dade8c6094ca3ff5e246e1ff72e97644 | 2026-01-13T22:44:35-08:00 | 2,327 | https://github.com/flashinfer-ai/flashinfer/pull/2327 | [perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32 (#2327) | [perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32 (#2327)
<!-- .github/pull_request_template.md -->
## 📌 Description
Improves gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch
sizes <= 32.
These are shapes typical for DeepSeek V3 and Qwen 3 235B - q, k, v, and
o_proj:... | csrc/gemm_groupwise_sm100.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/gemm_groupwise_sm100.cu
+++ csrc/gemm_groupwise_sm100.cu
@@ -80,8 +80,17 @@
int MmaSM, typename DTypeIn, typename DTypeOut>
cudaError_t CutlassGroupwiseScaledGEMMSM100(void* float_buffer, size_t float_buffer_size_in_bytes,
DTypeIn* A_ptr, DTypeIn* B_ptr,... | 38 | 10 | 2 | [
"deepseek",
"qwen"
] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/gemm_groupwise_sm100.cu).
Goal: [perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32
Target hardware: unspecified
Target models: deepseek, qwen
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under... | <!-- .github/pull_request_template.md -->
## 📌 Description
Improves gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32.
These are shapes typical for DeepSeek V3 and Qwen 3 235B - q, k, v, and o_proj:
```
+-------+-------+------+-----------+---------------+--------------+---------------+-------... | [{"scope": "kernel", "hardware": null, "model": "DeepSeek V3, Qwen 3 235B", "shape": "out=1536,in=7168", "batch_size": 8, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 24.58, "optimized": 20.48, "stated_speedup": 1.2, "speedup": 1.2002}, {"scope": "kernel", "hardware": null, "model": "DeepSe... | 1.1997 | null |
flashinfer | 2bf87713dade8c6094ca3ff5e246e1ff72e97644 | 2026-01-13T22:44:35-08:00 | 2,327 | https://github.com/flashinfer-ai/flashinfer/pull/2327 | [perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32 (#2327) | [perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32 (#2327)
<!-- .github/pull_request_template.md -->
## 📌 Description
Improves gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch
sizes <= 32.
These are shapes typical for DeepSeek V3 and Qwen 3 235B - q, k, v, and
o_proj:... | include/flashinfer/gemm/gemm_groupwise_sm100.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2025 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- include/flashinfer/gemm/gemm_groupwise_sm100.cuh
+++ include/flashinfer/gemm/gemm_groupwise_sm100.cuh
@@ -17,6 +17,7 @@
#define FLASHINFER_GEMM_GROUPWISE_SM100_CUH_
#include <type_traits>
+#include <utility>
#include "../allocator.h"
#include "../cutlass_utils.cuh"
@@ -32,7 +33,7 @@
int MmaSM, ty... | 148 | 3 | 2 | [
"deepseek",
"qwen"
] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/gemm/gemm_groupwise_sm100.cuh).
Goal: [perf] Improve gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32
Target hardware: unspecified
Target models: deepseek, qwen
Current file:
```cuda
/*
* Copyright (c) 2025 by FlashInfer team.
... | <!-- .github/pull_request_template.md -->
## 📌 Description
Improves gemm_fp8_nt_groupwise (cutlass backend) by 10-40% for batch sizes <= 32.
These are shapes typical for DeepSeek V3 and Qwen 3 235B - q, k, v, and o_proj:
```
+-------+-------+------+-----------+---------------+--------------+---------------+-------... | [{"scope": "kernel", "hardware": null, "model": "DeepSeek V3, Qwen 3 235B", "shape": "out=1536,in=7168", "batch_size": 8, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 24.58, "optimized": 20.48, "stated_speedup": 1.2, "speedup": 1.2002}, {"scope": "kernel", "hardware": null, "model": "DeepSe... | 1.1997 | null |
flashinfer | 4ccc133c216f3ceaf49fc94ba8ad5984feb0f039 | 2026-01-13T22:20:39+01:00 | 2,323 | https://github.com/flashinfer-ai/flashinfer/pull/2323 | [ML3] Optimized Router Gemm (#2323) | [ML3] Optimized Router Gemm (#2323) | csrc/dsv3_router_gemm.cu | cuda | Apache-2.0 | #include "flashinfer/gemm/dsv3_router_gemm.cuh"
#include "tvm_ffi_utils.h"
namespace flashinfer::trtllm_dsv3_router_gemm {
template <typename T, int kNumTokens, int kNumExperts, int kHiddenDim>
void invokeRouterGemm(float* output, T const* mat_a, T const* mat_b, cudaStream_t stream,
bool use_pdl ... | #include "flashinfer/gemm/dsv3_router_gemm.cuh"
#include "tvm_ffi_utils.h"
namespace flashinfer::trtllm_dsv3_router_gemm {
// Note: Explicit template instantiations are not needed here because
// LoopUnroller already forces instantiation of all required specializations.
template <typename Tin, typename Tout, int kNum... | --- csrc/dsv3_router_gemm.cu
+++ csrc/dsv3_router_gemm.cu
@@ -2,10 +2,13 @@
#include "tvm_ffi_utils.h"
namespace flashinfer::trtllm_dsv3_router_gemm {
-template <typename T, int kNumTokens, int kNumExperts, int kHiddenDim>
-void invokeRouterGemm(float* output, T const* mat_a, T const* mat_b, cudaStream_t stream,
+
... | 33 | 80 | 5 | [
"deepseek"
] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/dsv3_router_gemm.cu).
Goal: [ML3] Optimized Router Gemm
Target hardware: unspecified
Target models: deepseek
Current file:
```cuda
#include "flashinfer/gemm/dsv3_router_gemm.cuh"
#include "tvm_ffi_utils.h"
namespace flashinfer::trtllm_dsv3_router_gemm {
template <... | <!-- .github/pull_request_template.md -->
## 📌 Description
This PR extends #2019 by @nvmbreughe for use with Mistral Large 3, which has similar MoE routing to DSV3. The differences are:
- The number of experts is 128 (DSV3: 256)
- The output type is `bfloat16` (DSV3: `float32`)
The code has been extended with a tem... | [{"scope": "kernel", "hardware": "B200", "model": "Mistral Large 3", "shape": "M=16,K=7168,N=128", "batch_size": 16, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 45.6, "optimized": 9.41, "stated_speedup": null, "speedup": 4.8459}] | 4.8459 | null |
flashinfer | 4ccc133c216f3ceaf49fc94ba8ad5984feb0f039 | 2026-01-13T22:20:39+01:00 | 2,323 | https://github.com/flashinfer-ai/flashinfer/pull/2323 | [ML3] Optimized Router Gemm (#2323) | [ML3] Optimized Router Gemm (#2323) | include/flashinfer/gemm/dsv3_router_gemm.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/gemm/dsv3_router_gemm.cuh
+++ include/flashinfer/gemm/dsv3_router_gemm.cuh
@@ -39,9 +39,10 @@
}
}
-template <typename T, int kBlockSize, int VPT, int kNumTokens, int kNumExperts, int kHiddenDim>
-__global__ __launch_bounds__(128, 1) void router_gemm_kernel(float* out, T const* mat_a,
- ... | 5 | 4 | 5 | [
"deepseek"
] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/gemm/dsv3_router_gemm.cuh).
Goal: [ML3] Optimized Router Gemm
Target hardware: unspecified
Target models: deepseek
Current file:
```cuda
/*
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, ... | <!-- .github/pull_request_template.md -->
## 📌 Description
This PR extends #2019 by @nvmbreughe for use with Mistral Large 3, which has similar MoE routing to DSV3. The differences are:
- The number of experts is 128 (DSV3: 256)
- The output type is `bfloat16` (DSV3: `float32`)
The code has been extended with a tem... | [{"scope": "kernel", "hardware": "B200", "model": "Mistral Large 3", "shape": "M=16,K=7168,N=128", "batch_size": 16, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 45.6, "optimized": 9.41, "stated_speedup": null, "speedup": 4.8459}] | 4.8459 | null |
flashinfer | e079eee48dec413adb66d4a142e3eb66f9f42b6f | 2026-01-08T07:48:37+08:00 | 2,265 | https://github.com/flashinfer-ai/flashinfer/pull/2265 | [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265) | [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265)
<!-- .github/pull_request_template.md -->
## 📌 Description
This MR adds the optimized decode attention kernels for high throughput
(large batch size) + speculative decoding (seqlen_q > 1).
See below for spe... | csrc/trtllm_fmha_kernel_launcher.cu | cuda | Apache-2.0 | /*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distribut... | /*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distribut... | --- csrc/trtllm_fmha_kernel_launcher.cu
+++ csrc/trtllm_fmha_kernel_launcher.cu
@@ -159,8 +159,11 @@
runner_params.cumSeqLensQPtr = cum_seq_lens_q;
runner_params.cumSeqLensKvPtr = cum_seq_lens_kv;
} else {
- // ForGen
- runner_params.mMaskType = TrtllmGenAttentionMaskType::Dense;
+ // Generation.
... | 5 | 2 | 5 | [
"qwen",
"gpt-oss"
] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/trtllm_fmha_kernel_launcher.cu).
Goal: [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding
Target hardware: unspecified
Target models: qwen, gpt-oss
Current file:
```cuda
/*
* Licensed under the Apache License, Vers... | <!-- .github/pull_request_template.md -->
## 📌 Description
This MR adds the optimized decode attention kernels for high throughput (large batch size) + speculative decoding (seqlen_q > 1).
See below for speedups (collected by `benchmarks/flashinfer_benchmark.py`). The seqlenKv is 16K for all cases.
| test case ... | [] | null | null |
flashinfer | e079eee48dec413adb66d4a142e3eb66f9f42b6f | 2026-01-08T07:48:37+08:00 | 2,265 | https://github.com/flashinfer-ai/flashinfer/pull/2265 | [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265) | [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265)
<!-- .github/pull_request_template.md -->
## 📌 Description
This MR adds the optimized decode attention kernels for high throughput
(large batch size) + speculative decoding (seqlen_q > 1).
See below for spe... | include/flashinfer/trtllm/fmha/fmhaKernels.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless r... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless r... | --- include/flashinfer/trtllm/fmha/fmhaKernels.cuh
+++ include/flashinfer/trtllm/fmha/fmhaKernels.cuh
@@ -19,6 +19,7 @@
#include <cuda.h>
#include <cstdint>
+#include <cuda/std/cfloat>
#include <iterator>
#include <memory>
#include <mutex>
@@ -51,6 +52,16 @@
} // namespace flashinfer::trtllm_cubin_loader
usin... | 394 | 176 | 5 | [
"qwen",
"gpt-oss"
] | [] | [] | Optimize this cuda kernel file from flashinfer (include/flashinfer/trtllm/fmha/fmhaKernels.cuh).
Goal: [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding
Target hardware: unspecified
Target models: qwen, gpt-oss
Current file:
```cuda
/*
* Copyright (c) 2020-2023, NVI... | <!-- .github/pull_request_template.md -->
## 📌 Description
This MR adds the optimized decode attention kernels for high throughput (large batch size) + speculative decoding (seqlen_q > 1).
See below for speedups (collected by `benchmarks/flashinfer_benchmark.py`). The seqlenKv is 16K for all cases.
| test case ... | [] | null | null |
flashinfer | e079eee48dec413adb66d4a142e3eb66f9f42b6f | 2026-01-08T07:48:37+08:00 | 2,265 | https://github.com/flashinfer-ai/flashinfer/pull/2265 | [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265) | [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265)
<!-- .github/pull_request_template.md -->
## 📌 Description
This MR adds the optimized decode attention kernels for high throughput
(large batch size) + speculative decoding (seqlen_q > 1).
See below for spe... | include/flashinfer/trtllm/fmha/fmhaRunnerParams.h | cpp | Apache-2.0 | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless ... | --- include/flashinfer/trtllm/fmha/fmhaRunnerParams.h
+++ include/flashinfer/trtllm/fmha/fmhaRunnerParams.h
@@ -348,12 +348,16 @@
bool mForceGmemReduction;
// The mask type.
TrtllmGenAttentionMaskType mMaskType;
+ // The number of tokens per page.
+ int mNumTokensPerPage;
// Reuse smemK for V or not (only... | 6 | 0 | 5 | [
"qwen",
"gpt-oss"
] | [] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/fmha/fmhaRunnerParams.h).
Goal: [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding
Target hardware: unspecified
Target models: qwen, gpt-oss
Current file:
```cpp
/*
* Copyright (c) 2020-2023, NV... | <!-- .github/pull_request_template.md -->
## 📌 Description
This MR adds the optimized decode attention kernels for high throughput (large batch size) + speculative decoding (seqlen_q > 1).
See below for speedups (collected by `benchmarks/flashinfer_benchmark.py`). The seqlenKv is 16K for all cases.
| test case ... | [] | null | null |
flashinfer | e079eee48dec413adb66d4a142e3eb66f9f42b6f | 2026-01-08T07:48:37+08:00 | 2,265 | https://github.com/flashinfer-ai/flashinfer/pull/2265 | [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265) | [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding (#2265)
<!-- .github/pull_request_template.md -->
## 📌 Description
This MR adds the optimized decode attention kernels for high throughput
(large batch size) + speculative decoding (seqlen_q > 1).
See below for spe... | include/flashinfer/trtllm/fmha/kernelParams.h | cpp | BSD | /***************************************************************************************************
* Copyright (c) 2011-2024, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are not permit-
* ted.
*
* THIS SOFTWARE IS PROVIDED BY THE... | /***************************************************************************************************
* Copyright (c) 2011-2024, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are not permit-
* ted.
*
* THIS SOFTWARE IS PROVIDED BY THE... | --- include/flashinfer/trtllm/fmha/kernelParams.h
+++ include/flashinfer/trtllm/fmha/kernelParams.h
@@ -30,6 +30,36 @@
#include "../../utils.cuh"
#include "../common.h"
#include "fmhaRunnerParams.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////
+
+//
+// CCCL... | 64 | 13 | 5 | [
"qwen",
"gpt-oss"
] | [] | [] | Optimize this cpp kernel file from flashinfer (include/flashinfer/trtllm/fmha/kernelParams.h).
Goal: [TRTLLM-Gen Fmha] add optimized trtllm-gen decode kernels for high throughput + speculative decoding
Target hardware: unspecified
Target models: qwen, gpt-oss
Current file:
```cpp
/************************************... | <!-- .github/pull_request_template.md -->
## 📌 Description
This MR adds the optimized decode attention kernels for high throughput (large batch size) + speculative decoding (seqlen_q > 1).
See below for speedups (collected by `benchmarks/flashinfer_benchmark.py`). The seqlenKv is 16K for all cases.
| test case ... | [] | null | null |
flashinfer | 4de2a45a5d38da7487ec37b694c644d8906551a6 | 2025-12-27T15:53:00+08:00 | 2,268 | https://github.com/flashinfer-ai/flashinfer/pull/2268 | [performance]optimize for nvfp4 (#2268) | [performance]optimize for nvfp4 (#2268)
<!-- .github/pull_request_template.md -->
## 📌 Description
I find the nvfp4 implemantation could only 1.3-1.4x speedup compared to
fp8 in deepseek-v3-0324 model .
and as the fp4 pflops is twice that of fp8, I think there should be some
points that could be optimization.
now ... | include/flashinfer/comm/trtllm_allreduce_fusion.cuh | cuda | Apache-2.0 | #include <cooperative_groups.h>
#include <cuda.h>
#include <cuda_bf16.h>
#include <cuda_fp16.h>
#if CUDA_VERSION >= 12080
#include <cuda_fp4.h>
#endif
#include <cuda/std/optional>
#include <tuple>
#include <type_traits>
#include "../exception.h"
#include "../fp4_layout.cuh"
#include "../logging.h"
#include "../utils... | #include <cooperative_groups.h>
#include <cuda.h>
#include <cuda_bf16.h>
#include <cuda_fp16.h>
#if CUDA_VERSION >= 12080
#include <cuda_fp4.h>
#endif
#include <cuda/std/optional>
#include <tuple>
#include <type_traits>
#include "../exception.h"
#include "../fp4_layout.cuh"
#include "../logging.h"
#include "../utils... | --- include/flashinfer/comm/trtllm_allreduce_fusion.cuh
+++ include/flashinfer/comm/trtllm_allreduce_fusion.cuh
@@ -529,6 +529,26 @@
uint32_t val3 = c3;
return (val3 << 24) | (val2 << 16) | (val1 << 8) | val0;
+}
+
+// Convert single float2 pair to e2m1 (2 float32 -> 2 e2m1, returns uint8_t)
+// Optimization: a... | 102 | 41 | 1 | [
"deepseek"
] | [] | [
"1.4x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/comm/trtllm_allreduce_fusion.cuh).
Goal: [performance]optimize for nvfp4
Target hardware: unspecified
Target models: deepseek
Current file:
```cuda
#include <cooperative_groups.h>
#include <cuda.h>
#include <cuda_bf16.h>
#include <cuda_fp16.h>
#if CU... | <!-- .github/pull_request_template.md -->
## 📌 Description
I find the nvfp4 implemantation could only 1.3-1.4x speedup compared to fp8 in deepseek-v3-0324 model .
and as the fp4 pflops is twice that of fp8, I think there should be some points that could be optimization.
now after applying this pr, we can get an ext... | [{"scope": "e2e", "hardware": null, "model": "DeepSeek-V3-0324", "shape": null, "batch_size": 60, "metric": "throughput", "unit": "tok/s", "higher_is_better": true, "baseline": 1192.91, "optimized": 1369.89, "stated_speedup": 1.148, "speedup": 1.1484}] | null | 1.1484 |
flashinfer | 3a301a102c6a2ba7b52030910899a405bad156b0 | 2025-12-18T21:45:15-08:00 | 2,215 | https://github.com/flashinfer-ai/flashinfer/pull/2215 | feat: further optimize top-k and add fused top-k page construction kernels for DSA (#2215) | feat: further optimize top-k and add fused top-k page construction kernels for DSA (#2215) | csrc/flashinfer_topk_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/flashinfer_topk_binding.cu
+++ csrc/flashinfer_topk_binding.cu
@@ -20,5 +20,25 @@
void radix_topk(TensorView input, TensorView output_indices, TensorView output_values,
Optional<TensorView> maybe_row_states_buffer, int64_t top_k);
+void radix_topk_page_table_transform(TensorView input, Tens... | 20 | 0 | 5 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/flashinfer_topk_binding.cu).
Goal: feat: further optimize top-k and add fused top-k page construction kernels for DSA
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the... | <!-- .github/pull_request_template.md -->
## 📌 Description
Follow up of #2119 , this PR implements `top_k_page_table_transform` and `top_k_ragged_transform` function required for dsa in sglang. (fp16/bf16/fp32 are supported), as requested in #2221 .
This PR also adds the more top-k algorithm to choose from:
1. filt... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "seq_len=4096,k=2048", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 8.06, "optimized": 8.03, "stated_speedup": 1.0, "speedup": 1.0037}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "seq_len=... | 0.7785 | null |
flashinfer | 3a301a102c6a2ba7b52030910899a405bad156b0 | 2025-12-18T21:45:15-08:00 | 2,215 | https://github.com/flashinfer-ai/flashinfer/pull/2215 | feat: further optimize top-k and add fused top-k page construction kernels for DSA (#2215) | feat: further optimize top-k and add fused top-k page construction kernels for DSA (#2215) | csrc/topk.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/topk.cu
+++ csrc/topk.cu
@@ -14,6 +14,7 @@
* limitations under the License.
*/
#include <flashinfer/sampling.cuh>
+#include <flashinfer/topk.cuh>
#include "tvm_ffi_utils.h"
@@ -46,15 +47,105 @@
static_cast<sampling::RadixRowState*>(maybe_row_states_buffer.value().data_ptr());
}
+ // Us... | 96 | 5 | 5 | [] | [] | [] | Optimize this cuda kernel file from flashinfer (csrc/topk.cu).
Goal: feat: further optimize top-k and add fused top-k page construction kernels for DSA
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Ve... | <!-- .github/pull_request_template.md -->
## 📌 Description
Follow up of #2119 , this PR implements `top_k_page_table_transform` and `top_k_ragged_transform` function required for dsa in sglang. (fp16/bf16/fp32 are supported), as requested in #2221 .
This PR also adds the more top-k algorithm to choose from:
1. filt... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "seq_len=4096,k=2048", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 8.06, "optimized": 8.03, "stated_speedup": 1.0, "speedup": 1.0037}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "seq_len=... | 0.7785 | null |
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