Developed by the **CAKE team**, the kernels in this PR **outperform**\nthe relevant **SOTA baselines at the time of merge** on the **vast\nmajority of performance benchmark shapes**, matching them otherwise.\n\n## Cake radix sampling, round 9: leader-push exchange twins of the\nmulti-CTA streams, graph-replay host fix\n\nFollow-up of #5439, #5482, #5585, #5607, #5636, #5684, #5731, #5847 and\n#5950 (the round-8 bundle `0df0c683` as merged in #5950 and re-listed by\nthe lean loader of #5985 is the baseline; this PR's `fi9-base` tree is\nupstream `f2794d5890`).\n\n### What changes\n\n- **Leader-push exchange twins (`_lp`, `_cs_lp`, `_sp_lp`; launch flag\nbit 9, manifest `leader_push`, 18 new stage-1 kernels).** In the\nmulti-CTA streaming variants (cluster 2 / 4 / 8 x ept 16 / 32) every CTA\nstores its compacted candidate list straight into rank 0's shared-memory\nreceive buffer and its list length into every CTA before the single\nexchange barrier; rank 0 gathers locally, resolves the threshold,\ncollects and runs the fused tail, the other CTAs exit. This removes the\npull form's DSM read round and its exit rendezvous (`fused_sync`) -- two\ncluster rounds -- without the N-copy byte amplification of a push-to-all\nexchange. Outputs are bit-identical to the pull form (fused launches:\npositions and bits; two-launch chains: the same exact candidate set\nhanded to stage 2/3, whose samples / counts / renorm are bitwise\nidentical end to end).\n- **Host rule (`_leader_push_flag`).** Bit 9 is taken on compute\ncapability 9.0 / 10.0 / 10.3 / 10.7 (RTX PRO 6000 keeps the round-8\nroutes), for any row on an ept-16 stream and for a row of at most one\nregister chunk per CTA on an ept-32 stream\n(`_LEADER_PUSH_WIDE_MAX_CHUNKS = 1`: the two-to-five-chunk ept-32 rows\nmeasured 1.01-1.31 with the pushes on R200 / B200 / H100), never with\nthe whole-CTA tail (bit 3); where it applies it displaces the slab tail\n(bit 7) and the pushed coarse sums (bit 8). The binding rejects bit 9 on\na resident / single-CTA variant and with bits 3 / 7 / 8; the loader\nvalidates `leader_push` only on multi-CTA stream entries without\n`block_tail` / `slab_tail` / `coarse_push`.\n- **Graph-replay host fix.** Reading the default generator\n(`get_state()`) inside a CUDA-graph capture registers the generator with\nthe graph and adds two `FillFunctor<long>` kernels to every replay\n(+17-19 us on GB300) although both routes take the Philox parameters by\nvalue. Under capture `_philox_params` now uses the generator's initial\nseed and a host-side per-(device, generator) offset counter and never\ntouches the generator; outside capture the generator is read and\nadvanced exactly as before (lockstep with `top_k_first`). Replays stay\nbitwise reproducible per (seed, offset); the k = 1000 graph rows drop to\n0.53-0.83 of round 8 and the k <= 50 graph rows to 0.40-0.85 on all four\nGPUs.\n- The 88 kernels of the round-8 bundle are byte-identical (normalised\nsource identity of the generated bundle; cubin `.text` identity of the\nJIT modules on sm_90a / sm_100a / sm_103a / sm_107a), so every unchanged\nroute keeps its binary.\n- Tests: `tests/utils/test_cake_sampling.py` gains\n`test_leader_push_build_matches_pull_build` (fused: bitwise; chains:\ncandidate-set identity + end-to-end bitwise), the capability / ept /\nchunk-rule pins of the bit-9 policy, and the graph-replay generator test\n(no generator access inside capture, draws reproducible per (seed,\noffset)); the manifest / loader tests cover the new field.\n\n### Speedup (same node / run CUPTI medians, round-8 tree -> round-9\ntree; eager small cells and every k = 1000 eager row re-measured as\nmedians over 10 fresh perturbed processes per tree)\n\n| GPU | k | mode | cells | round-9 / round-8 time (median, min .. max) |\nrows > +0.5 % in both tree orders | speedup vs top_k_first (min .. max)\n|\n|---|---|---|---|---|---|---|\n| B200 | 10 | eager | 32 | 1.000 (0.938 .. 1.010) | 0 | 3.1x .. 9.7x |\n| B200 | 10 | graph | 32 | 0.560 (0.404 .. 0.789) | 0 | 3.9x .. 8.4x |\n| B200 | 50 | eager | 32 | 1.000 (0.955 .. 1.000) | 0 | 3.2x .. 9.6x |\n| B200 | 50 | graph | 32 | 0.562 (0.507 .. 0.792) | 0 | 3.8x .. 7.8x |\n| B200 | 1000 | eager | 32 | 1.000 (0.980 .. 1.028) | 5 | 2.9x .. 7.9x |\n| B200 | 1000 | graph | 32 | 0.651 (0.571 .. 0.825) | 0 | 2.9x .. 7.4x |\n| B200 | all | | 192 | summary: FLAGGED_BOTH_ORDERS 5 (all k = 1000\neager), NOT_FASTER 0 | | |\n| GB300 | 10 | eager | 32 | 1.000 (0.905 .. 1.000) | 0 | 5.3x .. 17.6x |\n| GB300 | 10 | graph | 32 | 0.506 (0.443 .. 0.737) | 0 | 3.9x .. 7.3x |\n| GB300 | 50 | eager | 32 | 1.000 (0.923 .. 1.008) | 0 | 5.0x .. 16.6x |\n| GB300 | 50 | graph | 32 | 0.516 (0.466 .. 0.754) | 0 | 3.8x .. 7.5x |\n| GB300 | 1000 | eager | 32 | 1.006 (0.883 .. 1.087) | 17 | 3.8x .. 7.7x\n|\n| GB300 | 1000 | graph | 32 | 0.606 (0.531 .. 0.787) | 0 | 2.9x .. 8.6x\n|\n| GB300 | all | | 192 | summary: FLAGGED_BOTH_ORDERS 17 (all k = 1000\neager), NOT_FASTER 0 | | |\n| H100 | 10 | eager | 32 | 0.944 (0.819 .. 1.004) | 0 | 2.5x .. 10.9x |\n| H100 | 10 | graph | 32 | 0.512 (0.437 .. 0.846) | 0 | 2.7x .. 7.8x |\n| H100 | 50 | eager | 32 | 0.944 (0.827 .. 1.000) | 0 | 2.5x .. 10.8x |\n| H100 | 50 | graph | 32 | 0.514 (0.447 .. 0.842) | 0 | 2.8x .. 8.1x |\n| H100 | 1000 | eager | 32 | 1.000 (0.970 .. 1.025) | 2 | 2.5x .. 6.7x |\n| H100 | 1000 | graph | 32 | 0.635 (0.559 .. 0.850) | 0 | 2.9x .. 7.1x |\n| H100 | all | | 192 | summary: FLAGGED_BOTH_ORDERS 2 (all k = 1000\neager), NOT_FASTER 0 | | |\n| R200 | 10 | eager | 32 | 1.000 (0.992 .. 1.009) | 0 | 3.3x .. 6.4x |\n| R200 | 10 | graph | 32 | 0.635 (0.561 .. 0.792) | 0 | 3.7x .. 6.3x |\n| R200 | 50 | eager | 32 | 1.000 (0.992 .. 1.010) | 0 | 3.4x .. 6.4x |\n| R200 | 50 | graph | 32 | 0.639 (0.570 .. 0.791) | 0 | 3.2x .. 6.6x |\n| R200 | 1000 | eager | 32 | 0.994 (0.929 .. 1.021) | 2 | 2.4x .. 7.7x |\n| R200 | 1000 | graph | 32 | 0.614 (0.524 .. 0.780) | 0 | 2.7x .. 8.7x |\n| R200 | all | | 192 | summary: FLAGGED_BOTH_ORDERS 2 (all k = 1000\neager), NOT_FASTER 0 | | |\n\nPerturbed-process medians of the served leader-push cells: B200 V128256\nB1-8 k10 0.927-0.949 / k50 0.945-0.973; GB300 V128256 B1-8 k10\n0.946-0.955 / k50 0.956-0.974; H100 cluster-8 cells V128256 / V151936 /\nV262144 B1-8 0.81-0.86 (12.8 / 13.3 / 14.0 -> 10.4 / 11.0 / 11.6 us at\nB1), c2 / c4 e16 chains 0.94-1.00; R200 ept-16 cells 0.84-0.96,\ncluster-8 chains 0.91-0.96. Every flagged row (all k = 1000 eager) is a\nbyte-identical kernel on an unchanged host route or a kernel change that\nthe same-node interleaved A/B contradicts (H100 V151936 B32 `_sp` ->\n`_sp_lp` chain 0.987): the cross-tree per-kernel cold-L2 timeline (fresh\nprocess per tree, alternating, identical address offsets) reads the same\nkernel durations in both trees on every flagged GB300 cell (e.g. the\nfused V151936 B1 k = 1000 kernel 20.4 us in both), and the call launches\nno other GPU work -> **0 confirmed regressions on every GPU; every cell\nfaster than `top_k_first`**. Nodes: B200 nsc-svg gpu-188, GB300 oci-jhb\nnvl72d056-T02, H100 cw-dfw pool0-01616, R200 hecate0356.\n\n### Correctness\n\n- Exactness suite (bitwise vs the pull builds) on B200 / GB300 / H100 /\nR200; FlashInfer tests at this head: 258 passed / 18 skipped per GPU\n(GB300, B200, H100, R200); RTX PRO 6000 (sm_120, this head): 252 passed\n/ 24 skipped (dlcluster 2380558, Docker pytorch:26.07,\n`supported_capability (12, 0)`, route `pipeline` as in rounds 7 / 8 --\nsm_120 semantics unchanged).\n- compute-sanitizer synccheck + memcheck: 0 errors on B200 and R200 for\nthe leader-push form of every multi-CTA stream.\n- sglang GSM8K parity on B200 (Qwen3.5-35B-A3B, n = 1319; k50 p0.9 x2,\nk1000 p0.9): cake 0.7066 / 0.7043 / 0.6869 vs top_k_first 0.7036 /\n0.6854 / 0.6937 vs joint 0.7180 / 0.7172 / 0.6945; greedy-equivalent k =\n1 identical; next-token histograms within the reported support in both\narms.\n\n🤖 Generated with [Claude Code](https://claude.com/claude-code)\n\n---------\n\nCo-authored-by: "},"path":{"kind":"string","value":"csrc/cake_sampling/generated/cake_sampling_kernels.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2026 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n// Generated by Cake for FlashInfer.\n// Bundle: radix top-k -> sparse top-p renormalization -> sampling pipeline\n// (thread-block-cluster radix select with DSM histogram reduction, PDL-chained\n// sorted-prefix top-p and inverse-CDF sampling).\n// Target: compute capability 9.0 and newer\n// (rendered for sm_100a; compiled per device by the FlashInfer JIT); compile flags: none.\n// Generated file; do not edit manually.\n// The kernel bodies are split over the parts below (in this order) to keep every\n// file under the repository size limit; this file is the single translation unit.\n#include \"cake_sampling_kernels_part1.cuh\"\n#include \"cake_sampling_kernels_part2.cuh\"\n#include \"cake_sampling_kernels_part3.cuh\"\n#include \"cake_sampling_kernels_part4.cuh\"\n#include \"cake_sampling_kernels_part5.cuh\"\n#include \"cake_sampling_kernels_part6.cuh\"\n#include \"cake_sampling_kernels_part7.cuh\"\n#include \"cake_sampling_kernels_part8.cuh\"\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2026 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n// Generated by Cake for FlashInfer.\n// Bundle: radix top-k -> sparse top-p renormalization -> sampling pipeline\n// (thread-block-cluster radix select with DSM histogram reduction, PDL-chained\n// sorted-prefix top-p and inverse-CDF sampling).\n// Target: compute capability 9.0 and newer\n// (rendered for sm_100a; compiled per device by the FlashInfer JIT); compile flags: none.\n// Generated file; do not edit manually.\n// The kernel bodies are split over the parts below (in this order) to keep every\n// file under the repository size limit; this file is the single translation unit.\n#include \"cake_sampling_kernels_part1.cuh\"\n#include \"cake_sampling_kernels_part2.cuh\"\n#include \"cake_sampling_kernels_part3.cuh\"\n#include \"cake_sampling_kernels_part4.cuh\"\n#include \"cake_sampling_kernels_part5.cuh\"\n#include \"cake_sampling_kernels_part6.cuh\"\n#include \"cake_sampling_kernels_part7.cuh\"\n#include \"cake_sampling_kernels_part8.cuh\"\n#include \"cake_sampling_kernels_part9.cuh\"\n#include \"cake_sampling_kernels_part10.cuh\"\n"},"diff":{"kind":"string","value":"--- csrc/cake_sampling/generated/cake_sampling_kernels.cu\n+++ csrc/cake_sampling/generated/cake_sampling_kernels.cu\n@@ -30,3 +30,5 @@\n #include \"cake_sampling_kernels_part6.cuh\"\n #include \"cake_sampling_kernels_part7.cuh\"\n #include \"cake_sampling_kernels_part8.cuh\"\n+#include \"cake_sampling_kernels_part9.cuh\"\n+#include \"cake_sampling_kernels_part10.cuh\""},"lines_added":{"kind":"number","value":2,"string":"2"},"lines_removed":{"kind":"number","value":0,"string":"0"},"files_in_commit":{"kind":"number","value":5,"string":"5"},"models_mentioned":{"kind":"list like","value":["qwen"],"string":"[\n \"qwen\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200","GB300","H100","SM100","SM103","SM107","SM120","SM90"],"string":"[\n \"B200\",\n \"GB300\",\n \"H100\",\n \"SM100\",\n \"SM103\",\n \"SM107\",\n \"SM120\",\n \"SM90\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["8 x","3.1x","9.7x","3.9x","8.4x","3.2x","9.6x","3.8x","7.8x","2.9x"],"string":"[\n \"8 x\",\n \"3.1x\",\n \"9.7x\",\n \"3.9x\",\n \"8.4x\",\n \"3.2x\",\n \"9.6x\",\n \"3.8x\",\n \"7.8x\",\n \"2.9x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/cake_sampling/generated/cake_sampling_kernels.cu).\n\nGoal: perf(cake_sampling): round 9 -- leader-push exchange twins of the multi-CTA streams, graph-replay host fix\nTarget hardware: B200, GB300, H100, SM100, SM103, SM107, SM120, SM90\nTarget models: qwen\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2026 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n// Generated by Cake for FlashInfer.\n// Bundle: radix top-k -> sparse top-p renormalization -> sampling pipeline\n// (thread-block-cluster radix select with DSM histogram reduction, PDL-chained\n// sorted-prefix top-p and inverse-CDF sampling).\n// Target: compute capability 9.0 and newer\n// (rendered for sm_100a; compiled per device by the FlashInfer JIT); compile flags: none.\n// Generated file; do not edit manually.\n// The kernel bodies are split over the parts below (in this order) to keep every\n// file under the repository size limit; this file is the single translation unit.\n#include \"cake_sampling_kernels_part1.cuh\"\n#include \"cake_sampling_kernels_part2.cuh\"\n#include \"cake_sampling_kernels_part3.cuh\"\n#include \"cake_sampling_kernels_part4.cuh\"\n#include \"cake_sampling_kernels_part5.cuh\"\n#include \"cake_sampling_kernels_part6.cuh\"\n#include \"cake_sampling_kernels_part7.cuh\"\n#include \"cake_sampling_kernels_part8.cuh\"\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"> Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.\n\n## Cake radix sampling, round 9: leader-push exchange twins of the multi-CTA streams, graph-replay host fix\n\nFollow-up of #5439, #5482, #5585, #5607, #5636, #5684, #5731, #5847 and #5950 (the round-8 bundle `0df0c683` as merged in #5950 and re-listed by the lean loader of #5985 is the baseline; this PR's `fi9-base` tree is upstream `f2794d5890`).\n\n### What changes\n\n- **Leader-push exchange twins (`_lp`, `_cs_lp`, `_sp_lp`; launch flag bit 9, manifest `leader_push`, 18 new stage-1 kernels).** In the multi-CTA streaming variants (cluster 2 / 4 / 8 x ept 16 / 32) every CTA stores its compacted candidate list straight into rank 0's shared-memory receive buffer and its list length into every CTA before the single exchange barrier; rank 0 gathers locally, resolves the threshold, collects and runs the fused tail, the other CTAs exit. This removes the pull form's DSM read round and its exit rendezvous (`fused_sync`) -- two cluster rounds -- without the N-copy byte amplification of a push-to-all exchange. Outputs are bit-identical to the pull form (fused launches: positions and bits; two-launch chains: the same exact candidate set handed to stage 2/3, whose samples / counts / renorm are bitwise identical end to end).\n- **Host rule (`_leader_push_flag`).** Bit 9 is taken on compute capability 9.0 / 10.0 / 10.3 / 10.7 (RTX PRO 6000 keeps the round-8 routes), for any row on an ept-16 stream and for a row of at most one register chunk per CTA on an ept-32 stream (`_LEADER_PUSH_WIDE_MAX_CHUNKS = 1`: the two-to-five-chunk ept-32 rows measured 1.01-1.31 with the pushes on R200 / B200 / H100), never with the whole-CTA tail (bit 3); where it applies it displaces the slab tail (bit 7) and the pushed coarse sums (bit 8). The binding rejects bit 9 on a resident / single-CTA variant and with bits 3 / 7 / 8; the loader validates `leader_push` only on multi-CTA stream entries without `block_tail` / `slab_tail` / `coarse_push`.\n- **Graph-replay host fix.** Reading the default generator (`get_state()`) inside a CUDA-graph capture registers the generator with the graph and adds two `FillFunctor<long>` kernels to every replay (+17-19 us on GB300) although both routes take the Philox parameters by value. Under capture `_philox_params` now uses the generator's initial seed and a host-side per-(device, generator) offset counter and never touches the generator; outside capture the generator is read and advanced exactly as before (lockstep with `top_k_first`). Replays stay bitwise reproducible per (seed, offset); the k = 1000 graph rows drop to 0.53-0.83 of round 8 and the k <= 50 graph rows to 0.40-0.85 on all four GPUs.\n- The 88 kernels of the round-8 bundle are byte-identical (normalised source identity of the generated bundle; cubin `.text` identity of the JIT modules on sm_90a / sm_100a / sm_103a / sm_107a), so every unchanged route keeps its binary.\n- Tests: `tests/utils/test_cake_sampling.py` gains `test_leader_push_build_matches_pull_build` (fused: bitwise; chains: candidate-set identity + end-to-end bitwise), the capability / ept / chunk-rule pins of the bit-9 policy, and the graph-replay generator test (no generator access inside capture, draws reproducible per (seed, offset)); the manifest / loader tests cover the new field.\n\n### Speedup (same node / run CUPTI medians, round-8 tree -> round-9 tree; eager small cells and every k = 1000 eager row re-measured as medians over 10 fresh perturbed processes per tree)\n\n| GPU | k | mode | cells | round-9 / round-8 time (median, min .. max) | rows > +0.5 % in both tree orders | speedup vs top_k_first (min .. max) |\n|---|---|---|---|---|---|---|\n| B200 | 10 | eager | 32 | 1.000 (0.938 .. 1.010) | 0 | 3.1x .. 9.7x |\n| B200 | 10 | graph | 32 | 0.560 (0.404 .. 0.789) | 0 | 3.9x .. 8.4x |\n| B200 | 50 | eager | 32 | 1.000 (0.955 .. 1.000) | 0 | 3.2x .. 9.6x |\n| B200 | 50 | graph | 32 | 0.562 (0.507 .. 0.792) | 0 | 3.8x .. 7.8x |\n| B200 | 1000 | eager | 32 | 1.000 (0.980 .. 1.028) | 5 | 2.9x .. 7.9x |\n| B200 | 1000 | graph | 32 | 0.651 (0.571 .. 0.825) | 0 | 2.9x .. 7.4x |\n| B200 | all | | 192 | summary: FLAGGED_BOTH_ORDERS 5 (all k = 1000 eager), NOT_FASTER 0 | | |\n| GB300 | 10 | eager | 32 | 1.000 (0.905 .. 1.000) | 0 | 5.3x .. 17.6x |\n| GB300 | 10 | graph | 32 | 0.506 (0.443 .. 0.737) | 0 | 3.9x .. 7.3x |\n| GB300 | 50 | eager | 32 | 1.000 (0.923 .. 1.008) | 0 | 5.0x .. 16.6x |\n| GB300 | 50 | graph | 32 | 0.516 (0.466 .. 0.754) | 0 | 3.8x .. 7.5x |\n| GB300 | 1000 | eager | 32 | 1.006 (0.883 .. 1.087) | 17 | 3.8x .. 7.7x |\n| GB300 | 1000 | graph | 32 | 0.606 (0.531 .. 0.787) | 0 | 2.9x .. 8.6x |\n| GB300 | all | | 192 | summary: FLAGGED_BOTH_ORDERS 17 (all k = 1000 eager), NOT_FASTER 0 | | |\n| H100 | 10 | eager | 32 | 0.944 (0.819 .. 1.004) | 0 | 2.5x .. 10.9x |\n| H100 | 10 | graph | 32 | 0.512 (0.437 .. 0.846) | 0 | 2.7x .. 7.8x |\n| H100 | 50 | eager | 32 | 0.944 (0.827 .. 1.000) | 0 | 2.5x .. 10.8x |\n| H100 | 50 | graph | 32 | 0.514 (0.447 .. 0.842) | 0 | 2.8x .. 8.1x |\n| H100 | 1000 | eager | 32 | 1.000 (0.970 .. 1.025) | 2 | 2.5x .. 6.7x |\n| H100 | 1000 | graph | 32 | 0.635 (0.559 .. 0.850) | 0 | 2.9x .. 7.1x |\n| H100 | all | | 192 | summary: FLAGGED_BOTH_ORDERS 2 (all k = 1000 eager), NOT_FASTER 0 | | |\n| R200 | 10 | eager | 32 | 1.000 (0.992 .. 1.009) | 0 | 3.3x .. 6.4x |\n| R200 | 10 | graph | 32 | 0.635 (0.561 .. 0.792) | 0 | 3.7x .. 6.3x |\n| R200 | 50 | eager | 32 | 1.000 (0.992 .. 1.010) | 0 | 3.4x .. 6.4x |\n| R200 | 50 | graph | 32 | 0.639 (0.570 .. 0.791) | 0 | 3.2x .. 6.6x |\n| R200 | 1000 | eager | 32 | 0.994 (0.929 .. 1.021) | 2 | 2.4x .. 7.7x |\n| R200 | 1000 | graph | 32 | 0.614 (0.524 .. 0.780) | 0 | 2.7x .. 8.7x |\n| R200 | all | | 192 | summary: FLAGGED_BOTH_ORDERS 2 (all k = 1000 eager), NOT_FASTER 0 | | |\n\nPerturbed-process medians of the served leader-push cells: B200 V128256 B1-8 k10 0.927-0.949 / k50 0.945-0.973; GB300 V128256 B1-8 k10 0.946-0.955 / k50 0.956-0.974; H100 cluster-8 cells V128256 / V151936 / V262144 B1-8 0.81-0.86 (12.8 / 13.3 / 14.0 -> 10.4 / 11.0 / 11.6 us at B1), c2 / c4 e16 chains 0.94-1.00; R200 ept-16 cells 0.84-0.96, cluster-8 chains 0.91-0.96. Every flagged row (all k = 1000 eager) is a byte-identical kernel on an unchanged host route or a kernel change that the same-node interleaved A/B contradicts (H100 V151936 B32 `_sp` -> `_sp_lp` chain 0.987): the cross-tree per-kernel cold-L2 timeline (fresh process per tree, alternating, identical address offsets) reads the same kernel durations in both trees on every flagged GB300 cell (e.g. the fused V151936 B1 k = 1000 kernel 20.4 us in both), and the call launches no other GPU work -> **0 confirmed regressions on every GPU; every cell faster than `top_k_first`**. Nodes: B200 nsc-svg gpu-188, GB300 oci-jhb nvl72d056-T02, H100 cw-dfw pool0-01616, R200 hecate0356.\n\n### Per-shape timings (us, CUPTI `max(end)-min(start)` of the call's kernels, cold L2; every cell is the `pipeline` route; order 1 = round-8 tree first, order 2 = round-9 tree first; `top_k_first` from the same run)\n\n<details><summary>B200: 192 cells</summary>\n\n\n**k = 10, eager**\n\n|V|B|top_k_first|round 8|round 9|r9/r8 order 1 / 2|speedup|\n|-|-|-|-|-|-|-|\n|32768|1|41.1|9.80|9.80|1.000 / 1.000|4.20x|\n|32768|2|43.2|9.60|9.70|1.010 / 1.000|4.47x|\n|32768|4|45.0|9.70|9.70|1.000 / 1.000|4.66x|\n|32768|8|45.5|9.70|9.70|1.000 / 1.000|4.69x|\n|32768|16|49.0|9.90|9.90|1.000 / 1.000|4.97x|\n|32768|32|51.1|10.20|10.20|1.000 / 1.000|5.01x|\n|32768|64|52.7|10.70|10.70|1.000 / 1.000|4.94x|\n|32768|128|53.6|11.90|11.90|1.000 / 1.000|4.52x|\n|128256|1|101.4|11.00|10.50|0.955 / 0.955|9.63x|\n|128256|2|102.1|11.30|10.60|0.938 / 0.946|9.67x|\n|128256|4|102.2|11.40|10.70|0.939 / 0.939|9.54x|\n|128256|8|102.3|11.70|11.10|0.949 / 0.949|9.21x|\n|128256|16|102.3|12.80|12.80|1.000 / 1.000|7.97x|\n|128256|32|105.8|14.30|14.30|1.000 / 1.000|7.38x|\n|128256|64|106.0|17.00|17.00|1.000 / 1.000|6.25x|\n|128256|128|106.4|22.30|22.30|1.000 / 1.000|4.78x|\n|151936|1|103.2|12.50|12.50|1.000 / 0.992|8.27x|\n|151936|2|103.3|12.70|12.70|1.000 / 1.000|8.13x|\n|151936|4|103.6|12.70|12.70|1.000 / 1.000|8.15x|\n|151936|8|106.2|13.10|13.10|1.000 / 1.000|8.09x|\n|151936|16|105.2|14.20|14.20|1.000 / 1.000|7.41x|\n|151936|32|105.3|15.70|15.70|1.000 / 1.000|6.71x|\n|151936|64|109.2|19.00|19.00|1.000 / 1.000|5.75x|\n|151936|128|109.7|25.40|25.40|1.000 / 1.000|4.32x|\n|262144|1|104.5|12.30|12.20|0.992 / 1.000|8.55x|\n|262144|2|106.7|12.50|12.50|1.000 / 1.000|8.55x|\n|262144|4|105.7|13.00|13.00|1.000 / 1.000|8.16x|\n|262144|8|105.5|13.60|13.60|1.000 / 1.000|7.78x|\n|262144|16|106.1|15.60|15.50|0.994 / 0.994|6.84x|\n|262144|32|113.5|18.00|18.00|1.000 / 1.000|6.29x|\n|262144|64|110.5|24.70|24.70|1.000 / 1.000|4.47x|\n|262144|128|124.2|39.70|39.70|1.000 / 1.000|3.13x|\n\n**k = 10, graph**\n\n|V|B|top_k_first|round 8|round 9|r9/r8 order 1 / 2|speedup|\n|-|-|-|-|-|-|-|\n|32768|1|42.4|19.10|9.80|0.513 / 0.513|4.34x|\n|32768|2|46.6|19.30|9.70|0.503 / 0.497|4.82x|\n|32768|4|53.0|19.10|9.60|0.503 / 0.505|5.52x|\n|32768|8|55.1|19.50|9.80|0.503 / 0.500|5.64x|\n|32768|16|50.0|19.30|10.00|0.518 / 0.516|5.03x|\n|32768|32|56.0|19.60|10.40|0.531 / 0.531|5.40x|\n|32768|64|57.9|20.80|10.90|0.524 / 0.524|5.32x|\n|32768|128|57.5|21.50|12.10|0.563 / 0.561|4.76x|\n|128256|1|89.6|21.20|10.70|0.505 / 0.507|8.39x|\n|128256|2|88.8|26.70|10.80|0.404 / 0.507|8.24x|\n|128256|4|86.7|22.10|11.00|0.498 / 0.500|7.90x|\n|128256|8|85.9|22.10|11.30|0.511 / 0.514|7.61x|\n|128256|16|87.2|23.00|13.10|0.570 / 0.572|6.65x|\n|128256|32|90.2|24.80|14.70|0.593 / 0.598|6.16x|\n|128256|64|94.5|27.60|17.20|0.623 / 0.629|5.48x|\n|128256|128|99.8|32.50|22.50|0.692 / 0.694|4.43x|\n|151936|1|91.1|22.70|12.70|0.559 / 0.559|7.19x|\n|151936|2|90.8|22.80|12.80|0.561 / 0.561|7.11x|\n|151936|4|89.5|23.20|12.90|0.556 / 0.561|6.93x|\n|151936|8|95.8|23.60|13.40|0.568 / 0.570|7.17x|\n|151936|16|92.7|24.80|14.50|0.585 / 0.587|6.40x|\n|151936|32|94.5|26.50|15.90|0.600 / 0.600|5.93x|\n|151936|64|99.0|30.10|19.30|0.641 / 0.643|5.14x|\n|151936|128|108.6|35.90|25.60|0.713 / 0.717|4.24x|\n|262144|1|97.4|22.90|12.40|0.541 / 0.544|7.82x|\n|262144|2|97.4|23.40|12.70|0.543 / 0.550|7.65x|\n|262144|4|95.6|23.90|13.30|0.556 / 0.561|7.18x|\n|262144|8|98.4|24.60|13.90|0.565 / 0.570|7.07x|\n|262144|16|100.1|26.60|15.80|0.594 / 0.598|6.35x|\n|262144|32|140.5|28.90|18.30|0.633 / 0.635|7.69x|\n|262144|64|130.7|36.10|25.00|0.693 / 0.696|5.22x|\n|262144|128|150.3|50.10|39.00|0.778 / 0.789|3.85x|\n\n**k = 50, eager**\n\n|V|B|top_k_first|round 8|round 9|r9/r8 order 1 / 2|speedup|\n|-|-|-|-|-|-|-|\n|32768|1|43.0|10.10|10.10|1.000 / 1.000|4.25x|\n|32768|2|44.3|10.00|10.00|1.000 / 1.000|4.42x|\n|32768|4|45.3|10.00|10.00|1.000 / 1.000|4.51x|\n|32768|8|47.2|10.10|10.10|1.000 / 1.000|4.67x|\n|32768|16|50.1|10.20|10.20|1.000 / 1.000|4.93x|\n|32768|32|51.5|10.50|10.50|1.000 / 1.000|4.92x|\n|32768|64|53.2|10.90|10.90|1.000 / 1.000|4.86x|\n|32768|128|54.2|12.10|12.10|1.000 / 1.000|4.50x|\n|128256|1|101.9|10.90|10.60|0.972 / 0.972|9.62x|\n|128256|2|102.7|11.20|10.70|0.955 / 0.955|9.61x|\n|128256|4|102.3|11.40|11.00|0.965 / 0.965|9.29x|\n|128256|8|103.1|11.70|11.30|0.966 / 0.966|9.15x|\n|128256|16|102.3|13.20|13.20|1.000 / 1.000|7.76x|\n|128256|32|106.3|14.50|14.50|1.000 / 1.000|7.35x|\n|128256|64|106.4|17.20|17.20|1.000 / 1.000|6.18x|\n|128256|128|107.3|22.80|22.80|1.000 / 1.000|4.71x|\n|151936|1|103.8|12.20|12.20|1.000 / 1.000|8.51x|\n|151936|2|103.7|12.50|12.50|1.000 / 1.000|8.31x|\n|151936|4|103.5|12.60|12.60|1.000 / 1.000|8.19x|\n|151936|8|105.1|13.10|13.10|1.000 / 1.000|8.05x|\n|151936|16|104.9|14.60|14.60|1.000 / 1.000|7.20x|\n|151936|32|104.9|16.10|16.10|1.000 / 1.000|6.53x|\n|151936|64|107.7|19.40|19.40|1.000 / 1.000|5.55x|\n|151936|128|108.0|25.80|25.80|1.000 / 1.000|4.18x|\n|262144|1|104.2|12.30|12.30|1.000 / 1.000|8.50x|\n|262144|2|105.0|12.50|12.50|1.000 / 1.000|8.39x|\n|262144|4|104.5|13.00|13.00|1.000 / 1.000|8.04x|\n|262144|8|105.7|13.60|13.60|1.000 / 1.000|7.79x|\n|262144|16|105.9|15.60|15.60|1.000 / 1.000|6.77x|\n|262144|32|115.5|18.10|18.10|1.000 / 1.000|6.37x|\n|262144|64|109.3|24.90|24.90|1.000 / 1.000|4.40x|\n|262144|128|125.6|39.80|39.80|1.000 / 1.000|3.16x|\n\n**k = 50, graph**\n\n|V|B|top_k_first|round 8|round 9|r9/r8 order 1 / 2|speedup|\n|-|-|-|-|-|-|-|\n|32768|1|40.1|19.60|10.20|0.520 / 0.531|3.94x|\n|32768|2|45.5|19.70|10.10|0.513 / 0.515|4.51x|\n|32768|4|60.4|19.60|10.00|0.510 / 0.518|6.01x|\n|32768|8|45.5|19.90|10.10|0.508 / 0.520|4.48x|\n|32768|16|48.9|19.70|10.30|0.523 / 0.523|4.75x|\n|32768|32|52.9|20.00|10.60|0.530 / 0.535|4.99x|\n|32768|64|53.7|21.10|11.10|0.526 / 0.529|4.83x|\n|32768|128|60.0|21.70|12.30|0.567 / 0.572|4.90x|\n|128256|1|83.6|21.10|10.70|0.507 / 0.512|7.80x|\n|128256|2|82.6|21.50|11.00|0.512 / 0.519|7.53x|\n|128256|4|81.8|22.00|11.40|0.518 / 0.521|7.20x|\n|128256|8|82.3|22.00|11.50|0.523 / 0.530|7.14x|\n|128256|16|81.9|23.40|13.40|0.573 / 0.580|6.10x|\n|128256|32|84.3|24.90|14.80|0.594 / 0.599|5.72x|\n|128256|64|86.1|27.80|17.40|0.626 / 0.636|4.94x|\n|128256|128|94.6|32.90|23.00|0.699 / 0.703|4.11x|\n|151936|1|84.9|22.50|12.40|0.551 / 0.556|6.86x|\n|151936|2|89.7|22.70|12.60|0.555 / 0.555|7.09x|\n|151936|4|85.9|23.00|13.00|0.565 / 0.565|6.61x|\n|151936|8|86.6|23.60|13.40|0.568 / 0.573|6.48x|\n|151936|16|91.0|25.10|14.80|0.590 / 0.594|6.14x|\n|151936|32|93.2|26.90|16.30|0.606 / 0.614|5.71x|\n|151936|64|93.4|30.50|19.60|0.643 / 0.647|4.76x|\n|151936|128|103.7|36.20|26.00|0.718 / 0.724|3.99x|\n|262144|1|89.6|22.90|12.40|0.541 / 0.549|7.20x|\n|262144|2|90.0|23.10|12.70|0.550 / 0.552|7.06x|\n|262144|4|90.3|23.90|13.30|0.556 / 0.564|6.77x|\n|262144|8|91.1|24.50|14.00|0.571 / 0.576|6.53x|\n|262144|16|93.7|26.60|15.90|0.598 / 0.605|5.89x|\n|262144|32|133.3|29.00|18.40|0.634 / 0.641|7.24x|\n|262144|64|124.6|36.10|25.10|0.695 / 0.699|4.96x|\n|262144|128|147.7|49.80|39.20|0.787 / 0.792|3.77x|\n\n**k = 1000, eager**\n\n|V|B|top_k_first|round 8|round 9|r9/r8 order 1 / 2|speedup|\n|-|-|-|-|-|-|-|\n|32768|1|42.6|14.30|14.30|1.000 / 1.000|2.99x|\n|32768|2|43.7|14.20|14.20|1.000 / 1.000|3.08x|\n|32768|4|44.9|14.60|14.60|1.000 / 1.000|3.09x|\n|32768|8|46.2|14.70|14.70|1.000 / 1.000|3.14x|\n|32768|16|49.9|14.90|14.90|1.000 / 0.993|3.35x|\n|32768|32|51.8|15.80|15.80|1.000 / 1.000|3.29x|\n|32768|64|52.8|17.00|17.20|1.012 / 1.012|3.08x|\n|32768|128|54.0|18.50|18.50|1.000 / 1.000|2.92x|\n|128256|1|66.2|17.10|17.10|1.000 / 1.000|3.87x|\n|128256|2|71.7|17.10|17.10|1.000 / 1.000|4.20x|\n|128256|4|75.6|17.60|17.60|1.000 / 1.000|4.29x|\n|128256|8|81.4|18.10|18.10|1.000 / 1.000|4.49x|\n|128256|16|92.5|20.10|19.90|0.990 / 0.980|4.64x|\n|128256|32|99.9|21.30|21.20|0.995 / 0.991|4.71x|\n|128256|64|144.2|29.20|29.20|1.000 / 1.000|4.94x|\n|128256|128|193.5|36.20|35.90|0.992 / 0.992|5.38x|\n|151936|1|73.5|18.60|18.60|1.000 / 1.000|3.96x|\n|151936|2|80.7|18.60|18.60|1.000 / 1.000|4.34x|\n|151936|4|85.9|19.00|19.30|1.016 / 1.016|4.44x|\n|151936|8|92.0|19.50|19.50|1.000 / 1.000|4.71x|\n|151936|16|103.8|21.30|21.20|0.995 / 0.995|4.90x|\n|151936|32|114.0|22.50|22.30|0.991 / 0.987|5.12x|\n|151936|64|164.3|28.10|28.10|1.000 / 1.000|5.85x|\n|151936|128|223.2|42.80|43.40|1.014 / 1.014|5.15x|\n|262144|1|92.7|20.50|20.30|0.990 / 0.990|4.58x|\n|262144|2|102.6|20.00|20.00|1.000 / 1.000|5.14x|\n|262144|4|112.1|20.70|20.70|1.000 / 1.000|5.42x|\n|262144|8|122.9|21.20|21.30|1.005 / 1.005|5.77x|\n|262144|16|144.5|23.20|23.20|1.000 / 1.000|6.23x|\n|262144|32|199.5|25.30|25.40|1.004 / 1.004|7.86x|\n|262144|64|263.4|34.20|34.40|1.006 / 1.009|7.65x|\n|262144|128|376.9|50.50|51.80|1.026 / 1.028|7.27x|\n\n**k = 1000, graph**\n\n|V|B|top_k_first|round 8|round 9|r9/r8 order 1 / 2|speedup|\n|-|-|-|-|-|-|-|\n|32768|1|42.9|25.20|14.70|0.583 / 0.586|2.92x|\n|32768|2|45.8|26.00|14.90|0.573 / 0.573|3.06x|\n|32768|4|47.4|25.30|14.80|0.585 / 0.583|3.19x|\n|32768|8|47.5|25.80|14.80|0.574 / 0.571|3.21x|\n|32768|16|50.6|26.30|15.40|0.586 / 0.586|3.28x|\n|32768|32|60.6|27.40|16.60|0.606 / 0.610|3.66x|\n|32768|64|55.4|28.70|18.10|0.631 / 0.633|3.06x|\n|32768|128|57.3|30.70|19.60|0.638 / 0.641|2.93x|\n|128256|1|74.6|28.40|17.60|0.620 / 0.620|4.25x|\n|128256|2|80.7|29.20|17.90|0.613 / 0.615|4.51x|\n|128256|4|86.6|28.80|18.00|0.625 / 0.625|4.81x|\n|128256|8|92.8|29.40|18.10|0.616 / 0.618|5.12x|\n|128256|16|92.4|31.50|20.40|0.648 / 0.646|4.52x|\n|128256|32|114.2|33.20|22.40|0.675 / 0.677|5.10x|\n|128256|64|146.0|41.60|30.60|0.736 / 0.736|4.77x|\n|128256|128|214.8|47.60|36.50|0.767 / 0.767|5.88x|\n|151936|1|105.9|29.40|18.80|0.639 / 0.639|5.63x|\n|151936|2|108.8|28.90|18.90|0.654 / 0.654|5.76x|\n|151936|4|96.6|29.50|19.40|0.658 / 0.660|4.97x|\n|151936|8|105.2|30.50|20.00|0.656 / 0.660|5.26x|\n|151936|16|103.8|33.50|21.70|0.648 / 0.650|4.78x|\n|151936|32|106.6|34.70|23.10|0.666 / 0.666|4.62x|\n|151936|64|169.5|41.20|29.10|0.706 / 0.706|5.83x|\n|151936|128|223.1|56.60|44.20|0.781 / 0.782|5.05x|\n|262144|1|98.6|30.90|20.40|0.660 / 0.660|4.82x|\n|262144|2|113.0|31.50|20.40|0.648 / 0.650|5.53x|\n|262144|4|144.7|31.80|21.00|0.660 / 0.662|6.90x|\n|262144|8|136.9|32.00|21.40|0.669 / 0.673|6.39x|\n|262144|16|135.2|35.40|23.80|0.672 / 0.665|5.69x|\n|262144|32|180.5|38.30|26.20|0.684 / 0.684|6.88x|\n|262144|64|255.4|46.80|35.10|0.750 / 0.750|7.27x|\n|262144|128|381.6|62.60|51.50|0.823 / 0.825|7.41x|\n\n</details>\n\n<details><summary>GB300: 192 cells</summary>\n\n\n**k = 10, eager**\n\n|V|B|top_k_first|round 8|round 9|r9/r8 order 1 / 2|speedup|\n|-|-|-|-|-|-|-|\n|32768|1|72.9|9.70|9.70|1.000 / 1.000|7.52x|\n|32768|2|74.4|9.70|9.70|1.000 / 1.000|7.70x|\n|32768|4|74.4|9.60|9.60|1.000 / 1.000|7.75x|\n|32768|8|77.0|9.60|9.60|1.000 / 1.000|7.99x|\n|32768|16|76.8|10.00|10.00|1.000 / 1.000|7.72x|\n|32768|32|77.4|10.30|10.30|1.000 / 1.000|7.51x|\n|32768|64|79.9|10.80|10.80|1.000 / 1.000|7.37x|\n|32768|128|81.5|11.70|11.70|1.000 / 1.000|6.96x|\n|128256|1|181.9|11.60|10.50|0.905 / 0.905|17.39x|\n|128256|2|180.3|11.50|10.60|0.922 / 0.922|17.07x|\n|128256|4|187.6|11.80|10.70|0.907 / 0.915|17.55x|\n|128256|8|187.9|12.20|11.20|0.918 / 0.926|16.83x|\n|128256|16|188.0|13.20|13.20|1.000 / 1.000|14.26x|\n|128256|32|188.0|14.40|14.40|1.000 / 1.000|13.06x|\n|128256|64|189.0|16.90|16.90|1.000 / 1.000|11.19x|\n|128256|128|178.7|22.00|22.00|1.000 / 1.000|8.13x|\n|151936|1|190.0|12.90|12.40|0.961 / 0.961|15.30x|\n|151936|2|188.2|12.80|12.40|0.969 / 0.969|15.16x|\n|151936|4|185.3|13.10|12.70|0.969 / 0.969|14.59x|\n|151936|8|186.0|13.50|13.10|0.970 / 0.970|14.18x|\n|151936|16|185.0|14.30|14.30|1.000 / 1.000|12.91x|\n|151936|32|184.7|15.60|15.60|1.000 / 1.000|11.85x|\n|151936|64|196.4|18.90|18.90|1.000 / 1.000|10.37x|\n|151936|128|188.7|25.50|25.50|1.000 / 1.000|7.40x|\n|262144|1|195.4|13.00|12.60|0.969 / 0.969|15.53x|\n|262144|2|190.9|13.10|12.60|0.962 / 0.969|15.14x|\n|262144|4|188.7|13.40|13.00|0.970 / 0.970|14.49x|\n|262144|8|205.8|14.30|13.90|0.972 / 0.979|14.82x|\n|262144|16|188.8|15.50|15.50|1.000 / 1.000|12.19x|\n|262144|32|179.2|17.80|17.80|1.000 / 1.000|10.07x|\n|262144|64|199.2|25.10|25.10|1.000 / 1.000|7.94x|\n|262144|128|191.1|36.30|36.30|1.000 / 1.000|5.27x|\n\n**k = 10, graph**\n\n|V|B|top_k_first|round 8|round 9|r9/r8 order 1 / 2|speedup|\n|-|-|-|-|-|-|-|\n|32768|1|44.2|21.30|9.90|0.465 / 0.448|4.47x|\n|32768|2|44.6|21.10|9.80|0.464 / 0.471|4.54x|\n|32768|4|46.3|21.00|9.80|0.467 / 0.443|4.73x|\n|32768|8|45.4|20.60|9.80|0.476 / 0.471|4.62x|\n|32768|16|52.7|21.20|10.00|0.472 / 0.461|5.26x|\n|32768|32|51.2|22.40|10.40|0.464 / 0.475|4.91x|\n|32768|64|53.2|22.10|11.10|0.502 / 0.491|4.79x|\n|32768|128|56.8|23.10|12.00|0.519 / 0.494|4.75x|\n|128256|1|77.5|24.00|10.80|0.450 / 0.444|7.17x|\n|128256|2|78.1|23.60|10.90|0.462 / 0.450|7.16x|\n|128256|4|76.9|23.60|11.10|0.470 / 0.462|6.95x|\n|128256|8|78.7|24.10|11.40|0.473 / 0.467|6.89x|\n|128256|16|77.6|25.80|13.50|0.523 / 0.519|5.76x|\n|128256|32|85.5|27.10|14.70|0.542 / 0.542|5.81x|\n|128256|64|88.0|29.50|17.10|0.580 / 0.592|5.14x|\n|128256|128|93.4|33.90|22.20|0.655 / 0.642|4.21x|\n|151936|1|82.4|25.00|12.80|0.512 / 0.529|6.44x|\n|151936|2|82.7|25.00|12.70|0.508 / 0.498|6.51x|\n|151936|4|84.8|25.00|12.90|0.516 / 0.492|6.58x|\n|151936|8|86.0|25.20|13.40|0.532 / 0.517|6.43x|\n|151936|16|86.0|27.10|14.60|0.539 / 0.525|5.88x|\n|151936|32|88.4|28.40|15.80|0.556 / 0.554|5.58x|\n|151936|64|92.4|31.60|19.20|0.608 / 0.604|4.81x|\n|151936|128|102.5|38.70|25.70|0.664 / 0.675|3.99x|\n|262144|1|82.5|25.50|12.90|0.506 / 0.504|6.40x|\n|262144|2|83.1|25.60|12.90|0.504 / 0.500|6.43x|\n|262144|4|84.1|26.30|13.20|0.502 / 0.500|6.35x|\n|262144|8|86.2|27.50|14.10|0.513 / 0.528|6.11x|\n|262144|16|89.6|28.60|15.70|0.549 / 0.559|5.70x|\n|262144|32|131.7|30.80|18.10|0.588 / 0.592|7.28x|\n|262144|64|120.7|38.80|25.30|0.652 / 0.676|4.76x|\n|262144|128|141.8|50.10|36.90|0.737 / 0.736|3.85x|\n\n**k = 50, eager**\n\n|V|B|top_k_first|round 8|round 9|r9/r8 order 1 / 2|speedup|\n|-|-|-|-|-|-|-|\n|32768|1|68.5|10.20|10.20|1.000 / 1.000|6.71x|\n|32768|2|68.0|10.10|10.10|1.000 / 1.000|6.73x|\n|32768|4|69.3|10.10|10.10|1.000 / 1.000|6.85x|\n|32768|8|73.0|10.20|10.20|1.000 / 1.000|7.18x|\n|32768|16|73.7|10.30|10.30|1.000 / 1.000|7.17x|\n|32768|32|76.4|10.50|10.50|1.000 / 1.000|7.26x|\n|32768|64|74.5|11.10|11.10|1.000 / 1.000|6.69x|\n|32768|128|77.9|12.20|12.10|0.992 / 1.000|6.42x|\n|128256|1|173.0|11.50|10.70|0.930 / 0.930|16.24x|\n|128256|2|179.3|11.70|10.80|0.923 / 0.923|16.58x|\n|128256|4|179.9|11.60|11.10|0.957 / 0.957|16.25x|\n|128256|8|181.5|12.00|11.30|0.942 / 0.942|16.03x|\n|128256|16|179.0|13.30|13.40|1.008 / 1.000|13.38x|\n|128256|32|182.8|14.50|14.50|1.000 / 1.000|12.58x|\n|128256|64|183.6|17.10|17.10|1.000 / 1.000|10.75x|\n|128256|128|185.6|22.50|22.50|1.000 / 1.000|8.24x|\n|151936|1|181.1|12.70|12.20|0.961 / 0.968|14.81x|\n|151936|2|179.0|12.80|12.50|0.977 / 0.977|14.31x|\n|151936|4|182.8|12.90|12.70|0.984 / 0.984|14.43x|\n|151936|8|182.8|13.20|13.00|0.985 / 0.985|14.04x|\n|151936|16|179.6|14.50|14.50|1.000 / 1.000|12.36x|\n|151936|32|183.5|15.80|15.80|1.000 / 1.000|11.61x|\n|151936|64|182.1|19.30|19.30|1.000 / 1.005|9.45x|\n|151936|128|187.0|25.80|25.80|1.000 / 1.000|7.24x|\n|262144|1|180.2|12.90|12.40|0.961 / 0.961|14.51x|\n|262144|2|180.7|13.10|12.70|0.969 / 0.969|14.23x|\n|262144|4|180.2|13.10|12.90|0.985 / 0.985|13.97x|\n|262144|8|178.9|13.90|13.80|0.993 / 0.993|13.00x|\n|262144|16|180.3|15.50|15.50|1.000 / 1.000|11.62x|\n|262144|32|180.1|17.80|17.80|1.000 / 1.000|10.12x|\n|262144|64|183.7|25.20|25.20|1.000 / 1.000|7.29x|\n|262144|128|183.0|36.40|36.40|1.000 / 1.000|5.03x|\n\n**k = 50, graph**\n\n|V|B|top_k_first|round 8|round 9|r9/r8 order 1 / 2|speedup|\n|-|-|-|-|-|-|-|\n|32768|1|41.4|21.40|10.20|0.477 / 0.466|4.06x|\n|32768|2|44.5|20.80|10.10|0.486 / 0.488|4.40x|\n|32768|4|61.5|21.00|10.10|0.481 / 0.486|6.08x|\n|32768|8|52.9|20.90|10.20|0.488 / 0.493|5.20x|\n|32768|16|48.5|21.20|10.30|0.486 / 0.495|4.69x|\n|32768|32|53.0|21.70|10.70|0.493 / 0.495|4.97x|\n|32768|64|57.0|22.20|11.30|0.509 / 0.509|5.03x|\n|32768|128|54.2|23.50|12.40|0.528 / 0.532|4.38x|\n|128256|1|76.0|22.80|10.80|0.474 / 0.474|7.03x|\n|128256|2|80.2|23.40|11.10|0.474 / 0.474|7.24x|\n|128256|4|83.3|23.10|11.40|0.494 / 0.498|7.31x|\n|128256|8|87.6|23.60|11.60|0.492 / 0.483|7.54x|\n|128256|16|84.4|25.20|13.60|0.540 / 0.542|6.20x|\n|128256|32|85.2|26.30|14.80|0.563 / 0.563|5.75x|\n|128256|64|84.6|29.00|17.30|0.597 / 0.607|4.88x|\n|128256|128|89.6|33.80|22.70|0.672 / 0.674|3.94x|\n|151936|1|78.1|24.30|12.40|0.510 / 0.515|6.31x|\n|151936|2|82.8|24.40|12.60|0.516 / 0.512|6.57x|\n|151936|4|84.2|24.70|12.80|0.518 / 0.520|6.56x|\n|151936|8|91.2|25.20|13.30|0.528 / 0.532|6.83x|\n|151936|16|90.3|26.40|14.80|0.561 / 0.556|6.08x|\n|151936|32|89.8|27.60|16.20|0.587 / 0.587|5.55x|\n|151936|64|89.5|30.80|19.50|0.633 / 0.627|4.60x|\n|151936|128|98.1|37.80|26.00|0.688 / 0.691|3.78x|\n|262144|1|81.8|24.70|12.50|0.506 / 0.506|6.54x|\n|262144|2|84.4|24.60|12.80|0.520 / 0.508|6.58x|\n|262144|4|88.0|25.80|13.10|0.508 / 0.520|6.71x|\n|262144|8|93.4|26.10|14.10|0.540 / 0.530|6.62x|\n|262144|16|90.6|28.20|15.70|0.557 / 0.568|5.75x|\n|262144|32|131.5|30.30|18.10|0.597 / 0.599|7.25x|\n|262144|64|120.8|37.40|25.50|0.682 / 0.685|4.74x|\n|262144|128|143.4|49.10|37.00|0.754 / 0.754|3.88x|\n\n**k = 1000, eager**\n\n|V|B|top_k_first|round 8|round 9|r9/r8 order 1 / "},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"R200\", \"model\": null, \"shape\": \"ept=32, two-to-five-chunk rows\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.01, \"speedup\": 1.01}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"ept=32, two-to-five-chunk rows\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.31, \"speedup\": 1.31}, {\"scope\": \"kernel\", \"hardware\": \"H100\", \"model\": null, \"shape\": \"ept=32, two-to-five-chunk rows\", \"batch_size\": null, \"metric\": \"speedup\", \"unit\": null, \"higher_is_better\": true, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.31, \"speedup\": 1.31}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"k = 1000, graph replay\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 0.17, \"speedup\": 0.17}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"k = 1000, graph replay\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 0.19, \"speedup\": 0.19}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"k = 1000, graph replay\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 0.53, \"speedup\": 0.53}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"k = 1000, graph replay\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 0.83, \"speedup\": 0.83}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"k <= 50, graph replay\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 0.4, \"speedup\": 0.4}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"k <= 50, graph replay\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 0.85, \"speedup\": 0.85}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"k=10\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 0.938, \"stated_speedup\": null, \"speedup\": 1.0661}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"k=10\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 1.01, \"stated_speedup\": null, \"speedup\": 0.9901}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"k=10\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 12.8, \"optimized\": 10.4, \"stated_speedup\": null, \"speedup\": 1.2308}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"k=10\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 13.3, \"optimized\": 11.0, \"stated_speedup\": null, \"speedup\": 1.2091}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"k=10\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 14.0, \"optimized\": 11.6, \"stated_speedup\": null, \"speedup\": 1.2069}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"k=50\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 0.955, \"stated_speedup\": null, \"speedup\": 1.0471}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"k=50\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 1.0, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"k=1000\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 0.98, \"stated_speedup\": null, \"speedup\": 1.0204}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"k=1000\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 1.028, \"stated_speedup\": null, \"speedup\": 0.9728}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"k=10\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 0.905, \"stated_speedup\": null, \"speedup\": 1.105}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"k=10\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 1.0, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"k=50\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 0.923, \"stated_speedup\": null, \"speedup\": 1.0834}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"k=50\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 1.008, \"stated_speedup\": null, \"speedup\": 0.9921}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"k=1000\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 0.883, \"stated_speedup\": null, \"speedup\": 1.1325}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"k=1000\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 1.087, \"stated_speedup\": null, \"speedup\": 0.92}, {\"scope\": \"kernel\", \"hardware\": \"H100\", \"model\": null, \"shape\": \"k=10\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 0.819, \"stated_speedup\": null, \"speedup\": 1.221}, {\"scope\": \"kernel\", \"hardware\": \"H100\", \"model\": null, \"shape\": \"k=10\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 1.004, \"stated_speedup\": null, \"speedup\": 0.996}, {\"scope\": \"kernel\", \"hardware\": \"H100\", \"model\": null, \"shape\": \"k=50\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 0.827, \"stated_speedup\": null, \"speedup\": 1.2092}, {\"scope\": \"kernel\", \"hardware\": \"H100\", \"model\": null, \"shape\": \"k=50\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 1.0, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"H100\", \"model\": null, \"shape\": \"k=1000\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 0.97, \"stated_speedup\": null, \"speedup\": 1.0309}, {\"scope\": \"kernel\", \"hardware\": \"H100\", \"model\": null, \"shape\": \"k=1000\", \"batch_size\": null, \"metric\": \"time\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 1.0, \"optimized\": 1.025, \"stated_speedup\": null, \"speedup\": 0.9756}, {\"scope\": \"kernel\", \"hardware\": \"R200\", \"model\": null, \"shape\": \"k=10\", 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null, \"model\": null, \"shape\": \"V=262144,B=128\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": null, \"higher_is_better\": false, \"baseline\": 49.5, \"optimized\": 38.6, \"stated_speedup\": 7.5, \"speedup\": 1.2824}]"},"kernel_speedup":{"kind":"number","value":1.0667,"string":"1.0667"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":997,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"a1b9e13a4aa0093b0585a65d4808f6469b390555"},"date":{"kind":"string","value":"2026-10-05T21:10:40+03:00"},"pr_number":{"kind":"number","value":5267,"string":"5,267"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/5267"},"title":{"kind":"string","value":"perf(mamba): enable native SM107 stochastic rounding (#5267)"},"message":{"kind":"string","value":"perf(mamba): enable native SM107 stochastic rounding (#5267)\n\n<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nEnable native stochastic rounding on Rubin (SM107a) for Mamba state\nupdates. The existing architecture guard omitted SM107a, causing Rubin\nto use software conversion. This PR adds `__CUDA_ARCH_FEAT_SM107_ALL` to\n`FLASHINFER_MAMBA_HAS_CVT_RS`, adds compute capability `(10, 7)` to\n`is_cvt_rs_supported()`, and updates the hardware-test descriptions and\nskip messages. The shared guard enables the existing FP16 and E4M3\nnative conversion paths.\n\n### Performance\n\nCompared using CUDA 13.4, PyTorch `2.14.0a0+4fdf77b940.nv26.08`, and\nTriton 3.8.0.\n\nWorkload: Nemotron 3 Ultra TP1, 256 heads, head dimension 64, state\ndimension 128, and 8 groups. Horizontal single-token update (`T=1`),\nFP16 state, BF16 inputs/output, FP32 A, seeded stochastic rounding with\n`philox_rounds=5`.\n\n| Batch | Before (µs) | After (µs) | Paired speedup | Latency reduction\n|\n|---:|---:|---:|---:|---:|\n| 1 | 10.848 | 7.648 | 1.413× | 29.21% |\n| 64 | 132.768 | 85.808 | 1.547× | 35.37% |\n| 256 | 502.880 | 319.760 | 1.573× | 36.41% |\n\nEach measurement used 20 warmups and 100 eager CUDA-event samples; state\nrestoration and a 2×L2 flush occurred outside timing. Each revision used\na fresh JIT cache, with compilation outside timing. CUDA graphs and\nclock locks were disabled.\n\nLatencies are pooled medians over 200 samples per revision/batch. Paired\nspeedup is the geometric mean of the two within-round median ratios;\nlatency reduction is `1 − 1 / paired_speedup`. Consequently, the pooled\nlatency ratio may differ slightly from the paired speedup.\n\nThese are SSU kernel/API timings. The two rounds do not establish\nstatistical significance or measure full-model serving throughput.\n\n## 🔍 Related Issues\n\nNone linked.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull\nrequest, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit`\n(or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files`\nand fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n\n## Reviewer Notes\n\nThe capability helper and CUDA guard should remain synchronized. The\nshared guard affects both FP16 and E4M3 conversion, while the\nperformance results above cover FP16 horizontal single-token updates\nonly.\n\nInternal benchmark provenance: `login-hecate`, run directory\n`/lustre/fsw/coreai_nvfm_llm/rgarnett/lights-out-inference/runs/flashinfer-ssu-5f29e0eb-before-after-20260916-125122/`.\nThe directory contains `report.md`, the benchmark scripts, per-round\nCSVs, raw timing samples, numerical errors, loaded binary hashes, and\nenvironment metadata. Slurm job `595820` completed successfully. These\nartifacts require internal access.\n\nGPU test provenance: Slurm job `595895` completed with exit `0:0` in\n17m59s. Full pytest logs, JUnit XML, per-case outcomes and environment\nmetadata are under\n`/lustre/fsw/coreai_nvfm_llm/rgarnett/lights-out-inference/runs/flashinfer-sm107-tests-cc5a53a6-20260916-132253/`\non `login-hecate`.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai\n-->\n## Summary by CodeRabbit\n\n* **New Features**\n* Added hardware-accelerated stochastic rounding support for SM107\n(Rubin) GPUs, alongside SM100 and SM103.\n* Updated FP16 and FP8 conversion support to recognize SM107-compatible\nhardware.\n* **Bug Fixes**\n* Improved capability detection so supported architectures are\nidentified consistently.\n* **Tests**\n* Updated hardware compatibility checks and unsupported-device messages\nto include SM107 GPUs and the supported architecture list.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\nSigned-off-by: Roi Garnett <rgarnett@nvidia.com>"},"path":{"kind":"string","value":"include/flashinfer/mamba/conversion.cuh"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"#pragma once\n#include <cuda.h>\n#include <cuda_fp16.h>\n#include <cuda_fp8.h>\n#ifdef FLASHINFER_ENABLE_BF16\n#include <cuda_bf16.h>\n#endif\n\nnamespace flashinfer::mamba::conversion {\n\ninline __device__ float toFloat(float f) { return f; }\n\ninline __device__ float toFloat(__half h) { return __half2float(h); }\n\n#ifdef FLASHINFER_ENABLE_BF16\ninline __device__ float toFloat(__nv_bfloat16 val) { return __bfloat162float(val); }\n#endif\n\n// No accuracy loss: int8_t / int16_t range fits exactly in float32 (24-bit\n// mantissa represents all integers up to 2^24 = 16M exactly).\ninline __device__ float toFloat(int8_t val) { return static_cast<float>(val); }\ninline __device__ float toFloat(int16_t val) { return static_cast<float>(val); }\n\n// fp8 e4m3 → fp32. Goes via __half (cuda_fp8 library has the implicit\n// conversion that compiles to `cvt.rn.f16.e4m3` PTX on sm_89+), then\n// __half2float for the final step. No direct fp8→fp32 PTX op exists.\ninline __device__ float toFloat(__nv_fp8_e4m3 val) {\n return __half2float(static_cast<__half>(val));\n}\n\n// Packed 2-element conversion: convert a packed pair to float2.\n// Uses native packed intrinsics for bf16/fp16 (fewer PRMT/SHF instructions).\ninline __device__ float2 toFloat2(float2 packed) { return packed; }\n\ninline __device__ float2 toFloat2(__half2 packed) { return __half22float2(packed); }\n\n// Pointer-based overloads: read two consecutive elements and convert to float2.\n// Dispatches to the packed intrinsic for bf16/fp16 via the overloads above.\ninline __device__ float2 toFloat2(float const* ptr) { return {ptr[0], ptr[1]}; }\n\ninline __device__ float2 toFloat2(__half const* ptr) {\n return toFloat2(*reinterpret_cast<__half2 const*>(ptr));\n}\n\n#ifdef FLASHINFER_ENABLE_BF16\n// inline __device__ float2 toFloat2(__nv_bfloat162 packed) { return __bfloat1622float2(packed); }\n\ninline __device__ float2 toFloat2(__nv_bfloat162 packed) {\n // bf16 is the upper 16 bits of f32 — shift/mask is cheaper than PRMT byte permutation.\n // NOTE: this ignores denormals\n uint32_t bits = reinterpret_cast<uint32_t const&>(packed);\n float2 out;\n out.x = __uint_as_float(bits << 16); // low bf16 → upper 16 bits of f32\n out.y = __uint_as_float(bits & 0xFFFF0000u); // high bf16 already in upper 16 bits\n return out;\n}\n\ninline __device__ float2 toFloat2(__nv_bfloat16 const* ptr) {\n return toFloat2(*reinterpret_cast<__nv_bfloat162 const*>(ptr));\n}\n\n// Paired f32 → bf16 conversion: pack two f32 values into __nv_bfloat162.\n// Uses native cvt.rn.bf16x2.f32 — single instruction, round-to-nearest-even.\ninline __device__ __nv_bfloat162 fromFloat2(float2 val) {\n uint32_t result;\n asm(\"cvt.rn.bf16x2.f32 %0, %1, %2;\\n\" : \"=r\"(result) : \"f\"(val.y), \"f\"(val.x));\n return reinterpret_cast<__nv_bfloat162 const&>(result);\n}\n\n#endif\n\ninline __device__ float2 toFloat2(int8_t const* ptr) { return {toFloat(ptr[0]), toFloat(ptr[1])}; }\ninline __device__ float2 toFloat2(int16_t const* ptr) { return {toFloat(ptr[0]), toFloat(ptr[1])}; }\n\ninline __device__ void convertAndStore(float* output, float input) { *output = input; }\n\ninline __device__ void convertAndStore(__half* output, float input) {\n *output = __float2half(input);\n}\n\n#ifdef FLASHINFER_ENABLE_BF16\ninline __device__ void convertAndStore(__nv_bfloat16* output, float input) {\n *output = __float2bfloat16(input);\n}\n#endif\n\ninline __device__ void convertAndStore(int16_t* output, float input) {\n // Symmetric clip: [-max, max] (not [-max-1, max]) so that negation is safe.\n // Matches Triton reference which clips to [-32767, 32767] before storing.\n constexpr float int16_max = static_cast<float>(std::numeric_limits<int16_t>::max());\n input = fminf(fmaxf(input, -int16_max), int16_max);\n *output = static_cast<int16_t>(__float2int_rn(input));\n}\n\n// =============================================================================\n// Philox-4x32 PRNG (matches Triton's tl.randint)\n// =============================================================================\n\n// Derive a per-layer Philox seed with the SplitMix64 finalizer (Stafford mix13).\n// Multi-layer kernels use this to derive independent layer streams from one\n// base seed; single-layer kernels receive their layer-specific seed directly.\n__device__ __forceinline__ int64_t layer_philox_seed(int64_t base_seed, int layer) {\n uint64_t z = static_cast<uint64_t>(base_seed) ^ (0x9E3779B97F4A7C15ULL * (uint64_t(layer) + 1));\n z = (z ^ (z >> 30)) * 0xBF58476D1CE4E5B9ULL;\n z = (z ^ (z >> 27)) * 0x94D049BB133111EBULL;\n return static_cast<int64_t>(z ^ (z >> 31));\n}\n\n// Generates four pseudorandom uint32s from (seed, offset) using the Philox-4x32 algorithm.\n// Produces bit-identical output to Triton's tl.randint4x(seed, offset, n_rounds).\n// The offset is int64 and split across Philox c0 (low 32 bits) and c1 (high\n// 32 bits) — matches the i64 path of `randint4x` in triton/language/random.py.\n// Provides 2^64 unique counter values per seed, avoiding collisions in large\n// caches where `cache_slot * stride` exceeds 2^32.\n// All four outputs (c0..c3) are independent and uniformly distributed.\ntemplate <int n_rounds = 10>\n__device__ __forceinline__ void philox_randint4x(int64_t seed, int64_t offset, uint32_t& r0,\n uint32_t& r1, uint32_t& r2, uint32_t& r3) {\n constexpr uint32_t PHILOX_KEY_A = 0x9E3779B9u;\n constexpr uint32_t PHILOX_KEY_B = 0xBB67AE85u;\n constexpr uint32_t PHILOX_ROUND_A = 0xD2511F53u;\n constexpr uint32_t PHILOX_ROUND_B = 0xCD9E8D57u;\n\n uint32_t k0 = static_cast<uint32_t>(static_cast<uint64_t>(seed));\n uint32_t k1 = static_cast<uint32_t>(static_cast<uint64_t>(seed) >> 32);\n uint64_t uoffset = static_cast<uint64_t>(offset);\n uint32_t c0 = static_cast<uint32_t>(uoffset);\n uint32_t c1 = static_cast<uint32_t>(uoffset >> 32);\n uint32_t c2 = 0, c3 = 0;\n\n#pragma unroll\n for (int i = 0; i < n_rounds; i++) {\n uint32_t _c0 = c0, _c2 = c2;\n c0 = __umulhi(PHILOX_ROUND_B, _c2) ^ c1 ^ k0;\n c2 = __umulhi(PHILOX_ROUND_A, _c0) ^ c3 ^ k1;\n c1 = PHILOX_ROUND_B * _c2;\n c3 = PHILOX_ROUND_A * _c0;\n k0 += PHILOX_KEY_A;\n k1 += PHILOX_KEY_B;\n }\n r0 = c0;\n r1 = c1;\n r2 = c2;\n r3 = c3;\n}\n\n// Generates a pseudorandom uint32 from (seed, offset) using the Philox-4x32 algorithm.\n// Produces bit-identical output to Triton's tl.randint(seed, offset, n_rounds).\n// The offset is int64 (low/high split across Philox c0/c1) — see\n// philox_randint4x for the full rationale.\n// NOTE: This discards 3 of the 4 Philox outputs. For better throughput, use\n// philox_randint4x to get all 4 outputs from a single Philox invocation.\ntemplate <int n_rounds = 10>\n__device__ __forceinline__ uint32_t philox_randint(int64_t seed, int64_t offset) {\n uint32_t r0, r1, r2, r3;\n philox_randint4x<n_rounds>(seed, offset, r0, r1, r2, r3);\n return r0;\n}\n\n// Hardware `cvt.rs.*` (stochastic-rounding convert) is available ONLY on the\n// datacenter Blackwell \"a\" targets that actually carry the `.rs` PTX feature:\n// sm_100a (B200) and sm_103a (B300). There is NO generic CUDA feature macro for\n// it — `__CUDA_ARCH_SPECIFIC__` is too broad (sm_120a defines it but ptxas\n// rejects `.rs`), so the arches are enumerated here in ONE place.\n//\n// The trap this guard exists to avoid: B300 is sm_103a and does NOT define\n// `__CUDA_ARCH_FEAT_SM100_ALL`, so a SM100-only guard silently compiled the\n// ~12-instruction software emulation there — measured +99% SR cost at b1024 vs\n// +24% on B200 (2026-07-13). sm_110a / sm_120a lack `.rs` (ptxas errors) → they\n// correctly fall to the software path below. Extend the list only after\n// confirming `cvt.rs.f16x2.f32` assembles for the new arch. sm_107a: verified with\n// the CUDA 13.4 ptxas (sm_110a/sm_120a still reject `.rs`).\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 1000 && \\\n (defined(__CUDA_ARCH_FEAT_SM100_ALL) || defined(__CUDA_ARCH_FEAT_SM103_ALL) || \\\n defined(__CUDA_ARCH_FEAT_SM107_ALL))\n#define FLASHINFER_MAMBA_HAS_CVT_RS 1\n#else\n#define FLASHINFER_MAMBA_HAS_CVT_RS 0\n#endif\n\n// =============================================================================\n// Stochastic rounding: fp32 → fp16\n// =============================================================================\n\n// Software stochastic rounding: convert one fp32 value to fp16 using 13 random bits.\n// Adds random noise at the sub-fp16-mantissa position, then truncates.\n// rand13: 13-bit random value in bits [12:0].\n__device__ __forceinline__ uint16_t cvt_rs_f16_sw(float x, uint32_t rand13) {\n uint32_t bits = __float_as_uint(x);\n uint32_t sign = bits & 0x80000000u;\n uint32_t abs_bits = bits & 0x7FFFFFFFu;\n\n // fp32 has 23 mantissa bits, fp16 has 10. The 13 LSBs are the remainder.\n // Add 13-bit random noise at bits [12:0]. Carry into bit 13 → round up.\n abs_bits += (rand13 & 0x1FFFu);\n\n // Convert to fp16 by truncation.\n uint32_t f32_exp = (abs_bits >> 23) & 0xFFu;\n uint32_t f32_mantissa = abs_bits & 0x7FFFFFu;\n\n uint16_t f16_bits;\n if (f32_exp == 0xFF) {\n f16_bits = (f32_mantissa != 0) ? 0x7E00u : 0x7C00u; // NaN or Inf\n } else if (f32_exp > 142) { // 127 + 15 = 142 → overflow to Inf\n f16_bits = 0x7C00u;\n } else if (f32_exp < 113) { // 127 - 14 = 113 → underflow to zero\n f16_bits = 0;\n } else {\n uint16_t f16_exp = static_cast<uint16_t>(f32_exp - 112); // rebias: 127→15\n uint16_t f16_mantissa = static_cast<uint16_t>(f32_mantissa >> 13);\n f16_bits = (f16_exp << 10) | f16_mantissa;\n }\n\n return static_cast<uint16_t>(sign >> 16) | f16_bits;\n}\n\n// Forward declaration (defined below, after cvt_rs_f16x2_f32).\n__device__ __forceinline__ uint32_t cvt_rs_f16x2_f32(float a, float b, uint32_t rbits);\n\n// Stochastic rounding: convert one fp32 value to fp16 using 13 random bits.\n// On sm_100a+: uses PTX cvt.rs.f16x2.f32 with a dummy zero second input.\n// On other archs: software emulation.\n__device__ __forceinline__ __half cvt_rs_f16_f32(float x, uint32_t rand13) {\n#if FLASHINFER_MAMBA_HAS_CVT_RS\n // Pack rand13 into rbits[12:0] (for PTX operand b → low half → our x).\n // High half gets zero noise for the dummy input.\n uint32_t rbits = rand13 & 0x1FFFu;\n uint32_t packed = cvt_rs_f16x2_f32(x, 0.0f, rbits);\n return __ushort_as_half(static_cast<uint16_t>(packed & 0xFFFFu));\n#else\n return __ushort_as_half(cvt_rs_f16_sw(x, rand13));\n#endif\n}\n\n// Stochastic rounding: convert two fp32 values to packed fp16x2 using random bits.\n// On sm_100a+: uses PTX cvt.rs.f16x2.f32 instruction.\n// On other archs: software emulation matching the hardware behavior.\n//\n// rbits layout (from PTX docs):\n// bits [28:16] = 13 random bits for PTX operand \"a\" (→ d[31:16], high half)\n// bits [12:0] = 13 random bits for PTX operand \"b\" (→ d[15:0], low half)\n// bits [31:29] and [15:13] = unused (zero)\n// from: https://docs.nvidia.com/cuda/parallel-thread-execution/#cvt-rs-rbits-layout-f16\n//\n// Our asm maps: %1→C++ a→PTX b→d[15:0], %2→C++ b→PTX a→d[31:16]\n// So: C++ a uses rbits[12:0], C++ b uses rbits[28:16].\n__device__ __forceinline__ uint32_t cvt_rs_f16x2_f32(float a, float b, uint32_t rbits) {\n#if FLASHINFER_MAMBA_HAS_CVT_RS\n uint32_t packed;\n asm(\"cvt.rs.f16x2.f32 %0, %2, %1, %3;\"\n : \"=r\"(packed)\n : \"r\"(__float_as_uint(a)), \"r\"(__float_as_uint(b)), \"r\"(rbits));\n return packed;\n#else\n uint32_t rand_a = rbits & 0x1FFFu; // bits [12:0] → C++ a (PTX b → low half)\n uint32_t rand_b = (rbits >> 16) & 0x1FFFu; // bits [28:16] → C++ b (PTX a → high half)\n uint16_t a_fp16 = __half_as_ushort(cvt_rs_f16_f32(a, rand_a));\n uint16_t b_fp16 = __half_as_ushort(cvt_rs_f16_f32(b, rand_b));\n return static_cast<uint32_t>(a_fp16) | (static_cast<uint32_t>(b_fp16) << 16);\n#endif\n}\n\n// Stochastic rounding store: generates Philox random bits and converts fp32 → fp16 in one call.\n// PHILOX_ROUNDS: number of Philox rounds (compile-time), must be > 0.\n// seed: Philox seed (from params.rand_seed).\n// offset: unique per-element offset (e.g. d * DSTATE + i) for deterministic randomness.\ntemplate <int PHILOX_ROUNDS>\ninline __device__ void convertSRAndStore(__half* output, float input, int64_t seed,\n uint32_t offset) {\n uint32_t rand = philox_randint<PHILOX_ROUNDS>(seed, offset);\n *output = cvt_rs_f16_f32(input, rand & 0x1FFFu);\n}\n\n// =============================================================================\n// Stochastic rounding: fp32 → fp8 (e4m3)\n// =============================================================================\n\n// Bit-reverse 16 bits. HW gives both elements of a pair 16 bits of independent\n// SR randomness while consuming a single 16-bit chunk per pair: one element uses\n// the chunk straight, the other uses bitrev16 of it. Two bitrev16'd halves of a\n// uniformly random 16-bit value remain uniformly distributed and are statistically\n// independent, so each element gets full 16-bit unbiased SR while sharing one\n// 16-bit register with its pair-mate.\n//\n// Implementation: PTX `brev.b32` (CUDA intrinsic `__brev`) is a single-ALU-op\n// 32-bit reverse; we right-shift by 16 to land the 16 LSBs of input in the 16\n// LSBs of output. Total: 2 SASS instructions (brev + shf/shr), vs the prior\n// software 4-step mask/shift/OR chain (~12-16 inst).\n__device__ __forceinline__ uint32_t bitrev16(uint32_t b) { return __brev(b) >> 16; }\n\n// Software stochastic rounding: convert one fp32 value to e4m3 (FN, satfinite) using 16 random\n// bits.\n//\n// Algorithm: place `rand16` at the top of the discarded mantissa range, then truncate.\n// shift_truncate = 20 for normal binade (unbiased >= -6)\n// = 14 - unbiased for subnormal/underflow\n// contribution = rand16 << (shift_truncate - 16)\n// total = mant24 + contribution (in uint64 to avoid overflow)\n// int_part = total >> shift_truncate\n// Then re-encode int_part as e4m3, handling subnormal→normal transitions and saturation.\n//\n// Saturation (satfinite):\n// |x| > 448 → ±448 (max finite e4m3 = 0x7E)\n// ±Inf → ±448\n// NaN → canonical NaN with sign preserved (S|1111|111 = 0x7F or 0xFF)\n//\n// Verified bitwise against HW (cvt.rs.satfinite.e4m3x4.f32 on sm_100a) across 22528\n// inputs spanning subnormal, normal, and saturation regions during the SR\n// reverse-engineering effort — see .plans/e4m3_stochastic_rounding.md.\n__device__ __forceinline__ uint8_t cvt_rs_e4m3_sw(float x, uint32_t rand16) {\n uint32_t bits = __float_as_uint(x);\n uint32_t sign = (bits >> 31) & 1u;\n uint32_t abs_bits = bits & 0x7FFFFFFFu;\n uint32_t f32_exp = (abs_bits >> 23) & 0xFFu;\n uint32_t f32_mant = abs_bits & 0x7FFFFFu;\n\n // NaN / Inf\n if (f32_exp == 0xFFu) {\n if (f32_mant != 0) {\n return static_cast<uint8_t>(0x7Fu | (sign << 7)); // canonical e4m3 NaN\n } else {\n return static_cast<uint8_t>(0x7Eu | (sign << 7)); // Inf → ±max finite\n }\n }\n\n // fp32 zero / denormal → e4m3 zero (with sign).\n if (f32_exp == 0u) {\n return static_cast<uint8_t>(sign << 7);\n }\n\n int unbiased = static_cast<int>(f32_exp) - 127;\n uint64_t mant24 = 0x800000u | f32_mant; // implicit-1 + mantissa, 24-bit\n int shift_truncate = (unbiased >= -6) ? 20 : (14 - unbiased);\n int rand_shift = shift_truncate - 16;\n uint64_t rand_contrib;\n if (rand_shift < 0) {\n // Defensive: shift_truncate < 16 shouldn't happen for valid normal/subnormal e4m3.\n rand_contrib = static_cast<uint64_t>(rand16 & 0xFFFFu) >> (-rand_shift);\n } else if (rand_shift < 56) {\n rand_contrib = static_cast<uint64_t>(rand16 & 0xFFFFu) << rand_shift;\n } else {\n rand_contrib = 0;\n }\n uint64_t total = mant24 + rand_contrib;\n // Guard the shift: shift_truncate reaches 140 for tiny-normal fp32\n // (unbiased < -49), which is UB for a uint64_t shift. Mathematically the\n // result is 0 there (the value is far below e4m3's smallest subnormal),\n // so flush to int_part = 0. The downstream subnormal branch rounds it to ±0.\n uint32_t int_part = (shift_truncate >= 64) ? 0u : static_cast<uint32_t>(total >> shift_truncate);\n\n if (unbiased >= -6) {\n // Started in normal binade. int_part ∈ [8, 15] normally; can overflow to 16+ if rand\n // bumped the exponent.\n int e4m3_exp = unbiased + 7;\n while (int_part >= 16u) {\n int_part >>= 1;\n e4m3_exp += 1;\n }\n if (e4m3_exp > 15 || (e4m3_exp == 15 && (int_part & 0x7u) == 7u)) {\n return static_cast<uint8_t>(0x7Eu | (sign << 7));\n }\n return static_cast<uint8_t>((sign << 7) | (e4m3_exp << 3) | (int_part & 0x7u));\n } else {\n // Started in subnormal/underflow. int_part:\n // 0 → zero\n // 1..7 → subnormal e4m3\n // 8..15 → smallest normal binade (e4m3_exp = 1)\n // 16+ → higher normal binades (rare; only if rand pushed up multiple binades)\n if (int_part == 0u) {\n return static_cast<uint8_t>(sign << 7);\n }\n if (int_part <= 7u) {\n return static_cast<uint8_t>((sign << 7) | int_part);\n }\n int e4m3_exp = 1;\n while (int_part >= 16u) {\n int_part >>= 1;\n e4m3_exp += 1;\n }\n if (e4m3_exp > 15 || (e4m3_exp == 15 && (int_part & 0x7u) == 7u)) {\n return static_cast<uint8_t>(0x7Eu | (sign << 7));\n }\n return static_cast<uint8_t>((sign << 7) | (e4m3_exp << 3) | (int_part & 0x7u));\n }\n}\n\n// Stochastic rounding: convert four fp32 values to packed fp8x4 e4m3 using random bits.\n// On sm_100a+: uses PTX cvt.rs.satfinite.e4m3x4.f32 (combined stochastic-round + saturate).\n// On other archs: software fallback via cvt_rs_e4m3_sw.\n//\n// Output layout (low byte first):\n// packed[ 7: 0] = e4m3(a)\n// packed[15: 8] = e4m3(b)\n// packed[23:16] = e4m3(c)\n// packed[31:24] = e4m3(d)\n//\n// rbits layout (per PTX docs + empirical HW oracle, see .plans/e4m3_stochastic_rounding.md):\n// bits [31:16] = pair rbits for PTX operands a/b (high two outputs)\n// bits [15: 0] = pair rbits for PTX operands e/f (low two outputs)\n// Each PAIR shares its 16-bit chunk: HW uses the chunk straight for the \"even\"\n// PTX operand (b, f → low byte of pair output) and bitrev16 of the chunk for\n// the \"odd\" operand (a, e → high byte of pair output). Both elements get the\n// full 16 bits of independent SR randomness this way.\n// our `a` (PTX f, → byte 0) uses rbits[15: 0]\n// our `b` (PTX e, → byte 1) uses bitrev16(rbits[15: 0])\n// our `c` (PTX b, → byte 2) uses rbits[31:16]\n// our `d` (PTX a, → byte 3) uses bitrev16(rbits[31:16])\n//\n// PTX syntax `cvt.rs.satfinite.e4m3x4.f32 d, {a3, a2, a1, a0}, rbits` writes\n// e4m3(a_i) into byte i of d. We want byte 0 = e4m3(a), so the source-vector\n// ordering is {d, c, b, a} = {%4, %3, %2, %1}. See PTX ISA:\n// https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt\n__device__ __forceinline__ uint32_t cvt_rs_e4m3x4_f32(float a, float b, float c, float d,\n uint32_t rbits) {\n#if FLASHINFER_MAMBA_HAS_CVT_RS\n uint32_t packed;\n asm(\"cvt.rs.satfinite.e4m3x4.f32 %0, {%4, %3, %2, %1}, %5;\"\n : \"=r\"(packed)\n : \"r\"(__float_as_uint(a)), \"r\"(__float_as_uint(b)), \"r\"(__float_as_uint(c)),\n \"r\"(__float_as_uint(d)), \"r\"(rbits));\n return packed;\n#else\n uint32_t low_chunk = rbits & 0xFFFFu;\n uint32_t high_chunk = (rbits >> 16) & 0xFFFFu;\n uint8_t pa = cvt_rs_e4m3_sw(a, low_chunk); // PTX f → byte 0\n uint8_t pb = cvt_rs_e4m3_sw(b, bitrev16(low_chunk)); // PTX e → byte 1\n uint8_t pc = cvt_rs_e4m3_sw(c, high_chunk); // PTX b → byte 2\n uint8_t pd = cvt_rs_e4m3_sw(d, bitrev16(high_chunk)); // PTX a → byte 3\n return static_cast<uint32_t>(pa) | (static_cast<uint32_t>(pb) << 8) |\n (static_cast<uint32_t>(pc) << 16) | (static_cast<uint32_t>(pd) << 24);\n#endif\n}\n\n// =============================================================================\n// Round-to-nearest-even + saturate: fp32 → int8\n// =============================================================================\n\n// cvt.rni.sat.s8.f32: single PTX instruction on sm_80+, replaces\n// the F2I.S32 + VIMNMX(min 127) + VIMNMX(max -127) chain.\n// Saturates to [-128, 127]. Callers using encode_scale = 127/amax\n// guarantee |input| ≤ 127.0, so -128 is never produced.\n__device__ __forceinline__ int8_t cvt_rni_sat_s8(float x) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800\n int32_t result;\n asm(\"cvt.rni.sat.s8.f32 %0, %1;\" : \"=r\"(result) : \"f\"(x));\n return static_cast<int8_t>(result);\n#else\n return static_cast<int8_t>(max(-128, min(127, __float2int_rn(x))));\n#endif\n}\n\n// =============================================================================\n// Stochastic rounding + saturate: fp32 → int8\n// =============================================================================\n\n// Software SR for int8: add uniform noise in [0, 1) then floor.\n// Matches Triton's `floor(scaled_value + rand01)` where\n// `rand01 = (rand & 0x00FFFFFF) * (1.0 / (1 << 24))`.\n// Saturates to [-127, 127] (symmetric, matching encode_scale = 127/amax).\n__device__ __forceinline__ int8_t cvt_rs_sat_s8(float x, uint32_t rand_bits) {\n float const rand01 =\n static_cast<float>(rand_bits & 0x00FFFFFFu) * (1.0f / static_cast<float>(1 << 24));\n // `__float2int_rd` (round toward -infinity) fuses `floorf` + `__float2int_rz`\n // into a single `cvt.rmi.s32.f32` SASS instruction, saving one FRND per call.\n int32_t const clamped = max(-127, min(127, __float2int_rd(x + rand01)));\n return static_cast<int8_t>(clamped);\n}\n\n// Stochastic rounding: convert four fp32 values to packed s8x4 using a single\n// 32-bit random integer. Analogous to cvt_rs_e4m3x4_f32: 16-bit chunks are\n// reused via bitrev16 so each output gets 16 bits of independent randomness\n// while consuming only one shared 16-bit chunk per pair (two bitrev16'd halves\n// of a uniform 16-bit value remain uniformly distributed and statistically\n// independent).\n//\n// 16-bit entropy per element is far more than int8 SR requires: the rounding\n// decision compares against a fractional residual with at most ~7 bits of\n// meaningful precision for int8, so no quality loss vs the 24-bit scalar path.\n//\n// Amortization: 1 random u32 → 4 SR int8s. A single Philox call (4 u32s)\n// covers 16 int8 conversions, a 4× reduction in PRNG cost vs the scalar\n// cvt_rs_sat_s8 path.\n__device__ __forceinline__ uint32_t cvt_rs_sat_s8x4_f32(float a, float b, float c, float d,\n uint32_t rbits) {\n uint32_t const low_chunk = rbits & 0xFFFFu;\n uint32_t const high_chunk = (rbits >> 16) & 0xFFFFu;\n constexpr float kInv16 = 1.0f / static_cast<float>(1u << 16);\n\n float const r_a = static_cast<float>(low_chunk) * kInv16;\n float const r_b = static_cast<float>(bitrev16(low_chunk)) * kInv16;\n float const r_c = static_cast<float>(high_chunk) * kInv16;\n float const r_d = static_cast<float>(bitrev16(high_chunk)) * kInv16;\n\n // `__float2int_rd` (round toward -infinity) emits a single `cvt.rmi.s32.f32`\n // SASS op, fusing the `floorf` + `__float2int_rz` chain into one instruction.\n int32_t const pa = max(-127, min(127, __float2int_rd(a + r_a)));\n int32_t const pb = max(-127, min(127, __float2int_rd(b + r_b)));\n int32_t const pc = max(-127, min(127, __float2int_rd(c + r_c)));\n int32_t const pd = max(-127, min(127, __float2int_rd(d + r_d)));\n\n return (static_cast<uint32_t>(pa) & 0xFFu) | ((static_cast<uint32_t>(pb) & 0xFFu) << 8) |\n ((static_cast<uint32_t>(pc) & 0xFFu) << 16) | ((static_cast<uint32_t>(pd) & 0xFFu) << 24);\n}\n\n} // namespace flashinfer::mamba::conversion\n"},"after_code":{"kind":"string","value":"#pragma once\n#include <cuda.h>\n#include <cuda_fp16.h>\n#include <cuda_fp8.h>\n#ifdef FLASHINFER_ENABLE_BF16\n#include <cuda_bf16.h>\n#endif\n\nnamespace flashinfer::mamba::conversion {\n\ninline __device__ float toFloat(float f) { return f; }\n\ninline __device__ float toFloat(__half h) { return __half2float(h); }\n\n#ifdef FLASHINFER_ENABLE_BF16\ninline __device__ float toFloat(__nv_bfloat16 val) { return __bfloat162float(val); }\n#endif\n\n// No accuracy loss: int8_t / int16_t range fits exactly in float32 (24-bit\n// mantissa represents all integers up to 2^24 = 16M exactly).\ninline __device__ float toFloat(int8_t val) { return static_cast<float>(val); }\ninline __device__ float toFloat(int16_t val) { return static_cast<float>(val); }\n\n// fp8 e4m3 → fp32. Goes via __half (cuda_fp8 library has the implicit\n// conversion that compiles to `cvt.rn.f16.e4m3` PTX on sm_89+), then\n// __half2float for the final step. No direct fp8→fp32 PTX op exists.\ninline __device__ float toFloat(__nv_fp8_e4m3 val) {\n return __half2float(static_cast<__half>(val));\n}\n\n// Packed 2-element conversion: convert a packed pair to float2.\n// Uses native packed intrinsics for bf16/fp16 (fewer PRMT/SHF instructions).\ninline __device__ float2 toFloat2(float2 packed) { return packed; }\n\ninline __device__ float2 toFloat2(__half2 packed) { return __half22float2(packed); }\n\n// Pointer-based overloads: read two consecutive elements and convert to float2.\n// Dispatches to the packed intrinsic for bf16/fp16 via the overloads above.\ninline __device__ float2 toFloat2(float const* ptr) { return {ptr[0], ptr[1]}; }\n\ninline __device__ float2 toFloat2(__half const* ptr) {\n return toFloat2(*reinterpret_cast<__half2 const*>(ptr));\n}\n\n#ifdef FLASHINFER_ENABLE_BF16\n// inline __device__ float2 toFloat2(__nv_bfloat162 packed) { return __bfloat1622float2(packed); }\n\ninline __device__ float2 toFloat2(__nv_bfloat162 packed) {\n // bf16 is the upper 16 bits of f32 — shift/mask is cheaper than PRMT byte permutation.\n // NOTE: this ignores denormals\n uint32_t bits = reinterpret_cast<uint32_t const&>(packed);\n float2 out;\n out.x = __uint_as_float(bits << 16); // low bf16 → upper 16 bits of f32\n out.y = __uint_as_float(bits & 0xFFFF0000u); // high bf16 already in upper 16 bits\n return out;\n}\n\ninline __device__ float2 toFloat2(__nv_bfloat16 const* ptr) {\n return toFloat2(*reinterpret_cast<__nv_bfloat162 const*>(ptr));\n}\n\n// Paired f32 → bf16 conversion: pack two f32 values into __nv_bfloat162.\n// Uses native cvt.rn.bf16x2.f32 — single instruction, round-to-nearest-even.\ninline __device__ __nv_bfloat162 fromFloat2(float2 val) {\n uint32_t result;\n asm(\"cvt.rn.bf16x2.f32 %0, %1, %2;\\n\" : \"=r\"(result) : \"f\"(val.y), \"f\"(val.x));\n return reinterpret_cast<__nv_bfloat162 const&>(result);\n}\n\n#endif\n\ninline __device__ float2 toFloat2(int8_t const* ptr) { return {toFloat(ptr[0]), toFloat(ptr[1])}; }\ninline __device__ float2 toFloat2(int16_t const* ptr) { return {toFloat(ptr[0]), toFloat(ptr[1])}; }\n\ninline __device__ void convertAndStore(float* output, float input) { *output = input; }\n\ninline __device__ void convertAndStore(__half* output, float input) {\n *output = __float2half(input);\n}\n\n#ifdef FLASHINFER_ENABLE_BF16\ninline __device__ void convertAndStore(__nv_bfloat16* output, float input) {\n *output = __float2bfloat16(input);\n}\n#endif\n\ninline __device__ void convertAndStore(int16_t* output, float input) {\n // Symmetric clip: [-max, max] (not [-max-1, max]) so that negation is safe.\n // Matches Triton reference which clips to [-32767, 32767] before storing.\n constexpr float int16_max = static_cast<float>(std::numeric_limits<int16_t>::max());\n input = fminf(fmaxf(input, -int16_max), int16_max);\n *output = static_cast<int16_t>(__float2int_rn(input));\n}\n\n// =============================================================================\n// Philox-4x32 PRNG (matches Triton's tl.randint)\n// =============================================================================\n\n// Derive a per-layer Philox seed with the SplitMix64 finalizer (Stafford mix13).\n// Multi-layer kernels use this to derive independent layer streams from one\n// base seed; single-layer kernels receive their layer-specific seed directly.\n__device__ __forceinline__ int64_t layer_philox_seed(int64_t base_seed, int layer) {\n uint64_t z = static_cast<uint64_t>(base_seed) ^ (0x9E3779B97F4A7C15ULL * (uint64_t(layer) + 1));\n z = (z ^ (z >> 30)) * 0xBF58476D1CE4E5B9ULL;\n z = (z ^ (z >> 27)) * 0x94D049BB133111EBULL;\n return static_cast<int64_t>(z ^ (z >> 31));\n}\n\n// Generates four pseudorandom uint32s from (seed, offset) using the Philox-4x32 algorithm.\n// Produces bit-identical output to Triton's tl.randint4x(seed, offset, n_rounds).\n// The offset is int64 and split across Philox c0 (low 32 bits) and c1 (high\n// 32 bits) — matches the i64 path of `randint4x` in triton/language/random.py.\n// Provides 2^64 unique counter values per seed, avoiding collisions in large\n// caches where `cache_slot * stride` exceeds 2^32.\n// All four outputs (c0..c3) are independent and uniformly distributed.\ntemplate <int n_rounds = 10>\n__device__ __forceinline__ void philox_randint4x(int64_t seed, int64_t offset, uint32_t& r0,\n uint32_t& r1, uint32_t& r2, uint32_t& r3) {\n constexpr uint32_t PHILOX_KEY_A = 0x9E3779B9u;\n constexpr uint32_t PHILOX_KEY_B = 0xBB67AE85u;\n constexpr uint32_t PHILOX_ROUND_A = 0xD2511F53u;\n constexpr uint32_t PHILOX_ROUND_B = 0xCD9E8D57u;\n\n uint32_t k0 = static_cast<uint32_t>(static_cast<uint64_t>(seed));\n uint32_t k1 = static_cast<uint32_t>(static_cast<uint64_t>(seed) >> 32);\n uint64_t uoffset = static_cast<uint64_t>(offset);\n uint32_t c0 = static_cast<uint32_t>(uoffset);\n uint32_t c1 = static_cast<uint32_t>(uoffset >> 32);\n uint32_t c2 = 0, c3 = 0;\n\n#pragma unroll\n for (int i = 0; i < n_rounds; i++) {\n uint32_t _c0 = c0, _c2 = c2;\n c0 = __umulhi(PHILOX_ROUND_B, _c2) ^ c1 ^ k0;\n c2 = __umulhi(PHILOX_ROUND_A, _c0) ^ c3 ^ k1;\n c1 = PHILOX_ROUND_B * _c2;\n c3 = PHILOX_ROUND_A * _c0;\n k0 += PHILOX_KEY_A;\n k1 += PHILOX_KEY_B;\n }\n r0 = c0;\n r1 = c1;\n r2 = c2;\n r3 = c3;\n}\n\n// Generates a pseudorandom uint32 from (seed, offset) using the Philox-4x32 algorithm.\n// Produces bit-identical output to Triton's tl.randint(seed, offset, n_rounds).\n// The offset is int64 (low/high split across Philox c0/c1) — see\n// philox_randint4x for the full rationale.\n// NOTE: This discards 3 of the 4 Philox outputs. For better throughput, use\n// philox_randint4x to get all 4 outputs from a single Philox invocation.\ntemplate <int n_rounds = 10>\n__device__ __forceinline__ uint32_t philox_randint(int64_t seed, int64_t offset) {\n uint32_t r0, r1, r2, r3;\n philox_randint4x<n_rounds>(seed, offset, r0, r1, r2, r3);\n return r0;\n}\n\n// Hardware `cvt.rs.*` (stochastic-rounding convert) is available ONLY on the\n// datacenter Blackwell and Rubin \"a\" targets that carry the `.rs` PTX feature:\n// sm_100a (B200), sm_103a (B300), and sm_107a (Rubin). There is NO generic CUDA\n// feature macro for it — `__CUDA_ARCH_SPECIFIC__` is too broad (sm_120a defines\n// it but ptxas rejects `.rs`), so the arches are enumerated here in ONE place.\n//\n// The trap this guard exists to avoid: B300 is sm_103a and does NOT define\n// `__CUDA_ARCH_FEAT_SM100_ALL`, so a SM100-only guard silently compiled the\n// ~12-instruction software emulation there — measured +99% SR cost at b1024 vs\n// +24% on B200 (2026-07-13). sm_110a / sm_120a lack `.rs` (ptxas errors) → they\n// correctly fall to the software path below. Extend the list only after\n// confirming `cvt.rs.f16x2.f32` assembles for the new arch. sm_107a: verified with\n// the CUDA 13.4 ptxas (sm_110a/sm_120a still reject `.rs`).\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 1000 && \\\n (defined(__CUDA_ARCH_FEAT_SM100_ALL) || defined(__CUDA_ARCH_FEAT_SM103_ALL) || \\\n defined(__CUDA_ARCH_FEAT_SM107_ALL))\n#define FLASHINFER_MAMBA_HAS_CVT_RS 1\n#else\n#define FLASHINFER_MAMBA_HAS_CVT_RS 0\n#endif\n\n// =============================================================================\n// Stochastic rounding: fp32 → fp16\n// =============================================================================\n\n// Software stochastic rounding: convert one fp32 value to fp16 using 13 random bits.\n// Adds random noise at the sub-fp16-mantissa position, then truncates.\n// rand13: 13-bit random value in bits [12:0].\n__device__ __forceinline__ uint16_t cvt_rs_f16_sw(float x, uint32_t rand13) {\n uint32_t bits = __float_as_uint(x);\n uint32_t sign = bits & 0x80000000u;\n uint32_t abs_bits = bits & 0x7FFFFFFFu;\n\n // fp32 has 23 mantissa bits, fp16 has 10. The 13 LSBs are the remainder.\n // Add 13-bit random noise at bits [12:0]. Carry into bit 13 → round up.\n abs_bits += (rand13 & 0x1FFFu);\n\n // Convert to fp16 by truncation.\n uint32_t f32_exp = (abs_bits >> 23) & 0xFFu;\n uint32_t f32_mantissa = abs_bits & 0x7FFFFFu;\n\n uint16_t f16_bits;\n if (f32_exp == 0xFF) {\n f16_bits = (f32_mantissa != 0) ? 0x7E00u : 0x7C00u; // NaN or Inf\n } else if (f32_exp > 142) { // 127 + 15 = 142 → overflow to Inf\n f16_bits = 0x7C00u;\n } else if (f32_exp < 113) { // 127 - 14 = 113 → underflow to zero\n f16_bits = 0;\n } else {\n uint16_t f16_exp = static_cast<uint16_t>(f32_exp - 112); // rebias: 127→15\n uint16_t f16_mantissa = static_cast<uint16_t>(f32_mantissa >> 13);\n f16_bits = (f16_exp << 10) | f16_mantissa;\n }\n\n return static_cast<uint16_t>(sign >> 16) | f16_bits;\n}\n\n// Forward declaration (defined below, after cvt_rs_f16x2_f32).\n__device__ __forceinline__ uint32_t cvt_rs_f16x2_f32(float a, float b, uint32_t rbits);\n\n// Stochastic rounding: convert one fp32 value to fp16 using 13 random bits.\n// On sm_100a/sm_103a/sm_107a: uses PTX cvt.rs.f16x2.f32 with a dummy zero second input.\n// On other archs: software emulation.\n__device__ __forceinline__ __half cvt_rs_f16_f32(float x, uint32_t rand13) {\n#if FLASHINFER_MAMBA_HAS_CVT_RS\n // Pack rand13 into rbits[12:0] (for PTX operand b → low half → our x).\n // High half gets zero noise for the dummy input.\n uint32_t rbits = rand13 & 0x1FFFu;\n uint32_t packed = cvt_rs_f16x2_f32(x, 0.0f, rbits);\n return __ushort_as_half(static_cast<uint16_t>(packed & 0xFFFFu));\n#else\n return __ushort_as_half(cvt_rs_f16_sw(x, rand13));\n#endif\n}\n\n// Stochastic rounding: convert two fp32 values to packed fp16x2 using random bits.\n// On sm_100a/sm_103a/sm_107a: uses PTX cvt.rs.f16x2.f32 instruction.\n// On other archs: software emulation matching the hardware behavior.\n//\n// rbits layout (from PTX docs):\n// bits [28:16] = 13 random bits for PTX operand \"a\" (→ d[31:16], high half)\n// bits [12:0] = 13 random bits for PTX operand \"b\" (→ d[15:0], low half)\n// bits [31:29] and [15:13] = unused (zero)\n// from: https://docs.nvidia.com/cuda/parallel-thread-execution/#cvt-rs-rbits-layout-f16\n//\n// Our asm maps: %1→C++ a→PTX b→d[15:0], %2→C++ b→PTX a→d[31:16]\n// So: C++ a uses rbits[12:0], C++ b uses rbits[28:16].\n__device__ __forceinline__ uint32_t cvt_rs_f16x2_f32(float a, float b, uint32_t rbits) {\n#if FLASHINFER_MAMBA_HAS_CVT_RS\n uint32_t packed;\n asm(\"cvt.rs.f16x2.f32 %0, %2, %1, %3;\"\n : \"=r\"(packed)\n : \"r\"(__float_as_uint(a)), \"r\"(__float_as_uint(b)), \"r\"(rbits));\n return packed;\n#else\n uint32_t rand_a = rbits & 0x1FFFu; // bits [12:0] → C++ a (PTX b → low half)\n uint32_t rand_b = (rbits >> 16) & 0x1FFFu; // bits [28:16] → C++ b (PTX a → high half)\n uint16_t a_fp16 = __half_as_ushort(cvt_rs_f16_f32(a, rand_a));\n uint16_t b_fp16 = __half_as_ushort(cvt_rs_f16_f32(b, rand_b));\n return static_cast<uint32_t>(a_fp16) | (static_cast<uint32_t>(b_fp16) << 16);\n#endif\n}\n\n// Stochastic rounding store: generates Philox random bits and converts fp32 → fp16 in one call.\n// PHILOX_ROUNDS: number of Philox rounds (compile-time), must be > 0.\n// seed: Philox seed (from params.rand_seed).\n// offset: unique per-element offset (e.g. d * DSTATE + i) for deterministic randomness.\ntemplate <int PHILOX_ROUNDS>\ninline __device__ void convertSRAndStore(__half* output, float input, int64_t seed,\n uint32_t offset) {\n uint32_t rand = philox_randint<PHILOX_ROUNDS>(seed, offset);\n *output = cvt_rs_f16_f32(input, rand & 0x1FFFu);\n}\n\n// =============================================================================\n// Stochastic rounding: fp32 → fp8 (e4m3)\n// =============================================================================\n\n// Bit-reverse 16 bits. HW gives both elements of a pair 16 bits of independent\n// SR randomness while consuming a single 16-bit chunk per pair: one element uses\n// the chunk straight, the other uses bitrev16 of it. Two bitrev16'd halves of a\n// uniformly random 16-bit value remain uniformly distributed and are statistically\n// independent, so each element gets full 16-bit unbiased SR while sharing one\n// 16-bit register with its pair-mate.\n//\n// Implementation: PTX `brev.b32` (CUDA intrinsic `__brev`) is a single-ALU-op\n// 32-bit reverse; we right-shift by 16 to land the 16 LSBs of input in the 16\n// LSBs of output. Total: 2 SASS instructions (brev + shf/shr), vs the prior\n// software 4-step mask/shift/OR chain (~12-16 inst).\n__device__ __forceinline__ uint32_t bitrev16(uint32_t b) { return __brev(b) >> 16; }\n\n// Software stochastic rounding: convert one fp32 value to e4m3 (FN, satfinite) using 16 random\n// bits.\n//\n// Algorithm: place `rand16` at the top of the discarded mantissa range, then truncate.\n// shift_truncate = 20 for normal binade (unbiased >= -6)\n// = 14 - unbiased for subnormal/underflow\n// contribution = rand16 << (shift_truncate - 16)\n// total = mant24 + contribution (in uint64 to avoid overflow)\n// int_part = total >> shift_truncate\n// Then re-encode int_part as e4m3, handling subnormal→normal transitions and saturation.\n//\n// Saturation (satfinite):\n// |x| > 448 → ±448 (max finite e4m3 = 0x7E)\n// ±Inf → ±448\n// NaN → canonical NaN with sign preserved (S|1111|111 = 0x7F or 0xFF)\n//\n// Verified bitwise against HW (cvt.rs.satfinite.e4m3x4.f32 on sm_100a) across 22528\n// inputs spanning subnormal, normal, and saturation regions during the SR\n// reverse-engineering effort — see .plans/e4m3_stochastic_rounding.md.\n__device__ __forceinline__ uint8_t cvt_rs_e4m3_sw(float x, uint32_t rand16) {\n uint32_t bits = __float_as_uint(x);\n uint32_t sign = (bits >> 31) & 1u;\n uint32_t abs_bits = bits & 0x7FFFFFFFu;\n uint32_t f32_exp = (abs_bits >> 23) & 0xFFu;\n uint32_t f32_mant = abs_bits & 0x7FFFFFu;\n\n // NaN / Inf\n if (f32_exp == 0xFFu) {\n if (f32_mant != 0) {\n return static_cast<uint8_t>(0x7Fu | (sign << 7)); // canonical e4m3 NaN\n } else {\n return static_cast<uint8_t>(0x7Eu | (sign << 7)); // Inf → ±max finite\n }\n }\n\n // fp32 zero / denormal → e4m3 zero (with sign).\n if (f32_exp == 0u) {\n return static_cast<uint8_t>(sign << 7);\n }\n\n int unbiased = static_cast<int>(f32_exp) - 127;\n uint64_t mant24 = 0x800000u | f32_mant; // implicit-1 + mantissa, 24-bit\n int shift_truncate = (unbiased >= -6) ? 20 : (14 - unbiased);\n int rand_shift = shift_truncate - 16;\n uint64_t rand_contrib;\n if (rand_shift < 0) {\n // Defensive: shift_truncate < 16 shouldn't happen for valid normal/subnormal e4m3.\n rand_contrib = static_cast<uint64_t>(rand16 & 0xFFFFu) >> (-rand_shift);\n } else if (rand_shift < 56) {\n rand_contrib = static_cast<uint64_t>(rand16 & 0xFFFFu) << rand_shift;\n } else {\n rand_contrib = 0;\n }\n uint64_t total = mant24 + rand_contrib;\n // Guard the shift: shift_truncate reaches 140 for tiny-normal fp32\n // (unbiased < -49), which is UB for a uint64_t shift. Mathematically the\n // result is 0 there (the value is far below e4m3's smallest subnormal),\n // so flush to int_part = 0. The downstream subnormal branch rounds it to ±0.\n uint32_t int_part = (shift_truncate >= 64) ? 0u : static_cast<uint32_t>(total >> shift_truncate);\n\n if (unbiased >= -6) {\n // Started in normal binade. int_part ∈ [8, 15] normally; can overflow to 16+ if rand\n // bumped the exponent.\n int e4m3_exp = unbiased + 7;\n while (int_part >= 16u) {\n int_part >>= 1;\n e4m3_exp += 1;\n }\n if (e4m3_exp > 15 || (e4m3_exp == 15 && (int_part & 0x7u) == 7u)) {\n return static_cast<uint8_t>(0x7Eu | (sign << 7));\n }\n return static_cast<uint8_t>((sign << 7) | (e4m3_exp << 3) | (int_part & 0x7u));\n } else {\n // Started in subnormal/underflow. int_part:\n // 0 → zero\n // 1..7 → subnormal e4m3\n // 8..15 → smallest normal binade (e4m3_exp = 1)\n // 16+ → higher normal binades (rare; only if rand pushed up multiple binades)\n if (int_part == 0u) {\n return static_cast<uint8_t>(sign << 7);\n }\n if (int_part <= 7u) {\n return static_cast<uint8_t>((sign << 7) | int_part);\n }\n int e4m3_exp = 1;\n while (int_part >= 16u) {\n int_part >>= 1;\n e4m3_exp += 1;\n }\n if (e4m3_exp > 15 || (e4m3_exp == 15 && (int_part & 0x7u) == 7u)) {\n return static_cast<uint8_t>(0x7Eu | (sign << 7));\n }\n return static_cast<uint8_t>((sign << 7) | (e4m3_exp << 3) | (int_part & 0x7u));\n }\n}\n\n// Stochastic rounding: convert four fp32 values to packed fp8x4 e4m3 using random bits.\n// On sm_100a+: uses PTX cvt.rs.satfinite.e4m3x4.f32 (combined stochastic-round + saturate).\n// On other archs: software fallback via cvt_rs_e4m3_sw.\n//\n// Output layout (low byte first):\n// packed[ 7: 0] = e4m3(a)\n// packed[15: 8] = e4m3(b)\n// packed[23:16] = e4m3(c)\n// packed[31:24] = e4m3(d)\n//\n// rbits layout (per PTX docs + empirical HW oracle, see .plans/e4m3_stochastic_rounding.md):\n// bits [31:16] = pair rbits for PTX operands a/b (high two outputs)\n// bits [15: 0] = pair rbits for PTX operands e/f (low two outputs)\n// Each PAIR shares its 16-bit chunk: HW uses the chunk straight for the \"even\"\n// PTX operand (b, f → low byte of pair output) and bitrev16 of the chunk for\n// the \"odd\" operand (a, e → high byte of pair output). Both elements get the\n// full 16 bits of independent SR randomness this way.\n// our `a` (PTX f, → byte 0) uses rbits[15: 0]\n// our `b` (PTX e, → byte 1) uses bitrev16(rbits[15: 0])\n// our `c` (PTX b, → byte 2) uses rbits[31:16]\n// our `d` (PTX a, → byte 3) uses bitrev16(rbits[31:16])\n//\n// PTX syntax `cvt.rs.satfinite.e4m3x4.f32 d, {a3, a2, a1, a0}, rbits` writes\n// e4m3(a_i) into byte i of d. We want byte 0 = e4m3(a), so the source-vector\n// ordering is {d, c, b, a} = {%4, %3, %2, %1}. See PTX ISA:\n// https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt\n__device__ __forceinline__ uint32_t cvt_rs_e4m3x4_f32(float a, float b, float c, float d,\n uint32_t rbits) {\n#if FLASHINFER_MAMBA_HAS_CVT_RS\n uint32_t packed;\n asm(\"cvt.rs.satfinite.e4m3x4.f32 %0, {%4, %3, %2, %1}, %5;\"\n : \"=r\"(packed)\n : \"r\"(__float_as_uint(a)), \"r\"(__float_as_uint(b)), \"r\"(__float_as_uint(c)),\n \"r\"(__float_as_uint(d)), \"r\"(rbits));\n return packed;\n#else\n uint32_t low_chunk = rbits & 0xFFFFu;\n uint32_t high_chunk = (rbits >> 16) & 0xFFFFu;\n uint8_t pa = cvt_rs_e4m3_sw(a, low_chunk); // PTX f → byte 0\n uint8_t pb = cvt_rs_e4m3_sw(b, bitrev16(low_chunk)); // PTX e → byte 1\n uint8_t pc = cvt_rs_e4m3_sw(c, high_chunk); // PTX b → byte 2\n uint8_t pd = cvt_rs_e4m3_sw(d, bitrev16(high_chunk)); // PTX a → byte 3\n return static_cast<uint32_t>(pa) | (static_cast<uint32_t>(pb) << 8) |\n (static_cast<uint32_t>(pc) << 16) | (static_cast<uint32_t>(pd) << 24);\n#endif\n}\n\n// =============================================================================\n// Round-to-nearest-even + saturate: fp32 → int8\n// =============================================================================\n\n// cvt.rni.sat.s8.f32: single PTX instruction on sm_80+, replaces\n// the F2I.S32 + VIMNMX(min 127) + VIMNMX(max -127) chain.\n// Saturates to [-128, 127]. Callers using encode_scale = 127/amax\n// guarantee |input| ≤ 127.0, so -128 is never produced.\n__device__ __forceinline__ int8_t cvt_rni_sat_s8(float x) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800\n int32_t result;\n asm(\"cvt.rni.sat.s8.f32 %0, %1;\" : \"=r\"(result) : \"f\"(x));\n return static_cast<int8_t>(result);\n#else\n return static_cast<int8_t>(max(-128, min(127, __float2int_rn(x))));\n#endif\n}\n\n// =============================================================================\n// Stochastic rounding + saturate: fp32 → int8\n// =============================================================================\n\n// Software SR for int8: add uniform noise in [0, 1) then floor.\n// Matches Triton's `floor(scaled_value + rand01)` where\n// `rand01 = (rand & 0x00FFFFFF) * (1.0 / (1 << 24))`.\n// Saturates to [-127, 127] (symmetric, matching encode_scale = 127/amax).\n__device__ __forceinline__ int8_t cvt_rs_sat_s8(float x, uint32_t rand_bits) {\n float const rand01 =\n static_cast<float>(rand_bits & 0x00FFFFFFu) * (1.0f / static_cast<float>(1 << 24));\n // `__float2int_rd` (round toward -infinity) fuses `floorf` + `__float2int_rz`\n // into a single `cvt.rmi.s32.f32` SASS instruction, saving one FRND per call.\n int32_t const clamped = max(-127, min(127, __float2int_rd(x + rand01)));\n return static_cast<int8_t>(clamped);\n}\n\n// Stochastic rounding: convert four fp32 values to packed s8x4 using a single\n// 32-bit random integer. Analogous to cvt_rs_e4m3x4_f32: 16-bit chunks are\n// reused via bitrev16 so each output gets 16 bits of independent randomness\n// while consuming only one shared 16-bit chunk per pair (two bitrev16'd halves\n// of a uniform 16-bit value remain uniformly distributed and statistically\n// independent).\n//\n// 16-bit entropy per element is far more than int8 SR requires: the rounding\n// decision compares against a fractional residual with at most ~7 bits of\n// meaningful precision for int8, so no quality loss vs the 24-bit scalar path.\n//\n// Amortization: 1 random u32 → 4 SR int8s. A single Philox call (4 u32s)\n// covers 16 int8 conversions, a 4× reduction in PRNG cost vs the scalar\n// cvt_rs_sat_s8 path.\n__device__ __forceinline__ uint32_t cvt_rs_sat_s8x4_f32(float a, float b, float c, float d,\n uint32_t rbits) {\n uint32_t const low_chunk = rbits & 0xFFFFu;\n uint32_t const high_chunk = (rbits >> 16) & 0xFFFFu;\n constexpr float kInv16 = 1.0f / static_cast<float>(1u << 16);\n\n float const r_a = static_cast<float>(low_chunk) * kInv16;\n float const r_b = static_cast<float>(bitrev16(low_chunk)) * kInv16;\n float const r_c = static_cast<float>(high_chunk) * kInv16;\n float const r_d = static_cast<float>(bitrev16(high_chunk)) * kInv16;\n\n // `__float2int_rd` (round toward -infinity) emits a single `cvt.rmi.s32.f32`\n // SASS op, fusing the `floorf` + `__float2int_rz` chain into one instruction.\n int32_t const pa = max(-127, min(127, __float2int_rd(a + r_a)));\n int32_t const pb = max(-127, min(127, __float2int_rd(b + r_b)));\n int32_t const pc = max(-127, min(127, __float2int_rd(c + r_c)));\n int32_t const pd = max(-127, min(127, __float2int_rd(d + r_d)));\n\n return (static_cast<uint32_t>(pa) & 0xFFu) | ((static_cast<uint32_t>(pb) & 0xFFu) << 8) |\n ((static_cast<uint32_t>(pc) & 0xFFu) << 16) | ((static_cast<uint32_t>(pd) & 0xFFu) << 24);\n}\n\n} // namespace flashinfer::mamba::conversion\n"},"diff":{"kind":"string","value":"--- include/flashinfer/mamba/conversion.cuh\n+++ include/flashinfer/mamba/conversion.cuh\n@@ -158,10 +158,10 @@\n }\n \n // Hardware `cvt.rs.*` (stochastic-rounding convert) is available ONLY on the\n-// datacenter Blackwell \"a\" targets that actually carry the `.rs` PTX feature:\n-// sm_100a (B200) and sm_103a (B300). There is NO generic CUDA feature macro for\n-// it — `__CUDA_ARCH_SPECIFIC__` is too broad (sm_120a defines it but ptxas\n-// rejects `.rs`), so the arches are enumerated here in ONE place.\n+// datacenter Blackwell and Rubin \"a\" targets that carry the `.rs` PTX feature:\n+// sm_100a (B200), sm_103a (B300), and sm_107a (Rubin). There is NO generic CUDA\n+// feature macro for it — `__CUDA_ARCH_SPECIFIC__` is too broad (sm_120a defines\n+// it but ptxas rejects `.rs`), so the arches are enumerated here in ONE place.\n //\n // The trap this guard exists to avoid: B300 is sm_103a and does NOT define\n // `__CUDA_ARCH_FEAT_SM100_ALL`, so a SM100-only guard silently compiled the\n@@ -218,7 +218,7 @@\n __device__ __forceinline__ uint32_t cvt_rs_f16x2_f32(float a, float b, uint32_t rbits);\n \n // Stochastic rounding: convert one fp32 value to fp16 using 13 random bits.\n-// On sm_100a+: uses PTX cvt.rs.f16x2.f32 with a dummy zero second input.\n+// On sm_100a/sm_103a/sm_107a: uses PTX cvt.rs.f16x2.f32 with a dummy zero second input.\n // On other archs: software emulation.\n __device__ __forceinline__ __half cvt_rs_f16_f32(float x, uint32_t rand13) {\n #if FLASHINFER_MAMBA_HAS_CVT_RS\n@@ -233,7 +233,7 @@\n }\n \n // Stochastic rounding: convert two fp32 values to packed fp16x2 using random bits.\n-// On sm_100a+: uses PTX cvt.rs.f16x2.f32 instruction.\n+// On sm_100a/sm_103a/sm_107a: uses PTX cvt.rs.f16x2.f32 instruction.\n // On other archs: software emulation matching the hardware behavior.\n //\n // rbits layout (from PTX docs):"},"lines_added":{"kind":"number","value":6,"string":"6"},"lines_removed":{"kind":"number","value":6,"string":"6"},"files_in_commit":{"kind":"number","value":2,"string":"2"},"models_mentioned":{"kind":"list like","value":["mamba","nemotron"],"string":"[\n \"mamba\",\n \"nemotron\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["SM100","SM103","SM107"],"string":"[\n \"SM100\",\n \"SM103\",\n \"SM107\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["1.413×","1.547×","1.573×"],"string":"[\n \"1.413×\",\n \"1.547×\",\n \"1.573×\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (include/flashinfer/mamba/conversion.cuh).\n\nGoal: perf(mamba): enable native SM107 stochastic rounding\nTarget hardware: SM100, SM103, SM107\nTarget models: mamba, nemotron\n\nCurrent file:\n```cuda\n#pragma once\n#include <cuda.h>\n#include <cuda_fp16.h>\n#include <cuda_fp8.h>\n#ifdef FLASHINFER_ENABLE_BF16\n#include <cuda_bf16.h>\n#endif\n\nnamespace flashinfer::mamba::conversion {\n\ninline __device__ float toFloat(float f) { return f; }\n\ninline __device__ float toFloat(__half h) { return __half2float(h); }\n\n#ifdef FLASHINFER_ENABLE_BF16\ninline __device__ float toFloat(__nv_bfloat16 val) { return __bfloat162float(val); }\n#endif\n\n// No accuracy loss: int8_t / int16_t range fits exactly in float32 (24-bit\n// mantissa represents all integers up to 2^24 = 16M exactly).\ninline __device__ float toFloat(int8_t val) { return static_cast<float>(val); }\ninline __device__ float toFloat(int16_t val) { return static_cast<float>(val); }\n\n// fp8 e4m3 → fp32. Goes via __half (cuda_fp8 library has the implicit\n// conversion that compiles to `cvt.rn.f16.e4m3` PTX on sm_89+), then\n// __half2float for the final step. No direct fp8→fp32 PTX op exists.\ninline __device__ float toFloat(__nv_fp8_e4m3 val) {\n return __half2float(static_cast<__half>(val));\n}\n\n// Packed 2-element conversion: convert a packed pair to float2.\n// Uses native packed intrinsics for bf16/fp16 (fewer PRMT/SHF instructions).\ninline __device__ float2 toFloat2(float2 packed) { return packed; }\n\ninline __device__ float2 toFloat2(__half2 packed) { return __half22float2(packed); }\n\n// Pointer-based overloads: read two consecutive elements and convert to float2.\n// Dispatches to the packed intrinsic for bf16/fp16 via the overloads above.\ninline __device__ float2 toFloat2(float const* ptr) { return {ptr[0], ptr[1]}; }\n\ninline __device__ float2 toFloat2(__half const* ptr) {\n return toFloat2(*reinterpret_cast<__half2 const*>(ptr));\n}\n\n#ifdef FLASHINFER_ENABLE_BF16\n// inline __device__ float2 toFloat2(__nv_bfloat162 packed) { return __bfloat1622float2(packed); }\n\ninline __device__ float2 toFloat2(__nv_bfloat162 packed) {\n // bf16 is the upper 16 bits of f32 — shift/mask is cheaper than PRMT byte permutation.\n // NOTE: this ignores denormals\n uint32_t bits = reinterpret_cast<uint32_t const&>(packed);\n float2 out;\n out.x = __uint_as_float(bits << 16); // low bf16 → upper 16 bits of f32\n out.y = __uint_as_float(bits & 0xFFFF0000u); // high bf16 already in upper 16 bits\n return out;\n}\n\ninline __device__ float2 toFloat2(__nv_bfloat16 const* ptr) {\n return toFloat2(*reinterpret_cast<__nv_bfloat162 const*>(ptr));\n}\n\n// Paired f32 → bf16 conversion: pack two f32 values into __nv_bfloat162.\n// Uses native cvt.rn.bf16x2.f32 — single instruction, round-to-nearest-even.\ninline __device__ __nv_bfloat162 fromFloat2(float2 val) {\n uint32_t result;\n asm(\"cvt.rn.bf16x2.f32 %0, %1, %2;\\n\" : \"=r\"(result) : \"f\"(val.y), \"f\"(val.x));\n return reinterpret_cast<__nv_bfloat162 const&>(result);\n}\n\n#endif\n\ninline __device__ float2 toFloat2(int8_t const* ptr) { return {toFloat(ptr[0]), toFloat(ptr[1])}; }\ninline __device__ float2 toFloat2(int16_t const* ptr) { return {toFloat(ptr[0]), toFloat(ptr[1])}; }\n\ninline __device__ void convertAndStore(float* output, float input) { *output = input; }\n\ninline __device__ void convertAndStore(__half* output, float input) {\n *output = __float2half(input);\n}\n\n#ifdef FLASHINFER_ENABLE_BF16\ninline __device__ void convertAndStore(__nv_bfloat16* output, float input) {\n *output = __float2bfloat16(input);\n}\n#endif\n\ninline __device__ void convertAndStore(int16_t* output, float input) {\n // Symmetric clip: [-max, max] (not [-max-1, max]) so that negation is safe.\n // Matches Triton reference which clips to [-32767, 32767] before storing.\n constexpr float int16_max = static_cast<float>(std::numeric_limits<int16_t>::max());\n input = fminf(fmaxf(input, -int16_max), int16_max);\n *output = static_cast<int16_t>(__float2int_rn(input));\n}\n\n// =============================================================================\n// Philox-4x32 PRNG (matches Triton's tl.randint)\n// =============================================================================\n\n// Derive a per-layer Philox seed with the SplitMix64 finalizer (Stafford mix13).\n// Multi-layer kernels use this to derive independent layer streams from one\n// base seed; single-layer kernels receive their layer-specific seed directly.\n__device__ __forceinline__ int64_t layer_philox_seed(int64_t base_seed, int layer) {\n uint64_t z = static_cast<uint64_t>(base_seed) ^ (0x9E3779B97F4A7C15ULL * (uint64_t(layer) + 1));\n z = (z ^ (z >> 30)) * 0xBF58476D1CE4E5B9ULL;\n z = (z ^ (z >> 27)) * 0x94D049BB133111EBULL;\n return static_cast<int64_t>(z ^ (z >> 31));\n}\n\n// Generates four pseudorandom uint32s from (seed, offset) using the Philox-4x32 algorithm.\n// Produces bit-identical output to Triton's tl.randint4x(seed, offset, n_rounds).\n// The offset is int64 and split across Philox c0 (low 32 bits) and c1 (high\n// 32 bits) — matches the i64 path of `randint4x` in triton/language/random.py.\n// Provides 2^64 unique counter values per seed, avoiding collisions in large\n// caches where `cache_slot * stride` exceeds 2^32.\n// All four outputs (c0..c3) are independent and uniformly distributed.\ntemplate <int n_rounds = 10>\n__device__ __forceinline__ void philox_randint4x(int64_t seed, int64_t offset, uint32_t& r0,\n uint32_t& r1, uint32_t& r2, uint32_t& r3) {\n constexpr uint32_t PHILOX_KEY_A = 0x9E3779B9u;\n constexpr uint32_t PHILOX_KEY_B = 0xBB67AE85u;\n constexpr uint32_t PHILOX_ROUND_A = 0xD2511F53u;\n constexpr uint32_t PHILOX_ROUND_B = 0xCD9E8D57u;\n\n uint32_t k0 = static_cast<uint32_t>(static_cast<uint64_t>(seed));\n uint32_t k1 = static_cast<uint32_t>(static_cast<uint64_t>(seed) >> 32);\n uint64_t uoffset = static_cast<uint64_t>(offset);\n uint32_t c0 = static_cast<uint32_t>(uoffset);\n uint32_t c1 = static_cast<uint32_t>(uoffset >> 32);\n uint32_t c2 = 0, c3 = 0;\n\n#pragma unroll\n for (int i = 0; i < n_rounds; i++) {\n uint32_t _c0 = c0, _c2 = c2;\n c0 = __umulhi(PHILOX_ROUND_B, _c2) ^ c1 ^ k0;\n c2 = __umulhi(PHILOX_ROUND_A, _c0) ^ c3 ^ k1;\n c1 = PHILOX_ROUND_B * _c2;\n c3 = PHILOX_ROUND_A * _c0;\n k0 += PHILOX_KEY_A;\n k1 += PHILOX_KEY_B;\n }\n r0 = c0;\n r1 = c1;\n r2 = c2;\n r3 = c3;\n}\n\n// Generates a pseudorandom uint32 from (seed, offset) using the Philox-4x32 algorithm.\n// Produces bit-identical output to Triton's tl.randint(seed, offset, n_rounds).\n// The offset is int64 (low/high split across Philox c0/c1) — see\n// philox_randint4x for the full rationale.\n// NOTE: This discards 3 of the 4 Philox outputs. For better throughput, use\n// philox_randint4x to get all 4 outputs from a single Philox invocation.\ntemplate <int n_rounds = 10>\n__device__ __forceinline__ uint32_t philox_randint(int64_t seed, int64_t offset) {\n uint32_t r0, r1, r2, r3;\n philox_randint4x<n_rounds>(seed, offset, r0, r1, r2, r3);\n return r0;\n}\n\n// Hardware `cvt.rs.*` (stochastic-rounding convert) is available ONLY on the\n// datacenter Blackwell \"a\" targets that actually carry the `.rs` PTX feature:\n// sm_100a (B200) and sm_103a (B300). There is NO generic CUDA feature macro for\n// it — `__CUDA_ARCH_SPECIFIC__` is too broad (sm_120a defines it but ptxas\n// rejects `.rs`), so the arches are enumerated here in ONE place.\n//\n// The trap this guard exists to avoid: B300 is sm_103a and does NOT define\n// `__CUDA_ARCH_FEAT_SM100_ALL`, so a SM100-only guard silently compiled the\n// ~12-instruction software emulation there — measured +99% SR cost at b1024 vs\n// +24% on B200 (2026-07-13). sm_110a / sm_120a lack `.rs` (ptxas errors) → they\n// correctly fall to the software path below. Extend the list only after\n// confirming `cvt.rs.f16x2.f32` assembles for the new arch. sm_107a: verified with\n// the CUDA 13.4 ptxas (sm_110a/sm_120a still reject `.rs`).\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 1000 && \\\n (defined(__CUDA_ARCH_FEAT_SM100_ALL) || defined(__CUDA_ARCH_FEAT_SM103_ALL) || \\\n defined(__CUDA_ARCH_FEAT_SM107_ALL))\n#define FLASHINFER_MAMBA_HAS_CVT_RS 1\n#else\n#define FLASHINFER_MAMBA_HAS_CVT_RS 0\n#endif\n\n// =============================================================================\n// Stochastic rounding: fp32 → fp16\n// =============================================================================\n\n// Software stochastic rounding: convert one fp32 value to fp16 using 13 random bits.\n// Adds random noise at the sub-fp16-mantissa position, then truncates.\n// rand13: 13-bit random value in bits [12:0].\n__device__ __forceinline__ uint16_t cvt_rs_f16_sw(float x, uint32_t rand13) {\n uint32_t bits = __float_as_uint(x);\n uint32_t sign = bits & 0x80000000u;\n uint32_t abs_bits = bits & 0x7FFFFFFFu;\n\n // fp32 has 23 mantissa bits, fp16 has 10. The 13 LSBs are the remainder.\n // Add 13-bit random noise at bits [12:0]. Carry into bit 13 → round up.\n abs_bits += (rand13 & 0x1FFFu);\n\n // Convert to fp16 by truncation.\n uint32_t f32_exp = (abs_bits >> 23) & 0xFFu;\n uint32_t f32_mantissa = abs_bits & 0x7FFFFFu;\n\n uint16_t f16_bits;\n if (f32_exp == 0xFF) {\n f16_bits = (f32_mantissa != 0) ? 0x7E00u : 0x7C00u; // NaN or Inf\n } else if (f32_exp > 142) { // 127 + 15 = 142 → overflow to Inf\n f16_bits = 0x7C00u;\n } else if (f32_exp < 113) { // 127 - 14 = 113 → underflow to zero\n f16_bits = 0;\n } else {\n uint16_t f16_exp = static_cast<uint16_t>(f32_exp - 112); // rebias: 127→15\n uint16_t f16_mantissa = static_cast<uint16_t>(f32_mantissa >> 13);\n f16_bits = (f16_exp << 10) | f16_mantissa;\n }\n\n return static_cast<uint16_t>(sign >> 16) | f16_bits;\n}\n\n// Forward declaration (defined below, after cvt_rs_f16x2_f32).\n__device__ __forceinline__ uint32_t cvt_rs_f16x2_f32(float a, float b, uint32_t rbits);\n\n// Stochastic rounding: convert one fp32 value to fp16 using 13 random bits.\n// On sm_100a+: uses PTX cvt.rs.f16x2.f32 with a dummy zero second input.\n// On other archs: software emulation.\n__device__ __forceinline__ __half cvt_rs_f16_f32(float x, uint32_t rand13) {\n#if FLASHINFER_MAMBA_HAS_CVT_RS\n // Pack rand13 into rbits[12:0] (for PTX operand b → low half → our x).\n // High half gets zero noise for the dummy input.\n uint32_t rbits = rand13 & 0x1FFFu;\n uint32_t packed = cvt_rs_f16x2_f32(x, 0.0f, rbits);\n return __ushort_as_half(static_cast<uint16_t>(packed & 0xFFFFu));\n#else\n return __ushort_as_half(cvt_rs_f16_sw(x, rand13));\n#endif\n}\n\n// Stochastic rounding: convert two fp32 values to packed fp16x2 using random bits.\n// On sm_100a+: uses PTX cvt.rs.f16x2.f32 instruction.\n// On other archs: software emulation matching the hardware behavior.\n//\n// rbits layout (from PTX docs):\n// bits [28:16] = 13 random bits for PTX operand \"a\" (→ d[31:16], high half)\n// bits [12:0] = 13 random bits for PTX operand \"b\" (→ d[15:0], low half)\n// bits [31:29] and [15:13] = unused (zero)\n// from: https://docs.nvidia.com/cuda/parallel-thread-execution/#cvt-rs-rbits-layout-f16\n//\n// Our asm maps: %1→C++ a→PTX b→d[15:0], %2→C++ b→PTX a→d[31:16]\n// So: C++ a uses rbits[12:0], C++ b uses rbits[28:16].\n__device__ __forceinline__ uint32_t cvt_rs_f16x2_f32(float a, float b, uint32_t rbits) {\n#if FLASHINFER_MAMBA_HAS_CVT_RS\n uint32_t packed;\n asm(\"cvt.rs.f16x2.f32 %0, %2, %1, %3;\"\n : \"=r\"(packed)\n : \"r\"(__float_as_uint(a)), \"r\"(__float_as_uint(b)), \"r\"(rbits));\n return packed;\n#else\n uint32_t rand_a = rbits & 0x1FFFu; // bits [12:0] → C++ a (PTX b → low half)\n uint32_t rand_b = (rbits >> 16) & 0x1FFFu; // bits [28:16] → C++ b (PTX a → high half)\n uint16_t a_fp16 = __half_as_ushort(cvt_rs_f16_f32(a, rand_a));\n uint16_t b_fp16 = __half_as_ushort(cvt_rs_f16_f32(b, rand_b));\n return static_cast<uint32_t>(a_fp16) | (static_cast<uint32_t>(b_fp16) << 16);\n#endif\n}\n\n// Stochastic rounding store: generates Philox random bits and converts fp32 → fp16 in one call.\n// PHILOX_ROUNDS: number of Philox rounds (compile-time), must be > 0.\n// seed: Philox seed (from params.rand_seed).\n// offset: unique per-element offset (e.g. d * DSTATE + i) for deterministic randomness.\ntemplate <int PHILOX_ROUNDS>\ninline __device__ void convertSRAndStore(__half* output, float input, int64_t seed,\n uint32_t offset) {\n uint32_t rand = philox_randint<PHILOX_ROUNDS>(seed, offset);\n *output = cvt_rs_f16_f32(input, rand & 0x1FFFu);\n}\n\n// =============================================================================\n// Stochastic rounding: fp32 → fp8 (e4m3)\n// =============================================================================\n\n// Bit-reverse 16 bits. HW gives both elements of a pair 16 bits of independent\n// SR randomness while consuming a single 16-bit chunk per pair: one element uses\n// the chunk straight, the other uses bitrev16 of it. Two bitrev16'd halves of a\n// uniformly random 16-bit value remain uniformly distributed and are statistically\n// independent, so each element gets full 16-bit unbiased SR while sharing one\n// 16-bit register with its pair-mate.\n//\n// Implementation: PTX `brev.b32` (CUDA intrinsic `__brev`) is a single-ALU-op\n// 32-bit reverse; we right-shift by 16 to land the 16 LSBs of input in the 16\n// LSBs of output. Total: 2 SASS instructions (brev + shf/shr), vs the prior\n// software 4-step mask/shift/OR chain (~12-16 inst).\n__device__ __forceinline__ uint32_t bitrev16(uint32_t b) { return __brev(b) >> 16; }\n\n// Software stochastic rounding: convert one fp32 value to e4m3 (FN, satfinite) using 16 random\n// bits.\n//\n// Algorithm: place `rand16` at the top of the discarded mantissa range, then truncate.\n// shift_truncate = 20 for normal binade (unbiased >= -6)\n// = 14 - unbiased for subnormal/underflow\n// contribution = rand16 << (shift_truncate - 16)\n// total = mant24 + contribution (in uint64 to avoid overflow)\n// int_part = total >> shift_truncate\n// Then re-encode int_part as e4m3, handling subnormal→normal transitions and saturation.\n//\n// Saturation (satfinite):\n// |x| > 448 → ±448 (max finite e4m3 = 0x7E)\n// ±Inf → ±448\n// NaN → canonical NaN with sign preserved (S|1111|111 = 0x7F or 0xFF)\n//\n// Verified bitwise against HW (cvt.rs.satfinite.e4m3x4.f32 on sm_100a) across 22528\n// inputs spanning subnormal, normal, and saturation regions during the SR\n// reverse-engineering effort — see .plans/e4m3_stochastic_rounding.md.\n__device__ __forceinline__ uint8_t cvt_rs_e4m3_sw(float x, uint32_t rand16) {\n uint32_t bits = __float_as_uint(x);\n uint32_t sign = (bits >> 31) & 1u;\n uint32_t abs_bits = bits & 0x7FFFFFFFu;\n uint32_t f32_exp = (abs_bits >> 23) & 0xFFu;\n uint32_t f32_mant = abs_bits & 0x7FFFFFu;\n\n // NaN / Inf\n if (f32_exp == 0xFFu) {\n if (f32_mant != 0) {\n return static_cast<uint8_t>(0x7Fu | (sign << 7)); // canonical e4m3 NaN\n } else {\n return static_cast<uint8_t>(0x7Eu | (sign << 7)); // Inf → ±max finite\n }\n }\n\n // fp32 zero / denormal → e4m3 zero (with sign).\n if (f32_exp == 0u) {\n return static_cast<uint8_t>(sign << 7);\n }\n\n int unbiased = static_cast<int>(f32_exp) - 127;\n uint64_t mant24 = 0x800000u | f32_mant; // implicit-1 + mantissa, 24-bit\n int shift_truncate = (unbiased >= -6) ? 20 : (14 - unbiased);\n int rand_shift = shift_truncate - 16;\n uint64_t rand_contrib;\n if (rand_shift < 0) {\n // Defensive: shift_truncate < 16 shouldn't happen for valid normal/subnormal e4m3.\n rand_contrib = static_cast<uint64_t>(rand16 & 0xFFFFu) >> (-rand_shift);\n } else if (rand_shift < 56) {\n rand_contrib = static_cast<uint64_t>(rand16 & 0xFFFFu) << rand_shift;\n } else {\n rand_contrib = 0;\n }\n uint64_t total = mant24 + rand_contrib;\n // Guard the shift: shift_truncate reaches 140 for tiny-normal fp32\n // (unbiased < -49), which is UB for a uint64_t shift. Mathematically the\n // result is 0 there (the value is far below e4m3's smallest subnormal),\n // so flush to int_part = 0. The downstream subnormal branch rounds it to ±0.\n uint32_t int_part = (shift_truncate >= 64) ? 0u : static_cast<uint32_t>(total >> shift_truncate);\n\n if (unbiased >= -6) {\n // Started in normal binade. int_part ∈ [8, 15] normally; can overflow to 16+ if rand\n // bumped the exponent.\n int e4m3_exp = unbiased + 7;\n while (int_part >= 16u) {\n int_part >>= 1;\n e4m3_exp += 1;\n }\n if (e4m3_exp > 15 || (e4m3_exp == 15 && (int_part & 0x7u) == 7u)) {\n return static_cast<uint8_t>(0x7Eu | (sign << 7));\n }\n return static_cast<uint8_t>((sign << 7) | (e4m3_exp << 3) | (int_part & 0x7u));\n } else {\n // Started in subnormal/underflow. int_part:\n // 0 → zero\n // 1..7 → subnormal e4m3\n // 8..15 → smallest normal binade (e4m3_exp = 1)\n // 16+ → higher normal binades (rare; only if rand pushed up multiple binades)\n if (int_part == 0u) {\n return static_cast<uint8_t>(sign << 7);\n }\n if (int_part <= 7u) {\n return static_cast<uint8_t>((sign << 7) | int_part);\n }\n int e4m3_exp = 1;\n while (int_part >= 16u) {\n int_part >>= 1;\n e4m3_exp += 1;\n }\n if (e4m3_exp > 15 || (e4m3_exp == 15 && (int_part & 0x7u) == 7u)) {\n return static_cast<uint8_t>(0x7Eu | (sign << 7));\n }\n return static_cast<uint8_t>((sign << 7) | (e4m3_exp << 3) | (int_part & 0x7u));\n }\n}\n\n// Stochastic rounding: convert four fp32 values to packed fp8x4 e4m3 using random bits.\n// On sm_100a+: uses PTX cvt.rs.satfinite.e4m3x4.f32 (combined stochastic-round + saturate).\n// On other archs: software fallback via cvt_rs_e4m3_sw.\n//\n// Output layout (low byte first):\n// packed[ 7: 0] = e4m3(a)\n// packed[15: 8] = e4m3(b)\n// packed[23:16] = e4m3(c)\n// packed[31:24] = e4m3(d)\n//\n// rbits layout (per PTX docs + empirical HW oracle, see .plans/e4m3_stochastic_rounding.md):\n// bits [31:16] = pair rbits for PTX operands a/b (high two outputs)\n// bits [15: 0] = pair rbits for PTX operands e/f (low two outputs)\n// Each PAIR shares its 16-bit chunk: HW uses the chunk straight for the \"even\"\n// PTX operand (b, f → low byte of pair output) and bitrev16 of the chunk for\n// the \"odd\" operand (a, e → high byte of pair output). Both elements get the\n// full 16 bits of independent SR randomness this way.\n// our `a` (PTX f, → byte 0) uses rbits[15: 0]\n// our `b` (PTX e, → byte 1) uses bitrev16(rbits[15: 0])\n// our `c` (PTX b, → byte 2) uses rbits[31:16]\n// our `d` (PTX a, → byte 3) uses bitrev16(rbits[31:16])\n//\n// PTX syntax `cvt.rs.satfinite.e4m3x4.f32 d, {a3, a2, a1, a0}, rbits` writes\n// e4m3(a_i) into byte i of d. We want byte 0 = e4m3(a), so the source-vector\n// ordering is {d, c, b, a} = {%4, %3, %2, %1}. See PTX ISA:\n// https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt\n__device__ __forceinline__ uint32_t cvt_rs_e4m3x4_f32(float a, float b, float c, float d,\n uint32_t rbits) {\n#if FLASHINFER_MAMBA_HAS_CVT_RS\n uint32_t packed;\n asm(\"cvt.rs.satfinite.e4m3x4.f32 %0, {%4, %3, %2, %1}, %5;\"\n : \"=r\"(packed)\n : \"r\"(__float_as_uint(a)), \"r\"(__float_as_uint(b)), \"r\"(__float_as_uint(c)),\n \"r\"(__float_as_uint(d)), \"r\"(rbits));\n return packed;\n#else\n uint32_t low_chunk = rbits & 0xFFFFu;\n uint32_t high_chunk = (rbits >> 16) & 0xFFFFu;\n uint8_t pa = cvt_rs_e4m3_sw(a, low_chunk); // PTX f → byte 0\n uint8_t pb = cvt_rs_e4m3_sw(b, bitrev16(low_chunk)); // PTX e → byte 1\n uint8_t pc = cvt_rs_e4m3_sw(c, high_chunk); // PTX b → byte 2\n uint8_t pd = cvt_rs_e4m3_sw(d, bitrev16(high_chunk)); // PTX a → byte 3\n return static_cast<uint32_t>(pa) | (static_cast<uint32_t>(pb) << 8) |\n (static_cast<uint32_t>(pc) << 16) | (static_cast<uint32_t>(pd) << 24);\n#endif\n}\n\n// =============================================================================\n// Round-to-nearest-even + saturate: fp32 → int8\n// =============================================================================\n\n// cvt.rni.sat.s8.f32: single PTX instruction on sm_80+, replaces\n// the F2I.S32 + VIMNMX(min 127) + VIMNMX(max -127) chain.\n// Saturates to [-128, 127]. Callers using encode_scale = 127/amax\n// guarantee |input| ≤ 127.0, so -128 is never produced.\n__device__ __forceinline__ int8_t cvt_rni_sat_s8(float x) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800\n int32_t result;\n asm(\"cvt.rni.sat.s8.f32 %0, %1;\" : \"=r\"(result) : \"f\"(x));\n return static_cast<int8_t>(result);\n#else\n return static_cast<int8_t>(max(-128, min(127, __float2int_rn(x))));\n#endif\n}\n\n// =============================================================================\n// Stochastic rounding + saturate: fp32 → int8\n// =============================================================================\n\n// Software SR for int8: add uniform noise in [0, 1) then floor.\n// Matches Triton's `floor(scaled_value + rand01)` where\n// `rand01 = (rand & 0x00FFFFFF) * (1.0 / (1 << 24))`.\n// Saturates to [-127, 127] (symmetric, matching encode_scale = 127/amax).\n__device__ __forceinline__ int8_t cvt_rs_sat_s8(float x, uint32_t rand_bits) {\n float const rand01 =\n static_cast<float>(rand_bits & 0x00FFFFFFu) * (1.0f / static_cast<float>(1 << 24));\n // `__float2int_rd` (round toward -infinity) fuses `floorf` + `__float2int_rz`\n // into a single `cvt.rmi.s32.f32` SASS instruction, saving one FRND per call.\n int32_t const clamped = max(-127, min(127, __float2int_rd(x + rand01)));\n return static_cast<int8_t>(clamped);\n}\n\n// Stochastic rounding: convert four fp32 values to packed s8x4 using a single\n// 32-bit random integer. Analogous to cvt_rs_e4m3x4_f32: 16-bit chunks are\n// reused via bitrev16 so each output gets 16 bits of independent randomness\n// while consuming only one shared 16-bit chunk per pair (two bitrev16'd halves\n// of a uniform 16-bit value remain uniformly distributed and statistically\n// independent).\n//\n// 16-bit entropy per element is far more than int8 SR requires: the rounding\n// decision compares against a fractional residual with at most ~7 bits of\n// meaningful precision for int8, so no quality loss vs the 24-bit scalar path.\n//\n// Amortization: 1 random u32 → 4 SR int8s. A single Philox call (4 u32s)\n// covers 16 int8 conversions, a 4× reduction in PRNG cost vs the scalar\n// cvt_rs_sat_s8 path.\n__device__ __forceinline__ uint32_t cvt_rs_sat_s8x4_f32(float a, float b, float c, float d,\n uint32_t rbits) {\n uint32_t const low_chunk = rbits & 0xFFFFu;\n uint32_t const high_chunk = (rbits >> 16) & 0xFFFFu;\n constexpr float kInv16 = 1.0f / static_cast<float>(1u << 16);\n\n float const r_a = static_cast<float>(low_chunk) * kInv16;\n float const r_b = static_cast<float>(bitrev16(low_chunk)) * kInv16;\n float const r_c = static_cast<float>(high_chunk) * kInv16;\n float const r_d = static_cast<float>(bitrev16(high_chunk)) * kInv16;\n\n // `__float2int_rd` (round toward -infinity) emits a single `cvt.rmi.s32.f32`\n // SASS op, fusing the `floorf` + `__float2int_rz` chain into one instruction.\n int32_t const pa = max(-127, min(127, __float2int_rd(a + r_a)));\n int32_t const pb = max(-127, min(127, __float2int_rd(b + r_b)));\n int32_t const pc = max(-127, min(127, __float2int_rd(c + r_c)));\n int32_t const pd = max(-127, min(127, __float2int_rd(d + r_d)));\n\n return (static_cast<uint32_t>(pa) & 0xFFu) | ((static_cast<uint32_t>(pb) & 0xFFu) << 8) |\n ((static_cast<uint32_t>(pc) & 0xFFu) << 16) | ((static_cast<uint32_t>(pd) & 0xFFu) << 24);\n}\n\n} // namespace flashinfer::mamba::conversion\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"<!-- .github/pull_request_template.md -->\n\n## 📌 Description\n\nEnable native stochastic rounding on Rubin (SM107a) for Mamba state updates. The existing architecture guard omitted SM107a, causing Rubin to use software conversion. This PR adds `__CUDA_ARCH_FEAT_SM107_ALL` to `FLASHINFER_MAMBA_HAS_CVT_RS`, adds compute capability `(10, 7)` to `is_cvt_rs_supported()`, and updates the hardware-test descriptions and skip messages. The shared guard enables the existing FP16 and E4M3 native conversion paths.\n\n### Performance\n\nCompared using CUDA 13.4, PyTorch `2.14.0a0+4fdf77b940.nv26.08`, and Triton 3.8.0.\n\nWorkload: Nemotron 3 Ultra TP1, 256 heads, head dimension 64, state dimension 128, and 8 groups. Horizontal single-token update (`T=1`), FP16 state, BF16 inputs/output, FP32 A, seeded stochastic rounding with `philox_rounds=5`.\n\n| Batch | Before (µs) | After (µs) | Paired speedup | Latency reduction |\n|---:|---:|---:|---:|---:|\n| 1 | 10.848 | 7.648 | 1.413× | 29.21% |\n| 64 | 132.768 | 85.808 | 1.547× | 35.37% |\n| 256 | 502.880 | 319.760 | 1.573× | 36.41% |\n\nEach measurement used 20 warmups and 100 eager CUDA-event samples; state restoration and a 2×L2 flush occurred outside timing. Each revision used a fresh JIT cache, with compilation outside timing. CUDA graphs and clock locks were disabled.\n\nLatencies are pooled medians over 200 samples per revision/batch. Paired speedup is the geometric mean of the two within-round median ratios; latency reduction is `1 − 1 / paired_speedup`. Consequently, the pooled latency ratio may differ slightly from the paired speedup.\n\nThese are SSU kernel/API timings. The two rounds do not establish statistical significance or measure full-model serving throughput.\n\n## 🔍 Related Issues\n\nNone linked.\n\n## 🚀 Pull Request Checklist\n\nThank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.\n\n### ✅ Pre-commit Checks\n\n- [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method).\n- [x] I have installed the hooks with `pre-commit install`.\n- [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues.\n\n## 🧪 Tests\n\n- [x] Tests have been added or updated as needed.\n- [x] All tests are passing (`unittest`, etc.).\n\n\n## Reviewer Notes\n\nThe capability helper and CUDA guard should remain synchronized. The shared guard affects both FP16 and E4M3 conversion, while the performance results above cover FP16 horizontal single-token updates only.\n\nInternal benchmark provenance: `login-hecate`, run directory `/lustre/fsw/coreai_nvfm_llm/rgarnett/lights-out-inference/runs/flashinfer-ssu-5f29e0eb-before-after-20260916-125122/`. The directory contains `report.md`, the benchmark scripts, per-round CSVs, raw timing samples, numerical errors, loaded binary hashes, and environment metadata. Slurm job `595820` completed successfully. These artifacts require internal access.\n\nGPU test provenance: Slurm job `595895` completed with exit `0:0` in 17m59s. Full pytest logs, JUnit XML, per-case outcomes and environment metadata are under `/lustre/fsw/coreai_nvfm_llm/rgarnett/lights-out-inference/runs/flashinfer-sm107-tests-cc5a53a6-20260916-132253/` on `login-hecate`.\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n## Summary by CodeRabbit\n\n* **New Features**\n * Added hardware-accelerated stochastic rounding support for SM107 (Rubin) GPUs, alongside SM100 and SM103.\n * Updated FP16 and FP8 conversion support to recognize SM107-compatible hardware.\n* **Bug Fixes**\n * Improved capability detection so supported architectures are identified consistently.\n* **Tests**\n * Updated hardware compatibility checks and unsupported-device messages to include SM107 GPUs and the supported architecture list.\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": null, \"model\": \"Nemotron 3 Ultra TP1\", \"shape\": \"heads=256,head_dim=64,state_dim=128,groups=8,T=1\", \"batch_size\": 1, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 10.848, \"optimized\": 7.648, \"stated_speedup\": 1.413, \"speedup\": 1.4184}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"Nemotron 3 Ultra TP1\", \"shape\": \"heads=256,head_dim=64,state_dim=128,groups=8,T=1\", \"batch_size\": 64, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 132.768, \"optimized\": 85.808, \"stated_speedup\": 1.547, \"speedup\": 1.5473}, {\"scope\": \"kernel\", \"hardware\": null, \"model\": \"Nemotron 3 Ultra TP1\", \"shape\": \"heads=256,head_dim=64,state_dim=128,groups=8,T=1\", \"batch_size\": 256, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 502.88, \"optimized\": 319.76, \"stated_speedup\": 1.573, \"speedup\": 1.5727}]"},"kernel_speedup":{"kind":"number","value":1.5473,"string":"1.5473"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":998,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"911cb09d0981c38d15b775b7820e4a76c72fcfa0"},"date":{"kind":"string","value":"2026-10-04T10:47:29-07:00"},"pr_number":{"kind":"number","value":6045,"string":"6,045"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/6045"},"title":{"kind":"string","value":"perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative) (#6045)"},"message":{"kind":"string","value":"perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative) (#6045)\n\n## Summary\n\nRounds 7-17 of the DSv4 sparse-MLA Cake backend (`backend=\"cake\"`, SM100\n+ SM103) as one cumulative change on the #5920 layout (per-variant\nbindings taking their checks from `tvm_ffi_utils.h`, shared sources\nunder `common/`, `run_sequence`, the host's direct variant launches).\nMain carries round 6 (#5700) for this family; the eight per-round PRs\nstacked on it (#5728, #5742, #5845, #5854, #5879, #5946, #5973, #5999)\nand the held round 15-17 fork branches were closed in favour of this PR.\nPrograms: whole-family regeneration of the `cake_dsv4` sources from Cake\n!1037's tree (the round-17 kernel tree `c7284461b47` merged into Cake\nmain, rendered by main's codegen) for sm_103a and sm_100a through the\nexporter's #5920-layout path, replacing the round-6 sources. Host: the\nfour round 11-14 host changes re-expressed on main's host (descriptor\npool and `run_sequence` unchanged), plus the round tests ported onto\nmain's collapsed tests.\n\nNumerics rule (every round): no precision-level change anywhere (same\ntolerances, same or higher-precision intermediates). Rounds that change\noutput bits are called out below; every other program is bit-identical\nto its predecessor (NaN-poisoned bit compare on the measured cells).\n\n### What changed per round\n\n- Round 7 ([Cake\n!1037](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1037),\nwas #5728): FP8/H64 single-CTA SWA (class K1): single-pass softmax with\nthe TMEM-alias correctness fix (Q x400 over-tolerance elements\n398..64359 -> 0) and softmax warps helping the first K-tile gather,\n-0.7..-0.85 us per row; FP8/H64 cluster / wide one-partition: V4 gather\nowner, whole 128-key tile per cluster CTA with an f32 end merge over\nDSMEM (bits change by merge grouping), -0.13..-0.70 us; H8/H16 decode:\nloader warps skip the padded gather rows, up to -1.6 us.\n- Round 8 ([Cake\n!1043](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1043),\nwas #5742): FP8/H64 wide one-partition in the whole-tile form with the\nno-LSE epilogue, -0.8..-0.9 us per row (bits change by merge grouping);\nK1 row max through `tcgen05.ld.red.max` on SM103a / full-tile fast max\non SM100a, -0.45..-0.83 us; H8/H16 index-row L2 prefetch, -0.10..-0.26\nus; BF16 one-tile SWA chain K stage-0 gather before the index barrier,\n-0.03..-0.10 us.\n- Round 9 ([Cake\n!1061](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1061),\nwas #5845): six bit-identical levers: coalesced final-O epilogue of the\nfp8 H64 M64 persistent body (-7..-18 % on the six M64 rows), K4\nfirst-tile gather split across the three warp roles (-2.5..-2.7 %), bf16\nH64 guard by-value TMA descriptor ABI on sm_103a, K1 8-warp O epilogue\ndrain, H/I SwapsAb page pair 0 from page-loader registers, class-O fp8\nH64 5-slot KV ring (-12 % / -7..-9 %).\n- Round 10 ([Cake\n!1066](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1066),\nwas #5854): bit-identical: class-O fp8 H64 split O-accumulator handshake\n+ six-slot K ring with early Q release (-8..-10 %), bf16 H64 guard\nmask-flag pre-decode + transposed O store (-3.1..-4.1 %), H/I SwapsAb\nindex-row L2 prefetch on sm_103a; the h8/h16 bindings gain the\n`num_query_tokens` scalar the host already passes by name.\n- Round 11 ([Cake\n!1085](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1085),\nwas #5879): seven bit-identical levers (fp8 H64 M64 gated box-TMA K\ngather + per-stage O split credit; fp8 K4 last-tile key split; fp8 H128\npersistent epilogue load-ahead-4 on sm_100a + deferred staging wait;\nbf16 H128 row-first elected multi-warp gather issue; bf16 H64 guard\nclass-conditional gather4 issue) plus three contract-identical\ncorrectness fixes (split-FP8 P stage 1024 B-aligned at SMEM 175104 in\nthe K4 / M64 / fp8 H128 persistent programs; guarded 16 B vector loads\nin the top-k index producers). **Host:** `out=None` is allocated in\n`run_cake_dsv4` after routing and placed at `base % 4 KiB == 0x800` on\nthe six routes where the phase law was measured\n(`allocate_cake_dsv4_output`, `cake_dsv4_out_phase`, `out_shape`);\ncaller-provided `out` and the other routes are unchanged. New\n`tests/mla/test_cake_dsv4_out_placement.py`.\n- Round 12 ([Cake\n!1126](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1126),\nwas #5946): bf16 H128 row-first / prefill O epilogue `tcgen05.wait::ld`\nper 32-column TMEM load (-1.4..-6.0 %); bf16 H32 top-k mixed-pool split\nassignment (re-associates f32 partials by split geometry, strictly more\nprecise: cells > 1 ulp vs fp32 118.8k -> ~630) and active_topk mask\nbefore the s_full wait (-3.5..-5.2 %); fp8 K4 wide quarter-tile tail +\nhelper-correction readback pre-issue (-2.0..-4.1 %); **Host:** the fp8\nH64 M64 body is two exported programs selected by the item width in\n`_route` (`_fp8_h64_m64_program`:\n`fp8_h64_prefill_source_persistent_m64` for `sparse_topk == 128`,\n`..._m64_multi_tile` otherwise; same ABI, same bits).\n- Round 13 ([Cake\n!1152](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1152),\nwas #5973): bit-identical: **Host + program:** bf16 H128 row-first rows\nwith 17-37 tokens run the new `bf16_h128_topk128x_row_first_vsplit`\nprogram (two 2-CTA clusters per token gathering only their N256 V half;\ngrid 4 x tokens; `_BF16_ROW_FIRST_V_HALF_SPLIT_MAX_TOKENS = 37`),\nhardening-000025 -8.4 % GB300 / -7.8 % B200; fp8 K4 whole-tile `st.async\n... complete_tx` peer O push + four-stage chunked merge (-0.70..-0.74\nus); fp8 H64 M64 multi-tile next-item Q TMA after the CLC response\n(-0.4..-1.5 %); fp8 H128 persistent partial-o accumulation before the\nfinal `o_full` wait (-0.3..-1.1 %).\n- Round 14 ([Cake\n!1168](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1168),\nwas #5999): bit-identical: bf16 H128 row-first (owner + vsplit) index\nwarp issues its nine index loads before the nine `st.shared` passes\n(-5.0..-6.6 %); bf16 H64 guard program stores O through a TMA tensor map\nfrom per-warp staging (-0.9..-3.5 %) -- **Host:** the explicit `\"O\":\n\"O\"` entry in `_TMA_SOURCE_ALIASES` so the guard binding's\n`(\"tma_buffer\", \"O\")` resolves; fp8 H128 persistent two-box pipelined\nepilogue drain on sm_103a.\n- Round 15 ([Cake\n!1177](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1177),\nheld on the layout decision): bit-identical: the two-box pipelined\nepilogue drain becomes the default for the sm_100a fp8 H128 lane-gather\nvariant (>= 128 work items); no host change.\n- Round 16 ([Cake\n!1182](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1182),\nheld): bit-identical: fp8 H64 M64 multi-tile softmax -1 ballot hoisted\nabove the `s_full` join (-0.22..-0.56 us); bf16 H64 guard O store split\nper V stage so the stage-0 O drain overlaps PV1 (-0.19..-0.35 us); no\nhost change.\n- Round 17 ([Cake\n!1186](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1186),\nheld): bit-identical: bf16 H128 row-first programs (owner + vsplit)\nhoist the swa / compressed V table select out of the four elected gather\ngroups (hardening-000025 -0.593 us GB300 / -0.800 us B200,\nhardening-000031 -0.160 / -0.751 us); no host change. Round 18 ([Cake\n!1193](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1193))\nshipped no program change (ledger only).\n\n### Layout (#5920) notes\n\n- Per-arch registry schema unchanged: arch-prefixed `sources`,\n`arg_plan` as `_PLAN_<LABEL> [+ _SLAB] + _GRID`, `tma_workspace_bytes`\nonly where non-zero, reducers shared through `common/` where both\narchitectures compile the same kernel (`split_reduce`,\n`bf16_h64_compressed_reduce`); the split-5 reducers stay per-arch under\nthe one key `bf16_h128_split5_reduce` (sm_103a grid `(tokens, heads / 4,\n1)`, sm_100a `(token"},"path":{"kind":"string","value":"csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_binding.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n// Generated by the Cake source exporter — do not edit.\n// tvm-ffi direct-source launcher for Cake kernel 'kernel_cake_dsv4_697c8662eb01c8d6bd50'.\n#include \"cake_dsv4_host_shim.h\"\n\nextern \"C\" __global__ void kernel_cake_dsv4_697c8662eb01c8d6bd50(__nv_bfloat16* __restrict__ partial_O, float* __restrict__ partial_lse, __nv_bfloat16* __restrict__ O, int num_heads, int num_splits);\n\nnamespace cake_host_shim_15c8bc70f310de48 {\n\nusing namespace cake_dsv4_host_shim;\n\nvoid Run(TensorView arg_partial_O, TensorView arg_partial_lse, TensorView arg_O, int64_t arg_num_heads, int64_t arg_num_splits, int64_t grid_x, int64_t grid_y, int64_t grid_z) {\n DLDevice dev = arg_partial_O.device();\n ScopedCudaDevice device_guard(dev.device_id);\n CheckCudaTensor(arg_partial_O, \"partial_O\");\n CheckDtype(arg_partial_O, \"partial_O\", 4, 16, 1);\n CheckContiguous(arg_partial_O, \"partial_O\");\n CheckCudaTensor(arg_partial_lse, \"partial_lse\");\n CheckDtype(arg_partial_lse, \"partial_lse\", 2, 32, 1);\n CheckContiguous(arg_partial_lse, \"partial_lse\");\n CheckCudaTensor(arg_O, \"O\");\n CheckDtype(arg_O, \"O\", 4, 16, 1);\n CheckContiguous(arg_O, \"O\");\n TVM_FFI_CHECK(arg_num_heads >= -2147483648LL && arg_num_heads <= 2147483647LL, ValueError)\n << \"scalar 'num_heads' value \" << arg_num_heads\n << \" is outside i32 range [-2147483648, 2147483647]\";\n TVM_FFI_CHECK(arg_num_splits >= -2147483648LL && arg_num_splits <= 2147483647LL, ValueError)\n << \"scalar 'num_splits' value \" << arg_num_splits\n << \" is outside i32 range [-2147483648, 2147483647]\";\n CheckSameCudaDevice(arg_partial_lse, arg_partial_O, \"partial_lse\", \"partial_O\");\n CheckSameCudaDevice(arg_O, arg_partial_O, \"O\", \"partial_O\");\n TVM_FFI_CHECK(grid_x > 0 && grid_y > 0 && grid_z > 0, ValueError)\n << \"launch grid dimensions must be positive, got (\" << grid_x << \", \" << grid_y\n << \", \" << grid_z << \")\";\n\n cudaStream_t stream = (cudaStream_t)TVMFFIEnvGetStream(dev.device_type, dev.device_id);\n __nv_bfloat16* p_partial_O = static_cast<__nv_bfloat16*>(arg_partial_O.data_ptr());\n float* p_partial_lse = static_cast<float*>(arg_partial_lse.data_ptr());\n __nv_bfloat16* p_O = static_cast<__nv_bfloat16*>(arg_O.data_ptr());\n int32_t v_num_heads = (int32_t)arg_num_heads;\n int32_t v_num_splits = (int32_t)arg_num_splits;\n void* kargs[] = {&p_partial_O, &p_partial_lse, &p_O, &v_num_heads, &v_num_splits};\n\n\n dim3 grid((uint32_t)grid_x, (uint32_t)grid_y, (uint32_t)grid_z);\n dim3 block(128u, 1u, 1u);\n\n cudaLaunchConfig_t config{};\n config.gridDim = grid;\n config.blockDim = block;\n config.dynamicSmemBytes = 0u;\n config.stream = stream;\n cudaError_t launch_status = cudaLaunchKernelExC(\n &config, reinterpret_cast<const void*>(kernel_cake_dsv4_697c8662eb01c8d6bd50), kargs);\n TVM_FFI_CHECK(launch_status == cudaSuccess, RuntimeError)\n << \"cudaLaunchKernelExC for kernel_cake_dsv4_697c8662eb01c8d6bd50 failed: \"\n << cudaGetErrorString(launch_status);\n}\n\n} // namespace cake_host_shim_15c8bc70f310de48\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(run, cake_host_shim_15c8bc70f310de48::Run);\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n// Generated by the Cake source exporter — do not edit.\n// tvm-ffi direct-source launcher for Cake kernel 'kernel_cake_dsv4_ff2e22a8db18dbc0c76e'.\n#include <cuda.h>\n#include <cuda_bf16.h>\n#include <cuda_fp16.h>\n#include <cuda_runtime.h>\n\n#include \"tvm_ffi_utils.h\"\n\n#include <cstdint>\n\nextern \"C\" __global__ void kernel_cake_dsv4_ff2e22a8db18dbc0c76e(__nv_bfloat16* __restrict__ partial_O, float* __restrict__ partial_lse, __nv_bfloat16* __restrict__ O, int num_heads, int num_splits);\n\n\nnamespace cake_host_shim_d07f0b28eef7fa6d {\n\nusing tvm::ffi::TensorView;\n\nvoid Run(TensorView arg_partial_O, TensorView arg_partial_lse, TensorView arg_O, int64_t arg_num_heads, int64_t arg_num_splits, int64_t grid_x, int64_t grid_y, int64_t grid_z) {\n DLDevice dev = arg_partial_O.device();\n tvm::ffi::CUDADeviceGuard device_guard(dev.device_id);\n check_cuda_tensor(arg_partial_O, \"partial_O\");\n check_dtype(arg_partial_O, DLDataType{kDLBfloat, 16, 1}, \"partial_O\");\n check_contiguous(arg_partial_O, \"partial_O\");\n check_cuda_tensor(arg_partial_lse, \"partial_lse\");\n check_dtype(arg_partial_lse, DLDataType{kDLFloat, 32, 1}, \"partial_lse\");\n check_contiguous(arg_partial_lse, \"partial_lse\");\n check_cuda_tensor(arg_O, \"O\");\n check_dtype(arg_O, DLDataType{kDLBfloat, 16, 1}, \"O\");\n check_contiguous(arg_O, \"O\");\n TVM_FFI_CHECK(arg_num_heads >= -2147483648LL && arg_num_heads <= 2147483647LL, ValueError)\n << \"scalar 'num_heads' value \" << arg_num_heads\n << \" is outside i32 range [-2147483648, 2147483647]\";\n TVM_FFI_CHECK(arg_num_splits >= -2147483648LL && arg_num_splits <= 2147483647LL, ValueError)\n << \"scalar 'num_splits' value \" << arg_num_splits\n << \" is outside i32 range [-2147483648, 2147483647]\";\n check_same_device(arg_partial_lse, arg_partial_O, \"partial_lse\", \"partial_O\");\n check_same_device(arg_O, arg_partial_O, \"O\", \"partial_O\");\n TVM_FFI_CHECK(grid_x > 0 && grid_y > 0 && grid_z > 0, ValueError)\n << \"launch grid dimensions must be positive, got (\" << grid_x << \", \" << grid_y\n << \", \" << grid_z << \")\";\n\n cudaStream_t stream = (cudaStream_t)TVMFFIEnvGetStream(dev.device_type, dev.device_id);\n __nv_bfloat16* p_partial_O = static_cast<__nv_bfloat16*>(arg_partial_O.data_ptr());\n float* p_partial_lse = static_cast<float*>(arg_partial_lse.data_ptr());\n __nv_bfloat16* p_O = static_cast<__nv_bfloat16*>(arg_O.data_ptr());\n int32_t v_num_heads = (int32_t)arg_num_heads;\n int32_t v_num_splits = (int32_t)arg_num_splits;\n void* kargs[] = {&p_partial_O, &p_partial_lse, &p_O, &v_num_heads, &v_num_splits};\n\n\n dim3 grid((uint32_t)grid_x, (uint32_t)grid_y, (uint32_t)grid_z);\n dim3 block(128u, 1u, 1u);\n\n cudaLaunchConfig_t config{};\n config.gridDim = grid;\n config.blockDim = block;\n config.dynamicSmemBytes = 0u;\n config.stream = stream;\n cudaError_t launch_status = cudaLaunchKernelExC(\n &config, reinterpret_cast<const void*>(kernel_cake_dsv4_ff2e22a8db18dbc0c76e), kargs);\n TVM_FFI_CHECK(launch_status == cudaSuccess, RuntimeError)\n << \"cudaLaunchKernelExC for kernel_cake_dsv4_ff2e22a8db18dbc0c76e failed: \"\n << cudaGetErrorString(launch_status);\n}\n\n} // namespace cake_host_shim_d07f0b28eef7fa6d\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(run, cake_host_shim_d07f0b28eef7fa6d::Run);\n"},"diff":{"kind":"string","value":"--- csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_binding.cu\n+++ csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_binding.cu\n@@ -15,35 +15,43 @@\n */\n \n // Generated by the Cake source exporter — do not edit.\n-// tvm-ffi direct-source launcher for Cake kernel 'kernel_cake_dsv4_697c8662eb01c8d6bd50'.\n-#include \"cake_dsv4_host_shim.h\"\n+// tvm-ffi direct-source launcher for Cake kernel 'kernel_cake_dsv4_ff2e22a8db18dbc0c76e'.\n+#include <cuda.h>\n+#include <cuda_bf16.h>\n+#include <cuda_fp16.h>\n+#include <cuda_runtime.h>\n \n-extern \"C\" __global__ void kernel_cake_dsv4_697c8662eb01c8d6bd50(__nv_bfloat16* __restrict__ partial_O, float* __restrict__ partial_lse, __nv_bfloat16* __restrict__ O, int num_heads, int num_splits);\n+#include \"tvm_ffi_utils.h\"\n \n-namespace cake_host_shim_15c8bc70f310de48 {\n+#include <cstdint>\n \n-using namespace cake_dsv4_host_shim;\n+extern \"C\" __global__ void kernel_cake_dsv4_ff2e22a8db18dbc0c76e(__nv_bfloat16* __restrict__ partial_O, float* __restrict__ partial_lse, __nv_bfloat16* __restrict__ O, int num_heads, int num_splits);\n+\n+\n+namespace cake_host_shim_d07f0b28eef7fa6d {\n+\n+using tvm::ffi::TensorView;\n \n void Run(TensorView arg_partial_O, TensorView arg_partial_lse, TensorView arg_O, int64_t arg_num_heads, int64_t arg_num_splits, int64_t grid_x, int64_t grid_y, int64_t grid_z) {\n DLDevice dev = arg_partial_O.device();\n- ScopedCudaDevice device_guard(dev.device_id);\n- CheckCudaTensor(arg_partial_O, \"partial_O\");\n- CheckDtype(arg_partial_O, \"partial_O\", 4, 16, 1);\n- CheckContiguous(arg_partial_O, \"partial_O\");\n- CheckCudaTensor(arg_partial_lse, \"partial_lse\");\n- CheckDtype(arg_partial_lse, \"partial_lse\", 2, 32, 1);\n- CheckContiguous(arg_partial_lse, \"partial_lse\");\n- CheckCudaTensor(arg_O, \"O\");\n- CheckDtype(arg_O, \"O\", 4, 16, 1);\n- CheckContiguous(arg_O, \"O\");\n+ tvm::ffi::CUDADeviceGuard device_guard(dev.device_id);\n+ check_cuda_tensor(arg_partial_O, \"partial_O\");\n+ check_dtype(arg_partial_O, DLDataType{kDLBfloat, 16, 1}, \"partial_O\");\n+ check_contiguous(arg_partial_O, \"partial_O\");\n+ check_cuda_tensor(arg_partial_lse, \"partial_lse\");\n+ check_dtype(arg_partial_lse, DLDataType{kDLFloat, 32, 1}, \"partial_lse\");\n+ check_contiguous(arg_partial_lse, \"partial_lse\");\n+ check_cuda_tensor(arg_O, \"O\");\n+ check_dtype(arg_O, DLDataType{kDLBfloat, 16, 1}, \"O\");\n+ check_contiguous(arg_O, \"O\");\n TVM_FFI_CHECK(arg_num_heads >= -2147483648LL && arg_num_heads <= 2147483647LL, ValueError)\n << \"scalar 'num_heads' value \" << arg_num_heads\n << \" is outside i32 range [-2147483648, 2147483647]\";\n TVM_FFI_CHECK(arg_num_splits >= -2147483648LL && arg_num_splits <= 2147483647LL, ValueError)\n << \"scalar 'num_splits' value \" << arg_num_splits\n << \" is outside i32 range [-2147483648, 2147483647]\";\n- CheckSameCudaDevice(arg_partial_lse, arg_partial_O, \"partial_lse\", \"partial_O\");\n- CheckSameCudaDevice(arg_O, arg_partial_O, \"O\", \"partial_O\");\n+ check_same_device(arg_partial_lse, arg_partial_O, \"partial_lse\", \"partial_O\");\n+ check_same_device(arg_O, arg_partial_O, \"O\", \"partial_O\");\n TVM_FFI_CHECK(grid_x > 0 && grid_y > 0 && grid_z > 0, ValueError)\n << \"launch grid dimensions must be positive, got (\" << grid_x << \", \" << grid_y\n << \", \" << grid_z << \")\";\n@@ -66,12 +74,12 @@\n config.dynamicSmemBytes = 0u;\n config.stream = stream;\n cudaError_t launch_status = cudaLaunchKernelExC(\n- &config, reinterpret_cast<const void*>(kernel_cake_dsv4_697c8662eb01c8d6bd50), kargs);\n+ &config, reinterpret_cast<const void*>(kernel_cake_dsv4_ff2e22a8db18dbc0c76e), kargs);\n TVM_FFI_CHECK(launch_status == cudaSuccess, RuntimeError)\n- << \"cudaLaunchKernelExC for kernel_cake_dsv4_697c8662eb01c8d6bd50 failed: \"\n+ << \"cudaLaunchKernelExC for kernel_cake_dsv4_ff2e22a8db18dbc0c76e failed: \"\n << cudaGetErrorString(launch_status);\n }\n \n-} // namespace cake_host_shim_15c8bc70f310de48\n+} // namespace cake_host_shim_d07f0b28eef7fa6d\n \n-TVM_FFI_DLL_EXPORT_TYPED_FUNC(run, cake_host_shim_15c8bc70f310de48::Run);\n+TVM_FFI_DLL_EXPORT_TYPED_FUNC(run, cake_host_shim_d07f0b28eef7fa6d::Run);"},"lines_added":{"kind":"number","value":29,"string":"29"},"lines_removed":{"kind":"number","value":21,"string":"21"},"files_in_commit":{"kind":"number","value":7,"string":"7"},"models_mentioned":{"kind":"list like","value":["deepseek"],"string":"[\n \"deepseek\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200","CPU","GB300","SM100","SM103","SM120"],"string":"[\n \"B200\",\n \"CPU\",\n \"GB300\",\n \"SM100\",\n \"SM103\",\n \"SM120\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["4 x","0.9578x","0.9820x","6 x"],"string":"[\n \"4 x\",\n \"0.9578x\",\n \"0.9820x\",\n \"6 x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_binding.cu).\n\nGoal: perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative)\nTarget hardware: B200, CPU, GB300, SM100, SM103, SM120\nTarget models: deepseek\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n// Generated by the Cake source exporter — do not edit.\n// tvm-ffi direct-source launcher for Cake kernel 'kernel_cake_dsv4_697c8662eb01c8d6bd50'.\n#include \"cake_dsv4_host_shim.h\"\n\nextern \"C\" __global__ void kernel_cake_dsv4_697c8662eb01c8d6bd50(__nv_bfloat16* __restrict__ partial_O, float* __restrict__ partial_lse, __nv_bfloat16* __restrict__ O, int num_heads, int num_splits);\n\nnamespace cake_host_shim_15c8bc70f310de48 {\n\nusing namespace cake_dsv4_host_shim;\n\nvoid Run(TensorView arg_partial_O, TensorView arg_partial_lse, TensorView arg_O, int64_t arg_num_heads, int64_t arg_num_splits, int64_t grid_x, int64_t grid_y, int64_t grid_z) {\n DLDevice dev = arg_partial_O.device();\n ScopedCudaDevice device_guard(dev.device_id);\n CheckCudaTensor(arg_partial_O, \"partial_O\");\n CheckDtype(arg_partial_O, \"partial_O\", 4, 16, 1);\n CheckContiguous(arg_partial_O, \"partial_O\");\n CheckCudaTensor(arg_partial_lse, \"partial_lse\");\n CheckDtype(arg_partial_lse, \"partial_lse\", 2, 32, 1);\n CheckContiguous(arg_partial_lse, \"partial_lse\");\n CheckCudaTensor(arg_O, \"O\");\n CheckDtype(arg_O, \"O\", 4, 16, 1);\n CheckContiguous(arg_O, \"O\");\n TVM_FFI_CHECK(arg_num_heads >= -2147483648LL && arg_num_heads <= 2147483647LL, ValueError)\n << \"scalar 'num_heads' value \" << arg_num_heads\n << \" is outside i32 range [-2147483648, 2147483647]\";\n TVM_FFI_CHECK(arg_num_splits >= -2147483648LL && arg_num_splits <= 2147483647LL, ValueError)\n << \"scalar 'num_splits' value \" << arg_num_splits\n << \" is outside i32 range [-2147483648, 2147483647]\";\n CheckSameCudaDevice(arg_partial_lse, arg_partial_O, \"partial_lse\", \"partial_O\");\n CheckSameCudaDevice(arg_O, arg_partial_O, \"O\", \"partial_O\");\n TVM_FFI_CHECK(grid_x > 0 && grid_y > 0 && grid_z > 0, ValueError)\n << \"launch grid dimensions must be positive, got (\" << grid_x << \", \" << grid_y\n << \", \" << grid_z << \")\";\n\n cudaStream_t stream = (cudaStream_t)TVMFFIEnvGetStream(dev.device_type, dev.device_id);\n __nv_bfloat16* p_partial_O = static_cast<__nv_bfloat16*>(arg_partial_O.data_ptr());\n float* p_partial_lse = static_cast<float*>(arg_partial_lse.data_ptr());\n __nv_bfloat16* p_O = static_cast<__nv_bfloat16*>(arg_O.data_ptr());\n int32_t v_num_heads = (int32_t)arg_num_heads;\n int32_t v_num_splits = (int32_t)arg_num_splits;\n void* kargs[] = {&p_partial_O, &p_partial_lse, &p_O, &v_num_heads, &v_num_splits};\n\n\n dim3 grid((uint32_t)grid_x, (uint32_t)grid_y, (uint32_t)grid_z);\n dim3 block(128u, 1u, 1u);\n\n cudaLaunchConfig_t config{};\n config.gridDim = grid;\n config.blockDim = block;\n config.dynamicSmemBytes = 0u;\n config.stream = stream;\n cudaError_t launch_status = cudaLaunchKernelExC(\n &config, reinterpret_cast<const void*>(kernel_cake_dsv4_697c8662eb01c8d6bd50), kargs);\n TVM_FFI_CHECK(launch_status == cudaSuccess, RuntimeError)\n << \"cudaLaunchKernelExC for kernel_cake_dsv4_697c8662eb01c8d6bd50 failed: \"\n << cudaGetErrorString(launch_status);\n}\n\n} // namespace cake_host_shim_15c8bc70f310de48\n\nTVM_FFI_DLL_EXPORT_TYPED_FUNC(run, cake_host_shim_15c8bc70f310de48::Run);\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Summary\n\nRounds 7-17 of the DSv4 sparse-MLA Cake backend (`backend=\"cake\"`, SM100 + SM103) as one cumulative change on the #5920 layout (per-variant bindings taking their checks from `tvm_ffi_utils.h`, shared sources under `common/`, `run_sequence`, the host's direct variant launches). Main carries round 6 (#5700) for this family; the eight per-round PRs stacked on it (#5728, #5742, #5845, #5854, #5879, #5946, #5973, #5999) and the held round 15-17 fork branches were closed in favour of this PR. Programs: whole-family regeneration of the `cake_dsv4` sources from Cake !1037's tree (the round-17 kernel tree `c7284461b47` merged into Cake main, rendered by main's codegen) for sm_103a and sm_100a through the exporter's #5920-layout path, replacing the round-6 sources. Host: the four round 11-14 host changes re-expressed on main's host (descriptor pool and `run_sequence` unchanged), plus the round tests ported onto main's collapsed tests.\n\nNumerics rule (every round): no precision-level change anywhere (same tolerances, same or higher-precision intermediates). Rounds that change output bits are called out below; every other program is bit-identical to its predecessor (NaN-poisoned bit compare on the measured cells).\n\n### What changed per round\n\n- Round 7 ([Cake !1037](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1037), was #5728): FP8/H64 single-CTA SWA (class K1): single-pass softmax with the TMEM-alias correctness fix (Q x400 over-tolerance elements 398..64359 -> 0) and softmax warps helping the first K-tile gather, -0.7..-0.85 us per row; FP8/H64 cluster / wide one-partition: V4 gather owner, whole 128-key tile per cluster CTA with an f32 end merge over DSMEM (bits change by merge grouping), -0.13..-0.70 us; H8/H16 decode: loader warps skip the padded gather rows, up to -1.6 us.\n- Round 8 ([Cake !1043](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1043), was #5742): FP8/H64 wide one-partition in the whole-tile form with the no-LSE epilogue, -0.8..-0.9 us per row (bits change by merge grouping); K1 row max through `tcgen05.ld.red.max` on SM103a / full-tile fast max on SM100a, -0.45..-0.83 us; H8/H16 index-row L2 prefetch, -0.10..-0.26 us; BF16 one-tile SWA chain K stage-0 gather before the index barrier, -0.03..-0.10 us.\n- Round 9 ([Cake !1061](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1061), was #5845): six bit-identical levers: coalesced final-O epilogue of the fp8 H64 M64 persistent body (-7..-18 % on the six M64 rows), K4 first-tile gather split across the three warp roles (-2.5..-2.7 %), bf16 H64 guard by-value TMA descriptor ABI on sm_103a, K1 8-warp O epilogue drain, H/I SwapsAb page pair 0 from page-loader registers, class-O fp8 H64 5-slot KV ring (-12 % / -7..-9 %).\n- Round 10 ([Cake !1066](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1066), was #5854): bit-identical: class-O fp8 H64 split O-accumulator handshake + six-slot K ring with early Q release (-8..-10 %), bf16 H64 guard mask-flag pre-decode + transposed O store (-3.1..-4.1 %), H/I SwapsAb index-row L2 prefetch on sm_103a; the h8/h16 bindings gain the `num_query_tokens` scalar the host already passes by name.\n- Round 11 ([Cake !1085](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1085), was #5879): seven bit-identical levers (fp8 H64 M64 gated box-TMA K gather + per-stage O split credit; fp8 K4 last-tile key split; fp8 H128 persistent epilogue load-ahead-4 on sm_100a + deferred staging wait; bf16 H128 row-first elected multi-warp gather issue; bf16 H64 guard class-conditional gather4 issue) plus three contract-identical correctness fixes (split-FP8 P stage 1024 B-aligned at SMEM 175104 in the K4 / M64 / fp8 H128 persistent programs; guarded 16 B vector loads in the top-k index producers). **Host:** `out=None` is allocated in `run_cake_dsv4` after routing and placed at `base % 4 KiB == 0x800` on the six routes where the phase law was measured (`allocate_cake_dsv4_output`, `cake_dsv4_out_phase`, `out_shape`); caller-provided `out` and the other routes are unchanged. New `tests/mla/test_cake_dsv4_out_placement.py`.\n- Round 12 ([Cake !1126](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1126), was #5946): bf16 H128 row-first / prefill O epilogue `tcgen05.wait::ld` per 32-column TMEM load (-1.4..-6.0 %); bf16 H32 top-k mixed-pool split assignment (re-associates f32 partials by split geometry, strictly more precise: cells > 1 ulp vs fp32 118.8k -> ~630) and active_topk mask before the s_full wait (-3.5..-5.2 %); fp8 K4 wide quarter-tile tail + helper-correction readback pre-issue (-2.0..-4.1 %); **Host:** the fp8 H64 M64 body is two exported programs selected by the item width in `_route` (`_fp8_h64_m64_program`: `fp8_h64_prefill_source_persistent_m64` for `sparse_topk == 128`, `..._m64_multi_tile` otherwise; same ABI, same bits).\n- Round 13 ([Cake !1152](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1152), was #5973): bit-identical: **Host + program:** bf16 H128 row-first rows with 17-37 tokens run the new `bf16_h128_topk128x_row_first_vsplit` program (two 2-CTA clusters per token gathering only their N256 V half; grid 4 x tokens; `_BF16_ROW_FIRST_V_HALF_SPLIT_MAX_TOKENS = 37`), hardening-000025 -8.4 % GB300 / -7.8 % B200; fp8 K4 whole-tile `st.async ... complete_tx` peer O push + four-stage chunked merge (-0.70..-0.74 us); fp8 H64 M64 multi-tile next-item Q TMA after the CLC response (-0.4..-1.5 %); fp8 H128 persistent partial-o accumulation before the final `o_full` wait (-0.3..-1.1 %).\n- Round 14 ([Cake !1168](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1168), was #5999): bit-identical: bf16 H128 row-first (owner + vsplit) index warp issues its nine index loads before the nine `st.shared` passes (-5.0..-6.6 %); bf16 H64 guard program stores O through a TMA tensor map from per-warp staging (-0.9..-3.5 %) -- **Host:** the explicit `\"O\": \"O\"` entry in `_TMA_SOURCE_ALIASES` so the guard binding's `(\"tma_buffer\", \"O\")` resolves; fp8 H128 persistent two-box pipelined epilogue drain on sm_103a.\n- Round 15 ([Cake !1177](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1177), held on the layout decision): bit-identical: the two-box pipelined epilogue drain becomes the default for the sm_100a fp8 H128 lane-gather variant (>= 128 work items); no host change.\n- Round 16 ([Cake !1182](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1182), held): bit-identical: fp8 H64 M64 multi-tile softmax -1 ballot hoisted above the `s_full` join (-0.22..-0.56 us); bf16 H64 guard O store split per V stage so the stage-0 O drain overlaps PV1 (-0.19..-0.35 us); no host change.\n- Round 17 ([Cake !1186](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1186), held): bit-identical: bf16 H128 row-first programs (owner + vsplit) hoist the swa / compressed V table select out of the four elected gather groups (hardening-000025 -0.593 us GB300 / -0.800 us B200, hardening-000031 -0.160 / -0.751 us); no host change. Round 18 ([Cake !1193](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1193)) shipped no program change (ledger only).\n\n### Layout (#5920) notes\n\n- Per-arch registry schema unchanged: arch-prefixed `sources`, `arg_plan` as `_PLAN_<LABEL> [+ _SLAB] + _GRID`, `tma_workspace_bytes` only where non-zero, reducers shared through `common/` where both architectures compile the same kernel (`split_reduce`, `bf16_h64_compressed_reduce`); the split-5 reducers stay per-arch under the one key `bf16_h128_split5_reduce` (sm_103a grid `(tokens, heads / 4, 1)`, sm_100a `(tokens, heads, 1)`, as main's launch test pins).\n- Two new variant keys per architecture: `bf16_h128_topk128x_row_first_vsplit`, `fp8_h64_prefill_source_persistent_m64_multi_tile` (27 variants per arch).\n- No family bindings; two-stage routes go through `run_sequence`; the host's descriptor pool is untouched.\n\n### Variant / file diff vs main `a12173ca0`\n\n- Per-arch registrations: 27 variants each (main had 25): new keys `bf16_h128_topk128x_row_first_vsplit` (round 13, host-routed for 17-37-token rows) and `fp8_h64_prefill_source_persistent_m64_multi_tile` (round 12). Loader `flashinfer/jit/cake_dsv4.py`: data-only edits (registrations, plan/grid constants, source lists); loader functions and `__all__` untouched.\n- Files: `common/` 30 (4 before), `sm_100a/` 24 (46 before), `sm_103a/` 24 (46 before); `sm_120a/` and every other family untouched. Diff vs main: 107 files, +17906 / -62404.\n- Fold disclosure: the exporter serves a variant from `common/` when its kernel + binding sources are byte-identical on both architectures modulo hash tokens. With the rounds 7-18 kernel tree rendered by current Cake main codegen, 15 of the 27 variants fold (bf16_h128_swa128, bf16_h128_topk128x_row_first, …_vsplit, bf16_h128_topk128x_split4_sm100, bf16_h16_h32_swa128_v44, bf16_h32_topk128x_early_v47, bf16_h64_compressed_q8_v38, bf16_h64_compressed_reduce, bf16_h64_guard_q_tma_batch_r25, bf16_h64_prefill, fp8_h64_prefill_source_persistent_m64, …_m64_multi_tile, fp8_h64_source_exact, fp8_lowhead_h64, split_reduce); 12 stay per-arch. Each architecture still compiles its own module from the shared source.\n- Host: the six host/test commits below the export commits port the rounds 13-17 host changes (vsplit route, descriptor-pool and `run_sequence` plumbing, output-placement test) onto the #5920 host; `cake_dsv4_host_shim.h` is unreferenced by the regenerated bindings and left in place.\n\n## Validation\n\nBoth architectures measured on the exported programs of this branch (GB300 = sm_103a commit `08d1c3c8`, whose sm_103a sources are byte-identical modulo hash tokens to this head; B200 = this head `4146373e`). Baseline = FlashInfer trtllm-gen default path of the same clone. Paired CUPTI sweeps (cold L2, active-union median), same-process; same-GPU ABBA = legs A1 B1 B2 A2 on one GPU, A = this branch, B = the round-17 fork head `dbf86c4d6` (quantum q = 0.032 us).\n\n| | GB300 (sm_103a) | B200 (sm_100a) |\n|---|---|---|\n| production export: 134 shapes timed + correct vs the Cake source programs (receipts) | 133/134 pass, source/export geomean 1.0022, trtllm-gen/export 1.4948 (94 canonical); hardening-000004 timing-only 0.9578x (correctness pass; retained first-run receipt — an independent full run on another node measured it 0.9820x pass; the same-GPU ABBA below shows the row 0.16 us *faster* than round 17 in both orders) — JHB 802461 nvl72d426-T11, 4 GPUs | 134/134 pass, source/export 1.0037 (min h004 0.9845), trtllm-gen/export 1.4404 — NSC 2138957, 4 GPUs |\n| **94 canonical rows faster than the default path** | 94/94 correct, every row > 1.0: geomean 1.4617, min 1.1191 (decode-000051) | 94/94 correct, every row > 1.0: geomean 1.4447, min 1.1774 (decode-000034) |\n| 40 hardening rows faster than the default path | 40/40 correct, every row > 1.0: geomean 1.4857, min 1.1068 (hardening-000004) | 40/40 correct, every row > 1.0: geomean 1.4396, min 1.1357 (hardening-000023) |\n| all 134 rows | geomean 1.4688, min 1.1068, 0 rows <= 1.0 | geomean 1.4432, min 1.1357, 0 rows <= 1.0 |\n| no row > 2 % slower than the round-17 programs (same-GPU ABBA vs `dbf86c4d6`) | pin rows (8): 0 slower, h004 -0.160 us / 064 -0.100 / 065 -0.070 faster both orders, rest within 1 q; hardening 00-39 (40): 0 rows beyond 1.25 q (h034 +0.040 us = +0.13 %, h037 +0.040 us = +0.07 %; h020 -0.580 us); canonical 94: 94 rows in 3 parts (`68a1e0f7` `1e1726bf` `59741678`): 134-row totals = 18 rows slower in both orders, 27 faster in both orders, geomean A/B 0.9956; **1 row above +2 %: decode-000056 +0.350 us (6.53 -> 6.88 us, +5.4 %, program fp8_h16_source_exact)**, next largest +1.7 % (decode-000074/077); largest gains decode-000078 -7.1 %, hardening-000020 -6.9 %, decode-000006/018 -6.7 %, 081 -6.6 %, prefill-style-000086 -2.7 %. Attribution of decode-000056 (Cake round 19, measured on another GB300 node): **not a codegen or ABI effect**. The non-ABI text differences compile to byte-identical SASS on sm_103a (128 regs / 0 spills in every form); A-vs-B replications flip sign between fresh processes of the same install; repeat sampling (5 alternating fresh A/B processes x 3 GPUs) gives this head 6.807 us vs round 17 6.803 us (0.1 q). The kernel (`fp8_h16_source_exact`) has two placement-dependent timing modes ~0.3 us apart that both exports reach; the round-18 cell caught the two installs in different modes. Programs unchanged | pin rows (8): `ea69b60d`: 1 slower both orders = decode-000002 +0.070 us (10.46 us, +0.67 %, 2.2 q); 6 rows timing-identical in all four legs; h031 within its band; hardening 00-39 (40): `0365c256` / `f0fee955` (B200 legs take ~45 min per 20 rows; both steps hit the 3 h step budget during leg A2): 25/40 rows with all four legs, code part <= +0.030 us (<= 1 q) on every one; the 15 rows without A2 have |A1 - B1|, |A1 - B2| <= 0.09 us (h017 -0.09 us = faster); no row > 2 % in any leg; canonical 94: 6 x 16-row parts (`d69139af` `1b42ff9f` `d2cf5268` `49f23a7d` `fedccecc` `c3874f40`, all four legs): 134-row totals = 8 rows slower in both orders (max decode-000002 +0.070 us = +0.67 %, the other seven +0.04..+0.06 us <= 2 q), 0 rows faster in both orders, 112 rows timing-identical or within 1 q, geomean A/B 1.0004; **no row above +2 %**; decode-000056 (the GB300 +5.4 % row) is 6.690 us in all four legs on B200: sm_100a already used the `grid_constant` TMA ABI in round 17, consistent with the GB300 cell being a sampling artefact (see the GB300 column) |\n| `tests/mla/test_cake_dsv4*.py` (GPU, fresh clone of this head) | 320 passed, 4 skipped, 0 failed (`5e70a6c9`, 1 GPU of 802461) | 319 passed, 4 skipped, 1 failed in the full run (`b13c39b1`: `test_cuda_graph_replay_matches_eager[h32-fp8-q1]` at \"eager call allocated\" with memory_allocated *lower* than the baseline, i.e. a GC of earlier tests' tensors during the call); the test re-run in isolation passes 12/12 params (`cb812a81`) |\n| Cake-side gates of the kernel tree (Cake !1037, head `f3108393953`) | 134 rows x all axes 528/528 correct; synccheck 8/8 + memcheck 7/8 rows 0 errors; CPU rule tests 705/705 | same: 528/528; synccheck 8/8 + memcheck 7/8 rows 0 errors; 705/705 |\n\nCross-node note: the sweep medians of this run are not comparable to the round-17 PR numbers (different nodes / clock regime: on GB300 both Cake and trtllm-gen moved +5.0 % / +3.0 % geomean vs the round-17 sweep); the same-GPU ABBA row above is the valid round-over-round comparison.\n\n## Baselines and their source PRs\n\n- trtllm-gen default path: FlashInfer main as of `a12173ca0` (this branch's base; the DSv4 trtllm-gen MLA path is unchanged since `c4cb63534`, the #5879 head: the only commit touching the MLA dispatch files since then is #5983, which adds an SM120 source to `flashinfer/jit/mla.py`; #5854, #5845, #5742, #5728, #5700 before it).\n- Cake round 17: fork branch `cake-772-dsv4-round17` (`dbf86c4d6`, held on the #5920 layout decision); round 16: `cake-772-dsv4-round16` (`45c0b819c`, held); round 15: `cake-772-dsv4-round15` (`1a91f12a9`, held); round 14: #5999 (`e2f7310ee`); round 13: #5973; round 12: #5946; round 11: #5879; round 10: #5854; round 9: #5845; round 8: #5742; round 7: #5728; round 6 and before: #5700 and the tracker's earlier PRs.\n- Round 18 (Cake !1193) changed no program: the exported programs here are the round-17 kernel tree `c7284461b47` as merged into Cake main (!1037 head `f3108393953`), rendered on the #5920 layout by the exporter (main's codegen since the round-17 base changes every generated program's text — dead-helper pruning, grid_constant tensor maps, `__shfl_sync`, launch-bounds macro — without touching the kernel schedules); the pre-export source-vs-export agreement for the sm_103a build-gap row (hardening-000031) is in the round-18 Cake doc.\n\n- Tracker: flashinfer#4254 (DSv4 sparse-MLA Cake backend; this PR supersedes the round 7-14 PRs listed above and the held round 15-17 fork branches `cake-772-dsv4-round15` `1a91f12a9`, `cake-772-dsv4-round16` `45c0b819c`, `cake-772-dsv4-round17` `dbf86c4d6`).\n\nCake MRs: !1037 .. !1193 (Linear CAKE-772); exporter #5920-layout support: [Cake !1200](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1200) (stacked on !1037).\n\n🤖 Generated with [Claude Code](https://claude.com/claude-code)\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n\n## Summary by CodeRabbit\n\n* **New Features**\n * CAKE DSV4 can now allocate its output when none is provided, with route-specific output placement.\n * Added and refined kernel routing for selected BF16 and FP8 workloads, including support for wider sparse inputs and smaller query batches.\n* **Bug Fixes**\n * Improved tensor and launch validation across CUDA devices, including checks for tensor placement and descriptor dimensions.\n * Updated output handling for selected kernels to support tensor-map-based writes and revised buffering.\n* **Tests**\n * Expanded coverage for route selection, output allocation, and output placement.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n<!-- cake-shared-references:start -->\n## References\n\nThe shared reference corpus for CAKE kernel development includes the following projects, documentation, and existing CAKE work:\n\n- **GPU programming and instructions:** [NVIDIA CUDA Programming Guide](https://docs.nvidia.com/cuda/cuda-programming-guide/index.html), [NVIDIA PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/), and gau-nernst's [tcgen05 tutorial](https://gau-nernst.github.io/tcgen05/) and [CUDA kernel examples](https://github.com/gau-nernst/learn-cuda).\n- **Kernel programming libraries and compilers:** [NVIDIA CUTLASS / CuTe](https://github.com/NVIDIA/cutlass), [Triton](https://github.com/triton-lang/triton), [TileLang](https://github.com/tile-ai/tilelang), [NVIDIA cuTile Python](https://github.com/NVIDIA/cutile-python), and [ThunderKittens](https://github.com/HazyResearch/ThunderKittens) ([ThunderKittens 2.0 techniques](https://hazyresearch.stanford.edu/blog/2026-02-19-tk-2)).\n- **Attention and inference:** [FlashAttention (including Hopper and CuTe implementations)](https://github.com/Dao-AILab/flash-attention), [FlashInfer, including its TRT-LLM kernel integration](https://github.com/flashinfer-ai/flashinfer), [Flash Linear Attention](https://github.com/fla-org/flash-linear-attention), [SageAttention](https://github.com/thu-ml/SageAttention), [FlashAttention-FP4](https://github.com/hao-ai-lab/flash-attention-fp4), and [FastVideo](https://github.com/hao-ai-lab/FastVideo).\n- **GEMM and MoE:** [DeepGEMM](https://github.com/deepseek-ai/DeepGEMM), [SonicMoE](https://github.com/Dao-AILab/sonic-moe), [Alpha-MoE](https://github.com/Aleph-Alpha/Alpha-MoE), and [Mixture of Kittens](https://github.com/cursor/mixture-of-kittens).\n- **Clustering and nearest-neighbor kernels:** [Flash K-Means](https://github.com/svg-project/flash-kmeans) and [FlashLib](https://github.com/FlashML-org/flashlib).\n- **Existing CAKE implementations and PRs:** [CAKE-generated kernel progress tracker and PR index (#4254)](https://github.com/flashinfer-ai/flashinfer/issues/4254).\n\nThese are corpus-level references. PR-specific implementation details, changes, and benchmark references are documented above.\n<!-- cake-shared-references:end -->\n\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 6.53, \"optimized\": 6.88, \"stated_speedup\": null, \"speedup\": 0.9491}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 6.69, \"optimized\": 6.69, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"hardening-000025\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.084, \"speedup\": 1.084}, {\"scope\": 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\"GB300\", \"model\": null, \"shape\": \"decode-000056\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.054, \"speedup\": 1.054}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"decode-000074\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.017, \"speedup\": 1.017}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"decode-000077\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.017, \"speedup\": 1.017}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"decode-000002\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0067, \"speedup\": 1.0067}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"hardening-000031\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.00593, \"speedup\": 1.00593}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"hardening-000031\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.008, \"speedup\": 1.008}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"hardening-000031\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.0016, \"speedup\": 1.0016}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": \"hardening-000031\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.00751, \"speedup\": 1.00751}]"},"kernel_speedup":{"kind":"number","value":1.022,"string":"1.022"},"e2e_speedup":{"kind":"null"}}},{"rowIdx":999,"cells":{"repo":{"kind":"string","value":"flashinfer"},"commit":{"kind":"string","value":"911cb09d0981c38d15b775b7820e4a76c72fcfa0"},"date":{"kind":"string","value":"2026-10-04T10:47:29-07:00"},"pr_number":{"kind":"number","value":6045,"string":"6,045"},"pr_url":{"kind":"string","value":"https://github.com/flashinfer-ai/flashinfer/pull/6045"},"title":{"kind":"string","value":"perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative) (#6045)"},"message":{"kind":"string","value":"perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative) (#6045)\n\n## Summary\n\nRounds 7-17 of the DSv4 sparse-MLA Cake backend (`backend=\"cake\"`, SM100\n+ SM103) as one cumulative change on the #5920 layout (per-variant\nbindings taking their checks from `tvm_ffi_utils.h`, shared sources\nunder `common/`, `run_sequence`, the host's direct variant launches).\nMain carries round 6 (#5700) for this family; the eight per-round PRs\nstacked on it (#5728, #5742, #5845, #5854, #5879, #5946, #5973, #5999)\nand the held round 15-17 fork branches were closed in favour of this PR.\nPrograms: whole-family regeneration of the `cake_dsv4` sources from Cake\n!1037's tree (the round-17 kernel tree `c7284461b47` merged into Cake\nmain, rendered by main's codegen) for sm_103a and sm_100a through the\nexporter's #5920-layout path, replacing the round-6 sources. Host: the\nfour round 11-14 host changes re-expressed on main's host (descriptor\npool and `run_sequence` unchanged), plus the round tests ported onto\nmain's collapsed tests.\n\nNumerics rule (every round): no precision-level change anywhere (same\ntolerances, same or higher-precision intermediates). Rounds that change\noutput bits are called out below; every other program is bit-identical\nto its predecessor (NaN-poisoned bit compare on the measured cells).\n\n### What changed per round\n\n- Round 7 ([Cake\n!1037](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1037),\nwas #5728): FP8/H64 single-CTA SWA (class K1): single-pass softmax with\nthe TMEM-alias correctness fix (Q x400 over-tolerance elements\n398..64359 -> 0) and softmax warps helping the first K-tile gather,\n-0.7..-0.85 us per row; FP8/H64 cluster / wide one-partition: V4 gather\nowner, whole 128-key tile per cluster CTA with an f32 end merge over\nDSMEM (bits change by merge grouping), -0.13..-0.70 us; H8/H16 decode:\nloader warps skip the padded gather rows, up to -1.6 us.\n- Round 8 ([Cake\n!1043](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1043),\nwas #5742): FP8/H64 wide one-partition in the whole-tile form with the\nno-LSE epilogue, -0.8..-0.9 us per row (bits change by merge grouping);\nK1 row max through `tcgen05.ld.red.max` on SM103a / full-tile fast max\non SM100a, -0.45..-0.83 us; H8/H16 index-row L2 prefetch, -0.10..-0.26\nus; BF16 one-tile SWA chain K stage-0 gather before the index barrier,\n-0.03..-0.10 us.\n- Round 9 ([Cake\n!1061](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1061),\nwas #5845): six bit-identical levers: coalesced final-O epilogue of the\nfp8 H64 M64 persistent body (-7..-18 % on the six M64 rows), K4\nfirst-tile gather split across the three warp roles (-2.5..-2.7 %), bf16\nH64 guard by-value TMA descriptor ABI on sm_103a, K1 8-warp O epilogue\ndrain, H/I SwapsAb page pair 0 from page-loader registers, class-O fp8\nH64 5-slot KV ring (-12 % / -7..-9 %).\n- Round 10 ([Cake\n!1066](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1066),\nwas #5854): bit-identical: class-O fp8 H64 split O-accumulator handshake\n+ six-slot K ring with early Q release (-8..-10 %), bf16 H64 guard\nmask-flag pre-decode + transposed O store (-3.1..-4.1 %), H/I SwapsAb\nindex-row L2 prefetch on sm_103a; the h8/h16 bindings gain the\n`num_query_tokens` scalar the host already passes by name.\n- Round 11 ([Cake\n!1085](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1085),\nwas #5879): seven bit-identical levers (fp8 H64 M64 gated box-TMA K\ngather + per-stage O split credit; fp8 K4 last-tile key split; fp8 H128\npersistent epilogue load-ahead-4 on sm_100a + deferred staging wait;\nbf16 H128 row-first elected multi-warp gather issue; bf16 H64 guard\nclass-conditional gather4 issue) plus three contract-identical\ncorrectness fixes (split-FP8 P stage 1024 B-aligned at SMEM 175104 in\nthe K4 / M64 / fp8 H128 persistent programs; guarded 16 B vector loads\nin the top-k index producers). **Host:** `out=None` is allocated in\n`run_cake_dsv4` after routing and placed at `base % 4 KiB == 0x800` on\nthe six routes where the phase law was measured\n(`allocate_cake_dsv4_output`, `cake_dsv4_out_phase`, `out_shape`);\ncaller-provided `out` and the other routes are unchanged. New\n`tests/mla/test_cake_dsv4_out_placement.py`.\n- Round 12 ([Cake\n!1126](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1126),\nwas #5946): bf16 H128 row-first / prefill O epilogue `tcgen05.wait::ld`\nper 32-column TMEM load (-1.4..-6.0 %); bf16 H32 top-k mixed-pool split\nassignment (re-associates f32 partials by split geometry, strictly more\nprecise: cells > 1 ulp vs fp32 118.8k -> ~630) and active_topk mask\nbefore the s_full wait (-3.5..-5.2 %); fp8 K4 wide quarter-tile tail +\nhelper-correction readback pre-issue (-2.0..-4.1 %); **Host:** the fp8\nH64 M64 body is two exported programs selected by the item width in\n`_route` (`_fp8_h64_m64_program`:\n`fp8_h64_prefill_source_persistent_m64` for `sparse_topk == 128`,\n`..._m64_multi_tile` otherwise; same ABI, same bits).\n- Round 13 ([Cake\n!1152](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1152),\nwas #5973): bit-identical: **Host + program:** bf16 H128 row-first rows\nwith 17-37 tokens run the new `bf16_h128_topk128x_row_first_vsplit`\nprogram (two 2-CTA clusters per token gathering only their N256 V half;\ngrid 4 x tokens; `_BF16_ROW_FIRST_V_HALF_SPLIT_MAX_TOKENS = 37`),\nhardening-000025 -8.4 % GB300 / -7.8 % B200; fp8 K4 whole-tile `st.async\n... complete_tx` peer O push + four-stage chunked merge (-0.70..-0.74\nus); fp8 H64 M64 multi-tile next-item Q TMA after the CLC response\n(-0.4..-1.5 %); fp8 H128 persistent partial-o accumulation before the\nfinal `o_full` wait (-0.3..-1.1 %).\n- Round 14 ([Cake\n!1168](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1168),\nwas #5999): bit-identical: bf16 H128 row-first (owner + vsplit) index\nwarp issues its nine index loads before the nine `st.shared` passes\n(-5.0..-6.6 %); bf16 H64 guard program stores O through a TMA tensor map\nfrom per-warp staging (-0.9..-3.5 %) -- **Host:** the explicit `\"O\":\n\"O\"` entry in `_TMA_SOURCE_ALIASES` so the guard binding's\n`(\"tma_buffer\", \"O\")` resolves; fp8 H128 persistent two-box pipelined\nepilogue drain on sm_103a.\n- Round 15 ([Cake\n!1177](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1177),\nheld on the layout decision): bit-identical: the two-box pipelined\nepilogue drain becomes the default for the sm_100a fp8 H128 lane-gather\nvariant (>= 128 work items); no host change.\n- Round 16 ([Cake\n!1182](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1182),\nheld): bit-identical: fp8 H64 M64 multi-tile softmax -1 ballot hoisted\nabove the `s_full` join (-0.22..-0.56 us); bf16 H64 guard O store split\nper V stage so the stage-0 O drain overlaps PV1 (-0.19..-0.35 us); no\nhost change.\n- Round 17 ([Cake\n!1186](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1186),\nheld): bit-identical: bf16 H128 row-first programs (owner + vsplit)\nhoist the swa / compressed V table select out of the four elected gather\ngroups (hardening-000025 -0.593 us GB300 / -0.800 us B200,\nhardening-000031 -0.160 / -0.751 us); no host change. Round 18 ([Cake\n!1193](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1193))\nshipped no program change (ledger only).\n\n### Layout (#5920) notes\n\n- Per-arch registry schema unchanged: arch-prefixed `sources`,\n`arg_plan` as `_PLAN_<LABEL> [+ _SLAB] + _GRID`, `tma_workspace_bytes`\nonly where non-zero, reducers shared through `common/` where both\narchitectures compile the same kernel (`split_reduce`,\n`bf16_h64_compressed_reduce`); the split-5 reducers stay per-arch under\nthe one key `bf16_h128_split5_reduce` (sm_103a grid `(tokens, heads / 4,\n1)`, sm_100a `(token"},"path":{"kind":"string","value":"csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_kernel.cu"},"language":{"kind":"string","value":"cuda"},"license":{"kind":"string","value":"Apache-2.0"},"before_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\ntypedef signed char int8_t;\ntypedef unsigned char uint8_t;\ntypedef unsigned short uint16_t;\ntypedef unsigned int uint32_t;\n#if defined(__CUDACC_RTC__)\ntypedef unsigned long long uint64_t;\n#else\ntypedef unsigned long uint64_t;\n#endif\nstatic_assert(sizeof(uint64_t) == 8, \"Cake requires an LP64 CUDA host ABI\");\ntypedef signed int int32_t;\ntypedef short int int16_t;\nstruct __align__(128) CakeTensorMap { uint64_t opaque[16]; };\nstruct __align__(64) CakeTensorMap64 { uint64_t opaque[16]; };\nstatic_assert(sizeof(CakeTensorMap64) == 128, \"64-aligned tensor-map ABI size\");\nstatic_assert(alignof(CakeTensorMap64) == 64, \"64-aligned tensor-map ABI alignment\");\ntemplate <int N>\nstruct __align__(128) CakeTensorMapPack { CakeTensorMap maps[N]; };\n\n#if defined(__CUDACC_RTC__)\ntypedef struct __align__(128) { uint64_t opaque[16]; } CUtensorMap;\n#else\n#include <cuda.h>\n#endif\n\nstatic_assert(sizeof(CUtensorMap) == 128, \"CUtensorMap CUDA ABI must be 128 bytes\");\nstatic_assert(alignof(CakeTensorMap) >= alignof(CUtensorMap), \"CakeTensorMap alignment must cover the CUtensorMap CUDA ABI\");\n#include <cuda_bf16.h>\n#include <cuda_fp8.h>\n\n__device__ __forceinline__ int make_warp_uniform(int x) {\n int result;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;\"\n : \"=r\"(result) : \"r\"(x));\n return result;\n}\n\n#define CAKE_INF CUDART_INF_F\n#define NUM_MAIN_STAGES 1\n#define THREADS 128\n\n#include <math_constants.h>\n\n__device__ __forceinline__ float approx_exp2(float x) {\n float y;\n asm(\"ex2.approx.ftz.f32 %0, %1;\" : \"=f\"(y) : \"f\"(x));\n return y;\n}\n\n\n__device__ __forceinline__ float approx_rcp(float x) {\n float y;\n asm(\"rcp.approx.ftz.f32 %0, %1;\" : \"=f\"(y) : \"f\"(x));\n return y;\n}\n\n\n__device__ __forceinline__ float max_noftz(float a, float b) {\n float c;\n asm(\"max.f32 %0, %1, %2;\" : \"=f\"(c) : \"f\"(a), \"f\"(b));\n return c;\n}\n\nextern \"C\" {\n\n__global__ __launch_bounds__(128) void\nkernel_cake_dsv4_697c8662eb01c8d6bd50(__nv_bfloat16* __restrict__ partial_O, float* __restrict__ partial_lse, __nv_bfloat16* __restrict__ O, int num_heads, int num_splits)\n{\n const int tid = threadIdx.x;\n const int warp = make_warp_uniform(tid / 32);\n const int lane = tid % 32;\n\n\n const int bid = blockIdx.x;\n const int num_bids = gridDim.x;\n\n const int cta_rank = 0;\n\n // === Task calls (dependency order) ===\n int query_idx = blockIdx.x;\n int head_idx = blockIdx.y;\n int stat_base = (query_idx * num_heads + head_idx) * num_splits;\n float local_lse = -CAKE_INF;\n if (lane < num_splits) {\n local_lse = partial_lse[stat_base + lane];\n }\n float _warp_reduce_0 = local_lse;\n #pragma unroll\n for (int offset = 16; offset > 0; offset >>= 1)\n _warp_reduce_0 = max_noftz(_warp_reduce_0, __shfl_xor_sync(0xFFFFFFFF, _warp_reduce_0, offset));\n float global_max = _warp_reduce_0;\n float local_weight = 0.0f;\n if (lane < num_splits) {\n float _exp2_0 = approx_exp2(local_lse - global_max);\n local_weight = ((local_lse == -CAKE_INF) ? 0.0f : _exp2_0);\n }\n float _warp_reduce_1 = local_weight;\n #pragma unroll\n for (int offset = 16; offset > 0; offset >>= 1)\n _warp_reduce_1 += __shfl_xor_sync(0xFFFFFFFF, _warp_reduce_1, offset);\n float global_sum = _warp_reduce_1;\n float _rcp_0 = approx_rcp(global_sum);\n float normalized_weight = ((global_sum > 0.0f) ? local_weight * _rcp_0 : 0.0f);\n int partial_base = stat_base * 512;\n int output_base = (query_idx * num_heads + head_idx) * 512;\n int d_base = tid * 4;\n float acc[4];\n #pragma unroll\n for (int elem = 0; elem < 4; elem++) {\n acc[elem] = 0.0f;\n }\n if (num_splits == 4) {\n float _vec_load_0[4];\n {\n uint2 _vld_0;\n _vld_0 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + d_base) + 0);\n uint32_t* _vpairs_0 = reinterpret_cast<uint32_t*>(&_vld_0);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_0[0 + _pair * 2])[0]), \"=f\"((&_vec_load_0[0 + _pair * 2])[1])\n : \"r\"(_vpairs_0[_pair]));\n }\n }\n float _vec_load_1[4];\n {\n uint2 _vld_1;\n _vld_1 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 512 + d_base) + 0);\n uint32_t* _vpairs_1 = reinterpret_cast<uint32_t*>(&_vld_1);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_1[0 + _pair * 2])[0]), \"=f\"((&_vec_load_1[0 + _pair * 2])[1])\n : \"r\"(_vpairs_1[_pair]));\n }\n }\n float _vec_load_2[4];\n {\n uint2 _vld_2;\n _vld_2 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 1024 + d_base) + 0);\n uint32_t* _vpairs_2 = reinterpret_cast<uint32_t*>(&_vld_2);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_2[0 + _pair * 2])[0]), \"=f\"((&_vec_load_2[0 + _pair * 2])[1])\n : \"r\"(_vpairs_2[_pair]));\n }\n }\n float _vec_load_3[4];\n {\n uint2 _vld_3;\n _vld_3 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 1536 + d_base) + 0);\n uint32_t* _vpairs_3 = reinterpret_cast<uint32_t*>(&_vld_3);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_3[0 + _pair * 2])[0]), \"=f\"((&_vec_load_3[0 + _pair * 2])[1])\n : \"r\"(_vpairs_3[_pair]));\n }\n }\n float _shfl_0;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_0) : \"f\"(normalized_weight), \"r\"(0));\n float weight0 = _shfl_0;\n float _shfl_1;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_1) : \"f\"(normalized_weight), \"r\"(1));\n float weight1 = _shfl_1;\n float _shfl_2;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_2) : \"f\"(normalized_weight), \"r\"(2));\n float weight2 = _shfl_2;\n float _shfl_3;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_3) : \"f\"(normalized_weight), \"r\"(3));\n float weight3 = _shfl_3;\n #pragma unroll\n for (int elem_1 = 0; elem_1 < 4; elem_1++) {\n acc[elem_1] = acc[elem_1] + weight0 * _vec_load_0[elem_1];\n acc[elem_1] = acc[elem_1] + weight1 * _vec_load_1[elem_1];\n acc[elem_1] = acc[elem_1] + weight2 * _vec_load_2[elem_1];\n acc[elem_1] = acc[elem_1] + weight3 * _vec_load_3[elem_1];\n }\n } else if (num_splits == 3) {\n float _vec_load_4[4];\n {\n uint2 _vld_4;\n _vld_4 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + d_base) + 0);\n uint32_t* _vpairs_4 = reinterpret_cast<uint32_t*>(&_vld_4);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_4[0 + _pair * 2])[0]), \"=f\"((&_vec_load_4[0 + _pair * 2])[1])\n : \"r\"(_vpairs_4[_pair]));\n }\n }\n float _vec_load_5[4];\n {\n uint2 _vld_5;\n _vld_5 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 512 + d_base) + 0);\n uint32_t* _vpairs_5 = reinterpret_cast<uint32_t*>(&_vld_5);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_5[0 + _pair * 2])[0]), \"=f\"((&_vec_load_5[0 + _pair * 2])[1])\n : \"r\"(_vpairs_5[_pair]));\n }\n }\n float _vec_load_6[4];\n {\n uint2 _vld_6;\n _vld_6 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 1024 + d_base) + 0);\n uint32_t* _vpairs_6 = reinterpret_cast<uint32_t*>(&_vld_6);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_6[0 + _pair * 2])[0]), \"=f\"((&_vec_load_6[0 + _pair * 2])[1])\n : \"r\"(_vpairs_6[_pair]));\n }\n }\n float _shfl_4;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_4) : \"f\"(normalized_weight), \"r\"(0));\n float weight0_1 = _shfl_4;\n float _shfl_5;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_5) : \"f\"(normalized_weight), \"r\"(1));\n float weight1_1 = _shfl_5;\n float _shfl_6;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_6) : \"f\"(normalized_weight), \"r\"(2));\n float weight2_1 = _shfl_6;\n #pragma unroll\n for (int elem_2 = 0; elem_2 < 4; elem_2++) {\n acc[elem_2] = acc[elem_2] + weight0_1 * _vec_load_4[elem_2];\n acc[elem_2] = acc[elem_2] + weight1_1 * _vec_load_5[elem_2];\n acc[elem_2] = acc[elem_2] + weight2_1 * _vec_load_6[elem_2];\n }\n } else {\n #pragma unroll 5\n for (int split = 0; split < num_splits; split++) {\n float _vec_load_7[4];\n {\n uint2 _vld_7;\n _vld_7 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + split * 512 + d_base) + 0);\n uint32_t* _vpairs_7 = reinterpret_cast<uint32_t*>(&_vld_7);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_7[0 + _pair * 2])[0]), \"=f\"((&_vec_load_7[0 + _pair * 2])[1])\n : \"r\"(_vpairs_7[_pair]));\n }\n }\n float _shfl_7;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_7) : \"f\"(normalized_weight), \"r\"(split));\n float weight = _shfl_7;\n #pragma unroll\n for (int elem_3 = 0; elem_3 < 4; elem_3++) {\n acc[elem_3] = acc[elem_3] + weight * _vec_load_7[elem_3];\n }\n }\n }\n {\n uint2 _pk2;\n __nv_bfloat162* _pk = reinterpret_cast<__nv_bfloat162*>(&_pk2);\n _pk[0] = __floats2bfloat162_rn(acc[0 + 0], acc[0 + 1]);\n _pk[1] = __floats2bfloat162_rn(acc[0 + 2], acc[0 + 3]);\n *reinterpret_cast<uint2*>(&((__nv_bfloat16*)(O + (output_base + d_base)))[0]) = _pk2;\n }\n}\n\n} // extern \"C\"\n"},"after_code":{"kind":"string","value":"/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\ntypedef signed char int8_t;\ntypedef unsigned char uint8_t;\ntypedef unsigned short uint16_t;\ntypedef unsigned int uint32_t;\n#if defined(__CUDACC_RTC__)\ntypedef unsigned long long uint64_t;\n#else\ntypedef unsigned long uint64_t;\n#endif\nstatic_assert(sizeof(uint64_t) == 8, \"Cake requires an LP64 CUDA host ABI\");\ntypedef signed int int32_t;\ntypedef short int int16_t;\nstruct __align__(64) CakeTensorMap64 { uint64_t opaque[16]; };\nstatic_assert(sizeof(CakeTensorMap64) == 128, \"64-aligned tensor-map ABI size\");\nstatic_assert(alignof(CakeTensorMap64) == 64, \"64-aligned tensor-map ABI alignment\");\n\n#if defined(__CUDACC_RTC__)\ntypedef struct __align__(128) { uint64_t opaque[16]; } CUtensorMap;\n#else\n#include <cuda.h>\n#endif\n\nstatic_assert(sizeof(CUtensorMap) == 128, \"CUtensorMap CUDA ABI must be 128 bytes\");\n#include <cuda_bf16.h>\n#include <cuda_fp8.h>\n\n__device__ __forceinline__ int make_warp_uniform(int x) {\n int result;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;\"\n : \"=r\"(result) : \"r\"(x));\n return result;\n}\n\n#define CAKE_INF CUDART_INF_F\n#define NUM_MAIN_STAGES 1\n#define THREADS 128\n\n#include <math_constants.h>\n\n__device__ __forceinline__ float approx_exp2(float x) {\n float y;\n asm(\"ex2.approx.ftz.f32 %0, %1;\" : \"=f\"(y) : \"f\"(x));\n return y;\n}\n\n\n__device__ __forceinline__ float approx_rcp(float x) {\n float y;\n asm(\"rcp.approx.ftz.f32 %0, %1;\" : \"=f\"(y) : \"f\"(x));\n return y;\n}\n\n\n__device__ __forceinline__ float max_noftz(float a, float b) {\n float c;\n asm(\"max.f32 %0, %1, %2;\" : \"=f\"(c) : \"f\"(a), \"f\"(b));\n return c;\n}\n\nextern \"C\" {\n\n__global__ __launch_bounds__(128) void\nkernel_cake_dsv4_ff2e22a8db18dbc0c76e(__nv_bfloat16* __restrict__ partial_O, float* __restrict__ partial_lse, __nv_bfloat16* __restrict__ O, int num_heads, int num_splits)\n{\n const int tid = threadIdx.x;\n const int warp = make_warp_uniform(tid / 32);\n const int lane = tid % 32;\n\n\n const int bid = blockIdx.x;\n const int num_bids = gridDim.x;\n\n const int cta_rank = 0;\n\n // === Task calls (dependency order) ===\n int query_idx = blockIdx.x;\n int head_idx = blockIdx.y;\n int stat_base = (query_idx * num_heads + head_idx) * num_splits;\n float local_lse = -CAKE_INF;\n if (lane < num_splits) {\n local_lse = partial_lse[stat_base + lane];\n }\n float _warp_reduce_0 = local_lse;\n #pragma unroll\n for (int offset = 16; offset > 0; offset >>= 1)\n _warp_reduce_0 = max_noftz(_warp_reduce_0, __shfl_xor_sync(0xFFFFFFFF, _warp_reduce_0, offset));\n float global_max = _warp_reduce_0;\n float local_weight = 0.0f;\n if (lane < num_splits) {\n float _exp2_0 = approx_exp2(local_lse - global_max);\n local_weight = ((local_lse == -CAKE_INF) ? 0.0f : _exp2_0);\n }\n float _warp_reduce_1 = local_weight;\n #pragma unroll\n for (int offset = 16; offset > 0; offset >>= 1)\n _warp_reduce_1 += __shfl_xor_sync(0xFFFFFFFF, _warp_reduce_1, offset);\n float global_sum = _warp_reduce_1;\n float _rcp_0 = approx_rcp(global_sum);\n float normalized_weight = ((global_sum > 0.0f) ? local_weight * _rcp_0 : 0.0f);\n int partial_base = stat_base * 512;\n int output_base = (query_idx * num_heads + head_idx) * 512;\n int d_base = tid * 4;\n float acc[4];\n #pragma unroll\n for (int elem = 0; elem < 4; elem++) {\n acc[elem] = 0.0f;\n }\n if (num_splits == 4) {\n float _vec_load_0[4];\n {\n uint2 _vld_0;\n _vld_0 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + d_base) + 0);\n uint32_t* _vpairs_0 = reinterpret_cast<uint32_t*>(&_vld_0);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_0[0 + _pair * 2])[0]), \"=f\"((&_vec_load_0[0 + _pair * 2])[1])\n : \"r\"(_vpairs_0[_pair]));\n }\n }\n float _vec_load_1[4];\n {\n uint2 _vld_1;\n _vld_1 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 512 + d_base) + 0);\n uint32_t* _vpairs_1 = reinterpret_cast<uint32_t*>(&_vld_1);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_1[0 + _pair * 2])[0]), \"=f\"((&_vec_load_1[0 + _pair * 2])[1])\n : \"r\"(_vpairs_1[_pair]));\n }\n }\n float _vec_load_2[4];\n {\n uint2 _vld_2;\n _vld_2 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 1024 + d_base) + 0);\n uint32_t* _vpairs_2 = reinterpret_cast<uint32_t*>(&_vld_2);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_2[0 + _pair * 2])[0]), \"=f\"((&_vec_load_2[0 + _pair * 2])[1])\n : \"r\"(_vpairs_2[_pair]));\n }\n }\n float _vec_load_3[4];\n {\n uint2 _vld_3;\n _vld_3 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 1536 + d_base) + 0);\n uint32_t* _vpairs_3 = reinterpret_cast<uint32_t*>(&_vld_3);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_3[0 + _pair * 2])[0]), \"=f\"((&_vec_load_3[0 + _pair * 2])[1])\n : \"r\"(_vpairs_3[_pair]));\n }\n }\n float _shfl_0 = __shfl_sync(0xFFFFFFFF, normalized_weight, 0);\n float weight0 = _shfl_0;\n float _shfl_1 = __shfl_sync(0xFFFFFFFF, normalized_weight, 1);\n float weight1 = _shfl_1;\n float _shfl_2 = __shfl_sync(0xFFFFFFFF, normalized_weight, 2);\n float weight2 = _shfl_2;\n float _shfl_3 = __shfl_sync(0xFFFFFFFF, normalized_weight, 3);\n float weight3 = _shfl_3;\n #pragma unroll\n for (int elem_1 = 0; elem_1 < 4; elem_1++) {\n acc[elem_1] = acc[elem_1] + weight0 * _vec_load_0[elem_1];\n acc[elem_1] = acc[elem_1] + weight1 * _vec_load_1[elem_1];\n acc[elem_1] = acc[elem_1] + weight2 * _vec_load_2[elem_1];\n acc[elem_1] = acc[elem_1] + weight3 * _vec_load_3[elem_1];\n }\n } else if (num_splits == 3) {\n float _vec_load_4[4];\n {\n uint2 _vld_4;\n _vld_4 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + d_base) + 0);\n uint32_t* _vpairs_4 = reinterpret_cast<uint32_t*>(&_vld_4);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_4[0 + _pair * 2])[0]), \"=f\"((&_vec_load_4[0 + _pair * 2])[1])\n : \"r\"(_vpairs_4[_pair]));\n }\n }\n float _vec_load_5[4];\n {\n uint2 _vld_5;\n _vld_5 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 512 + d_base) + 0);\n uint32_t* _vpairs_5 = reinterpret_cast<uint32_t*>(&_vld_5);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_5[0 + _pair * 2])[0]), \"=f\"((&_vec_load_5[0 + _pair * 2])[1])\n : \"r\"(_vpairs_5[_pair]));\n }\n }\n float _vec_load_6[4];\n {\n uint2 _vld_6;\n _vld_6 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 1024 + d_base) + 0);\n uint32_t* _vpairs_6 = reinterpret_cast<uint32_t*>(&_vld_6);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_6[0 + _pair * 2])[0]), \"=f\"((&_vec_load_6[0 + _pair * 2])[1])\n : \"r\"(_vpairs_6[_pair]));\n }\n }\n float _shfl_4 = __shfl_sync(0xFFFFFFFF, normalized_weight, 0);\n float weight0_1 = _shfl_4;\n float _shfl_5 = __shfl_sync(0xFFFFFFFF, normalized_weight, 1);\n float weight1_1 = _shfl_5;\n float _shfl_6 = __shfl_sync(0xFFFFFFFF, normalized_weight, 2);\n float weight2_1 = _shfl_6;\n #pragma unroll\n for (int elem_2 = 0; elem_2 < 4; elem_2++) {\n acc[elem_2] = acc[elem_2] + weight0_1 * _vec_load_4[elem_2];\n acc[elem_2] = acc[elem_2] + weight1_1 * _vec_load_5[elem_2];\n acc[elem_2] = acc[elem_2] + weight2_1 * _vec_load_6[elem_2];\n }\n } else {\n #pragma unroll 5\n for (int split = 0; split < num_splits; split++) {\n float _vec_load_7[4];\n {\n uint2 _vld_7;\n _vld_7 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + split * 512 + d_base) + 0);\n uint32_t* _vpairs_7 = reinterpret_cast<uint32_t*>(&_vld_7);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_7[0 + _pair * 2])[0]), \"=f\"((&_vec_load_7[0 + _pair * 2])[1])\n : \"r\"(_vpairs_7[_pair]));\n }\n }\n float _shfl_7 = __shfl_sync(0xFFFFFFFF, normalized_weight, split);\n float weight = _shfl_7;\n #pragma unroll\n for (int elem_3 = 0; elem_3 < 4; elem_3++) {\n acc[elem_3] = acc[elem_3] + weight * _vec_load_7[elem_3];\n }\n }\n }\n {\n uint2 _pk2;\n __nv_bfloat162* _pk = reinterpret_cast<__nv_bfloat162*>(&_pk2);\n _pk[0] = __floats2bfloat162_rn(acc[0 + 0], acc[0 + 1]);\n _pk[1] = __floats2bfloat162_rn(acc[0 + 2], acc[0 + 3]);\n *reinterpret_cast<uint2*>(&((__nv_bfloat16*)(O + (output_base + d_base)))[0]) = _pk2;\n }\n}\n\n} // extern \"C\"\n"},"diff":{"kind":"string","value":"--- csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_kernel.cu\n+++ csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_kernel.cu\n@@ -26,12 +26,9 @@\n static_assert(sizeof(uint64_t) == 8, \"Cake requires an LP64 CUDA host ABI\");\n typedef signed int int32_t;\n typedef short int int16_t;\n-struct __align__(128) CakeTensorMap { uint64_t opaque[16]; };\n struct __align__(64) CakeTensorMap64 { uint64_t opaque[16]; };\n static_assert(sizeof(CakeTensorMap64) == 128, \"64-aligned tensor-map ABI size\");\n static_assert(alignof(CakeTensorMap64) == 64, \"64-aligned tensor-map ABI alignment\");\n-template <int N>\n-struct __align__(128) CakeTensorMapPack { CakeTensorMap maps[N]; };\n \n #if defined(__CUDACC_RTC__)\n typedef struct __align__(128) { uint64_t opaque[16]; } CUtensorMap;\n@@ -40,7 +37,6 @@\n #endif\n \n static_assert(sizeof(CUtensorMap) == 128, \"CUtensorMap CUDA ABI must be 128 bytes\");\n-static_assert(alignof(CakeTensorMap) >= alignof(CUtensorMap), \"CakeTensorMap alignment must cover the CUtensorMap CUDA ABI\");\n #include <cuda_bf16.h>\n #include <cuda_fp8.h>\n \n@@ -80,7 +76,7 @@\n extern \"C\" {\n \n __global__ __launch_bounds__(128) void\n-kernel_cake_dsv4_697c8662eb01c8d6bd50(__nv_bfloat16* __restrict__ partial_O, float* __restrict__ partial_lse, __nv_bfloat16* __restrict__ O, int num_heads, int num_splits)\n+kernel_cake_dsv4_ff2e22a8db18dbc0c76e(__nv_bfloat16* __restrict__ partial_O, float* __restrict__ partial_lse, __nv_bfloat16* __restrict__ O, int num_heads, int num_splits)\n {\n const int tid = threadIdx.x;\n const int warp = make_warp_uniform(tid / 32);\n@@ -190,17 +186,13 @@\n : \"r\"(_vpairs_3[_pair]));\n }\n }\n- float _shfl_0;\n- asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_0) : \"f\"(normalized_weight), \"r\"(0));\n+ float _shfl_0 = __shfl_sync(0xFFFFFFFF, normalized_weight, 0);\n float weight0 = _shfl_0;\n- float _shfl_1;\n- asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_1) : \"f\"(normalized_weight), \"r\"(1));\n+ float _shfl_1 = __shfl_sync(0xFFFFFFFF, normalized_weight, 1);\n float weight1 = _shfl_1;\n- float _shfl_2;\n- asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_2) : \"f\"(normalized_weight), \"r\"(2));\n+ float _shfl_2 = __shfl_sync(0xFFFFFFFF, normalized_weight, 2);\n float weight2 = _shfl_2;\n- float _shfl_3;\n- asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_3) : \"f\"(normalized_weight), \"r\"(3));\n+ float _shfl_3 = __shfl_sync(0xFFFFFFFF, normalized_weight, 3);\n float weight3 = _shfl_3;\n #pragma unroll\n for (int elem_1 = 0; elem_1 < 4; elem_1++) {\n@@ -258,14 +250,11 @@\n : \"r\"(_vpairs_6[_pair]));\n }\n }\n- float _shfl_4;\n- asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_4) : \"f\"(normalized_weight), \"r\"(0));\n+ float _shfl_4 = __shfl_sync(0xFFFFFFFF, normalized_weight, 0);\n float weight0_1 = _shfl_4;\n- float _shfl_5;\n- asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_5) : \"f\"(normalized_weight), \"r\"(1));\n+ float _shfl_5 = __shfl_sync(0xFFFFFFFF, normalized_weight, 1);\n float weight1_1 = _shfl_5;\n- float _shfl_6;\n- asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_6) : \"f\"(normalized_weight), \"r\"(2));\n+ float _shfl_6 = __shfl_sync(0xFFFFFFFF, normalized_weight, 2);\n float weight2_1 = _shfl_6;\n #pragma unroll\n for (int elem_2 = 0; elem_2 < 4; elem_2++) {\n@@ -292,8 +281,7 @@\n : \"r\"(_vpairs_7[_pair]));\n }\n }\n- float _shfl_7;\n- asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_7) : \"f\"(normalized_weight), \"r\"(split));\n+ float _shfl_7 = __shfl_sync(0xFFFFFFFF, normalized_weight, split);\n float weight = _shfl_7;\n #pragma unroll\n for (int elem_3 = 0; elem_3 < 4; elem_3++) {"},"lines_added":{"kind":"number","value":9,"string":"9"},"lines_removed":{"kind":"number","value":21,"string":"21"},"files_in_commit":{"kind":"number","value":7,"string":"7"},"models_mentioned":{"kind":"list like","value":["deepseek"],"string":"[\n \"deepseek\"\n]","isConversational":false},"hardware_mentioned":{"kind":"list like","value":["B200","CPU","GB300","SM100","SM103","SM120"],"string":"[\n \"B200\",\n \"CPU\",\n \"GB300\",\n \"SM100\",\n \"SM103\",\n \"SM120\"\n]","isConversational":false},"speedup_claims":{"kind":"list like","value":["4 x","0.9578x","0.9820x","6 x"],"string":"[\n \"4 x\",\n \"0.9578x\",\n \"0.9820x\",\n \"6 x\"\n]","isConversational":false},"prompt":{"kind":"string","value":"Optimize this cuda kernel file from flashinfer (csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_kernel.cu).\n\nGoal: perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative)\nTarget hardware: B200, CPU, GB300, SM100, SM103, SM120\nTarget models: deepseek\n\nCurrent file:\n```cuda\n/*\n * Copyright (c) 2023 by FlashInfer team.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\ntypedef signed char int8_t;\ntypedef unsigned char uint8_t;\ntypedef unsigned short uint16_t;\ntypedef unsigned int uint32_t;\n#if defined(__CUDACC_RTC__)\ntypedef unsigned long long uint64_t;\n#else\ntypedef unsigned long uint64_t;\n#endif\nstatic_assert(sizeof(uint64_t) == 8, \"Cake requires an LP64 CUDA host ABI\");\ntypedef signed int int32_t;\ntypedef short int int16_t;\nstruct __align__(128) CakeTensorMap { uint64_t opaque[16]; };\nstruct __align__(64) CakeTensorMap64 { uint64_t opaque[16]; };\nstatic_assert(sizeof(CakeTensorMap64) == 128, \"64-aligned tensor-map ABI size\");\nstatic_assert(alignof(CakeTensorMap64) == 64, \"64-aligned tensor-map ABI alignment\");\ntemplate <int N>\nstruct __align__(128) CakeTensorMapPack { CakeTensorMap maps[N]; };\n\n#if defined(__CUDACC_RTC__)\ntypedef struct __align__(128) { uint64_t opaque[16]; } CUtensorMap;\n#else\n#include <cuda.h>\n#endif\n\nstatic_assert(sizeof(CUtensorMap) == 128, \"CUtensorMap CUDA ABI must be 128 bytes\");\nstatic_assert(alignof(CakeTensorMap) >= alignof(CUtensorMap), \"CakeTensorMap alignment must cover the CUtensorMap CUDA ABI\");\n#include <cuda_bf16.h>\n#include <cuda_fp8.h>\n\n__device__ __forceinline__ int make_warp_uniform(int x) {\n int result;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, 0, 0x1F, 0xFFFFFFFF;\"\n : \"=r\"(result) : \"r\"(x));\n return result;\n}\n\n#define CAKE_INF CUDART_INF_F\n#define NUM_MAIN_STAGES 1\n#define THREADS 128\n\n#include <math_constants.h>\n\n__device__ __forceinline__ float approx_exp2(float x) {\n float y;\n asm(\"ex2.approx.ftz.f32 %0, %1;\" : \"=f\"(y) : \"f\"(x));\n return y;\n}\n\n\n__device__ __forceinline__ float approx_rcp(float x) {\n float y;\n asm(\"rcp.approx.ftz.f32 %0, %1;\" : \"=f\"(y) : \"f\"(x));\n return y;\n}\n\n\n__device__ __forceinline__ float max_noftz(float a, float b) {\n float c;\n asm(\"max.f32 %0, %1, %2;\" : \"=f\"(c) : \"f\"(a), \"f\"(b));\n return c;\n}\n\nextern \"C\" {\n\n__global__ __launch_bounds__(128) void\nkernel_cake_dsv4_697c8662eb01c8d6bd50(__nv_bfloat16* __restrict__ partial_O, float* __restrict__ partial_lse, __nv_bfloat16* __restrict__ O, int num_heads, int num_splits)\n{\n const int tid = threadIdx.x;\n const int warp = make_warp_uniform(tid / 32);\n const int lane = tid % 32;\n\n\n const int bid = blockIdx.x;\n const int num_bids = gridDim.x;\n\n const int cta_rank = 0;\n\n // === Task calls (dependency order) ===\n int query_idx = blockIdx.x;\n int head_idx = blockIdx.y;\n int stat_base = (query_idx * num_heads + head_idx) * num_splits;\n float local_lse = -CAKE_INF;\n if (lane < num_splits) {\n local_lse = partial_lse[stat_base + lane];\n }\n float _warp_reduce_0 = local_lse;\n #pragma unroll\n for (int offset = 16; offset > 0; offset >>= 1)\n _warp_reduce_0 = max_noftz(_warp_reduce_0, __shfl_xor_sync(0xFFFFFFFF, _warp_reduce_0, offset));\n float global_max = _warp_reduce_0;\n float local_weight = 0.0f;\n if (lane < num_splits) {\n float _exp2_0 = approx_exp2(local_lse - global_max);\n local_weight = ((local_lse == -CAKE_INF) ? 0.0f : _exp2_0);\n }\n float _warp_reduce_1 = local_weight;\n #pragma unroll\n for (int offset = 16; offset > 0; offset >>= 1)\n _warp_reduce_1 += __shfl_xor_sync(0xFFFFFFFF, _warp_reduce_1, offset);\n float global_sum = _warp_reduce_1;\n float _rcp_0 = approx_rcp(global_sum);\n float normalized_weight = ((global_sum > 0.0f) ? local_weight * _rcp_0 : 0.0f);\n int partial_base = stat_base * 512;\n int output_base = (query_idx * num_heads + head_idx) * 512;\n int d_base = tid * 4;\n float acc[4];\n #pragma unroll\n for (int elem = 0; elem < 4; elem++) {\n acc[elem] = 0.0f;\n }\n if (num_splits == 4) {\n float _vec_load_0[4];\n {\n uint2 _vld_0;\n _vld_0 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + d_base) + 0);\n uint32_t* _vpairs_0 = reinterpret_cast<uint32_t*>(&_vld_0);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_0[0 + _pair * 2])[0]), \"=f\"((&_vec_load_0[0 + _pair * 2])[1])\n : \"r\"(_vpairs_0[_pair]));\n }\n }\n float _vec_load_1[4];\n {\n uint2 _vld_1;\n _vld_1 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 512 + d_base) + 0);\n uint32_t* _vpairs_1 = reinterpret_cast<uint32_t*>(&_vld_1);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_1[0 + _pair * 2])[0]), \"=f\"((&_vec_load_1[0 + _pair * 2])[1])\n : \"r\"(_vpairs_1[_pair]));\n }\n }\n float _vec_load_2[4];\n {\n uint2 _vld_2;\n _vld_2 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 1024 + d_base) + 0);\n uint32_t* _vpairs_2 = reinterpret_cast<uint32_t*>(&_vld_2);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_2[0 + _pair * 2])[0]), \"=f\"((&_vec_load_2[0 + _pair * 2])[1])\n : \"r\"(_vpairs_2[_pair]));\n }\n }\n float _vec_load_3[4];\n {\n uint2 _vld_3;\n _vld_3 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 1536 + d_base) + 0);\n uint32_t* _vpairs_3 = reinterpret_cast<uint32_t*>(&_vld_3);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_3[0 + _pair * 2])[0]), \"=f\"((&_vec_load_3[0 + _pair * 2])[1])\n : \"r\"(_vpairs_3[_pair]));\n }\n }\n float _shfl_0;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_0) : \"f\"(normalized_weight), \"r\"(0));\n float weight0 = _shfl_0;\n float _shfl_1;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_1) : \"f\"(normalized_weight), \"r\"(1));\n float weight1 = _shfl_1;\n float _shfl_2;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_2) : \"f\"(normalized_weight), \"r\"(2));\n float weight2 = _shfl_2;\n float _shfl_3;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_3) : \"f\"(normalized_weight), \"r\"(3));\n float weight3 = _shfl_3;\n #pragma unroll\n for (int elem_1 = 0; elem_1 < 4; elem_1++) {\n acc[elem_1] = acc[elem_1] + weight0 * _vec_load_0[elem_1];\n acc[elem_1] = acc[elem_1] + weight1 * _vec_load_1[elem_1];\n acc[elem_1] = acc[elem_1] + weight2 * _vec_load_2[elem_1];\n acc[elem_1] = acc[elem_1] + weight3 * _vec_load_3[elem_1];\n }\n } else if (num_splits == 3) {\n float _vec_load_4[4];\n {\n uint2 _vld_4;\n _vld_4 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + d_base) + 0);\n uint32_t* _vpairs_4 = reinterpret_cast<uint32_t*>(&_vld_4);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_4[0 + _pair * 2])[0]), \"=f\"((&_vec_load_4[0 + _pair * 2])[1])\n : \"r\"(_vpairs_4[_pair]));\n }\n }\n float _vec_load_5[4];\n {\n uint2 _vld_5;\n _vld_5 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 512 + d_base) + 0);\n uint32_t* _vpairs_5 = reinterpret_cast<uint32_t*>(&_vld_5);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_5[0 + _pair * 2])[0]), \"=f\"((&_vec_load_5[0 + _pair * 2])[1])\n : \"r\"(_vpairs_5[_pair]));\n }\n }\n float _vec_load_6[4];\n {\n uint2 _vld_6;\n _vld_6 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + 1024 + d_base) + 0);\n uint32_t* _vpairs_6 = reinterpret_cast<uint32_t*>(&_vld_6);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_6[0 + _pair * 2])[0]), \"=f\"((&_vec_load_6[0 + _pair * 2])[1])\n : \"r\"(_vpairs_6[_pair]));\n }\n }\n float _shfl_4;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_4) : \"f\"(normalized_weight), \"r\"(0));\n float weight0_1 = _shfl_4;\n float _shfl_5;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_5) : \"f\"(normalized_weight), \"r\"(1));\n float weight1_1 = _shfl_5;\n float _shfl_6;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_6) : \"f\"(normalized_weight), \"r\"(2));\n float weight2_1 = _shfl_6;\n #pragma unroll\n for (int elem_2 = 0; elem_2 < 4; elem_2++) {\n acc[elem_2] = acc[elem_2] + weight0_1 * _vec_load_4[elem_2];\n acc[elem_2] = acc[elem_2] + weight1_1 * _vec_load_5[elem_2];\n acc[elem_2] = acc[elem_2] + weight2_1 * _vec_load_6[elem_2];\n }\n } else {\n #pragma unroll 5\n for (int split = 0; split < num_splits; split++) {\n float _vec_load_7[4];\n {\n uint2 _vld_7;\n _vld_7 = *reinterpret_cast<const uint2*>(partial_O + (partial_base + split * 512 + d_base) + 0);\n uint32_t* _vpairs_7 = reinterpret_cast<uint32_t*>(&_vld_7);\n #pragma unroll\n for (int _pair = 0; _pair < 2; _pair++) {\n asm volatile(\n \"{\\n\\t\"\n \"shl.b32 %0, %2, 16;\\n\\t\"\n \"and.b32 %1, %2, 0xffff0000;\\n\\t\"\n \"}\\n\"\n : \"=f\"((&_vec_load_7[0 + _pair * 2])[0]), \"=f\"((&_vec_load_7[0 + _pair * 2])[1])\n : \"r\"(_vpairs_7[_pair]));\n }\n }\n float _shfl_7;\n asm volatile(\"shfl.sync.idx.b32 %0, %1, %2, 0x1f, 0xffffffff;\" : \"=f\"(_shfl_7) : \"f\"(normalized_weight), \"r\"(split));\n float weight = _shfl_7;\n #pragma unroll\n for (int elem_3 = 0; elem_3 < 4; elem_3++) {\n acc[elem_3] = acc[elem_3] + weight * _vec_load_7[elem_3];\n }\n }\n }\n {\n uint2 _pk2;\n __nv_bfloat162* _pk = reinterpret_cast<__nv_bfloat162*>(&_pk2);\n _pk[0] = __floats2bfloat162_rn(acc[0 + 0], acc[0 + 1]);\n _pk[1] = __floats2bfloat162_rn(acc[0 + 2], acc[0 + 3]);\n *reinterpret_cast<uint2*>(&((__nv_bfloat16*)(O + (output_base + d_base)))[0]) = _pk2;\n }\n}\n\n} // extern \"C\"\n\n```\n\nRespond with one or more edits to the file, each in exactly this format:\n<<<<<<< SEARCH\n(exact, contiguous lines copied from the current file)\n=======\n(the replacement lines)\n>>>>>>> REPLACE"},"pr_body":{"kind":"string","value":"## Summary\n\nRounds 7-17 of the DSv4 sparse-MLA Cake backend (`backend=\"cake\"`, SM100 + SM103) as one cumulative change on the #5920 layout (per-variant bindings taking their checks from `tvm_ffi_utils.h`, shared sources under `common/`, `run_sequence`, the host's direct variant launches). Main carries round 6 (#5700) for this family; the eight per-round PRs stacked on it (#5728, #5742, #5845, #5854, #5879, #5946, #5973, #5999) and the held round 15-17 fork branches were closed in favour of this PR. Programs: whole-family regeneration of the `cake_dsv4` sources from Cake !1037's tree (the round-17 kernel tree `c7284461b47` merged into Cake main, rendered by main's codegen) for sm_103a and sm_100a through the exporter's #5920-layout path, replacing the round-6 sources. Host: the four round 11-14 host changes re-expressed on main's host (descriptor pool and `run_sequence` unchanged), plus the round tests ported onto main's collapsed tests.\n\nNumerics rule (every round): no precision-level change anywhere (same tolerances, same or higher-precision intermediates). Rounds that change output bits are called out below; every other program is bit-identical to its predecessor (NaN-poisoned bit compare on the measured cells).\n\n### What changed per round\n\n- Round 7 ([Cake !1037](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1037), was #5728): FP8/H64 single-CTA SWA (class K1): single-pass softmax with the TMEM-alias correctness fix (Q x400 over-tolerance elements 398..64359 -> 0) and softmax warps helping the first K-tile gather, -0.7..-0.85 us per row; FP8/H64 cluster / wide one-partition: V4 gather owner, whole 128-key tile per cluster CTA with an f32 end merge over DSMEM (bits change by merge grouping), -0.13..-0.70 us; H8/H16 decode: loader warps skip the padded gather rows, up to -1.6 us.\n- Round 8 ([Cake !1043](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1043), was #5742): FP8/H64 wide one-partition in the whole-tile form with the no-LSE epilogue, -0.8..-0.9 us per row (bits change by merge grouping); K1 row max through `tcgen05.ld.red.max` on SM103a / full-tile fast max on SM100a, -0.45..-0.83 us; H8/H16 index-row L2 prefetch, -0.10..-0.26 us; BF16 one-tile SWA chain K stage-0 gather before the index barrier, -0.03..-0.10 us.\n- Round 9 ([Cake !1061](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1061), was #5845): six bit-identical levers: coalesced final-O epilogue of the fp8 H64 M64 persistent body (-7..-18 % on the six M64 rows), K4 first-tile gather split across the three warp roles (-2.5..-2.7 %), bf16 H64 guard by-value TMA descriptor ABI on sm_103a, K1 8-warp O epilogue drain, H/I SwapsAb page pair 0 from page-loader registers, class-O fp8 H64 5-slot KV ring (-12 % / -7..-9 %).\n- Round 10 ([Cake !1066](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1066), was #5854): bit-identical: class-O fp8 H64 split O-accumulator handshake + six-slot K ring with early Q release (-8..-10 %), bf16 H64 guard mask-flag pre-decode + transposed O store (-3.1..-4.1 %), H/I SwapsAb index-row L2 prefetch on sm_103a; the h8/h16 bindings gain the `num_query_tokens` scalar the host already passes by name.\n- Round 11 ([Cake !1085](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1085), was #5879): seven bit-identical levers (fp8 H64 M64 gated box-TMA K gather + per-stage O split credit; fp8 K4 last-tile key split; fp8 H128 persistent epilogue load-ahead-4 on sm_100a + deferred staging wait; bf16 H128 row-first elected multi-warp gather issue; bf16 H64 guard class-conditional gather4 issue) plus three contract-identical correctness fixes (split-FP8 P stage 1024 B-aligned at SMEM 175104 in the K4 / M64 / fp8 H128 persistent programs; guarded 16 B vector loads in the top-k index producers). **Host:** `out=None` is allocated in `run_cake_dsv4` after routing and placed at `base % 4 KiB == 0x800` on the six routes where the phase law was measured (`allocate_cake_dsv4_output`, `cake_dsv4_out_phase`, `out_shape`); caller-provided `out` and the other routes are unchanged. New `tests/mla/test_cake_dsv4_out_placement.py`.\n- Round 12 ([Cake !1126](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1126), was #5946): bf16 H128 row-first / prefill O epilogue `tcgen05.wait::ld` per 32-column TMEM load (-1.4..-6.0 %); bf16 H32 top-k mixed-pool split assignment (re-associates f32 partials by split geometry, strictly more precise: cells > 1 ulp vs fp32 118.8k -> ~630) and active_topk mask before the s_full wait (-3.5..-5.2 %); fp8 K4 wide quarter-tile tail + helper-correction readback pre-issue (-2.0..-4.1 %); **Host:** the fp8 H64 M64 body is two exported programs selected by the item width in `_route` (`_fp8_h64_m64_program`: `fp8_h64_prefill_source_persistent_m64` for `sparse_topk == 128`, `..._m64_multi_tile` otherwise; same ABI, same bits).\n- Round 13 ([Cake !1152](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1152), was #5973): bit-identical: **Host + program:** bf16 H128 row-first rows with 17-37 tokens run the new `bf16_h128_topk128x_row_first_vsplit` program (two 2-CTA clusters per token gathering only their N256 V half; grid 4 x tokens; `_BF16_ROW_FIRST_V_HALF_SPLIT_MAX_TOKENS = 37`), hardening-000025 -8.4 % GB300 / -7.8 % B200; fp8 K4 whole-tile `st.async ... complete_tx` peer O push + four-stage chunked merge (-0.70..-0.74 us); fp8 H64 M64 multi-tile next-item Q TMA after the CLC response (-0.4..-1.5 %); fp8 H128 persistent partial-o accumulation before the final `o_full` wait (-0.3..-1.1 %).\n- Round 14 ([Cake !1168](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1168), was #5999): bit-identical: bf16 H128 row-first (owner + vsplit) index warp issues its nine index loads before the nine `st.shared` passes (-5.0..-6.6 %); bf16 H64 guard program stores O through a TMA tensor map from per-warp staging (-0.9..-3.5 %) -- **Host:** the explicit `\"O\": \"O\"` entry in `_TMA_SOURCE_ALIASES` so the guard binding's `(\"tma_buffer\", \"O\")` resolves; fp8 H128 persistent two-box pipelined epilogue drain on sm_103a.\n- Round 15 ([Cake !1177](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1177), held on the layout decision): bit-identical: the two-box pipelined epilogue drain becomes the default for the sm_100a fp8 H128 lane-gather variant (>= 128 work items); no host change.\n- Round 16 ([Cake !1182](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1182), held): bit-identical: fp8 H64 M64 multi-tile softmax -1 ballot hoisted above the `s_full` join (-0.22..-0.56 us); bf16 H64 guard O store split per V stage so the stage-0 O drain overlaps PV1 (-0.19..-0.35 us); no host change.\n- Round 17 ([Cake !1186](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1186), held): bit-identical: bf16 H128 row-first programs (owner + vsplit) hoist the swa / compressed V table select out of the four elected gather groups (hardening-000025 -0.593 us GB300 / -0.800 us B200, hardening-000031 -0.160 / -0.751 us); no host change. Round 18 ([Cake !1193](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1193)) shipped no program change (ledger only).\n\n### Layout (#5920) notes\n\n- Per-arch registry schema unchanged: arch-prefixed `sources`, `arg_plan` as `_PLAN_<LABEL> [+ _SLAB] + _GRID`, `tma_workspace_bytes` only where non-zero, reducers shared through `common/` where both architectures compile the same kernel (`split_reduce`, `bf16_h64_compressed_reduce`); the split-5 reducers stay per-arch under the one key `bf16_h128_split5_reduce` (sm_103a grid `(tokens, heads / 4, 1)`, sm_100a `(tokens, heads, 1)`, as main's launch test pins).\n- Two new variant keys per architecture: `bf16_h128_topk128x_row_first_vsplit`, `fp8_h64_prefill_source_persistent_m64_multi_tile` (27 variants per arch).\n- No family bindings; two-stage routes go through `run_sequence`; the host's descriptor pool is untouched.\n\n### Variant / file diff vs main `a12173ca0`\n\n- Per-arch registrations: 27 variants each (main had 25): new keys `bf16_h128_topk128x_row_first_vsplit` (round 13, host-routed for 17-37-token rows) and `fp8_h64_prefill_source_persistent_m64_multi_tile` (round 12). Loader `flashinfer/jit/cake_dsv4.py`: data-only edits (registrations, plan/grid constants, source lists); loader functions and `__all__` untouched.\n- Files: `common/` 30 (4 before), `sm_100a/` 24 (46 before), `sm_103a/` 24 (46 before); `sm_120a/` and every other family untouched. Diff vs main: 107 files, +17906 / -62404.\n- Fold disclosure: the exporter serves a variant from `common/` when its kernel + binding sources are byte-identical on both architectures modulo hash tokens. With the rounds 7-18 kernel tree rendered by current Cake main codegen, 15 of the 27 variants fold (bf16_h128_swa128, bf16_h128_topk128x_row_first, …_vsplit, bf16_h128_topk128x_split4_sm100, bf16_h16_h32_swa128_v44, bf16_h32_topk128x_early_v47, bf16_h64_compressed_q8_v38, bf16_h64_compressed_reduce, bf16_h64_guard_q_tma_batch_r25, bf16_h64_prefill, fp8_h64_prefill_source_persistent_m64, …_m64_multi_tile, fp8_h64_source_exact, fp8_lowhead_h64, split_reduce); 12 stay per-arch. Each architecture still compiles its own module from the shared source.\n- Host: the six host/test commits below the export commits port the rounds 13-17 host changes (vsplit route, descriptor-pool and `run_sequence` plumbing, output-placement test) onto the #5920 host; `cake_dsv4_host_shim.h` is unreferenced by the regenerated bindings and left in place.\n\n## Validation\n\nBoth architectures measured on the exported programs of this branch (GB300 = sm_103a commit `08d1c3c8`, whose sm_103a sources are byte-identical modulo hash tokens to this head; B200 = this head `4146373e`). Baseline = FlashInfer trtllm-gen default path of the same clone. Paired CUPTI sweeps (cold L2, active-union median), same-process; same-GPU ABBA = legs A1 B1 B2 A2 on one GPU, A = this branch, B = the round-17 fork head `dbf86c4d6` (quantum q = 0.032 us).\n\n| | GB300 (sm_103a) | B200 (sm_100a) |\n|---|---|---|\n| production export: 134 shapes timed + correct vs the Cake source programs (receipts) | 133/134 pass, source/export geomean 1.0022, trtllm-gen/export 1.4948 (94 canonical); hardening-000004 timing-only 0.9578x (correctness pass; retained first-run receipt — an independent full run on another node measured it 0.9820x pass; the same-GPU ABBA below shows the row 0.16 us *faster* than round 17 in both orders) — JHB 802461 nvl72d426-T11, 4 GPUs | 134/134 pass, source/export 1.0037 (min h004 0.9845), trtllm-gen/export 1.4404 — NSC 2138957, 4 GPUs |\n| **94 canonical rows faster than the default path** | 94/94 correct, every row > 1.0: geomean 1.4617, min 1.1191 (decode-000051) | 94/94 correct, every row > 1.0: geomean 1.4447, min 1.1774 (decode-000034) |\n| 40 hardening rows faster than the default path | 40/40 correct, every row > 1.0: geomean 1.4857, min 1.1068 (hardening-000004) | 40/40 correct, every row > 1.0: geomean 1.4396, min 1.1357 (hardening-000023) |\n| all 134 rows | geomean 1.4688, min 1.1068, 0 rows <= 1.0 | geomean 1.4432, min 1.1357, 0 rows <= 1.0 |\n| no row > 2 % slower than the round-17 programs (same-GPU ABBA vs `dbf86c4d6`) | pin rows (8): 0 slower, h004 -0.160 us / 064 -0.100 / 065 -0.070 faster both orders, rest within 1 q; hardening 00-39 (40): 0 rows beyond 1.25 q (h034 +0.040 us = +0.13 %, h037 +0.040 us = +0.07 %; h020 -0.580 us); canonical 94: 94 rows in 3 parts (`68a1e0f7` `1e1726bf` `59741678`): 134-row totals = 18 rows slower in both orders, 27 faster in both orders, geomean A/B 0.9956; **1 row above +2 %: decode-000056 +0.350 us (6.53 -> 6.88 us, +5.4 %, program fp8_h16_source_exact)**, next largest +1.7 % (decode-000074/077); largest gains decode-000078 -7.1 %, hardening-000020 -6.9 %, decode-000006/018 -6.7 %, 081 -6.6 %, prefill-style-000086 -2.7 %. Attribution of decode-000056 (Cake round 19, measured on another GB300 node): **not a codegen or ABI effect**. The non-ABI text differences compile to byte-identical SASS on sm_103a (128 regs / 0 spills in every form); A-vs-B replications flip sign between fresh processes of the same install; repeat sampling (5 alternating fresh A/B processes x 3 GPUs) gives this head 6.807 us vs round 17 6.803 us (0.1 q). The kernel (`fp8_h16_source_exact`) has two placement-dependent timing modes ~0.3 us apart that both exports reach; the round-18 cell caught the two installs in different modes. Programs unchanged | pin rows (8): `ea69b60d`: 1 slower both orders = decode-000002 +0.070 us (10.46 us, +0.67 %, 2.2 q); 6 rows timing-identical in all four legs; h031 within its band; hardening 00-39 (40): `0365c256` / `f0fee955` (B200 legs take ~45 min per 20 rows; both steps hit the 3 h step budget during leg A2): 25/40 rows with all four legs, code part <= +0.030 us (<= 1 q) on every one; the 15 rows without A2 have |A1 - B1|, |A1 - B2| <= 0.09 us (h017 -0.09 us = faster); no row > 2 % in any leg; canonical 94: 6 x 16-row parts (`d69139af` `1b42ff9f` `d2cf5268` `49f23a7d` `fedccecc` `c3874f40`, all four legs): 134-row totals = 8 rows slower in both orders (max decode-000002 +0.070 us = +0.67 %, the other seven +0.04..+0.06 us <= 2 q), 0 rows faster in both orders, 112 rows timing-identical or within 1 q, geomean A/B 1.0004; **no row above +2 %**; decode-000056 (the GB300 +5.4 % row) is 6.690 us in all four legs on B200: sm_100a already used the `grid_constant` TMA ABI in round 17, consistent with the GB300 cell being a sampling artefact (see the GB300 column) |\n| `tests/mla/test_cake_dsv4*.py` (GPU, fresh clone of this head) | 320 passed, 4 skipped, 0 failed (`5e70a6c9`, 1 GPU of 802461) | 319 passed, 4 skipped, 1 failed in the full run (`b13c39b1`: `test_cuda_graph_replay_matches_eager[h32-fp8-q1]` at \"eager call allocated\" with memory_allocated *lower* than the baseline, i.e. a GC of earlier tests' tensors during the call); the test re-run in isolation passes 12/12 params (`cb812a81`) |\n| Cake-side gates of the kernel tree (Cake !1037, head `f3108393953`) | 134 rows x all axes 528/528 correct; synccheck 8/8 + memcheck 7/8 rows 0 errors; CPU rule tests 705/705 | same: 528/528; synccheck 8/8 + memcheck 7/8 rows 0 errors; 705/705 |\n\nCross-node note: the sweep medians of this run are not comparable to the round-17 PR numbers (different nodes / clock regime: on GB300 both Cake and trtllm-gen moved +5.0 % / +3.0 % geomean vs the round-17 sweep); the same-GPU ABBA row above is the valid round-over-round comparison.\n\n## Baselines and their source PRs\n\n- trtllm-gen default path: FlashInfer main as of `a12173ca0` (this branch's base; the DSv4 trtllm-gen MLA path is unchanged since `c4cb63534`, the #5879 head: the only commit touching the MLA dispatch files since then is #5983, which adds an SM120 source to `flashinfer/jit/mla.py`; #5854, #5845, #5742, #5728, #5700 before it).\n- Cake round 17: fork branch `cake-772-dsv4-round17` (`dbf86c4d6`, held on the #5920 layout decision); round 16: `cake-772-dsv4-round16` (`45c0b819c`, held); round 15: `cake-772-dsv4-round15` (`1a91f12a9`, held); round 14: #5999 (`e2f7310ee`); round 13: #5973; round 12: #5946; round 11: #5879; round 10: #5854; round 9: #5845; round 8: #5742; round 7: #5728; round 6 and before: #5700 and the tracker's earlier PRs.\n- Round 18 (Cake !1193) changed no program: the exported programs here are the round-17 kernel tree `c7284461b47` as merged into Cake main (!1037 head `f3108393953`), rendered on the #5920 layout by the exporter (main's codegen since the round-17 base changes every generated program's text — dead-helper pruning, grid_constant tensor maps, `__shfl_sync`, launch-bounds macro — without touching the kernel schedules); the pre-export source-vs-export agreement for the sm_103a build-gap row (hardening-000031) is in the round-18 Cake doc.\n\n- Tracker: flashinfer#4254 (DSv4 sparse-MLA Cake backend; this PR supersedes the round 7-14 PRs listed above and the held round 15-17 fork branches `cake-772-dsv4-round15` `1a91f12a9`, `cake-772-dsv4-round16` `45c0b819c`, `cake-772-dsv4-round17` `dbf86c4d6`).\n\nCake MRs: !1037 .. !1193 (Linear CAKE-772); exporter #5920-layout support: [Cake !1200](https://gitlab-master.nvidia.com/averyh/r94494673bb0150eeffa896f7/-/merge_requests/1200) (stacked on !1037).\n\n🤖 Generated with [Claude Code](https://claude.com/claude-code)\n\n\n<!-- This is an auto-generated comment: release notes by coderabbit.ai -->\n\n## Summary by CodeRabbit\n\n* **New Features**\n * CAKE DSV4 can now allocate its output when none is provided, with route-specific output placement.\n * Added and refined kernel routing for selected BF16 and FP8 workloads, including support for wider sparse inputs and smaller query batches.\n* **Bug Fixes**\n * Improved tensor and launch validation across CUDA devices, including checks for tensor placement and descriptor dimensions.\n * Updated output handling for selected kernels to support tensor-map-based writes and revised buffering.\n* **Tests**\n * Expanded coverage for route selection, output allocation, and output placement.\n\n<!-- end of auto-generated comment: release notes by coderabbit.ai -->\n\n<!-- cake-shared-references:start -->\n## References\n\nThe shared reference corpus for CAKE kernel development includes the following projects, documentation, and existing CAKE work:\n\n- **GPU programming and instructions:** [NVIDIA CUDA Programming Guide](https://docs.nvidia.com/cuda/cuda-programming-guide/index.html), [NVIDIA PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/), and gau-nernst's [tcgen05 tutorial](https://gau-nernst.github.io/tcgen05/) and [CUDA kernel examples](https://github.com/gau-nernst/learn-cuda).\n- **Kernel programming libraries and compilers:** [NVIDIA CUTLASS / CuTe](https://github.com/NVIDIA/cutlass), [Triton](https://github.com/triton-lang/triton), [TileLang](https://github.com/tile-ai/tilelang), [NVIDIA cuTile Python](https://github.com/NVIDIA/cutile-python), and [ThunderKittens](https://github.com/HazyResearch/ThunderKittens) ([ThunderKittens 2.0 techniques](https://hazyresearch.stanford.edu/blog/2026-02-19-tk-2)).\n- **Attention and inference:** [FlashAttention (including Hopper and CuTe implementations)](https://github.com/Dao-AILab/flash-attention), [FlashInfer, including its TRT-LLM kernel integration](https://github.com/flashinfer-ai/flashinfer), [Flash Linear Attention](https://github.com/fla-org/flash-linear-attention), [SageAttention](https://github.com/thu-ml/SageAttention), [FlashAttention-FP4](https://github.com/hao-ai-lab/flash-attention-fp4), and [FastVideo](https://github.com/hao-ai-lab/FastVideo).\n- **GEMM and MoE:** [DeepGEMM](https://github.com/deepseek-ai/DeepGEMM), [SonicMoE](https://github.com/Dao-AILab/sonic-moe), [Alpha-MoE](https://github.com/Aleph-Alpha/Alpha-MoE), and [Mixture of Kittens](https://github.com/cursor/mixture-of-kittens).\n- **Clustering and nearest-neighbor kernels:** [Flash K-Means](https://github.com/svg-project/flash-kmeans) and [FlashLib](https://github.com/FlashML-org/flashlib).\n- **Existing CAKE implementations and PRs:** [CAKE-generated kernel progress tracker and PR index (#4254)](https://github.com/flashinfer-ai/flashinfer/issues/4254).\n\nThese are corpus-level references. PR-specific implementation details, changes, and benchmark references are documented above.\n<!-- cake-shared-references:end -->\n\n"},"gains":{"kind":"string","value":"[{\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 6.53, \"optimized\": 6.88, \"stated_speedup\": null, \"speedup\": 0.9491}, {\"scope\": \"kernel\", \"hardware\": \"B200\", \"model\": null, \"shape\": null, \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": 6.69, \"optimized\": 6.69, \"stated_speedup\": null, \"speedup\": 1.0}, {\"scope\": \"kernel\", \"hardware\": \"GB300\", \"model\": null, \"shape\": \"hardening-000025\", \"batch_size\": null, \"metric\": \"latency\", \"unit\": \"us\", \"higher_is_better\": false, \"baseline\": null, \"optimized\": null, \"stated_speedup\": 1.084, \"speedup\": 1.084}, {\"scope\": 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repo stringclasses 3
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values | license stringclasses 4
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
sglang | 07f944631e747d7489fde1f11de93e503afa90ba | 2025-03-12T00:10:02-07:00 | 4,104 | https://github.com/sgl-project/sglang/pull/4104 | Add awq dequantize kernel to sgl with 1x to 3x speedup (#4104) | Add awq dequantize kernel to sgl with 1x to 3x speedup (#4104) | sgl-kernel/csrc/torch_extension.cc | cpp | Apache-2.0 | /* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in... | /* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in... | --- sgl-kernel/csrc/torch_extension.cc
+++ sgl-kernel/csrc/torch_extension.cc
@@ -75,6 +75,9 @@
/*
* From csrc/gemm
*/
+ m.def("awq_dequantize(Tensor qweight, Tensor scales, Tensor qzeros) -> Tensor");
+ m.impl("awq_dequantize", torch::kCUDA, &awq_dequantize);
+
m.def(
"int8_scaled_mm(Tensor mat_... | 3 | 0 | 5 | [] | [] | [
"1x",
"3x"
] | Optimize this cpp kernel file from sglang (sgl-kernel/csrc/torch_extension.cc).
Goal: Add awq dequantize kernel to sgl with 1x to 3x speedup
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 ... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
#2965
Adapted from [vllm awq_dequant](https://git... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "qweight_row=3584,qweight_col=448", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 80.863997, "optimized": 27.519999, "stated_speedup": null, "speedup": 2.9384}, {"scope": "kernel", "hardware": null, "model": n... | 1.0684 | null |
sglang | 07f944631e747d7489fde1f11de93e503afa90ba | 2025-03-12T00:10:02-07:00 | 4,104 | https://github.com/sgl-project/sglang/pull/4104 | Add awq dequantize kernel to sgl with 1x to 3x speedup (#4104) | Add awq dequantize kernel to sgl with 1x to 3x speedup (#4104) | sgl-kernel/include/sgl_kernel_ops.h | cpp | Apache-2.0 | /* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in... | /* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in... | --- sgl-kernel/include/sgl_kernel_ops.h
+++ sgl-kernel/include/sgl_kernel_ops.h
@@ -112,6 +112,7 @@
/*
* From csrc/gemm
*/
+torch::Tensor awq_dequantize(torch::Tensor qweight, torch::Tensor scales, torch::Tensor qzeros);
torch::Tensor int8_scaled_mm(
const torch::Tensor& mat_a,
const torch::Tensor& mat_... | 1 | 0 | 5 | [] | [] | [
"1x",
"3x"
] | Optimize this cpp kernel file from sglang (sgl-kernel/include/sgl_kernel_ops.h).
Goal: Add awq dequantize kernel to sgl with 1x to 3x speedup
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
#2965
Adapted from [vllm awq_dequant](https://git... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "qweight_row=3584,qweight_col=448", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 80.863997, "optimized": 27.519999, "stated_speedup": null, "speedup": 2.9384}, {"scope": "kernel", "hardware": null, "model": n... | 1.0684 | null |
sglang | e0917e6bd0fbbbbc8ba3db48ae26f07366ab9a0c | 2025-03-12T00:08:03-07:00 | 4,215 | https://github.com/sgl-project/sglang/pull/4215 | Remove vllm ops scaled fp8 quant and accelerate per token quant by 20-28% (#4215) | Remove vllm ops scaled fp8 quant and accelerate per token quant by 20-28% (#4215)
Co-authored-by: Stefan He <bhe@linkedin.com> | python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py | triton | Apache-2.0 | # Adapted from https://github.com/vllm-project/vllm/blob/a6221a144af772fd1a68fe7e627935dc53e81738/vllm/model_executor/layers/fused_moe/fused_moe.py
"""Fused MoE kernel."""
import functools
import json
import logging
import os
from typing import Any, Callable, Dict, List, Optional, Tuple
import torch
import triton
im... | # Adapted from https://github.com/vllm-project/vllm/blob/a6221a144af772fd1a68fe7e627935dc53e81738/vllm/model_executor/layers/fused_moe/fused_moe.py
"""Fused MoE kernel."""
import functools
import json
import logging
import os
from typing import Any, Callable, Dict, List, Optional, Tuple
import torch
import triton
im... | --- python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py
+++ python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py
@@ -11,7 +11,7 @@
import torch
import triton
import triton.language as tl
-from vllm import _custom_ops as ops
+from vllm import _custom_ops as vllm_ops
from sglang.srt.layers.moe.topk imp... | 14 | 6 | 3 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py).
Goal: Remove vllm ops scaled fp8 quant and accelerate per token quant by 20-28%
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# Adapted from https://github.com/vllm-project/vllm... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
Part of initiative: https://github.com/sgl-project/s... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "hidden_dim=4096", "batch_size": 16, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 26.272001, "optimized": 24.928, "stated_speedup": null, "speedup": 1.0539}, {"scope": "kernel", "hardware": null, "model": null, "shape": "hidden_... | 1.3507 | null |
sglang | e0917e6bd0fbbbbc8ba3db48ae26f07366ab9a0c | 2025-03-12T00:08:03-07:00 | 4,215 | https://github.com/sgl-project/sglang/pull/4215 | Remove vllm ops scaled fp8 quant and accelerate per token quant by 20-28% (#4215) | Remove vllm ops scaled fp8 quant and accelerate per token quant by 20-28% (#4215)
Co-authored-by: Stefan He <bhe@linkedin.com> | sgl-kernel/csrc/gemm/per_token_quant_fp8.cu | cuda | Apache-2.0 | #include <ATen/cuda/CUDAContext.h>
#include <cmath>
#include <cub/block/block_reduce.cuh>
#include <flashinfer/vec_dtypes.cuh>
#include "utils.h"
template <typename T>
__global__ void per_token_quant_fp8_kernel(
const T* __restrict__ input,
FP8_TYPE* __restrict__ output_q,
float* __restrict__ output_s,
... | #include <ATen/cuda/CUDAContext.h>
#include <cmath>
#include <cub/block/block_reduce.cuh>
#include <flashinfer/vec_dtypes.cuh>
#include "utils.h"
template <typename T>
__global__ void per_token_quant_fp8_kernel(
const T* __restrict__ input,
FP8_TYPE* __restrict__ output_q,
float* __restrict__ output_s,
... | --- sgl-kernel/csrc/gemm/per_token_quant_fp8.cu
+++ sgl-kernel/csrc/gemm/per_token_quant_fp8.cu
@@ -14,7 +14,6 @@
const int64_t hidden_dim,
const int64_t num_tokens) {
const int token_idx = blockIdx.x;
-
if (token_idx >= num_tokens) return;
const int tid = threadIdx.x;
@@ -25,9 +24,20 @@
float... | 19 | 23 | 3 | [] | [] | [] | Optimize this cuda kernel file from sglang (sgl-kernel/csrc/gemm/per_token_quant_fp8.cu).
Goal: Remove vllm ops scaled fp8 quant and accelerate per token quant by 20-28%
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include <ATen/cuda/CUDAContext.h>
#include <cmath>
#include <cub/blo... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
Part of initiative: https://github.com/sgl-project/s... | [{"scope": "kernel", "hardware": null, "model": null, "shape": "hidden_dim=4096", "batch_size": 16, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 26.272001, "optimized": 24.928, "stated_speedup": null, "speedup": 1.0539}, {"scope": "kernel", "hardware": null, "model": null, "shape": "hidden_... | 1.3507 | null |
sglang | cf0ccd406e38a63bdb984578ba742ca3c8ab81b8 | 2025-03-10T10:07:45-07:00 | 4,267 | https://github.com/sgl-project/sglang/pull/4267 | Optimize rope in sgl kernel (#4267) | Optimize rope in sgl kernel (#4267) | sgl-kernel/csrc/elementwise/rope.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- sgl-kernel/csrc/elementwise/rope.cu
+++ sgl-kernel/csrc/elementwise/rope.cu
@@ -65,7 +65,7 @@
static_cast<c_type*>(q_rope.data_ptr()),
static_cast<c_type*>(k_rope.data_ptr()),
static_cast<float*>(cos_sin_cache.data_ptr()),
- static_cast<int32_t*>(pos_ids.data_ptr()),
+ stati... | 1 | 1 | 2 | [] | [] | [] | Optimize this cuda kernel file from sglang (sgl-kernel/csrc/elementwise/rope.cu).
Goal: Optimize rope in sgl kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/*
* Copyright (c) 2024 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you ma... | `positions` is int64, so we should not cast it to int32.
This removes an extra copy
| [] | null | null |
sglang | ddcf9fe3beacd8aed573c711942194dd02350da4 | 2025-02-21T00:54:41+08:00 | 3,731 | https://github.com/sgl-project/sglang/pull/3731 | Optimize triton attention custom mask (#3731) | Optimize triton attention custom mask (#3731) | python/sglang/srt/layers/attention/triton_ops/extend_attention.py | triton | Apache-2.0 | # Copyright 2023-2024 SGLang Team
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writin... | # Copyright 2023-2024 SGLang Team
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writin... | --- python/sglang/srt/layers/attention/triton_ops/extend_attention.py
+++ python/sglang/srt/layers/attention/triton_ops/extend_attention.py
@@ -74,6 +74,7 @@
BLOCK_M: tl.constexpr,
BLOCK_N: tl.constexpr,
USE_CUSTOM_MASK: tl.constexpr,
+ SKIP_PREFIX_CUSTOM_MASK: tl.constexpr,
STORE_TRANSPOSE: tl.c... | 6 | 1 | 1 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/attention/triton_ops/extend_attention.py).
Goal: Optimize triton attention custom mask
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# Copyright 2023-2024 SGLang Team
# Licensed under the Apache License, Version 2... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
Skip custom mask for prefix part of triton attentio... | [] | null | null |
sglang | 634a3561ac5b58d6ed1fe07c2665bf523d7825ac | 2025-02-19T01:35:58+08:00 | 3,665 | https://github.com/sgl-project/sglang/pull/3665 | AMD Prefill optimize (#3665) | AMD Prefill optimize (#3665)
Co-authored-by: AMD-dteng <dteng@amd.com>
Co-authored-by: HAI <hixiao@gmail.com> | python/sglang/srt/layers/attention/triton_ops/extend_attention.py | triton | Apache-2.0 | # Copyright 2023-2024 SGLang Team
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writin... | # Copyright 2023-2024 SGLang Team
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writin... | --- python/sglang/srt/layers/attention/triton_ops/extend_attention.py
+++ python/sglang/srt/layers/attention/triton_ops/extend_attention.py
@@ -74,6 +74,7 @@
BLOCK_M: tl.constexpr,
BLOCK_N: tl.constexpr,
USE_CUSTOM_MASK: tl.constexpr,
+ STORE_TRANSPOSE: tl.constexpr,
):
cur_seq = tl.program_id(0... | 16 | 5 | 1 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/attention/triton_ops/extend_attention.py).
Goal: AMD Prefill optimize
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# Copyright 2023-2024 SGLang Team
# Licensed under the Apache License, Version 2.0 (the "License"... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
<!-- Explain the purpose of this PR and the goals i... | [] | null | null |
sglang | bb418ced802c6dbb6b0ae0d65218327129148769 | 2025-02-11T22:19:05+08:00 | 3,490 | https://github.com/sgl-project/sglang/pull/3490 | optimize per token group quant fp8 (#3490) | optimize per token group quant fp8 (#3490) | sgl-kernel/src/sgl-kernel/include/sgl_kernels_ops.h | cpp | Apache-2.0 | /* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in... | /* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in... | --- sgl-kernel/src/sgl-kernel/include/sgl_kernels_ops.h
+++ sgl-kernel/src/sgl-kernel/include/sgl_kernels_ops.h
@@ -143,3 +143,7 @@
void build_tree_kernel(at::Tensor parent_list, at::Tensor selected_index, at::Tensor verified_seq_len,
at::Tensor tree_mask, at::Tensor positions, at::Tensor retri... | 4 | 0 | 5 | [] | [] | [] | Optimize this cpp kernel file from sglang (sgl-kernel/src/sgl-kernel/include/sgl_kernels_ops.h).
Goal: optimize per token group quant fp8
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (th... | From the nsys profiling of DeepSeek H200 R1, it can be observed that the Triton version of the _per_token_group_quant_fp8 kernel is a relatively time-consuming operation, accounting for 2.1%. Upon examining its number of blocks and threads, it is found that the number of blocks is large while the number of threads is s... | [] | null | null |
sglang | bb418ced802c6dbb6b0ae0d65218327129148769 | 2025-02-11T22:19:05+08:00 | 3,490 | https://github.com/sgl-project/sglang/pull/3490 | optimize per token group quant fp8 (#3490) | optimize per token group quant fp8 (#3490) | sgl-kernel/src/sgl-kernel/torch_extension.cc | cpp | Apache-2.0 | /* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in... | /* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in... | --- sgl-kernel/src/sgl-kernel/torch_extension.cc
+++ sgl-kernel/src/sgl-kernel/torch_extension.cc
@@ -153,6 +153,12 @@
"Tensor! tree_mask, Tensor! positions, Tensor! retrive_index, "
"int topk, int depth, int draft_token_num) -> ()");
m.impl("build_tree_kernel", torch::kCUDA, &build_tree_kernel);
+
+ ... | 6 | 0 | 5 | [] | [] | [] | Optimize this cpp kernel file from sglang (sgl-kernel/src/sgl-kernel/torch_extension.cc).
Goal: optimize per token group quant fp8
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
/* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "Lice... | From the nsys profiling of DeepSeek H200 R1, it can be observed that the Triton version of the _per_token_group_quant_fp8 kernel is a relatively time-consuming operation, accounting for 2.1%. Upon examining its number of blocks and threads, it is found that the number of blocks is large while the number of threads is s... | [] | null | null |
sglang | cdae77b03dfc6fec3863630550b45bbfc789f957 | 2025-02-07T00:53:46+08:00 | 3,347 | https://github.com/sgl-project/sglang/pull/3347 | optimize moe_align_kernel cuda (#3347) | optimize moe_align_kernel cuda (#3347) | python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py | triton | Apache-2.0 | # Adapted from https://github.com/vllm-project/vllm/blob/a6221a144af772fd1a68fe7e627935dc53e81738/vllm/model_executor/layers/fused_moe/fused_moe.py
"""Fused MoE kernel."""
import functools
import json
import logging
import os
from typing import Any, Callable, Dict, List, Optional, Tuple
import torch
import triton
im... | # Adapted from https://github.com/vllm-project/vllm/blob/a6221a144af772fd1a68fe7e627935dc53e81738/vllm/model_executor/layers/fused_moe/fused_moe.py
"""Fused MoE kernel."""
import functools
import json
import logging
import os
from typing import Any, Callable, Dict, List, Optional, Tuple
import torch
import triton
im... | --- python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py
+++ python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py
@@ -417,12 +417,12 @@
num_tokens_post_pad,
)
else:
- token_cnts_buffer = torch.empty(
+ token_cnts_buffer = torch.zeros(
... | 2 | 2 | 2 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py).
Goal: optimize moe_align_kernel cuda
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# Adapted from https://github.com/vllm-project/vllm/blob/a6221a144af772fd1a68fe7e627935dc53e81... | Thanks to @tim-zou help in https://github.com/sgl-project/sglang/issues/3339.
## DeepSeek V3 end2end benchmark
```shell
python3 -m sglang.launch_server --model deepseek-ai/DeepSeek-V3 --tp 8 --trust-remote-code
python3 benchmark/gsm8k/bench_sglang.py --num-questions 2000 --parallel 2000 --num-shots 8
```
After start... | [] | null | null |
sglang | cdae77b03dfc6fec3863630550b45bbfc789f957 | 2025-02-07T00:53:46+08:00 | 3,347 | https://github.com/sgl-project/sglang/pull/3347 | optimize moe_align_kernel cuda (#3347) | optimize moe_align_kernel cuda (#3347) | sgl-kernel/src/sgl-kernel/csrc/moe_align_kernel.cu | cuda | Apache-2.0 | /* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in... | /* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in... | --- sgl-kernel/src/sgl-kernel/csrc/moe_align_kernel.cu
+++ sgl-kernel/src/sgl-kernel/csrc/moe_align_kernel.cu
@@ -25,11 +25,23 @@
#define WARP_SIZE 32
template <typename scalar_t>
+__global__ void moe_token_sort_kernel(scalar_t* __restrict__ topk_ids, int32_t* sorted_token_ids,
+ ... | 23 | 15 | 2 | [] | [] | [] | Optimize this cuda kernel file from sglang (sgl-kernel/src/sgl-kernel/csrc/moe_align_kernel.cu).
Goal: optimize moe_align_kernel cuda
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
/* Copyright 2025 SGLang Team. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "... | Thanks to @tim-zou help in https://github.com/sgl-project/sglang/issues/3339.
## DeepSeek V3 end2end benchmark
```shell
python3 -m sglang.launch_server --model deepseek-ai/DeepSeek-V3 --tp 8 --trust-remote-code
python3 benchmark/gsm8k/bench_sglang.py --num-questions 2000 --parallel 2000 --num-shots 8
```
After start... | [] | null | null |
sglang | d9eb9358ccf8803253d2f5cf7feafef13b60b8c5 | 2025-02-01T19:29:45-06:00 | 3,255 | https://github.com/sgl-project/sglang/pull/3255 | Tune paged attention parameters for AMD GPU. (#3255) | Tune paged attention parameters for AMD GPU. (#3255) | python/sglang/srt/layers/attention/triton_ops/decode_attention.py | triton | Apache-2.0 | # Copyright 2023-2024 SGLang Team
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writin... | # Copyright 2023-2024 SGLang Team
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writin... | --- python/sglang/srt/layers/attention/triton_ops/decode_attention.py
+++ python/sglang/srt/layers/attention/triton_ops/decode_attention.py
@@ -181,6 +181,9 @@
logit_cap,
):
BLOCK = 64
+ # [TODO] work around SGPR limit on MI3xx
+ if is_hip_:
+ BLOCK = 8
NUM_KV_SPLITS = num_kv_splits
Lk... | 9 | 2 | 1 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/attention/triton_ops/decode_attention.py).
Goal: Tune paged attention parameters for AMD GPU.
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# Copyright 2023-2024 SGLang Team
# Licensed under the Apache License, Ve... | ## Motivation
Fine tune SGLang page attention kernel performance on AMD MI GPU for LLM.
## Modifications
Changes:
- num_kv_splits : 8 -> 16
- BLOCK : 64 -> 8
- num_warps : 2 -> 1 when kv_group_num is more than 1
- waves_per_cu : 4 -> 1 in grouped paged attention kernel
These knobs have been tested with a couple of ... | [] | null | null |
sglang | fb11a4398158ce1838813b729d4ca188865b69f1 | 2025-01-26T23:28:00-08:00 | 3,134 | https://github.com/sgl-project/sglang/pull/3134 | [kernel] Integrate flashinfer's rope with higher precision and better perf (#3134) | [kernel] Integrate flashinfer's rope with higher precision and better perf (#3134) | sgl-kernel/src/sgl-kernel/csrc/rotary_embedding.cu | cuda | Apache-2.0 | // Reference: https://github.com/vllm-project/vllm/blob/main/csrc/pos_encoding_kernels.cu
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <torch/all.h>
template <typename scalar_t, bool IS_NEOX>
inline __device__ void apply_token_rotary_embedding(scalar_t* __restrict__ arr, const scalar_t*... | // Reference: https://github.com/vllm-project/vllm/blob/main/csrc/pos_encoding_kernels.cu
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>
#include <torch/all.h>
template <typename scalar_t, bool IS_NEOX>
inline __device__ void apply_token_rotary_embedding(scalar_t* __restrict__ arr, const scalar_t*... | --- sgl-kernel/src/sgl-kernel/csrc/rotary_embedding.cu
+++ sgl-kernel/src/sgl-kernel/csrc/rotary_embedding.cu
@@ -98,7 +98,7 @@
int64_t query_stride = query.stride(-2);
int64_t key_stride = key.stride(-2);
- dim3 grid(num_tokens);
+ dim3 grid(num_tokens); // each block is responsible for one token
dim3 bl... | 1 | 1 | 6 | [] | [] | [] | Optimize this cuda kernel file from sglang (sgl-kernel/src/sgl-kernel/csrc/rotary_embedding.cu).
Goal: [kernel] Integrate flashinfer's rope with higher precision and better perf
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
// Reference: https://github.com/vllm-project/vllm/blob/main/c... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
<!-- Explain the purpose of this PR and the goals i... | [] | null | null |
sglang | fb11a4398158ce1838813b729d4ca188865b69f1 | 2025-01-26T23:28:00-08:00 | 3,134 | https://github.com/sgl-project/sglang/pull/3134 | [kernel] Integrate flashinfer's rope with higher precision and better perf (#3134) | [kernel] Integrate flashinfer's rope with higher precision and better perf (#3134) | sgl-kernel/src/sgl-kernel/include/sgl_kernels_ops.h | cpp | Apache-2.0 | #pragma once
#include <Python.h>
#include <torch/extension.h>
#include <vector>
#define _CONCAT(A, B) A##B
#define CONCAT(A, B) _CONCAT(A, B)
#define _STRINGIFY(A) #A
#define STRINGIFY(A) _STRINGIFY(A)
#define TORCH_LIBRARY_EXPAND(NAME, MODULE) TORCH_LIBRARY(NAME, MODULE)
#define REGISTER_EXTENSION(NAME) ... | #pragma once
#include <Python.h>
#include <torch/extension.h>
#include <vector>
#define _CONCAT(A, B) A##B
#define CONCAT(A, B) _CONCAT(A, B)
#define _STRINGIFY(A) #A
#define STRINGIFY(A) _STRINGIFY(A)
#define TORCH_LIBRARY_EXPAND(NAME, MODULE) TORCH_LIBRARY(NAME, MODULE)
#define REGISTER_EXTENSION(NAME) ... | --- sgl-kernel/src/sgl-kernel/include/sgl_kernels_ops.h
+++ sgl-kernel/src/sgl-kernel/include/sgl_kernels_ops.h
@@ -112,3 +112,7 @@
void top_p_sampling_from_probs(at::Tensor probs, at::Tensor uniform_samples, at::Tensor samples, at::Tensor success,
std::optional<at::Tensor> maybe_top_p_... | 4 | 0 | 6 | [] | [] | [] | Optimize this cpp kernel file from sglang (sgl-kernel/src/sgl-kernel/include/sgl_kernels_ops.h).
Goal: [kernel] Integrate flashinfer's rope with higher precision and better perf
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#pragma once
#include <Python.h>
#include <torch/extension.h>
... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
<!-- Explain the purpose of this PR and the goals i... | [] | null | null |
sglang | fb11a4398158ce1838813b729d4ca188865b69f1 | 2025-01-26T23:28:00-08:00 | 3,134 | https://github.com/sgl-project/sglang/pull/3134 | [kernel] Integrate flashinfer's rope with higher precision and better perf (#3134) | [kernel] Integrate flashinfer's rope with higher precision and better perf (#3134) | sgl-kernel/src/sgl-kernel/torch_extension.cc | cpp | Apache-2.0 |
#include <ATen/core/dispatch/Dispatcher.h>
#include <torch/library.h>
#include "sgl_kernels_ops.h"
TORCH_LIBRARY_EXPAND(sgl_kernels, m) {
// trt_reduce
m.def(
"init_custom_ar(int rank_id, int world_size, Tensor rank_data, int[] buffers, int[] tmp_result_buffers, int[] "
"barrier_in, int[] barrier_out... | #include <ATen/core/dispatch/Dispatcher.h>
#include <torch/library.h>
#include "sgl_kernels_ops.h"
TORCH_LIBRARY_EXPAND(sgl_kernels, m) {
// trt_reduce
m.def(
"init_custom_ar(int rank_id, int world_size, Tensor rank_data, int[] buffers, int[] tmp_result_buffers, int[] "
"barrier_in, int[] barrier_out)... | --- sgl-kernel/src/sgl-kernel/torch_extension.cc
+++ sgl-kernel/src/sgl-kernel/torch_extension.cc
@@ -1,4 +1,3 @@
-
#include <ATen/core/dispatch/Dispatcher.h>
#include <torch/library.h>
@@ -116,6 +115,12 @@
"top_p_sampling_from_probs(Tensor probs, Tensor uniform_samples, Tensor! samples, Tensor! success, Ten... | 6 | 1 | 6 | [] | [] | [] | Optimize this cpp kernel file from sglang (sgl-kernel/src/sgl-kernel/torch_extension.cc).
Goal: [kernel] Integrate flashinfer's rope with higher precision and better perf
Target hardware: unspecified
Target models: unspecified
Current file:
```cpp
#include <ATen/core/dispatch/Dispatcher.h>
#include <torch/library.h>... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
<!-- Explain the purpose of this PR and the goals i... | [] | null | null |
sglang | 6cb3974e77524ee2b291919ca6a8b55547bca8e0 | 2025-01-16T03:04:25+08:00 | 2,904 | https://github.com/sgl-project/sglang/pull/2904 | optimize custom allreduce kernel (#2904) | optimize custom allreduce kernel (#2904) | sgl-kernel/src/sgl-kernel/csrc/sgl_kernel_ops.cu | cuda | Apache-2.0 | #include "utils.hpp"
// trt_reduce
using fptr_t = int64_t;
fptr_t init_custom_ar(int64_t rank_id, int64_t world_size, const std::vector<fptr_t>& buffers,
const std::vector<fptr_t>& barrier_in, const std::vector<fptr_t>& barrier_out);
void dispose(fptr_t _fa);
void all_reduce(fptr_t _fa, torch::Te... | #include "utils.hpp"
// trt_reduce
using fptr_t = int64_t;
fptr_t init_custom_ar(int64_t rank_id, int64_t world_size, torch::Tensor& rank_data, const std::vector<fptr_t>& buffers,
const std::vector<fptr_t>& tmp_result_buffers, const std::vector<fptr_t>& barrier_in,
const std... | --- sgl-kernel/src/sgl-kernel/csrc/sgl_kernel_ops.cu
+++ sgl-kernel/src/sgl-kernel/csrc/sgl_kernel_ops.cu
@@ -2,10 +2,14 @@
// trt_reduce
using fptr_t = int64_t;
-fptr_t init_custom_ar(int64_t rank_id, int64_t world_size, const std::vector<fptr_t>& buffers,
- const std::vector<fptr_t>& barrier_... | 8 | 2 | 7 | [] | [] | [] | Optimize this cuda kernel file from sglang (sgl-kernel/src/sgl-kernel/csrc/sgl_kernel_ops.cu).
Goal: optimize custom allreduce kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
#include "utils.hpp"
// trt_reduce
using fptr_t = int64_t;
fptr_t init_custom_ar(int64_t rank_id, int64_t... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
<!-- Explain the purpose of this PR and the goals i... | [] | null | null |
sglang | 6cb3974e77524ee2b291919ca6a8b55547bca8e0 | 2025-01-16T03:04:25+08:00 | 2,904 | https://github.com/sgl-project/sglang/pull/2904 | optimize custom allreduce kernel (#2904) | optimize custom allreduce kernel (#2904) | sgl-kernel/src/sgl-kernel/csrc/trt_reduce_internal.cu | cuda | Apache-2.0 | // reference:
// https://github.com/NVIDIA/TensorRT-LLM/blob/release/0.14/cpp/tensorrt_llm/kernels/customAllReduceKernels.cu
/*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance wi... | // reference:
// https://github.com/NVIDIA/TensorRT-LLM/blob/release/0.14/cpp/tensorrt_llm/kernels/customAllReduceKernels.cu
/*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance wi... | --- sgl-kernel/src/sgl-kernel/csrc/trt_reduce_internal.cu
+++ sgl-kernel/src/sgl-kernel/csrc/trt_reduce_internal.cu
@@ -126,10 +126,10 @@
__syncthreads();
}
+template <bool start, bool need_fence = false>
__inline__ __device__ void block_barrier(uint32_t** signals, uint32_t const flag, size_t const local_rank,
-... | 95 | 68 | 7 | [] | [] | [] | Optimize this cuda kernel file from sglang (sgl-kernel/src/sgl-kernel/csrc/trt_reduce_internal.cu).
Goal: optimize custom allreduce kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
// reference:
// https://github.com/NVIDIA/TensorRT-LLM/blob/release/0.14/cpp/tensorrt_llm/kernels/cu... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
<!-- Explain the purpose of this PR and the goals i... | [] | null | null |
sglang | 6cb3974e77524ee2b291919ca6a8b55547bca8e0 | 2025-01-16T03:04:25+08:00 | 2,904 | https://github.com/sgl-project/sglang/pull/2904 | optimize custom allreduce kernel (#2904) | optimize custom allreduce kernel (#2904) | sgl-kernel/src/sgl-kernel/csrc/trt_reduce_internal.cuh | cuda | Apache-2.0 | // reference:
// https://github.com/NVIDIA/TensorRT-LLM/blob/release/0.14/cpp/tensorrt_llm/plugins/ncclPlugin/allreducePlugin.cpp
/*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in complian... | // reference:
// https://github.com/NVIDIA/TensorRT-LLM/blob/release/0.14/cpp/tensorrt_llm/plugins/ncclPlugin/allreducePlugin.cpp
/*
* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in complian... | --- sgl-kernel/src/sgl-kernel/csrc/trt_reduce_internal.cuh
+++ sgl-kernel/src/sgl-kernel/csrc/trt_reduce_internal.cuh
@@ -36,6 +36,10 @@
AUTO = 3,
};
+struct RankData {
+ void* ptrs[MAX_RANKS_PER_NODE];
+};
+
struct AllReduceParams {
size_t elts_size;
size_t elts_total;
@@ -46,9 +50,11 @@
uint32_t barr... | 7 | 1 | 7 | [] | [] | [] | Optimize this cuda kernel file from sglang (sgl-kernel/src/sgl-kernel/csrc/trt_reduce_internal.cuh).
Goal: optimize custom allreduce kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
// reference:
// https://github.com/NVIDIA/TensorRT-LLM/blob/release/0.14/cpp/tensorrt_llm/plugins/n... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
<!-- Explain the purpose of this PR and the goals i... | [] | null | null |
sglang | 6cb3974e77524ee2b291919ca6a8b55547bca8e0 | 2025-01-16T03:04:25+08:00 | 2,904 | https://github.com/sgl-project/sglang/pull/2904 | optimize custom allreduce kernel (#2904) | optimize custom allreduce kernel (#2904) | sgl-kernel/src/sgl-kernel/csrc/trt_reduce_kernel.cu | cuda | Apache-2.0 | // reference: https://github.com/NVIDIA/TensorRT-LLM/blob/release/0.14/cpp/tensorrt_llm/kernels/customAllReduceKernels.h
#include <c10/cuda/CUDAStream.h>
#include <cassert>
#include <iostream>
#include <sstream>
#include <unordered_map>
#include "trt_reduce_internal.cuh"
using namespace trt_llm;
using fptr_t = int... | // reference: https://github.com/NVIDIA/TensorRT-LLM/blob/release/0.14/cpp/tensorrt_llm/kernels/customAllReduceKernels.h
#include <c10/cuda/CUDAStream.h>
#include <cassert>
#include <iostream>
#include <sstream>
#include <unordered_map>
#include "trt_reduce_internal.cuh"
using namespace trt_llm;
using fptr_t = int... | --- sgl-kernel/src/sgl-kernel/csrc/trt_reduce_kernel.cu
+++ sgl-kernel/src/sgl-kernel/csrc/trt_reduce_kernel.cu
@@ -12,25 +12,46 @@
using namespace trt_llm;
using fptr_t = int64_t;
+using IPC_KEY = std::array<uint8_t, sizeof(cudaIpcMemHandle_t)>;
class AllReduceMeta {
public:
- AllReduceMeta(int64_t rank_id, ... | 109 | 8 | 7 | [] | [] | [] | Optimize this cuda kernel file from sglang (sgl-kernel/src/sgl-kernel/csrc/trt_reduce_kernel.cu).
Goal: optimize custom allreduce kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```cuda
// reference: https://github.com/NVIDIA/TensorRT-LLM/blob/release/0.14/cpp/tensorrt_llm/kernels/customA... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
<!-- Explain the purpose of this PR and the goals i... | [] | null | null |
sglang | 148254d4db8bf3bffee23710cd1acbd5711ebd1b | 2025-01-02T17:11:06+08:00 | 2,705 | https://github.com/sgl-project/sglang/pull/2705 | Improve moe reduce sum kernel performance (#2705) | Improve moe reduce sum kernel performance (#2705)
Co-authored-by: wunhuang <wunhuang@amd.com> | python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py | triton | Apache-2.0 | # Adapted from https://github.com/vllm-project/vllm/blob/a6221a144af772fd1a68fe7e627935dc53e81738/vllm/model_executor/layers/fused_moe/fused_moe.py
"""Fused MoE kernel."""
import functools
import json
import logging
import os
from typing import Any, Callable, Dict, List, Optional, Tuple
import torch
import triton
im... | # Adapted from https://github.com/vllm-project/vllm/blob/a6221a144af772fd1a68fe7e627935dc53e81738/vllm/model_executor/layers/fused_moe/fused_moe.py
"""Fused MoE kernel."""
import functools
import json
import logging
import os
from typing import Any, Callable, Dict, List, Optional, Tuple
import torch
import triton
im... | --- python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py
+++ python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py
@@ -854,11 +854,17 @@
block_shape=block_shape,
)
- torch.sum(
- intermediate_cache3.view(*intermediate_cache3.shape),
- dim=1,
- o... | 11 | 5 | 1 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py).
Goal: Improve moe reduce sum kernel performance
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# Adapted from https://github.com/vllm-project/vllm/blob/a6221a144af772fd1a68fe7e62... | ## Motivation
torch.sum could not use GPU core efficiency, implement specific kernel to enhance the performance
## Modifications
change the base docker image and modify torch.sum to ops.moe_sum in fused_moe.py
## Checklist
- [+] Format your code according to the [Contributor Guide](https://github.com/sgl-project/s... | [] | null | null |
sglang | 7dc66fcb40aa693a299bdcf17247f52cc9deeff0 | 2024-12-08T17:17:37+08:00 | 2,394 | https://github.com/sgl-project/sglang/pull/2394 | Optimize Triton decoding kernel for long context (#2394) | Optimize Triton decoding kernel for long context (#2394) | python/sglang/srt/layers/attention/triton_ops/decode_attention.py | triton | Apache-2.0 | # Copyright 2023-2024 SGLang Team
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writin... | # Copyright 2023-2024 SGLang Team
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writin... | --- python/sglang/srt/layers/attention/triton_ops/decode_attention.py
+++ python/sglang/srt/layers/attention/triton_ops/decode_attention.py
@@ -17,8 +17,8 @@
"""
# Adapted from
-# https://github.com/ModelTC/lightllm/blob/f2a54f0912293f683bf1d1695fd12c4098a5bf82/lightllm/models/llama/triton_kernel/token_attention_no... | 314 | 369 | 2 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/attention/triton_ops/decode_attention.py).
Goal: Optimize Triton decoding kernel for long context
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# Copyright 2023-2024 SGLang Team
# Licensed under the Apache License... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
As mentioned in https://github.com/sgl-project/sgla... | [] | null | null |
sglang | 95f93f493a60a4dfdb30aa3d24ba3fc3b8666d3e | 2024-12-07T05:18:26-08:00 | 2,388 | https://github.com/sgl-project/sglang/pull/2388 | Fp8 MoE optimizations on AMD (#2388) | Fp8 MoE optimizations on AMD (#2388) | python/sglang/srt/layers/fused_moe_triton/fused_moe.py | triton | Apache-2.0 | # Adapted from https://github.com/vllm-project/vllm/blob/a6221a144af772fd1a68fe7e627935dc53e81738/vllm/model_executor/layers/fused_moe/fused_moe.py
"""Fused MoE kernel."""
import functools
import json
import logging
import os
from typing import Any, Callable, Dict, Optional, Tuple
import torch
import triton
import t... | # Adapted from https://github.com/vllm-project/vllm/blob/a6221a144af772fd1a68fe7e627935dc53e81738/vllm/model_executor/layers/fused_moe/fused_moe.py
"""Fused MoE kernel."""
import functools
import json
import logging
import os
from typing import Any, Callable, Dict, Optional, Tuple
import torch
import triton
import t... | --- python/sglang/srt/layers/fused_moe_triton/fused_moe.py
+++ python/sglang/srt/layers/fused_moe_triton/fused_moe.py
@@ -16,6 +16,7 @@
from sglang.srt.utils import direct_register_custom_op, get_device_name
logger = logging.getLogger(__name__)
+padding_size = 128 if bool(int(os.getenv("MOE_PADDING", "0"))) else 0
... | 64 | 21 | 2 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/fused_moe_triton/fused_moe.py).
Goal: Fp8 MoE optimizations on AMD
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# Adapted from https://github.com/vllm-project/vllm/blob/a6221a144af772fd1a68fe7e627935dc53e81738/vl... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
<!-- Explain the purpose of this PR and the goals i... | [] | null | null |
sglang | 087ab832236ef264746d8c75af8cd8752f56ca6b | 2024-11-10T18:54:43-08:00 | 1,980 | https://github.com/sgl-project/sglang/pull/1980 | [Performance, Triton] Optimize over mask compute to tl.load in fused_moe_kernel (#1980) | [Performance, Triton] Optimize over mask compute to tl.load in fused_moe_kernel (#1980) | python/sglang/srt/layers/attention/triton_ops/decode_attention.py | triton | Apache-2.0 | """
Copyright 2023-2024 SGLang Team
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, softwar... | """
Copyright 2023-2024 SGLang Team
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, softwar... | --- python/sglang/srt/layers/attention/triton_ops/decode_attention.py
+++ python/sglang/srt/layers/attention/triton_ops/decode_attention.py
@@ -506,6 +506,12 @@
)
num_warps = 4
+
+ extra_kargs = {}
+ if is_hip():
+ # https://rocm.docs.amd.com/en/docs-6.2.0/how-to/llm-fine-tuning-optimization/op... | 7 | 0 | 2 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/attention/triton_ops/decode_attention.py).
Goal: [Performance, Triton] Optimize over mask compute to tl.load in fused_moe_kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```python
"""
Copyright 2023-2024 SGLang Team
Li... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
Test shows `~0.5%` boost to prefill, `~1.0%` boost ... | [{"scope": "e2e", "hardware": null, "model": "Grok-1", "shape": "b32/i1023/o256", "batch_size": null, "metric": "prefill throughput", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.005, "speedup": 1.005}, {"scope": "e2e", "hardware": null, "model": "Grok-1", "shape": "b... | null | 1.0075 |
sglang | 087ab832236ef264746d8c75af8cd8752f56ca6b | 2024-11-10T18:54:43-08:00 | 1,980 | https://github.com/sgl-project/sglang/pull/1980 | [Performance, Triton] Optimize over mask compute to tl.load in fused_moe_kernel (#1980) | [Performance, Triton] Optimize over mask compute to tl.load in fused_moe_kernel (#1980) | python/sglang/srt/layers/fused_moe/fused_moe.py | triton | Apache-2.0 | # Adapted from
# https://github.com/vllm-project/vllm/tree/v0.5.4/vllm/model_executor/layers/fused_moe
"""Fused MoE kernel."""
import functools
import json
import os
from typing import Any, Dict, Optional, Tuple
import torch
import triton
import triton.language as tl
import vllm.envs as envs
from vllm import _custom_o... | # Adapted from
# https://github.com/vllm-project/vllm/tree/v0.5.4/vllm/model_executor/layers/fused_moe
"""Fused MoE kernel."""
import functools
import json
import os
from typing import Any, Dict, Optional, Tuple
import torch
import triton
import triton.language as tl
import vllm.envs as envs
from vllm import _custom_o... | --- python/sglang/srt/layers/fused_moe/fused_moe.py
+++ python/sglang/srt/layers/fused_moe/fused_moe.py
@@ -54,6 +54,7 @@
top_k: tl.constexpr,
compute_type: tl.constexpr,
use_fp8: tl.constexpr,
+ even_Ks: tl.constexpr,
):
"""
Implements the fused computation for a Mixture of Experts (MOE) u... | 23 | 7 | 2 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/fused_moe/fused_moe.py).
Goal: [Performance, Triton] Optimize over mask compute to tl.load in fused_moe_kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```python
# Adapted from
# https://github.com/vllm-project/vllm/tr... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
Test shows `~0.5%` boost to prefill, `~1.0%` boost ... | [{"scope": "e2e", "hardware": null, "model": "Grok-1", "shape": "b32/i1023/o256", "batch_size": null, "metric": "prefill throughput", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.005, "speedup": 1.005}, {"scope": "e2e", "hardware": null, "model": "Grok-1", "shape": "b... | null | 1.0075 |
sglang | 67c424cce310d36b7261992ebce00bd218378769 | 2024-11-07T18:24:02-08:00 | 1,941 | https://github.com/sgl-project/sglang/pull/1941 | [Performance, Triton Kernel Args] extend_attention, optimize kern args to _fwd_kernel (#1941) | [Performance, Triton Kernel Args] extend_attention, optimize kern args to _fwd_kernel (#1941) | python/sglang/srt/layers/attention/triton_ops/extend_attention.py | triton | Apache-2.0 | """
Copyright 2023-2024 SGLang Team
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, softwar... | """
Copyright 2023-2024 SGLang Team
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, softwar... | --- python/sglang/srt/layers/attention/triton_ops/extend_attention.py
+++ python/sglang/srt/layers/attention/triton_ops/extend_attention.py
@@ -25,6 +25,7 @@
from sglang.srt.layers.attention.triton_ops.prefill_attention import (
context_attention_fwd,
)
+from sglang.srt.utils import is_hip
is_cuda_available =... | 6 | 0 | 1 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/attention/triton_ops/extend_attention.py).
Goal: [Performance, Triton Kernel Args] extend_attention, optimize kern args to _fwd_kernel
Target hardware: unspecified
Target models: unspecified
Current file:
```python
"""
Copyright 2023-2024 SGLang T... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
Speedup:
`Llama-3.1-8B, TP=8, FP8, b32/i1024`: pref... | [{"scope": "e2e", "hardware": null, "model": "Llama-3.1-8B", "shape": "TP=8, FP8, b32/i1024", "batch_size": 32, "metric": "prefill throughput", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.0282, "speedup": 1.0282}, {"scope": "e2e", "hardware": null, "model": "Grok-1",... | null | 1.0252 |
sglang | 2d4ce1b7928d253144bc4b030a643af2b9267b40 | 2024-10-30T17:33:36-07:00 | 1,845 | https://github.com/sgl-project/sglang/pull/1845 | [Performance, Triton Kernel Args] _decode_grouped_softmax_reducev_fwd… (#1845) | [Performance, Triton Kernel Args] _decode_grouped_softmax_reducev_fwd… (#1845) | python/sglang/srt/layers/attention/triton_ops/decode_attention.py | triton | Apache-2.0 | """
Copyright 2023-2024 SGLang Team
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, softwar... | """
Copyright 2023-2024 SGLang Team
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, softwar... | --- python/sglang/srt/layers/attention/triton_ops/decode_attention.py
+++ python/sglang/srt/layers/attention/triton_ops/decode_attention.py
@@ -23,6 +23,8 @@
# https://github.com/ModelTC/lightllm/blob/f2a54f0912293f683bf1d1695fd12c4098a5bf82/lightllm/models/llama/triton_kernel/token_attention_softmax_and_reducev.py
i... | 9 | 0 | 1 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/attention/triton_ops/decode_attention.py).
Goal: [Performance, Triton Kernel Args] _decode_grouped_softmax_reducev_fwd…
Target hardware: unspecified
Target models: unspecified
Current file:
```python
"""
Copyright 2023-2024 SGLang Team
Licensed un... | … speedup on ROCm
<!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
Speedup `_decode_grouped_softmax... | [{"scope": "e2e", "hardware": "MI300x", "model": "Grok-1", "shape": "b32/i1024/o256", "batch_size": 32, "metric": "decode throughput", "unit": "tok/s", "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.01, "speedup": 1.01}] | null | 1.01 |
sglang | 5f65e2b830a4cf752ae8ab5739ae7ad958eced83 | 2024-10-30T12:17:32-07:00 | 1,836 | https://github.com/sgl-project/sglang/pull/1836 | [Performance, Hardware] MoE weights padding to AMD MI300x GPUs (#1836) | [Performance, Hardware] MoE weights padding to AMD MI300x GPUs (#1836) | python/sglang/srt/layers/fused_moe/fused_moe.py | triton | Apache-2.0 | # Adapted from
# https://github.com/vllm-project/vllm/tree/v0.5.4/vllm/model_executor/layers/fused_moe
"""Fused MoE kernel."""
import functools
import json
import os
from typing import Any, Dict, Optional, Tuple
import torch
import triton
import triton.language as tl
import vllm.envs as envs
from vllm import _custom_o... | # Adapted from
# https://github.com/vllm-project/vllm/tree/v0.5.4/vllm/model_executor/layers/fused_moe
"""Fused MoE kernel."""
import functools
import json
import os
from typing import Any, Dict, Optional, Tuple
import torch
import triton
import triton.language as tl
import vllm.envs as envs
from vllm import _custom_o... | --- python/sglang/srt/layers/fused_moe/fused_moe.py
+++ python/sglang/srt/layers/fused_moe/fused_moe.py
@@ -14,6 +14,7 @@
from vllm.logger import init_logger
logger = init_logger(__name__)
+padding_size = 128 if bool(int(os.getenv("MOE_PADDING", "0"))) else 0
@triton.jit
@@ -263,7 +264,7 @@
expert_ids... | 4 | 3 | 2 | [] | [
"MI300X"
] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/fused_moe/fused_moe.py).
Goal: [Performance, Hardware] MoE weights padding to AMD MI300x GPUs
Target hardware: MI300X
Target models: unspecified
Current file:
```python
# Adapted from
# https://github.com/vllm-project/vllm/tree/v0.5.4/vllm/model_e... | <!-- Thank you for your contribution! We appreciate it. The following guidelines will help improve your pull request and facilitate feedback. If anything is unclear, don't hesitate to submit your pull request and ask the maintainers for assistance. -->
## Motivation
Padding MoE weights (last dim) to minimize Memory C... | [{"scope": "e2e", "hardware": "AMD MI300x", "model": "Grok-1", "shape": "b32/i1024/o512", "batch_size": 32, "metric": "latency", "unit": null, "higher_is_better": false, "baseline": null, "optimized": null, "stated_speedup": 1.022, "speedup": 1.022}, {"scope": "e2e", "hardware": "AMD MI300x", "model": "Grok-1", "shape"... | null | 1.026 |
sglang | df191254abc002b3284560d9c4b94214a4656265 | 2024-08-19T18:23:07+08:00 | 1,138 | https://github.com/sgl-project/sglang/pull/1138 | Optimize MLA/GQA/MQA Triton decoding (#1138) | Optimize MLA/GQA/MQA Triton decoding (#1138)
Co-authored-by: Yineng Zhang <me@zhyncs.com> | python/sglang/srt/layers/decode_attention.py | triton | Apache-2.0 | """
Copyright 2023-2024 SGLang Team
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, softwar... | """
Copyright 2023-2024 SGLang Team
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, softwar... | --- python/sglang/srt/layers/decode_attention.py
+++ python/sglang/srt/layers/decode_attention.py
@@ -58,7 +58,6 @@
att_stride_h,
kv_group_num: tl.constexpr,
BLOCK_DMODEL: tl.constexpr,
- BLOCK_DPE: tl.constexpr,
BLOCK_N: tl.constexpr,
logit_cap: tl.constexpr,
):
@@ -77,10 +76,6 @@
cur... | 337 | 49 | 1 | [] | [] | [] | Optimize this triton kernel file from sglang (python/sglang/srt/layers/decode_attention.py).
Goal: Optimize MLA/GQA/MQA Triton decoding
Target hardware: unspecified
Target models: unspecified
Current file:
```python
"""
Copyright 2023-2024 SGLang Team
Licensed under the Apache License, Version 2.0 (the "License");
yo... | <!-- Thank you for your contribution, we really appreciate it. The following instructions will help improve your pull request and make it easier to receive feedback. If there are any items you don't understand, don't worry. Just submit the pull request and ask the maintainers for help. -->
## Motivation
Optimize memo... | [] | null | null |
flashinfer | c66ced7b31c0ed860ae87b249f55004c9e530d78 | 2026-10-17T18:50:27-07:00 | 6,525 | https://github.com/flashinfer-ai/flashinfer/pull/6525 | perf(cake_deepgemm_mixed_gemm): cooperative mbarrier initialisation, early load start, and a split-K route for the 148-SM M = 16 / N = 4608 / K = 5120 swap-AB configuration (SM100a, SM103a; shipped programs bitwise unchanged, split-K output deterministic) (#6525) | perf(cake_deepgemm_mixed_gemm): cooperative mbarrier initialisation, early load start, and a split-K route for the 148-SM M = 16 / N = 4608 / K = 5120 swap-AB configuration (SM100a, SM103a; shipped programs bitwise unchanged, split-K output deterministic) (#6525)
## Summary
Regenerates the mixed FP8 x FP4 GEMM family... | csrc/experimental/deepgemm_mixed_gemm/cake_deepgemm_mixed_gemm_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/experimental/deepgemm_mixed_gemm/cake_deepgemm_mixed_gemm_device_common.cuh
+++ csrc/experimental/deepgemm_mixed_gemm/cake_deepgemm_mixed_gemm_device_common.cuh
@@ -19,7 +19,8 @@
// Generated by cake.codegen — do not edit.
// Shared device preamble of the sm_100a, sm_103a generated kernels: typedefs, tenso... | 17 | 141 | 2 | [] | [
"B200",
"GB300",
"SM100",
"SM103"
] | [
"1.05x",
"3 x",
"36 x",
"128 x",
"1.05x",
"1.0309x",
"1.0465x",
"0.9967x",
"1.0000x",
"1.0219x"
] | Optimize this cuda kernel file from flashinfer (csrc/experimental/deepgemm_mixed_gemm/cake_deepgemm_mixed_gemm_device_common.cuh).
Goal: perf(cake_deepgemm_mixed_gemm): cooperative mbarrier initialisation, early load start, and a split-K route for the 148-SM M = 16 / N = 4608 / K = 5120 swap-AB configuration (SM100a, ... | ## Summary
Regenerates the mixed FP8 x FP4 GEMM family `flashinfer.experimental.deepgemm_mixed_gemm` (public API `flashinfer.fp8_fp4_gemm.prepare_fp8_fp4_gemm`) for SM100a (B200) and
SM103a (GB300) at FlashInfer `22d60b5bb`. One route change reaches the mixed FP8 x FP4 programs in this update. On a 148-SM device (SM10... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "M=16,N=4608,K=5120", "batch_size": 16, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 8.96, "optimized": 8.704, "stated_speedup": null, "speedup": 1.0294}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "M=16,N... | 1.0294 | null |
flashinfer | f09a0f551e2f6f0f1f90434e267c2a2b39f66052 | 2026-10-17T18:45:23-07:00 | 6,524 | https://github.com/flashinfer-ai/flashinfer/pull/6524 | perf(cake_deepgemm_fp4_gemm): cooperative mbarrier initialisation on six routes, early load start on the BN224 / BN256 routes, and a cross-pass epilogue pipeline on the normal BN160 program (SM100a, SM103a; outputs bitwise unchanged) (#6524) | perf(cake_deepgemm_fp4_gemm): cooperative mbarrier initialisation on six routes, early load start on the BN224 / BN256 routes, and a cross-pass epilogue pipeline on the normal BN160 program (SM100a, SM103a; outputs bitwise unchanged) (#6524)
## Summary
Regenerates the native FP4 GEMM family
`flashinfer.experimental.d... | csrc/experimental/deepgemm_fp4_gemm/cake_deepgemm_fp4_gemm_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
... | /*
* Copyright (c) 2026 by FlashInfer team.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
... | --- csrc/experimental/deepgemm_fp4_gemm/cake_deepgemm_fp4_gemm_device_common.cuh
+++ csrc/experimental/deepgemm_fp4_gemm/cake_deepgemm_fp4_gemm_device_common.cuh
@@ -20,7 +20,8 @@
// Generated by cake.codegen — do not edit.
// Shared device preamble of the sm_100a, sm_103a generated kernels: typedefs, tensor-map AB... | 17 | 141 | 2 | [] | [
"B200",
"GB300",
"SM100",
"SM103"
] | [
"1.05x",
"1.0309x",
"1.0422x",
"0.9862x",
"1.0000x",
"1.0177x",
"0.9946x",
"1.0113x",
"1.0000x",
"1.0085x"
] | Optimize this cuda kernel file from flashinfer (csrc/experimental/deepgemm_fp4_gemm/cake_deepgemm_fp4_gemm_device_common.cuh).
Goal: perf(cake_deepgemm_fp4_gemm): cooperative mbarrier initialisation on six routes, early load start on the BN224 / BN256 routes, and a cross-pass epilogue pipeline on the normal BN160 prog... | ## Summary
Regenerates the native FP4 GEMM family `flashinfer.experimental.deepgemm_fp4_gemm` (public API `flashinfer.fp4_gemm.prepare_fp4_gemm`) for SM100a (B200) and
SM103a (GB300) at FlashInfer `22d60b5bb`. One exact schedule change reaches the native FP4 GEMM programs in this update. The normal BN160 program (`nor... | [{"scope": "kernel", "hardware": "B200", "model": "model-fp4gemm-l2-m512", "shape": null, "batch_size": 512, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 7.5, "optimized": 6.912, "stated_speedup": null, "speedup": 1.0851}, {"scope": "kernel", "hardware": "GB300", "model": "model-fp4gemm-l2-... | 1.0566 | null |
flashinfer | ccce2135a71dee8d50cb37cb5bacb5656879985e | 2026-10-17T12:05:12-07:00 | 6,518 | https://github.com/flashinfer-ai/flashinfer/pull/6518 | perf(cake_msa): faster Blackwell MSA uniform-FP8 decode and Top-K programs — epilogue overlap and QK ahead of PV (D-U1, D-U2, D-U2b), streaming Top-K merge network (S2), tradix v2 radix layout, per-architecture topk_select (CAKE-1183 round 10) (#6518) | perf(cake_msa): faster Blackwell MSA uniform-FP8 decode and Top-K programs — epilogue overlap and QK ahead of PV (D-U1, D-U2, D-U2b), streaming Top-K merge network (S2), tradix v2 radix layout, per-architecture topk_select (CAKE-1183 round 10) (#6518)
> Developed by the **CAKE team**, this PR re-exports the Cake-gener... | csrc/blackwell_msa/cake_blackwell_msa_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- csrc/blackwell_msa/cake_blackwell_msa_device_common.cuh
+++ csrc/blackwell_msa/cake_blackwell_msa_device_common.cuh
@@ -83,4 +83,3 @@
#include "cake_device_helpers/cake_add_f32x2_74578aa6314ab32b.cuh"
#include "cake_device_helpers/cake_fma_f32x2_rn_ftz_abada39162909eda.cuh"
#include "cake_device_helpers/cake_tcg... | 0 | 1 | 2 | [
"minimax"
] | [
"B200",
"BLACKWELL",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"1.1398×",
"1.1355×",
"1.1230×",
"8 ×",
"11 ×"
] | Optimize this cuda kernel file from flashinfer (csrc/blackwell_msa/cake_blackwell_msa_device_common.cuh).
Goal: perf(cake_msa): faster Blackwell MSA uniform-FP8 decode and Top-K programs — epilogue overlap and QK ahead of PV (D-U1, D-U2, D-U2b), streaming Top-K merge network (S2), tradix v2 radix layout, per-architect... | > Developed by the **CAKE team**, this PR re-exports the Cake-generated MiniMax Sparse Attention family for SM100 / SM103 with the CAKE-1183 levers accepted in rounds 9-10 that are not yet on `main`.
> Two route groups change: uniform-FP8 decode (D-U1, D-U2, D-U2b) and Top-K select (S2, tradix v2, per-architecture `top... | [{"scope": "kernel", "hardware": "GB300", "model": null, "shape": "FP8 decode, 14 rows (12 uniform-FP8 q8 + 2 legacy q1)", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.747, "speedup": 1.747}, {"scope": "kernel", "hardware": "B2... | 1.5491 | null |
flashinfer | 3184bbea6e41290320237fbda2ed87b05661881e | 2026-10-16T22:53:55-07:00 | 6,577 | https://github.com/flashinfer-ai/flashinfer/pull/6577 | perf(cake_fused_moe): swap-AB cluster split-K GEMM1 forms, grouped dense raster and the CuTe DSL cluster rendezvous fix for the Kimi-K3 MXFP4 SiTU MoE export (cake, cake_cute) (#6577) | perf(cake_fused_moe): swap-AB cluster split-K GEMM1 forms, grouped dense raster and the CuTe DSL cluster rendezvous fix for the Kimi-K3 MXFP4 SiTU MoE export (cake, cake_cute) (#6577)
## Summary
Re-renders the two Cake-exported Kimi-K3 MXFP4 SiTU MoE backends from
Cake revision `d28a547564d7` with one command. The ba... | flashinfer/fused_moe/cake_cute/cake_mxfp4_situ_moe_kernels.py | cute_dsl | Apache-2.0 | #
# Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | #
# Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | --- flashinfer/fused_moe/cake_cute/cake_mxfp4_situ_moe_kernels.py
+++ flashinfer/fused_moe/cake_cute/cake_mxfp4_situ_moe_kernels.py
@@ -327,6 +327,7 @@
*,
pdl_trigger_after_wait: bool | None = None,
weight_l2_hint: bool | None = None,
+ cluster_split: bool = False,
) -> Kernel:
"""The swap-AB GE... | 5 | 1 | 4 | [
"deepseek",
"kimi"
] | [
"B300",
"CPU",
"HOPPER",
"SM103"
] | [
"128 x",
"2 x",
"0 x",
"3 x",
"3 x",
"51 x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cake_cute/cake_mxfp4_situ_moe_kernels.py).
Goal: perf(cake_fused_moe): swap-AB cluster split-K GEMM1 forms, grouped dense raster and the CuTe DSL cluster rendezvous fix for the Kimi-K3 MXFP4 SiTU MoE export (cake, cake_cute)
Target hardware: B300... | ## Summary
Re-renders the two Cake-exported Kimi-K3 MXFP4 SiTU MoE backends from Cake revision `d28a547564d7` with one command. The backends are `flashinfer/fused_moe/cake/` for `backend="cake"` (cuda_cpp) and `flashinfer/fused_moe/cake_cute/` for `backend="cake_cute"` (CuTe DSL). Their device sources live under `csrc... | [{"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size": null, "metric": "geomean speedup", "unit": null, "higher_is_better": true, "baseline": 1.2527, "optimized": 1.2647, "stated_speedup": null, "speedup": 1.0096}, {"scope": "e2e", "hardware": "B300", "model": null, "shape": null, "batch_size... | null | 1.0137 |
flashinfer | 92f2b13f022ed2080c8ab8b6d29c7ce5536c3021 | 2026-10-16T15:48:46-07:00 | 6,578 | https://github.com/flashinfer-ai/flashinfer/pull/6578 | perf(cake_dsv4): launch the NVFP4 sparse-MLA decode split-KV merge with programmatic dependent launch (SM100/SM103) (#6578) | perf(cake_dsv4): launch the NVFP4 sparse-MLA decode split-KV merge with programmatic dependent launch (SM100/SM103) (#6578)
## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family
(`backend="cake"`, `kv_cache_format="nvfp4"`)
with one change, in the split-KV **merge** kernel and its launche... | csrc/cake_dsv4/common/cake_dsv4_nvfp4_merge_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_dsv4/common/cake_dsv4_nvfp4_merge_binding.cu
+++ csrc/cake_dsv4/common/cake_dsv4_nvfp4_merge_binding.cu
@@ -15,7 +15,7 @@
*/
// Generated by the Cake source exporter — do not edit.
-// tvm-ffi direct-source launcher for Cake kernel 'kernel_cake_dsv4_nvfp4_a9c628c1d0493dc9608a'.
+// tvm-ffi direct-sou... | 12 | 6 | 3 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"0.912x",
"0.905x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_dsv4/common/cake_dsv4_nvfp4_merge_binding.cu).
Goal: perf(cake_dsv4): launch the NVFP4 sparse-MLA decode split-KV merge with programmatic dependent launch (SM100/SM103)
Target hardware: B200, CPU, GB300, SM100, SM103
Target models: deepseek
Current file:
```cu... | ## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family (`backend="cake"`, `kv_cache_format="nvfp4"`)
with one change, in the split-KV **merge** kernel and its launcher. The merge now waits on the decode grid with
`griddepcontrol.wait`. It is launched with programmatic stream serialization, ... | [{"scope": "kernel", "hardware": "B200", "model": "DeepSeek-V4", "shape": "C-h16-k512-t1", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 10.0, "optimized": 8.03, "stated_speedup": null, "speedup": 1.2453}, {"scope": "kernel", "hardware": "GB300", "model": "DeepSeek-V4", "... | 1.1993 | null |
flashinfer | 92f2b13f022ed2080c8ab8b6d29c7ce5536c3021 | 2026-10-16T15:48:46-07:00 | 6,578 | https://github.com/flashinfer-ai/flashinfer/pull/6578 | perf(cake_dsv4): launch the NVFP4 sparse-MLA decode split-KV merge with programmatic dependent launch (SM100/SM103) (#6578) | perf(cake_dsv4): launch the NVFP4 sparse-MLA decode split-KV merge with programmatic dependent launch (SM100/SM103) (#6578)
## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family
(`backend="cake"`, `kv_cache_format="nvfp4"`)
with one change, in the split-KV **merge** kernel and its launche... | csrc/cake_dsv4/common/cake_dsv4_nvfp4_merge_kernel.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_dsv4/common/cake_dsv4_nvfp4_merge_kernel.cu
+++ csrc/cake_dsv4/common/cake_dsv4_nvfp4_merge_kernel.cu
@@ -25,7 +25,7 @@
extern "C" {
__global__ __launch_bounds__(THREADS, LAUNCH_MIN_BLOCKS) void
-kernel_cake_dsv4_nvfp4_a9c628c1d0493dc9608a(__nv_bfloat16* __restrict__ partial_O, float* __restrict__ par... | 2 | 1 | 3 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"0.912x",
"0.905x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_dsv4/common/cake_dsv4_nvfp4_merge_kernel.cu).
Goal: perf(cake_dsv4): launch the NVFP4 sparse-MLA decode split-KV merge with programmatic dependent launch (SM100/SM103)
Target hardware: B200, CPU, GB300, SM100, SM103
Target models: deepseek
Current file:
```cud... | ## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family (`backend="cake"`, `kv_cache_format="nvfp4"`)
with one change, in the split-KV **merge** kernel and its launcher. The merge now waits on the decode grid with
`griddepcontrol.wait`. It is launched with programmatic stream serialization, ... | [{"scope": "kernel", "hardware": "B200", "model": "DeepSeek-V4", "shape": "C-h16-k512-t1", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 10.0, "optimized": 8.03, "stated_speedup": null, "speedup": 1.2453}, {"scope": "kernel", "hardware": "GB300", "model": "DeepSeek-V4", "... | 1.1993 | null |
flashinfer | 5c5c44c314a6dfe7d918bd7e45a90913168e50e5 | 2026-10-16T13:17:31-07:00 | 6,582 | https://github.com/flashinfer-ai/flashinfer/pull/6582 | perf(cake_ssd_combined): fused exact-scan programs, host routing, look-back chunk-parallel, exactpre family (SM100 / SM103) (#6582) | perf(cake_ssd_combined): fused exact-scan programs, host routing, look-back chunk-parallel, exactpre family (SM100 / SM103) (#6582)
## Summary
This PR updates the generated Cake SSDCombined programs for B200
(sm_100a) and GB300 (sm_103a). It also updates the loader
`flashinfer/mamba/cake_ssd_combined.py`. The baselin... | csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_chunk_parallel_sequence.cpp | cpp | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
// Generated by cake.runtime.host_shim — do not edit.
// CAKE_SSD_TEMPLATE: one launcher for every chunk-parallel SSDCombined program
// (chunkpar_*): the exact-scan arithmetic in grid-barrier-separated phases.... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
// Generated by cake.runtime.host_shim — do not edit.
// CAKE_SSD_TEMPLATE: one launcher for every chunk-parallel SSDCombined program
// (chunkpar_*): the exact-scan arithmetic in grid-barrier-separated phases.... | --- csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_chunk_parallel_sequence.cpp
+++ csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_chunk_parallel_sequence.cpp
@@ -707,6 +707,7 @@
void* p_seq_chunk_cumsum = nullptr;
void* p_out_native = nullptr;
void* p_s_work = nullptr;
+ void* ... | 37 | 23 | 2 | [
"mamba",
"nemotron"
] | [
"B200",
"CPU",
"GB200",
"GB300",
"SM100",
"SM103"
] | [
"162 x",
"81 x",
"12 x"
] | Optimize this cpp kernel file from flashinfer (csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_chunk_parallel_sequence.cpp).
Goal: perf(cake_ssd_combined): fused exact-scan programs, host routing, look-back chunk-parallel, exactpre family (SM100 / SM103)
Target hardware: B200, CPU, GB200, GB300, SM100, ... | ## Summary
This PR updates the generated Cake SSDCombined programs for B200 (sm_100a) and GB300 (sm_103a). It also updates the loader `flashinfer/mamba/cake_ssd_combined.py`. The baseline is the previous release, FlashInfer `36fd76859292ac2ac5aebd0892fc64715569b9da` (PR #6330 merge). The public API is unchanged.
### ... | [{"scope": "kernel", "hardware": "GB300", "model": null, "shape": "perf_varlen_1x1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 14.176, "optimized": 8.576, "stated_speedup": null, "speedup": 1.653}, {"scope": "kernel", "hardware": "GB300", "model": null, "shape": "perf_va... | 1.4115 | null |
flashinfer | 8dad2adc7fb11260230ac14795e179350d79a251 | 2026-10-16T11:29:52-07:00 | 5,312 | https://github.com/flashinfer-ai/flashinfer/pull/5312 | feat(topk_varlen): gvr_2 decode: fused page-table output (page_table), decode latency floor, K=2048 clustered admission, two-CTA slab for unsplit rows (#5312) | feat(topk_varlen): gvr_2 decode: fused page-table output (page_table), decode latency floor, K=2048 clustered admission, two-CTA slab for unsplit rows (#5312)
<!-- .github/pull_request_template.md -->
## 📌 Description
Decode-side work on the `top_k_varlen` gvr_2 backend: the fused
page-table output the DeepSeek-V4 ... | flashinfer/topk_varlen/topk_varlen.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/topk_varlen/topk_varlen.py
+++ flashinfer/topk_varlen/topk_varlen.py
@@ -182,6 +182,8 @@
row_starts=None,
max_window_len=None,
absolute_indices=False,
+ page_table=None,
+ page_size=None,
compress_ratio=None,
next_n=None,
pre_idx=None,
@@ -195,8 +197,8 @@
"""Radix... | 114 | 17 | 4 | [
"deepseek"
] | [
"A100",
"B200",
"B300",
"H100",
"L40S",
"RTX5080",
"SM100",
"SM107",
"SM120"
] | [
"8.24x",
"7.84x",
"7.77x",
"3.04x",
"3.10x",
"2.96x",
"1.04x",
"1.00x",
"1.00x",
"2.01x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/topk_varlen/topk_varlen.py).
Goal: feat(topk_varlen): gvr_2 decode: fused page-table output (page_table), decode latency floor, K=2048 clustered admission, two-CTA slab for unsplit rows
Target hardware: A100, B200, B300, H100, L40S, RTX5080, SM100, SM107, ... | <!-- .github/pull_request_template.md -->
## 📌 Description
Decode-side work on the `top_k_varlen` gvr_2 backend: the fused page-table output the DeepSeek-V4 decode integration asked for (`page_table=` / `page_size=`: the selected keys leave the kernel as physical KV slots), the register-family latency-floor fixes fo... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "K=512,N=4096", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 3.05, "optimized": 3.15, "stated_speedup": 0.968, "speedup": 0.9683}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "K=512,N=8192"... | 1.02 | null |
flashinfer | 840fb69656b336da91f0a8131c2e61b907bbc2cf | 2026-10-16T17:57:51+08:00 | 6,544 | https://github.com/flashinfer-ai/flashinfer/pull/6544 | [Feat] Support Muse-Spark-Open with fused normalization and TP/EP MoE optimizations (#6544) | [Feat] Support Muse-Spark-Open with fused normalization and TP/EP MoE optimizations (#6544)
<!-- .github/pull_request_template.md -->
## 📌 Description
Add fused normalization and TP/EP MoE kernels for Muse Spark that
combine normalization, gating, residual operations, and communication to
reduce intermediate tensor... | flashinfer/comm/mnnvl_cutedsl/cute_dsl_primitives.py | cute_dsl | Apache-2.0 | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | --- flashinfer/comm/mnnvl_cutedsl/cute_dsl_primitives.py
+++ flashinfer/comm/mnnvl_cutedsl/cute_dsl_primitives.py
@@ -887,3 +887,44 @@
loc=loc,
ip=ip,
)
+
+
+@cute.jit
+def load_f32x8(base: cute.Tensor, offset: Int64):
+ pointer = cute.make_ptr(
+ Float32,
+ (base.iterator + offs... | 41 | 0 | 10 | [] | [
"SM100",
"SM103",
"SM107"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/comm/mnnvl_cutedsl/cute_dsl_primitives.py).
Goal: [Feat] Support Muse-Spark-Open with fused normalization and TP/EP MoE optimizations
Target hardware: SM100, SM103, SM107
Target models: unspecified
Current file:
```python
# Copyright (c) 2026 by FlashInfe... | <!-- .github/pull_request_template.md -->
## 📌 Description
Add fused normalization and TP/EP MoE kernels for Muse Spark that combine normalization, gating, residual operations, and communication to reduce intermediate tensors, kernel launches, and data movement.
- **Gated residual RMSNorm fusion:** Fuse RMSNorm, ga... | [] | null | null |
flashinfer | 840fb69656b336da91f0a8131c2e61b907bbc2cf | 2026-10-16T17:57:51+08:00 | 6,544 | https://github.com/flashinfer-ai/flashinfer/pull/6544 | [Feat] Support Muse-Spark-Open with fused normalization and TP/EP MoE optimizations (#6544) | [Feat] Support Muse-Spark-Open with fused normalization and TP/EP MoE optimizations (#6544)
<!-- .github/pull_request_template.md -->
## 📌 Description
Add fused normalization and TP/EP MoE kernels for Muse Spark that
combine normalization, gating, residual operations, and communication to
reduce intermediate tensor... | flashinfer/comm/mnnvl_cutedsl/kernel_ll/device_kernels.py | cute_dsl | Apache-2.0 | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | --- flashinfer/comm/mnnvl_cutedsl/kernel_ll/device_kernels.py
+++ flashinfer/comm/mnnvl_cutedsl/kernel_ll/device_kernels.py
@@ -747,9 +747,6 @@
self.weight_bias = weight_bias
self.add_residual = add_residual
self.write_residual_output = write_residual_output
- # When False the collecti... | 24 | 23 | 10 | [] | [
"SM100",
"SM103",
"SM107"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/comm/mnnvl_cutedsl/kernel_ll/device_kernels.py).
Goal: [Feat] Support Muse-Spark-Open with fused normalization and TP/EP MoE optimizations
Target hardware: SM100, SM103, SM107
Target models: unspecified
Current file:
```python
# Copyright (c) 2026 by Flas... | <!-- .github/pull_request_template.md -->
## 📌 Description
Add fused normalization and TP/EP MoE kernels for Muse Spark that combine normalization, gating, residual operations, and communication to reduce intermediate tensors, kernel launches, and data movement.
- **Gated residual RMSNorm fusion:** Fuse RMSNorm, ga... | [] | null | null |
flashinfer | 840fb69656b336da91f0a8131c2e61b907bbc2cf | 2026-10-16T17:57:51+08:00 | 6,544 | https://github.com/flashinfer-ai/flashinfer/pull/6544 | [Feat] Support Muse-Spark-Open with fused normalization and TP/EP MoE optimizations (#6544) | [Feat] Support Muse-Spark-Open with fused normalization and TP/EP MoE optimizations (#6544)
<!-- .github/pull_request_template.md -->
## 📌 Description
Add fused normalization and TP/EP MoE kernels for Muse Spark that
combine normalization, gating, residual operations, and communication to
reduce intermediate tensor... | flashinfer/comm/mnnvl_cutedsl/kernel_ll/protocol.py | cute_dsl | Apache-2.0 | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | --- flashinfer/comm/mnnvl_cutedsl/kernel_ll/protocol.py
+++ flashinfer/comm/mnnvl_cutedsl/kernel_ll/protocol.py
@@ -139,6 +139,65 @@
class LLProtocolState:
contribution_mailbox: SymmetricBuffer
stage_state: torch.Tensor
+
+
+def create_ll_state(
+ group: dist.ProcessGroup,
+ tp_size: int,
+ rank: in... | 61 | 36 | 10 | [] | [
"SM100",
"SM103",
"SM107"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/comm/mnnvl_cutedsl/kernel_ll/protocol.py).
Goal: [Feat] Support Muse-Spark-Open with fused normalization and TP/EP MoE optimizations
Target hardware: SM100, SM103, SM107
Target models: unspecified
Current file:
```python
# Copyright (c) 2026 by FlashInfer... | <!-- .github/pull_request_template.md -->
## 📌 Description
Add fused normalization and TP/EP MoE kernels for Muse Spark that combine normalization, gating, residual operations, and communication to reduce intermediate tensors, kernel launches, and data movement.
- **Gated residual RMSNorm fusion:** Fuse RMSNorm, ga... | [] | null | null |
flashinfer | 840fb69656b336da91f0a8131c2e61b907bbc2cf | 2026-10-16T17:57:51+08:00 | 6,544 | https://github.com/flashinfer-ai/flashinfer/pull/6544 | [Feat] Support Muse-Spark-Open with fused normalization and TP/EP MoE optimizations (#6544) | [Feat] Support Muse-Spark-Open with fused normalization and TP/EP MoE optimizations (#6544)
<!-- .github/pull_request_template.md -->
## 📌 Description
Add fused normalization and TP/EP MoE kernels for Muse Spark that
combine normalization, gating, residual operations, and communication to
reduce intermediate tensor... | flashinfer/comm/mnnvl_cutedsl/runtime.py | cute_dsl | Apache-2.0 | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | # Copyright (c) 2026 by FlashInfer team.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in... | --- flashinfer/comm/mnnvl_cutedsl/runtime.py
+++ flashinfer/comm/mnnvl_cutedsl/runtime.py
@@ -77,5 +77,51 @@
)
+def is_dense_on(t: torch.Tensor, device: torch.device, alignment: int) -> bool:
+ """Contiguous, on ``device``, with an ``alignment``-byte base address."""
+ return t.device == device and t.is_... | 46 | 0 | 10 | [] | [
"SM100",
"SM103",
"SM107"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/comm/mnnvl_cutedsl/runtime.py).
Goal: [Feat] Support Muse-Spark-Open with fused normalization and TP/EP MoE optimizations
Target hardware: SM100, SM103, SM107
Target models: unspecified
Current file:
```python
# Copyright (c) 2026 by FlashInfer team.
#
# ... | <!-- .github/pull_request_template.md -->
## 📌 Description
Add fused normalization and TP/EP MoE kernels for Muse Spark that combine normalization, gating, residual operations, and communication to reduce intermediate tensors, kernel launches, and data movement.
- **Gated residual RMSNorm fusion:** Fuse RMSNorm, ga... | [] | null | null |
flashinfer | 6eb3221c969fc681f64bf5b04a34e534abd427e9 | 2026-10-16T00:58:11-07:00 | 6,133 | https://github.com/flashinfer-ai/flashinfer/pull/6133 | perf(norm): SM107 launch config for add_rmsnorm_fp4quant (#6133) | perf(norm): SM107 launch config for add_rmsnorm_fp4quant (#6133)
<!-- .github/pull_request_template.md -->
## 📌 Description
On SM107, `add_rmsnorm_fp4quant` (CuTe-DSL) does not get the measured
SM100/SM103 config. It falls back to the generic launch heuristic in
`_compute_launch_config`. This PR adds an SM107 branc... | flashinfer/cute_dsl/add_rmsnorm_fp4quant.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/cute_dsl/add_rmsnorm_fp4quant.py
+++ flashinfer/cute_dsl/add_rmsnorm_fp4quant.py
@@ -329,6 +329,25 @@
return threads_per_row, num_threads
@staticmethod
+ def _compute_sm107_launch_config(
+ H_per_cta: int,
+ elem_size: int,
+ ) -> tuple[int, int]:
+ """Select th... | 22 | 0 | 1 | [] | [
"GB300",
"SM100",
"SM103",
"SM107"
] | [
"2.92x",
"0.44x",
"1.31x",
"4.36x",
"0.32x",
"1.43x",
"3.23x",
"0.39x",
"1.31x",
"4.16x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/cute_dsl/add_rmsnorm_fp4quant.py).
Goal: perf(norm): SM107 launch config for add_rmsnorm_fp4quant
Target hardware: GB300, SM100, SM103, SM107
Target models: unspecified
Current file:
```python
"""
Copyright (c) 2025 by FlashInfer team.
Licensed under the... | <!-- .github/pull_request_template.md -->
## 📌 Description
On SM107, `add_rmsnorm_fp4quant` (CuTe-DSL) does not get the measured SM100/SM103 config. It falls back to the generic launch heuristic in `_compute_launch_config`. This PR adds an SM107 branch, `_compute_sm107_launch_config`, next to the SM100/SM103 one.
*... | [{"scope": "kernel", "hardware": "SM107", "model": null, "shape": "NVFP4 M2048 H4096", "batch_size": 2048, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.92, "speedup": 2.92}, {"scope": "kernel", "hardware": "SM107", "model": null, "shape": "NVFP4 M... | 2.8 | null |
flashinfer | 73437da87c5d80b1f4903e513f526c310a3133ca | 2026-10-15T14:39:03-07:00 | 6,552 | https://github.com/flashinfer-ai/flashinfer/pull/6552 | perf(cake_kimi_k3_fp8_projection): round 11 — static / grid-stride GEMM schedules, PDL-after-weights loader, 19 table adoptions (SM100a, SM103a) (#6552) | perf(cake_kimi_k3_fp8_projection): round 11 — static / grid-stride GEMM schedules, PDL-after-weights loader, 19 table adoptions (SM100a, SM103a) (#6552)
## Summary
This is round 11 of the Cake `kimi_k3_fp8_projection` generated-program
export: the FP8 block-scaled projection GEMMs of the Kimi-K3 KDA / MLA
families, o... | flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh
+++ flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh
@@ -16,7 +16,7 @@
// Generated by cake.codegen — do not e... | 1 | 1 | 4 | [
"kimi"
] | [
"B200",
"B300",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"3 ×",
"3 ×",
"1.10×",
"1.070 ×",
"1.0 ×",
"1.0 ×",
"1.0405 ×",
"1.04032 ×",
"0.99614 ×",
"1.0 ×"
] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh).
Goal: perf(cake_kimi_k3_fp8_projection): round 11 — static / grid-stride GEMM schedules, PDL-after-weights loader, 19 table adoptions (SM100a, ... | ## Summary
This is round 11 of the Cake `kimi_k3_fp8_projection` generated-program export: the FP8 block-scaled projection GEMMs of the Kimi-K3 KDA / MLA families, on SM100 (B200) and SM103 (GB300).
The contract has not changed:
- 352 rows per GPU.
- 198 perf rows: 22 (N, K) families × M in {1, 8, 64, 256, 512, 1024,... | [{"scope": "kernel", "hardware": "SM103", "model": null, "shape": "N=50,K=28,M=1024", "batch_size": 1024, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.624, "optimized": 39.088, "stated_speedup": null, "speedup": 1.0905}, {"scope": "kernel", "hardware": "SM103", "model": null, "shape": "N... | 1.0514 | null |
flashinfer | 042162c8ed2237d4a82404f82032652e25b5c735 | 2026-10-15T14:28:12-07:00 | 6,530 | https://github.com/flashinfer-ai/flashinfer/pull/6530 | perf(cake_deepgemm): SM120 paged MQA-logits indexer: batch-aware Q-atom programs, DeepGEMM block-table cache, num_heads metadata kwarg (#6530) | perf(cake_deepgemm): SM120 paged MQA-logits indexer: batch-aware Q-atom programs, DeepGEMM block-table cache, num_heads metadata kwarg (#6530)
## Summary
> **Speedup over DeepGEMM (geomean of the 216 shapes per device, kernel
time, measured with `max_context_hint`): RTX 5090 1.23×, RTX PRO 6000
1.20×.** Ratios below ... | csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | --- csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_device_common.cuh
+++ csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_device_common.cuh
@@ -19,32 +19,28 @@
// Generated by cake.codegen — do not edit.
// Shared devi... | 16 | 20 | 6 | [
"deepseek"
] | [
"BLACKWELL",
"CPU",
"RTX5090",
"SM120"
] | [
"1.23×",
"1.20×",
"1.21×",
"1.19×",
"2.5×",
"8 ×",
"6 ×",
"8 ×",
"8 ×",
"8 ×"
] | Optimize this cuda kernel file from flashinfer (csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_device_common.cuh).
Goal: perf(cake_deepgemm): SM120 paged MQA-logits indexer: batch-aware Q-atom programs, DeepGEMM block-table cache, num_heads metadata kwarg
Target hardwa... | ## Summary
> **Speedup over DeepGEMM (geomean of the 216 shapes per device, kernel time, measured with `max_context_hint`): RTX 5090 1.23×, RTX PRO 6000 1.20×.** Ratios below are Cake / DeepGEMM time (0.8151 and 0.8354); r2 without the hint measured 1.21× / 1.19×. Best shapes reach 2.5× (32-head `next_n` 5 at batch 25... | [{"scope": "kernel", "hardware": "RTX 5090", "model": null, "shape": null, "batch_size": null, "metric": "kernel time", "unit": null, "higher_is_better": false, "baseline": 1.0, "optimized": 0.8151, "stated_speedup": 1.23, "speedup": 1.2268}, {"scope": "kernel", "hardware": "RTX PRO 6000", "model": null, "shape": null,... | 1.1951 | null |
flashinfer | 042162c8ed2237d4a82404f82032652e25b5c735 | 2026-10-15T14:28:12-07:00 | 6,530 | https://github.com/flashinfer-ai/flashinfer/pull/6530 | perf(cake_deepgemm): SM120 paged MQA-logits indexer: batch-aware Q-atom programs, DeepGEMM block-table cache, num_heads metadata kwarg (#6530) | perf(cake_deepgemm): SM120 paged MQA-logits indexer: batch-aware Q-atom programs, DeepGEMM block-table cache, num_heads metadata kwarg (#6530)
## Summary
> **Speedup over DeepGEMM (geomean of the 216 shapes per device, kernel
time, measured with `max_context_hint`): RTX 5090 1.23×, RTX PRO 6000
1.20×.** Ratios below ... | csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_f48f226f30690af34bd7_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | --- csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_f48f226f30690af34bd7_binding.cu
+++ csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_f48f226f30690af34bd7_binding.cu
@@ -18,30 +18,27 @@
// DeepGEMM portions are licensed... | 14 | 22 | 6 | [
"deepseek"
] | [
"BLACKWELL",
"CPU",
"RTX5090",
"SM120"
] | [
"1.23×",
"1.20×",
"1.21×",
"1.19×",
"2.5×",
"8 ×",
"6 ×",
"8 ×",
"8 ×",
"8 ×"
] | Optimize this cuda kernel file from flashinfer (csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_f48f226f30690af34bd7_binding.cu).
Goal: perf(cake_deepgemm): SM120 paged MQA-logits indexer: batch-aware Q-atom programs, DeepGEMM block-table cache, num_heads metadata kwarg... | ## Summary
> **Speedup over DeepGEMM (geomean of the 216 shapes per device, kernel time, measured with `max_context_hint`): RTX 5090 1.23×, RTX PRO 6000 1.20×.** Ratios below are Cake / DeepGEMM time (0.8151 and 0.8354); r2 without the hint measured 1.21× / 1.19×. Best shapes reach 2.5× (32-head `next_n` 5 at batch 25... | [{"scope": "kernel", "hardware": "RTX 5090", "model": null, "shape": null, "batch_size": null, "metric": "kernel time", "unit": null, "higher_is_better": false, "baseline": 1.0, "optimized": 0.8151, "stated_speedup": 1.23, "speedup": 1.2268}, {"scope": "kernel", "hardware": "RTX PRO 6000", "model": null, "shape": null,... | 1.1951 | null |
flashinfer | 042162c8ed2237d4a82404f82032652e25b5c735 | 2026-10-15T14:28:12-07:00 | 6,530 | https://github.com/flashinfer-ai/flashinfer/pull/6530 | perf(cake_deepgemm): SM120 paged MQA-logits indexer: batch-aware Q-atom programs, DeepGEMM block-table cache, num_heads metadata kwarg (#6530) | perf(cake_deepgemm): SM120 paged MQA-logits indexer: batch-aware Q-atom programs, DeepGEMM block-table cache, num_heads metadata kwarg (#6530)
## Summary
> **Speedup over DeepGEMM (geomean of the 216 shapes per device, kernel
time, measured with `max_context_hint`): RTX 5090 1.23×, RTX PRO 6000
1.20×.** Ratios below ... | csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_f48f226f30690af34bd7_kernel.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | --- csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_f48f226f30690af34bd7_kernel.cu
+++ csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_f48f226f30690af34bd7_kernel.cu
@@ -30,108 +30,107 @@
extern "C" {
-__global__
-__l... | 94 | 95 | 6 | [
"deepseek"
] | [
"BLACKWELL",
"CPU",
"RTX5090",
"SM120"
] | [
"1.23×",
"1.20×",
"1.21×",
"1.19×",
"2.5×",
"8 ×",
"6 ×",
"8 ×",
"8 ×",
"8 ×"
] | Optimize this cuda kernel file from flashinfer (csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_f48f226f30690af34bd7_kernel.cu).
Goal: perf(cake_deepgemm): SM120 paged MQA-logits indexer: batch-aware Q-atom programs, DeepGEMM block-table cache, num_heads metadata kwarg
... | ## Summary
> **Speedup over DeepGEMM (geomean of the 216 shapes per device, kernel time, measured with `max_context_hint`): RTX 5090 1.23×, RTX PRO 6000 1.20×.** Ratios below are Cake / DeepGEMM time (0.8151 and 0.8354); r2 without the hint measured 1.21× / 1.19×. Best shapes reach 2.5× (32-head `next_n` 5 at batch 25... | [{"scope": "kernel", "hardware": "RTX 5090", "model": null, "shape": null, "batch_size": null, "metric": "kernel time", "unit": null, "higher_is_better": false, "baseline": 1.0, "optimized": 0.8151, "stated_speedup": 1.23, "speedup": 1.2268}, {"scope": "kernel", "hardware": "RTX PRO 6000", "model": null, "shape": null,... | 1.1951 | null |
flashinfer | 042162c8ed2237d4a82404f82032652e25b5c735 | 2026-10-15T14:28:12-07:00 | 6,530 | https://github.com/flashinfer-ai/flashinfer/pull/6530 | perf(cake_deepgemm): SM120 paged MQA-logits indexer: batch-aware Q-atom programs, DeepGEMM block-table cache, num_heads metadata kwarg (#6530) | perf(cake_deepgemm): SM120 paged MQA-logits indexer: batch-aware Q-atom programs, DeepGEMM block-table cache, num_heads metadata kwarg (#6530)
## Summary
> **Speedup over DeepGEMM (geomean of the 216 shapes per device, kernel
time, measured with `max_context_hint`): RTX 5090 1.23×, RTX PRO 6000
1.20×.** Ratios below ... | csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_host_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | --- csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_host_common.cuh
+++ csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_host_common.cuh
@@ -39,8 +39,9 @@
TVM_FFI_CHECK_CUDA_ERROR(cudaGetDeviceCount(&device_count));
i... | 3 | 2 | 6 | [
"deepseek"
] | [
"BLACKWELL",
"CPU",
"RTX5090",
"SM120"
] | [
"1.23×",
"1.20×",
"1.21×",
"1.19×",
"2.5×",
"8 ×",
"6 ×",
"8 ×",
"8 ×",
"8 ×"
] | Optimize this cuda kernel file from flashinfer (csrc/experimental/deepgemm_sm120_paged_mqa_logits/generated/cake_deepgemm_sm120_paged_mqa_logits_host_common.cuh).
Goal: perf(cake_deepgemm): SM120 paged MQA-logits indexer: batch-aware Q-atom programs, DeepGEMM block-table cache, num_heads metadata kwarg
Target hardware... | ## Summary
> **Speedup over DeepGEMM (geomean of the 216 shapes per device, kernel time, measured with `max_context_hint`): RTX 5090 1.23×, RTX PRO 6000 1.20×.** Ratios below are Cake / DeepGEMM time (0.8151 and 0.8354); r2 without the hint measured 1.21× / 1.19×. Best shapes reach 2.5× (32-head `next_n` 5 at batch 25... | [{"scope": "kernel", "hardware": "RTX 5090", "model": null, "shape": null, "batch_size": null, "metric": "kernel time", "unit": null, "higher_is_better": false, "baseline": 1.0, "optimized": 0.8151, "stated_speedup": 1.23, "speedup": 1.2268}, {"scope": "kernel", "hardware": "RTX PRO 6000", "model": null, "shape": null,... | 1.1951 | null |
flashinfer | 0a0cecb50b1250f0b609a9c51f1b25816ba073b8 | 2026-10-14T16:58:06-07:00 | 6,447 | https://github.com/flashinfer-ai/flashinfer/pull/6447 | perf(moe): optimize sparse SM107 MegaMoE decode (#6447) | perf(moe): optimize sparse SM107 MegaMoE decode (#6447)
<!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few
routes are live. This optimizes the existing SM107 Generic and GenPhase
MegaMoE paths by avoiding invalid-slot work, shortening spar... | flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/shim/block_scaled.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
"""SM107 (Rubin) block-scaled swap-AB inference mega-MoE frontend.
Wraps the vendored generic inference and GenPhase kernels behind the standard
two-entry-point mega contract:
- :func:`get_symm_buffer_fo... | # Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
"""SM107 (Rubin) block-scaled swap-AB inference mega-MoE frontend.
Wraps the vendored generic inference and GenPhase kernels behind the standard
two-entry-point mega contract:
- :func:`get_symm_buffer_fo... | --- flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/shim/block_scaled.py
+++ flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/shim/block_scaled.py
@@ -364,15 +364,38 @@
if self.kernel_variant == "genphase":
if self.padded_tokens_per_rank > 1024:
raise ValueError("Ge... | 30 | 7 | 10 | [
"deepseek",
"qwen",
"kimi",
"glm"
] | [
"BLACKWELL",
"CPU",
"H100",
"SM107"
] | [
"1.73×",
"1.51×",
"1.104×",
"1.058×",
"1.037×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/shim/block_scaled.py).
Goal: perf(moe): optimize sparse SM107 MegaMoE decode
Target hardware: BLACKWELL, CPU, H100, SM107
Target models: deepseek, qwen, kimi, glm
Current file:
```python
# Copyright (c) 2026 NV... | <!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few routes are live. This optimizes the existing SM107 Generic and GenPhase MegaMoE paths by avoiding invalid-slot work, shortening sparse metadata handling and reducing tail synchronization ov... | [{"scope": "kernel", "hardware": "SM107", "model": "Qwen-shaped", "shape": "H=2560,I=640,E=512,top-k=10,capacity=1024", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.29, "optimized": 24.49, "stated_speedup": 1.73, "speedup": 1.7268}, {"scope": "kernel", "hardware": "SM107... | 1.104 | null |
flashinfer | 0a0cecb50b1250f0b609a9c51f1b25816ba073b8 | 2026-10-14T16:58:06-07:00 | 6,447 | https://github.com/flashinfer-ai/flashinfer/pull/6447 | perf(moe): optimize sparse SM107 MegaMoE decode (#6447) | perf(moe): optimize sparse SM107 MegaMoE decode (#6447)
<!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few
routes are live. This optimizes the existing SM107 Generic and GenPhase
MegaMoE paths by avoiding invalid-slot work, shortening spar... | flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/communication/nvlink_domain/token_comm.py | cute_dsl | Apache-2.0 | """Metadata-push routing and fused non-deterministic token communication."""
import dataclasses
import os
from typing import Callable, ClassVar, Literal, Optional, Tuple, Union
import cuda.bindings.driver as cuda
import cutlass
import cutlass.cute as cute
import cutlass.pipeline as pipeline
import cutlass.utils
from... | """Metadata-push routing and fused non-deterministic token communication."""
import dataclasses
import os
from typing import Callable, ClassVar, Literal, Optional, Tuple, Union
import cuda.bindings.driver as cuda
import cutlass
import cutlass.cute as cute
import cutlass.pipeline as pipeline
import cutlass.utils
from... | --- flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/communication/nvlink_domain/token_comm.py
+++ flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/communication/nvlink_domain/token_comm.py
@@ -703,6 +703,11 @@
@cute.jit
def _broadcast_sizes_to_peers(self, smem_expert_c... | 49 | 15 | 10 | [
"deepseek",
"qwen",
"kimi",
"glm"
] | [
"BLACKWELL",
"CPU",
"H100",
"SM107"
] | [
"1.73×",
"1.51×",
"1.104×",
"1.058×",
"1.037×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/communication/nvlink_domain/token_comm.py).
Goal: perf(moe): optimize sparse SM107 MegaMoE decode
Target hardware: BLACKWELL, CPU, H100, SM107
Target models: deepseek, qwen, kimi, glm
Current file:
... | <!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few routes are live. This optimizes the existing SM107 Generic and GenPhase MegaMoE paths by avoiding invalid-slot work, shortening sparse metadata handling and reducing tail synchronization ov... | [{"scope": "kernel", "hardware": "SM107", "model": "Qwen-shaped", "shape": "H=2560,I=640,E=512,top-k=10,capacity=1024", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.29, "optimized": 24.49, "stated_speedup": 1.73, "speedup": 1.7268}, {"scope": "kernel", "hardware": "SM107... | 1.104 | null |
flashinfer | 0a0cecb50b1250f0b609a9c51f1b25816ba073b8 | 2026-10-14T16:58:06-07:00 | 6,447 | https://github.com/flashinfer-ai/flashinfer/pull/6447 | perf(moe): optimize sparse SM107 MegaMoE decode (#6447) | perf(moe): optimize sparse SM107 MegaMoE decode (#6447)
<!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few
routes are live. This optimizes the existing SM107 Generic and GenPhase
MegaMoE paths by avoiding invalid-slot work, shortening spar... | flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/helpers/ptx_helpers.py | cute_dsl | Apache-2.0 | """Minimal inline-PTX primitives required by the greenfield NVFP4 kernels."""
from typing import Optional
import cutlass
import cutlass.cute as cute
from cutlass._mlir import ir
from cutlass._mlir.dialects import arith, llvm, vector
from cutlass.cutlass_dsl import Float32, Int32, Int64, T, dsl_user_op
TmaCacheHintE... | """Minimal inline-PTX primitives required by the greenfield NVFP4 kernels."""
from typing import Optional
import cutlass
import cutlass.cute as cute
from cutlass._mlir import ir
from cutlass._mlir.dialects import arith, llvm, vector
from cutlass.cutlass_dsl import Float32, Int32, Int64, T, dsl_user_op
TmaCacheHintE... | --- flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/helpers/ptx_helpers.py
+++ flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/helpers/ptx_helpers.py
@@ -749,3 +749,18 @@
"stg_f32",
"tma_load_1d",
]
+
+
+@dsl_user_op
+def barrier_sync_unaligned(barrier_id, num_threads,... | 15 | 0 | 10 | [
"deepseek",
"qwen",
"kimi",
"glm"
] | [
"BLACKWELL",
"CPU",
"H100",
"SM107"
] | [
"1.73×",
"1.51×",
"1.104×",
"1.058×",
"1.037×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/helpers/ptx_helpers.py).
Goal: perf(moe): optimize sparse SM107 MegaMoE decode
Target hardware: BLACKWELL, CPU, H100, SM107
Target models: deepseek, qwen, kimi, glm
Current file:
```python
"""Minima... | <!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few routes are live. This optimizes the existing SM107 Generic and GenPhase MegaMoE paths by avoiding invalid-slot work, shortening sparse metadata handling and reducing tail synchronization ov... | [{"scope": "kernel", "hardware": "SM107", "model": "Qwen-shaped", "shape": "H=2560,I=640,E=512,top-k=10,capacity=1024", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.29, "optimized": 24.49, "stated_speedup": 1.73, "speedup": 1.7268}, {"scope": "kernel", "hardware": "SM107... | 1.104 | null |
flashinfer | 0a0cecb50b1250f0b609a9c51f1b25816ba073b8 | 2026-10-14T16:58:06-07:00 | 6,447 | https://github.com/flashinfer-ai/flashinfer/pull/6447 | perf(moe): optimize sparse SM107 MegaMoE decode (#6447) | perf(moe): optimize sparse SM107 MegaMoE decode (#6447)
<!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few
routes are live. This optimizes the existing SM107 Generic and GenPhase
MegaMoE paths by avoiding invalid-slot work, shortening spar... | flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_fc12_mainloop.py | cute_dsl | Apache-2.0 | """Mainloop component for the Rubin block-scaled swap-AB FC12 kernel."""
from typing import ClassVar, Optional, Tuple
import cutlass
import cutlass.cute as cute
import cutlass.pipeline as pipeline
import cutlass.utils as utils
import cutlass.utils.blackwell_helpers as sm100_utils
import cutlass.utils.blockscaled_layo... | """Mainloop component for the Rubin block-scaled swap-AB FC12 kernel."""
from typing import ClassVar, Optional, Tuple
import cutlass
from .....helpers.ptx_helpers import barrier_sync_unaligned
import cutlass.cute as cute
import cutlass.pipeline as pipeline
import cutlass.utils as utils
import cutlass.utils.blackwell_... | --- flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_fc12_mainloop.py
+++ flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_fc12_mainloop.py
@@ -3,6 +3,7 @@
from typing import ... | 2 | 1 | 10 | [
"deepseek",
"qwen",
"kimi",
"glm"
] | [
"BLACKWELL",
"CPU",
"H100",
"SM107"
] | [
"1.73×",
"1.51×",
"1.104×",
"1.058×",
"1.037×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_fc12_mainloop.py).
Goal: perf(moe): optimize sparse SM107 MegaMoE decode
Target hardware: BLACKWELL, CPU, H100, SM107
Target models: deepseek, qwe... | <!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few routes are live. This optimizes the existing SM107 Generic and GenPhase MegaMoE paths by avoiding invalid-slot work, shortening sparse metadata handling and reducing tail synchronization ov... | [{"scope": "kernel", "hardware": "SM107", "model": "Qwen-shaped", "shape": "H=2560,I=640,E=512,top-k=10,capacity=1024", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.29, "optimized": 24.49, "stated_speedup": 1.73, "speedup": 1.7268}, {"scope": "kernel", "hardware": "SM107... | 1.104 | null |
flashinfer | 0a0cecb50b1250f0b609a9c51f1b25816ba073b8 | 2026-10-14T16:58:06-07:00 | 6,447 | https://github.com/flashinfer-ai/flashinfer/pull/6447 | perf(moe): optimize sparse SM107 MegaMoE decode (#6447) | perf(moe): optimize sparse SM107 MegaMoE decode (#6447)
<!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few
routes are live. This optimizes the existing SM107 Generic and GenPhase
MegaMoE paths by avoiding invalid-slot work, shortening spar... | flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_fc12_mainloop_gen_specialized.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
"""Mainloop component for the Rubin generation-phase block-scaled swap-AB FC12 kernel.
Three properties separate this from the two mainloops it descends from.
FC1's token operand arrives by ``TILE_GATHER... | # Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
"""Mainloop component for the Rubin generation-phase block-scaled swap-AB FC12 kernel.
Three properties separate this from the two mainloops it descends from.
FC1's token operand arrives by ``TILE_GATHER... | --- flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_fc12_mainloop_gen_specialized.py
+++ flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_fc12_mainloop_gen_specialized.py
@@ -... | 98 | 41 | 10 | [
"deepseek",
"qwen",
"kimi",
"glm"
] | [
"BLACKWELL",
"CPU",
"H100",
"SM107"
] | [
"1.73×",
"1.51×",
"1.104×",
"1.058×",
"1.037×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_fc12_mainloop_gen_specialized.py).
Goal: perf(moe): optimize sparse SM107 MegaMoE decode
Target hardware: BLACKWELL, CPU, H100, SM107
Target model... | <!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few routes are live. This optimizes the existing SM107 Generic and GenPhase MegaMoE paths by avoiding invalid-slot work, shortening sparse metadata handling and reducing tail synchronization ov... | [{"scope": "kernel", "hardware": "SM107", "model": "Qwen-shaped", "shape": "H=2560,I=640,E=512,top-k=10,capacity=1024", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.29, "optimized": 24.49, "stated_speedup": 1.73, "speedup": 1.7268}, {"scope": "kernel", "hardware": "SM107... | 1.104 | null |
flashinfer | 0a0cecb50b1250f0b609a9c51f1b25816ba073b8 | 2026-10-14T16:58:06-07:00 | 6,447 | https://github.com/flashinfer-ai/flashinfer/pull/6447 | perf(moe): optimize sparse SM107 MegaMoE decode (#6447) | perf(moe): optimize sparse SM107 MegaMoE decode (#6447)
<!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few
routes are live. This optimizes the existing SM107 Generic and GenPhase
MegaMoE paths by avoiding invalid-slot work, shortening spar... | flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_mega_moe_kernel.py | cute_dsl | Apache-2.0 | """Fused pull-dispatch MegaMoE kernel composition for Rubin."""
from typing import ClassVar, Optional, Tuple
import cuda.bindings.driver as cuda
import cutlass
import cutlass.cute as cute
import cutlass.pipeline as pipeline
import cutlass.utils as utils
import cutlass.utils.blockscaled_layout as blockscaled_utils
fr... | """Fused pull-dispatch MegaMoE kernel composition for Rubin."""
from typing import ClassVar, Optional, Tuple
import cuda.bindings.driver as cuda
import cutlass
from .....helpers.ptx_helpers import barrier_sync_unaligned
import cutlass.cute as cute
import cutlass.pipeline as pipeline
import cutlass.utils as utils
imp... | --- flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_mega_moe_kernel.py
+++ flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_mega_moe_kernel.py
@@ -5,6 +5,7 @@
import cuda.bin... | 9 | 3 | 10 | [
"deepseek",
"qwen",
"kimi",
"glm"
] | [
"BLACKWELL",
"CPU",
"H100",
"SM107"
] | [
"1.73×",
"1.51×",
"1.104×",
"1.058×",
"1.037×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_mega_moe_kernel.py).
Goal: perf(moe): optimize sparse SM107 MegaMoE decode
Target hardware: BLACKWELL, CPU, H100, SM107
Target models: deepseek, q... | <!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few routes are live. This optimizes the existing SM107 Generic and GenPhase MegaMoE paths by avoiding invalid-slot work, shortening sparse metadata handling and reducing tail synchronization ov... | [{"scope": "kernel", "hardware": "SM107", "model": "Qwen-shaped", "shape": "H=2560,I=640,E=512,top-k=10,capacity=1024", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.29, "optimized": 24.49, "stated_speedup": 1.73, "speedup": 1.7268}, {"scope": "kernel", "hardware": "SM107... | 1.104 | null |
flashinfer | 0a0cecb50b1250f0b609a9c51f1b25816ba073b8 | 2026-10-14T16:58:06-07:00 | 6,447 | https://github.com/flashinfer-ai/flashinfer/pull/6447 | perf(moe): optimize sparse SM107 MegaMoE decode (#6447) | perf(moe): optimize sparse SM107 MegaMoE decode (#6447)
<!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few
routes are live. This optimizes the existing SM107 Generic and GenPhase
MegaMoE paths by avoiding invalid-slot work, shortening spar... | flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_mega_moe_kernel_gen_specialized.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
"""Generation-phase MegaMoE kernel composition for Rubin.
Specialised for few tokens per rank and large expert parallelism. The narrowing
buys a short communication path: ``GenphaseTokenComm`` is a separa... | # Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
"""Generation-phase MegaMoE kernel composition for Rubin.
Specialised for few tokens per rank and large expert parallelism. The narrowing
buys a short communication path: ``GenphaseTokenComm`` is a separa... | --- flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_mega_moe_kernel_gen_specialized.py
+++ flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_mega_moe_kernel_gen_specialized.py
... | 95 | 47 | 10 | [
"deepseek",
"qwen",
"kimi",
"glm"
] | [
"BLACKWELL",
"CPU",
"H100",
"SM107"
] | [
"1.73×",
"1.51×",
"1.104×",
"1.058×",
"1.037×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/block_scaled_swap_ab_mega_moe_kernel_gen_specialized.py).
Goal: perf(moe): optimize sparse SM107 MegaMoE decode
Target hardware: BLACKWELL, CPU, H100, SM107
Target mod... | <!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few routes are live. This optimizes the existing SM107 Generic and GenPhase MegaMoE paths by avoiding invalid-slot work, shortening sparse metadata handling and reducing tail synchronization ov... | [{"scope": "kernel", "hardware": "SM107", "model": "Qwen-shaped", "shape": "H=2560,I=640,E=512,top-k=10,capacity=1024", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.29, "optimized": 24.49, "stated_speedup": 1.73, "speedup": 1.7268}, {"scope": "kernel", "hardware": "SM107... | 1.104 | null |
flashinfer | 0a0cecb50b1250f0b609a9c51f1b25816ba073b8 | 2026-10-14T16:58:06-07:00 | 6,447 | https://github.com/flashinfer-ai/flashinfer/pull/6447 | perf(moe): optimize sparse SM107 MegaMoE decode (#6447) | perf(moe): optimize sparse SM107 MegaMoE decode (#6447)
<!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few
routes are live. This optimizes the existing SM107 Generic and GenPhase
MegaMoE paths by avoiding invalid-slot work, shortening spar... | flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/token_comm_gen_specialized.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
"""Genphase MegaMoE token communication.
The design target is a single cross-rank round trip on the critical path. Both
outbound transfers leave at kernel entry with no routing dependency:
exchange CTA... | # Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
"""Genphase MegaMoE token communication.
The design target is a single cross-rank round trip on the critical path. Both
outbound transfers leave at kernel entry with no routing dependency:
exchange CTA... | --- flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/token_comm_gen_specialized.py
+++ flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/token_comm_gen_specialized.py
@@ -202,6 +202,7 @@
refine_work_counter_region:... | 117 | 47 | 10 | [
"deepseek",
"qwen",
"kimi",
"glm"
] | [
"BLACKWELL",
"CPU",
"H100",
"SM107"
] | [
"1.73×",
"1.51×",
"1.104×",
"1.058×",
"1.037×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/token_comm_gen_specialized.py).
Goal: perf(moe): optimize sparse SM107 MegaMoE decode
Target hardware: BLACKWELL, CPU, H100, SM107
Target models: deepseek, qwen, kimi,... | <!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few routes are live. This optimizes the existing SM107 Generic and GenPhase MegaMoE paths by avoiding invalid-slot work, shortening sparse metadata handling and reducing tail synchronization ov... | [{"scope": "kernel", "hardware": "SM107", "model": "Qwen-shaped", "shape": "H=2560,I=640,E=512,top-k=10,capacity=1024", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.29, "optimized": 24.49, "stated_speedup": 1.73, "speedup": 1.7268}, {"scope": "kernel", "hardware": "SM107... | 1.104 | null |
flashinfer | 0a0cecb50b1250f0b609a9c51f1b25816ba073b8 | 2026-10-14T16:58:06-07:00 | 6,447 | https://github.com/flashinfer-ai/flashinfer/pull/6447 | perf(moe): optimize sparse SM107 MegaMoE decode (#6447) | perf(moe): optimize sparse SM107 MegaMoE decode (#6447)
<!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few
routes are live. This optimizes the existing SM107 Generic and GenPhase
MegaMoE paths by avoiding invalid-slot work, shortening spar... | flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/topk_reduce.py | cute_dsl | BSD-3-Clause | # Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
"""Device combine reduce: collapse per-(token, topk) fc2 cells into one row.
The combine step writes one fc2 output per ``(token, topk)`` cell; this reduces
over the topk axis into the token-centric ``(to... | # Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# SPDX-License-Identifier: BSD-3-Clause
"""Device combine reduce: collapse per-(token, topk) fc2 cells into one row.
The combine step writes one fc2 output per ``(token, topk)`` cell; this reduces
over the topk axis into the token-centric ``(to... | --- flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/topk_reduce.py
+++ flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/topk_reduce.py
@@ -164,9 +164,10 @@
# topk loop (small enough to not bloat registers; a CTA-... | 26 | 6 | 10 | [
"deepseek",
"qwen",
"kimi",
"glm"
] | [
"BLACKWELL",
"CPU",
"H100",
"SM107"
] | [
"1.73×",
"1.51×",
"1.104×",
"1.058×",
"1.037×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/moe_ep/kernel_src/sm107/next_cutedsl_megamoe/src/sources/kernel_src/rubin/inference/mega/topk_reduce.py).
Goal: perf(moe): optimize sparse SM107 MegaMoE decode
Target hardware: BLACKWELL, CPU, H100, SM107
Target models: deepseek, qwen, kimi, glm
Current f... | <!-- .github/pull_request_template.md -->
## 📌 Description
Sparse decode often reserves a large token capacity while only a few routes are live. This optimizes the existing SM107 Generic and GenPhase MegaMoE paths by avoiding invalid-slot work, shortening sparse metadata handling and reducing tail synchronization ov... | [{"scope": "kernel", "hardware": "SM107", "model": "Qwen-shaped", "shape": "H=2560,I=640,E=512,top-k=10,capacity=1024", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 42.29, "optimized": 24.49, "stated_speedup": 1.73, "speedup": 1.7268}, {"scope": "kernel", "hardware": "SM107... | 1.104 | null |
flashinfer | fd14b3056d0c1aa72c80fc9c35c8493f38c5a9a5 | 2026-10-14T14:18:10-07:00 | 6,267 | https://github.com/flashinfer-ai/flashinfer/pull/6267 | perf(trtllm-gen decode): keep CGA reduction for small-batch long-KV decode; fuse v_scale in the decode wrapper (#6267) | perf(trtllm-gen decode): keep CGA reduction for small-batch long-KV decode; fuse v_scale in the decode wrapper (#6267)
<!-- .github/pull_request_template.md -->
## 📌 Description
This PR makes three changes to trtllm-gen paged decode, one per commit.
Commit 3 extends commit 1 to multi-token (spec-decode) queries.
#... | include/flashinfer/trtllm/fmha/fmhaKernels.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2020-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless r... | /*
* Copyright (c) 2020-2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless r... | --- include/flashinfer/trtllm/fmha/fmhaKernels.cuh
+++ include/flashinfer/trtllm/fmha/fmhaKernels.cuh
@@ -81,6 +81,9 @@
public:
static constexpr int kDynamicNumTokensPerPageThreshold = 128;
static constexpr int kDynamicNumTokensPerPageKernelKey = 128;
+ // Max KV splits per CGA cluster, and the per-CTA KV leng... | 18 | 0 | 2 | [
"deepseek"
] | [
"B200",
"B300",
"BLACKWELL",
"GB300",
"SM107"
] | [
"0.98x",
"1.02x",
"1.12x",
"0.99x",
"1.29x",
"1.00x",
"1.26x",
"1.01x",
"1.29x",
"1.00x"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/trtllm/fmha/fmhaKernels.cuh).
Goal: perf(trtllm-gen decode): keep CGA reduction for small-batch long-KV decode; fuse v_scale in the decode wrapper
Target hardware: B200, B300, BLACKWELL, GB300, SM107
Target models: deepseek
Current file:
```cuda
/*
*... | <!-- .github/pull_request_template.md -->
## 📌 Description
This PR makes three changes to trtllm-gen paged decode, one per commit. Commit 3 extends commit 1 to multi-token (spec-decode) queries.
### 1. `perf(trtllm-gen decode)`: clamp >16 KV splits to the CGA reduction limit
`computeCtaAndClusterConfig` sets the K... | [{"scope": "kernel", "hardware": "SM107", "model": null, "shape": "batch=1,KV=9216,q_heads=64,kv_heads=8,head_dim=64,dtype=fp8", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.12, "speedup": 1.12}, {"scope": "kernel", "hardware": "B... | 1.1 | null |
flashinfer | ba87b199601858ce18ba919369cbedad7d917708 | 2026-10-14T12:19:41-07:00 | 6,357 | https://github.com/flashinfer-ai/flashinfer/pull/6357 | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357) | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357)
## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family
(`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member**
(`nvf... | csrc/cake_device_helpers/cake_desc_encode_a56f6347f8d37641.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_device_helpers/cake_desc_encode_a56f6347f8d37641.cuh
+++ csrc/cake_device_helpers/cake_desc_encode_a56f6347f8d37641.cuh
@@ -1,6 +1,5 @@
/*
- * Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) 2023 by FlashInfer team.
*
* Licensed u... | 2 | 7 | 10 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"0.98x",
"0.99x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_device_helpers/cake_desc_encode_a56f6347f8d37641.cuh).
Goal: perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103)
Target hardware: B200, CPU, GB300, SM100, SM103
Target models: deepseek
Cur... | ## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family (`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member** (`nvfp4_decode_persistent`, the member that serves the 128-head
throughput rows): the next tile's V transform now runs under the current t... | [{"scope": "kernel", "hardware": "B200", "model": "DeepSeek-V4", "shape": "C-h128-k512-t128", "batch_size": 128, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 33.54, "optimized": 32.35, "stated_speedup": null, "speedup": 1.0368}, {"scope": "kernel", "hardware": "GB300", "model": "DeepSeek-V4... | 1.0356 | null |
flashinfer | ba87b199601858ce18ba919369cbedad7d917708 | 2026-10-14T12:19:41-07:00 | 6,357 | https://github.com/flashinfer-ai/flashinfer/pull/6357 | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357) | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357)
## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family
(`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member**
(`nvf... | csrc/cake_device_helpers/cake_tcgen05_commit_3d61b9d0baed52f9.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_device_helpers/cake_tcgen05_commit_3d61b9d0baed52f9.cuh
+++ csrc/cake_device_helpers/cake_tcgen05_commit_3d61b9d0baed52f9.cuh
@@ -1,6 +1,5 @@
/*
- * Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) 2023 by FlashInfer team.
*
* Lice... | 5 | 8 | 10 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"0.98x",
"0.99x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_device_helpers/cake_tcgen05_commit_3d61b9d0baed52f9.cuh).
Goal: perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103)
Target hardware: B200, CPU, GB300, SM100, SM103
Target models: deepseek
... | ## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family (`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member** (`nvfp4_decode_persistent`, the member that serves the 128-head
throughput rows): the next tile's V transform now runs under the current t... | [{"scope": "kernel", "hardware": "B200", "model": "DeepSeek-V4", "shape": "C-h128-k512-t128", "batch_size": 128, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 33.54, "optimized": 32.35, "stated_speedup": null, "speedup": 1.0368}, {"scope": "kernel", "hardware": "GB300", "model": "DeepSeek-V4... | 1.0356 | null |
flashinfer | ba87b199601858ce18ba919369cbedad7d917708 | 2026-10-14T12:19:41-07:00 | 6,357 | https://github.com/flashinfer-ai/flashinfer/pull/6357 | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357) | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357)
## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family
(`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member**
(`nvf... | csrc/cake_device_helpers/cake_tcgen05_cp_32x128b_warpx4_889f02d6972847cb.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_device_helpers/cake_tcgen05_cp_32x128b_warpx4_889f02d6972847cb.cuh
+++ csrc/cake_device_helpers/cake_tcgen05_cp_32x128b_warpx4_889f02d6972847cb.cuh
@@ -1,6 +1,5 @@
/*
- * Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) 2023 by FlashIn... | 3 | 9 | 10 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"0.98x",
"0.99x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_device_helpers/cake_tcgen05_cp_32x128b_warpx4_889f02d6972847cb.cuh).
Goal: perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103)
Target hardware: B200, CPU, GB300, SM100, SM103
Target models:... | ## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family (`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member** (`nvfp4_decode_persistent`, the member that serves the 128-head
throughput rows): the next tile's V transform now runs under the current t... | [{"scope": "kernel", "hardware": "B200", "model": "DeepSeek-V4", "shape": "C-h128-k512-t128", "batch_size": 128, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 33.54, "optimized": 32.35, "stated_speedup": null, "speedup": 1.0368}, {"scope": "kernel", "hardware": "GB300", "model": "DeepSeek-V4... | 1.0356 | null |
flashinfer | ba87b199601858ce18ba919369cbedad7d917708 | 2026-10-14T12:19:41-07:00 | 6,357 | https://github.com/flashinfer-ai/flashinfer/pull/6357 | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357) | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357)
## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family
(`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member**
(`nvf... | csrc/cake_device_helpers/cake_tmem_ld_x16_a9ed61940fdba296.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_device_helpers/cake_tmem_ld_x16_a9ed61940fdba296.cuh
+++ csrc/cake_device_helpers/cake_tmem_ld_x16_a9ed61940fdba296.cuh
@@ -1,6 +1,5 @@
/*
- * Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) 2023 by FlashInfer team.
*
* Licensed u... | 9 | 13 | 10 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"0.98x",
"0.99x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_device_helpers/cake_tmem_ld_x16_a9ed61940fdba296.cuh).
Goal: perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103)
Target hardware: B200, CPU, GB300, SM100, SM103
Target models: deepseek
Cur... | ## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family (`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member** (`nvfp4_decode_persistent`, the member that serves the 128-head
throughput rows): the next tile's V transform now runs under the current t... | [{"scope": "kernel", "hardware": "B200", "model": "DeepSeek-V4", "shape": "C-h128-k512-t128", "batch_size": 128, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 33.54, "optimized": 32.35, "stated_speedup": null, "speedup": 1.0368}, {"scope": "kernel", "hardware": "GB300", "model": "DeepSeek-V4... | 1.0356 | null |
flashinfer | ba87b199601858ce18ba919369cbedad7d917708 | 2026-10-14T12:19:41-07:00 | 6,357 | https://github.com/flashinfer-ai/flashinfer/pull/6357 | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357) | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357)
## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family
(`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member**
(`nvf... | csrc/cake_device_helpers/cake_tmem_ld_x8_38cb8e5e57da80f2.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_device_helpers/cake_tmem_ld_x8_38cb8e5e57da80f2.cuh
+++ csrc/cake_device_helpers/cake_tmem_ld_x8_38cb8e5e57da80f2.cuh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the ... | 1 | 1 | 10 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"0.98x",
"0.99x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_device_helpers/cake_tmem_ld_x8_38cb8e5e57da80f2.cuh).
Goal: perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103)
Target hardware: B200, CPU, GB300, SM100, SM103
Target models: deepseek
Curr... | ## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family (`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member** (`nvfp4_decode_persistent`, the member that serves the 128-head
throughput rows): the next tile's V transform now runs under the current t... | [{"scope": "kernel", "hardware": "B200", "model": "DeepSeek-V4", "shape": "C-h128-k512-t128", "batch_size": 128, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 33.54, "optimized": 32.35, "stated_speedup": null, "speedup": 1.0368}, {"scope": "kernel", "hardware": "GB300", "model": "DeepSeek-V4... | 1.0356 | null |
flashinfer | ba87b199601858ce18ba919369cbedad7d917708 | 2026-10-14T12:19:41-07:00 | 6,357 | https://github.com/flashinfer-ai/flashinfer/pull/6357 | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357) | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357)
## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family
(`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member**
(`nvf... | csrc/cake_dsv4/common/cake_dsv4_nvfp4_decode_persistent_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_dsv4/common/cake_dsv4_nvfp4_decode_persistent_binding.cu
+++ csrc/cake_dsv4/common/cake_dsv4_nvfp4_decode_persistent_binding.cu
@@ -15,7 +15,7 @@
*/
// Generated by the Cake source exporter — do not edit.
-// tvm-ffi direct-source launcher for Cake kernel 'kernel_cake_dsv4_nvfp4_90f6e277b0c617925053'... | 10 | 10 | 10 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"0.98x",
"0.99x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_dsv4/common/cake_dsv4_nvfp4_decode_persistent_binding.cu).
Goal: perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103)
Target hardware: B200, CPU, GB300, SM100, SM103
Target models: deepseek
... | ## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family (`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member** (`nvfp4_decode_persistent`, the member that serves the 128-head
throughput rows): the next tile's V transform now runs under the current t... | [{"scope": "kernel", "hardware": "B200", "model": "DeepSeek-V4", "shape": "C-h128-k512-t128", "batch_size": 128, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 33.54, "optimized": 32.35, "stated_speedup": null, "speedup": 1.0368}, {"scope": "kernel", "hardware": "GB300", "model": "DeepSeek-V4... | 1.0356 | null |
flashinfer | ba87b199601858ce18ba919369cbedad7d917708 | 2026-10-14T12:19:41-07:00 | 6,357 | https://github.com/flashinfer-ai/flashinfer/pull/6357 | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357) | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357)
## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family
(`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member**
(`nvf... | csrc/cake_dsv4/common/cake_dsv4_nvfp4_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_dsv4/common/cake_dsv4_nvfp4_device_common.cuh
+++ csrc/cake_dsv4/common/cake_dsv4_nvfp4_device_common.cuh
@@ -50,8 +50,8 @@
#include <math_constants.h>
#include "cake_device_helpers/cake_elect_sync_1ee8cd91025d8932.cuh"
#include "cake_device_helpers/cake_mbarrier_init_15e581aef85ee586.cuh"
+#include "c... | 6 | 6 | 10 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"0.98x",
"0.99x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_dsv4/common/cake_dsv4_nvfp4_device_common.cuh).
Goal: perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103)
Target hardware: B200, CPU, GB300, SM100, SM103
Target models: deepseek
Current fi... | ## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family (`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member** (`nvfp4_decode_persistent`, the member that serves the 128-head
throughput rows): the next tile's V transform now runs under the current t... | [{"scope": "kernel", "hardware": "B200", "model": "DeepSeek-V4", "shape": "C-h128-k512-t128", "batch_size": 128, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 33.54, "optimized": 32.35, "stated_speedup": null, "speedup": 1.0368}, {"scope": "kernel", "hardware": "GB300", "model": "DeepSeek-V4... | 1.0356 | null |
flashinfer | ba87b199601858ce18ba919369cbedad7d917708 | 2026-10-14T12:19:41-07:00 | 6,357 | https://github.com/flashinfer-ai/flashinfer/pull/6357 | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357) | perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103) (#6357)
## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family
(`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member**
(`nvf... | csrc/cake_dsv4/common/cake_dsv4_nvfp4_host_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_dsv4/common/cake_dsv4_nvfp4_host_common.cuh
+++ csrc/cake_dsv4/common/cake_dsv4_nvfp4_host_common.cuh
@@ -74,7 +74,7 @@
// 4D TMA descriptor for buffer 'tmap_q' — compiled from the
// descriptor's std.Expr global_dim/global_strides/checks record.
-inline CUtensorMap EncodeTma_tmap_q_2a50cecfe3df(const... | 242 | 242 | 10 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"0.98x",
"0.99x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_dsv4/common/cake_dsv4_nvfp4_host_common.cuh).
Goal: perf(cake_dsv4): overlap the next tile's V transform with PV in the NVFP4 sparse-MLA decode persistent member (SM100/SM103)
Target hardware: B200, CPU, GB300, SM100, SM103
Target models: deepseek
Current file... | ## Summary
Re-exports the SM100 / SM103 DeepSeek-V4 NVFP4 sparse-MLA decode family (`backend="cake"`, `kv_cache_format="nvfp4"`)
with one kernel change in the **persistent member** (`nvfp4_decode_persistent`, the member that serves the 128-head
throughput rows): the next tile's V transform now runs under the current t... | [{"scope": "kernel", "hardware": "B200", "model": "DeepSeek-V4", "shape": "C-h128-k512-t128", "batch_size": 128, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 33.54, "optimized": 32.35, "stated_speedup": null, "speedup": 1.0368}, {"scope": "kernel", "hardware": "GB300", "model": "DeepSeek-V4... | 1.0356 | null |
flashinfer | 87ef73934ef61e4d85444b91aeaa8e0df667f6ae | 2026-10-14T01:35:40-07:00 | 6,463 | https://github.com/flashinfer-ai/flashinfer/pull/6463 | perf(cake_msa): faster Blackwell MSA prefill programs — union-route selection census, Q-resident long-route order, two-stage folded-GQA rings, shared-TMEM QK/PV issue order, tile interleave, host-side cu_seqlens_k removal (rounds 4–9 levers) (#6463) | perf(cake_msa): faster Blackwell MSA prefill programs — union-route selection census, Q-resident long-route order, two-stage folded-GQA rings, shared-TMEM QK/PV issue order, tile interleave, host-side cu_seqlens_k removal (rounds 4–9 levers) (#6463)
> Developed by the **CAKE team**, this PR regenerates the **prefill**... | csrc/blackwell_msa/cake_blackwell_msa_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- csrc/blackwell_msa/cake_blackwell_msa_device_common.cuh
+++ csrc/blackwell_msa/cake_blackwell_msa_device_common.cuh
@@ -16,7 +16,7 @@
// Generated by cake.codegen — do not edit.
// Shared device preamble of the sm_100a, sm_103a generated kernels: typedefs, tensor-map ABI
-// and the union of their compiler help... | 1 | 1 | 3 | [
"minimax"
] | [
"B200",
"BLACKWELL",
"CPU",
"GB300",
"SM100",
"SM103"
] | [
"2.7×",
"2.7×",
"1.76×",
"1.94×",
"1.18×",
"1.11×",
"1.04×",
"1.08×",
"0.39×",
"0.59×"
] | Optimize this cuda kernel file from flashinfer (csrc/blackwell_msa/cake_blackwell_msa_device_common.cuh).
Goal: perf(cake_msa): faster Blackwell MSA prefill programs — union-route selection census, Q-resident long-route order, two-stage folded-GQA rings, shared-TMEM QK/PV issue order, tile interleave, host-side cu_seq... | > Developed by the **CAKE team**, this PR regenerates the **prefill** routes of the Cake-generated MiniMax Sparse Attention family for
> SM100 / SM103 with every prefill lever the CAKE-1183 ceiling round accepted since the family's last prefill delivery (#6397): the paged
> `first_topk` rows run **1.8–2.7× faster** (2.... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "N=8192", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 965, "optimized": 411, "stated_speedup": null, "speedup": 2.3479}, {"scope": "kernel", "hardware": "GB300", "model": null, "shape": "N=8192", "batch_size"... | 1.616 | null |
flashinfer | 13149016323d04a2ff439a151c564dde7406e611 | 2026-10-13T20:57:28-07:00 | 6,410 | https://github.com/flashinfer-ai/flashinfer/pull/6410 | perf(cake_msa): faster Blackwell MSA Top-K select programs (keq fold, 32-query instance, plan refit; bit-identical indices) (#6410) | perf(cake_msa): faster Blackwell MSA Top-K select programs (keq fold, 32-query instance, plan refit; bit-identical indices) (#6410)
> Developed by the **CAKE team**, the Top-K select programs in this PR
**outperform** the programs they replace on 3 of the 6 distinct
> frozen Top-K shapes per architecture (1.18–2.28×: ... | csrc/blackwell_msa/cake_blackwell_msa_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- csrc/blackwell_msa/cake_blackwell_msa_device_common.cuh
+++ csrc/blackwell_msa/cake_blackwell_msa_device_common.cuh
@@ -16,7 +16,7 @@
// Generated by cake.codegen — do not edit.
// Shared device preamble of the sm_100a, sm_103a generated kernels: typedefs, tensor-map ABI
-// and the union of their compiler help... | 1 | 1 | 3 | [
"kimi",
"minimax"
] | [
"B200",
"BLACKWELL",
"GB300",
"SM100",
"SM103",
"SM120",
"SM121"
] | [
"2.28×",
"4x"
] | Optimize this cuda kernel file from flashinfer (csrc/blackwell_msa/cake_blackwell_msa_device_common.cuh).
Goal: perf(cake_msa): faster Blackwell MSA Top-K select programs (keq fold, 32-query instance, plan refit; bit-identical indices)
Target hardware: B200, BLACKWELL, GB300, SM100, SM103, SM120, SM121
Target models: ... | > Developed by the **CAKE team**, the Top-K select programs in this PR **outperform** the programs they replace on 3 of the 6 distinct
> frozen Top-K shapes per architecture (1.18–2.28×: the `t1024` shape now served by the new 32-query instance, the tied `t256` shape now
> served by the new all-equal-fold instance, and... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "t1024", "batch_size": null, "metric": "performance ratio", "unit": null, "higher_is_better": true, "baseline": 1, "optimized": 1.1832, "stated_speedup": null, "speedup": 1.1832}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "t1024", "b... | 1.488 | null |
flashinfer | 6326e4aa99289906090f50449e696752e95ac95c | 2026-10-13T17:09:32-07:00 | 6,194 | https://github.com/flashinfer-ai/flashinfer/pull/6194 | perf(cake_fused_moe): Kimi-K3 NVFP4 SiTU experts SM103 single-token fused quant+route FC1 (#6194) | perf(cake_fused_moe): Kimi-K3 NVFP4 SiTU experts SM103 single-token fused quant+route FC1 (#6194)
## Kimi-K3 NVFP4 SiTU experts: SM103 single-token fused quant+route FC1
(re-authored on #6135)
Route the SM103 (B300) single-token row of the Kimi-K3 NVFP4 SiTU
experts to a fused FC1 program that performs the activation... | csrc/fused_moe/cake_kimi_k3_situ/cake_kimi_k3_nvfp4_situ_routed_moe_a264957aa770dad84302_kernel.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/fused_moe/cake_kimi_k3_situ/cake_kimi_k3_nvfp4_situ_routed_moe_a264957aa770dad84302_kernel.cu
+++ csrc/fused_moe/cake_kimi_k3_situ/cake_kimi_k3_nvfp4_situ_routed_moe_a264957aa770dad84302_kernel.cu
@@ -966,12 +966,8 @@
extern __shared__ __align__(1024) char smem_raw[];
int smem;
-#if __CUDA_ARCH__ =... | 0 | 4 | 3 | [
"deepseek",
"kimi"
] | [
"B300",
"HOPPER",
"SM100",
"SM103"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/fused_moe/cake_kimi_k3_situ/cake_kimi_k3_nvfp4_situ_routed_moe_a264957aa770dad84302_kernel.cu).
Goal: perf(cake_fused_moe): Kimi-K3 NVFP4 SiTU experts SM103 single-token fused quant+route FC1
Target hardware: B300, HOPPER, SM100, SM103
Target models: deepseek, kimi
... | ## Kimi-K3 NVFP4 SiTU experts: SM103 single-token fused quant+route FC1 (re-authored on #6135)
Route the SM103 (B300) single-token row of the Kimi-K3 NVFP4 SiTU experts to a fused FC1 program that performs the activation quantization and the expert routing inside the FC1 prologue, so a call runs three kernels (FC1, FC... | [] | null | null |
flashinfer | f77a20b2afb9664b5d2be3b452ee460fa61e2f64 | 2026-10-13T15:30:35-07:00 | 6,413 | https://github.com/flashinfer-ai/flashinfer/pull/6413 | perf(cake_deepgemm): fused 32-head FP8 routes, next_n-4 paged text, static windows (SM100a, SM103a) (#6413) | perf(cake_deepgemm): fused 32-head FP8 routes, next_n-4 paged text, static windows (SM100a, SM103a) (#6413)
## Summary
Re-export of the `deepgemm_dense_mqa` family (dense 32-head FP8 / FP4
and 64-head FP8 MQA logits, paged FP8 MQA logits) from the producer tip
of the third convergence round against the stock DeepGEMM... | csrc/experimental/deepgemm_dense_mqa/generated/cake_deepgemm_dense_mqa_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | --- csrc/experimental/deepgemm_dense_mqa/generated/cake_deepgemm_dense_mqa_device_common.cuh
+++ csrc/experimental/deepgemm_dense_mqa/generated/cake_deepgemm_dense_mqa_device_common.cuh
@@ -19,7 +19,7 @@
// Generated by cake.codegen — do not edit.
// Shared device preamble of the sm_100a, sm_103a generated kernels:... | 1 | 1 | 4 | [] | [
"B200",
"SM100",
"SM103"
] | [
"1.98x",
"64 x",
"32 x",
"64 x",
"64 x",
"64 x",
"256 x",
"2 x"
] | Optimize this cuda kernel file from flashinfer (csrc/experimental/deepgemm_dense_mqa/generated/cake_deepgemm_dense_mqa_device_common.cuh).
Goal: perf(cake_deepgemm): fused 32-head FP8 routes, next_n-4 paged text, static windows (SM100a, SM103a)
Target hardware: B200, SM100, SM103
Target models: unspecified
Current fi... | ## Summary
Re-export of the `deepgemm_dense_mqa` family (dense 32-head FP8 / FP4 and 64-head FP8 MQA logits, paged FP8 MQA logits) from the producer tip of the third convergence round against the stock DeepGEMM kernels (`fp8_mqa_logits` / `fp8_paged_mqa_logits`, sgl-deep-gemm 0.2.0), rebuilt on `main` after the v9 sin... | [{"scope": "kernel", "hardware": "SM100a", "model": null, "shape": "Q=37,K=4137", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.92, "speedup": 1.92}, {"scope": "kernel", "hardware": "SM103a", "model": null, "shape": "Q=37,K=4137", ... | 1.0488 | null |
flashinfer | ea5f740951ac45f8a73aed036e28a5a9c7e57838 | 2026-10-13T13:11:55-07:00 | 6,433 | https://github.com/flashinfer-ai/flashinfer/pull/6433 | perf(cake_kimi_k3_fp8_projection): round 10 — cluster split-K pair GEMM, prefetched stream-K, 128×384 pair-tile GEMM, interleaved confirm protocol and dispatch-table re-tune (SM100a, SM103a) (#6433) | perf(cake_kimi_k3_fp8_projection): round 10 — cluster split-K pair GEMM, prefetched stream-K, 128×384 pair-tile GEMM, interleaved confirm protocol and dispatch-table re-tune (SM100a, SM103a) (#6433)
## Summary
Round 10 of the Cake `kimi_k3_fp8_projection` generated-program export
(FP8 block-scaled projection GEMMs of... | flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh
+++ flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh
@@ -16,7 +16,7 @@
// Generated by cake.codegen — do not e... | 7 | 6 | 4 | [
"kimi"
] | [
"CPU",
"SM100",
"SM103"
] | [
"128 ×",
"3 ×",
"1.0168 ×",
"1.0322\n×",
"24 ×",
"1.043×",
"5 ×",
"0.9617 ×",
"1×",
"0.964×"
] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh).
Goal: perf(cake_kimi_k3_fp8_projection): round 10 — cluster split-K pair GEMM, prefetched stream-K, 128×384 pair-tile GEMM, interleaved confirm... | ## Summary
Round 10 of the Cake `kimi_k3_fp8_projection` generated-program export (FP8 block-scaled projection GEMMs of the Kimi-K3 KDA / MLA families — 22 families, 352 contract rows per GPU: 198 perf rows = 22 (N, K) families × M in {1, 8, 64, 256, 512, 1024, 2048, 4096, 16384} and 154 correctness rows at M 3 / 129 ... | [{"scope": "kernel", "hardware": "SM103", "model": null, "shape": "N=5,K=28,M=2048", "batch_size": 2048, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 24.432, "optimized": 23.616, "stated_speedup": null, "speedup": 1.0346}, {"scope": "kernel", "hardware": "SM100", "model": null, "shape": "N=... | 1.0498 | null |
flashinfer | 5c4058bd9b75967de947971d7f28d36bd600d888 | 2026-10-13T11:07:21+08:00 | 5,168 | https://github.com/flashinfer-ai/flashinfer/pull/5168 | perf(sm12x): optimize fused MoE kernels (#5168) | perf(sm12x): optimize fused MoE kernels (#5168)
<!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the existing SM12x fused FP4 MoE backends, particularly
workloads whose intermediate dimension is not a multiple of 128. The
changes reduce padded weight storage, routing overhead, unnecessary data
mo... | flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_micro_kernel.py | cute_dsl | Apache-2.0 | """
MoEMicroKernel — micro-scheduled routed W4A4 MoE kernel for SM120/SM121.
Ported from the b12x kernel library to FlashInfer.
This is the micro control-plane fusion step for decode workloads: keep the
proven FC1/FC2 compute body, but pull the route/pack frontend into the same
resident kernel, using precompacted rou... | """
MoEMicroKernel — micro-scheduled routed W4A4 MoE kernel for SM120/SM121.
Ported from the b12x kernel library to FlashInfer.
This is the micro control-plane fusion step for decode workloads: keep the
proven FC1/FC2 compute body, but pull the route/pack frontend into the same
resident kernel, using precompacted rou... | --- flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_micro_kernel.py
+++ flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_micro_kernel.py
@@ -682,9 +682,33 @@
)
sfa_tensor = cute.make_tensor(sfa_ptr, sfa_layout)
- # Single SF tensor for concatenated w13 (gate+up scale factors)
+ # w1... | 72 | 34 | 8 | [
"qwen"
] | [
"BLACKWELL",
"SM120"
] | [
"0.55 ×"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/fused_moe/cute_dsl/blackwell_sm12x/moe_micro_kernel.py).
Goal: perf(sm12x): optimize fused MoE kernels
Target hardware: BLACKWELL, SM120
Target models: qwen
Current file:
```python
"""
MoEMicroKernel — micro-scheduled routed W4A4 MoE kernel for SM120/SM12... | <!-- .github/pull_request_template.md -->
## 📌 Description
Optimize the existing SM12x fused FP4 MoE backends, particularly workloads whose intermediate dimension is not a multiple of 128. The changes reduce padded weight storage, routing overhead, unnecessary data movement, and synchronization while preserving supp... | [{"scope": "e2e", "hardware": "NVIDIA Blackwell SM120", "model": null, "shape": "E=512, H=2560, I=320, topk=10", "batch_size": 64, "metric": "latency", "unit": "\u00b5s", "higher_is_better": false, "baseline": 744.27, "optimized": 480.38, "stated_speedup": null, "speedup": 1.5493}, {"scope": "e2e", "hardware": "NVIDIA ... | null | 1.3624 |
flashinfer | 1ed137d9f8283e55c4388782cde4b54eeabad2ea | 2026-10-12T15:50:16-07:00 | 6,375 | https://github.com/flashinfer-ai/flashinfer/pull/6375 | perf(cake_minimax_h3_varlen_attention): round-13 per-plan program dispatch -- dynamic ticket scheduling for long multi-wave plans (SM100a, SM103a) and a publish-tail cut for the SM100a static plans (#6375) | perf(cake_minimax_h3_varlen_attention): round-13 per-plan program dispatch -- dynamic ticket scheduling for long multi-wave plans (SM100a, SM103a) and a publish-tail cut for the SM100a static plans (#6375)
## Summary
`flashinfer.experimental.minimax_h3_varlen_attention` (Cake backend,
SM100a/SM103a BF16 packed-varlen... | flashinfer/experimental/minimax_h3_varlen_attention/csrc/cake_minimax_h3_varlen_attention/cake_minimax_h3_varlen_attention_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- flashinfer/experimental/minimax_h3_varlen_attention/csrc/cake_minimax_h3_varlen_attention/cake_minimax_h3_varlen_attention_device_common.cuh
+++ flashinfer/experimental/minimax_h3_varlen_attention/csrc/cake_minimax_h3_varlen_attention/cake_minimax_h3_varlen_attention_device_common.cuh
@@ -16,7 +16,7 @@
// Genera... | 5 | 4 | 3 | [
"minimax"
] | [
"B200",
"GB300",
"SM100",
"SM103"
] | [
"1.01x"
] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/minimax_h3_varlen_attention/csrc/cake_minimax_h3_varlen_attention/cake_minimax_h3_varlen_attention_device_common.cuh).
Goal: perf(cake_minimax_h3_varlen_attention): round-13 per-plan program dispatch -- dynamic ticket scheduling for long multi-wav... | ## Summary
`flashinfer.experimental.minimax_h3_varlen_attention` (Cake backend, SM100a/SM103a BF16 packed-varlen attention), round 13 on top of #6328. The host planner now selects one of three bitwise-identical programs per plan:
- **Dynamic whole-unit ticket scheduling** (`DYN_SCHED` + ticket prefetch) for plans wit... | [{"scope": "kernel", "hardware": "SM103a", "model": null, "shape": null, "batch_size": null, "metric": "performance ratio", "unit": null, "higher_is_better": true, "baseline": 1.0, "optimized": 1.004, "stated_speedup": 1.004, "speedup": 1.004}, {"scope": "kernel", "hardware": "SM103a", "model": null, "shape": null, "ba... | 1.0055 | null |
flashinfer | ae312f7cc1723b06fda5168105ade0f328ee47d8 | 2026-10-12T00:07:46-07:00 | 6,323 | https://github.com/flashinfer-ai/flashinfer/pull/6323 | perf(cake_gdn): SM107a FP64-free q-scale, fp32 T=1 tilev32 band, chunked-parallel prefill route and native packed-KDA tile64 variant (#6323) | perf(cake_gdn): SM107a FP64-free q-scale, fp32 T=1 tilev32 band, chunked-parallel prefill route and native packed-KDA tile64 variant (#6323)
Follow-up to #6238 (merged). Same backend family as #5467 (@Vinnie6167,
FYI). Cake GDN decode on SM107a (Rubin, CC 10.7) only; SM100a / SM103a
kernel text is unchanged.
## What ... | csrc/gdn/cake/cake_gdn_device_common.cuh | cuda | Apache-2.0 | // Copyright (c) 2026 by FlashInfer team.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or a... | // Copyright (c) 2026 by FlashInfer team.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or a... | --- csrc/gdn/cake/cake_gdn_device_common.cuh
+++ csrc/gdn/cake/cake_gdn_device_common.cuh
@@ -229,3 +229,8 @@
"f"(src[24]), "f"(src[25]), "f"(src[26]), "f"(src[27]),
"f"(src[28]), "f"(src[29]), "f"(src[30]), "f"(src[31]));
}
+
+// Added after the shipped text (append-only delivery): device help... | 5 | 0 | 7 | [] | [
"B200",
"BLACKWELL",
"CPU",
"GB300",
"SM100",
"SM103",
"SM107",
"SM90"
] | [
"0.92×",
"6 ×",
"7 ×",
"4 ×",
"5 ×",
"1.0×",
"1.44×",
"1.041×"
] | Optimize this cuda kernel file from flashinfer (csrc/gdn/cake/cake_gdn_device_common.cuh).
Goal: perf(cake_gdn): SM107a FP64-free q-scale, fp32 T=1 tilev32 band, chunked-parallel prefill route and native packed-KDA tile64 variant
Target hardware: B200, BLACKWELL, CPU, GB300, SM100, SM103, SM107, SM90
Target models: un... | Follow-up to #6238 (merged). Same backend family as #5467 (@Vinnie6167, FYI). Cake GDN decode on SM107a (Rubin, CC 10.7) only; SM100a / SM103a kernel text is unchanged.
## What this PR does
Every Cake GDN decode kernel scales q by `(float)((double)x * SCALE)`. On SM107a that FP64 multiply is now lowered to an exact F... | [{"scope": "e2e", "hardware": "R200", "model": null, "shape": null, "batch_size": 128, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": 1.014, "optimized": 1.132, "stated_speedup": null, "speedup": 1.1164}, {"scope": "e2e", "hardware": "R200", "model": null, "shape": null, "batch_size": 1, "metr... | 1.0484 | 1.2538 |
flashinfer | b05599ede4371d7e9b6b8a89800da351ef6450c4 | 2026-10-11T23:34:03-07:00 | 6,325 | https://github.com/flashinfer-ai/flashinfer/pull/6325 | perf(cake_deepgemm): single-launch 32-head FP8 / FP4 dense MQA logits routes, per-architecture 64-head programs and new paged next_n = 2 geometries; catalog schema v9 re-export (#6325) | perf(cake_deepgemm): single-launch 32-head FP8 / FP4 dense MQA logits routes, per-architecture 64-head programs and new paged next_n = 2 geometries; catalog schema v9 re-export (#6325)
## Summary
Re-export of the `deepgemm_dense_mqa` family (dense 32-head and 64-head
FP8 / FP4 MQA logits, paged FP8 MQA logits) from t... | csrc/cake_device_helpers/cake_mbarrier_wait_relaxed_hint_6c7a98f6a495754c.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | --- csrc/cake_device_helpers/cake_mbarrier_wait_relaxed_hint_6c7a98f6a495754c.cuh
+++ csrc/cake_device_helpers/cake_mbarrier_wait_relaxed_hint_6c7a98f6a495754c.cuh
@@ -24,17 +24,17 @@
// Exact unqualified CTA wait used by source schedules whose PTX intentionally
// omits the acquire qualifier while retaining a type... | 13 | 13 | 4 | [
"deepseek"
] | [
"CPU",
"SM100",
"SM103"
] | [
"1.09x",
"1.05x",
"0.87x",
"1.03x",
"0.98x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_device_helpers/cake_mbarrier_wait_relaxed_hint_6c7a98f6a495754c.cuh).
Goal: perf(cake_deepgemm): single-launch 32-head FP8 / FP4 dense MQA logits routes, per-architecture 64-head programs and new paged next_n = 2 geometries; catalog schema v9 re-export
Target h... | ## Summary
Re-export of the `deepgemm_dense_mqa` family (dense 32-head and 64-head FP8 / FP4 MQA logits, paged FP8 MQA logits) from the producer tip that closes the current DeepSeek-V3.2 lightning-indexer performance round on SM100a / SM103a, onto `main`. The `cake_dsa_indexer` programs regenerated at the same produce... | [{"scope": "kernel", "hardware": "SM103a", "model": null, "shape": null, "batch_size": null, "metric": "performance ratio", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 5.02, "speedup": 5.02}, {"scope": "kernel", "hardware": "SM100a", "model": null, "shape": null, "batc... | 3.425 | 1.735 |
flashinfer | b05599ede4371d7e9b6b8a89800da351ef6450c4 | 2026-10-11T23:34:03-07:00 | 6,325 | https://github.com/flashinfer-ai/flashinfer/pull/6325 | perf(cake_deepgemm): single-launch 32-head FP8 / FP4 dense MQA logits routes, per-architecture 64-head programs and new paged next_n = 2 geometries; catalog schema v9 re-export (#6325) | perf(cake_deepgemm): single-launch 32-head FP8 / FP4 dense MQA logits routes, per-architecture 64-head programs and new paged next_n = 2 geometries; catalog schema v9 re-export (#6325)
## Summary
Re-export of the `deepgemm_dense_mqa` family (dense 32-head and 64-head
FP8 / FP4 MQA logits, paged FP8 MQA logits) from t... | csrc/experimental/deepgemm_dense_mqa/generated/cake_deepgemm_dense_mqa_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | --- csrc/experimental/deepgemm_dense_mqa/generated/cake_deepgemm_dense_mqa_device_common.cuh
+++ csrc/experimental/deepgemm_dense_mqa/generated/cake_deepgemm_dense_mqa_device_common.cuh
@@ -19,7 +19,7 @@
// Generated by cake.codegen — do not edit.
// Shared device preamble of the sm_100a, sm_103a generated kernels:... | 1 | 1 | 4 | [
"deepseek"
] | [
"CPU",
"SM100",
"SM103"
] | [
"1.09x",
"1.05x",
"0.87x",
"1.03x",
"0.98x"
] | Optimize this cuda kernel file from flashinfer (csrc/experimental/deepgemm_dense_mqa/generated/cake_deepgemm_dense_mqa_device_common.cuh).
Goal: perf(cake_deepgemm): single-launch 32-head FP8 / FP4 dense MQA logits routes, per-architecture 64-head programs and new paged next_n = 2 geometries; catalog schema v9 re-expo... | ## Summary
Re-export of the `deepgemm_dense_mqa` family (dense 32-head and 64-head FP8 / FP4 MQA logits, paged FP8 MQA logits) from the producer tip that closes the current DeepSeek-V3.2 lightning-indexer performance round on SM100a / SM103a, onto `main`. The `cake_dsa_indexer` programs regenerated at the same produce... | [{"scope": "kernel", "hardware": "SM103a", "model": null, "shape": null, "batch_size": null, "metric": "performance ratio", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 5.02, "speedup": 5.02}, {"scope": "kernel", "hardware": "SM100a", "model": null, "shape": null, "batc... | 3.425 | 1.735 |
flashinfer | 7eb9b13b70534b1a1b0e6745b0b5bbfbc2783999 | 2026-10-11T23:33:36-07:00 | 6,327 | https://github.com/flashinfer-ai/flashinfer/pull/6327 | perf(cake_dsa_indexer): SM103a dispatch set for the wide, paired and split scan programs of the DSA indexer top-k (SM100a programs unchanged) (#6327) | perf(cake_dsa_indexer): SM103a dispatch set for the wide, paired and split scan programs of the DSA indexer top-k (SM100a programs unchanged) (#6327)
## Summary
Re-export of the `cake_dsa_indexer` top-k programs (scan, merge,
finalize and finalize-rank roles) from the producer tip that closes the
current DeepSeek-V3.... | flashinfer/experimental/cake_dsa_indexer/csrc/cake_dsa_indexer_topk/cake_dsa_indexer_topk_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- flashinfer/experimental/cake_dsa_indexer/csrc/cake_dsa_indexer_topk/cake_dsa_indexer_topk_device_common.cuh
+++ flashinfer/experimental/cake_dsa_indexer/csrc/cake_dsa_indexer_topk/cake_dsa_indexer_topk_device_common.cuh
@@ -16,7 +16,7 @@
// Generated by cake.codegen — do not edit.
// Shared device preamble of t... | 2 | 2 | 2 | [
"deepseek"
] | [
"SM100",
"SM103",
"SM107"
] | [] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/cake_dsa_indexer/csrc/cake_dsa_indexer_topk/cake_dsa_indexer_topk_device_common.cuh).
Goal: perf(cake_dsa_indexer): SM103a dispatch set for the wide, paired and split scan programs of the DSA indexer top-k (SM100a programs unchanged)
Target hardwa... | ## Summary
Re-export of the `cake_dsa_indexer` top-k programs (scan, merge, finalize and finalize-rank roles) from the producer tip that closes the current DeepSeek-V3.2 lightning-indexer round. On **SM103a** the scan programs of the wide, paired-l6 and split kinds take the dispatch set measured for them this round --... | [{"scope": "kernel", "hardware": "SM103a", "model": "DeepSeek-V3.2", "shape": null, "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 0.4359, "optimized": 0.4113, "stated_speedup": null, "speedup": 1.0598}, {"scope": "kernel", "hardware": "SM100a", "model": "DeepSeek-V3.2", "... | 1.0116 | null |
flashinfer | 23dc1d5957558a04d03d5bc0003a09c0035ed776 | 2026-10-11T14:37:02-07:00 | 6,335 | https://github.com/flashinfer-ai/flashinfer/pull/6335 | perf(cake_kimi_k3_fp8_projection): round 9 — cluster split-K re-association cells, K=128 / 192-wide GEMM cells, fused-shape re-tune, quant_done barrier (SM100a, SM103a) (#6335) | perf(cake_kimi_k3_fp8_projection): round 9 — cluster split-K re-association cells, K=128 / 192-wide GEMM cells, fused-shape re-tune, quant_done barrier (SM100a, SM103a) (#6335)
## Summary
Round 9 of the Cake `kimi_k3_fp8_projection` generated-program export
(FP8 block-scaled projection GEMMs of the Kimi-K3 KDA / MLA ... | flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh
+++ flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh
@@ -16,7 +16,7 @@
// Generated by cake.codegen — do not e... | 5 | 5 | 4 | [
"kimi"
] | [
"B200",
"GB300",
"SM100",
"SM103"
] | [
"24 ×",
"1.00×",
"1.00×",
"1.00×",
"1.10×",
"1.10×",
"1.10×"
] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh).
Goal: perf(cake_kimi_k3_fp8_projection): round 9 — cluster split-K re-association cells, K=128 / 192-wide GEMM cells, fused-shape re-tune, quan... | ## Summary
Round 9 of the Cake `kimi_k3_fp8_projection` generated-program export (FP8 block-scaled projection GEMMs of the Kimi-K3 KDA / MLA families — 22 families, 352 contract rows per GPU: 198 perf rows = 22 (N, K) families × M in {1, 8, 64, 256, 512, 1024, 2048, 4096, 16384} and 154 correctness rows at M 3 / 129 /... | [{"scope": "kernel", "hardware": "SM103", "model": null, "shape": "1,28,512", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 17.44, "optimized": 14.24, "stated_speedup": null, "speedup": 1.2247}, {"scope": "kernel", "hardware": "SM100", "model": null, "shape": "1,28,2048",... | 1.1125 | null |
flashinfer | adae6837f1962a5790162be0ee45e014659cbbf8 | 2026-10-11T14:28:04-07:00 | 6,318 | https://github.com/flashinfer-ai/flashinfer/pull/6318 | perf(cake_deepgemm): per-architecture 64-head FP8 dense texts, static-preferred windows and two new paged geometries (SM100a, SM103a) (#6318) | perf(cake_deepgemm): per-architecture 64-head FP8 dense texts, static-preferred windows and two new paged geometries (SM100a, SM103a) (#6318)
## Summary
Re-export of the `deepgemm_dense_mqa` family (dense 32-head and 64-head
FP8 / FP4 MQA logits, paged FP8 MQA logits) from the producer tip of the
convergence round ag... | csrc/experimental/deepgemm_dense_mqa/generated/cake_deepgemm_dense_mqa_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/lic... | --- csrc/experimental/deepgemm_dense_mqa/generated/cake_deepgemm_dense_mqa_device_common.cuh
+++ csrc/experimental/deepgemm_dense_mqa/generated/cake_deepgemm_dense_mqa_device_common.cuh
@@ -19,7 +19,7 @@
// Generated by cake.codegen — do not edit.
// Shared device preamble of the sm_100a, sm_103a generated kernels:... | 4 | 3 | 3 | [] | [
"SM100",
"SM103"
] | [
"64 x",
"64 x",
"32 x",
"64 x",
"64 x",
"256 x"
] | Optimize this cuda kernel file from flashinfer (csrc/experimental/deepgemm_dense_mqa/generated/cake_deepgemm_dense_mqa_device_common.cuh).
Goal: perf(cake_deepgemm): per-architecture 64-head FP8 dense texts, static-preferred windows and two new paged geometries (SM100a, SM103a)
Target hardware: SM100, SM103
Target mod... | ## Summary
Re-export of the `deepgemm_dense_mqa` family (dense 32-head and 64-head FP8 / FP4 MQA logits, paged FP8 MQA logits) from the producer tip of the convergence round against the stock DeepGEMM kernels (`fp8_mqa_logits` / `fp8_paged_mqa_logits`, sgl-deep-gemm 0.2.0). Catalog schema `dense_mqa.v7` -> `dense_mqa.... | [{"scope": "kernel", "hardware": "SM100a", "model": null, "shape": null, "batch_size": null, "metric": "paired CUPTI timing ratio", "unit": null, "higher_is_better": true, "baseline": 1.0, "optimized": 1.018, "stated_speedup": null, "speedup": 1.018}, {"scope": "kernel", "hardware": "SM103a", "model": null, "shape": nu... | 1.017 | null |
flashinfer | 36fd76859292ac2ac5aebd0892fc64715569b9da | 2026-10-11T14:18:41-07:00 | 6,330 | https://github.com/flashinfer-ai/flashinfer/pull/6330 | perf(cake_ssd_combined): exact-scan epilogue ring + calibrated schedule-variant rule (SM100 / SM103) (#6330) | perf(cake_ssd_combined): exact-scan epilogue ring + calibrated schedule-variant rule (SM100 / SM103) (#6330)
## Summary
Fifth performance round of the Cake Mamba2 SSD combined prefill
(`flashinfer.mamba.SSDCombined(backend="cake")` and its Cake-only
functional wrapper `flashinfer.mamba.ssd_combined_fwd`), SM100 (B200)... | csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_sequence.cpp | cpp | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
// Generated by cake.runtime.host_shim — do not edit.
// CAKE_SSD_TEMPLATE: one launcher for every exact-scan SSDCombined program
// (exact_*).
// The nine CAKE_SSD_* placeholders (program name, preprocess modu... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
// Generated by cake.runtime.host_shim — do not edit.
// CAKE_SSD_TEMPLATE: one launcher for every exact-scan SSDCombined program
// (exact_*).
// The nine CAKE_SSD_* placeholders (program name, preprocess modu... | --- csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_sequence.cpp
+++ csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_sequence.cpp
@@ -565,7 +565,7 @@
uint64_t global_dim[4] = {(uint64_t)(d1), (uint64_t)(d2), (uint64_t)(d3), (uint64_t)(d4)};
TVM_FFI_CHECK(global_dim[0] > 0 && global_d... | 1 | 1 | 2 | [
"mamba",
"nemotron"
] | [
"B200",
"CPU",
"GB200",
"GB300",
"SM100",
"SM103"
] | [
"2 x",
"4 x",
"63 x",
"65 x",
"2 x",
"2 x",
"3 x",
"1 x",
"1 x",
"8 x"
] | Optimize this cpp kernel file from flashinfer (csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_sequence.cpp).
Goal: perf(cake_ssd_combined): exact-scan epilogue ring + calibrated schedule-variant rule (SM100 / SM103)
Target hardware: B200, CPU, GB200, GB300, SM100, SM103
Target models: mamba, nemotron
... | ## Summary
Fifth performance round of the Cake Mamba2 SSD combined prefill (`flashinfer.mamba.SSDCombined(backend="cake")` and its Cake-only functional wrapper `flashinfer.mamba.ssd_combined_fwd`), SM100 (B200) and SM103 (GB300). Exact arithmetic is preserved: every kernel change is a schedule / data-movement / issue-o... | [{"scope": "e2e", "hardware": "GB200", "model": "Nemotron-H-8B-Reasoning-128K", "shape": "BF16 TP1", "batch_size": null, "metric": "accuracy", "unit": null, "higher_is_better": true, "baseline": 0.885, "optimized": 0.885, "stated_speedup": null, "speedup": 1.0}, {"scope": "e2e", "hardware": "GB200", "model": "Nemotron-... | 1.0444 | 1.0025 |
flashinfer | 1f28b952d8bd75e380e03d0c55e2c00055b527a5 | 2026-10-10T15:16:52-07:00 | 6,217 | https://github.com/flashinfer-ai/flashinfer/pull/6217 | perf(cake_kimi_k3_fp8_projection): round 8 — bit-exact dispatch-cell convergence, K=128 GEMM operand hand-off, cached launch receipts, short-row TMA-store fix (SM100a, SM103a) (#6217) | perf(cake_kimi_k3_fp8_projection): round 8 — bit-exact dispatch-cell convergence, K=128 GEMM operand hand-off, cached launch receipts, short-row TMA-store fix (SM100a, SM103a) (#6217)
## Summary
Round 8 of the Cake `kimi_k3_fp8_projection` generated-program export
(FP8 block-scaled projection GEMMs of the Kimi-K3 KDA... | flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh
+++ flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh
@@ -16,7 +16,7 @@
// Generated by cake.codegen — do not e... | 24 | 223 | 4 | [
"kimi"
] | [
"B200",
"GB300",
"SM100",
"SM103"
] | [
"2.21x",
"1.02x",
"1.00x",
"2.43x",
"1.05x",
"3.47x",
"1.02x",
"2.21x",
"1.04x",
"1.06x"
] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh).
Goal: perf(cake_kimi_k3_fp8_projection): round 8 — bit-exact dispatch-cell convergence, K=128 GEMM operand hand-off, cached launch receipts, sh... | ## Summary
Round 8 of the Cake `kimi_k3_fp8_projection` generated-program export (FP8 block-scaled projection GEMMs of the Kimi-K3 KDA / MLA families — 22 families: TP8 and TP1 of q_proj, fused_qkvg, in_proj_qkvgfab, f_a, f_b, b_proj (KDA) and kv_a, fused_qkv_a, q_b, kv_b, o_proj (MLA) — on SM100 + SM103). Output stay... | [{"scope": "kernel", "hardware": "GB300", "model": null, "shape": null, "batch_size": null, "metric": "geomean performance ratio", "unit": null, "higher_is_better": true, "baseline": 1.0164, "optimized": 1.0222, "stated_speedup": null, "speedup": 1.0057}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": ... | 1.0204 | 1.0504 |
flashinfer | 817555dd1f9203bf64f997bf024cd0219f063c6a | 2026-10-10T01:03:39-07:00 | 6,291 | https://github.com/flashinfer-ai/flashinfer/pull/6291 | perf(cake_ssd_combined): round-4 exact-scan schedule, chunk-parallel host model and graph-capturable prepared submission (SM100 / SM103) (#6291) | perf(cake_ssd_combined): round-4 exact-scan schedule, chunk-parallel host model and graph-capturable prepared submission (SM100 / SM103) (#6291)
## Summary
Fourth performance round of the Cake Mamba2 SSD combined prefill
(`flashinfer.mamba.SSDCombined(backend="cake")` and its Cake-only
functional wrapper `flashinfer.m... | csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_chunk_parallel_sequence.cpp | cpp | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
// Generated by cake.runtime.host_shim — do not edit.
// CAKE_SSD_TEMPLATE: one launcher for every chunk-parallel SSDCombined program
// (chunkpar_*): the exact-scan arithmetic in grid-barrier-separated phases.... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
// Generated by cake.runtime.host_shim — do not edit.
// CAKE_SSD_TEMPLATE: one launcher for every chunk-parallel SSDCombined program
// (chunkpar_*): the exact-scan arithmetic in grid-barrier-separated phases.... | --- csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_chunk_parallel_sequence.cpp
+++ csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_chunk_parallel_sequence.cpp
@@ -349,7 +349,7 @@
TVM_FFI_CHECK(global_dim[0] > 0 && global_dim[1] > 0 && global_dim[2] > 0 && global_dim[3] > 0, ValueError)... | 4 | 4 | 4 | [
"mamba",
"nemotron"
] | [
"B200",
"CPU",
"GB200",
"GB300",
"SM100",
"SM103"
] | [
"2 ×",
"1 x",
"32768 x",
"1 x",
"1 x",
"2048 x",
"4 x",
"2048 x",
"1.09x",
"1.06x"
] | Optimize this cpp kernel file from flashinfer (csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_chunk_parallel_sequence.cpp).
Goal: perf(cake_ssd_combined): round-4 exact-scan schedule, chunk-parallel host model and graph-capturable prepared submission (SM100 / SM103)
Target hardware: B200, CPU, GB200, G... |
## Summary
Fourth performance round of the Cake Mamba2 SSD combined prefill (`flashinfer.mamba.SSDCombined(backend="cake")` and its Cake-only functional wrapper `flashinfer.mamba.ssd_combined_fwd`), SM100 (B200) and SM103 (GB300). Exact arithmetic is preserved: every kernel change is a schedule / data-movement / issue... | [{"scope": "kernel", "hardware": "SM100", "model": null, "shape": "v1x128", "batch_size": null, "metric": "scan time", "unit": null, "higher_is_better": true, "baseline": 0.918, "optimized": null, "stated_speedup": 1.05, "speedup": 1.05}, {"scope": "kernel", "hardware": "SM100", "model": null, "shape": "v8x128", "batch... | 1.33 | 1.212 |
flashinfer | 817555dd1f9203bf64f997bf024cd0219f063c6a | 2026-10-10T01:03:39-07:00 | 6,291 | https://github.com/flashinfer-ai/flashinfer/pull/6291 | perf(cake_ssd_combined): round-4 exact-scan schedule, chunk-parallel host model and graph-capturable prepared submission (SM100 / SM103) (#6291) | perf(cake_ssd_combined): round-4 exact-scan schedule, chunk-parallel host model and graph-capturable prepared submission (SM100 / SM103) (#6291)
## Summary
Fourth performance round of the Cake Mamba2 SSD combined prefill
(`flashinfer.mamba.SSDCombined(backend="cake")` and its Cake-only
functional wrapper `flashinfer.m... | csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_sequence.cpp | cpp | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
// Generated by cake.runtime.host_shim — do not edit.
// CAKE_SSD_TEMPLATE: one launcher for every exact-scan SSDCombined program
// (exact_*).
// The nine CAKE_SSD_* placeholders (program name, preprocess modu... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
// Generated by cake.runtime.host_shim — do not edit.
// CAKE_SSD_TEMPLATE: one launcher for every exact-scan SSDCombined program
// (exact_*).
// The nine CAKE_SSD_* placeholders (program name, preprocess modu... | --- csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_sequence.cpp
+++ csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_sequence.cpp
@@ -346,7 +346,7 @@
TVM_FFI_CHECK(global_dim[0] > 0 && global_dim[1] > 0 && global_dim[2] > 0 && global_dim[3] > 0, ValueError)
<< "TMA descriptor for... | 4 | 4 | 4 | [
"mamba",
"nemotron"
] | [
"B200",
"CPU",
"GB200",
"GB300",
"SM100",
"SM103"
] | [
"2 ×",
"1 x",
"32768 x",
"1 x",
"1 x",
"2048 x",
"4 x",
"2048 x",
"1.09x",
"1.06x"
] | Optimize this cpp kernel file from flashinfer (csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_sequence.cpp).
Goal: perf(cake_ssd_combined): round-4 exact-scan schedule, chunk-parallel host model and graph-capturable prepared submission (SM100 / SM103)
Target hardware: B200, CPU, GB200, GB300, SM100, SM... |
## Summary
Fourth performance round of the Cake Mamba2 SSD combined prefill (`flashinfer.mamba.SSDCombined(backend="cake")` and its Cake-only functional wrapper `flashinfer.mamba.ssd_combined_fwd`), SM100 (B200) and SM103 (GB300). Exact arithmetic is preserved: every kernel change is a schedule / data-movement / issue... | [{"scope": "kernel", "hardware": "SM100", "model": null, "shape": "v1x128", "batch_size": null, "metric": "scan time", "unit": null, "higher_is_better": true, "baseline": 0.918, "optimized": null, "stated_speedup": 1.05, "speedup": 1.05}, {"scope": "kernel", "hardware": "SM100", "model": null, "shape": "v8x128", "batch... | 1.33 | 1.212 |
flashinfer | 817555dd1f9203bf64f997bf024cd0219f063c6a | 2026-10-10T01:03:39-07:00 | 6,291 | https://github.com/flashinfer-ai/flashinfer/pull/6291 | perf(cake_ssd_combined): round-4 exact-scan schedule, chunk-parallel host model and graph-capturable prepared submission (SM100 / SM103) (#6291) | perf(cake_ssd_combined): round-4 exact-scan schedule, chunk-parallel host model and graph-capturable prepared submission (SM100 / SM103) (#6291)
## Summary
Fourth performance round of the Cake Mamba2 SSD combined prefill
(`flashinfer.mamba.SSDCombined(backend="cake")` and its Cake-only
functional wrapper `flashinfer.m... | flashinfer/mamba/ssd_combined.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2025 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/mamba/ssd_combined.py
+++ flashinfer/mamba/ssd_combined.py
@@ -269,8 +269,10 @@
returns a token-major view of it; the Cake kernels write the token-major
``[batch, seqlen, nheads, headdim]`` buffer directly and return it. The
Cake backend also accepts any positive ``seqlen``, including few... | 75 | 4 | 4 | [
"mamba",
"nemotron"
] | [
"B200",
"CPU",
"GB200",
"GB300",
"SM100",
"SM103"
] | [
"2 ×",
"1 x",
"32768 x",
"1 x",
"1 x",
"2048 x",
"4 x",
"2048 x",
"1.09x",
"1.06x"
] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/mamba/ssd_combined.py).
Goal: perf(cake_ssd_combined): round-4 exact-scan schedule, chunk-parallel host model and graph-capturable prepared submission (SM100 / SM103)
Target hardware: B200, CPU, GB200, GB300, SM100, SM103
Target models: mamba, nemotron
Cu... |
## Summary
Fourth performance round of the Cake Mamba2 SSD combined prefill (`flashinfer.mamba.SSDCombined(backend="cake")` and its Cake-only functional wrapper `flashinfer.mamba.ssd_combined_fwd`), SM100 (B200) and SM103 (GB300). Exact arithmetic is preserved: every kernel change is a schedule / data-movement / issue... | [{"scope": "kernel", "hardware": "SM100", "model": null, "shape": "v1x128", "batch_size": null, "metric": "scan time", "unit": null, "higher_is_better": true, "baseline": 0.918, "optimized": null, "stated_speedup": 1.05, "speedup": 1.05}, {"scope": "kernel", "hardware": "SM100", "model": null, "shape": "v8x128", "batch... | 1.33 | 1.212 |
flashinfer | 0926b61815fac88384d8fafb18599a103600fec9 | 2026-10-09T22:57:39-07:00 | 6,195 | https://github.com/flashinfer-ai/flashinfer/pull/6195 | perf(cake_dsa_indexer): one lowering of the weighted ReLU sum in the DSA indexer top-k programs (SM100a, SM103a, SM107a) (#6195) | perf(cake_dsa_indexer): one lowering of the weighted ReLU sum in the DSA indexer top-k programs (SM100a, SM103a, SM107a) (#6195)
## Summary
Re-export of the `cake_dsa_indexer` top-k programs (the program set
delivered by #6230: scan, merge, finalize and finalize-rank roles) with
a single lowering of the per-row weigh... | flashinfer/experimental/cake_dsa_indexer/csrc/cake_dsa_indexer_topk/cake_dsa_indexer_topk_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- flashinfer/experimental/cake_dsa_indexer/csrc/cake_dsa_indexer_topk/cake_dsa_indexer_topk_device_common.cuh
+++ flashinfer/experimental/cake_dsa_indexer/csrc/cake_dsa_indexer_topk/cake_dsa_indexer_topk_device_common.cuh
@@ -50,8 +50,6 @@
#include "cake_device_helpers/cake_elect_sync_1ee8cd91025d8932.cuh"
#include... | 4 | 4 | 2 | [] | [
"SM100",
"SM103",
"SM107"
] | [
"0.65\nx"
] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/cake_dsa_indexer/csrc/cake_dsa_indexer_topk/cake_dsa_indexer_topk_device_common.cuh).
Goal: perf(cake_dsa_indexer): one lowering of the weighted ReLU sum in the DSA indexer top-k programs (SM100a, SM103a, SM107a)
Target hardware: SM100, SM103, SM1... | ## Summary
Re-export of the `cake_dsa_indexer` top-k programs (the program set delivered by #6230: scan, merge, finalize and finalize-rank roles) with a single lowering of the per-row weighted ReLU sum. The delivered scan programs form |a| in CUDA C (`make_float2(fabsf(a.x), fabsf(a.y))`) and then run the packed `add.... | [{"scope": "kernel", "hardware": "SM100a", "model": null, "shape": "dsa_RC3", "batch_size": null, "metric": "latency", "unit": "ms", "higher_is_better": false, "baseline": 26.9564, "optimized": 27.219, "stated_speedup": null, "speedup": 0.9904}, {"scope": "kernel", "hardware": "SM100a", "model": null, "shape": null, "b... | 1.0005 | null |
flashinfer | d217e8915e32949b49d93bbda467ffef0e8d1329 | 2026-10-08T14:25:38-07:00 | 6,206 | https://github.com/flashinfer-ai/flashinfer/pull/6206 | perf(cake_ssd_combined): preprocess, exact-scan and chunk-parallel prefill improvements (SM100 / SM103) (#6206) | perf(cake_ssd_combined): preprocess, exact-scan and chunk-parallel prefill improvements (SM100 / SM103) (#6206)
# FI PR draft (round 3) — title: `perf(cake_ssd_combined): preprocess,
exact-scan and chunk-parallel prefill improvements (SM100 / SM103)`
<!-- PUBLIC TEXT: no issue-tracker ids, no tracker links, no interna... | csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_sequence.cpp | cpp | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
// Generated by cake.runtime.host_shim — do not edit.
// CAKE_SSD_TEMPLATE: one launcher for every SSDCombined program. The nine
// CAKE_SSD_* placeholders (program name, preprocess module/kernel/threads,
// m... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
// Generated by cake.runtime.host_shim — do not edit.
// CAKE_SSD_TEMPLATE: one launcher for every exact-scan SSDCombined program
// (exact_*).
// The nine CAKE_SSD_* placeholders (program name, preprocess modu... | --- csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_sequence.cpp
+++ csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_sequence.cpp
@@ -3,8 +3,9 @@
* SPDX-License-Identifier: Apache-2.0
*/
// Generated by cake.runtime.host_shim — do not edit.
-// CAKE_SSD_TEMPLATE: one launcher for ever... | 5 | 4 | 2 | [
"deepseek",
"mamba",
"nemotron"
] | [
"B200",
"B300",
"CPU",
"GB200",
"GB300",
"HOPPER",
"SM100",
"SM103"
] | [
"2.42×",
"3.15×"
] | Optimize this cpp kernel file from flashinfer (csrc/cake_mamba_ssd_combined/generated/host/mamba_ssd_combined_sequence.cpp).
Goal: perf(cake_ssd_combined): preprocess, exact-scan and chunk-parallel prefill improvements (SM100 / SM103)
Target hardware: B200, B300, CPU, GB200, GB300, HOPPER, SM100, SM103
Target models: ... | # FI PR draft (round 3) — title: `perf(cake_ssd_combined): preprocess, exact-scan and chunk-parallel prefill improvements (SM100 / SM103)`
<!-- PUBLIC TEXT: no issue-tracker ids, no tracker links, no internal cluster/lease names, no dev-log text. grep before posting. -->
## Summary
Third performance round of the Cake ... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "single-chunk", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 19, "optimized": 4, "stated_speedup": null, "speedup": 4.75}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "single-chunk", "ba... | 4.875 | 2.7875 |
flashinfer | 99828461c2ee49b9e242a6ad4b0a6e9f0f576a78 | 2026-10-07T20:34:03-07:00 | 6,215 | https://github.com/flashinfer-ai/flashinfer/pull/6215 | perf(cake_dsv4): dequantize the NVFP4 decode cache with the hardware QMUL4 via PTX ISA 9.4; require CUDA 13.4 (SM100/SM103) (#6215) | perf(cake_dsv4): dequantize the NVFP4 decode cache with the hardware QMUL4 via PTX ISA 9.4; require CUDA 13.4 (SM100/SM103) (#6215)
## Summary
Stacked on #6190 (merge that first; this PR's own change is its top
commit). Same SM100 / SM103 DeepSeek-V4
NVFP4 sparse-MLA decode kernels and the same host path as #6190; on... | csrc/cake_dsv4/common/cake_dsv4_nvfp4_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_dsv4/common/cake_dsv4_nvfp4_device_common.cuh
+++ csrc/cake_dsv4/common/cake_dsv4_nvfp4_device_common.cuh
@@ -372,56 +372,18 @@
: "r"(tmem_addr));
}
-// Portable (public-PTX) QMUL4 for the DSv4 NVFP4 cache: E2M1 x E4M3 -> E4M3 with one rounding.
-// Per 16-value block the eight possible magnit... | 13 | 51 | 8 | [
"deepseek"
] | [
"B200",
"BLACKWELL",
"GB300",
"SM100",
"SM103",
"SM120"
] | [] | Optimize this cuda kernel file from flashinfer (csrc/cake_dsv4/common/cake_dsv4_nvfp4_device_common.cuh).
Goal: perf(cake_dsv4): dequantize the NVFP4 decode cache with the hardware QMUL4 via PTX ISA 9.4; require CUDA 13.4 (SM100/SM103)
Target hardware: B200, BLACKWELL, GB300, SM100, SM103, SM120
Target models: deepsee... | ## Summary
Stacked on #6190 (merge that first; this PR's own change is its top commit). Same SM100 / SM103 DeepSeek-V4
NVFP4 sparse-MLA decode kernels and the same host path as #6190; one generated helper changes (the shared device header's QMUL4
helper, `cake_dsv4_qmul4_portable` -> `cake_dsv4_qmul4`, so the six NVFP... | [{"scope": "kernel", "hardware": "B200", "model": "DeepSeek-V3", "shape": null, "batch_size": null, "metric": "source/export geomean", "unit": null, "higher_is_better": true, "baseline": 0.952, "optimized": 0.999, "stated_speedup": null, "speedup": 1.0494}, {"scope": "kernel", "hardware": "GB300", "model": "DeepSeek-V3... | 1.0086 | null |
flashinfer | 5dc3cd06c57465c48f6c6f7317f642b6eb683083 | 2026-10-06T17:37:40-07:00 | 6,109 | https://github.com/flashinfer-ai/flashinfer/pull/6109 | perf(cake_kimi_k3_latent_moe): plan from the device SM count; qualify 148- and 152-SM parts (SM100a, SM103a) (#6109) | perf(cake_kimi_k3_latent_moe): plan from the device SM count; qualify 148- and 152-SM parts (SM100a, SM103a) (#6109)
## Summary
The Kimi-K3 LatentMoE front / tail backend
(`flashinfer.experimental.kimi_k3_latent_moe`) planned every route for a
fixed 148-SM device and refused other parts. It now derives every plan
fro... | flashinfer/experimental/kimi_k3_latent_moe/csrc/cake_kimi_k3_latent_moe/cake_kimi_k3_latent_moe_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- flashinfer/experimental/kimi_k3_latent_moe/csrc/cake_kimi_k3_latent_moe/cake_kimi_k3_latent_moe_device_common.cuh
+++ flashinfer/experimental/kimi_k3_latent_moe/csrc/cake_kimi_k3_latent_moe/cake_kimi_k3_latent_moe_device_common.cuh
@@ -73,12 +73,6 @@
:: "r"(mbar_addr), "r"(count) : "memory");
}
-__devic... | 42 | 42 | 3 | [
"kimi"
] | [
"B200",
"B300",
"CPU",
"GB200",
"GB300",
"SM100",
"SM103"
] | [] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/kimi_k3_latent_moe/csrc/cake_kimi_k3_latent_moe/cake_kimi_k3_latent_moe_device_common.cuh).
Goal: perf(cake_kimi_k3_latent_moe): plan from the device SM count; qualify 148- and 152-SM parts (SM100a, SM103a)
Target hardware: B200, B300, CPU, GB200,... | ## Summary
The Kimi-K3 LatentMoE front / tail backend (`flashinfer.experimental.kimi_k3_latent_moe`) planned every route for a
fixed 148-SM device and refused other parts. It now derives every plan from the device's `multi_processor_count`
and admits a device when its SM count is in the qualified set `{148, 152}` and ... | [] | null | null |
flashinfer | 8565c8358e7bc3048c7411f566173a562f15d2a0 | 2026-10-06T15:13:24-07:00 | 6,129 | https://github.com/flashinfer-ai/flashinfer/pull/6129 | perf(cake_deepgemm_mega_gate): 16-way split-K cluster reduction with a compensated token-parallel combine on the small-M routing-gate routes (SM100a, SM103a) (#6129) | perf(cake_deepgemm_mega_gate): 16-way split-K cluster reduction with a compensated token-parallel combine on the small-M routing-gate routes (SM100a, SM103a) (#6129)
## Summary
Regenerates the fused routing-gate family
`flashinfer.experimental.deepgemm_mega_gate` (public API
`flashinfer.mega_gate.prepare_mega_gate`)
... | csrc/experimental/deepgemm_mega_gate/generated/cake_deepgemm_mega_gate_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- csrc/experimental/deepgemm_mega_gate/generated/cake_deepgemm_mega_gate_device_common.cuh
+++ csrc/experimental/deepgemm_mega_gate/generated/cake_deepgemm_mega_gate_device_common.cuh
@@ -19,7 +19,7 @@
// Generated by cake.codegen — do not edit.
// Shared device preamble of the sm_100a, sm_103a generated kernels:... | 48 | 48 | 2 | [] | [
"B200",
"GB300",
"SM100",
"SM103"
] | [
"1.05x",
"0.9957x",
"1.0000x",
"1.0037x",
"1.0032x",
"1.0083x",
"1.0001x",
"1.0019x",
"0.9987x",
"0.9975x"
] | Optimize this cuda kernel file from flashinfer (csrc/experimental/deepgemm_mega_gate/generated/cake_deepgemm_mega_gate_device_common.cuh).
Goal: perf(cake_deepgemm_mega_gate): 16-way split-K cluster reduction with a compensated token-parallel combine on the small-M routing-gate routes (SM100a, SM103a)
Target hardware:... | ## Summary
Regenerates the fused routing-gate family `flashinfer.experimental.deepgemm_mega_gate` (public API `flashinfer.mega_gate.prepare_mega_gate`)
for SM100a (B200) and SM103a (GB300) at FlashInfer `d4a3ad6c1`. Two scheduling changes on the single-tile small-M routes, everything
else keeps its program:
- The M =... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "K=5120,E=384,top-6,sqrtsoftplus,FP32 bias", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 8.896, "optimized": 7.36, "stated_speedup": null, "speedup": 1.2087}, {"scope": "kernel", "hardware": "B200", "model": ... | 1.1274 | null |
flashinfer | 26fe42d91acc1d56bd27560f64e9bf727d623cca | 2026-10-06T15:07:53-07:00 | 6,146 | https://github.com/flashinfer-ai/flashinfer/pull/6146 | perf(cake_fp8_projection): Kimi-K3 KDA/MLA projection GEMM round 7 (FP8 token ring on the M=256 cluster split-K cell, parallel-issue DSM partial exchange), shared-source export (SM100a, SM103a) (#6146) | perf(cake_fp8_projection): Kimi-K3 KDA/MLA projection GEMM round 7 (FP8 token ring on the M=256 cluster split-K cell, parallel-issue DSM partial exchange), shared-source export (SM100a, SM103a) (#6146)
Developed by the **CAKE team**, the kernels in this PR **outperform**
the relevant **SOTA baselines at the time of me... | flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh
+++ flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh
@@ -16,7 +16,7 @@
// Generated by cake.codegen — do not e... | 101 | 101 | 4 | [
"kimi"
] | [
"B200",
"B300",
"GB300",
"SM100",
"SM103"
] | [
"1.022x",
"1.014x",
"2.04x",
"2.03x"
] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh).
Goal: perf(cake_fp8_projection): Kimi-K3 KDA/MLA projection GEMM round 7 (FP8 token ring on the M=256 cluster split-K cell, parallel-issue DSM ... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise (see Baselines).
## Summary
Round 7 of the experimental generated-program backend for the serialized `FP8_PB_WO` ... | [{"scope": "e2e", "hardware": "B200", "model": "Kimi-K3-NVFP4", "shape": null, "batch_size": null, "metric": "performance ratio", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.022, "speedup": 1.022}, {"scope": "e2e", "hardware": "GB300", "model": "Kimi-K3-NVFP4", "shap... | null | 2.022 |
flashinfer | a9d3d64fee145fa2be06e08063de7d6ca1c45095 | 2026-10-06T14:04:10-07:00 | 6,128 | https://github.com/flashinfer-ai/flashinfer/pull/6128 | perf(cake_moe_finalize_allreduce_fusion): poll the owner segment at world size 8 too (#6128) | perf(cake_moe_finalize_allreduce_fusion): poll the owner segment at world size 8 too (#6128)
## Summary
Second performance round for `cake_moe_finalize_allreduce_fusion`
(indexed MoE finalize + Lamport all-reduce +
residual/RMSNorm + optional NVFP4 epilogue, SM100/SM103), on top of
#6057. No API, workspace-ABI, bindi... | csrc/cake_moe_finalize_allreduce_fusion/cake_moe_finalize_kernels.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
typedef signed char int8_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
#if defined(__CUDACC_RTC__)
typedef unsigned long long uint64_t;... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
typedef signed char int8_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
#if defined(__CUDACC_RTC__)
typedef unsigned long long uint64_t;... | --- csrc/cake_moe_finalize_allreduce_fusion/cake_moe_finalize_kernels.cu
+++ csrc/cake_moe_finalize_allreduce_fusion/cake_moe_finalize_kernels.cu
@@ -43,6 +43,10 @@
#define SMEM_RMS_SLOTS_STRIDE 32
#define SMEM_TOTAL 256
#define THREADS 224
+
+template <typename F, size_t... _i> __device__ __forceinline__ void poll_... | 12 | 23 | 1 | [] | [
"B200",
"B300",
"SM100",
"SM103"
] | [
"2048 ×",
"8 ×",
"8 ×"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_moe_finalize_allreduce_fusion/cake_moe_finalize_kernels.cu).
Goal: perf(cake_moe_finalize_allreduce_fusion): poll the owner segment at world size 8 too
Target hardware: B200, B300, SM100, SM103
Target models: unspecified
Current file:
```cuda
/*
* Copyright (... | ## Summary
Second performance round for `cake_moe_finalize_allreduce_fusion` (indexed MoE finalize + Lamport all-reduce +
residual/RMSNorm + optional NVFP4 epilogue, SM100/SM103), on top of #6057. No API, workspace-ABI, binding-table or
numerics change: the same twelve kernels, the same workspace layout, and every out... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "tokens=1", "batch_size": 1, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.097, "speedup": 1.097}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "tokens=2", "batch_s... | 1.2068 | null |
flashinfer | e835a9742ce4c999b211211cd9c70c75d32b2df2 | 2026-10-06T02:43:25-07:00 | 6,105 | https://github.com/flashinfer-ai/flashinfer/pull/6105 | perf(cake_sampling): round 10 -- CTA-local select twins, integer-tested whole-CTA tail, R200 one-wave re-pick (SM90, SM100a, SM103a, SM107a) (#6105) | perf(cake_sampling): round 10 -- CTA-local select twins, integer-tested whole-CTA tail, R200 one-wave re-pick (SM90, SM100a, SM103a, SM107a) (#6105)
## cake_sampling round 10 -- exact levers to the hardware floor
Follow-up of #5439, #5553, #5664, #5771, #5873, #5950, #6065 (rounds
3-9). Round 10 keeps the correctness... | csrc/cake_sampling/cake_sampling_binding.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_sampling/cake_sampling_binding.cuh
+++ csrc/cake_sampling/cake_sampling_binding.cuh
@@ -89,6 +89,10 @@
// the default / sample builds of a multi-CTA stream)
constexpr int64_t kFlagCoarsePush = 256; // host-side build selection (pushed-coarse-sums form of
... | 78 | 22 | 5 | [] | [
"B200",
"GB300",
"H100",
"SM100",
"SM103",
"SM107",
"SM120",
"SM90"
] | [
"1000 x",
"4.74x",
"11.04x",
"18.74x",
"3.84x",
"5.66x",
"7.81x",
"4.78x",
"10.78x",
"16.89x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_sampling/cake_sampling_binding.cuh).
Goal: perf(cake_sampling): round 10 -- CTA-local select twins, integer-tested whole-CTA tail, R200 one-wave re-pick (SM90, SM100a, SM103a, SM107a)
Target hardware: B200, GB300, H100, SM100, SM103, SM107, SM120, SM90
Target m... | ## cake_sampling round 10 -- exact levers to the hardware floor
Follow-up of #5439, #5553, #5664, #5771, #5873, #5950, #6065 (rounds 3-9). Round 10 keeps the correctness contract
unchanged (exact top-k set and tie rule, eps-exact top-p cut, deterministic sampling per (input, seed, offset), fp32 keys,
no reduced-precis... | [{"scope": "kernel", "hardware": "gb300", "model": null, "shape": "k=10", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 4.74, "speedup": 4.74}, {"scope": "kernel", "hardware": "gb300", "model": null, "shape": "k=10", "batch_size":... | 5.33 | null |
flashinfer | e835a9742ce4c999b211211cd9c70c75d32b2df2 | 2026-10-06T02:43:25-07:00 | 6,105 | https://github.com/flashinfer-ai/flashinfer/pull/6105 | perf(cake_sampling): round 10 -- CTA-local select twins, integer-tested whole-CTA tail, R200 one-wave re-pick (SM90, SM100a, SM103a, SM107a) (#6105) | perf(cake_sampling): round 10 -- CTA-local select twins, integer-tested whole-CTA tail, R200 one-wave re-pick (SM90, SM100a, SM103a, SM107a) (#6105)
## cake_sampling round 10 -- exact levers to the hardware floor
Follow-up of #5439, #5553, #5664, #5771, #5873, #5950, #6065 (rounds
3-9). Round 10 keeps the correctness... | csrc/cake_sampling/generated/cake_sampling_kernels.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_sampling/generated/cake_sampling_kernels.cu
+++ csrc/cake_sampling/generated/cake_sampling_kernels.cu
@@ -32,3 +32,6 @@
#include "cake_sampling_kernels_part8.cuh"
#include "cake_sampling_kernels_part9.cuh"
#include "cake_sampling_kernels_part10.cuh"
+#include "cake_sampling_kernels_part11.cuh"
+#includ... | 3 | 0 | 5 | [] | [
"B200",
"GB300",
"H100",
"SM100",
"SM103",
"SM107",
"SM120",
"SM90"
] | [
"1000 x",
"4.74x",
"11.04x",
"18.74x",
"3.84x",
"5.66x",
"7.81x",
"4.78x",
"10.78x",
"16.89x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_sampling/generated/cake_sampling_kernels.cu).
Goal: perf(cake_sampling): round 10 -- CTA-local select twins, integer-tested whole-CTA tail, R200 one-wave re-pick (SM90, SM100a, SM103a, SM107a)
Target hardware: B200, GB300, H100, SM100, SM103, SM107, SM120, SM90... | ## cake_sampling round 10 -- exact levers to the hardware floor
Follow-up of #5439, #5553, #5664, #5771, #5873, #5950, #6065 (rounds 3-9). Round 10 keeps the correctness contract
unchanged (exact top-k set and tie rule, eps-exact top-p cut, deterministic sampling per (input, seed, offset), fp32 keys,
no reduced-precis... | [{"scope": "kernel", "hardware": "gb300", "model": null, "shape": "k=10", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 4.74, "speedup": 4.74}, {"scope": "kernel", "hardware": "gb300", "model": null, "shape": "k=10", "batch_size":... | 5.33 | null |
flashinfer | 67b54628b821a65f67f8fa16685852e48ba32913 | 2026-10-06T01:09:09-07:00 | 5,672 | https://github.com/flashinfer-ai/flashinfer/pull/5672 | perf(cake_fp8_projection): Kimi-K3 KDA/MLA projection GEMM round 6 (L2 prefetch, weight multicast, TMA-store epilogue, cluster split-K, 192-wide / stream-K GEMM, PDL), shared-source export (SM100a, SM103a) (#5672) | perf(cake_fp8_projection): Kimi-K3 KDA/MLA projection GEMM round 6 (L2 prefetch, weight multicast, TMA-store epilogue, cluster split-K, 192-wide / stream-K GEMM, PDL), shared-source export (SM100a, SM103a) (#5672)
Developed by the **CAKE team**, the kernels in this PR **outperform**
the relevant **SOTA baselines at th... | flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... | --- flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh
+++ flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh
@@ -16,7 +16,8 @@
// Generated by cake.codegen — do not e... | 106 | 95 | 4 | [
"kimi"
] | [
"B200",
"B300",
"GB300",
"SM100",
"SM103"
] | [
"2.040x",
"1.030x",
"2.026x",
"1.040x"
] | Optimize this cuda kernel file from flashinfer (flashinfer/experimental/kimi_k3_fp8_projection/csrc/cake_kimi_k3_fp8_projection/cake_kimi_k3_fp8_projection_device_common.cuh).
Goal: perf(cake_fp8_projection): Kimi-K3 KDA/MLA projection GEMM round 6 (L2 prefetch, weight multicast, TMA-store epilogue, cluster split-K, 1... | Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## Summary
Round 6 of the experimental generated-program backend for the serialized `FP8_PB_WO` KDA / MLA projec... | [{"scope": "e2e", "hardware": "B200", "model": "Kimi-K3-NVFP4", "shape": null, "batch_size": null, "metric": "performance", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 2.04, "speedup": 2.04}, {"scope": "e2e", "hardware": "B300", "model": "Kimi-K3-NVFP4", "shape": null,... | null | 2.033 |
flashinfer | 55edb4288eb5c82fbfb5f110d1329bd75d0b9849 | 2026-10-05T22:46:26-07:00 | 6,057 | https://github.com/flashinfer-ai/flashinfer/pull/6057 | perf(cake_moe_finalize_allreduce_fusion): route-pair prefetch, DSM slot-ring RMSNorm reduction, occupancy-sized grid (#6057) | perf(cake_moe_finalize_allreduce_fusion): route-pair prefetch, DSM slot-ring RMSNorm reduction, occupancy-sized grid (#6057)
## Summary
Performance round for `cake_moe_finalize_allreduce_fusion` (indexed MoE
finalize + Lamport all-reduce + residual/RMSNorm +
optional NVFP4 epilogue, SM100/SM103). No API, workspace-AB... | csrc/cake_moe_finalize_allreduce_fusion/cake_moe_finalize_allreduce_fusion_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
// Host launcher for the Cake MoE finalize + all-reduce fusion kernels in
// sm_100a/*_device.cu. One module per architecture links the twelve generated
// kernels (dtype x world size x optional NVFP4 epilogue... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
// Host launcher for the Cake MoE finalize + all-reduce fusion kernels in
// sm_100a/*_device.cu. One module per architecture links the twelve generated
// kernels (dtype x world size x optional NVFP4 epilogue... | --- csrc/cake_moe_finalize_allreduce_fusion/cake_moe_finalize_allreduce_fusion_binding.cu
+++ csrc/cake_moe_finalize_allreduce_fusion/cake_moe_finalize_allreduce_fusion_binding.cu
@@ -13,6 +13,9 @@
#include <algorithm>
#include <cstdint>
+#include <map>
+#include <mutex>
+#include <utility>
#include "tvm_ffi_uti... | 33 | 4 | 2 | [] | [
"B200",
"B300",
"SM100",
"SM103"
] | [
"2048 ×",
"8 ×"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_moe_finalize_allreduce_fusion/cake_moe_finalize_allreduce_fusion_binding.cu).
Goal: perf(cake_moe_finalize_allreduce_fusion): route-pair prefetch, DSM slot-ring RMSNorm reduction, occupancy-sized grid
Target hardware: B200, B300, SM100, SM103
Target models: uns... | ## Summary
Performance round for `cake_moe_finalize_allreduce_fusion` (indexed MoE finalize + Lamport all-reduce + residual/RMSNorm +
optional NVFP4 epilogue, SM100/SM103). No API, workspace-ABI, binding-table or numerics change: every output stays
bit-identical to the current kernel on the full test matrix (fp16/bf16... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "TP2", "batch_size": 128, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.673, "speedup": 1.673}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "TP4", "batch_size": 12... | 1.27 | null |
flashinfer | 55edb4288eb5c82fbfb5f110d1329bd75d0b9849 | 2026-10-05T22:46:26-07:00 | 6,057 | https://github.com/flashinfer-ai/flashinfer/pull/6057 | perf(cake_moe_finalize_allreduce_fusion): route-pair prefetch, DSM slot-ring RMSNorm reduction, occupancy-sized grid (#6057) | perf(cake_moe_finalize_allreduce_fusion): route-pair prefetch, DSM slot-ring RMSNorm reduction, occupancy-sized grid (#6057)
## Summary
Performance round for `cake_moe_finalize_allreduce_fusion` (indexed MoE
finalize + Lamport all-reduce + residual/RMSNorm +
optional NVFP4 epilogue, SM100/SM103). No API, workspace-AB... | csrc/cake_moe_finalize_allreduce_fusion/cake_moe_finalize_kernels.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
typedef signed char int8_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
#if defined(__CUDACC_RTC__)
typedef unsigned long long uint64_t;... | /*
* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
typedef signed char int8_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
#if defined(__CUDACC_RTC__)
typedef unsigned long long uint64_t;... | --- csrc/cake_moe_finalize_allreduce_fusion/cake_moe_finalize_kernels.cu
+++ csrc/cake_moe_finalize_allreduce_fusion/cake_moe_finalize_kernels.cu
@@ -38,6 +38,9 @@
#define SMEM_RMS_SCALAR_OFF 132
#define SMEM_RMS_SCALAR_STAGE_BYTES 4
#define SMEM_RMS_SCALAR_STRIDE 4
+#define SMEM_RMS_SLOTS_OFF 136
+#define SMEM_RMS_... | 271 | 169 | 2 | [] | [
"B200",
"B300",
"SM100",
"SM103"
] | [
"2048 ×",
"8 ×"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_moe_finalize_allreduce_fusion/cake_moe_finalize_kernels.cu).
Goal: perf(cake_moe_finalize_allreduce_fusion): route-pair prefetch, DSM slot-ring RMSNorm reduction, occupancy-sized grid
Target hardware: B200, B300, SM100, SM103
Target models: unspecified
Current... | ## Summary
Performance round for `cake_moe_finalize_allreduce_fusion` (indexed MoE finalize + Lamport all-reduce + residual/RMSNorm +
optional NVFP4 epilogue, SM100/SM103). No API, workspace-ABI, binding-table or numerics change: every output stays
bit-identical to the current kernel on the full test matrix (fp16/bf16... | [{"scope": "kernel", "hardware": "B200", "model": null, "shape": "TP2", "batch_size": 128, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.673, "speedup": 1.673}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": "TP4", "batch_size": 12... | 1.27 | null |
flashinfer | 557721463e31a7e3cff42491b09b3b75f6ca9b92 | 2026-10-05T22:22:16-07:00 | 5,902 | https://github.com/flashinfer-ai/flashinfer/pull/5902 | perf(kda): one-wave dispatch and single-pass RMSNorm for multi-token KDA decode on SM10x (#5902) | perf(kda): one-wave dispatch and single-pass RMSNorm for multi-token KDA decode on SM10x (#5902)
## Description
Avoid wave quantization in fused multi-token KDA decode and repeated
RMSNorm
reduction work on tiles that preserve its float32 addition grouping.
### Dispatch rule
Select `(R, KQ, bpm, NCH, SPLIT) = (2, 1... | flashinfer/kda_kernels/fused_kda_decode_multitoken.py | cute_dsl | Apache-2.0 | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | """
Copyright (c) 2026 by FlashInfer team.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, s... | --- flashinfer/kda_kernels/fused_kda_decode_multitoken.py
+++ flashinfer/kda_kernels/fused_kda_decode_multitoken.py
@@ -75,17 +75,18 @@
return (value + alignment - 1) // alignment * alignment
-def _required_smem_bytes(T, R, KQ, NCH, SPLIT=1):
+def _required_smem_bytes(T, R, KQ, NCH, SPLIT=1, norm_order=1):
... | 82 | 27 | 1 | [] | [
"B200",
"B300",
"CPU",
"GB300",
"SM107"
] | [] | Optimize this cute_dsl kernel file from flashinfer (flashinfer/kda_kernels/fused_kda_decode_multitoken.py).
Goal: perf(kda): one-wave dispatch and single-pass RMSNorm for multi-token KDA decode on SM10x
Target hardware: B200, B300, CPU, GB300, SM107
Target models: unspecified
Current file:
```python
"""
Copyright (c)... | ## Description
Avoid wave quantization in fused multi-token KDA decode and repeated RMSNorm
reduction work on tiles that preserve its float32 addition grouping.
### Dispatch rule
Select `(R, KQ, bpm, NCH, SPLIT) = (2, 16, 2, 2, 1)` by default on
B200, B300, GB300, and SM107 for T in {5, 8} when the unsplit sequence-... | [{"scope": "kernel", "hardware": "SM107", "model": null, "shape": "96,5,3", "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 21.31, "optimized": 18.05, "stated_speedup": null, "speedup": 1.1806}, {"scope": "kernel", "hardware": "SM107", "model": null, "shape": "96,5,4", "bat... | 1.0281 | null |
flashinfer | 9c6797eda4d208b4b56dcb30383b8772b112240b | 2026-10-05T12:47:43-07:00 | 6,065 | https://github.com/flashinfer-ai/flashinfer/pull/6065 | perf(cake_sampling): round 9 -- leader-push exchange twins of the multi-CTA streams, graph-replay host fix (#6065) | perf(cake_sampling): round 9 -- leader-push exchange twins of the multi-CTA streams, graph-replay host fix (#6065)
> Developed by the **CAKE team**, the kernels in this PR **outperform**
the relevant **SOTA baselines at the time of merge** on the **vast
majority of performance benchmark shapes**, matching them otherwi... | csrc/cake_sampling/cake_sampling_binding.cuh | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_sampling/cake_sampling_binding.cuh
+++ csrc/cake_sampling/cake_sampling_binding.cuh
@@ -28,7 +28,7 @@
// (the slab row) CAKE_SAMPLING_STAGE1_TABLE(X) X(symbol, cluster, ept, stream, threads,
// smem_bytes, fused_tail,
// fused_block_tail, coarse_sample, spec_samp... | 27 | 8 | 5 | [
"qwen"
] | [
"B200",
"GB300",
"H100",
"SM100",
"SM103",
"SM107",
"SM120",
"SM90"
] | [
"8 x",
"3.1x",
"9.7x",
"3.9x",
"8.4x",
"3.2x",
"9.6x",
"3.8x",
"7.8x",
"2.9x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_sampling/cake_sampling_binding.cuh).
Goal: perf(cake_sampling): round 9 -- leader-push exchange twins of the multi-CTA streams, graph-replay host fix
Target hardware: B200, GB300, H100, SM100, SM103, SM107, SM120, SM90
Target models: qwen
Current file:
```cuda... | > Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## Cake radix sampling, round 9: leader-push exchange twins of the multi-CTA streams, graph-replay host fix
Fo... | [{"scope": "kernel", "hardware": "R200", "model": null, "shape": "ept=32, two-to-five-chunk rows", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.01, "speedup": 1.01}, {"scope": "kernel", "hardware": "B200", "model": null, "shape... | 1.0667 | null |
flashinfer | 9c6797eda4d208b4b56dcb30383b8772b112240b | 2026-10-05T12:47:43-07:00 | 6,065 | https://github.com/flashinfer-ai/flashinfer/pull/6065 | perf(cake_sampling): round 9 -- leader-push exchange twins of the multi-CTA streams, graph-replay host fix (#6065) | perf(cake_sampling): round 9 -- leader-push exchange twins of the multi-CTA streams, graph-replay host fix (#6065)
> Developed by the **CAKE team**, the kernels in this PR **outperform**
the relevant **SOTA baselines at the time of merge** on the **vast
majority of performance benchmark shapes**, matching them otherwi... | csrc/cake_sampling/generated/cake_sampling_kernels.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2026 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_sampling/generated/cake_sampling_kernels.cu
+++ csrc/cake_sampling/generated/cake_sampling_kernels.cu
@@ -30,3 +30,5 @@
#include "cake_sampling_kernels_part6.cuh"
#include "cake_sampling_kernels_part7.cuh"
#include "cake_sampling_kernels_part8.cuh"
+#include "cake_sampling_kernels_part9.cuh"
+#include ... | 2 | 0 | 5 | [
"qwen"
] | [
"B200",
"GB300",
"H100",
"SM100",
"SM103",
"SM107",
"SM120",
"SM90"
] | [
"8 x",
"3.1x",
"9.7x",
"3.9x",
"8.4x",
"3.2x",
"9.6x",
"3.8x",
"7.8x",
"2.9x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_sampling/generated/cake_sampling_kernels.cu).
Goal: perf(cake_sampling): round 9 -- leader-push exchange twins of the multi-CTA streams, graph-replay host fix
Target hardware: B200, GB300, H100, SM100, SM103, SM107, SM120, SM90
Target models: qwen
Current file... | > Developed by the **CAKE team**, the kernels in this PR **outperform** the relevant **SOTA baselines at the time of merge** on the **vast majority of performance benchmark shapes**, matching them otherwise.
## Cake radix sampling, round 9: leader-push exchange twins of the multi-CTA streams, graph-replay host fix
Fo... | [{"scope": "kernel", "hardware": "R200", "model": null, "shape": "ept=32, two-to-five-chunk rows", "batch_size": null, "metric": "speedup", "unit": null, "higher_is_better": true, "baseline": null, "optimized": null, "stated_speedup": 1.01, "speedup": 1.01}, {"scope": "kernel", "hardware": "B200", "model": null, "shape... | 1.0667 | null |
flashinfer | a1b9e13a4aa0093b0585a65d4808f6469b390555 | 2026-10-05T21:10:40+03:00 | 5,267 | https://github.com/flashinfer-ai/flashinfer/pull/5267 | perf(mamba): enable native SM107 stochastic rounding (#5267) | perf(mamba): enable native SM107 stochastic rounding (#5267)
<!-- .github/pull_request_template.md -->
## 📌 Description
Enable native stochastic rounding on Rubin (SM107a) for Mamba state
updates. The existing architecture guard omitted SM107a, causing Rubin
to use software conversion. This PR adds `__CUDA_ARCH_FEA... | include/flashinfer/mamba/conversion.cuh | cuda | Apache-2.0 | #pragma once
#include <cuda.h>
#include <cuda_fp16.h>
#include <cuda_fp8.h>
#ifdef FLASHINFER_ENABLE_BF16
#include <cuda_bf16.h>
#endif
namespace flashinfer::mamba::conversion {
inline __device__ float toFloat(float f) { return f; }
inline __device__ float toFloat(__half h) { return __half2float(h); }
#ifdef FLASHI... | #pragma once
#include <cuda.h>
#include <cuda_fp16.h>
#include <cuda_fp8.h>
#ifdef FLASHINFER_ENABLE_BF16
#include <cuda_bf16.h>
#endif
namespace flashinfer::mamba::conversion {
inline __device__ float toFloat(float f) { return f; }
inline __device__ float toFloat(__half h) { return __half2float(h); }
#ifdef FLASHI... | --- include/flashinfer/mamba/conversion.cuh
+++ include/flashinfer/mamba/conversion.cuh
@@ -158,10 +158,10 @@
}
// Hardware `cvt.rs.*` (stochastic-rounding convert) is available ONLY on the
-// datacenter Blackwell "a" targets that actually carry the `.rs` PTX feature:
-// sm_100a (B200) and sm_103a (B300). There ... | 6 | 6 | 2 | [
"mamba",
"nemotron"
] | [
"SM100",
"SM103",
"SM107"
] | [
"1.413×",
"1.547×",
"1.573×"
] | Optimize this cuda kernel file from flashinfer (include/flashinfer/mamba/conversion.cuh).
Goal: perf(mamba): enable native SM107 stochastic rounding
Target hardware: SM100, SM103, SM107
Target models: mamba, nemotron
Current file:
```cuda
#pragma once
#include <cuda.h>
#include <cuda_fp16.h>
#include <cuda_fp8.h>
#if... | <!-- .github/pull_request_template.md -->
## 📌 Description
Enable native stochastic rounding on Rubin (SM107a) for Mamba state updates. The existing architecture guard omitted SM107a, causing Rubin to use software conversion. This PR adds `__CUDA_ARCH_FEAT_SM107_ALL` to `FLASHINFER_MAMBA_HAS_CVT_RS`, adds compute ca... | [{"scope": "kernel", "hardware": null, "model": "Nemotron 3 Ultra TP1", "shape": "heads=256,head_dim=64,state_dim=128,groups=8,T=1", "batch_size": 1, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 10.848, "optimized": 7.648, "stated_speedup": 1.413, "speedup": 1.4184}, {"scope": "kernel", "ha... | 1.5473 | null |
flashinfer | 911cb09d0981c38d15b775b7820e4a76c72fcfa0 | 2026-10-04T10:47:29-07:00 | 6,045 | https://github.com/flashinfer-ai/flashinfer/pull/6045 | perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative) (#6045) | perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative) (#6045)
## Summary
Rounds 7-17 of the DSv4 sparse-MLA Cake backend (`backend="cake"`, SM100
+ SM103) as one cumulative change on the #5920 layout (per-variant
bindings taking their checks from `tvm_ffi_ut... | csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_binding.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_binding.cu
+++ csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_binding.cu
@@ -15,35 +15,43 @@
*/
// Generated by the Cake source exporter — do not edit.
-// tvm-ffi direct-source launcher for Cake kernel 'kernel_cake_dsv4_697c8662eb01c8d6bd5... | 29 | 21 | 7 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103",
"SM120"
] | [
"4 x",
"0.9578x",
"0.9820x",
"6 x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_binding.cu).
Goal: perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative)
Target hardware: B200, CPU, GB300, SM100, SM103, SM120
Target models: deepseek
... | ## Summary
Rounds 7-17 of the DSv4 sparse-MLA Cake backend (`backend="cake"`, SM100 + SM103) as one cumulative change on the #5920 layout (per-variant bindings taking their checks from `tvm_ffi_utils.h`, shared sources under `common/`, `run_sequence`, the host's direct variant launches). Main carries round 6 (#5700) f... | [{"scope": "kernel", "hardware": "GB300", "model": null, "shape": null, "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 6.53, "optimized": 6.88, "stated_speedup": null, "speedup": 0.9491}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": null, "batch_size": n... | 1.022 | null |
flashinfer | 911cb09d0981c38d15b775b7820e4a76c72fcfa0 | 2026-10-04T10:47:29-07:00 | 6,045 | https://github.com/flashinfer-ai/flashinfer/pull/6045 | perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative) (#6045) | perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative) (#6045)
## Summary
Rounds 7-17 of the DSv4 sparse-MLA Cake backend (`backend="cake"`, SM100
+ SM103) as one cumulative change on the #5920 layout (per-variant
bindings taking their checks from `tvm_ffi_ut... | csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_kernel.cu | cuda | Apache-2.0 | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | /*
* Copyright (c) 2023 by FlashInfer team.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or ... | --- csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_kernel.cu
+++ csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_kernel.cu
@@ -26,12 +26,9 @@
static_assert(sizeof(uint64_t) == 8, "Cake requires an LP64 CUDA host ABI");
typedef signed int int32_t;
typedef short int int16_t;
-st... | 9 | 21 | 7 | [
"deepseek"
] | [
"B200",
"CPU",
"GB300",
"SM100",
"SM103",
"SM120"
] | [
"4 x",
"0.9578x",
"0.9820x",
"6 x"
] | Optimize this cuda kernel file from flashinfer (csrc/cake_dsv4/common/cake_dsv4_bf16_h64_compressed_reduce_kernel.cu).
Goal: perf(cake_sparse_mla): rounds 7-17 DSv4 sparse-MLA Cake programs for SM100/SM103 on the #5920 layout (cumulative)
Target hardware: B200, CPU, GB300, SM100, SM103, SM120
Target models: deepseek
... | ## Summary
Rounds 7-17 of the DSv4 sparse-MLA Cake backend (`backend="cake"`, SM100 + SM103) as one cumulative change on the #5920 layout (per-variant bindings taking their checks from `tvm_ffi_utils.h`, shared sources under `common/`, `run_sequence`, the host's direct variant launches). Main carries round 6 (#5700) f... | [{"scope": "kernel", "hardware": "GB300", "model": null, "shape": null, "batch_size": null, "metric": "latency", "unit": "us", "higher_is_better": false, "baseline": 6.53, "optimized": 6.88, "stated_speedup": null, "speedup": 0.9491}, {"scope": "kernel", "hardware": "B200", "model": null, "shape": null, "batch_size": n... | 1.022 | null |
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