repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -328,6 +352,16 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
rewriter.replaceOpWithNewOp<LLVM::ShuffleVectorOp>(op, dstType, shfl01,
shfl23, attr);
} break;
+ case 8: {
+ unsigned num = 8;
+ Value undef ... | Can we come up with a lowering that works for all number of inputs? I don't think this is scalable at all. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -339,33 +373,166 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
/// %extract = ttgi.extract %a[0] : tensor<8xf16> -> tensor<4xf16>
/// is converted to
/// %extract = llvm.shufflevector %a, %a : [0, 1, 2, 3] : vector<4xf16>
-class ExtractOpConversion : public ConvertTritonGPUOpToLLVMP... | As it is in theory possible, I'd return failure here instead of asserting out. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -339,33 +373,166 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
/// %extract = ttgi.extract %a[0] : tensor<8xf16> -> tensor<4xf16>
/// is converted to
/// %extract = llvm.shufflevector %a, %a : [0, 1, 2, 3] : vector<4xf16>
-class ExtractOpConversion : public ConvertTritonGPUOpToLLVMP... | This case should not be upstream as tensors cannot be directly converted to LLVM dialect. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -339,33 +373,166 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
/// %extract = ttgi.extract %a[0] : tensor<8xf16> -> tensor<4xf16>
/// is converted to
/// %extract = llvm.shufflevector %a, %a : [0, 1, 2, 3] : vector<4xf16>
-class ExtractOpConversion : public ConvertTritonGPUOpToLLVMP... | Isn't `dstAttrType` the same type as `vecType`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -339,33 +373,166 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
/// %extract = ttgi.extract %a[0] : tensor<8xf16> -> tensor<4xf16>
/// is converted to
/// %extract = llvm.shufflevector %a, %a : [0, 1, 2, 3] : vector<4xf16>
-class ExtractOpConversion : public ConvertTritonGPUOpToLLVMP... | ```suggestion
auto poison = rewriter.create<LLVM::PoisonOp>(loc, vecTy);
auto splat = rewriter.create<LLVM::InsertElementOp>(
loc, vecTy, poison, adaptor.getSrc(),
rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI32Type(), 0));
auto convertedTy = typeConverter->convertType(resultType... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -339,33 +373,166 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
/// %extract = ttgi.extract %a[0] : tensor<8xf16> -> tensor<4xf16>
/// is converted to
/// %extract = llvm.shufflevector %a, %a : [0, 1, 2, 3] : vector<4xf16>
-class ExtractOpConversion : public ConvertTritonGPUOpToLLVMP... | Will we always get `adaptor.getSrc().getType() == op.getType()`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -339,33 +373,166 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
/// %extract = ttgi.extract %a[0] : tensor<8xf16> -> tensor<4xf16>
/// is converted to
/// %extract = llvm.shufflevector %a, %a : [0, 1, 2, 3] : vector<4xf16>
-class ExtractOpConversion : public ConvertTritonGPUOpToLLVMP... | Can we just add the rest of the cases here now? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -339,33 +373,166 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
/// %extract = ttgi.extract %a[0] : tensor<8xf16> -> tensor<4xf16>
/// is converted to
/// %extract = llvm.shufflevector %a, %a : [0, 1, 2, 3] : vector<4xf16>
-class ExtractOpConversion : public ConvertTritonGPUOpToLLVMP... | Is this reduction pattern correct? Wouldn't we end up having each subgroup reduce a slice, but not the whole tensor? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -339,33 +373,166 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
/// %extract = ttgi.extract %a[0] : tensor<8xf16> -> tensor<4xf16>
/// is converted to
/// %extract = llvm.shufflevector %a, %a : [0, 1, 2, 3] : vector<4xf16>
-class ExtractOpConversion : public ConvertTritonGPUOpToLLVMP... | I'm not sure this and `tt.expand_dims` patterns are correct. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -380,6 +547,29 @@ class AddPtrOpConversion : public ConvertTritonGPUOpToLLVMPattern<AddPtrOp> {
}
};
+class ArithDivFOpLowering
+ : public ConvertTritonGPUOpToLLVMPattern<mlir::arith::DivFOp> {
+ using ConvertTritonGPUOpToLLVMPattern<
+ mlir::arith::DivFOp>::ConvertTritonGPUOpToLLVMPattern;
+ Logical... | Why do we need this? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -28,8 +28,13 @@ TritonIntelGPUToLLVMTypeConverter::TritonIntelGPUToLLVMTypeConverter(
// tensor type is flattened and divided by 16 (subgroupSize).
addConversion([&](mlir::RankedTensorType type) -> mlir::Type {
- return mlir::VectorType::get(type.getNumElements() / 16,
- ... | Dot operand encoding should go here too? |
intel-xpu-backend-for-triton | github_2023 | python | 1,574 | intel | etiotto | @@ -87,6 +87,45 @@ def make_ttgir(mod, metadata, opt):
pm.run(mod)
return mod
+ @staticmethod
+ def make_llir(mod, metadata, opt): | Can we use the default pass pipeline "make_llir" code ? We are producing TritonGPU IR and the existing "make_llir" should work fine.
What is the reason it does not ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -339,33 +370,169 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
/// %extract = ttgi.extract %a[0] : tensor<8xf16> -> tensor<4xf16>
/// is converted to
/// %extract = llvm.shufflevector %a, %a : [0, 1, 2, 3] : vector<4xf16>
-class ExtractOpConversion : public ConvertTritonGPUOpToLLVMP... | I'm surprised we need `VectorType` here as upstream already supports this.
|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -58,6 +60,44 @@ namespace {
/// Import the GPU Ops to TritonGEN Patterns.
#include "GPUToTritonGEN.cpp.inc"
+struct GPUSubgroupReduceOpLowering
+ : public ConvertOpToLLVMPattern<mlir::gpu::SubgroupReduceOp> {
+ using ConvertOpToLLVMPattern<
+ mlir::gpu::SubgroupReduceOp>::ConvertOpToLLVMPattern;
+
+ Lo... | Should we use threads per warp instead? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -36,6 +36,8 @@
#include "mlir/Transforms/DialectConversion.h"
#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
#include "llvm/Support/FormatVariadic.h"
+#include <cstdint>
+#include <optional> | Are they really needed? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -0,0 +1,75 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+namespace {
+// FIXME: remove this when upstream ConstantOpLowering has such lowering
+class ArithConstantOpLowering
+ : public ConvertTriton... | ```suggestion
// arith.constant should only have vector or tensor types.
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -0,0 +1,75 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+namespace {
+// FIXME: remove this when upstream ConstantOpLowering has such lowering
+class ArithConstantOpLowering
+ : public ConvertTriton... | please remove commented code. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -0,0 +1,75 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+namespace {
+// FIXME: remove this when upstream ConstantOpLowering has such lowering | Should we attempt to upstream ourselves? |
intel-xpu-backend-for-triton | github_2023 | python | 1,574 | intel | whitneywhtsang | @@ -222,7 +222,8 @@ def make_ttgir(mod, metadata, opt, properties):
return mod
@staticmethod
- def make_llir(src, metadata, options):
+ def make_llir(src, metadata, options, properties): | Why passing `properties` if it is not used? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -92,8 +92,13 @@ struct ConvertTritonGPUToLLVM
int numCTAs = triton::gpu::TritonGPUDialect::getNumCTAs(mod);
int threadsPerWarp = triton::gpu::TritonGPUDialect::getThreadsPerWarp(mod);
- // Allocate shared memory and set barrier
- if (!pipelineManager.skipSharedMemoryAllocation()) {
+ // FIXME: s... | should we change compiler.py to `metadata["shared"] = src.get_int_attr("triton_gpu.shared")` to check if `src.get_int_attr("triton_gpu.shared")` is none, if so `metadata["shared"] = 0` instead? |
intel-xpu-backend-for-triton | github_2023 | others | 1,574 | intel | whitneywhtsang | @@ -1,5 +1,4 @@
// RUN: triton-opt %s -split-input-file --convert-triton-intel-gpu-to-llvm | FileCheck %s --check-prefixes=CHECK,CHECK-SCALAR
-// RUN: env TRITON_INTEL_ADVANCED_PATH=1 triton-opt %s -split-input-file --convert-triton-intel-gpu-to-llvm | FileCheck %s --check-prefixes=CHECK,CHECK-VECTOR | Why is this removed? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -0,0 +1,72 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+namespace {
+// FIXME: remove this when upstream ConstantOpLowering has such lowering
+class ArithConstantOpLowering
+ : public ConvertTriton... | I'd say we don't need this as IGC should be handling it. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -0,0 +1,77 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+/// Custom lowering for converting arith ops to LLVMIR dialect.
+/// These ops lowering ONLY works for Advanced Path.
+/// This is a temporary s... | ```suggestion
/// proper lowering strategy for these ops.
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -0,0 +1,77 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+/// Custom lowering for converting arith ops to LLVMIR dialect.
+/// These ops lowering ONLY works for Advanced Path.
+/// This is a temporary s... | can we rely on upstream lowering for vector type? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -0,0 +1,85 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+/// Custom lowering for converting arith ops to LLVMIR dialect.
+/// These ops lowering ONLY works for the advanced path.
+/// This is a tempora... | Can we have a test case to prevent regression of this lowering?
There are no failures from removing this pattern. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -170,16 +174,19 @@ class LoadStorePrefetchOpConversion
return truncatedShape;
};
- Value surfaceW = calculateSurface(ptrOp.getShape()[1], true);
- Value surfaceH = calculateSurface(ptrOp.getShape()[0], false);
- Value surfaceP = calculateSurface(ptrOp.getStrides()[0], true);
+ Value surface... | [optional]
```suggestion
Value surfaceW = calculateSurface(
ptrOp.getShape()[!transpose], true);
Value surfaceH = calculateSurface(
ptrOp.getShape()[transpose], false);
Value surfaceP = calculateSurface(
ptrOp.getStrides()[transpose], true);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -189,6 +196,17 @@ class LoadStorePrefetchOpConversion
getVectorType(cast<RankedTensorType>(op.getResult().getType()),
isDword ? i32_ty : i16_ty);
bool vnni = (idx == 1) && dataSize < 32;
+
+ // FIXME: only support fp16/bf16 for now, add more support like tf32, fp8 | Can we return failure for unsupported types? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -198,7 +216,12 @@ class LoadStorePrefetchOpConversion
return failure();
}
rewriter.replaceOp(op, bitcast(load, resType));
- } else if constexpr (std::is_same_v<OpType, PrefetchOp>) {
+ } else if constexpr (std::is_same_v<OpType, ttgi::PrefetchOp>) {
+ if (ptrOp.getOrder()[0] == 0) {... | remove? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -328,9 +352,17 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
rewriter.replaceOpWithNewOp<LLVM::ShuffleVectorOp>(op, dstType, shfl01,
shfl23, attr);
} break;
- default:
- llvm_unreachable("add more support for... | ```suggestion
for (auto i = 0; i < num; ++i) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -339,33 +370,142 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
/// %extract = ttgi.extract %a[0] : tensor<8xf16> -> tensor<4xf16>
/// is converted to
/// %extract = llvm.shufflevector %a, %a : [0, 1, 2, 3] : vector<4xf16>
-class ExtractOpConversion : public ConvertTritonGPUOpToLLVMP... | `triton_intel_gpu.min_sg_size` means the minimum subgroup size of the platform, `triton_gpu.threads-per-warp` means the actual subgroup size used.
We should use `triton_gpu.threads-per-warp` in this case. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -339,33 +370,142 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
/// %extract = ttgi.extract %a[0] : tensor<8xf16> -> tensor<4xf16>
/// is converted to
/// %extract = llvm.shufflevector %a, %a : [0, 1, 2, 3] : vector<4xf16>
-class ExtractOpConversion : public ConvertTritonGPUOpToLLVMP... | ```suggestion
llvm_unreachable("Unhandled reduction kind");
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,574 | intel | victor-eds | @@ -145,3 +145,104 @@ module attributes {"triton_intel_gpu.support_sg_2d_block", "triton_intel_gpu.sup
tt.return
}
}
+
+// -----
+
+// COM: Checks the correct lowering of sub-group reductions.
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [16, 64], threadsPerWarp = [1, 1], order = [1, 0]}>
+module attribu... | ```suggestion
```
Not needed |
intel-xpu-backend-for-triton | github_2023 | others | 1,574 | intel | victor-eds | @@ -145,3 +145,104 @@ module attributes {"triton_intel_gpu.support_sg_2d_block", "triton_intel_gpu.sup
tt.return
}
}
+
+// -----
+
+// COM: Checks the correct lowering of sub-group reductions.
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [16, 64], threadsPerWarp = [1, 1], order = [1, 0]}>
+module attribu... | ```suggestion
```
Not needed |
intel-xpu-backend-for-triton | github_2023 | others | 1,574 | intel | victor-eds | @@ -145,3 +145,104 @@ module attributes {"triton_intel_gpu.support_sg_2d_block", "triton_intel_gpu.sup
tt.return
}
}
+
+// -----
+
+// COM: Checks the correct lowering of sub-group reductions.
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [16, 64], threadsPerWarp = [1, 1], order = [1, 0]}>
+module attribu... | ```suggestion
// COM: Checks the correct lowering of triton ops, including broadcast, splat, expand_dims, addptr.
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -0,0 +1,85 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+/// Custom lowering for converting arith ops to LLVMIR dialect.
+/// These ops lowering ONLY works for the advanced path.
+/// This is a tempora... | ```suggestion
auto dstElementsAttr = dyn_cast<DenseElementsAttr>(op.getValue());
if (!dstElementsAttr || !dstElementsAttr.isSplat())
return failure();
```
This will only work if the constant is a splat, e.g., it won't work for:
```
%0 = arith.constant dense[0, 1, 2, 3, ...] : tensor<128xi32>
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,574 | intel | victor-eds | @@ -145,3 +145,104 @@ module attributes {"triton_intel_gpu.support_sg_2d_block", "triton_intel_gpu.sup
tt.return
}
}
+
+// -----
+
+// COM: Checks the correct lowering of sub-group reductions.
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [16, 64], threadsPerWarp = [1, 1], order = [1, 0]}>
+module attribu... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,574 | intel | victor-eds | @@ -145,3 +145,104 @@ module attributes {"triton_intel_gpu.support_sg_2d_block", "triton_intel_gpu.sup
tt.return
}
}
+
+// -----
+
+// COM: Checks the correct lowering of sub-group reductions.
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [16, 64], threadsPerWarp = [1, 1], order = [1, 0]}>
+module attribu... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -122,8 +126,8 @@ class LoadStorePrefetchOpConversion
ConversionPatternRewriter &rewriter) const override {
auto ptrType = cast<PointerType>(op.getPtr().getType());
auto tensorType = cast<RankedTensorType>(ptrType.getPointeeType());
- assert(tensorType.getRank() <= 2 &&
- "on... | Should we return `failure()` instead of asserting here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -189,6 +194,19 @@ class LoadStorePrefetchOpConversion
getVectorType(cast<RankedTensorType>(op.getResult().getType()),
isDword ? i32_ty : i16_ty);
bool vnni = (idx == 1) && dataSize < 32;
+
+ // FIXME: only support fp16/bf16 transpose for now, add more support like
+ ... | Can we return `failure()` here instead? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | victor-eds | @@ -339,33 +368,141 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
/// %extract = ttgi.extract %a[0] : tensor<8xf16> -> tensor<4xf16>
/// is converted to
/// %extract = llvm.shufflevector %a, %a : [0, 1, 2, 3] : vector<4xf16>
-class ExtractOpConversion : public ConvertTritonGPUOpToLLVMP... | Can we return failure? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -170,16 +175,16 @@ class LoadStorePrefetchOpConversion
return truncatedShape;
};
- Value surfaceW = calculateSurface(ptrOp.getShape()[1], true);
- Value surfaceH = calculateSurface(ptrOp.getShape()[0], false);
- Value surfaceP = calculateSurface(ptrOp.getStrides()[0], true);
+ Value surface... | is it intentional to change from getStrides to getShape? |
intel-xpu-backend-for-triton | github_2023 | python | 1,574 | intel | FMarno | @@ -258,7 +258,7 @@ def make_llir(src, metadata, options):
intel.post_process_llir(llvm_mod)
# Get some metadata
- metadata["shared"] = src.get_int_attr("triton_gpu.shared")
+ metadata["shared"] = src.get_int_attr("triton_gpu.shared") if src.get_int_attr("triton_gpu.shared") else 0 | ```suggestion
metadata["shared"] = src.get_int_attr("triton_gpu.shared") or 0
```
I'm not a python expert but I think this works. https://realpython.com/python-or-operator/#using-or-with-common-objects |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | etiotto | @@ -0,0 +1,85 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+/// Custom lowering for converting arith ops to LLVMIR dialect.
+/// These ops lowering ONLY works for the advanced path.
+/// This is a tempora... | This check can be removed if the code at line 24 is modified to:
```
auto srcType = dyn_cast<RankedTensorType>(op.getType());
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | etiotto | @@ -7,10 +7,12 @@
#include "triton/Analysis/Utility.h"
#include "triton/Dialect/Triton/IR/Dialect.h"
#include "triton/Dialect/Triton/IR/Types.h"
+#include "triton/Dialect/TritonGPU/Transforms/Utility.h"
+#include "llvm/ADT/ArrayRef.h"
using namespace mlir;
-using namespace mlir::triton;
-using namespace mlir::tri... | why this change ? I think using the namespace as it was before was fine. We can revert this change and reduce the footprint of this PR. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | etiotto | @@ -28,8 +28,14 @@ TritonIntelGPUToLLVMTypeConverter::TritonIntelGPUToLLVMTypeConverter(
// tensor type is flattened and divided by 16 (subgroupSize).
addConversion([&](mlir::RankedTensorType type) -> mlir::Type {
- return mlir::VectorType::get(type.getNumElements() / 16,
- ... | why is this change required ? In particular if `num == 1` can't we return a vector (of one element) to avoid diverging from other cases ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | etiotto | @@ -385,14 +521,20 @@ class AddPtrOpConversion : public ConvertTritonGPUOpToLLVMPattern<AddPtrOp> {
void mlir::triton::intel::populateTritonOpsToLLVMPatterns(
TritonIntelGPUToLLVMTypeConverter &typeConverter,
RewritePatternSet &patterns, PatternBenefit benefit) {
- patterns.add<MakeTensorPtrOpConversion>(ty... | kudos for using alphabetical order here ! |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | etiotto | @@ -0,0 +1,85 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+/// Custom lowering for converting arith ops to LLVMIR dialect.
+/// These ops lowering ONLY works for the advanced path.
+/// This is a tempora... | The cast is unsafe, should modify the check at line 33 to check for this., |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | etiotto | @@ -0,0 +1,85 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+/// Custom lowering for converting arith ops to LLVMIR dialect.
+/// These ops lowering ONLY works for the advanced path.
+/// This is a tempora... | Can use `replaceOpWithNewOp` here. |
intel-xpu-backend-for-triton | github_2023 | others | 1,574 | intel | etiotto | @@ -145,3 +145,100 @@ module attributes {"triton_intel_gpu.support_sg_2d_block", "triton_intel_gpu.sup
tt.return
}
}
+
+// -----
+
+// COM: Checks the correct lowering of sub-group reductions.
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [16, 64], threadsPerWarp = [1, 1], order = [1, 0]}>
+module attribu... | [nit]: The indentation of the CHECKS is not consistent with the style used by the test cases already in this file. |
intel-xpu-backend-for-triton | github_2023 | others | 1,574 | intel | etiotto | @@ -145,3 +145,100 @@ module attributes {"triton_intel_gpu.support_sg_2d_block", "triton_intel_gpu.sup
tt.return
}
}
+
+// -----
+
+// COM: Checks the correct lowering of sub-group reductions.
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [16, 64], threadsPerWarp = [1, 1], order = [1, 0]}>
+module attribu... | These should be CHECK-DAG |
intel-xpu-backend-for-triton | github_2023 | others | 1,574 | intel | etiotto | @@ -145,3 +145,100 @@ module attributes {"triton_intel_gpu.support_sg_2d_block", "triton_intel_gpu.sup
tt.return
}
}
+
+// -----
+
+// COM: Checks the correct lowering of sub-group reductions.
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [16, 64], threadsPerWarp = [1, 1], order = [1, 0]}>
+module attribu... | Existing tests use a different style to match, example:
```
// CHECK: [[VAL_1:%.*]] = llvm.mlir.constant(0 : i32) : i32
```
Let's be consistent. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -0,0 +1,79 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+/// Custom lowering for converting arith ops to LLVMIR dialect.
+/// These ops lowering ONLY works... | ```suggestion
if (!dyn_cast_or_null<VectorType>(dstType))
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | whitneywhtsang | @@ -0,0 +1,79 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
+#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
+#include "mlir/IR/BuiltinTypes.h"
+
+using namespace mlir;
+
+/// Custom lowering for converting arith ops to LLVMIR dialect.
+/// These ops lowering ONLY works... | ```suggestion
if (!dyn_cast_or_null<VectorType>(dstType))
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | etiotto | @@ -328,9 +346,17 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
rewriter.replaceOpWithNewOp<LLVM::ShuffleVectorOp>(op, dstType, shfl01,
shfl23, attr);
} break;
- default:
- llvm_unreachable("add more support for... | Drop the semicolon here. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | etiotto | @@ -346,16 +372,120 @@ class ExtractOpConversion : public ConvertTritonGPUOpToLLVMPattern<ExtractOp> {
LogicalResult
matchAndRewrite(ExtractOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
+ Location loc = op.getLoc();
Value base = adaptor.getBase();
- ... | Use the `extract_element` macro |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | etiotto | @@ -189,6 +192,19 @@ class LoadStorePrefetchOpConversion
getVectorType(cast<RankedTensorType>(op.getResult().getType()),
isDword ? i32_ty : i16_ty);
bool vnni = (idx == 1) && dataSize < 32;
+
+ // FIXME: only support fp16/bf16 transpose for now, add more support like
+ ... | use the `lshr` macro |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | etiotto | @@ -328,9 +346,17 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
rewriter.replaceOpWithNewOp<LLVM::ShuffleVectorOp>(op, dstType, shfl01,
shfl23, attr);
} break;
- default:
- llvm_unreachable("add more support for... | use the `insert_element` macro |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | etiotto | @@ -328,9 +346,17 @@ class GlueOpConversion : public ConvertTritonGPUOpToLLVMPattern<GlueOp> {
rewriter.replaceOpWithNewOp<LLVM::ShuffleVectorOp>(op, dstType, shfl01,
shfl23, attr);
} break;
- default:
- llvm_unreachable("add more support for... | auto -> int |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,574 | intel | etiotto | @@ -346,16 +372,120 @@ class ExtractOpConversion : public ConvertTritonGPUOpToLLVMPattern<ExtractOp> {
LogicalResult
matchAndRewrite(ExtractOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
+ Location loc = op.getLoc();
Value base = adaptor.getBase();
- ... | Use:
```
int subgroupSize = triton::gpu::TritonGPUDialect::getThreadsPerWarp(mod); |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -0,0 +1,18 @@
+#ifndef TRITON_INTEL_ANALYSIS_UTILITY_H
+#define TRITON_INTEL_ANALYSIS_UTILITY_H
+
+#include "triton/Analysis/Utility.h"
+
+namespace mlir {
+namespace triton {
+namespace gpu {
+namespace intel { | [Suggestion]: use `namespace mlir::triton::gpu::intel` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -0,0 +1,32 @@
+#include "triton/Analysis/Utility.h"
+#include "intel/include/Analysis/Utility.h"
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
+
+namespace mlir {
+namespace triton {
+namespace gpu {
+namespace intel { | use `namespace mlir::triton::gpu::intel` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -0,0 +1,18 @@
+#ifndef TRITON_INTEL_ANALYSIS_UTILITY_H
+#define TRITON_INTEL_ANALYSIS_UTILITY_H
+
+#include "triton/Analysis/Utility.h"
+
+namespace mlir {
+namespace triton {
+namespace gpu {
+namespace intel {
+
+bool isDpasToDotShortcut(RankedTensorType srcTy, RankedTensorType dstTy); | Document what srcTy and dstTy are in this context (srcTy is the output type of a tt.dot operation and dstTy is the input type of one of the operand of another tt.dot operation) |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -0,0 +1,32 @@
+#include "triton/Analysis/Utility.h"
+#include "intel/include/Analysis/Utility.h"
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
+
+namespace mlir {
+namespace triton {
+namespace gpu {
+namespace intel {
+
+bool isDpasToDotShortcut(RankedTensorType srcTy, RankedTensorType dstTy) {
+ a... | Can we avoid hard coding the magic numbers (16,8,2) ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -455,6 +459,122 @@ struct ConvertLayoutOpConversion
return success();
}
+ using ValueTable = std::map<std::pair<unsigned, unsigned>, Value>;
+
+ ValueTable getValuesFromDpasLayoutStruct(Location loc,
+ ConversionPatternRewriter &rewriter,
+ ... | [nit]: use the same order you used in the then branch |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -455,6 +459,122 @@ struct ConvertLayoutOpConversion
return success();
}
+ using ValueTable = std::map<std::pair<unsigned, unsigned>, Value>;
+
+ ValueTable getValuesFromDpasLayoutStruct(Location loc,
+ ConversionPatternRewriter &rewriter,
+ ... | auto -> Location |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -455,6 +459,122 @@ struct ConvertLayoutOpConversion
return success();
}
+ using ValueTable = std::map<std::pair<unsigned, unsigned>, Value>;
+
+ ValueTable getValuesFromDpasLayoutStruct(Location loc,
+ ConversionPatternRewriter &rewriter,
+ ... | auto -> Type |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -455,6 +459,122 @@ struct ConvertLayoutOpConversion
return success();
}
+ using ValueTable = std::map<std::pair<unsigned, unsigned>, Value>;
+
+ ValueTable getValuesFromDpasLayoutStruct(Location loc,
+ ConversionPatternRewriter &rewriter,
+ ... | Early exit: `if (!intel:: ....) return failure();` |
intel-xpu-backend-for-triton | github_2023 | others | 1,729 | intel | etiotto | @@ -0,0 +1,1223 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s
+
+#mma = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA = [32, 1], repCluster = [1, 2], A = [8, ... | mma -> dpas |
intel-xpu-backend-for-triton | github_2023 | others | 1,729 | intel | etiotto | @@ -0,0 +1,1223 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s
+
+#mma = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA = [32, 1], repCluster = [1, 2], A = [8, ... | remove attributes noinline |
intel-xpu-backend-for-triton | github_2023 | others | 1,729 | intel | etiotto | @@ -0,0 +1,1223 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s
+
+#mma = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA = [32, 1], repCluster = [1, 2], A = [8, ... | hmmm. this is very verbose. Can we use CHECK-COUNT here ? |
intel-xpu-backend-for-triton | github_2023 | others | 1,729 | intel | etiotto | @@ -0,0 +1,1223 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s
+
+#mma = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA = [32, 1], repCluster = [1, 2], A = [8, ... | use CHECK-COUNT ? |
intel-xpu-backend-for-triton | github_2023 | others | 1,729 | intel | etiotto | @@ -0,0 +1,1223 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s
+
+#mma = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA = [32, 1], repCluster = [1, 2], A = [8, ... | mma -> dpas |
intel-xpu-backend-for-triton | github_2023 | others | 1,729 | intel | etiotto | @@ -0,0 +1,1223 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s
+
+#mma = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA = [32, 1], repCluster = [1, 2], A = [8, ... | use CHECK-COUNT ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -0,0 +1,27 @@
+#include "triton/Analysis/Utility.h"
+#include "intel/include/Analysis/Utility.h"
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
+
+namespace mlir::triton::gpu::intel {
+
+bool isDpasToDotShortcut(RankedTensorType dpasTy, RankedTensorType dotTy) {
+ auto dpasLayout = dyn_cast<DpasEncod... | no auto pls |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -457,6 +461,118 @@ struct ConvertLayoutOpConversion
return success();
}
+ using ValueTable = std::map<std::pair<unsigned, unsigned>, Value>;
+
+ ValueTable getValuesFromDpasLayoutStruct(Location loc,
+ ConversionPatternRewriter &rewriter,
+ ... | size_t -> unsigned. auto is ok here because the RHS type is clear already |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -457,6 +461,118 @@ struct ConvertLayoutOpConversion
return success();
}
+ using ValueTable = std::map<std::pair<unsigned, unsigned>, Value>;
+
+ ValueTable getValuesFromDpasLayoutStruct(Location loc,
+ ConversionPatternRewriter &rewriter,
+ ... | no auto |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -457,6 +461,118 @@ struct ConvertLayoutOpConversion
return success();
}
+ using ValueTable = std::map<std::pair<unsigned, unsigned>, Value>;
+
+ ValueTable getValuesFromDpasLayoutStruct(Location loc,
+ ConversionPatternRewriter &rewriter,
+ ... | unsigned ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,729 | intel | etiotto | @@ -457,6 +461,118 @@ struct ConvertLayoutOpConversion
return success();
}
+ using ValueTable = std::map<std::pair<unsigned, unsigned>, Value>;
+
+ ValueTable getValuesFromDpasLayoutStruct(Location loc,
+ ConversionPatternRewriter &rewriter,
+ ... | Can we use SmallVector ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,737 | intel | Dewei-Wang-sh | @@ -412,11 +413,17 @@ class ScfPattern : public OpRewritePattern<scf::ForOp> {
if (llvm::any_of(arg.getUsers(), [](Operation *user) {
return !isa<ttgi::ExtractOp>(user);
- })) {
+ }))
return false;
- }
}
+ // Bail out if any user of the loop result is not ... | not the way we want.
we can have loop results that result0's user is extract, result1's user is not extract, and still this should work. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,684 | intel | whitneywhtsang | @@ -0,0 +1,25 @@
+// Conversions from TritonIntelGPU DpasEncodingAttr to LinearLayout.
+
+#ifndef TRITON_DIALECT_TRITONINTELGPU_IR_LINEARLAYOUTCONVERSIONS_H
+#define TRITON_DIALECT_TRITONINTELGPU_IR_LINEARLAYOUTCONVERSIONS_H
+
+#include <optional>
+
+#include "intel/include/Dialect/TritonIntelGPU/IR/Attributes.h"
+#inc... | In the comment, it is written that default to -1, but here it is default to 2. |
intel-xpu-backend-for-triton | github_2023 | others | 1,684 | intel | whitneywhtsang | @@ -1,11 +1,12 @@
add_triton_library(TritonIntelGPUIR
Dialect.cpp
Ops.cpp
-
+ LinearLayoutConversions.cpp
DEPENDS
TritonIntelGPUTableGen
TritonIntelGPUAttrDefsIncGen
LINK_LIBS PUBLIC
MLIRSideEffectInterfaces
+ | Remove. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,684 | intel | whitneywhtsang | @@ -747,19 +754,32 @@ loadSharedToDistributed(Value dst, Value src, SharedMemoryObject &shrMemObj,
auto srcTy = cast<MemDescType>(src.getType());
SmallVector<Value> ret;
- if (emitTransferBetweenRegistersAndShared(
- dstTy, srcTy, elemTy, /*maxVecElems=*/std::nullopt,
- shrMemObj.getBase(), s... | ```suggestion
}
bool success = emitTransferBetweenRegistersAndShared(
dstTy, srcTy, elemTy, /*maxVecElems=*/std::nullopt,
shrMemObj.getBase(), shrMemObj.getStrides(), loc, rewriter,
target, [&](VectorType vecTy, Value vecAddr) {
auto vecVal... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,684 | intel | chengjunlu | @@ -140,3 +142,142 @@ Value llPrintf(ConversionPatternRewriter &rewriter, StringRef msg,
}
} // namespace mlir::LLVM::intel
+
+namespace mlir::triton::intel {
+bool emitTransferBetweenDPASAndShared(
+ RankedTensorType registerTy, MemDescType sharedTy, Type elemLlvmTy,
+ std::optional<int32_t> maxVecElems, Val... | This branch is taken only when the layout is the DPAS layout.
It seems this condition is always false. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,684 | intel | chengjunlu | @@ -140,3 +142,142 @@ Value llPrintf(ConversionPatternRewriter &rewriter, StringRef msg,
}
} // namespace mlir::LLVM::intel
+
+namespace mlir::triton::intel {
+bool emitTransferBetweenDPASAndShared(
+ RankedTensorType registerTy, MemDescType sharedTy, Type elemLlvmTy,
+ std::optional<int32_t> maxVecElems, Val... | The tensor in SLM should always have the SharedLayout.
It seems this condition is always false. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,684 | intel | chengjunlu | @@ -140,3 +142,142 @@ Value llPrintf(ConversionPatternRewriter &rewriter, StringRef msg,
}
} // namespace mlir::LLVM::intel
+
+namespace mlir::triton::intel {
+bool emitTransferBetweenDPASAndShared( | The LinearLayout allows us to use the common lowering code in TritonGPUToLLVM.
Is there any limitation in the function for us to re-use.
https://github.com/triton-lang/triton/blob/9c7f9f8e3f6c769d0c32d0c51265c04ba8b164ca/lib/Conversion/TritonGPUToLLVM/Utility.cpp#L267C6-L267C43 |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,720 | intel | etiotto | @@ -49,7 +49,10 @@ struct PrintOpConversion
LLVM::intel::llPrintf(rewriter, formatStr,
{pid[0], pid[1], pid[2], prefixStr});
} else {
+ assert(op.getNumOperands() == op.getIsSigned().size()); | add an assert message pls. |
intel-xpu-backend-for-triton | github_2023 | others | 1,694 | intel | whitneywhtsang | @@ -4,6 +4,9 @@
# Example usage:
# ./triton-opt.sh --triton-opt=<path to triton-opt> 01-vector-add-xpu.ttir --target=llir -mlir-print-ir-after-all
+echo "Warning: This script is deprecated, if you think it could be still helpful and needs to be updated, please create an Issue." >&2 | ```suggestion
echo "Warning: This script is deprecated, if you think it could be still helpful and needs to be updated, please create an GitHub issue." >&2
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,709 | intel | whitneywhtsang | @@ -10,34 +10,28 @@ using namespace mlir::triton::gpu;
// blocked -> shared.
// Swizzling in shared memory to avoid bank conflict. Normally used for
// A/B operands of dots.
-void lowerDistributedToShared(LocalAllocOp op, LocalAllocOpAdaptor adaptor,
+void lowerDistributedToShared(Location loc, Value src, Value dst,... | Can you please also change `mlir::triton::intel::storeDistributedToShared` signature to match the common `storeDistributedToShared`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,709 | intel | whitneywhtsang | @@ -10,34 +10,28 @@ using namespace mlir::triton::gpu;
// blocked -> shared.
// Swizzling in shared memory to avoid bank conflict. Normally used for
// A/B operands of dots.
-void lowerDistributedToShared(LocalAllocOp op, LocalAllocOpAdaptor adaptor,
+void lowerDistributedToShared(Location loc, Value src, Value dst,... | Can we change back to below in this PR?
```
Value smemBase =
LLVM::intel::getSharedMemoryBase(loc, rewriter, op.getOperation());
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,713 | intel | FMarno | @@ -58,6 +58,39 @@ namespace {
/// Import the GPU Ops to TritonGEN Patterns.
#include "GPUToTritonGEN.cpp.inc"
+struct GPUSubgroupReduceOpLowering
+ : public ConvertOpToLLVMPattern<mlir::gpu::SubgroupReduceOp> {
+ using ConvertOpToLLVMPattern<
+ mlir::gpu::SubgroupReduceOp>::ConvertOpToLLVMPattern;
+
+ Lo... | I think you should add a check for the uniform attribute, even if just to report that it isn't supported. |
intel-xpu-backend-for-triton | github_2023 | others | 1,713 | intel | FMarno | @@ -0,0 +1,18 @@
+// RUN: triton-opt -convert-gpu-to-tritongen %s | FileCheck %s
+
+module attributes {
+ "triton_gpu.threads-per-warp" = 16 : i32,
+ spirv.target_env = #spirv.target_env<#spirv.vce<v1.4, [Kernel, Addresses, GroupNonUniformShuffle, Int64], []>, #spirv.resource_limits<subgroup_size = 16>> | are both of these needed |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,713 | intel | FMarno | @@ -58,6 +58,39 @@ namespace {
/// Import the GPU Ops to TritonGEN Patterns.
#include "GPUToTritonGEN.cpp.inc"
+struct GPUSubgroupReduceOpLowering
+ : public ConvertOpToLLVMPattern<mlir::gpu::SubgroupReduceOp> {
+ using ConvertOpToLLVMPattern<
+ mlir::gpu::SubgroupReduceOp>::ConvertOpToLLVMPattern;
+
+ Lo... | Is there not a helper function to get the threads per warp/subgroup size? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,713 | intel | FMarno | @@ -58,6 +58,39 @@ namespace {
/// Import the GPU Ops to TritonGEN Patterns.
#include "GPUToTritonGEN.cpp.inc"
+struct GPUSubgroupReduceOpLowering
+ : public ConvertOpToLLVMPattern<mlir::gpu::SubgroupReduceOp> {
+ using ConvertOpToLLVMPattern<
+ mlir::gpu::SubgroupReduceOp>::ConvertOpToLLVMPattern;
+
+ Lo... | you could use `rewriter.replaceOpWithNewOp` here |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,713 | intel | victor-eds | @@ -58,6 +58,39 @@ namespace {
/// Import the GPU Ops to TritonGEN Patterns.
#include "GPUToTritonGEN.cpp.inc"
+struct GPUSubgroupReduceOpLowering
+ : public ConvertOpToLLVMPattern<mlir::gpu::SubgroupReduceOp> {
+ using ConvertOpToLLVMPattern<
+ mlir::gpu::SubgroupReduceOp>::ConvertOpToLLVMPattern;
+
+ Lo... | Can we this as a function and support remaining types? Shouldn't be much, right? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,687 | intel | whitneywhtsang | @@ -413,8 +413,12 @@ void init_triton_llvm(py::module &&m) {
// FIXME: Temporary workaround to avoid __devicelib_assert_fail
// optimization with InternalLinkage, which causes
// test_subprocess.py::test_assert to fail.
- if (fn.getName().str() == "__devicelib_assert_fail")
- ... | Why is it not enough to add optnone?
```suggestion
if (fn.getName().str() == "__devicelib_assert_fail")
fn.addFnAttr(llvm::Attribute::OptimizeNone);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,706 | intel | whitneywhtsang | @@ -105,12 +106,18 @@ static Value getSharedMemoryBase(Location loc,
auto ptrTy = LLVM::LLVMPointerType::get(
rewriter.getContext(), TritonGEN::TritonGENMemorySpace::kWorkgroup);
FunctionOpInterface func = op->getParentOfType<FunctionOpInterface>();
- size_t offset = 0;
- if (op->hasAttr("allocation.offs... | use llvm_unreachable instead. |
intel-xpu-backend-for-triton | github_2023 | python | 1,695 | intel | whitneywhtsang | @@ -401,9 +401,8 @@ def benchmark(B, M, N, K, provider):
func = getattr(xetla_kernel, name)
xetla_fn = lambda: func(a, b, c, acc, cnt)
torch_fn = lambda: torch.matmul(a, b).to(torch.float32)
- rtol = 1e-2 if a.dtype == torch.bfloat16 else 1e-3
# FIXME: XeTLA batch GEMM impleme... | ```suggestion
# benchmark_suit.assert_close(xetla_fn(), torch_fn(), atol=1e-4, rtol=1.0, err_msg="xetla to torch")
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,681 | intel | whitneywhtsang | @@ -951,6 +1008,7 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 :
tt.func @matmul_fmadot(%ptr:!tt.ptr<f32> {tt.divisibility = 16 : i32}, | Please help update memdesc with `#triton_gpu.shared_memory`. |
intel-xpu-backend-for-triton | github_2023 | others | 1,681 | intel | whitneywhtsang | @@ -1655,6 +1655,7 @@ module attributes {"triton_gpu.target" = "xpu:DEVICE_ARCH.PVC", "triton_gpu.num-
#blocked0 = #triton_gpu.blocked<{sizePerThread = [2], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
module attributes {"triton_gpu.num-ctas" = 1 : i32, ... | Can you open an issue to investigate? |
intel-xpu-backend-for-triton | github_2023 | others | 1,693 | intel | pbchekin | @@ -20,19 +20,28 @@ This is the development repository of Intel® XPU Backend for Triton\*, a new [T
# Install from source
```
-git clone https://github.com/intel/intel-xpu-backend-for-triton.git -b llvm-target
-cd intel-xpu-backend-for-triton
-scripts/compile-triton.sh
+git clone https://github.com/triton-lang/trit... | The instructions are confusing: this builds an upstream Triton instead of Triton XPU from this repository. Not sure why we need this. |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.