repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,540 | intel | etiotto | @@ -93,24 +90,30 @@ LogicalResult GlueOp::verify() {
SmallVector<Type> inputTypes;
for (auto input : getOperands())
inputTypes.push_back(input.getType());
-
+ Type inputType = inputTypes[0];
Type resultType = getRes().getType();
- unsigned resultRank = getRank(resultType);
- if (llvm::any_of(inputTypes... | If the operands do not have the same rank how are they glued ? Before generating a `GlueOp` I think one should reshape the input tensors. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,540 | intel | etiotto | @@ -133,30 +135,37 @@ LogicalResult GlueOp::verify() {
// Verify that the composition of the input operands covers the output tensor
// shape.
+ SmallVector<int64_t> inputShape = getShape(inputTypes[0]);
SmallVector<int64_t> resultShape = getShape(resultType);
unsigned numResultElems = product(resultShap... | why are we removing this constraint ? Can the producer of this operation reshape the input tensors so that we can maintain this constraint ? |
intel-xpu-backend-for-triton | github_2023 | others | 1,540 | intel | etiotto | @@ -116,60 +116,6 @@ tt.func public @simplify_scf_for(%arg0: tensor<16x8xf16>, %arg1: tensor<16x8xf16
// -----
-// COM: Test SCF canonicalization: ensure loop is not modified when the result is not used by just 'extract' operations. | this was working... can we preserve existing functionality and tests cases ? |
intel-xpu-backend-for-triton | github_2023 | others | 1,540 | intel | etiotto | @@ -59,7 +59,7 @@ def TTIG_GlueOp : TTIG_Op<"glue", [Pure]> {
-> ptr<tensor<16x24xf16>>
```
}];
- let arguments = (ins Variadic<TT_TensorOrTensorPtr>:$operands); | I think we should continue to constraint the input types of this operation. |
intel-xpu-backend-for-triton | github_2023 | others | 1,540 | intel | etiotto | @@ -116,4 +116,22 @@ def TTIG_PrefetchOp : TTIG_Op<"prefetch"> {
}];
}
+// same as tt.broadcast except that we don't require SameOperandsAndResultEncoding
+def TTIG_BroadcastOp : TTIG_Op<"broadcast", [Pure, | why do we need to create a new operation ? |
intel-xpu-backend-for-triton | github_2023 | others | 1,540 | intel | etiotto | @@ -1276,7 +1276,9 @@ elements along the K dim, or they use all elements of the tensor along the K dim
ins
"unsigned":$opIdx,
"Attribute":$parent,
- DefaultValuedParameter<"unsigned", "0">:$kWidth
+ DefaultValuedParameter<"unsigned", "0">:$kWidth,
+ // intel specific
+ DefaultValuedParameter<... | Document what this new parameter does (in the description). |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,540 | intel | etiotto | @@ -1018,7 +1018,7 @@ SmallVector<unsigned> DotOperandEncodingAttr::getShapePerCTATile(
LogicalResult DotOperandEncodingAttr::verify(
::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError,
- unsigned opIdx, Attribute parent, unsigned kWidth) {
+ unsigned opIdx, Attribute parent, unsigned kWidth, bo... | Any new constraints to verify here when transpose == true ? |
intel-xpu-backend-for-triton | github_2023 | others | 1,540 | intel | etiotto | @@ -279,3 +251,105 @@ tt.func public @matmul_kernel_with_block_pointers_tf32(%arg0: !tt.ptr<f32> {tt.d
tt.store %tptr_c, %35#0 {boundaryCheck = array<i32: 0, 1>} : !tt.ptr<tensor<8x32xf32, #warp>>
tt.return
}
+
+// -----
+
+// COM: Test Attention Related Ops
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [16... | I think we should CHECK that 32 tt.dot operations are generated here. |
intel-xpu-backend-for-triton | github_2023 | others | 1,540 | intel | etiotto | @@ -279,3 +251,105 @@ tt.func public @matmul_kernel_with_block_pointers_tf32(%arg0: !tt.ptr<f32> {tt.d
tt.store %tptr_c, %35#0 {boundaryCheck = array<i32: 0, 1>} : !tt.ptr<tensor<8x32xf32, #warp>>
tt.return
}
+
+// -----
+
+// COM: Test Attention Related Ops
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [16... | I think we should CHECK that 32 tt.dot operations are generated here. |
intel-xpu-backend-for-triton | github_2023 | others | 1,540 | intel | etiotto | @@ -279,3 +251,105 @@ tt.func public @matmul_kernel_with_block_pointers_tf32(%arg0: !tt.ptr<f32> {tt.d
tt.store %tptr_c, %35#0 {boundaryCheck = array<i32: 0, 1>} : !tt.ptr<tensor<8x32xf32, #warp>>
tt.return
}
+
+// -----
+
+// COM: Test Attention Related Ops
+
+#warp = #triton_intel_gpu.warp<{sizePerThread = [16... | Also CHECK that the advance operations are generated |
intel-xpu-backend-for-triton | github_2023 | others | 1,540 | intel | etiotto | @@ -116,4 +116,22 @@ def TTIG_PrefetchOp : TTIG_Op<"prefetch"> {
}];
}
+// same as tt.broadcast except that we don't require SameOperandsAndResultEncoding
+def TTIG_BroadcastOp : TTIG_Op<"broadcast", [Pure,
+ SameOperandsAndResultElementType]> {
+ let summary = "broadcas... | Use:
```
let assemblyFormat = [{
$src attr-dict `:` type($src) `->` type($result)
}]; |
intel-xpu-backend-for-triton | github_2023 | others | 1,540 | intel | etiotto | @@ -1,53 +1,21 @@
// RUN: triton-opt -split-input-file -verify-diagnostics %s
-tt.func @triton_intel_gpu.glue(%tensor1 : tensor<16x8xf16>, %tensor2 : tensor<8xf16>) {
- // expected-error @+1 {{'triton_intel_gpu.glue' op operands and result must have the same rank}}
- triton_intel_gpu.glue %tensor1, %tensor2 : (ten... | This test isn't needed. The previous test at line 3-7 already checks that tensors with the same shape but different element types cannot be glued.
We need a test to ensure tensors with same element type but different shape cannot be glued though. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,540 | intel | etiotto | @@ -567,6 +573,90 @@ MatchTargetSizePass::getSubTypeAndShape(Type type) const {
return {{0}, type, {0}};
}
+Value MatchTargetSizePass::getSubVal(Operation *op, Value val,
+ ArrayRef<int64_t> srcOffset,
+ ArrayRef<int64_t> dstSize) {
+ OpBuil... | auto -> int64_t |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,540 | intel | etiotto | @@ -567,6 +573,90 @@ MatchTargetSizePass::getSubTypeAndShape(Type type) const {
return {{0}, type, {0}};
}
+Value MatchTargetSizePass::getSubVal(Operation *op, Value val,
+ ArrayRef<int64_t> srcOffset,
+ ArrayRef<int64_t> dstSize) {
+ OpBuil... | This variable is dead, remove. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,540 | intel | etiotto | @@ -567,6 +573,90 @@ MatchTargetSizePass::getSubTypeAndShape(Type type) const {
return {{0}, type, {0}};
}
+Value MatchTargetSizePass::getSubVal(Operation *op, Value val,
+ ArrayRef<int64_t> srcOffset,
+ ArrayRef<int64_t> dstSize) {
+ OpBuil... | auto -> operation * |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,540 | intel | etiotto | @@ -731,18 +852,20 @@ void MatchTargetSizePass::transformGenericOp(Operation *op) {
case 2: {
for (unsigned j = 0; j < shape[0]; j += subSize[0]) {
SmallVector<Value> newOperands;
- llvm::transform(op->getOperands(), std::back_inserter(newOperands),
- [&](Value operand... | This is not needed. Removing these 2 lines is fine because we would `return operand` at line 867 |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,540 | intel | etiotto | @@ -91,26 +88,30 @@ namespace mlir::triton::gpu::intel {
LogicalResult GlueOp::verify() {
SmallVector<Type> inputTypes;
- for (auto input : getOperands())
+ for (Value input : getOperands())
inputTypes.push_back(input.getType());
+ Type inputType = inputTypes.front();
Type resultType = getRes().getTy... | This code is no longer required because we are checking that all operands have the same type at lines 96-97. |
intel-xpu-backend-for-triton | github_2023 | others | 1,540 | intel | etiotto | @@ -88,22 +58,6 @@ tt.func @triton_intel_gpu.glue(%tensor1 : tensor<16x8xf16>, %tensor2 : tensor<16
// -----
-tt.func @triton_intel_gpu.extract(%tensor : tensor<16x16xf16>) {
- // expected-error @+1 {{'triton_intel_gpu.extract' op operand and result must have the same rank}}
- triton_intel_gpu.extract %tensor[0]... | This is no longer diagnosed as invalid |
intel-xpu-backend-for-triton | github_2023 | others | 1,540 | intel | etiotto | @@ -279,3 +251,111 @@ tt.func public @matmul_kernel_with_block_pointers_tf32(%arg0: !tt.ptr<f32> {tt.d
tt.store %tptr_c, %35#0 {boundaryCheck = array<i32: 0, 1>} : !tt.ptr<tensor<8x32xf32, #warp>>
tt.return
}
+
+// -----
+
+// COM: Test Attention Related Ops
+#warp = #triton_intel_gpu.warp<{sizePerThread = [16, ... | It did not make a difference in the test case though. Existing CHECK verify without the module. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,540 | intel | whitneywhtsang | @@ -158,31 +163,36 @@ class MatchTargetSizePass
return WalkResult::advance();
if (isa<scf::ForOp, scf::YieldOp>(op))
return WalkResult::advance();
+ if (auto expand = dyn_cast<tt::ExpandDimsOp>(op))
+ return WalkResult::advance();
- LLVM_DEBUG({
- llvm::dbgs() << "Proc... | Can you elaborate on what should be fixed? |
intel-xpu-backend-for-triton | github_2023 | others | 1,540 | intel | victor-eds | @@ -1270,13 +1270,18 @@ The parent field is the layout of d.
kWidth defines number of consecutive elements stored by one thread along k dimension.
Some layouts do not use this parameter, either because they have a fixed number of
elements along the K dim, or they use all elements of the tensor along the K dim.
+
+`i... | Do we think we will be able to upstream this? Sounds like a hard one to pull out... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,540 | intel | etiotto | @@ -133,30 +121,36 @@ LogicalResult GlueOp::verify() {
// Verify that the composition of the input operands covers the output tensor
// shape.
+ SmallVector<int64_t> inputShape = getShape(inputTypes[0]);
SmallVector<int64_t> resultShape = getShape(resultType);
unsigned numResultElems = product(resultShap... | I'll post a PR to address this TODO after this one lands. |
intel-xpu-backend-for-triton | github_2023 | others | 1,616 | intel | victor-eds | @@ -19,9 +19,10 @@ def TritonIntelGPU_Dialect : Dialect {
];
let extraClassDeclaration = [{
- /// Get the name of the attribute used to indicate the target architecture.
- static constexpr ::llvm::StringLiteral getTargetAttrName() {
- return ::llvm::StringLiteral("triton_gpu.target");
+ /// Get th... | Make this `constexpr` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,616 | intel | victor-eds | @@ -65,22 +59,11 @@ DPASAnalysis::canUseDPAS(FunctionOpInterface funcOp) const {
return Result::Maybe;
unsigned threadsPerWarp = cast<IntegerAttr>(threadsPerWarpAttr).getInt();
- DeviceArch arch = getDeviceArch(mod);
- if (threadsPerWarp == supportedThreadsPerWarp(arch))
- return Result::True;
-
- retur... | ```suggestion
mod->getAttr<IntegerAttr>(TritonIntelGPUDialect::getMinSGSizeAttrName())
.getInt();
```
I think this is possible |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,616 | intel | victor-eds | @@ -46,14 +41,16 @@ struct TritonAnnotateModule
const std::string &AttrNumThreadsPerWarp =
TritonGPUDialect::getThreadsPerWarpAttrName();
- auto result = mod.walk([&](FunctionOpInterface funcOp) {
+ mod.walk([&](FunctionOpInterface funcOp) {
+ // TODO: DPAS lowering only implemented for 16 th... | Make `16` a constant |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,616 | intel | etiotto | @@ -23,18 +22,13 @@ DPASAnalysis::DPASAnalysis(Operation *root) {
else
funcToDotMap[funcOp] = {dotOp};
- DPASEngineType dpasEngineType =
- (!supportDPAS || arch == DeviceArch::UNKNOWN)
- ? DPASEngineType::NOT_APPLICABLE
- : DPASAnalysis::getDPASType(dotOp);
+ ... | ```suggestion
DPASEngineType dpasEngineType = supportDPAS ?
DPASAnalysis::getDPASType(dotOp) : DPASEngineType::NOT_APPLICABLE;;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,616 | intel | etiotto | @@ -19,15 +19,10 @@ struct TritonAnnotateModule
void runOnOperation() final {
ModuleOp mod = getOperation();
- if (target.getValue().empty()) {
- mod.emitError("Expecting target specification");
- return signalPassFailure();
- }
-
Builder builder(mod);
- mod->setAttr(intel::TritonIntel... | add newline before if stmt |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,608 | intel | etiotto | @@ -10,7 +10,8 @@ DPASAnalysis::DPASAnalysis(Operation *root) {
mod = root->getParentOfType<ModuleOp>();
DeviceArch arch = getDeviceArch(mod);
- bool isLTS = mod->hasAttr(TritonIntelGPUDialect::getLTSAttrName()); | Can we remove `getLTSAttrName` from the `TritonIntelGPUDialect` ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,608 | intel | etiotto | @@ -11,6 +11,7 @@
#include "mlir/Transforms/DialectConversion.h"
#include "intel/include/Dialect/TritonIntelGPU/IR/Attributes.h"
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h" | Is this needed ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,608 | intel | etiotto | @@ -267,7 +270,7 @@ class TritonGPUToLLVMPipelineManager {
/// Selects which conversion pipeline to use.
/// FIXME: this is temporary and should be removed once we have an analysis to
/// determine whether a kernel uses block pointers.
- bool blockPtrPathIsEnabled = false;
+ bool isAdvancePathEnabled = false... | Advance -> Advanced |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,608 | intel | etiotto | @@ -79,9 +79,14 @@ struct ConvertTritonGPUToLLVM
intel::TritonGPUToLLVMPipelineManager pipelineManager(mod, context);
mlir::LowerToLLVMOptions option(context);
option.overrideIndexBitwidth(32);
- bool isLTSDriver = mod->hasAttr("triton_gpu.is_lts");
+ bool isAdvancePathEnabled = | Advance -> Advanced |
intel-xpu-backend-for-triton | github_2023 | others | 1,608 | intel | etiotto | @@ -28,8 +28,10 @@ def TritonAnnotateModule: Pass<"triton-annotate-module", "mlir::ModuleOp"> {
Option<"target", "target",
"std::string", /*default*/"\"\"",
"the GPU target, e.g., PVC">,
- Option<"isLTS", "is-lts", "bool", /*default*/"false",
- "whether we are using an LTS driv... | whether the DPAS instruction is available |
intel-xpu-backend-for-triton | github_2023 | others | 1,608 | intel | etiotto | @@ -28,8 +28,10 @@ def TritonAnnotateModule: Pass<"triton-annotate-module", "mlir::ModuleOp"> {
Option<"target", "target",
"std::string", /*default*/"\"\"",
"the GPU target, e.g., PVC">,
- Option<"isLTS", "is-lts", "bool", /*default*/"false",
- "whether we are using an LTS driv... | whether subgroup 2D block operations (e.g. 2D block load/stores) are available">, |
intel-xpu-backend-for-triton | github_2023 | others | 1,608 | intel | etiotto | @@ -24,10 +24,8 @@ def TritonIntelGPU_Dialect : Dialect {
return ::llvm::StringLiteral("triton_gpu.target");
}
- /// Get the name of the attribute used to indicate the LTS driver.
- static ::llvm::StringLiteral getLTSAttrName() {
- return ::llvm::StringLiteral("triton_gpu.is_lts");
- }
+ ... | Add comment like at line 22 |
intel-xpu-backend-for-triton | github_2023 | python | 1,608 | intel | etiotto | @@ -174,7 +174,8 @@ def make_ttgir(mod, metadata, opt, device_arch):
pm = ir.pass_manager(mod.context)
pm.enable_debug()
- if (not is_lts and os.getenv("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") == "1"):
+ if (properties["support_cl_sg_2d_block_io"] and properties["support_cl_sg_matmul_acc"... | rename Experimental to Advanced? |
intel-xpu-backend-for-triton | github_2023 | others | 1,608 | intel | etiotto | @@ -1,8 +1,8 @@
-// RUN: triton-opt %s --split-input-file -triton-annotate-module='target=xpu:DEVICE_ARCH.PVC threads-per-warp=32' | FileCheck %s
+// RUN: triton-opt %s --split-input-file -triton-annotate-module='target=xpu:DEVICE_ARCH.PVC support-dpas=true threads-per-warp=32' | FileCheck %s | also test the option for 2D block operations. |
intel-xpu-backend-for-triton | github_2023 | others | 1,608 | intel | etiotto | @@ -214,7 +214,7 @@ module attributes {"triton_gpu.target" = "xpu:DEVICE_ARCH.PVC", "triton_gpu.num-
// COM: Case 3:
// COM: Check that operations using block pointers without a layout attribute are rewritten to use a legacy pointer.
-module attributes {"triton_gpu.target" = "xpu:DEVICE_ARCH.PVC"} {
+module attribu... | add the attribute indication the target HW supports DPAS. |
intel-xpu-backend-for-triton | github_2023 | others | 1,608 | intel | etiotto | @@ -9,7 +9,7 @@
#dpas = #triton_intel_gpu.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA = [16, 4], repCluster = [1, 1], A = [8, 16], B = [16, 16], C = [8, 16]}>
#dot0 = #triton_gpu.dot_op<{opIdx = 0, parent = #dpas, kWidth=2}>
#dot1 = #triton_gpu.dot_o... | add the attribute indication the target HW supports DPAS to all applicable tests |
intel-xpu-backend-for-triton | github_2023 | others | 1,608 | intel | etiotto | @@ -127,7 +127,7 @@ module attributes {"triton_gpu.target" = "xpu:DEVICE_ARCH.PVC", "triton_gpu.num-
#dot0 = #triton_gpu.dot_op<{opIdx = 0, parent = #dpas, kWidth=2}>
#dot1 = #triton_gpu.dot_op<{opIdx = 1, parent = #dpas, kWidth=2}>
-module attributes {"triton_gpu.target" = "xpu:DEVICE_ARCH.PVC", "triton_gpu.num-wa... | I see that the test CHECK for tt.dot with a DPAS annotation:
```
// CHECK: tt.dot {{.*}} : tensor<128x64xf16, #triton_gpu.dot_op<{opIdx = 0, parent = #[[$DPAS]], kWidth = 2}>> * tensor<64x256xf16, #triton_gpu.dot_op<{opIdx = 1, parent = #[[$DPAS]], kWidth = 2}>> -> tensor<128x256xf32, #[[$DPAS]]>
```
However the m... |
intel-xpu-backend-for-triton | github_2023 | python | 1,608 | intel | etiotto | @@ -152,19 +151,20 @@ def make_ttir(mod, metadata, opt):
return mod
@staticmethod
- def make_ttgir(mod, metadata, opt, device_arch):
+ def make_ttgir(mod, metadata, opt, properties):
cluster_info = intel.ClusterInfo()
if opt.cluster_dims is not None:
cluster_info.clu... | Would be best to pass all of the properties to the transformation so that it can annotate the module with all relevant properties. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | victor-eds | @@ -78,6 +83,9 @@ void init_triton_intel_passes_ttgpuir(py::module &&m) {
gpu::intel::createTritonIntelGPUDistributeToWarps);
ADD_PASS_WRAPPER_0("add_match_target_size",
gpu::intel::createTritonIntelGPUMatchTargetSize);
+ ADD_PASS_WRAPPER_OPT_3("add_triton_annotate_module... | ```suggestion
ADD_PASS_WRAPPER_OPT_3("add_triton_annotate_module",
gpu::intel::createTritonAnnotateModule, const std::string &,
bool, unsigned);
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,581 | intel | victor-eds | @@ -0,0 +1,38 @@
+//===-- Passes.td - Triton Annotate Module Passes ----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | ```suggestion
This pass analyzes the kernel's workload pattern and annotates the module with
attributes that can be used to steer exploitation of HW features of the target
device by subsequent transformations.
For example, this pass can override the subgroup size (aka warp size) provided
by the... |
intel-xpu-backend-for-triton | github_2023 | others | 1,581 | intel | victor-eds | @@ -0,0 +1,38 @@
+//===-- Passes.td - Triton Annotate Module Passes ----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | As we're using subgroup size above, can we be consistent with the naming? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | victor-eds | @@ -0,0 +1,69 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "intel/include/TritonAnnotateModule/Passes.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+namespace mlir::triton::gpu::intel {
+#define GEN_PASS_DEF_TRITONANNOTATEMODULE
+#include "intel/include/TritonAnnotateModule/Passes.h.inc"
+} // namesp... | ```suggestion
: intel::impl::TritonAnnotateModuleBase<TritonAnnotateModule> {
```
`public` is the default for `struct` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | victor-eds | @@ -0,0 +1,69 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "intel/include/TritonAnnotateModule/Passes.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+namespace mlir::triton::gpu::intel {
+#define GEN_PASS_DEF_TRITONANNOTATEMODULE
+#include "intel/include/TritonAnnotateModule/Passes.h.inc"
+} // namesp... | ```suggestion
void runOnOperation() final {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | victor-eds | @@ -0,0 +1,69 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "intel/include/TritonAnnotateModule/Passes.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+namespace mlir::triton::gpu::intel {
+#define GEN_PASS_DEF_TRITONANNOTATEMODULE
+#include "intel/include/TritonAnnotateModule/Passes.h.inc"
+} // namesp... | These should be defined [here](https://github.com/intel/intel-xpu-backend-for-triton/blob/c6394b4e37d8cadf364e19104ce9c8dde843759b/third_party/intel/include/Dialect/TritonIntelGPU/IR/TritonIntelGPUDialect.td#L21) IMO as we do [here](https://github.com/intel/intel-xpu-backend-for-triton/blob/c6394b4e37d8cadf364e19104ce9... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | victor-eds | @@ -0,0 +1,69 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "intel/include/TritonAnnotateModule/Passes.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+namespace mlir::triton::gpu::intel {
+#define GEN_PASS_DEF_TRITONANNOTATEMODULE
+#include "intel/include/TritonAnnotateModule/Passes.h.inc"
+} // namesp... | We're blindly setting an input string as the target here. I propose:
- Changing the option type from `std::string` to `mlir::triton::gpu::intel::DeviceArch`
- Setting the string accordingly here
This way, we would make sure users cannot put garbage there or make mistakes.
Note if `mlir::triton::gpu::intel::Devi... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | victor-eds | @@ -0,0 +1,69 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "intel/include/TritonAnnotateModule/Passes.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+namespace mlir::triton::gpu::intel {
+#define GEN_PASS_DEF_TRITONANNOTATEMODULE
+#include "intel/include/TritonAnnotateModule/Passes.h.inc"
+} // namesp... | Can we make this a `UnitAttr`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | victor-eds | @@ -0,0 +1,69 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "intel/include/TritonAnnotateModule/Passes.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+namespace mlir::triton::gpu::intel {
+#define GEN_PASS_DEF_TRITONANNOTATEMODULE
+#include "intel/include/TritonAnnotateModule/Passes.h.inc"
+} // namesp... | It is amazing this returns `std::string`... We cannot do much about it, tho |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | victor-eds | @@ -0,0 +1,69 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "intel/include/TritonAnnotateModule/Passes.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+namespace mlir::triton::gpu::intel {
+#define GEN_PASS_DEF_TRITONANNOTATEMODULE
+#include "intel/include/TritonAnnotateModule/Passes.h.inc"
+} // namesp... | We're paying the cost of creating a new `DPASAnalysis` in every iteration. We should define `DPASAnalysis` as a proper analysis ([see](https://mlir.llvm.org/docs/PassManagement/#analysis-management)) and query analysis here instead. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | victor-eds | @@ -0,0 +1,69 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "intel/include/TritonAnnotateModule/Passes.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+namespace mlir::triton::gpu::intel {
+#define GEN_PASS_DEF_TRITONANNOTATEMODULE
+#include "intel/include/TritonAnnotateModule/Passes.h.inc"
+} // namesp... | ```suggestion
ModuleOp mod = getOperation();
Builder builder(mod);
```
Create builder to use below |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | victor-eds | @@ -0,0 +1,69 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "intel/include/TritonAnnotateModule/Passes.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+namespace mlir::triton::gpu::intel {
+#define GEN_PASS_DEF_TRITONANNOTATEMODULE
+#include "intel/include/TritonAnnotateModule/Passes.h.inc"
+} // namesp... | We should not query for this in every iteration |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | victor-eds | @@ -0,0 +1,69 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "intel/include/TritonAnnotateModule/Passes.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+namespace mlir::triton::gpu::intel {
+#define GEN_PASS_DEF_TRITONANNOTATEMODULE
+#include "intel/include/TritonAnnotateModule/Passes.h.inc"
+} // namesp... | ```suggestion
builder.getI32IntegerAttr(reqThreadsPerWarp));
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | victor-eds | @@ -0,0 +1,69 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "intel/include/TritonAnnotateModule/Passes.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+namespace mlir::triton::gpu::intel {
+#define GEN_PASS_DEF_TRITONANNOTATEMODULE
+#include "intel/include/TritonAnnotateModule/Passes.h.inc"
+} // namesp... | Use builder interface here too |
intel-xpu-backend-for-triton | github_2023 | others | 1,581 | intel | victor-eds | @@ -0,0 +1,38 @@
+//===-- Passes.td - Triton Annotate Module Passes ----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | ```suggestion
Option<"target", "target",
"mlir::triton::gpu::intel::DeviceArch",
/*default*/"mlir::triton::gpu::intel::DeviceArch::UNKNOWN",
"the GPU target, e.g., PVC",
[{::llvm::cl::values(
clEnumValN(mlir::triton::gpu::intel::DeviceArch::UNKNOWN, "UNK... |
intel-xpu-backend-for-triton | github_2023 | python | 1,581 | intel | victor-eds | @@ -155,16 +155,24 @@ def make_ttir(mod, metadata, opt):
@staticmethod
def make_ttgir(mod, metadata, opt, device_arch):
is_lts = Version(metadata["target"].arch["driver_version"]) == Version("1.3.27642")
- if (not is_lts and os.getenv("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") == "1"):
- ... | ```suggestion
intel.passes.ttgpuir.add_triton_annotate_module(pm, device_arch, is_lts, opt.threads_per_warp)
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,581 | intel | whitneywhtsang | @@ -0,0 +1,70 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
+#include "intel/include/TritonAnnotateModule/Passes.h"
+
+namespace mlir::triton::gpu::intel {
+#define GEN_PASS_DEF_TRITONANNOTATEMODULE
+#include "intel/include/TritonAnnotateModule/Passes.h.inc"
... | do we need to return this?
```suggestion
return WalkResult::interrupt();
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,564 | intel | chengjunlu | @@ -0,0 +1,285 @@
+"""
+Stream K GEMM with Block Pointers
+=====================
+Stream K is a approach that aims to resovle quantization inefficiency in GPU work load for GEMM problems.
+This script implements a Stream K GEMM with block pointers to achieve better hardware utilization.
+"""
+
+import torch
+import int... | Replace `cuBLAS` with `oneDNN` |
intel-xpu-backend-for-triton | github_2023 | python | 1,564 | intel | chengjunlu | @@ -0,0 +1,285 @@
+"""
+Stream K GEMM with Block Pointers
+=====================
+Stream K is a approach that aims to resovle quantization inefficiency in GPU work load for GEMM problems.
+This script implements a Stream K GEMM with block pointers to achieve better hardware utilization.
+"""
+
+import torch
+import int... | Keep the same indentation |
intel-xpu-backend-for-triton | github_2023 | python | 1,564 | intel | chengjunlu | @@ -0,0 +1,285 @@
+"""
+Stream K GEMM with Block Pointers
+=====================
+Stream K is a approach that aims to resovle quantization inefficiency in GPU work load for GEMM problems.
+This script implements a Stream K GEMM with block pointers to achieve better hardware utilization.
+"""
+
+import torch
+import int... | Move the threads_per_warp to the triton.Config. |
intel-xpu-backend-for-triton | github_2023 | python | 1,564 | intel | chengjunlu | @@ -0,0 +1,285 @@
+"""
+Stream K GEMM with Block Pointers
+=====================
+Stream K is a approach that aims to resovle quantization inefficiency in GPU work load for GEMM problems.
+This script implements a Stream K GEMM with block pointers to achieve better hardware utilization.
+"""
+
+import torch
+import int... | Add the vendor specific compile option like this:
`triton.Config({'double_GRF': true, 'threads_per_warp': 16, 'BLOCK_SIZE_M': 256, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 32, 'GROUP_SIZE_M': 4}` |
intel-xpu-backend-for-triton | github_2023 | python | 885 | intel | whitneywhtsang | @@ -34,6 +34,11 @@ def is_hip():
def is_xpu():
return not is_interpreter() and triton.runtime.driver.active.get_current_target()[0] == "xpu"
+def xpu_has_fp64():
+ return is_xpu() and triton.runtime.driver.active.get_current_target()[1]['has_fp64']
+
+def threads_per_warp_dpas():
+ return 16 if xpu_has_fp... | assert is_xpu() |
intel-xpu-backend-for-triton | github_2023 | python | 885 | intel | whitneywhtsang | @@ -34,6 +34,11 @@ def is_hip():
def is_xpu():
return not is_interpreter() and triton.runtime.driver.active.get_current_target()[0] == "xpu"
+def xpu_has_fp64():
+ return is_xpu() and triton.runtime.driver.active.get_current_target()[1]['has_fp64'] | I prefer `assert is_xpu()` then `return is_xpu() and ...`, WDYT? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,537 | intel | etiotto | @@ -180,62 +180,77 @@ emitOffsetForDotOpLayout(const DotOperandEncodingAttr &dotLayout,
dpasLayout.getDPASRepetitions(shapePerCTA, opIdx);
SmallVector<unsigned> warpShape =
(opIdx == 0) ? dpasLayout.getShapeA() : dpasLayout.getShapeB();
+ SmallVector<unsigned> instShape = (opIdx == 0)
+ ... | [nit]: Lets use `unsigned` rather than uint32_t for consistency. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,537 | intel | etiotto | @@ -180,62 +180,77 @@ emitOffsetForDotOpLayout(const DotOperandEncodingAttr &dotLayout,
dpasLayout.getDPASRepetitions(shapePerCTA, opIdx);
SmallVector<unsigned> warpShape =
(opIdx == 0) ? dpasLayout.getShapeA() : dpasLayout.getShapeB();
+ SmallVector<unsigned> instShape = (opIdx == 0)
+ ... | Use static type here instead of auto |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,537 | intel | etiotto | @@ -288,19 +303,20 @@ emitBaseIndexForDotOpLayout(Location loc, RewriterBase &rewriter,
SmallVector<Value> multiDimWarpId =
mlir::LLVM::delinearize(rewriter, loc, warpId, warpsPerCTA, order);
- Value rowWarpId =
- urem(multiDimWarpId[0],
- i32_val(mlir::ceil<unsigned>(shapePerCTA[0], warpSha... | [Style]: Use ternary operator, code is shorter and it allows to initialize `warpIndex` immediately. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,537 | intel | etiotto | @@ -335,8 +351,12 @@ emitBaseIndexForDotOpLayout(Location loc, RewriterBase &rewriter,
} break;
}
- SmallVector<Value> multiDimBase = {add(laneRowIndex, rowWarpOffset),
- add(laneColIndex, colWarpOffset)};
+ SmallVector<Value> multiDimBase; | use ternary operator |
intel-xpu-backend-for-triton | github_2023 | others | 1,093 | intel | gshimansky | @@ -50,3 +50,50 @@ if [ "$QUIET" = false ]; then
echo "AGAMA_VERSION=$AGAMA_VERSION"
echo "GPU_DEVICE=$GPU_DEVICE"
fi
+
+agama_to_driver_type() {
+ local lts=(803)
+ local rolling=(821 775)
+
+ local agama=$1
+ local found="false"
+
+ for item in "${lts[@]}"; do
+ if [[ "$agama" -eq "$i... | echo "lts" |
intel-xpu-backend-for-triton | github_2023 | others | 1,093 | intel | pbchekin | @@ -34,6 +40,12 @@ pytest() {
mkdir -p "$CURRENT_SKIPLIST_DIR"
# skip comments in the skiplist
sed -e '/^#/d' "$TRITON_TEST_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt" > "$CURRENT_SKIPLIST_DIR/$TRITON_TEST_SUITE.txt"
+
+ # put skiplist/pvc_{rolling/lts}/language.txt to the current skiplist
+ ... | The skiplist can be changed by setting `TRITON_TEST_SKIPLIST_DIR`, no need to overwrite the exiting files in the current skiplist. |
intel-xpu-backend-for-triton | github_2023 | others | 1,093 | intel | vlad-penkin | @@ -50,3 +50,50 @@ if [ "$QUIET" = false ]; then
echo "AGAMA_VERSION=$AGAMA_VERSION"
echo "GPU_DEVICE=$GPU_DEVICE"
fi
+
+agama_to_driver_type() {
+ local lts=(803)
+ local rolling=(821 775) | Please do not hardcode the Rolling driver version numbers. |
intel-xpu-backend-for-triton | github_2023 | others | 1,591 | intel | pbchekin | @@ -13,7 +13,7 @@ This is the development repository of Intel® XPU Backend for Triton\*, a new [T
|OS|Ubuntu [22.04](http://releases.ubuntu.com/22.04/)| [Install Ubuntu](https://ubuntu.com/tutorials)|
|GPU Card | Intel® Data Center GPU Max, Flex Series or Intel Arc A770 |[Max](https://www.intel.com/content/www/us... | Should we use PyTorch Prerequisites for Intel GPUs instead?
```suggestion
|Toolchain |[PyTorch Prerequisites for Intel GPUs](https://www.intel.com/content/www/us/en/developer/articles/tool/pytorch-prerequisites-for-intel-gpus.html)|[Install PyTorch Prerequisites for Intel GPUs](https://www.intel.com/content/www/us/... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,571 | intel | FMarno | @@ -158,19 +158,19 @@ static LLVM::CallOp createSubGroupShuffle(ConversionPatternRewriter &rewriter,
std::string fnName = ""; | Create a new `StringRef` variable to get the result from the switch statement, then define `fnName` as the result of `mangle` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,571 | intel | victor-eds | @@ -155,22 +156,22 @@ static LLVM::CallOp createSubGroupShuffle(ConversionPatternRewriter &rewriter,
cast<IntegerType>(mask.getType()).isInteger(32) &&
"Expecting mask type to be i32");
- std::string fnName = "";
+ StringRef func;
switch (kind) {
case TritonGEN::ShflKind::XOR:
- fnName ... | That `j` should be added by mangling. Are we missing a type in the types argument to `intel::mangle`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,515 | intel | etiotto | @@ -697,58 +697,70 @@ struct StoreOpConversion
Value basePitch = mul(rowStride, elemSizeInBytes);
// A warp stride for the replicates.
- int outerDimWarpNum = std::min<int>(
- warpsPerCTA[0], mlir::ceil<unsigned>(tensorShape[0], elemsPerInstr[0]));
- int innerDimWarpNum = std::min<int>(
- ... | should we use unsigned here and on the next line ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,515 | intel | etiotto | @@ -697,58 +697,70 @@ struct StoreOpConversion
Value basePitch = mul(rowStride, elemSizeInBytes);
// A warp stride for the replicates.
- int outerDimWarpNum = std::min<int>(
- warpsPerCTA[0], mlir::ceil<unsigned>(tensorShape[0], elemsPerInstr[0]));
- int innerDimWarpNum = std::min<int>(
- ... | `offsetY` is invariant with respect to induction variable `n`. Here you could swap (interchange) loops `n` and `repM`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,515 | intel | victor-eds | @@ -697,58 +697,70 @@ struct StoreOpConversion
Value basePitch = mul(rowStride, elemSizeInBytes);
// A warp stride for the replicates.
- int outerDimWarpNum = std::min<int>(
- warpsPerCTA[0], mlir::ceil<unsigned>(tensorShape[0], elemsPerInstr[0]));
- int innerDimWarpNum = std::min<int>(
- ... | I assume we cannot fail early (no way to infer we'll be creating a bad op). Good approach in that case. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,515 | intel | etiotto | @@ -697,58 +697,70 @@ struct StoreOpConversion
Value basePitch = mul(rowStride, elemSizeInBytes);
// A warp stride for the replicates.
- int outerDimWarpNum = std::min<int>(
- warpsPerCTA[0], mlir::ceil<unsigned>(tensorShape[0], elemsPerInstr[0]));
- int innerDimWarpNum = std::min<int>(
- ... | we can remove the static_cast, do the multiplication and let the result be casted to an unsigned. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,514 | intel | etiotto | @@ -180,16 +180,20 @@ class DotOpDPASConversionHelper {
auto RC = IntegerAttr::get(rewriter.getIntegerType(32),
dpasEncoding.getRepeatCount());
- auto ret = rewriter.create<TritonGEN::MatrixDPASOp>(loc, dTy, valc, valA,
- ... | use prefix increment (consistency with other loops in this loop nest) |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,514 | intel | etiotto | @@ -226,19 +230,22 @@ class DotOpDPASConversionHelper {
Value composeValuesToDotOperandLayoutStruct(const ValueTable &vals,
int64_t dim0, int64_t dim1,
Type elemTy) const {
-
+ auto repCluster = dpasLayout.getRepCluster(... | use prefix increment |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,514 | intel | etiotto | @@ -226,19 +230,22 @@ class DotOpDPASConversionHelper {
Value composeValuesToDotOperandLayoutStruct(const ValueTable &vals,
int64_t dim0, int64_t dim1,
Type elemTy) const {
-
+ auto repCluster = dpasLayout.getRepCluster(... | auto -> Value |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,514 | intel | etiotto | @@ -226,19 +230,22 @@ class DotOpDPASConversionHelper {
Value composeValuesToDotOperandLayoutStruct(const ValueTable &vals,
int64_t dim0, int64_t dim1,
Type elemTy) const {
-
+ auto repCluster = dpasLayout.getRepCluster(... | auto -> Type |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,514 | intel | etiotto | @@ -226,19 +230,22 @@ class DotOpDPASConversionHelper {
Value composeValuesToDotOperandLayoutStruct(const ValueTable &vals,
int64_t dim0, int64_t dim1,
Type elemTy) const {
-
+ auto repCluster = dpasLayout.getRepCluster(... | auto -> Value |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,514 | intel | etiotto | @@ -248,24 +255,46 @@ class DotOpDPASConversionHelper {
return packLLElements(loc, typeConverter, elems, rewriter, structTy);
}
- ValueTable getValuesFromDotOperandLayoutStruct(Value val, int64_t dim0,
- int64_t dim1, Type elemTy,
- ... | use a switch stmt |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,514 | intel | etiotto | @@ -248,24 +255,46 @@ class DotOpDPASConversionHelper {
return packLLElements(loc, typeConverter, elems, rewriter, structTy);
}
- ValueTable getValuesFromDotOperandLayoutStruct(Value val, int64_t dim0,
- int64_t dim1, Type elemTy,
- ... | Replace last division with a multiplication. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,514 | intel | etiotto | @@ -248,24 +255,46 @@ class DotOpDPASConversionHelper {
return packLLElements(loc, typeConverter, elems, rewriter, structTy);
}
- ValueTable getValuesFromDotOperandLayoutStruct(Value val, int64_t dim0,
- int64_t dim1, Type elemTy,
- ... | use prefix increment for consistency |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,514 | intel | victor-eds | @@ -38,11 +38,11 @@ class DotOpDPASConversionHelper {
unsigned threadsPerWarp = layout.getSubGroupSize();
unsigned opsPerChannel = layout.getOpsPerChannel();
- SmallVector<unsigned> shapeC = layout.getShapeC();
+ SmallVector<unsigned> shapeC = layout.getDPASInstShapeC(); | I see we're copying `SmallVector` a lot in the file. Can we use `ArrayRef` instead? (TODO in a different PR, ofc) |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,514 | intel | etiotto | @@ -248,24 +255,55 @@ class DotOpDPASConversionHelper {
return packLLElements(loc, typeConverter, elems, rewriter, structTy);
}
- ValueTable getValuesFromDotOperandLayoutStruct(Value val, int64_t dim0,
- int64_t dim1, Type elemTy,
- ... | Should be initialized to 0u |
intel-xpu-backend-for-triton | github_2023 | others | 1,512 | intel | etiotto | @@ -0,0 +1,293 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm -canonicalize | FileCheck %s
+
+#blocked0 = #triton_gpu.blocked<{sizePerThread = [1, 8], threadsPerWarp = [2, 8], warpsPerCTA = [32, 1], order = [1, 0]}>
+#mma = #triton_intel_gpu.dpas<{repeatCou... | Some constants are not referenced so their CHECK-DAG should be removed |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,291 | intel | etiotto | @@ -101,25 +101,34 @@ Type annotatePrefetchType(Type type, unsigned numWarps) {
SmallVector<unsigned> sizePerWarp(2), warpsPerCTA(2);
int64_t m = shape[0], n = shape[1];
-
- // typical numWarps 4, 8, 16, 32, 64
- // naive way to get warp distribute
- int64_t sizeX = n < 32 ? n : 32; // elementtype
- int64_t... | Why do we need an env. variable ? Isn't skipping prefetch for small shapes always profitable ? |
intel-xpu-backend-for-triton | github_2023 | python | 1,291 | intel | etiotto | @@ -1367,9 +1367,6 @@ def _validate_dtype(dtype, allowed_types, operand_name):
assert lhs_rank == rhs_rank == 2 or lhs_rank == rhs_rank == 3, f"Both inputs must be either 2D or 3D; (lhs: {lhs.shape} vs rhs: {rhs.shape})"
assert lhs.shape[-1].value == rhs.shape[
-2].value, f"First input shape ({lhs.sh... | We cannot just remove code from files used upstream. The first question is why do we need to remove this assert ? Is it because you want to test shapes that have a small M ? If Triton consider this matmul shape invalid then I do not think we can handle it until the language remove this semantic constraint on the tl.d... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,291 | intel | whitneywhtsang | @@ -101,25 +101,34 @@ Type annotatePrefetchType(Type type, unsigned numWarps) {
SmallVector<unsigned> sizePerWarp(2), warpsPerCTA(2);
int64_t m = shape[0], n = shape[1];
-
- // typical numWarps 4, 8, 16, 32, 64
- // naive way to get warp distribute
- int64_t sizeX = n < 32 ? n : 32; // elementtype
- int64_t... | Why these need to be changed when skipping prefetch? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,291 | intel | Dewei-Wang-sh | @@ -404,14 +413,25 @@ void PrefetchBlockPass::injectPrefetchOpsInBody(
SmallVector<Value> advances;
unsigned i = 0;
+ char *envPrefetch = std::getenv("TRITON_INTEL_SKIP_PREFETCH_A");
+ const bool skipPrefetch = envPrefetch ? (bool)std::atoi(envPrefetch) : false;
+ bool isMatA = false;
Operation *prefetchI... | this pass aims to be general and not limited to gemm case unless proven necessary. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,558 | intel | whitneywhtsang | @@ -0,0 +1,60 @@
+#ifndef TRITON_ANALYSIS_INTEL_DPAS_H
+#define TRITON_ANALYSIS_INTEL_DPAS_H
+
+#include "intel/include/Dialect/TritonIntelGPU/Transforms/Utility.h"
+#include "mlir/Interfaces/FunctionInterfaces.h"
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include <cstdint>
+
+namespace mlir::triton::gpu::intel {... | Would `All` , `Some`, and `None` be useful to indicate if all/some/none of tt.dot can be lowered to DPAS instructions? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,558 | intel | whitneywhtsang | @@ -0,0 +1,116 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+using namespace mlir;
+
+namespace mlir::triton::gpu::intel {
+
+DPASAnalysis::DPASAnalysis(FunctionOpInterface func)
+ : mod(func->getParentOfType<mlir::ModuleOp>()) {
+ DeviceArch arch = getDeviceArch(... | can we check `triton_gpu.support_dpas` instead of `triton_gpu.is_lts` after https://github.com/intel/intel-xpu-backend-for-triton/pull/1565? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,558 | intel | whitneywhtsang | @@ -0,0 +1,116 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+using namespace mlir;
+
+namespace mlir::triton::gpu::intel {
+
+DPASAnalysis::DPASAnalysis(FunctionOpInterface func)
+ : mod(func->getParentOfType<mlir::ModuleOp>()) {
+ DeviceArch arch = getDeviceArch(... | We probably should change to check `sub_group_sizes` from device properties. WDYT? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,558 | intel | victor-eds | @@ -0,0 +1,60 @@
+#ifndef TRITON_ANALYSIS_INTEL_DPAS_H
+#define TRITON_ANALYSIS_INTEL_DPAS_H | ```suggestion
#ifndef TRITON_INTEL_ANALYSIS_DPAS_H
#define TRITON_INTEL_ANALYSIS_DPAS_H
```
Shouldn't it be like this? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,558 | intel | victor-eds | @@ -0,0 +1,116 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+using namespace mlir;
+
+namespace mlir::triton::gpu::intel {
+
+DPASAnalysis::DPASAnalysis(FunctionOpInterface func)
+ : mod(func->getParentOfType<mlir::ModuleOp>()) {
+ DeviceArch arch = getDeviceArch(... | Can we avoid the walk if the module does not have the `triton_gpu.support_dpas` attribute? Not populating the map should be enough. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,558 | intel | victor-eds | @@ -0,0 +1,116 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+using namespace mlir;
+
+namespace mlir::triton::gpu::intel {
+
+DPASAnalysis::DPASAnalysis(FunctionOpInterface func)
+ : mod(func->getParentOfType<mlir::ModuleOp>()) {
+ DeviceArch arch = getDeviceArch(... | Cache to avoid querying in `if` statement below. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,558 | intel | victor-eds | @@ -0,0 +1,116 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+using namespace mlir;
+
+namespace mlir::triton::gpu::intel {
+
+DPASAnalysis::DPASAnalysis(FunctionOpInterface func)
+ : mod(func->getParentOfType<mlir::ModuleOp>()) {
+ DeviceArch arch = getDeviceArch(... | ```suggestion
if (llvm::any_of(dpasMap, [](const auto &entry) {
return entry.second == DPASEngineType::NOT_APPLICABLE;
}))
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,558 | intel | victor-eds | @@ -0,0 +1,116 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+using namespace mlir;
+
+namespace mlir::triton::gpu::intel {
+
+DPASAnalysis::DPASAnalysis(FunctionOpInterface func)
+ : mod(func->getParentOfType<mlir::ModuleOp>()) {
+ DeviceArch arch = getDeviceArch(... | Can we move this check to the constructor to avoid the walk in the worst-case scenario? |
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