repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | python | 1,092 | intel | chengjunlu | @@ -0,0 +1,277 @@
+"""
+Block Pointer (Experimental)
+============================
+This tutorial will guide you through writing a matrix multiplication algorithm that utilizes block pointer semantics.
+These semantics are more friendly for Triton to optimize and can result in better performance on specific hardware.
+... | Change the warm up number and rep number to 10 |
intel-xpu-backend-for-triton | github_2023 | python | 1,092 | intel | chengjunlu | @@ -38,6 +38,31 @@ def naive_softmax(x):
return ret
+@triton.autotune(
+ configs=[
+ triton.Config({'BLOCK_SIZE': 128}, num_warps=32),
+ triton.Config({'BLOCK_SIZE': 256}, num_warps=32),
+ triton.Config({'BLOCK_SIZE': 512}, num_warps=32),
+ triton.Config({'BLOCK_SIZE': 1024}, num... | Please add the "BLOCK_SIZE" into the key. We should use different configuration based on different problem size used in the softmax. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,092 | intel | chengjunlu | @@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2020, Intel Corporation | Remove this file. We don't use the cm_kernel. |
intel-xpu-backend-for-triton | github_2023 | python | 1,092 | intel | chengjunlu | @@ -70,23 +95,19 @@ def softmax(x):
# increasing the number of warps (`num_warps`) over which each row is distributed.
# You will see in the next tutorial how to auto-tune this value in a more natural
# way so you don't have to come up with manual heuristics yourself.
- num_warps = 4
- if BLOCK_SIZ... | Remove the commented out code. |
intel-xpu-backend-for-triton | github_2023 | python | 1,092 | intel | chengjunlu | @@ -0,0 +1,277 @@
+""" | Change the file name. gemm_benchmark.py |
intel-xpu-backend-for-triton | github_2023 | python | 1,092 | intel | chengjunlu | @@ -38,6 +38,31 @@ def naive_softmax(x):
return ret
+@triton.autotune(
+ configs=[
+ triton.Config({'BLOCK_SIZE': 128}, num_warps=32),
+ triton.Config({'BLOCK_SIZE': 256}, num_warps=32),
+ triton.Config({'BLOCK_SIZE': 512}, num_warps=32),
+ triton.Config({'BLOCK_SIZE': 1024}, num... | Opps. My bad. It should be `n_cols`. The `BLOCK_SIZE` is an autotune configuration based on the `n_cols` |
intel-xpu-backend-for-triton | github_2023 | others | 1,489 | intel | whitneywhtsang | @@ -89,7 +93,35 @@ jobs:
- name: Get LLVM commit id
run: |
LLVM_COMMIT_ID=$(<cmake/llvm-hash.txt)
- echo "LLVM_COMMIT_ID=$LLVM_COMMIT_ID" >> $GITHUB_ENV
+ echo "LLVM_COMMIT_ID=$LLVM_COMMIT_ID" | tee -a $GITHUB_ENV
+
+ - name: Load LLVM cache
+ id: llvm-cache
+ ... | compile-triton.sh build intel/llvm genx branch, should we change that to build community llvm at the commit specified by cmake/llvm-hash.txt? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,407 | intel | etiotto | @@ -507,88 +507,114 @@ createBlock2DReadWithAddressPayloadUpdate(TritonGEN::Matrix2DBlockLoadOp op,
return createBlock2DRead(ptr, op);
}
+static SmallVector<Attribute>
+storeCacheControlToDecoration(Builder &builder, uint32_t operandNum,
+ TritonGEN::StoreCacheControl orig) {
+ const... | we have to evaluate whether setting the write-only/read-only attributes preempt optimizations in the experimental path. |
intel-xpu-backend-for-triton | github_2023 | others | 1,475 | intel | gshimansky | @@ -53,16 +53,6 @@ env:
TORCH_XPU_OPS_COMMIT: 39522db63ce045f52c9d61a286018c266cd00479
jobs:
- print_inputs:
- name: Print inputs
- runs-on: Linux
- steps:
- - name: Print inputs
- run: |
- cat <<EOF
- ${{ toJSON(inputs) }}
- EOF
- | Why not move this command inside of integration-tests job? |
intel-xpu-backend-for-triton | github_2023 | others | 1,475 | intel | leshikus | @@ -250,6 +246,7 @@ jobs:
- name: Pass rate
run: |
+ source ./scripts/capture-hw-details.sh | the script captures more than hw details; probably have to be renamed to `capture-configuration-details.sh` at some point |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,428 | intel | etiotto | @@ -480,4 +480,38 @@ LogicalResult TritonRaiseBlockPointer::visitAddPointerOperand(
return success();
}
+
+template <>
+LogicalResult
+TritonRaiseBlockPointer::visitAddPointerOperand(triton::BroadcastOp broadcastOp,
+ PtrState &state, Location loc,
+ ... | Add assert msg |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,402 | intel | mfrancepillois | @@ -349,4 +339,143 @@ struct TritonRaiseBlockPointer
llvm::SmallDenseMap<Value, PtrState> knownPtrs;
IRMapping ptrMap;
};
+
+template <>
+LogicalResult
+TritonRaiseBlockPointer::visitAddPointerOperand(triton::MakeRangeOp rangeOp, | It seems to me that
`template <>
LogicalResult visitOperand(...)`
is probably a better name for this function than
`template <>
LogicalResult
visitAddPointerOperand(...)`
which suggest that it is a visitor to the `triton::AddPtrOp` operation. |
intel-xpu-backend-for-triton | github_2023 | others | 1,402 | intel | etiotto | @@ -68,3 +68,90 @@ tt.func @test_addptr_splat_splat_2d(%arg0 : !tt.ptr<f32>, %arg1: i64, %arg2: ten
%3 = tt.load %2, %arg2, %arg3 : tensor<2x128x!tt.ptr<f32>>
tt.return %3 : tensor<2x128xf32>
}
+
+// CHECK-LABEL: tt.func @test_addptr_splat_splat_2d_store(
+// CHECK-SAME: ... | [nit]: `test_addptr_splat_const` -> `test_const_splat_addptr` |
intel-xpu-backend-for-triton | github_2023 | others | 1,402 | intel | etiotto | @@ -68,3 +68,90 @@ tt.func @test_addptr_splat_splat_2d(%arg0 : !tt.ptr<f32>, %arg1: i64, %arg2: ten
%3 = tt.load %2, %arg2, %arg3 : tensor<2x128x!tt.ptr<f32>>
tt.return %3 : tensor<2x128xf32>
}
+
+// CHECK-LABEL: tt.func @test_addptr_splat_splat_2d_store(
+// CHECK-SAME: ... | ditto |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,402 | intel | etiotto | @@ -223,115 +269,215 @@ struct TritonRaiseBlockPointer
return success();
}
- if (Operation *definingOp = operand.getDefiningOp()) {
- if (auto op = dyn_cast<triton::MakeRangeOp>(definingOp))
- return visitOperandMakeRange(op, state, loc, builder);
- if (auto op = dyn_cast<triton::Splat... | [nit]: just capture with "&"? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,402 | intel | etiotto | @@ -223,115 +269,215 @@ struct TritonRaiseBlockPointer
return success();
}
- if (Operation *definingOp = operand.getDefiningOp()) {
- if (auto op = dyn_cast<triton::MakeRangeOp>(definingOp))
- return visitOperandMakeRange(op, state, loc, builder);
- if (auto op = dyn_cast<triton::Splat... | Add assert msg |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,402 | intel | etiotto | @@ -223,115 +269,215 @@ struct TritonRaiseBlockPointer
return success();
}
- if (Operation *definingOp = operand.getDefiningOp()) {
- if (auto op = dyn_cast<triton::MakeRangeOp>(definingOp))
- return visitOperandMakeRange(op, state, loc, builder);
- if (auto op = dyn_cast<triton::Splat... | Add assert msg |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,402 | intel | etiotto | @@ -223,115 +269,215 @@ struct TritonRaiseBlockPointer
return success();
}
- if (Operation *definingOp = operand.getDefiningOp()) {
- if (auto op = dyn_cast<triton::MakeRangeOp>(definingOp))
- return visitOperandMakeRange(op, state, loc, builder);
- if (auto op = dyn_cast<triton::Splat... | Add assert msg, also below |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,402 | intel | etiotto | @@ -223,115 +269,215 @@ struct TritonRaiseBlockPointer
return success();
}
- if (Operation *definingOp = operand.getDefiningOp()) {
- if (auto op = dyn_cast<triton::MakeRangeOp>(definingOp))
- return visitOperandMakeRange(op, state, loc, builder);
- if (auto op = dyn_cast<triton::Splat... | Add assert msg |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,441 | intel | chengjunlu | @@ -209,9 +213,16 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
DpasEncodingAttr dpasLayout =
dyn_cast<DpasEncodingAttr>(D.getType().getEncoding());
if (dpasLayout) {
+
+ bool isNativeFP8 = AElType.isFloat8E5M2() || AElType.isFloat8E4M3FNUZ();
+
// No operands promotion because o... | Update the comments here correspondingly. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,441 | intel | whitneywhtsang | @@ -209,9 +213,16 @@ static void decomposeMixedModeDotOp(ModuleOp mod) {
DpasEncodingAttr dpasLayout =
dyn_cast<DpasEncodingAttr>(D.getType().getEncoding());
if (dpasLayout) {
+
+ bool isNativeFP8 = AElType.isFloat8E5M2() || AElType.isFloat8E4M3FNUZ();
+
// No operands promotion because o... | Please make it similar to the common file, something like...
```
bool isNativeFP8 = AElType.isFloat8E5M2() || AElType.isFloat8E4M3FNUZ();
// promote operands since fp8 DPAS is not natively supported.
if (!isNativeFP8)
return;
promoteType = builder.getF16Type();
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,441 | intel | whitneywhtsang | @@ -73,6 +73,10 @@ bool shouldRemove(tt::MakeTensorPtrOp &op, ttgi::DeviceArch deviceArch,
!(isUsedByStoreOp && ttgi::hasDpasEncoding(tensorType)))
return true;
+ // FIXME: Temporary workaround to avoid
+ // compile error on fp8 2d block read
+ if (tensorType.getElementTypeBitWidth() == 8) | Is 2D block read for int8 GEMM also avoided with this workaround?
Any way we can only avoid fp8 and not int8? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,435 | intel | etiotto | @@ -447,6 +447,12 @@ struct LoadOpConversion
/*transpose*/ false,
/*vnni_transform*/
(!isOperandA && eltTy.getIntOrFloatBitWidth() != 32));
+ load2dOp->dump(); | Remove left over trace |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,193 | intel | FMarno | @@ -138,6 +138,12 @@ bool hasDotDpasEncoding(RankedTensorType tensorType) {
return isa<ttgi::DpasEncodingAttr>(dotLayout.getParent());
}
+bool hasDpasEncoding(RankedTensorType tensorType) {
+ if (auto Enc = tensorType.getEncoding()) | I don't think `Enc` follows the style, maybe `enc` or better yet imo `encoding`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,193 | intel | FMarno | @@ -54,6 +54,7 @@ bool isDivisible(Value value, unsigned divisor) {
/// removed if:
/// - the device architecture is not PVC
/// - the tensor pointer does not have DotEncoding with DpasEncoding parent
+/// and not have a DpasEncoding | ```suggestion
/// and does not have DpasEncoding
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,193 | intel | FMarno | @@ -729,10 +731,15 @@ class TritonIntelGPURewriteTensorPointerPass
} else if (llvm::isa<tt::AdvanceOp, tt::LoadOp>(op)) {
markTensorPointerForRemoval(op->getOperand(0));
} else if (llvm::isa<tt::StoreOp>(op)) {
- // TODO: Block store should not be removed when 2d store is enabled
... | ```suggestion
auto makeTensorPtrOp = src.getDefiningOp<tt::MakeTensorPtrOp>();
if (!makeTensorPtrOp || shouldRemove(makeTensorPtrOp, arch)) {
valueToRemove.insert(src);
}
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,193 | intel | chengjunlu | @@ -1,10 +1,78 @@
// RUN: triton-opt %s -split-input-file -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// COM: Case 0:
+// COM: Check that operations using block pointers satisfying the following conditions are not rewritten:
+// COM: - the block pointer has the "dot" layout attribute (with dpas parent lay... | From the experience, the row major order is just `strides[1]==1`, which for 2D case, for general case should be `strides[-1]==1`.
Check the use case here of the `order`.
https://github.com/intel/intel-xpu-backend-for-triton/blob/da631c7b442151182ff4f395193e75df15dcc2ea/python/triton/ops/flash_attention.py#L47 |
intel-xpu-backend-for-triton | github_2023 | others | 1,193 | intel | chengjunlu | @@ -1,10 +1,78 @@
// RUN: triton-opt %s -split-input-file -tritonintelgpu-rewrite-tensor-pointer | FileCheck %s
+// COM: Case 0:
+// COM: Check that operations using block pointers satisfying the following conditions are not rewritten:
+// COM: - the block pointer has the "dot" layout attribute (with dpas parent lay... | The row stride should be `strides[0]` which for 2D case, for general case should be `strides[-2]`. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,193 | intel | LiyangLingIntel | @@ -729,10 +731,12 @@ class TritonIntelGPURewriteTensorPointerPass
} else if (llvm::isa<tt::AdvanceOp, tt::LoadOp>(op)) {
markTensorPointerForRemoval(op->getOperand(0));
} else if (llvm::isa<tt::StoreOp>(op)) {
- // TODO: Block store should not be removed when 2d store is enabled
... | We can remove the `tt::StoreOp` condition and add it to `LoadOp` case,
```cpp
} else if (llvm::isa<tt::AdvanceOp, tt::LoadOp, tt::StoreOp>(op)) {
markTensorPointerForRemoval(op->getOperand(0));
}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,193 | intel | whitneywhtsang | @@ -138,6 +138,12 @@ bool hasDotDpasEncoding(RankedTensorType tensorType) {
return isa<ttgi::DpasEncodingAttr>(dotLayout.getParent());
}
+bool hasDpasEncoding(RankedTensorType tensorType) {
+ if (auto encoding = tensorType.getEncoding())
+ return isa<ttgi::DpasEncodingAttr>(encoding);
+ return false; | ```suggestion
return isa_and_nonnull<ttgi::DpasEncodingAttr>(tensorType.getEncoding());
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,193 | intel | etiotto | @@ -717,19 +718,32 @@ class TritonIntelGPURewriteTensorPointerPass
ttgi::DeviceArch arch = ttgi::getDeviceArch(mod);
- auto markTensorPointerForRemoval = [this, arch](Value val) {
- if (tt::isTensorPointerType(val.getType())) {
- tt::MakeTensorPtrOp makeTensorPtrOp = getMakeTensorPtrOp(val);
- ... | This is a bit more readable.
[Suggestion]:
```
auto usedByStoreOp = [](Value val) {
return llvm::any_of(val.getUsers(), [](Operation *user){ return isa<tt.StoreOp>(user); });
}; |
intel-xpu-backend-for-triton | github_2023 | others | 1,419 | intel | leshikus | @@ -0,0 +1,259 @@
+name: Build and test reusable workflow
+run-name: ${{ inputs.run_name }} - ${{ inputs.python_version }} - ${{ inputs.install_ipex && 'IPEX' || 'no IPEX' }} - ${{ inputs.runner_label || 'default'}}
+
+on:
+ workflow_call:
+ inputs:
+ driver_version:
+ description: Driver version
+ ... | this is not a good place for this TODO, the tests come from developers, and they do not read our workflows; I believe it's better to file it as issue and assign to @etiotto |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,396 | intel | FMarno | @@ -300,30 +301,46 @@ struct TritonRaiseBlockPointer
return success();
}
- LogicalResult rewriteLoadOp(triton::LoadOp op) {
+ template <typename OpTy, typename = std::enable_if_t<llvm::is_one_of<
+ OpTy, triton::LoadOp, triton::StoreOp>::value>>
+ LogicalResult rewriteLoadStor... | are you missing the `replaceAllUsesWith` in the store branch? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,396 | intel | etiotto | @@ -303,30 +304,46 @@ struct TritonRaiseBlockPointer
return success();
}
- LogicalResult rewriteLoadOp(triton::LoadOp op) {
+ template <typename OpTy, typename = std::enable_if_t<llvm::is_one_of<
+ OpTy, triton::LoadOp, triton::StoreOp>::value>>
+ LogicalResult rewriteLoadStor... | Cool use of [[maybe_unused]] (to silence warning when DEBUG is not on). |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,396 | intel | etiotto | @@ -303,30 +304,46 @@ struct TritonRaiseBlockPointer
return success();
}
- LogicalResult rewriteLoadOp(triton::LoadOp op) {
+ template <typename OpTy, typename = std::enable_if_t<llvm::is_one_of<
+ OpTy, triton::LoadOp, triton::StoreOp>::value>> | Nice ! |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,401 | intel | whitneywhtsang | @@ -1241,6 +1241,11 @@ struct TritonMatrix2DBlockPrefetchLowering
LogicalResult
matchAndRewrite(TritonGEN::Matrix2DBlockPrefetchOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
+ // FIXME: Remove explict verification again if
+ // `-convert-triton-intel-gpu-... | Can we add one for 2DBlockLoad as well? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,401 | intel | victor-eds | @@ -1241,6 +1241,11 @@ struct TritonMatrix2DBlockPrefetchLowering
LogicalResult
matchAndRewrite(TritonGEN::Matrix2DBlockPrefetchOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
+ // FIXME: Remove explict verification again if
+ // `-convert-triton-intel-gpu-... | Here we're verifying the operation legality *after* creating it in the pattern lowering it. Cannot we make sure we do not create it that way in the first place, e.g., by failing the pattern creating the illegal op? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,401 | intel | victor-eds | @@ -1241,6 +1241,11 @@ struct TritonMatrix2DBlockPrefetchLowering
LogicalResult
matchAndRewrite(TritonGEN::Matrix2DBlockPrefetchOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
+ // FIXME: Remove explict verification again if
+ // `-convert-triton-intel-gpu-... | If this takes place, we would end up in a situation in which code does not verify and compilation fails, that's why I prefer not generating the illegal operation in the first place. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,401 | intel | Dewei-Wang-sh | @@ -514,7 +514,8 @@ MatchTargetSizePass::getSubOpSize(RankedTensorType type) const {
case 2: {
if (isa<ttgi::WarpEncodingAttr>(layout)) {
// 32 = 2 * 16(subgroupSize) which is for large load/store
- subSize[1] = std::min(32L, shape[1]);
+ // max 2d block prefetch width is 16 for 32-bit datatype... | from this line, it seems we can not tell whether it's prefetch or load.
does load2d has the same constraint? |
intel-xpu-backend-for-triton | github_2023 | others | 1,401 | intel | etiotto | @@ -0,0 +1,13 @@
+// RUN: TRITON_INTEL_ENABLE_BLOCK_PTR=1 triton-opt %s --convert-triton-intel-gpu-to-llvm --verify-diagnostics
+
+module attributes {"triton_gpu.num-warps" = 32 : i32, "triton_gpu.threads-per-warp" = 16 : i32} {
+ tt.func public @matmul_kernel_with_block_pointers(%arg0: !tt.ptr<f32>, %arg1: i64, %arg2... | The msg doesn't quite read correctly. Change: "should be equal to either be 8 or 16" to "should be either 8 or 16 |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,401 | intel | etiotto | @@ -319,6 +319,11 @@ struct PrefetchOpConversion
/*tile_height*/ tileHeightInElem,
/*v_blocks*/ 1,
/*cache_opt*/ TritonGEN::LoadCacheControl::L1C_L3C);
+ if (failed(newOp.verify())) { | Hmmm this is not ideal but you explain the reason so is OK. At some point we should "unravel" the huge pass that lower to LLVM dialect into individual passes. That would make each pass easier to debug as well as preempting the need to verify explicitly like here. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,395 | intel | etiotto | @@ -123,9 +123,17 @@ struct TritonRaiseBlockPointer
using Base::Base;
void runOnOperation() final {
- getOperation()->walk([this](triton::AddPtrOp addptr) {
- if (failed(rewriteAddPtrOp(addptr)))
- addptr->emitRemark("TritonRaiseToBlockPointer: Failed to rewrite");
+ getOperation()->walk([this... | if we change a ptr to a block pointer don't we also need to rewrite stores ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,395 | intel | etiotto | @@ -293,6 +301,34 @@ struct TritonRaiseBlockPointer
return success();
}
+ LogicalResult rewriteLoadOp(triton::LoadOp op) {
+ auto ptr = ptrMap.lookupOrNull(op.getPtr());
+
+ if (!ptr) {
+ op->emitRemark("TritonRaiseBlockPointer: pointer is not replace with " | replace -> replaced |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,405 | intel | etiotto | @@ -236,17 +221,24 @@ LogicalResult TritonGEN::Matrix2DBlockStoreOp::verify() {
if (verifyMatrixInput(*this).failed())
return failure();
- if (verifyMatrixTransposeTransform(*this).failed())
- return failure();
-
- if (getElemSizeInBits() == 8 && !getVnniTransform())
- if (getTileWidth() != 32)
- ... | add unreachable default |
intel-xpu-backend-for-triton | github_2023 | python | 1,387 | intel | victor-eds | @@ -1377,8 +1377,11 @@ def _validate_dtype(dtype, allowed_types, operand_name):
_0 = builder.get_int32(0)
ret_scalar_ty = tl.int32
elif out_dtype.is_bf16():
- raise ValueError(
- "out_dtype=bfloat16 is unsupported. Please use out_dtype=float32/float16 and cast with `.to(tl.bfloa... | Do we have access access to that info here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,387 | intel | victor-eds | @@ -172,28 +170,46 @@ static LLVM::CallOp createGenISADPAS(TritonGEN::MatrixDPASOp op,
if (bOrigTy != bTy)
b = rewriter.create<LLVM::BitcastOp>(loc, bTy, b);
+ Value c = op.getC();
+ VectorType cOrigTy = cast<VectorType>(c.getType());
+ assert(cOrigTy == op->getResultTypes()[0] &&
+ "Accumulator an... | ```suggestion
std::array argTypes{aTy, bTy, cTy};
std::array args{a, b, c};
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,387 | intel | whitneywhtsang | @@ -1124,8 +1140,8 @@ struct TritonMatrixDPASLowering
LogicalResult
matchAndRewrite(TritonGEN::MatrixDPASOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
- LLVM::CallOp callOp = createGenISADPAS(op, rewriter);
- rewriter.replaceOp(op, callOp);
+ Value cal... | ```suggestion
rewriter.replaceOp(op, createGenISADPAS(op, rewriter));
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,387 | intel | whitneywhtsang | @@ -1377,8 +1377,11 @@ def _validate_dtype(dtype, allowed_types, operand_name):
_0 = builder.get_int32(0)
ret_scalar_ty = tl.int32
elif out_dtype.is_bf16():
- raise ValueError(
- "out_dtype=bfloat16 is unsupported. Please use out_dtype=float32/float16 and cast with `.to(tl.bfloa... | Can we ask in Triton slack channel to see if that's something they are opened to enable? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,400 | intel | etiotto | @@ -689,22 +689,31 @@ struct StoreOpConversion
// encoded as bytes.
Value basePitch = mul(rowStride, elemSizeInBytes);
- // A dense stride for the replicates.
+ // A warp stride for the replicates.
+ int outerDimWarpNum = std::min<int>(
+ warpsPerCTA[0], mlir::ceil<unsigned>(tensorShape[0], ... | use static_cast rather than C style cast |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,390 | intel | mfrancepillois | @@ -0,0 +1,298 @@
+//===----------------------------------------------------------------------===//
+//
+// Copyright (c) Microsoft Corporation, Meta Platforms.
+// Licensed under the MIT license.
+//
+//===----------------------------------------------------------------------===//
+
+#include "intel/include/TritonRais... | Could the name reflect the fact there are bit-width? For me the term "Width" is a bit confusing. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,390 | intel | etiotto | @@ -0,0 +1,299 @@
+//===----------------------------------------------------------------------===//
+//
+// Copyright (c) Microsoft Corporation, Meta Platforms.
+// Licensed under the MIT license.
+//
+//===----------------------------------------------------------------------===//
+
+#include "intel/include/TritonRais... | typo: offsets -> Offsets |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,390 | intel | etiotto | @@ -0,0 +1,299 @@
+//===----------------------------------------------------------------------===//
+//
+// Copyright (c) Microsoft Corporation, Meta Platforms.
+// Licensed under the MIT license.
+//
+//===----------------------------------------------------------------------===//
+
+#include "intel/include/TritonRais... | auto -> Location |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,390 | intel | etiotto | @@ -0,0 +1,299 @@
+//===----------------------------------------------------------------------===//
+//
+// Copyright (c) Microsoft Corporation, Meta Platforms.
+// Licensed under the MIT license.
+//
+//===----------------------------------------------------------------------===//
+
+#include "intel/include/TritonRais... | auto -> size_t ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,390 | intel | etiotto | @@ -0,0 +1,299 @@
+//===----------------------------------------------------------------------===//
+//
+// Copyright (c) Microsoft Corporation, Meta Platforms.
+// Licensed under the MIT license.
+//
+//===----------------------------------------------------------------------===//
+
+#include "intel/include/TritonRais... | this is fine but in other places we use `const Type *` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,390 | intel | etiotto | @@ -0,0 +1,299 @@
+//===----------------------------------------------------------------------===//
+//
+// Copyright (c) Microsoft Corporation, Meta Platforms.
+// Licensed under the MIT license.
+//
+//===----------------------------------------------------------------------===//
+
+#include "intel/include/TritonRais... | this can be an if statement (drop the `else`) given that the "then" branch returns |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,390 | intel | whitneywhtsang | @@ -0,0 +1,299 @@
+//===----------------------------------------------------------------------===//
+//
+// Copyright (c) Microsoft Corporation, Meta Platforms.
+// Licensed under the MIT license.
+//
+//===----------------------------------------------------------------------===//
+
+#include "intel/include/TritonRais... | [optional]
```suggestion
offsets.size() == shape.size());
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,390 | intel | whitneywhtsang | @@ -0,0 +1,299 @@
+//===----------------------------------------------------------------------===//
+//
+// Copyright (c) Microsoft Corporation, Meta Platforms.
+// Licensed under the MIT license.
+//
+//===----------------------------------------------------------------------===//
+
+#include "intel/include/TritonRais... | Please change all postincrement to preincrement.
```suggestion
for (uint64_t i = 0; i < lhsState.getRank(); ++i) {
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,390 | intel | Dewei-Wang-sh | @@ -0,0 +1,30 @@
+//===-- Passes.td - Triton to Block Pointer Passes ---------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---... | ```suggestion
pointers (`tensor<...x!tt.ptr<ty>>`) to pointer to tensors
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,388 | intel | pbchekin | @@ -106,13 +106,6 @@ runs:
wget https://raw.githubusercontent.com/intel/torch-xpu-ops/main/.github/scripts/apply_torch_pr.py
python apply_torch_pr.py --pr-list https://github.com/pytorch/pytorch/pull/124147 --pr-list https://github.com/pytorch/pytorch/pull/126516
- # FIXME: Old PyTorch does not w... | I would recommend keeping this in the workflow, since we usually build/install PyTorch before Triton and PyTorch does not have any constraints for numpy (https://github.com/pytorch/pytorch/blob/main/requirements.txt#L5). Also the change in setup.py is only for `test` and we do not always install `triton[test]` in our w... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,379 | intel | chengjunlu | @@ -217,6 +208,11 @@ LogicalResult TritonGEN::Matrix2DBlockLoadOp::verify() {
<< " bits does not match the expected size of "
<< expectedSize << " bits";
+ if (getElemSizeInBits() == 8 && !getVnniTransform()) | For the prefetching ops in the TritonGen dialect, even the 2D load/store ops, I think it would be better we can decouple it with the DPAS.
Especially for the prefetching op semantic, the register layout attributes is meaningless because the op itself doesn't return the register value.
We can remove the register l... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,379 | intel | chengjunlu | @@ -67,18 +67,9 @@ template <typename Op> static LogicalResult verifyMatrixInput(Op op) {
return success();
}
- switch (op.getElemSizeInBits()) {
- case 16:
- if (tileWidth != 16)
- return op->emitOpError("tile_width for 16 bit elements should be equal "
- "to systolic de... | The better we can just verify whether the attribute is valid for the HW limitation.
Report the error like: `The total bytes number cannot exceed 64 per row for 2D block load/store.` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,379 | intel | victor-eds | @@ -228,9 +224,14 @@ LogicalResult TritonGEN::Matrix2DBlockStoreOp::verify() {
if (verifyMatrixInput(*this).failed())
return failure();
+ if (getElemSizeInBits() == 8 && !getVnniTransform())
+ if (getTileWidth() != 32)
+ return emitOpError("tile_width for 8 bit elements should be equal "
+ ... | Should we add that this error is conditioned by the `vnni_transform` value in the error message? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,379 | intel | victor-eds | @@ -591,13 +591,86 @@ createGenISA2DBlockWrite(TritonGEN::Matrix2DBlockStoreOp op,
return callOp;
}
+static bool isOCLBuiltinAvailable(TritonGEN::Matrix2DBlockPrefetchOp op) {
+ // FIXME: Incorrect usages of | Question: What "incorrect usages" are we talking about here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,379 | intel | victor-eds | @@ -591,13 +591,86 @@ createGenISA2DBlockWrite(TritonGEN::Matrix2DBlockStoreOp op,
return callOp;
}
+static bool isOCLBuiltinAvailable(TritonGEN::Matrix2DBlockPrefetchOp op) {
+ // FIXME: Incorrect usages of
+ // intel_sub_group_2d_block_prefetch_32b_2r32x1c,
+ // intel_sub_group_2d_block_prefetch_32b_4r32x1c ... | So this is an IGC bug, if I understand well |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,379 | intel | victor-eds | @@ -591,13 +591,86 @@ createGenISA2DBlockWrite(TritonGEN::Matrix2DBlockStoreOp op,
return callOp;
}
+static bool isOCLBuiltinAvailable(TritonGEN::Matrix2DBlockPrefetchOp op) {
+ // FIXME: Incorrect usages of
+ // intel_sub_group_2d_block_prefetch_32b_2r32x1c,
+ // intel_sub_group_2d_block_prefetch_32b_4r32x1c ... | ```suggestion
std::array argTypes{ptr_ty(context, 1), i32_ty, i32_ty, i32_ty,
vecType};
std::array args{op.getPtr(), op.getBaseWidth(), op.getBaseHeight(),
op.getBasePitch(), byteCoord};
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,379 | intel | etiotto | @@ -5,7 +5,7 @@ module attributes {"triton_gpu.num-warps" = 32 : i32, "triton_gpu.threads-per-wa
// CHECK-DAG: llvm.func spir_funccc @_Z38intel_sub_group_f16_f16_matrix_mad_k16Dv8_sDv8_iDv8_f(vector<8xi16>, vector<8xi32>, vector<8xf32>) -> vector<8xf32> attributes {passthrough = ["convergent"]}
// CHECK-DAG: llvm... | is llvm.readonly redundant ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,379 | intel | etiotto | @@ -591,13 +591,86 @@ createGenISA2DBlockWrite(TritonGEN::Matrix2DBlockStoreOp op,
return callOp;
}
+static bool isOCLBuiltinAvailable(TritonGEN::Matrix2DBlockPrefetchOp op) {
+ // FIXME: Incorrect usages of
+ // intel_sub_group_2d_block_prefetch_32b_2r32x1c,
+ // intel_sub_group_2d_block_prefetch_32b_4r32x1c ... | I'd remove this one because the memory semantic are described by the function attribute. |
intel-xpu-backend-for-triton | github_2023 | python | 1,355 | intel | vlad-penkin | @@ -0,0 +1,94 @@
+import argparse
+import os
+import uuid
+import json
+import datetime
+
+import pandas as pd
+
+
+host_info = {
+ n: os.getenv(n.upper(), default="")
+ for n in ["libigc1_version", "level_zero_version", "gpu_device", "agama_version"]
+}
+assert host_info['gpu_device'], "Could not find GPU device... | Can we move this code block to the main function body? |
intel-xpu-backend-for-triton | github_2023 | python | 1,355 | intel | vlad-penkin | @@ -0,0 +1,94 @@
+import argparse
+import os
+import uuid
+import json
+import datetime
+
+import pandas as pd
+
+
+host_info = {
+ n: os.getenv(n.upper(), default="")
+ for n in ["libigc1_version", "level_zero_version", "gpu_device", "agama_version"]
+}
+assert host_info['gpu_device'], "Could not find GPU device... | Is this argument required? |
intel-xpu-backend-for-triton | github_2023 | others | 1,374 | intel | vlad-penkin | @@ -0,0 +1,50 @@
+# Release Process
+
+Intel XPU Backend for Triton releases are aligned to the upstream `triton-lang/triton` project and to `PyTorch`. To make a release:
+
+1. Select a commit common to upstream [Triton](https://github.com/triton-lang/triton). Often this commit will be selected by PyTorch at [`pytorch/... | Shall we follow OpenAI release branch naming convention - `release/X.Y.Z` ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,247 | intel | whitneywhtsang | @@ -245,12 +245,60 @@ static bool isOCLBuiltinAvailable(TritonGEN::Matrix2DBlockLoadOp op) {
if (op.getVBlocks() != 2)
return false;
- if (op.getCacheControl() != TritonGEN::LoadCacheControl::DEFAULT)
- return false;
-
return true;
}
+static SmallVector<Attribute>
+loadCacheControlToDecoration(Build... | on PVC, SPIRV cache level 0 maps to L1 and cache level 1 maps to L3.
```suggestion
0, l1, operandNum),
builder.getAttr<TritonGEN::LoadCacheControlDecorationAttr>(
1, l3, operandNum)};
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,247 | intel | jopperm | @@ -367,16 +367,152 @@ llvm.func @triton_gen.dpas.f32(%c : vector<8xf32>, %a : vector<4xf32>, %b : vect
// -----
-// CHECK: llvm.func spir_funccc @intel_subgroup_block_read_u8_m8k32v2(!llvm.ptr<1>, i32, i32, i32, vector<2xi32>) -> vector<16xi16> attributes {passthrough = ["convergent"]}
+// CHECK: llvm.func spir_f... | `SIXTEEN`, or maybe just give this variable a speaking name. |
intel-xpu-backend-for-triton | github_2023 | others | 1,247 | intel | jopperm | @@ -367,16 +367,152 @@ llvm.func @triton_gen.dpas.f32(%c : vector<8xf32>, %a : vector<4xf32>, %b : vect
// -----
-// CHECK: llvm.func spir_funccc @intel_subgroup_block_read_u8_m8k32v2(!llvm.ptr<1>, i32, i32, i32, vector<2xi32>) -> vector<16xi16> attributes {passthrough = ["convergent"]}
+// CHECK: llvm.func spir_f... | This seems to be the same (or at least similar) in all added testcases; can you condense the tests into a single function that only check the difference `2Dblockload` variants? |
intel-xpu-backend-for-triton | github_2023 | others | 1,247 | intel | whitneywhtsang | @@ -297,16 +297,152 @@ llvm.func @triton_gen.dpas.f32(%c : vector<8xf32>, %a : vector<4xf32>, %b : vect
// -----
-// CHECK: llvm.func spir_funccc @intel_subgroup_block_read_u8_m8k32v2(!llvm.ptr<1> {llvm.nonnull}, i32, i32, i32, vector<2xi32>) -> vector<16xi16> attributes {passthrough = ["nounwind", ["memory", "1"]... | Let's only test the full codegen in the first test.
```suggestion
llvm.func @triton_gen.2Dblockload(%ptr : !llvm.ptr<1>, %base_width : i32, %base_height : i32, %base_pitch : i32, %x : i32, %y : i32) {
// CHECK: llvm.call spir_funccc @_Z40intel_sub_group_2d_block_read_8b_8r32x2cPU3AS1viiiDv2_iPt(%arg0, %arg1, %arg2... |
intel-xpu-backend-for-triton | github_2023 | others | 1,358 | intel | leshikus | @@ -44,10 +44,24 @@ pytest() {
}
run_tutorial_test() {
- echo
- echo "****** Running $1 test ******"
- echo
- python3 -u "$1.py" || $TRITON_TEST_IGNORE_ERRORS
+ echo
+ echo "****** Running $1 test ******"
+ echo
+
+ if python3 -u "$1.py"; then
+ TUTORIAL_RESULT=PASS
+ else
+ TUTORIA... | 1) one should avoid using boolean variables in conditionals like `if xxx = true` because `if xxx` does the same;
here are two booleans `$TRITON_TEST_IGNORE_ERRORS` and `$TRITON_TEST_REPORTS`
2) `TUTORIAL_RESULT` can also be boolean; just use `TUTORIAL_RESULT_SUCCESFULL` instead, this will simplify conditionals more
... |
intel-xpu-backend-for-triton | github_2023 | others | 1,330 | intel | gshimansky | @@ -12,29 +12,41 @@ inputs:
repository:
description: Repository name with owner
default: Stonepia/pytorch
- commit_id:
- description: Commit id of PyTorch repository
+ ref:
+ description: Branch, tag, commit id
default: ""
torch_xpu_ops_commit:
description: Commit id of third_party/xpu... | Is it possible to move this constant outside of bash code to `env` section or default parameter value for easier modification when necessary. |
intel-xpu-backend-for-triton | github_2023 | others | 1,330 | intel | gshimansky | @@ -8,6 +8,10 @@ on:
description: Install Intel PyTorch Extension | We may want to clarify that installed ipex means our fork of pytorch, otherwise upstream pytorch is used. Or create a separate parameter that specifies pytorch repo. |
intel-xpu-backend-for-triton | github_2023 | others | 1,330 | intel | leshikus | @@ -49,7 +57,9 @@ jobs:
steps:
- name: Print inputs
run: |
- echo "${{ toJSON(github.event.inputs) }}"
+ cat <<EOF | interesting; did this fail due to quotes in `inputs`? |
intel-xpu-backend-for-triton | github_2023 | others | 1,335 | intel | leshikus | @@ -10,6 +10,8 @@ inputs:
default: intel/intel-xpu-backend-for-triton
wheels_pattern:
# Example of specifying only some packages to install: '{intel_extension_for_pytorch-*,torch-*}'
+ # Extended globbing is enabled for this pattern so for example to exclude intel_extension_for_pytorch use pattern | I generally prefer to never use excludes in such cases. I better want a script to fail if the list (e.g. a list of wheels to install) no longer matches the one I expect, and fix this manually.
The reason behind this is when things change in future, the logic may be different as well and better to be rechecked. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,337 | intel | whitneywhtsang | @@ -87,6 +87,10 @@ bool TargetInfo::warpReduce(ConversionPatternRewriter &rewriter, Location loc,
SmallVector<Value> &acc, triton::ReduceOp op,
unsigned numLaneToReduce,
unsigned interleave) const {
+ const bool isLTS =
+ op->g... | [optional] IMO `triton_gpu.is_lts` is clear, no need to create a variable.
```suggestion
if (op->getParentOfType<ModuleOp>()->hasAttr("triton_gpu.is_lts"))
return false;
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,331 | intel | jopperm | @@ -159,27 +156,22 @@ def make_ttgir(mod, metadata, opt, device_arch):
pm = ir.pass_manager(mod.context)
pm.enable_debug()
passes.ttir.add_convert_to_ttgpuir(pm, f"xpu:{device_arch}", opt.num_warps, opt.threads_per_warp, opt.num_ctas)
-
- is_lts_driver = Version(metadata["target"].arch... | Nit: Please pass this bool with a keyword argument (or add a comment) to clarify what it means. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,331 | intel | etiotto | @@ -972,16 +973,17 @@ void LayoutRematerialization::updateRematMapping(
void LayoutRematerialization::rewriteSlice(SetVector<Value> &slice,
DenseMap<Value, Attribute> &layout,
ConvertLayoutOp convertOp,
- ... | hoist outside of the loop. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,331 | intel | etiotto | @@ -95,6 +94,14 @@ void init_triton_intel(py::module &&m) {
context.loadAllAvailableDialects();
});
+ // FIXME: Use SYCL runtime to query supported OpenCL extensions, instead of
+ // checking driver version.
+ m.def("set_device_properties", [](mlir::ModuleOp mod, bool isLTS) {
+ auto i1_ty = mlir::Integ... | 32 -> 1 |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,322 | intel | whitneywhtsang | @@ -64,6 +81,15 @@ class LICMPass : public PassInfoMixin<LICMPass> {
isa<InsertValueInst>(I) || isa<FreezeInst>(I));
}
+ bool isCandidateForHoisting(CallInst *CI, Loop *L) const {
+ if (CI->getCalledFunction()->getName().starts_with("__builtin_IB_subgroup"))
+ return true;
+ if (CI->getCal... | `_Z12get_local_id` is not hoisted by LLVM LICM even after you update the function attributes? |
intel-xpu-backend-for-triton | github_2023 | others | 1,272 | intel | jopperm | @@ -221,3 +221,72 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 :
tt.return
}
}
+
+
+// -----
+
+// COM: Case 4:
+// COM: Checks that DPAS encoding has been forwarded to the store op
+// COM: and the triton_gpu.convert_layout operation in the loop has been removed
+// CHECK:... | Check if you can replace the `make_tensor_ptr`'s operands with constants here; would let you condense the testcase by dropping most of the computation before this point. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,272 | intel | jopperm | @@ -803,54 +803,83 @@ bool LayoutPropagation::rewriteStoreOp(StoreOp storeOp) {
// 2D block store are preceeded by a MakeTensorPtrOp
auto makeTensorPtrOp = ptr.getDefiningOp<MakeTensorPtrOp>();
+ if (!makeTensorPtrOp)
+ return false;
+
// DPAS encoding have to be propagate if conversion from DPAS to
/... | Nit: For clarity, consider replacing `if (cond) {...} else {return false}` with `if (!cond) {return false;} ...` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,272 | intel | jopperm | @@ -803,54 +803,83 @@ bool LayoutPropagation::rewriteStoreOp(StoreOp storeOp) {
// 2D block store are preceeded by a MakeTensorPtrOp
auto makeTensorPtrOp = ptr.getDefiningOp<MakeTensorPtrOp>();
+ if (!makeTensorPtrOp)
+ return false;
+
// DPAS encoding have to be propagate if conversion from DPAS to
/... | Dito. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,272 | intel | etiotto | @@ -803,54 +803,83 @@ bool LayoutPropagation::rewriteStoreOp(StoreOp storeOp) {
// 2D block store are preceeded by a MakeTensorPtrOp
auto makeTensorPtrOp = ptr.getDefiningOp<MakeTensorPtrOp>();
+ if (!makeTensorPtrOp)
+ return false;
+
// DPAS encoding have to be propagate if conversion from DPAS to
/... | Replace with early return. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,272 | intel | etiotto | @@ -803,54 +803,83 @@ bool LayoutPropagation::rewriteStoreOp(StoreOp storeOp) {
// 2D block store are preceeded by a MakeTensorPtrOp
auto makeTensorPtrOp = ptr.getDefiningOp<MakeTensorPtrOp>();
+ if (!makeTensorPtrOp)
+ return false;
+
// DPAS encoding have to be propagate if conversion from DPAS to
/... | ditto |
intel-xpu-backend-for-triton | github_2023 | cpp | 687 | intel | whitneywhtsang | @@ -1891,320 +1893,6 @@ Value EmitDualBF16ElementwiseOp(Location loc,
undefRounding);
}
-struct CmpIOpConversion
- : public ElementwiseOpConversionBase<arith::CmpIOp, CmpIOpConversion> {
- using Base = ElementwiseOpConversionBase<arith::CmpIOp, CmpIOpConversion>;
-... | The E2E failure could be due to not setting the calling convention. |
intel-xpu-backend-for-triton | github_2023 | cpp | 700 | intel | chengjunlu | @@ -887,8 +887,7 @@ static void emitDpasOffsetForCTA(const DpasEncodingAttr &dpasLayout,
for (unsigned elem = 0; elem < elemsPerThreadPerGroup; elem++) {
uint32_t elemRowIndex = (elem / sizePerThreads[1]) * rowsPerWarp;
uint32_t elemColIndex = elem % sizePerThreads[1];
- offsets.push_back({ctaOffsetX * ... | The ctaOffsetX, ctaOffsetY is the coordinate of the CTA distributed to the 2D shape.
The returned offsets is the coordinate of each element in 2D shapes.
Why to remove the shapePerCTA size? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,224 | intel | FMarno | @@ -248,30 +248,36 @@ static bool isOCLBuiltinAvailable(TritonGEN::Matrix2DBlockLoadOp op) {
return true;
}
-static LLVM::CallOp
-createGenISA2DBlockRead(TritonGEN::Matrix2DBlockLoadOp op,
- ConversionPatternRewriter &rewriter) {
+static Value createGenISA2DBlockRead(TritonGEN::Matrix2DBloc... | remove fixme comment |
intel-xpu-backend-for-triton | github_2023 | others | 1,224 | intel | FMarno | @@ -367,16 +367,19 @@ llvm.func @triton_gen.dpas.f32(%c : vector<8xf32>, %a : vector<4xf32>, %b : vect
// -----
-// CHECK: llvm.func spir_funccc @intel_subgroup_block_read_u8_m8k32v2(!llvm.ptr<1>, i32, i32, i32, vector<2xi32>) -> vector<16xi16> attributes {passthrough = ["convergent"]}
+// CHECK: llvm.func spir_fu... | I think a test for all the other variations would be helpful. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,224 | intel | etiotto | @@ -248,30 +248,36 @@ static bool isOCLBuiltinAvailable(TritonGEN::Matrix2DBlockLoadOp op) {
return true;
}
-static LLVM::CallOp
-createGenISA2DBlockRead(TritonGEN::Matrix2DBlockLoadOp op,
- ConversionPatternRewriter &rewriter) {
+static Value createGenISA2DBlockRead(TritonGEN::Matrix2DBloc... | Have we verified that the new OCL builtins do not cause performance degradation given that now we have to allocate/call/load in loops ? |
intel-xpu-backend-for-triton | github_2023 | others | 1,224 | intel | FMarno | @@ -297,16 +297,19 @@ llvm.func @triton_gen.dpas.f32(%c : vector<8xf32>, %a : vector<4xf32>, %b : vect
// -----
-// CHECK: llvm.func spir_funccc @intel_subgroup_block_read_u8_m8k32v2(!llvm.ptr<1> {llvm.nonnull}, i32, i32, i32, vector<2xi32>) -> vector<16xi16> attributes {passthrough = ["nounwind"]}
+// CHECK: llvm... | ```suggestion
// CHECK: [[SIXTEEN:%.*]] = llvm.mlir.constant(16 : i32) : i32
```
or maybe `c16` something like that. |
intel-xpu-backend-for-triton | github_2023 | others | 1,224 | intel | etiotto | @@ -297,16 +297,19 @@ llvm.func @triton_gen.dpas.f32(%c : vector<8xf32>, %a : vector<4xf32>, %b : vect
// -----
-// CHECK: llvm.func spir_funccc @intel_subgroup_block_read_u8_m8k32v2(!llvm.ptr<1> {llvm.nonnull}, i32, i32, i32, vector<2xi32>) -> vector<16xi16> attributes {passthrough = ["nounwind"]}
+// CHECK: llvm... | Missing passthrough attribute to encode the memory semantics of this builtin function. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,289 | intel | victor-eds | @@ -683,37 +683,37 @@ struct StoreOpConversion
auto vals = unpackLLElements(loc, adaptor.getValue(), rewriter);
assert(vals.size() == numElems);
- SmallVector<Value> storededVals;
- Type vectorTy = LLVM::getFixedVectorType(typeConverter->convertType(eltTy),
- ... | Can we use `std::array` instead of `SmallVector` and `static_cast` instead of C-style casts? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,289 | intel | FMarno | @@ -683,37 +683,38 @@ struct StoreOpConversion
auto vals = unpackLLElements(loc, adaptor.getValue(), rewriter);
assert(vals.size() == numElems);
- SmallVector<Value> storededVals;
- Type vectorTy = LLVM::getFixedVectorType(typeConverter->convertType(eltTy),
- ... | ```suggestion
storeVal = insert_element(storeVal, vals[valOffset], i32_val(i));
++valOffset;
```
I just don't like the post-fix increment |
intel-xpu-backend-for-triton | github_2023 | others | 1,300 | intel | etiotto | @@ -8,19 +8,19 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 64
tt.func @reduce_problem_size_64_threads_per_warp_32(%f : tensor<2048xi32, #blocked>) {
// 1st round intra-warp reduce
- // CHECK: @_Z20sub_group_reduce_addi
+ // CHECK: llvm.call spir_funccc @_Z20sub_group_reduce... | Add a CHECK for the function declaration |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,282 | intel | FMarno | @@ -0,0 +1,27 @@
+//===- Mangling.h - Function name mangling utilities -----------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----... | ```suggestion
namespace mlir::triton::gpu::intel {
``` |
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