repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,558 | intel | victor-eds | @@ -0,0 +1,116 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+using namespace mlir;
+
+namespace mlir::triton::gpu::intel {
+
+DPASAnalysis::DPASAnalysis(FunctionOpInterface func)
+ : mod(func->getParentOfType<mlir::ModuleOp>()) {
+ DeviceArch arch = getDeviceArch(... | ```suggestion
default:
llvm_unreachable(...);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,558 | intel | victor-eds | @@ -0,0 +1,116 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+using namespace mlir;
+
+namespace mlir::triton::gpu::intel {
+
+DPASAnalysis::DPASAnalysis(FunctionOpInterface func)
+ : mod(func->getParentOfType<mlir::ModuleOp>()) {
+ DeviceArch arch = getDeviceArch(... | ```suggestion
if (aElemTy != bElemTy)
return DPASEngineType::NOT_APPLICABLE;
```
Second cannot happen |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,558 | intel | victor-eds | @@ -0,0 +1,116 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+using namespace mlir;
+
+namespace mlir::triton::gpu::intel {
+
+DPASAnalysis::DPASAnalysis(FunctionOpInterface func)
+ : mod(func->getParentOfType<mlir::ModuleOp>()) {
+ DeviceArch arch = getDeviceArch(... | ```suggestion
if (aElemTy.getIntOrFloatBitWidth() == 8)
```
Always the same. Same for all above checks. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,558 | intel | victor-eds | @@ -0,0 +1,116 @@
+#include "intel/include/Analysis/DPAS.h"
+#include "triton/Dialect/TritonGPU/IR/Dialect.h"
+
+using namespace mlir;
+
+namespace mlir::triton::gpu::intel {
+
+DPASAnalysis::DPASAnalysis(FunctionOpInterface func)
+ : mod(func->getParentOfType<mlir::ModuleOp>()) {
+ DeviceArch arch = getDeviceArch(... | Question: Are we getting unsigned integers from user code here at all? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,516 | intel | etiotto | @@ -377,25 +379,35 @@ struct LoadOpConversion
delinearize(rewriter, loc, warpId, warpsPerCTA, order);
bool isOperandA = (opIdx == 0);
- SmallVector<unsigned> operandShape =
- isOperandA ? dpasLayout.getShapeA() : dpasLayout.getShapeB();
- SmallVector<int64_t> elemsPerInstr = {operandShape[0... | int64_t --> unsigned |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,516 | intel | etiotto | @@ -377,25 +379,35 @@ struct LoadOpConversion
delinearize(rewriter, loc, warpId, warpsPerCTA, order);
bool isOperandA = (opIdx == 0);
- SmallVector<unsigned> operandShape =
- isOperandA ? dpasLayout.getShapeA() : dpasLayout.getShapeB();
- SmallVector<int64_t> elemsPerInstr = {operandShape[0... | int64_t -> unsigned |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,516 | intel | etiotto | @@ -377,25 +379,35 @@ struct LoadOpConversion
delinearize(rewriter, loc, warpId, warpsPerCTA, order);
bool isOperandA = (opIdx == 0);
- SmallVector<unsigned> operandShape =
- isOperandA ? dpasLayout.getShapeA() : dpasLayout.getShapeB();
- SmallVector<int64_t> elemsPerInstr = {operandShape[0... | use unsigned ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,516 | intel | etiotto | @@ -377,25 +379,35 @@ struct LoadOpConversion
delinearize(rewriter, loc, warpId, warpsPerCTA, order);
bool isOperandA = (opIdx == 0);
- SmallVector<unsigned> operandShape =
- isOperandA ? dpasLayout.getShapeA() : dpasLayout.getShapeB();
- SmallVector<int64_t> elemsPerInstr = {operandShape[0... | use unsigned |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,516 | intel | etiotto | @@ -407,65 +419,153 @@ struct LoadOpConversion
int64_t numRepOuter = numReps[opIdx];
int64_t numRepK = numReps[!opIdx];
- SmallVector<Value> rets;
+ unsigned tileHeight;
+ unsigned vBlocks;
+ unsigned numOperandsOuterDimPerLoad = 1;
+ unsigned numOperandsKDimPerLoad = 1;
+ // dot shape [M,... | use prefix increment |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,516 | intel | victor-eds | @@ -407,65 +419,153 @@ struct LoadOpConversion
int64_t numRepOuter = numReps[opIdx];
int64_t numRepK = numReps[!opIdx];
- SmallVector<Value> rets;
+ unsigned tileHeight;
+ unsigned vBlocks;
+ unsigned numOperandsOuterDimPerLoad = 1;
+ unsigned numOperandsKDimPerLoad = 1;
+ // dot shape [M,... | I assume we cannot check some kind of preconditions to early exit. If not, LGTM. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,516 | intel | whitneywhtsang | @@ -404,68 +416,156 @@ struct LoadOpConversion
getValuesFromBlockPointerStruct(adaptor.getPtr(), rewriter);
// Load the operand.
- int64_t numRepOuter = numReps[opIdx];
- int64_t numRepK = numReps[!opIdx];
+ unsigned numRepOuter = numReps[opIdx];
+ unsigned numRepK = numReps[!opIdx];
+
+ ... | ```suggestion
++elemIdx) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,513 | intel | etiotto | @@ -148,17 +148,43 @@ static void
emitOffsetForDpasLayoutPerCTA(const DpasEncodingAttr &dpasLayout,
SmallVector<SmallVector<unsigned>> &offsets,
unsigned ctaOffsetX, unsigned ctaOffsetY) {
+ // clang-format off
+ // For C operand the layout illustration. | [readibility]: For operand C the layout is: |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,513 | intel | etiotto | @@ -148,17 +148,43 @@ static void
emitOffsetForDpasLayoutPerCTA(const DpasEncodingAttr &dpasLayout,
SmallVector<SmallVector<unsigned>> &offsets,
unsigned ctaOffsetX, unsigned ctaOffsetY) {
+ // clang-format off
+ // For C operand the layout illustration.
... | I think we can remove subgroup size |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,513 | intel | etiotto | @@ -148,17 +148,43 @@ static void
emitOffsetForDpasLayoutPerCTA(const DpasEncodingAttr &dpasLayout,
SmallVector<SmallVector<unsigned>> &offsets,
unsigned ctaOffsetX, unsigned ctaOffsetY) {
+ // clang-format off
+ // For C operand the layout illustration.
... | [minor]: use prefix increment operator to increment the induction variable. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,513 | intel | victor-eds | @@ -324,6 +302,20 @@ struct ConvertLayoutOpConversion
auto llvmElemTy = getTypeConverter()->convertType(elemTy);
+ // llvm::outs() << "johnlu accumNumCTAsEachRep:" << accumNumCTAsEachRep
+ // << "\n";
+ // llvm::outs().flush();
+ // llvm::outs() << "johnlu layout:" << layou... | Can we drop? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,513 | intel | victor-eds | @@ -407,6 +399,8 @@ struct ConvertLayoutOpConversion
auto dstShapePerCTATile = getShapePerCTATile(dstLayout, shape);
auto shapePerCTA = getShapePerCTA(srcLayout, shape);
+ // llvm::outs() << "johnlu the convert layout op: " << op << "\n";
+ // llvm::outs().flush(); | Same |
intel-xpu-backend-for-triton | github_2023 | others | 1,565 | intel | victor-eds | @@ -12,7 +12,7 @@
// CHECK-LABEL: llvm.func spir_kernelcc @float_to_bfloat_conversion(
// CHECK-SCALAR: %[[VAL_0:.*]]: !llvm.struct<(f32, f32, f32, f32)>) -> !llvm.struct<(bf16, bf16, bf16, bf16)>
// CHECK-VECTOR: %[[VAL_0:.*]]... | ```suggestion
module attributes {"triton_gpu.support_sg_2d_block", "triton_gpu.support_dpas", "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32} {
```
I think we can make this a `UnitAttr` so we just need to check whether it's present |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,565 | intel | victor-eds | @@ -94,12 +94,18 @@ void init_triton_intel(py::module &&m) {
context.loadAllAvailableDialects();
});
- // FIXME: Use SYCL runtime to query supported OpenCL extensions, instead of
- // checking driver version.
- m.def("set_device_properties", [](mlir::ModuleOp mod, bool isLTS) {
+ m.def("set_device_propert... | ```suggestion
Builder b(mod);
if (supportSG2DBlock)
mod->setAttr("triton_gpu.support_sg_2d_block", b.getUnitAttr());
if (supportDPAS)
mod->setAttr("triton_gpu.support_dpas", b.getUnitAttr());
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,565 | intel | LiyangLingIntel | @@ -153,16 +153,16 @@ def make_ttir(mod, metadata, opt):
return mod
@staticmethod
- def make_ttgir(mod, metadata, opt, device_arch):
+ def make_ttgir(mod, metadata, opt, device_arch, support_sg_2d_block, support_dpas):
is_lts = Version(metadata["target"].arch["driver_version"]) == Version... | As we can do query to check if features are supported or not, can we remove attr `is_lts` from lowering passes? Are there any features not covered? |
intel-xpu-backend-for-triton | github_2023 | python | 1,565 | intel | LiyangLingIntel | @@ -153,16 +153,16 @@ def make_ttir(mod, metadata, opt):
return mod
@staticmethod
- def make_ttgir(mod, metadata, opt, device_arch):
+ def make_ttgir(mod, metadata, opt, device_arch, support_sg_2d_block, support_dpas): | How about use `self.properties` here and get the actual properties in `intel.set_device_properties`? In this way, when there are further property changes, we do not need to change the interface back and forth. |
intel-xpu-backend-for-triton | github_2023 | others | 1,565 | intel | victor-eds | @@ -19,6 +19,8 @@ def TritonIntelGPU_Dialect : Dialect {
];
let extraClassDeclaration = [{
+ static std::string getSupportSG2DBlockAttrName() { return "triton_intel_gpu.support_sg_2d_block"; }
+ static std::string getSupportDPASAttrName() { return "triton_intel_gpu.support_dpas"; } | ```suggestion
static llvm::StringRef getSupportSG2DBlockAttrName() { return "triton_intel_gpu.support_sg_2d_block"; }
static llvm::StringRef getSupportDPASAttrName() { return "triton_intel_gpu.support_dpas"; }
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,565 | intel | etiotto | @@ -18,7 +18,7 @@ class TritonIntelGPUToLLVMTypeConverter : public TritonGPUToLLVMTypeConverter {
using TypeConverter::convertType;
TritonIntelGPUToLLVMTypeConverter(
- MLIRContext *ctx, LowerToLLVMOptions &option, bool isLTSDriver,
+ MLIRContext *ctx, LowerToLLVMOptions &option, bool isBlockPtrPathEn... | Lets call it experimental path (Block pointers are a language features) |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,565 | intel | etiotto | @@ -79,9 +79,14 @@ struct ConvertTritonGPUToLLVM
intel::TritonGPUToLLVMPipelineManager pipelineManager(mod, context);
mlir::LowerToLLVMOptions option(context);
option.overrideIndexBitwidth(32);
- bool isLTSDriver = mod->hasAttr("triton_gpu.is_lts");
+ bool isBlockPtrPathEnabled = | Lets call `isExperimentalPath` (everwhere) |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | victor-eds | @@ -201,21 +202,368 @@ struct TritonRaiseBlockPointer
: triton::intel::impl::TritonRaiseBlockPointerBase<
TritonRaiseBlockPointer> {
using Base::Base;
+ using IndexMapSet = std::map<int, std::set<int>>;
+ SmallVector<Operation *> cleanUp;
void runOnOperation() final {
- getOperation()->walk... | We don't really care about the `WalkResult` here, right? Can we just `return`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | victor-eds | @@ -269,6 +644,7 @@ struct TritonRaiseBlockPointer
LogicalResult visitOperand(Value operand, PtrState &state, const Location loc,
OpBuilder &builder) {
+ | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | victor-eds | @@ -237,6 +585,33 @@ struct TritonRaiseBlockPointer
ptrMap.map(result, mapped);
+ // AddPtrOps that have been rewritten and no longer used in the code must be
+ // removed in the pass to avoid type matching issue.
+ cleanUp.push_back(op);
+
+ return success();
+ }
+
+ LogicalResult visitOperandMa... | ```suggestion
state.sizes = SmallVector<int>(shape);
state.strides = makeTPtrOp.getStrides();
state.offsets = makeTPtrOp.getOffsets();
state.shape = makeTPtrOp.getShape();
```
I think the 3 assignments can be out of the loop, for the sizes, not so sure due to typeconv |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | victor-eds | @@ -201,21 +202,368 @@ struct TritonRaiseBlockPointer
: triton::intel::impl::TritonRaiseBlockPointerBase<
TritonRaiseBlockPointer> {
using Base::Base;
+ using IndexMapSet = std::map<int, std::set<int>>;
+ SmallVector<Operation *> cleanUp;
void runOnOperation() final {
- getOperation()->walk... | ```suggestion
// Note that we want the knownPtrs to be indexed by block arg, but we
// only have index for now. Also, the state we record is the init
// arg, but want to use the newly created block arg. These block args
// are not created yet. We will translate this mapping later.
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | victor-eds | @@ -201,21 +202,368 @@ struct TritonRaiseBlockPointer
: triton::intel::impl::TritonRaiseBlockPointerBase<
TritonRaiseBlockPointer> {
using Base::Base;
+ using IndexMapSet = std::map<int, std::set<int>>;
+ SmallVector<Operation *> cleanUp;
void runOnOperation() final {
- getOperation()->walk... | I think this was messed up by formatting:
```suggestion
// arg):
// scf.for (%tensor_of_ptr) {
// %data = tt.load %tensor_of_ptr
// // more operations to update %tensor_of_ptr
// }
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | victor-eds | @@ -201,21 +202,368 @@ struct TritonRaiseBlockPointer
: triton::intel::impl::TritonRaiseBlockPointerBase<
TritonRaiseBlockPointer> {
using Base::Base;
+ using IndexMapSet = std::map<int, std::set<int>>;
+ SmallVector<Operation *> cleanUp;
void runOnOperation() final {
- getOperation()->walk... | ```suggestion
for (auto &[i, state] : initArgIndexState) {
```
Avoid copying `state` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | victor-eds | @@ -201,21 +202,368 @@ struct TritonRaiseBlockPointer
: triton::intel::impl::TritonRaiseBlockPointerBase<
TritonRaiseBlockPointer> {
using Base::Base;
+ using IndexMapSet = std::map<int, std::set<int>>;
+ SmallVector<Operation *> cleanUp;
void runOnOperation() final {
- getOperation()->walk... | ```suggestion
for (auto &[i, state] : knownPtrsTmp) {
```
same |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | victor-eds | @@ -201,21 +202,368 @@ struct TritonRaiseBlockPointer
: triton::intel::impl::TritonRaiseBlockPointerBase<
TritonRaiseBlockPointer> {
using Base::Base;
+ using IndexMapSet = std::map<int, std::set<int>>;
+ SmallVector<Operation *> cleanUp;
void runOnOperation() final {
- getOperation()->walk... | ```suggestion
auto &thisSet = levelToBlockArgIndex.find(level)->second;
```
Avoid copying set |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | etiotto | @@ -201,21 +202,378 @@ struct TritonRaiseBlockPointer
: triton::intel::impl::TritonRaiseBlockPointerBase<
TritonRaiseBlockPointer> {
using Base::Base;
+ using IndexMapSet = std::map<int, std::set<int>>;
+ SmallVector<Operation *> cleanUp;
void runOnOperation() final {
- getOperation()->walk... | Not sure about emitting warnings when this pass fails. If they become too verbose we may want to remove them. This pass will fail when the regular ptr cannot be raised to block pointer and in that situation nothing can be done (in the compiler) to avoid the failure. For now is fine to keep the warnings. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | etiotto | @@ -201,21 +202,378 @@ struct TritonRaiseBlockPointer
: triton::intel::impl::TritonRaiseBlockPointerBase<
TritonRaiseBlockPointer> {
using Base::Base;
+ using IndexMapSet = std::map<int, std::set<int>>;
+ SmallVector<Operation *> cleanUp;
void runOnOperation() final {
- getOperation()->walk... | do you really need to capture? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | etiotto | @@ -201,21 +202,378 @@ struct TritonRaiseBlockPointer
: triton::intel::impl::TritonRaiseBlockPointerBase<
TritonRaiseBlockPointer> {
using Base::Base;
+ using IndexMapSet = std::map<int, std::set<int>>;
+ SmallVector<Operation *> cleanUp;
void runOnOperation() final {
- getOperation()->walk... | add msg to assert |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | etiotto | @@ -201,21 +202,378 @@ struct TritonRaiseBlockPointer
: triton::intel::impl::TritonRaiseBlockPointerBase<
TritonRaiseBlockPointer> {
using Base::Base;
+ using IndexMapSet = std::map<int, std::set<int>>;
+ SmallVector<Operation *> cleanUp;
void runOnOperation() final {
- getOperation()->walk... | ditto |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | etiotto | @@ -201,21 +202,378 @@ struct TritonRaiseBlockPointer
: triton::intel::impl::TritonRaiseBlockPointerBase<
TritonRaiseBlockPointer> {
using Base::Base;
+ using IndexMapSet = std::map<int, std::set<int>>;
+ SmallVector<Operation *> cleanUp;
void runOnOperation() final {
- getOperation()->walk... | msg pls |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,546 | intel | etiotto | @@ -201,21 +202,378 @@ struct TritonRaiseBlockPointer
: triton::intel::impl::TritonRaiseBlockPointerBase<
TritonRaiseBlockPointer> {
using Base::Base;
+ using IndexMapSet = std::map<int, std::set<int>>;
+ SmallVector<Operation *> cleanUp;
void runOnOperation() final {
- getOperation()->walk... | ```suggestion
operands.push_back(mappedV ? mappedV : opnd);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,568 | intel | victor-eds | @@ -1415,8 +1372,50 @@ struct TritonMatrix2DBlockPrefetchLowering
LogicalResult
matchAndRewrite(TritonGEN::Matrix2DBlockPrefetchOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
- LLVM::CallOp callOp = createGenISA2DBlockPrefetch(op, rewriter);
- rewriter.rep... | ```suggestion
const bool useGenISA = std::getenv("TRITONGEN_FORCE_GENISA");
```
Maybe we can just do this if the variable's defined? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,568 | intel | victor-eds | @@ -1330,7 +1232,63 @@ struct TritonMatrix2DBlockLoadLowering
return success();
}
- rewriter.replaceOp(op, createGenISA2DBlockRead(op, rewriter));
+ // TODO: Remove GenISA lowering after PoC productization is completed.
+ char *env = std::getenv("TRITONGEN_FORCE_GENISA");
+ const bool useGenIS... | Same |
intel-xpu-backend-for-triton | github_2023 | python | 1,495 | intel | etiotto | @@ -62,7 +63,7 @@ def naive_softmax(x):
# Compute Kernel
# --------------
#
-# Our softmax kernel works as follows: each program loads a row of the input matrix X,
+# Our softmax kernel works as follows: each program loads a set of rows of the input matrix X strided by number of programs, | This is good but introduces a merge conflict. @whitneywhtsang do you prefer to leave the comment as it is upstream to reduce the merge conflict footprint ? |
intel-xpu-backend-for-triton | github_2023 | python | 1,495 | intel | whitneywhtsang | @@ -71,59 +72,70 @@ def naive_softmax(x):
@triton.jit
-def softmax_kernel(output_ptr, input_ptr, input_row_stride, output_row_stride, n_cols, BLOCK_SIZE: tl.constexpr):
- # The rows of the softmax are independent, so we parallelize across those
- row_idx = tl.program_id(0)
- # The stride represents how mu... | These variables are introduced to calculate the kernel launch instance, as we always launch `n_rows` instances, these variables are not used.
Why is it better for XPU to always launch `n_rows` instances? |
intel-xpu-backend-for-triton | github_2023 | python | 1,495 | intel | whitneywhtsang | @@ -71,59 +72,91 @@ def naive_softmax(x):
@triton.jit
-def softmax_kernel(output_ptr, input_ptr, input_row_stride, output_row_stride, n_cols, BLOCK_SIZE: tl.constexpr):
- # The rows of the softmax are independent, so we parallelize across those
- row_idx = tl.program_id(0)
- # The stride represents how mu... | ```suggestion
kernel[(num_programs, )](y, x, x.stride(0), y.stride(0), n_rows, n_cols, num_warps=num_warps,
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,495 | intel | whitneywhtsang | @@ -71,59 +72,91 @@ def naive_softmax(x):
@triton.jit
-def softmax_kernel(output_ptr, input_ptr, input_row_stride, output_row_stride, n_cols, BLOCK_SIZE: tl.constexpr):
- # The rows of the softmax are independent, so we parallelize across those
- row_idx = tl.program_id(0)
- # The stride represents how mu... | ```suggestion
# The block size of each loop iteration is the smallest power of two greater than the number of columns in `x`
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,495 | intel | whitneywhtsang | @@ -71,59 +72,91 @@ def naive_softmax(x):
@triton.jit
-def softmax_kernel(output_ptr, input_ptr, input_row_stride, output_row_stride, n_cols, BLOCK_SIZE: tl.constexpr):
- # The rows of the softmax are independent, so we parallelize across those
- row_idx = tl.program_id(0)
- # The stride represents how mu... | we may want to use num_stages for prefetch distance |
intel-xpu-backend-for-triton | github_2023 | python | 1,495 | intel | whitneywhtsang | @@ -71,59 +72,91 @@ def naive_softmax(x):
| Our softmax kernel works as follows: each program loads a set of rows of the input matrix X strided by number of programs,
... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,503 | intel | etiotto | @@ -574,15 +574,62 @@ TritonRaiseBlockPointer::visitAddPointerOperand(triton::BroadcastOp broadcastOp,
ArrayRef<int64_t> srcShape = cast<ShapedType>(src.getType()).getShape();
ArrayRef<int64_t> dstShape = cast<ShapedType>(dst.getType()).getShape();
- // TODO: Implement srcShape.size() < dstShape.size() case
- ... | typo: propagate -> propagated |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,503 | intel | etiotto | @@ -574,15 +574,62 @@ TritonRaiseBlockPointer::visitAddPointerOperand(triton::BroadcastOp broadcastOp,
ArrayRef<int64_t> srcShape = cast<ShapedType>(src.getType()).getShape();
ArrayRef<int64_t> dstShape = cast<ShapedType>(dst.getType()).getShape();
- // TODO: Implement srcShape.size() < dstShape.size() case
- ... | [nit]: use ++i (also for the other loop in the code below) |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,503 | intel | etiotto | @@ -574,15 +574,62 @@ TritonRaiseBlockPointer::visitAddPointerOperand(triton::BroadcastOp broadcastOp,
ArrayRef<int64_t> srcShape = cast<ShapedType>(src.getType()).getShape();
ArrayRef<int64_t> dstShape = cast<ShapedType>(dst.getType()).getShape();
- // TODO: Implement srcShape.size() < dstShape.size() case
- ... | Use early "continue":
if (condition) {
++srcAxis;
continue;
}
<else part here>
|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,525 | intel | whitneywhtsang | @@ -49,16 +49,39 @@ using namespace mlir::triton::gpu;
// Helper Functions
//===----------------------------------------------------------------------===//
-static intel::AttributeList
-getAttrList(const intel::AttrBuilder &funcAttrBuilder,
- ArrayRef<NamedAttrList> paramAttrs = {}) {
+static void addToA... | Is this function used? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,525 | intel | whitneywhtsang | @@ -627,9 +625,13 @@ createGenISA2DBlockWrite(TritonGEN::Matrix2DBlockStoreOp op,
cache,
storeVal};
- auto callOp = rewriter.create<LLVM::CallOp>(loc, funcOp, args);
- callOp.setCConv(LLVM::cconv::CConv::SPIR_FUNC);
- return callOp;
+ intel::AttributeList attr... | FYI by the GenISA definition, `GenISA_LSC2DBlockWrite` doesn't have any attributes. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,525 | intel | victor-eds | @@ -49,16 +49,39 @@ using namespace mlir::triton::gpu;
// Helper Functions
//===----------------------------------------------------------------------===//
-static intel::AttributeList
-getAttrList(const intel::AttrBuilder &funcAttrBuilder,
- ArrayRef<NamedAttrList> paramAttrs = {}) {
+static void addToA... | ```suggestion
ArrayRef<
std::pair<llvm::Attribute::AttrKind, std::optional<uint64_t>>>
attributes,
```
This is usually passed this like this |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,525 | intel | victor-eds | @@ -49,16 +49,39 @@ using namespace mlir::triton::gpu;
// Helper Functions
//===----------------------------------------------------------------------===//
-static intel::AttributeList
-getAttrList(const intel::AttrBuilder &funcAttrBuilder,
- ArrayRef<NamedAttrList> paramAttrs = {}) {
+static void addToA... | Same as above |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,525 | intel | victor-eds | @@ -49,16 +49,39 @@ using namespace mlir::triton::gpu;
// Helper Functions
//===----------------------------------------------------------------------===//
-static intel::AttributeList
-getAttrList(const intel::AttrBuilder &funcAttrBuilder,
- ArrayRef<NamedAttrList> paramAttrs = {}) {
+static void addToA... | ```suggestion
for (auto [kind, optValue] : attributes) {
if (optValue)
funcAttrBuilder.addPassthroughAttribute(kind, optValue);
else
funcAttrBuilder.addPassthroughAttribute(kind);
}
```
A bit cleaner IMO |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,525 | intel | whitneywhtsang | @@ -1288,11 +1242,14 @@ struct TritonSubGroupShuffleLowering
ConversionPatternRewriter &rewriter) const override {
Value val = op.getValue();
auto origTy = val.getType();
- val = extend(op, op.getValue(), origTy, rewriter);
+
+ origTy.print(llvm::errs()); | remove |
intel-xpu-backend-for-triton | github_2023 | others | 1,536 | intel | gshimansky | @@ -64,9 +68,7 @@ env:
jobs:
integration-tests:
name: Integration tests
- runs-on:
- - ${{ inputs.runner_label || 'Linux' }}
- - ${{ inputs.driver_version }}
+ runs-on: ${{ fromJson(inputs.runner_label && format('["{0}"]', inputs.runner_label) || format('["{0}", "{1}"]', inputs.device, inputs.d... | Would it be better to allow runner_label to specify a list of labels instead of just one element, e.g.
```
inputs.runner_label != '' && fromJson(inputs.runner_label) || fromJson(format('["{0}", "{1}"]', inputs.device, inputs.driver_version))
```
BTW, does it work to specify list of labels like `[inputs.device, inp... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,532 | intel | chengjunlu | @@ -1203,28 +1254,36 @@ struct TritonSubGroupReduceLowering
SmallVector<Type> argTypes{valTy};
SmallVector<Value> args{val};
bool useCluster = (getSubgroupSize(op) != op.getSize());
- std::string fnName = "sub_group_";
- if (useCluster)
- fnName += "clustered_";
- fnName += "reduce_" + stri... | Is the `TRITONGEN_FORCE_GENISA` for debug?
If it was for debugging, we could modify the code locally when debugging and remove the secret env variable. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,532 | intel | victor-eds | @@ -84,6 +92,46 @@ createDeviceFunctionCall(ConversionPatternRewriter &rewriter,
return callOp;
}
+static LLVM::CallOp
+createGenISASubGroupReduce(TritonGEN::SubGroupReduceOp op, Value val,
+ ConversionPatternRewriter &rewriter) {
+ Location loc = op.getLoc();
+ auto getKindVal = [](Tr... | ```suggestion
auto kind =
rewriter.create<LLVM::ConstantOp>(loc, i8_ty, static_cast<int>(op.getKind()));
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,506 | intel | whitneywhtsang | @@ -1190,6 +1190,55 @@ struct TritonSubGroupReduceLowering
}
};
+struct TritonSubGroupScanLowering
+ : public ConvertOpToLLVMPattern<TritonGEN::SubGroupScanOp> {
+ using ConvertOpToLLVMPattern<
+ TritonGEN::SubGroupScanOp>::ConvertOpToLLVMPattern;
+
+ LogicalResult
+ matchAndRewrite(TritonGEN::SubGroup... | We start to have similar pattern to zext and trunc < 8 bit type for each subgroup op lowering, do you think that's something we can common? |
intel-xpu-backend-for-triton | github_2023 | others | 1,506 | intel | whitneywhtsang | @@ -259,6 +259,31 @@ def TritonGEN_SubGroupReduceOp : TritonGEN_Op<"sub_group_reduce", [
let hasVerifier = 1;
}
+def TritonGEN_SubGroupScanOp : TritonGEN_Op<"sub_group_scan", [
+ AllTypesMatch<["res", "value"]>]>,
+ Results<(outs SignlessIntegerOrFloatLike:$res)>,
+ Arguments<(ins SignlessIntegerOrFloatLik... | can you please explain what is an inclusive or exclusive scan? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,506 | intel | whitneywhtsang | @@ -67,6 +67,18 @@ LogicalResult TritonGEN::SubGroupReduceOp::verify() {
return success();
}
+//===----------------------------------------------------------------------===//
+// gen.sub_group_scan
+//===----------------------------------------------------------------------===//
+
+LogicalResult TritonGEN::SubGro... | Why do you need SPIRV target env for SubGroupScanOp? |
intel-xpu-backend-for-triton | github_2023 | python | 1,493 | intel | etiotto | @@ -197,38 +185,150 @@ def matmul_kernel_with_block_pointers(
tl.store(c_block_ptr, c, boundary_check=(0, 1))
+@triton.autotune(
+ configs=[
+ triton.Config({'BLOCK_SIZE_M': 256, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 32, 'GROUP_SIZE_M': 4}, num_stages=2,
+ num_warps=32),
+ ... | what is the reason the other some entries are commented out ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,493 | intel | etiotto | @@ -355,6 +359,26 @@ class ExtractOpConversion : public ConvertTritonGPUOpToLLVMPattern<ExtractOp> {
}
};
+class AddPtrOpConversion : public ConvertTritonGPUOpToLLVMPattern<AddPtrOp> {
+public:
+ using ConvertTritonGPUOpToLLVMPattern<
+ AddPtrOp>::ConvertTritonGPUOpToLLVMPattern;
+ LogicalResult
+ matchAn... | `auto` -> `Location`
We should use static type where the type is not immediately clear from the context. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,493 | intel | etiotto | @@ -314,11 +315,16 @@ class TritonIntelGPUDistributeToWarpsPass
Dialect *arithDialect = getContext().getLoadedDialect("arith");
Dialect *mathDialect = getContext().getLoadedDialect("math");
+ auto hasTensorType = [](Type type) {
+ if (isa<RankedTensorType>(type))
+ return true;
+ ... | Instead of defining this lambda I think you can use the function `isTensorOrTensorPointerType` which is defined in Dialect/Triton/IR/Types.cpp.
Please take a look. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,493 | intel | whitneywhtsang | @@ -314,11 +315,16 @@ class TritonIntelGPUDistributeToWarpsPass
Dialect *arithDialect = getContext().getLoadedDialect("arith");
Dialect *mathDialect = getContext().getLoadedDialect("math");
+ auto hasTensorType = [](Type type) {
+ if (isa<RankedTensorType>(type))
+ return true;
+ ... | ```suggestion
if (!llvm::any_of(op->getResultTypes(), hasTensorType))
return WalkResult::advance();
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,493 | intel | Dewei-Wang-sh | @@ -181,28 +181,145 @@ def matmul_kernel_with_block_pointers(
tl.store(c_block_ptr, c, boundary_check=(0, 1))
+@triton.autotune(
+ configs=[
+ triton.Config({'BLOCK_SIZE_M': 256, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 32, 'GROUP_SIZE_M': 4}, num_stages=2,
+ num_warps=32),
+ ... | seems not testing the batched version with ci |
intel-xpu-backend-for-triton | github_2023 | python | 1,493 | intel | whitneywhtsang | @@ -214,14 +329,29 @@ def matmul(a, b, accum_dtype, res_dtype):
torch.manual_seed(0)
torch.xpu.set_fp32_math_mode(torch.xpu.utils.FP32MathMode.TF32)
-for dtype, accum_dtype, res_dtype in [(torch.float16, torch.float16, torch.float16),
- (torch.float16, torch.float32, torch.float... | Instead of duplicating the list, how about creating a loop to run both `(512, 512)` and `(batch_size, 512, 512)` for each dtype? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,493 | intel | whitneywhtsang | @@ -16,6 +16,8 @@
#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
#include "intel/include/Dialect/TritonIntelGPU/Transforms/Passes.h"
+#include "triton/Dialect/Triton/IR/Dialect.h"
+#include "triton/Dialect/Triton/IR/Types.h" | remove? |
intel-xpu-backend-for-triton | github_2023 | python | 1,493 | intel | whitneywhtsang | @@ -215,46 +330,60 @@ def matmul(a, b, accum_dtype, res_dtype):
torch.manual_seed(0)
torch.xpu.set_fp32_math_mode(torch.xpu.utils.FP32MathMode.TF32)
for dtype, accum_dtype, res_dtype in [(torch.float16, torch.float16, torch.float16),
+ (torch.float16, torch.float32, torch.float16... | remove? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,508 | intel | whitneywhtsang | @@ -14,6 +14,7 @@
#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
#include "triton/Conversion/TritonGPUToLLVM/Utility.h"
#include "triton/Dialect/Triton/IR/Utility.h"
+#include "llvm/Support/ErrorHandling.h" | Needed for `llvm_unreachable`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,502 | intel | etiotto | @@ -221,6 +221,9 @@ class ConvertTritonToTritonGPUWarp
case Workload::Attention: {
break;
}
+ case Workload::None:
+ case Workload::ElementWise:
+ case Workload::Reduction:; | [nit]: Formatting is silly here. The ';' is hard to see. Perhaps:
```
case Workload::Attention:
case Workload::None:
case Workload::ElementWise:
case Workload::Reduction:
break;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,502 | intel | etiotto | @@ -36,28 +36,32 @@ struct IntelDPASCapability {
uint32_t opsChanBitWidths;
};
-static IntelDPASCapability caps[] = {
- [(uint32_t)DeviceArch::UNKNOWN] = {},
-
- [(uint32_t)DeviceArch::ATS] =
- {
- .systolicDepth = 8,
- .repeatCount = 8,
- .executionSize = 8,
- ... | Use designated initializers? As in:
```
IntelDPASCapability cap = { .systolicDepth = 8, .repeatCount = 8, .executionSize = 8, .opsChanBitWidths = 32};
return cap;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,502 | intel | etiotto | @@ -36,28 +36,32 @@ struct IntelDPASCapability {
uint32_t opsChanBitWidths;
};
-static IntelDPASCapability caps[] = {
- [(uint32_t)DeviceArch::UNKNOWN] = {},
-
- [(uint32_t)DeviceArch::ATS] =
- {
- .systolicDepth = 8,
- .repeatCount = 8,
- .executionSize = 8,
- ... | Here we return an IntelDPASCapability with default values for its member variables. When the arch is not known we may be running on a GPU with no DPAS capability at all. Probably better to return std::optional<IntelDPASCapability> in that case. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,502 | intel | etiotto | @@ -2200,7 +2200,7 @@ struct MulhiUIOpConversion
Type resultElementTy = getElementTypeOrSelf(op.getResult().getType());
assert(resultElementTy.isInteger(32) || resultElementTy.isInteger(64));
- StringRef funcName = targetInfo.getMulhiFuncName(resultElementTy);
+ std::string funcName = targetInfo.getMu... | is this change really required (new clang 17.0.6 complains if we use StringRef)? |
intel-xpu-backend-for-triton | github_2023 | python | 1,492 | intel | etiotto | @@ -217,16 +217,18 @@ def __str__(self):
class DpasLayout:
- def __init__(self, repeatCount, systolic_depth, execution_size, ops_per_chan, threads_per_warp, warps_per_cta):
+ def __init__(self, repeatCount, systolic_depth, execution_size, ops_per_chan, threads_per_warp, rep_cluster,
+ warps_p... | [nit] add the new `rep_cluster` argument at the end ? |
intel-xpu-backend-for-triton | github_2023 | others | 1,492 | intel | whitneywhtsang | @@ -77,6 +78,9 @@ along the row (resp. col) dimension.
SmallVector<unsigned> getShapeA() const;
SmallVector<unsigned> getShapeB() const;
SmallVector<unsigned> getShapeC() const;
+ SmallVector<unsigned> getDPASInstShapeA() const;
+ SmallVector<unsigned> getDPASInstShapeB() const;
+ SmallVector<un... | [nit] Same order as the definition.
```suggestion
SmallVector<unsigned> getDPASInstShapeA() const;
SmallVector<unsigned> getDPASInstShapeB() const;
SmallVector<unsigned> getDPASInstShapeC() const;
SmallVector<unsigned> getShapeA() const;
SmallVector<unsigned> getShapeB() const;
SmallVect... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,209 | intel | whitneywhtsang | @@ -336,6 +338,78 @@ createGenISA2DBlockRead(TritonGEN::Matrix2DBlockLoadOp op,
return rewriter.create<LLVM::CallOp>(loc, funcOp, args);
}
+// FIXME: This is a temporary solution. Remove once IGC can update the address
+// payload.
+static LLVM::CallOp
+createBlock2DReadWithAddressPayloadUpdate(TritonGEN::Matrix2... | ```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,209 | intel | whitneywhtsang | @@ -336,6 +338,78 @@ createGenISA2DBlockRead(TritonGEN::Matrix2DBlockLoadOp op,
return rewriter.create<LLVM::CallOp>(loc, funcOp, args);
}
+// FIXME: This is a temporary solution. Remove once IGC can update the address
+// payload.
+static LLVM::CallOp
+createBlock2DReadWithAddressPayloadUpdate(TritonGEN::Matrix2... | ```suggestion
std::string fnName = "__builtin_IB_subgroup_block_read_ap_";
if (op.getVnniTransform())
fnName += "transform_";
fnName = "u" +
std::to_string(op.getElemSizeInBits()) + "_m" +
std::to_string(op.getTileHeight()) + "k" +
std::to_string(op.... |
intel-xpu-backend-for-triton | github_2023 | python | 1,140 | intel | whitneywhtsang | @@ -352,8 +352,8 @@ def matmul(a, b, activation=""):
a.stride(0), a.stride(1), #
b.stride(0), b.stride(1), #
c.stride(0), c.stride(1), #
- ACTIVATION=activation #
- )
+ ACTIVATION=activation, #
+ threads_per_warp=16) | [nit]
```suggestion
threads_per_warp=16 #
)
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,420 | intel | victor-eds | @@ -0,0 +1,424 @@
+#include "third_party/intel/include/Target/LLVMIR/DSE.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/AssumptionCache.h"
+#include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/MemoryBuiltins... | ```suggestion
static constexpr StringLiteral prefix =
"__builtin_IB_subgroup_setBlock2DAddressPayloadBlock";
```
nit |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,420 | intel | victor-eds | @@ -0,0 +1,424 @@
+#include "third_party/intel/include/Target/LLVMIR/DSE.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/AssumptionCache.h"
+#include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/MemoryBuiltins... | Why not `operator==` instead? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,420 | intel | victor-eds | @@ -0,0 +1,424 @@
+#include "third_party/intel/include/Target/LLVMIR/DSE.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/AssumptionCache.h"
+#include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/MemoryBuiltins... | ```suggestion
auto *CI = dyn_cast<CallInst>(I);
if (!CI)
return false;
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,420 | intel | victor-eds | @@ -0,0 +1,424 @@
+#include "third_party/intel/include/Target/LLVMIR/DSE.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/AssumptionCache.h"
+#include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/MemoryBuiltins... | Can we not print this unconditionally? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,420 | intel | victor-eds | @@ -0,0 +1,424 @@
+#include "third_party/intel/include/Target/LLVMIR/DSE.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/AssumptionCache.h"
+#include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/MemoryBuiltins... | NIT: I think we can drop this assertion if we're `cast`-ing later. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,420 | intel | victor-eds | @@ -0,0 +1,424 @@
+#include "third_party/intel/include/Target/LLVMIR/DSE.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/AssumptionCache.h"
+#include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/MemoryBuiltins... | We won't be finding duplicate kernels, so we can use lighter-weight `SmallVector` instead. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,420 | intel | victor-eds | @@ -0,0 +1,424 @@
+#include "third_party/intel/include/Target/LLVMIR/DSE.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/AssumptionCache.h"
+#include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/MemoryBuiltins... | Missing `return true` here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,420 | intel | victor-eds | @@ -0,0 +1,426 @@
+#include "third_party/intel/include/Target/LLVMIR/DSE.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/AssumptionCache.h"
+#include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/LoopInfo.h"
+#incl... | I think something like:
```suggestion
bool operator<(const SetAddressPayloadInfo &other) const {
if (ptr < other.ptr)
return true;
if (ptr > other.ptr)
return false;
if (val < other.val)
return true;
if (val > other.val)
return false;
if (static_cast<std::underly... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,420 | intel | victor-eds | @@ -0,0 +1,426 @@
+#include "third_party/intel/include/Target/LLVMIR/DSE.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/AssumptionCache.h"
+#include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/LoopInfo.h"
+#incl... | ```suggestion
if (trace) {
llvm::errs() << " visiting " << *Current;
if (!MSSA.isLiveOnEntryDef(Current) && isa<MemoryUseOrDef>(Current))
llvm::errs() << " ("
<< *cast<MemoryUseOrDef>(Current)->getMemoryInst()
<< ")";
... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,420 | intel | whitneywhtsang | @@ -0,0 +1,418 @@
+#include "third_party/intel/include/Target/LLVMIR/DSE.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/AssumptionCache.h"
+#include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/LoopInfo.h"
+#incl... | ```suggestion
for (unsigned i = 0; i < State.MemDefs.size(); ++i) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,420 | intel | whitneywhtsang | @@ -0,0 +1,418 @@
+#include "third_party/intel/include/Target/LLVMIR/DSE.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/AssumptionCache.h"
+#include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/LoopInfo.h"
+#incl... | ```suggestion
for (unsigned j = 0; j < ToCheck.size(); ++j) {
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,467 | intel | etiotto | @@ -38,53 +38,67 @@ namespace {
/// FIXME: maybe set sizePerWarp in the attr directly.
SmallVector<int64_t> getSizePerWarp(RankedTensorType type, Attribute layout) {
SmallVector<int64_t> sizePerWarp;
-
- TypeSwitch<Attribute>(layout)
- .Case<ttg::BlockedEncodingAttr>([&](auto blockedLayout) {
- const ... | Remove include header for TypeSwitch (no longer required). |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,467 | intel | etiotto | @@ -38,53 +38,62 @@ namespace {
/// FIXME: maybe set sizePerWarp in the attr directly.
SmallVector<int64_t> getSizePerWarp(RankedTensorType type, Attribute layout) {
SmallVector<int64_t> sizePerWarp;
-
- TypeSwitch<Attribute>(layout)
- .Case<ttg::BlockedEncodingAttr>([&](auto blockedLayout) {
- const ... | Should we use a TypeSwitch or is the it... else if... else OK here. @victor-eds, @whitneywhtsang ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,467 | intel | whitneywhtsang | @@ -312,28 +364,37 @@ class TritonIntelGPUDistributeToWarpsPass
typeMap[op] = cast<RankedTensorType>(op.getSrc().getType());
});
- Dialect *arithDialect = getContext().getLoadedDialect("arith");
- Dialect *mathDialect = getContext().getLoadedDialect("math");
+ Dialect *arithDialect = ct... | Can we use `isTensorOrTensorPointerType` defined in `Dialect/Triton/IR/Types.cpp`? |
intel-xpu-backend-for-triton | github_2023 | python | 1,485 | intel | whitneywhtsang | @@ -27,6 +28,8 @@
def test_cast_matmul(M, K, N, w_dtype, x_dtype, out_dtype, device):
if x_dtype == w_dtype:
pytest.xfail("skip same dtype")
+ if "float64" in (w_dtype, x_dtype) and not tr.driver.active.get_current_target().arch['has_fp64']: | ```suggestion
if device == "xpu" and "float64" in (w_dtype, x_dtype) and not tr.driver.active.get_current_target().arch['has_fp64']:
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,481 | intel | victor-eds | @@ -481,4 +505,42 @@ LogicalResult TritonRaiseBlockPointer::visitAddPointerOperand(
return success();
}
+
+template <>
+LogicalResult TritonRaiseBlockPointer::visitAddPointerOperand(
+ triton::ExpandDimsOp expandDimsOp, PtrState &state, Location loc,
+ OpBuilder &builder) {
+ assert(state.isEmpty() && "sta... | ```suggestion
"TritonRaiseBlockPointer: unsupported scenario where expand_dims result "
"has modulo and rank > 2");
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,481 | intel | victor-eds | @@ -50,6 +50,30 @@ struct PtrState {
return offsets.size();
}
+ bool isBlockPtr() const { return !order.empty(); }
+
+ bool dimHasModulo(uint32_t dim) const {
+ assert(
+ !isBlockPtr() &&
+ "Analysis should not check modulo if PtrState describes block pointer");
+
+ assert(dim < getRank(... | I don't think this will work with our current code, but it's good to have :+1: I'll create a ticket to take a look at this. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,481 | intel | etiotto | @@ -50,6 +50,30 @@ struct PtrState {
return offsets.size();
}
+ bool isBlockPtr() const { return !order.empty(); }
+
+ bool dimHasModulo(uint32_t dim) const {
+ assert(
+ !isBlockPtr() &&
+ "Analysis should not check modulo if PtrState describes block pointer");
+
+ assert(dim < getRank(... | add msg |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,481 | intel | etiotto | @@ -50,6 +50,30 @@ struct PtrState {
return offsets.size();
}
+ bool isBlockPtr() const { return !order.empty(); }
+
+ bool dimHasModulo(uint32_t dim) const { | What is this function really doing ? What does it means it has modulo. Can you add a comment (perhaps with example). |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,481 | intel | etiotto | @@ -50,6 +50,30 @@ struct PtrState {
return offsets.size();
}
+ bool isBlockPtr() const { return !order.empty(); }
+
+ bool dimHasModulo(uint32_t dim) const {
+ assert(
+ !isBlockPtr() &&
+ "Analysis should not check modulo if PtrState describes block pointer");
+
+ assert(dim < getRank(... | same as above, please add documentation |
intel-xpu-backend-for-triton | github_2023 | python | 1,092 | intel | chengjunlu | @@ -0,0 +1,277 @@
+"""
+Block Pointer (Experimental) | Remove these comments. Clean up the code just for benchmark usage. |
intel-xpu-backend-for-triton | github_2023 | python | 1,092 | intel | chengjunlu | @@ -0,0 +1,277 @@
+"""
+Block Pointer (Experimental)
+============================
+This tutorial will guide you through writing a matrix multiplication algorithm that utilizes block pointer semantics.
+These semantics are more friendly for Triton to optimize and can result in better performance on specific hardware.
+... | I think the `num_stages=3` for best performance |
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