repo_name stringlengths 1 62 | dataset stringclasses 1
value | lang stringclasses 11
values | pr_id int64 1 20.1k | owner stringlengths 2 34 | reviewer stringlengths 2 39 | diff_hunk stringlengths 15 262k | code_review_comment stringlengths 1 99.6k |
|---|---|---|---|---|---|---|---|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,282 | intel | FMarno | @@ -0,0 +1,27 @@
+//===- Mangling.h - Function name mangling utilities -----------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----... | do you need to expose getTypeMangling? Why can everything not just go through the mangle function? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,282 | intel | FMarno | @@ -0,0 +1,51 @@
+#include "Mangling.h"
+
+#include "mlir/IR/BuiltinTypes.h"
+#include "mlir/Support/LLVM.h"
+
+#include "llvm/ADT/TypeSwitch.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace mlir;
+
+namespace mlir {
+namespace triton {
+namespace gpu {
+namespace intel {
+std::string getTypeMangling(Type t... | NIT, I personally think just using the string append function directly is simpler and strings are basically vectors so it's not inefficient. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,282 | intel | FMarno | @@ -1023,8 +998,8 @@ struct TritonSubGroupReduceLowering
if (useCluster)
fnName += "clustered_";
fnName += "reduce_" + stringifyReduceKind(op.getKind()).str();
- fnName =
- "_Z" + std::to_string(fnName.size()) + fnName + getTypeMangling(val_ty);
+ fnName = "_Z" + std::to_string(fnName.size... | could this be replaced with a call to mangle |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,282 | intel | FMarno | @@ -0,0 +1,135 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "Dialect/TritonIntelGPU/Transforms/Utility.h"
+#include "Utils/Mangling.h"
+
+#include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Support/LLVM.h"
+
+#include "llvm/ADT/TypeSwitch.h"
+
+using namespace mlir;
+
+namespace {
+static bool isBF16OrVec... | hopefully this can all be handled by the spir-v translator tool one day. |
intel-xpu-backend-for-triton | github_2023 | others | 1,282 | intel | FMarno | @@ -1,59 +1,68 @@
-// RUN: triton-opt %s -split-input-file --convert-triton-intel-gpu-to-llvm | FileCheck %s
+// RUN: triton-opt %s -split-input-file --convert-triton-intel-gpu-to-llvm | FileCheck %s --check-prefixes=CHECK,CHECK-SCALAR
+// RUN: env TRITON_INTEL_ENABLE_BLOCK_PTR=1 triton-opt %s -split-input-file --conve... | Why are you dropping the check for the function declaration? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,282 | intel | etiotto | @@ -0,0 +1,132 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "Dialect/TritonIntelGPU/Transforms/Utility.h"
+#include "Utils/Mangling.h"
+
+#include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Support/LLVM.h"
+
+#include "llvm/ADT/TypeSwitch.h"
+
+using namespace mlir;
+
+namespace {
+static bool isBF16OrTen... | static isn't necessary given the function definitions are enclosed in an anonymous namespace. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,282 | intel | etiotto | @@ -0,0 +1,132 @@
+#include "PatternTritonGPUOpToLLVM.h"
+
+#include "Dialect/TritonIntelGPU/Transforms/Utility.h"
+#include "Utils/Mangling.h"
+
+#include "mlir/Dialect/Arith/IR/Arith.h"
+#include "mlir/Support/LLVM.h"
+
+#include "llvm/ADT/TypeSwitch.h"
+
+using namespace mlir;
+
+namespace {
+static bool isBF16OrTen... | The function name implies that a vector type will always be returned but I think is possible the function will return a scalar. The function name isn't quite conveying that. |
intel-xpu-backend-for-triton | github_2023 | python | 1,261 | intel | whitneywhtsang | @@ -218,6 +218,8 @@ def make_llir(src, metadata, options):
paths = [path for (name, path) in options.extern_libs]
llvm.link_extern_libs(llvm_mod, paths)
llvm.optimize_module(llvm_mod, llvm.OPTIMIZE_O3)
+ intel.post_process_llir(llvm_mod) | Can we only add the pass if `TRITON_INTEL_ENABLE_ADDRESS_PAYLOAD_OPT` env var is used? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,262 | intel | whitneywhtsang | @@ -1036,6 +1036,9 @@ struct TritonSubGroupReduceLowering
LLVM::LLVMFuncOp funcOp =
LLVM::lookupOrCreateFn(moduleOp, funcName, argTypes, val_ty);
funcOp.setCConv(LLVM::cconv::CConv::SPIR_FUNC);
+ auto convergentAttr =
+ rewriter.getArrayAttr(StringAttr::get(op->getContext(), "convergent"));... | Attributes on function and call op should match, can you please add convergent to the call op as well? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,262 | intel | whitneywhtsang | @@ -86,8 +86,66 @@ bool TargetInfo::warpReduce(ConversionPatternRewriter &rewriter, Location loc,
SmallVector<Value> &acc, triton::ReduceOp op,
unsigned numLaneToReduce,
unsigned interleave) const {
- assert("TODO: implement warpRed... | ```suggestion
// Horizontal reduce with interleave stride not support.
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,262 | intel | whitneywhtsang | @@ -86,8 +86,66 @@ bool TargetInfo::warpReduce(ConversionPatternRewriter &rewriter, Location loc,
SmallVector<Value> &acc, triton::ReduceOp op,
unsigned numLaneToReduce,
unsigned interleave) const {
- assert("TODO: implement warpRed... | can use TypeSwitch? |
intel-xpu-backend-for-triton | github_2023 | others | 1,262 | intel | whitneywhtsang | @@ -1370,6 +1370,275 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 1 :
// -----
+// CHECK-LABEL: reduce_wave_all
+#blocked = #triton_gpu.blocked<{sizePerThread = [8, 1], threadsPerWarp = [32, 1], warpsPerCTA = [1, 1], order = [1, 0], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAO... | missing a check to WaveAll here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,262 | intel | FMarno | @@ -86,8 +87,67 @@ bool TargetInfo::warpReduce(ConversionPatternRewriter &rewriter, Location loc,
SmallVector<Value> &acc, triton::ReduceOp op,
unsigned numLaneToReduce,
unsigned interleave) const {
- assert("TODO: implement warpRed... | ```suggestion
auto reduceKind =
llvm::TypeSwitch<mlir::Operation *, std::optional<TritonGEN::ReduceKind>>(
reduceOp)
.Case<arith::AddFOp>([](auto) { return TritonGEN::ReduceKind::FSUM; })
.Case<arith::MaxNumFOp>(
[](auto) { return TritonGEN::ReduceKind::FMAX; })... |
intel-xpu-backend-for-triton | github_2023 | others | 1,262 | intel | etiotto | @@ -3,43 +3,24 @@
// COM: Tests reduction when threads_per_warp < num_warps.
#blocked = #triton_gpu.blocked<{sizePerThread = [1], threadsPerWarp = [32], warpsPerCTA = [64], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
-module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" ... | The previous code was checking that the function argument have the expected value. We should do the same even with the new API! Please check that the arguments passed to function are correct. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,262 | intel | etiotto | @@ -86,8 +87,53 @@ bool TargetInfo::warpReduce(ConversionPatternRewriter &rewriter, Location loc,
SmallVector<Value> &acc, triton::ReduceOp op,
unsigned numLaneToReduce,
unsigned interleave) const {
- assert("TODO: implement warpRed... | not support -> not supported |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,262 | intel | etiotto | @@ -86,8 +87,53 @@ bool TargetInfo::warpReduce(ConversionPatternRewriter &rewriter, Location loc,
SmallVector<Value> &acc, triton::ReduceOp op,
unsigned numLaneToReduce,
unsigned interleave) const {
- assert("TODO: implement warpRed... | The comment mentions the underlying operation the SubGroupReduceOp which is an implementation detail. Better to make it more generic. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,262 | intel | etiotto | @@ -86,8 +87,53 @@ bool TargetInfo::warpReduce(ConversionPatternRewriter &rewriter, Location loc,
SmallVector<Value> &acc, triton::ReduceOp op,
unsigned numLaneToReduce,
unsigned interleave) const {
- assert("TODO: implement warpRed... | why not use -> ? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,262 | intel | etiotto | @@ -86,8 +87,53 @@ bool TargetInfo::warpReduce(ConversionPatternRewriter &rewriter, Location loc,
SmallVector<Value> &acc, triton::ReduceOp op,
unsigned numLaneToReduce,
unsigned interleave) const {
- assert("TODO: implement warpRed... | Please refrain from using `auto` when the type isn't clear. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,262 | intel | etiotto | @@ -86,8 +87,53 @@ bool TargetInfo::warpReduce(ConversionPatternRewriter &rewriter, Location loc,
SmallVector<Value> &acc, triton::ReduceOp op,
unsigned numLaneToReduce,
unsigned interleave) const {
- assert("TODO: implement warpRed... | Is it always true that the first operand of the terminator instruction is a reduce operation in this context?
The variable name imply so. If this is the case one should add an assert. It it is not always true the variable name should be generic. |
intel-xpu-backend-for-triton | github_2023 | others | 1,259 | intel | etiotto | @@ -3,8 +3,8 @@
module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 32 : i32, triton_gpu.shared = 0 : i32, "triton_gpu.threads-per-warp" = 1 : i32} {
// CHECK-DAG: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32, ve... | Add attributes for the ptr argument (nonnull). Does the function really need to be convergent. The function attributes should be nounwind (assuming the function will not throw an exception) and the memory semantics should also be added. |
intel-xpu-backend-for-triton | github_2023 | others | 1,259 | intel | etiotto | @@ -3,8 +3,8 @@
module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 32 : i32, triton_gpu.shared = 0 : i32, "triton_gpu.threads-per-warp" = 1 : i32} {
// CHECK-DAG: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32, ve... | Same comments for all the OCL function you had. |
intel-xpu-backend-for-triton | github_2023 | others | 1,259 | intel | etiotto | @@ -0,0 +1,307 @@
+// RUN: triton-opt -convert-tritongen-to-llvm -split-input-file %s | FileCheck %s
+
+// CHECK: llvm.func spir_funccc @_Z40intel_sub_group_2d_block_read_8b_8r32x1cPU3AS1viiiDv2_iPt(!llvm.ptr<1>, i32, i32, i32, vector<2xi32>, !llvm.ptr) attributes {passthrough = ["convergent"]}
+
+llvm.func @triton_gen... | These tests are duplicates (only test different variants) and I think is better to limit the number of tests we have to maintain. Add one only please. |
intel-xpu-backend-for-triton | github_2023 | others | 1,259 | intel | etiotto | @@ -3,8 +3,8 @@
module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 32 : i32, triton_gpu.shared = 0 : i32, "triton_gpu.threads-per-warp" = 1 : i32} {
// CHECK-DAG: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32, ve... | This needs passthrough attribute to describe the memory semantics (function can only read the memory pointed to by the ptr argument). Applies to all similar cases. |
intel-xpu-backend-for-triton | github_2023 | others | 1,259 | intel | etiotto | @@ -0,0 +1,271 @@
+// RUN: triton-opt -convert-tritongen-to-llvm -split-input-file %s | FileCheck %s
+
+// CHECK: llvm.func spir_funccc @_Z40intel_sub_group_2d_block_read_8b_8r32x1cPU3AS1viiiDv2_iPt(!llvm.ptr<1> {llvm.nonnull}, i32, i32, i32, vector<2xi32>, !llvm.ptr) attributes {passthrough = ["nounwind"]} | Add passthrough attribute for mem semantics |
intel-xpu-backend-for-triton | github_2023 | others | 1,259 | intel | etiotto | @@ -235,6 +235,14 @@ llvm.func @matrix_2Dblockload(%ptr : !llvm.ptr, %base_width : i32, %base_height
// -----
+llvm.func @matrix_2Dblockload(%ptr : !llvm.ptr, %base_width : i32, %base_height : i32, %base_pitch : i32, %x : i32, %y : i32) {
+ // expected-error @+1 {{'triton_gen.2Dblockload' op expecting tile_width ... | .. equal to 16 when vnni_transform is true |
intel-xpu-backend-for-triton | github_2023 | others | 1,259 | intel | etiotto | @@ -297,48 +297,6 @@ llvm.func @triton_gen.dpas.f32(%c : vector<8xf32>, %a : vector<4xf32>, %b : vect
// -----
-// CHECK: llvm.func spir_funccc @_Z40intel_sub_group_2d_block_read_8b_8r32x2cPU3AS1viiiDv2_iPt(!llvm.ptr<1> {llvm.nonnull}, i32, i32, i32, vector<2xi32>, !llvm.ptr) attributes {passthrough = ["nounwind"]... | What happened to this tests, where they moved? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,259 | intel | etiotto | @@ -48,26 +48,32 @@ template <typename Op> static LogicalResult verifyInput(Op op) {
return op->emitOpError("expecting tile_height to be 1, 2, 4, 8, 16, or 32");
uint32_t TileWidth = op.getTileWidth();
- switch (op.getElemSizeInBits()) {
- case 32:
- if (TileWidth != 8 && TileWidth != 16)
- return o... | ```
if (op.getVnniTransform() && TileWidth != 16)) {
return ...
if (!op.getVnniTransform())
switch....
|
intel-xpu-backend-for-triton | github_2023 | cpp | 1,270 | intel | victor-eds | @@ -169,6 +208,9 @@ class TritonGPUToLLVMPipelineManager {
using namespace mlir;
using namespace mlir::triton;
+ // should run before other patterns need the SPIRV-ENV attr
+ patterns.add<AddSPIRVEnvPattern>(&typeConverter.getContext(), benefit); | Can we define a higher benefit as a constant in the header where all benefits are defined and use it here? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,270 | intel | victor-eds | @@ -65,7 +68,8 @@ struct ConvertTritonGPUToLLVM
using ConvertTritonIntelGPUToLLVMBase::ConvertTritonIntelGPUToLLVMBase;
void getDependentDialects(DialectRegistry ®istry) const override { | I'm surprised we have to do this. We may be defining the pass in a weird way. Not to be handled in this PR, ofc. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,270 | intel | whitneywhtsang | @@ -26,6 +26,7 @@ constexpr int patternBenefitDefault = 1;
constexpr int patternBenefitPrioritizeOverLLVMConversions = 10;
constexpr int patternBenefitClampOptimizedPattern = 20;
constexpr int patternBenefitConvertLayoutOptimizedPattern = 20;
+constexpr int patternBenefitAddSPIRVEnv = 30; | I see the benefit of having all the benefits at the same place, but having changes in common file, i.e., not under third_party/intel, could impact upstreaming. We are working in the direction if minimizing changes in common files, so at some point, all changes requires are in `third_party/intel`, then we could be a plu... |
intel-xpu-backend-for-triton | github_2023 | others | 1,270 | intel | etiotto | @@ -0,0 +1,5 @@
+// RUN: triton-opt %s --convert-triton-intel-gpu-to-llvm | FileCheck %s
+
+// COM: check that the spirv target env is inserted
+// CHECK: spirv.target_env{{.*}}#spirv.resource_limits<subgroup_size = 16> | Where is the spirv.target_env added? It should be to the module? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,270 | intel | etiotto | @@ -135,6 +136,44 @@ struct FuncOpConversion : public ConvertOpToLLVMPattern<triton::FuncOp> {
int numWarps{0};
};
+struct AddSPIRVEnvPattern : public mlir::OpRewritePattern<ModuleOp> {
+
+ using mlir::OpRewritePattern<ModuleOp>::OpRewritePattern;
+
+ LogicalResult matchAndRewrite(ModuleOp op,
+ ... | [nit]: the :: in `::mlir` is not required. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,290 | intel | etiotto | @@ -36,43 +42,61 @@ template <typename Op> static LogicalResult verifyInput(Op op) {
return op->emitOpError(
"transpose and vnni transform are mutually exclusive");
- std::optional<int64_t> width = getConstantIntValue(op.getBaseWidth());
- std::optional<int64_t> pitch = getConstantIntValue(op.getBaseP... | I think the exact name of the attribute is `vnni_transform` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,290 | intel | etiotto | @@ -173,21 +197,42 @@ LogicalResult TritonGEN::MatrixDPASOp::verify() {
//===----------------------------------------------------------------------===//
LogicalResult TritonGEN::Matrix2DBlockLoadOp::verify() {
- return verifyInput(*this);
+ if (verifyMatrixInput(*this).failed())
+ return failure();
+
+ Vector... | can the expected value be printed in the msg? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,290 | intel | etiotto | @@ -36,43 +42,61 @@ template <typename Op> static LogicalResult verifyInput(Op op) {
return op->emitOpError(
"transpose and vnni transform are mutually exclusive");
- std::optional<int64_t> width = getConstantIntValue(op.getBaseWidth());
- std::optional<int64_t> pitch = getConstantIntValue(op.getBaseP... | tile_width when vnni_transform is true should ... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,290 | intel | etiotto | @@ -36,43 +42,61 @@ template <typename Op> static LogicalResult verifyInput(Op op) {
return op->emitOpError(
"transpose and vnni transform are mutually exclusive");
- std::optional<int64_t> width = getConstantIntValue(op.getBaseWidth());
- std::optional<int64_t> pitch = getConstantIntValue(op.getBaseP... | `tile_width for 32 bit elements should be equal to systolic depth (8 elements) for matrix A and the subgroup size (print value of subgroup size) for matrix B` |
intel-xpu-backend-for-triton | github_2023 | others | 1,290 | intel | etiotto | @@ -177,133 +177,197 @@ llvm.func @triton_gen.dpas(%c : vector<8xf32>, %a : vector<8xi16>, %b : vector<8
// -----
+llvm.func @matrix_2Dblockload(%ptr : !llvm.ptr, %base_height : i32, %x : i32, %y : i32) {
+ %base_width = llvm.mlir.constant(4 : i32) : i32
+ %base_pitch = llvm.mlir.constant(2 : i32) : i32
+ // ex... | change transpose back to false |
intel-xpu-backend-for-triton | github_2023 | others | 1,290 | intel | etiotto | @@ -177,133 +177,197 @@ llvm.func @triton_gen.dpas(%c : vector<8xf32>, %a : vector<8xi16>, %b : vector<8
// -----
+llvm.func @matrix_2Dblockload(%ptr : !llvm.ptr, %base_height : i32, %x : i32, %y : i32) {
+ %base_width = llvm.mlir.constant(4 : i32) : i32
+ %base_pitch = llvm.mlir.constant(2 : i32) : i32
+ // ex... | // expected-error @+1 {{'triton_gen.2Dblockload' op tile_width for 32 bit elements should be equal to either be 8 or 16}} |
intel-xpu-backend-for-triton | github_2023 | python | 1,294 | intel | etiotto | @@ -159,7 +159,7 @@ def check_cuda_or_hip(device):
# CUDA and HIP both use pytorch device 'cuda'. Other backends like Intel
# GPU do not.
if device not in ['cuda']:
- pytest.xfail("Only for cuda")
+ pytest.skip("Only for cuda or HIP") | xfail is fine here. |
intel-xpu-backend-for-triton | github_2023 | python | 1,294 | intel | etiotto | @@ -0,0 +1,45 @@
+import pytest
+import torch
+import triton
+import os
+
+
+def is_interpreter():
+ return os.environ.get('TRITON_INTERPRET', '0') == '1'
+
+
+def is_cuda():
+ return not is_interpreter() and \
+ triton.runtime.driver.active.get_current_target().backend == "cuda"
+
+
+@pytest.mark.parametr... | skip -> xfail (assume it is being run). |
intel-xpu-backend-for-triton | github_2023 | python | 1,294 | intel | etiotto | @@ -0,0 +1,49 @@
+import torch
+
+import pytest
+import os
+
+import triton
+import triton.language as tl
+
+test_stdout = 'Hello From First Instruction of GPU Kernel: kernel1\ttest_gpuhello.py:17:4\n\
+Hello From First Instruction of GPU Kernel: kernel2\ttest_gpuhello.py:23:4\n\
+Hello From First Instruction of GPU Ke... | open issue to port this to XPU |
intel-xpu-backend-for-triton | github_2023 | others | 1,280 | intel | etiotto | @@ -204,7 +204,7 @@ llvm.func @matrix_2Dblockload(%ptr : !llvm.ptr, %base_height : i32, %x : i32, %y
// -----
llvm.func @matrix_2Dblockload(%ptr : !llvm.ptr, %base_width : i32, %base_height : i32, %base_pitch : i32, %x : i32, %y : i32) {
- // expected-error @+1 {{'triton_gen.2Dblockload' op tile_width for 32 bit e... | @whitneywhtsang Please revert, the msg is not meaningful. Matrix A or B do not make sense because the 2D store operation doesn't have those operands. |
intel-xpu-backend-for-triton | github_2023 | python | 1,258 | intel | whitneywhtsang | @@ -222,32 +223,47 @@ def matmul(a, b, res_dtype):
# Still we can test our matrix multiplication with block pointers against a native torch implementation (i.e., cuBLAS).
torch.manual_seed(0)
-for dtype, res_dtype in [(torch.float16, torch.float32), (torch.bfloat16, torch.float32), (torch.int8, torch.int32),
- ... | ```suggestion
torch_output = torch.matmul(a.to(device='cpu', dtype=accum_dtype),
``` |
intel-xpu-backend-for-triton | github_2023 | others | 1,258 | intel | etiotto | @@ -140,3 +140,27 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 32
tt.return
}
}
+
+// -----
+
+// COM: Checks the correct lowering of a 16-bit 2D-block-store.
+
+module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 32 : i32, triton_gpu.shared = 0 : i32... | Remove `triton_gpu.num-ctas`, I do not think is required. |
intel-xpu-backend-for-triton | github_2023 | others | 1,258 | intel | etiotto | @@ -140,3 +140,27 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 32
tt.return
}
}
+
+// -----
+
+// COM: Checks the correct lowering of a 16-bit 2D-block-store.
+
+module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 32 : i32, triton_gpu.shared = 0 : i32... | can tt.divisibility be removed ? |
intel-xpu-backend-for-triton | github_2023 | others | 1,278 | intel | etiotto | @@ -297,7 +297,7 @@ llvm.func @triton_gen.dpas.f32(%c : vector<8xf32>, %a : vector<4xf32>, %b : vect
// -----
-// CHECK: llvm.func spir_funccc @intel_subgroup_block_read_u8_m8k32v2(!llvm.ptr<1>, i32, i32, i32, vector<2xi32>) -> vector<16xi16> attributes {passthrough = ["convergent"]}
+// CHECK: llvm.func spir_func... | the memory semantics associated with the ptr argument are missing. Can you add them please ? |
intel-xpu-backend-for-triton | github_2023 | python | 1,190 | intel | EikanWang | @@ -6,6 +6,26 @@
from typing import Any, Dict, List
from . import language as tl
+try:
+ import torch
+ import intel_extension_for_pytorch # type: ignore # noqa: F401 | From the product perspective, if users install both PyTorch and IPEX, there will be no opportunity to measure Triton kernel time within the stock PyTorch. |
intel-xpu-backend-for-triton | github_2023 | python | 1,190 | intel | Stonepia | @@ -6,6 +6,29 @@
from typing import Any, Dict, List
from . import language as tl
+if "intel_extension_for_pytorch" in sys.modules:
+ import torch
+
+ def Event(**kwargs):
+ return torch.xpu.Event(**kwargs)
+
+ USE_WALL_TIME = False
+else: | We no longer need this in PyTorch 2.3. The API could follow the stock Triton. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,276 | intel | whitneywhtsang | @@ -47,37 +44,39 @@ static uint32_t findKernels(llvm::Module &M,
}
void init_triton_intel_passes_ttir(py::module &&m) {
- ADD_PASS_WRAPPER_OPT_1("add_convert_to_ttgpuir_warp",
- mlir::triton::createConvertTritonToTritonGPUWarp,
- unsigned);
+ ADD_PASS_WRAPPER_OPT_1(... | ```suggestion
intel::createConvertTritonToTritonGPUWarp, unsigned);
``` |
intel-xpu-backend-for-triton | github_2023 | python | 1,256 | intel | etiotto | @@ -99,24 +99,28 @@
@triton.autotune(
configs=[
- triton.Config({'BLOCK_SIZE_M': 128, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 64, 'GROUP_SIZE_M': 4}, num_stages=2,
- num_warps=32),
- triton.Config({'BLOCK_SIZE_M': 64, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 32, 'GROUP_SIZE_M': 4}, n... | I wonder whether we need an option to autotune injecting split barriers. Is there any known case that is _significantly_ slower if split barriers are injected ? |
intel-xpu-backend-for-triton | github_2023 | python | 1,256 | intel | etiotto | @@ -48,6 +48,8 @@ class XPUOptions:
extern_libs: dict = None
debug: bool = False
backend_name: str = 'intel'
+ prefetch_distance: int = 2
+ inject_split_barriers: bool = False | I do not think this should be a tunable. |
intel-xpu-backend-for-triton | github_2023 | python | 1,256 | intel | LiyangLingIntel | @@ -99,23 +99,11 @@
@triton.autotune(
configs=[
- triton.Config({'BLOCK_SIZE_M': 128, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 64, 'GROUP_SIZE_M': 4}, num_stages=2,
- num_warps=32),
- triton.Config({'BLOCK_SIZE_M': 64, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 32, 'GROUP_SIZE_M': 4}, n... | Can you keep this one `'BLOCK_SIZE_M': 256, 'BLOCK_SIZE_N': 128`? From my practice, this would have 3-5% perf gain than `BLOCK_SIZE_M': 256, 'BLOCK_SIZE_N': 256` for some big M small N cases. |
intel-xpu-backend-for-triton | github_2023 | python | 1,240 | intel | whitneywhtsang | @@ -79,8 +81,7 @@ def make_ttgir(mod, metadata, opt, device_arch):
# FIXME: Use a better way to check if prefetch instructions are supported once available.
# Prefetch instruction is not available in older drivers.
if Version(metadata["target"].arch['driver_version']) > Version("1... | Why not use `opt.num_stages` directly? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,240 | intel | Dewei-Wang-sh | @@ -138,18 +138,20 @@ class PrefetchBlockPass
public:
/// Groups information for a candidate load.
struct LoadInfo {
- LoadInfo(tt::AdvanceOp advance, SmallVector<Value> offsets,
+ LoadInfo(tt::DotOp dot, tt::AdvanceOp advance, SmallVector<Value> offsets, | this pass is meant to be general, not bound to dot op.
so try to move prefetch after load. |
intel-xpu-backend-for-triton | github_2023 | python | 1,240 | intel | whitneywhtsang | @@ -48,7 +48,9 @@ class XPUOptions:
extern_libs: dict = None
debug: bool = False
backend_name: str = 'intel'
- isBlockPtrEnabled: bool = os.environ.get("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") == "1"
+ is_block_ptr_enabled: bool = os.environ.get("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") == "1"
+ prefet... | Let's try to be consistent with our usages of `os.getenv` and `os.environ.get`. Unless there is a reason to be different? |
intel-xpu-backend-for-triton | github_2023 | python | 1,240 | intel | etiotto | @@ -48,14 +48,16 @@ class XPUOptions:
extern_libs: dict = None
debug: bool = False
backend_name: str = 'intel'
- isBlockPtrEnabled: bool = os.environ.get("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") == "1"
+ is_block_ptr_enabled: bool = os.environ.get("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") == "1"
+ pref... | I do not think this is necessary. Introducing too many tuning flags is confusing. What is the difference in performance for cases that benefit from injecting the split barrier ? And how much does injecting a split barrier by default hurts for some configurations? |
intel-xpu-backend-for-triton | github_2023 | python | 1,240 | intel | etiotto | @@ -122,6 +123,8 @@ def parse_target(self, tgt_prop) -> dict:
def parse_options(self, opts) -> Any:
args = {k: opts[k] for k in XPUOptions.__dataclass_fields__.keys() if k in opts}
args["allow_fp8e4nv"] = True
+ # Use num_stages to represent prefetch distance to make it tunable.
+ a... | remove num_stages please and replace it with prefetch_distance. Having both is not necessary. |
intel-xpu-backend-for-triton | github_2023 | python | 1,240 | intel | whitneywhtsang | @@ -48,14 +48,14 @@ class XPUOptions:
extern_libs: dict = None
debug: bool = False
backend_name: str = 'intel'
- isBlockPtrEnabled: bool = os.environ.get("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") == "1"
+ is_block_ptr_enabled: bool = os.environ.get("TRITON_INTEL_ENABLE_BLOCK_PTR", "0") == "1"
de... | Let's change back to use `os.getenv` in this case, to be consistent with nvidia and amd. |
intel-xpu-backend-for-triton | github_2023 | others | 1,172 | intel | Dewei-Wang-sh | @@ -223,3 +223,59 @@ tt.func public @matmul_kernel_with_block_pointers(%arg0: !tt.ptr<i8> {tt.divisib
tt.store %tptr_c, %35#0 {boundaryCheck = array<i32: 0, 1>} : !tt.ptr<tensor<8x32xi32, #warp>>
tt.return
}
+
+// -----
+
+// COM: Test transformation for tf32 datatype
+
+// CHECK-LABEL: @matmul_kernel_with_block... | nit: maybe we can use a simpler lit test that has 1 loadA 1 loadB 1dot to ease the effort. |
intel-xpu-backend-for-triton | github_2023 | python | 1,172 | intel | Dewei-Wang-sh | @@ -243,8 +244,9 @@ def matmul(a, b, res_dtype):
# Note: the torch.matmul and Triton implementations uses different
# algorithms so we need to adjust tolerance.
+ atol = 4e-2 if dtype == torch.float32 else 1e-4 | for this, we can double confirm with other teams(kernel library, igc, etc) that used tf32 gemm previously.
to make sure this is as expected. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,172 | intel | mfrancepillois | @@ -120,10 +122,12 @@ class LoadStorePrefetchOpConversion
assert(tensorType.getRank() <= 2 &&
"only support 1d/2d load/store/prefetch for now");
+ Type elemType = tensorType.getElementType();
unsigned dataSize = tensorType.getElementType().getIntOrFloatBitWidth();
unsigned blockHeight = ... | ```suggestion
"only support 8/16/32/64 block");
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,172 | intel | FMarno | @@ -12,9 +12,11 @@ using namespace mlir::triton::gpu::intel;
namespace {
VectorType getVectorType(RankedTensorType tensorType, Type elemType) {
- unsigned ratio =
- elemType.getIntOrFloatBitWidth() / tensorType.getElementTypeBitWidth();
- unsigned num = (tensorType.getNumElements() / 16) / ratio;
+ // Deter... | I'd appreciate some parentheses since I can't remember the order of operations for this case |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,172 | intel | FMarno | @@ -219,12 +224,14 @@ class DotOpConversion : public ConvertTritonGPUOpToLLVMPattern<DotOp> {
LogicalResult
matchAndRewrite(DotOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
- auto encodePrecision = [&](Type type) -> TritonGEN::PrecisionType {
+ auto encod... | ```suggestion
[](Type type, InputPrecisionAttr attr) -> TritonGEN::PrecisionType {
```
I think you can get rid of this since rewriter is no longer used in the lambda |
intel-xpu-backend-for-triton | github_2023 | python | 1,172 | intel | etiotto | @@ -232,6 +233,8 @@ def matmul(a, b, res_dtype):
triton_output = matmul(a, b, res_dtype)
if dtype.is_floating_point:
+ torch.xpu.set_fp32_math_mode(torch.xpu.utils.FP32MathMode.TF32 if dtype == | cool! |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | FMarno | @@ -158,12 +158,19 @@ DpasEncodingAttr::getDPASRepetitions(ArrayRef<int64_t> shape, int opIdx) const {
auto shapePerWarp = getShapeA();
return {std::max<int64_t>(1, shape[0] / (shapePerWarp[0] * warpsPerCTA[0])),
std::max<int64_t>(1, shape[1] / shapePerWarp[1])};
- } else {
+ } else if (opIdx =... | this assert is a little redundant now, maybe move it to the `opIdx==2` branch |
intel-xpu-backend-for-triton | github_2023 | others | 1,212 | intel | FMarno | @@ -0,0 +1,68 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm --canonicalize | FileCheck %s --implicit-check-not=llvm.inline_asm
+
+// CHECK-DAG: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockWrite.v8i16(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, ... | use `dot0` |
intel-xpu-backend-for-triton | github_2023 | others | 1,212 | intel | FMarno | @@ -0,0 +1,68 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm --canonicalize | FileCheck %s --implicit-check-not=llvm.inline_asm
+
+// CHECK-DAG: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockWrite.v8i16(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, ... | use `dot0` |
intel-xpu-backend-for-triton | github_2023 | others | 1,212 | intel | FMarno | @@ -0,0 +1,68 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm --canonicalize | FileCheck %s --implicit-check-not=llvm.inline_asm
+
+// CHECK-DAG: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockWrite.v8i16(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, ... | remove unused args, same for the other test |
intel-xpu-backend-for-triton | github_2023 | others | 1,212 | intel | FMarno | @@ -0,0 +1,68 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm --canonicalize | FileCheck %s --implicit-check-not=llvm.inline_asm
+
+// CHECK-DAG: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockWrite.v8i16(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, ... | I think we could avoid these ext instruction by making arg3 etc an i64, same for the other test |
intel-xpu-backend-for-triton | github_2023 | others | 1,212 | intel | FMarno | @@ -0,0 +1,68 @@
+// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm --canonicalize | FileCheck %s --implicit-check-not=llvm.inline_asm | are canonicalize and intel allocate shared memory needed? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | FMarno | @@ -638,12 +638,117 @@ struct StoreOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::StoreOp>(converter, benefit),
LoadStoreConversionBase(targetInfo, axisAnalysisPass) {}
+ LogicalResult
+ rewriteTensorPointerStore(triton::StoreOp op, OpAdaptor adaptor,
+ ConversionP... | this seems unneeded to me since you've already returned if `isTensorPointerType` is true, unless `isTensorPointerType` has side effects. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | victor-eds | @@ -638,12 +638,117 @@ struct StoreOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::StoreOp>(converter, benefit),
LoadStoreConversionBase(targetInfo, axisAnalysisPass) {}
+ LogicalResult
+ rewriteTensorPointerStore(triton::StoreOp op, OpAdaptor adaptor,
+ ConversionP... | I think this `assert`'s not needed |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | FMarno | @@ -638,12 +638,117 @@ struct StoreOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::StoreOp>(converter, benefit),
LoadStoreConversionBase(targetInfo, axisAnalysisPass) {}
+ LogicalResult
+ rewriteTensorPointerStore(triton::StoreOp op, OpAdaptor adaptor,
+ ConversionP... | Can all tensor pointer store be converted to a 2D block store?
If no, is there a fall back path? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | victor-eds | @@ -638,12 +638,117 @@ struct StoreOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::StoreOp>(converter, benefit),
LoadStoreConversionBase(targetInfo, axisAnalysisPass) {}
+ LogicalResult
+ rewriteTensorPointerStore(triton::StoreOp op, OpAdaptor adaptor,
+ ConversionP... | Unused var |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | victor-eds | @@ -638,12 +638,117 @@ struct StoreOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::StoreOp>(converter, benefit),
LoadStoreConversionBase(targetInfo, axisAnalysisPass) {}
+ LogicalResult
+ rewriteTensorPointerStore(triton::StoreOp op, OpAdaptor adaptor,
+ ConversionP... | If we're expecting this to always be non-null, we can `cast` instead of `dyn_cast` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | FMarno | @@ -638,12 +638,117 @@ struct StoreOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::StoreOp>(converter, benefit),
LoadStoreConversionBase(targetInfo, axisAnalysisPass) {}
+ LogicalResult
+ rewriteTensorPointerStore(triton::StoreOp op, OpAdaptor adaptor,
+ ConversionP... | I don't know if I'm going to far here, but it looks to me like `offsetX` increases by `numReps[1]*elemsPerInstr[1]` each inner loop, while `offsetY` increases by `numReps[0]*elemsPerInstr[0]` each outer loop, so you could avoid the multiplications in the loops and just use adds.
Maybe that is something best left to th... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | victor-eds | @@ -638,12 +638,117 @@ struct StoreOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::StoreOp>(converter, benefit),
LoadStoreConversionBase(targetInfo, axisAnalysisPass) {}
+ LogicalResult
+ rewriteTensorPointerStore(triton::StoreOp op, OpAdaptor adaptor,
+ ConversionP... | Not really a big deal, but we can generate:
```
%poison = llvm.mlir.poison : <elemsPerLane x eltTy>
%zero = llvm.mlir.zero : <elemsPerLane x i32>
%vecinit = llvm.insert_element %poison, %val : <elemsPerLane x eltTy>
%stored = llvm.shuffle_vector %vecinit, %poison, %zero : <elemsPerLane x eltTy>, <elemsPerLane x i3... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | victor-eds | @@ -638,12 +638,117 @@ struct StoreOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::StoreOp>(converter, benefit),
LoadStoreConversionBase(targetInfo, axisAnalysisPass) {}
+ LogicalResult
+ rewriteTensorPointerStore(triton::StoreOp op, OpAdaptor adaptor,
+ ConversionP... | Use `loc` here |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | FMarno | @@ -638,12 +638,113 @@ struct StoreOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::StoreOp>(converter, benefit),
LoadStoreConversionBase(targetInfo, axisAnalysisPass) {}
+ LogicalResult
+ rewriteTensorPointerStore(triton::StoreOp op, OpAdaptor adaptor,
+ ConversionP... | ```suggestion
Value dimWarpId0 = mul(multiDimWarpId[0], i32_val(elemsPerInstr[0]));
Value dimWarpId1 = mul(multiDimWarpId[1], i32_val(elemsPerInstr[1]));
Value warpId0Offset = add(dimWarpId0, offsetBaseY);
Value warpId1Offset = add(dimWarpId1, offsetBaseX);
for (int m = 0; m < numReps[0]; ++m) ... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | whitneywhtsang | @@ -638,12 +638,115 @@ struct StoreOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::StoreOp>(converter, benefit),
LoadStoreConversionBase(targetInfo, axisAnalysisPass) {}
+ LogicalResult
+ rewriteTensorPointerStore(triton::StoreOp op, OpAdaptor adaptor,
+ ConversionP... | minus one is already created in TritonGEN to LLVM lowering, so we don't need to minus one here. |
intel-xpu-backend-for-triton | github_2023 | others | 1,212 | intel | etiotto | @@ -0,0 +1,70 @@
+// RUN: triton-opt %s -split-input-file --convert-triton-intel-gpu-to-llvm | FileCheck %s --implicit-check-not=llvm.inline_asm
+
+// CHECK-DAG: llvm.func spir_funccc @llvm.genx.GenISA.LSC2DBlockWrite.v8i16(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32, vector<8xi16>)
+#dpas = #triton_i... | This test looks like the one above except for the element type. I think the test above is sufficient (adding too many tests adds maintenance costs). Pls remove this one. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | etiotto | @@ -158,12 +158,19 @@ DpasEncodingAttr::getDPASRepetitions(ArrayRef<int64_t> shape, int opIdx) const {
auto shapePerWarp = getShapeA();
return {std::max<int64_t>(1, shape[0] / (shapePerWarp[0] * warpsPerCTA[0])),
std::max<int64_t>(1, shape[1] / shapePerWarp[1])};
- } else {
- assert(opIdx == ... | add msg to assert |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | etiotto | @@ -638,12 +638,113 @@ struct StoreOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::StoreOp>(converter, benefit),
LoadStoreConversionBase(targetInfo, axisAnalysisPass) {}
+ LogicalResult
+ rewriteTensorPointerStore(triton::StoreOp op, OpAdaptor adaptor,
+ ConversionP... | Fix comment, this is a store operation. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,212 | intel | etiotto | @@ -638,12 +638,113 @@ struct StoreOpConversion
: ConvertTritonGPUOpToLLVMPattern<triton::StoreOp>(converter, benefit),
LoadStoreConversionBase(targetInfo, axisAnalysisPass) {}
+ LogicalResult
+ rewriteTensorPointerStore(triton::StoreOp op, OpAdaptor adaptor,
+ ConversionP... | auto -> MLIRContext (use static types rather than auto when the type is not transparent). Same for other cases. |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | whitneywhtsang | @@ -0,0 +1,216 @@
+//===- Attributes.h - Construct MLIR attributes -----------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | ```suggestion
/// Add function, return value, and parameters attributes to the list.
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | whitneywhtsang | @@ -0,0 +1,216 @@
+//===- Attributes.h - Construct MLIR attributes -----------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | [nit] To be consistent, can we either use `Attrs` or `Attributes` for all function names? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | whitneywhtsang | @@ -0,0 +1,216 @@
+//===- Attributes.h - Construct MLIR attributes -----------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | passthrough is a word.
```suggestion
AttrBuilder &addPassthroughAttribute(llvm::Attribute::AttrKind Kind);
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,436 @@
+//===- Attributes.cc - Construct MLIR attributes --------------------------===// | ```suggestion
//===- Attributes.cpp - Construct MLIR attributes -------------------------===//
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,436 @@
+//===- Attributes.cc - Construct MLIR attributes --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Can we use `SmallVector` instead? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,436 @@
+//===- Attributes.cc - Construct MLIR attributes --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | No need to sort if we insert in order as per above:
```suggestion
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,436 @@
+//===- Attributes.cc - Construct MLIR attributes --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | This may be more readable.
```suggestion
assert((!ExistingFnAttr || ExistingFnAttr->getName() == PassThroughAttrName) && "...");
if (!ExistingFnAttr) {
FnAttrs.append(NewFnAttr);
} else if (ExistingFnAttr->getName() == PassThroughAttrName) {
// Merge the 'passthrough' attribute lists.
... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,436 @@
+//===- Attributes.cc - Construct MLIR attributes --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | We know this should never happen, so we can assert out on `std::optional::operator*`
```suggestion
for (const NamedAttribute &NewNamedAttr : Attrs) {
NamedAttribute ExistingAttr =
*RetAttrs.getNamed(NewNamedAttr.getName());
RetAttrs.append(NewNamedAttr);
}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,436 @@
+//===- Attributes.cc - Construct MLIR attributes --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Readability.
```suggestion
} else {
llvm_unreachable("Unexpected attribute kind");
}
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,436 @@
+//===- Attributes.cc - Construct MLIR attributes --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Simpler, `SmallVector` should know how to do this efficiently.
```suggestion
ParamAttrs.append(Attrs.begin(), Attrs.end());
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,436 @@
+//===- Attributes.cc - Construct MLIR attributes --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Can we use `SmallVector`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,436 @@
+//===- Attributes.cc - Construct MLIR attributes --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Can we replace `isa + cast` with `dyn_cast`? |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,436 @@
+//===- Attributes.cc - Construct MLIR attributes --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | Use `static_cast` instead of C-style cast |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,436 @@
+//===- Attributes.cc - Construct MLIR attributes --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | ```suggestion
return containsInPassThrough(AttrName) || getAttribute(AttrName).has_value();
``` |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,216 @@
+//===- Attributes.h - Construct MLIR attributes -----------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | LLVM discourages this [here](https://bcain-llvm.readthedocs.io/projects/llvm/en/latest/ProgrammersManual/#passing-functions-and-other-callable-objects).
Can we use `llvm::function_ref<AttrBuilder &(AttrBuilder &, ...)>` instead and just do:
```c++
[](AttrBuilder &builder, ...) -> AttrBuilder & { return builder.foo... |
intel-xpu-backend-for-triton | github_2023 | cpp | 1,249 | intel | victor-eds | @@ -0,0 +1,436 @@
+//===- Attributes.cc - Construct MLIR attributes --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--... | C++ 17 headers are available already. However, if we use the `llvm::function_ref`, we should be able to just :
```suggestion
OpBuilder Builder(&Ctx);
StringRef AttrName = llvm::Attribute::getNameFromAttrKind(Kind);
NamedAttribute NamedAttr(createStringAttribute(AttrName, Dialect, Ctx),
... |
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