repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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rurume/openrisc_vision_hardware | ISE/or1200_spram_64x24.v | 10,895 | module MODULE1(
VAR24, VAR52, VAR32,
clk, rst, VAR46, VAR29, VAR49, addr, VAR4, VAR25
);
parameter VAR44 = 6;
parameter VAR38 = 24;
input VAR24;
input [VAR16 - 1:0] VAR32;
output VAR52;
input clk; input rst; input VAR46; input VAR29; input VAR49; input [VAR44-1:0] addr; input [VAR38-1:0] VAR4; output [VAR38-1:0] VAR25;... | gpl-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/neek/rtl/verilog/rom.v | 4,415 | module MODULE1 #(
parameter VAR17 = 5,
parameter VAR10 = 0
)
(
input VAR3,
input VAR13,
input [(VAR17 + 2) - 1:2] VAR14,
input VAR2,
input VAR9,
input [2:0] VAR6,
input [1:0] VAR18,
output reg [31:0] VAR19,
output reg VAR4
);
reg [VAR17-1:0] VAR1;
always @ (posedge VAR3 or posedge VAR13)
if (VAR13)
VAR19 <= 32'h1500000... | gpl-2.0 |
eda-globetrotter/PicenoDecoders | andy/design/viterbidec.v | 5,182 | module MODULE1 (VAR2, VAR18, clk, reset);
output VAR2;
input [1:0] VAR18;
input clk;
input reset;
wire VAR2;
wire [1:0] VAR4,VAR22,VAR28,VAR29;
wire [1:0] VAR19,VAR10,VAR13,VAR24;
wire VAR16,VAR3,VAR30,VAR5;
wire [3:0] VAR1,VAR15,VAR11,VAR32;
wire [3:0] VAR14, VAR26, VAR27, VAR21;
VAR25 VAR8 (VAR18[0], VAR18[1],
VAR4,V... | mit |
hly11/CollisionDetectionFPGA | hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0/synth/design_1_auto_us_0.v | 10,216 | module MODULE1 (
VAR62,
VAR27,
VAR48,
VAR9,
VAR50,
VAR6,
VAR20,
VAR59,
VAR90,
VAR29,
VAR85,
VAR28,
VAR19,
VAR72,
VAR32,
VAR61,
VAR34,
VAR5,
VAR4,
VAR74,
VAR73,
VAR65,
VAR16,
VAR2,
VAR12,
VAR83,
VAR1,
VAR14,
VAR89,
VAR53,
VAR51,
VAR76,
VAR46,
VAR38,
VAR87,
VAR95,
VAR69,
VAR60
);
input wire VAR62;
input wire VAR27;
input... | gpl-2.0 |
fbalakirev/red-pitaya-notes | cores/axis_level_cross_v1_0/axis_level_cross.v | 2,293 | module MODULE1 #
(
parameter integer VAR3 = 32,
parameter integer VAR6 = 8192,
parameter VAR11 = "VAR13"
)
(
input wire VAR9,
input wire VAR10,
input wire signed[VAR3-1:0] VAR5,
input wire VAR18,
input wire signed [VAR3-1:0] VAR17, input wire VAR4, output wire VAR7,
input wire VAR16,
output wire signed [VAR3-1:0] VAR19... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3/sky130_fd_sc_hdll__nor3.pp.blackbox.v | 1,329 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR5 ,
VAR3 ,
VAR4,
VAR7,
VAR2 ,
VAR6
);
output VAR1 ;
input VAR8 ;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR7;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_axi_basic_rx_pipeline.v | 26,681 | module MODULE1 #(
parameter VAR75 = 128, parameter VAR41 = "VAR72", parameter VAR40 = 1,
parameter VAR15 = (VAR75 == 128) ? 2 : 1, parameter VAR59 = VAR75 / 8 ) (
output reg [VAR75-1:0] VAR68, output reg VAR74, input VAR61, output [VAR59-1:0] VAR16, output VAR31, output reg [21:0] VAR7,
input [VAR75-1:0] VAR29, input V... | mit |
impedimentToProgress/ProbableCause | ddr2/cores/ddr2/ddr2_top.v | 14,055 | module MODULE1 #
(
parameter VAR95 = 2, parameter VAR40 = 1, parameter VAR35 = 1, parameter VAR74 = 10, parameter VAR88 = 1, parameter VAR8 = 0, parameter VAR116 = 1, parameter VAR111 = 1, parameter VAR44 = 9, parameter VAR15 = 72, parameter VAR41 = 7, parameter VAR80 = 8, parameter VAR50 = 9, parameter VAR65 = 4, para... | mit |
aj-michael/Digital-Systems | Lab4-Part1-40x7bit-RAM/ipcore_dir/Clock35MHz/example_design/Clock35MHz_exdes.v | 4,919 | module MODULE1
parameter VAR15 = 100
)
( input VAR7,
input VAR9,
output [1:1] VAR16,
output VAR22,
output VAR20
);
localparam VAR23 = 16;
wire VAR2 = !VAR20 || VAR9;
reg VAR4;
reg VAR3;
reg VAR17;
reg VAR8;
wire VAR11;
wire VAR10;
wire clk;
reg [VAR23-1:0] counter;
VAR14 VAR1
( .VAR7 (VAR7),
.VAR25 (VAR11),
.VAR20 (VAR... | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_refgen/sky130_fd_io__top_refgen.behavioral.pp.v | 2,849 | module MODULE1 (VAR18, VAR1, VAR10,
VAR9, VAR25, VAR21, VAR24, VAR17, VAR13, VAR2, VAR15,
VAR3, VAR30, VAR6, VAR23, VAR5, VAR4, VAR32);
wire VAR16;
output VAR18;
output VAR1;
inout VAR10;
inout VAR9;
inout VAR25;
inout VAR21;
inout VAR24;
inout VAR17;
inout VAR13;
inout VAR2;
inout VAR15;
input VAR3;
input VAR30;
input... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3b/sky130_fd_sc_ls__nand3b_4.v | 2,229 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR1 ,
VAR9 ,
VAR4,
VAR2,
VAR6 ,
VAR7
);
output VAR3 ;
input VAR5 ;
input VAR1 ;
input VAR9 ;
input VAR4;
input VAR2;
input VAR6 ;
input VAR7 ;
VAR8 VAR10 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE1 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2b/sky130_fd_sc_hdll__nand2b.pp.blackbox.v | 1,301 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR7 ,
VAR1,
VAR4,
VAR5 ,
VAR2
);
output VAR6 ;
input VAR3 ;
input VAR7 ;
input VAR1;
input VAR4;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/neek/rtl/verilog/wb_intercon.v | 21,831 | module MODULE1
(input VAR306,
input VAR25,
input [31:0] VAR15,
input [31:0] VAR69,
input [3:0] VAR158,
input VAR156,
input VAR175,
input VAR118,
input [2:0] VAR283,
input [1:0] VAR49,
output [31:0] VAR70,
output VAR110,
output VAR136,
output VAR227,
input [31:0] VAR116,
input [31:0] VAR108,
input [3:0] VAR279,
input VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufinv/sky130_fd_sc_hs__bufinv.pp.symbol.v | 1,239 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_hinterp.v | 2,617 | module MODULE1(
input VAR4,
input VAR9,
output VAR25,
input VAR3,
output VAR26,
input signed [11:0] VAR5,
input signed [11:0] VAR36,
input signed [17:0] VAR28,
input signed [17:0] VAR20,
input VAR11,
input [16:0] VAR34,
input [16:0] VAR21,
input VAR37,
input [16:0] VAR38,
input [16:0] VAR17,
input [10:0] VAR30,
output ... | lgpl-3.0 |
peteasa/oh | src/common/hdl/oh_fifo_sync.v | 2,620 | module MODULE1 #(parameter VAR20 = 104, parameter VAR18 = 32, parameter VAR2 = (VAR18/2), parameter VAR7 = VAR10(VAR18) )
(
input clk, input VAR9, input [VAR20-1:0] din, input VAR22, input VAR3, output [VAR20-1:0] dout, output VAR8, output VAR5, output VAR13, output reg [VAR7-1:0] VAR12 );
reg [VAR7-1:0] VAR23;
reg [VA... | mit |
SiLab-Bonn/monopix_daq | firmware/src/timestamp640/timestamp640.v | 2,255 | module MODULE1
parameter VAR28 = 16'h0000,
parameter VAR30 = 16'h0000,
parameter VAR8 = 16,
parameter VAR23 = 4'b0001,
parameter VAR9 = 4
)(
input wire VAR10,
input wire [VAR8-1:0] VAR3,
inout wire [7:0] VAR31,
input wire VAR25,
input wire VAR34,
input wire VAR35,
input wire VAR27,
input wire VAR6,
input wire VAR4,
inp... | gpl-2.0 |
chahuja/hilbert-fpga | ROM_Weight.v | 1,029 | module MODULE1 ( input[3:0] VAR1 ,output[31:0] VAR3,output[31:0] VAR4);
reg [31:0] VAR5[0:15];
reg [31:0] VAR2[0:15]; | gpl-2.0 |
xuefei1/ElectronicEngineControl | niosII_system/synthesis/submodules/niosII_system_sdram_0.v | 23,941 | module MODULE1 (
clk,
rd,
VAR13,
wr,
VAR63,
VAR78,
VAR82,
VAR46,
VAR34,
VAR29
)
;
output VAR78;
output VAR82;
output VAR46;
output VAR34;
output [ 42: 0] VAR29;
input clk;
input rd;
input VAR13;
input wr;
input [ 42: 0] VAR63;
wire VAR78;
wire VAR82;
wire VAR46;
reg [ 1: 0] VAR69;
reg [ 42: 0] VAR11;
reg [ 42: 0] VAR53... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_di_buffer.v | 3,934 | module MODULE1 (
VAR6,
VAR12,
VAR11,
VAR1,
VAR5,
VAR7,
VAR8);
parameter VAR10 = 32;
parameter VAR9 = 4;
parameter VAR4 = 16;
input VAR6;
input [VAR10-1:0] VAR12;
input [VAR9-1:0] VAR11;
input [VAR9-1:0] VAR1;
input VAR5;
output [VAR10-1:0] VAR7;
input VAR8;
tri1 VAR6;
tri0 VAR5;
reg [VAR10-1:0] VAR7;
reg [VAR10-1:0] VA... | gpl-3.0 |
lvd2/zxevo | fpga/baseconf/trunk/vg93/vg93.v | 6,639 | module MODULE1(
input VAR27, input VAR37,
input VAR2,
output VAR46,
output reg VAR52,
input [7:0] din, output VAR13,VAR14, input VAR15,
output reg VAR24,
output wire VAR51,
output wire VAR30,
output reg [1:0] VAR6, output reg VAR41,
output reg VAR25,
input VAR42, input VAR18,VAR11,VAR38,
input VAR3,
input VAR31,
input ... | gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_addrram_wrap.v | 6,002 | module MODULE1 #
(
parameter VAR30 = "VAR21",
parameter VAR45 = "VAR39" ,
parameter VAR35 = 32,
parameter VAR47 = 32,
parameter VAR34 = 32,
parameter VAR10 = 0
) (
input VAR50 ,
input VAR17 ,
input [15:0] VAR11 ,
input VAR27 ,
input [15:0] VAR2 ,
input VAR26 ,
input VAR28 ,
input [VAR35*9/8+1-1:0] VAR25 ,
output [31:0]... | gpl-3.0 |
cospan/prometheus_fpga | sandbox/fx3_bus_controller.v | 5,783 | module MODULE1 (
input clk,
input rst,
input VAR14,
output reg VAR13,
input VAR4,
input VAR7,
output reg VAR29,
input VAR10,
input VAR23,
input VAR26,
output reg VAR2,
input VAR17,
input VAR30,
output reg VAR25,
input VAR16,
input VAR27,
input VAR8,
input VAR15,
input VAR18,
output reg [1:0] VAR1
);
localparam VAR22 = ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufinv/sky130_fd_sc_hdll__bufinv.behavioral.pp.v | 1,800 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR2,
VAR10,
VAR3 ,
VAR5
);
output VAR7 ;
input VAR9 ;
input VAR2;
input VAR10;
input VAR3 ;
input VAR5 ;
wire VAR4 ;
wire VAR8;
not VAR11 (VAR4 , VAR9 );
VAR1 VAR6 (VAR8, VAR4, VAR2, VAR10);
buf VAR12 (VAR7 , VAR8 );
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/riffa.v | 39,407 | module MODULE1
parameter VAR146 = 12,
parameter VAR356 = 512, parameter VAR158 = 5, parameter VAR286 = "VAR242",
parameter VAR215 = "VAR346", parameter VAR149 = 0, parameter VAR348 = 10)
(input VAR170,
input VAR205,
output VAR304,
input VAR119,
input VAR223,
input [VAR308-1:0] VAR74,
input VAR282,
input [(VAR308/32)-1:... | gpl-3.0 |
alexforencich/xfcp | lib/uart/example/NexysVideo/fpga/rtl/fpga_core.v | 3,404 | module MODULE1 (
input wire clk,
input wire rst,
input wire VAR9,
input wire VAR28,
input wire VAR25,
input wire VAR2,
input wire VAR15,
input wire [7:0] VAR23,
output wire [7:0] VAR19,
input wire VAR18,
output wire VAR5
);
reg [7:0] VAR22;
reg VAR16;
wire VAR29;
wire [7:0] VAR3;
wire VAR1;
reg VAR13;
VAR30
VAR12 (
.cl... | mit |
glennchid/font5-firmware | src/verilog/synthesis/uart3_rx.v | 2,962 | module MODULE1 #(parameter real VAR1 = 357e6, parameter real VAR15 = 9600, parameter VAR10 = 8, parameter VAR17 = 0, parameter VAR5 = 1) (
input clk,
input VAR13,
output reg [VAR10-1:0] VAR20 = {VAR10{1'b0}},
input VAR7,
output reg VAR19 = 1'b0
);
localparam VAR2 = VAR6(VAR1/(16*VAR15));
localparam VAR14 = VAR6(VAR10+V... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/fifo_rx.v | 6,664 | module MODULE1
parameter integer VAR8 = 9,
parameter integer VAR21 = 6
)
(
input VAR22, reset, VAR7, VAR2,
input [VAR8-1:0] VAR15,
output reg VAR4,VAR1,
output reg VAR3,
output reg VAR6,
output [VAR8-1:0] VAR5,
output reg [VAR21-1:0] counter
);
reg [VAR21-1:0] VAR14;
reg [VAR21-1:0] VAR11;
reg [VAR21-1:0] VAR19;
reg [1... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_processing_system7_0_2/zqynq_lab_1_design_processing_system7_0_2_stub.v | 5,396 | module MODULE1(VAR44, VAR68,
VAR34, VAR24, VAR60, VAR14,
VAR25, VAR56, VAR17, VAR66,
VAR53, VAR23, VAR7, VAR8, VAR30,
VAR26, VAR10, VAR27, VAR5,
VAR41, VAR22, VAR58, VAR46, VAR1,
VAR49, VAR32, VAR61, VAR36, VAR35,
VAR21, VAR29, VAR54, VAR48, VAR19,
VAR69, VAR62, VAR9, VAR40,
VAR12, VAR67, VAR63, VAR59, VAR6,
VAR20, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkmux2/sky130_fd_sc_hdll__clkmux2.symbol.v | 1,335 | module MODULE1 (
input VAR4,
input VAR6,
output VAR8 ,
input VAR7
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
ammelto/FPGAdventure | Adventure/SCenterMaze.v | 3,190 | module MODULE1(VAR2, VAR5, VAR3, VAR4, VAR1);
input VAR2;
input [9:0]VAR5;
input [8:0]VAR3;
input [7:0]VAR1;
output [7:0]VAR4;
reg [7:0]VAR6;
always @(posedge VAR2) begin
if((VAR5 >= 0 && VAR5 <=63) && (
(VAR3 <= 39) ||
(VAR3 >= 120 && VAR3 <= 359) ||
(VAR3 >= 441) ) )
VAR6[7:0] <= VAR1;
end
else if( (VAR5 >= 64 && VAR... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_15.v | 13,296 | module MODULE4 (
clk,
reset,
VAR98,
VAR47,
VAR53,
VAR86,
VAR10
);
parameter VAR18 = 18;
parameter VAR70 = 15;
parameter VAR4 = 8;
localparam VAR8 = 20;
input clk;
input reset;
input VAR98;
input VAR47;
input [VAR18-1:0] VAR53; output VAR86;
output [VAR18-1:0] VAR10;
localparam VAR19 = 18; localparam VAR82 = 36; localpa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbp/sky130_fd_sc_ls__dlrbp.functional.pp.v | 2,072 | module MODULE1 (
VAR9 ,
VAR16 ,
VAR3,
VAR10 ,
VAR15 ,
VAR14 ,
VAR17 ,
VAR12 ,
VAR2
);
output VAR9 ;
output VAR16 ;
input VAR3;
input VAR10 ;
input VAR15 ;
input VAR14 ;
input VAR17 ;
input VAR12 ;
input VAR2 ;
wire VAR4;
wire VAR5;
not VAR11 (VAR4 , VAR3 );
VAR7 VAR13 VAR8 (VAR5 , VAR10, VAR15, VAR4, , VAR14, VAR17);
b... | apache-2.0 |
ultraembedded/riscv | top_cache_axi/src_v/icache_tag_ram.v | 2,862 | module MODULE1
(
input VAR8
,input VAR4
,input [ 7:0] VAR7
,input [ 19:0] VAR1
,input VAR3
,output [ 19:0] VAR6
);
reg [19:0] VAR5 [255:0] ;
reg [19:0] VAR2;
always @ (posedge VAR8)
begin
if (VAR3)
VAR5[VAR7] <= VAR1;
VAR2 <= VAR5[VAR7];
end
assign VAR6 = VAR2;
endmodule | bsd-3-clause |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/meiko/sc_ref.v | 9,425 | module MODULE35( VAR13 ); output VAR13;
assign VAR13 = 1'b0;
endmodule
module MODULE27( VAR13 ); output VAR13;
assign VAR13 = 1'b1;
endmodule
module MODULE9(VAR57, VAR44, VAR22, VAR46);
input VAR57;
input VAR44;
output VAR22;
output VAR46;
xor VAR32(VAR22, VAR57, VAR44);
and VAR1(VAR46, VAR57, VAR44);
endmodule
module ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1.behavioral.pp.v | 9,064 | module MODULE1( VAR58, VAR65, VAR64, VAR60, VAR23, VAR77, VAR36 );
input VAR58, VAR65, VAR60, VAR64;
inout VAR77, VAR36;
output VAR23;
reg VAR33;
VAR85 VAR63(.VAR58(VAR58),.VAR65(VAR65),.VAR64(VAR64),.VAR60(VAR60),.VAR23(VAR23),.VAR77(VAR77),.VAR36(VAR36),.VAR33(VAR33));
VAR85 VAR6(.VAR58(VAR58),.VAR65(VAR65),.VAR64(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/maj3/sky130_fd_sc_ls__maj3.symbol.v | 1,284 | module MODULE1 (
input VAR7,
input VAR2,
input VAR8,
output VAR6
);
supply1 VAR1;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
praveendath92/securePUF | source/puf_files/pdl_block.v | 1,393 | module MODULE1(VAR9,VAR6,VAR11);
input VAR9;
input VAR11;
output VAR6;
wire VAR15;
wire VAR11;
VAR2 #(
.VAR3(64'h5655555555555555) ) VAR7 (
.VAR13(VAR15), .VAR1(VAR9), .VAR10(VAR11), .VAR8(VAR11), .VAR5(VAR11), .VAR14(VAR11), .VAR12(VAR11) );
VAR2 #(
.VAR3(64'h5655555555555555) ) VAR4 (
.VAR13(VAR6), .VAR1(VAR15), .VAR... | gpl-2.0 |
olgirard/openmsp430 | fpga/OBSOLETE/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v | 38,726 | module MODULE1 (
VAR42, VAR33, VAR78, VAR118, VAR106, VAR163, VAR154, VAR121, VAR56, VAR139, VAR27, VAR147, VAR12, VAR18, VAR120, VAR29, VAR71, VAR107, VAR53, VAR90, VAR92, VAR138, VAR21, VAR112, VAR159, VAR97, VAR184,
VAR86, VAR169, VAR38, VAR151, VAR117, VAR39, VAR162, VAR49, irq, VAR157, VAR45, VAR173, VAR91, VAR175... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2/sky130_fd_sc_hs__and2.pp.blackbox.v | 1,207 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR3 ,
VAR2,
VAR4
);
output VAR1 ;
input VAR5 ;
input VAR3 ;
input VAR2;
input VAR4;
endmodule | apache-2.0 |
thotypous/rtai-irq-latency | PCIe_HW/altgx_reconfig_bb.v | 4,244 | module MODULE1 (
VAR2,
VAR5,
VAR3,
VAR4,
VAR1);
input VAR2;
input [16:0] VAR5;
output VAR3;
output VAR4;
output [3:0] VAR1;
endmodule | mit |
jimurai/okWishboneMaster | verilog/ok_wbm.v | 4,196 | module MODULE1 (
input wire [7:0] VAR22,
output wire [1:0] VAR19,
inout wire [15:0] VAR102,
inout wire VAR65,
output wire VAR67,
input wire VAR32,
output wire [7:0] VAR18,
output wire [15:0] VAR63,
input wire [3:0] VAR96
);
wire VAR106;
wire [30:0] VAR28;
wire [16:0] VAR38;
wire [15:0] VAR14;
wire [15:0] VAR2;
wire [15... | mit |
kylemsguy/FPGA-Litecoin-Miner | experimental/LX150-SIXTYFOUR-A/salsaengine.v | 19,651 | module MODULE1 (VAR90, reset, din, dout, VAR67, VAR78, VAR19, VAR3 );
input VAR90;
input reset; input VAR67;
input VAR78; output VAR19;
output reg VAR3 = 1'b0;
parameter VAR34 = 8; input [VAR34-1:0] din;
output [VAR34-1:0] dout;
parameter VAR45 = 12;
parameter VAR107 = 64;
function integer VAR28; input integer VAR103;
... | gpl-3.0 |
takeshineshiro/fpga_linear_128 | Receive.v | 8,653 | module MODULE1(
input VAR33,
input [11:0] VAR75,VAR20,VAR10,VAR82,VAR84,VAR19,VAR59,VAR79,
input [7:0] VAR13, input [1:0] VAR26, input VAR80, input VAR44, input VAR8,
input VAR68,
output reg VAR1, output reg [14:0] VAR57,
output [7:0] VAR3
);
reg [15:0] VAR22;
reg [15:0] VAR39;
reg VAR58;
parameter
VAR9 = 16'd400;
alwa... | mit |
alankarkotwal/lca-processor | reg-file/register.v | 1,749 | module MODULE2(clk, out, in, write, reset);
output reg [15:0] out;
input [15:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 16'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module MODULE5(clk, out, in, write, reset);
output reg [3:0] out;
input [3:0] in;
input clk... | gpl-2.0 |
ptracton/pmodacl2 | behavioral/adxl362/adxl362_system_controller.v | 2,851 | module MODULE1 (
clk, VAR3, reset, VAR6, rst,
VAR1, VAR4
) ;
output reg clk;
output reg VAR3;
output wire reset;
input wire VAR1;
output wire VAR6;
input wire [2:0] VAR4;
output wire rst;
reg [5:0] VAR5 = 0;
reg VAR2 = 1;
assign rst = |VAR5;
always @(posedge VAR3)
if (VAR2 || VAR1) begin
VAR5 <= 1;
VAR2 <= 0;
end else ... | mit |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_ic_tag.v | 5,660 | module MODULE1(
clk, rst,
VAR15, VAR2, VAR7,
addr, en, VAR14, VAR18, VAR11, VAR13
);
parameter VAR20 = VAR3;
parameter VAR4 = VAR12;
input clk;
input rst;
input VAR15;
input [VAR9 - 1:0] VAR7;
output VAR2;
input [VAR4-1:0] addr;
input en;
input VAR14;
input [VAR20-1:0] VAR18;
output VAR11;
output [VAR20-2:0] VAR13;
ass... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_4.functional.pp.v | 1,404 | module MODULE1( VAR1, VAR13, VAR7, VAR10, VAR3, VAR12, VAR11 );
input VAR3, VAR10, VAR1, VAR7;
inout VAR12, VAR11;
output VAR13;
wire VAR15;
not VAR5( VAR15, VAR3 );
wire VAR9;
not VAR14( VAR9, VAR10 );
wire VAR16;
not VAR2( VAR16, VAR1 );
wire VAR8;
not VAR6( VAR8, VAR7 );
and VAR4( VAR13, VAR15, VAR9, VAR16, VAR8 );
... | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | counter.v | 1,634 | module MODULE1 (VAR4, VAR6, VAR2, VAR1, VAR8);
parameter VAR7=4, VAR3=0, final=8, VAR5=1;
input VAR4;
input VAR6;
input VAR2;
output VAR1;
output [VAR7-1:0] VAR8;
reg [VAR7-1:0] VAR8;
always @ (posedge VAR4 or posedge VAR2)
begin
if (VAR2)
VAR8 = VAR3;
end
else if (VAR6)
VAR8 = VAR8 + VAR5;
end
assign VAR1 = (VAR8 == f... | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/float_mega/float_mult/float_mult_bb.v | 3,752 | module MODULE1 (
VAR1,
VAR2,
VAR3,
VAR5,
VAR4);
input VAR1;
input [31:0] VAR2;
input [31:0] VAR3;
output VAR5;
output [31:0] VAR4;
endmodule | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/sort_module.v | 3,270 | module MODULE1 #(
parameter VAR20 = 128,
parameter VAR8=32,
parameter VAR18 = 0,
parameter VAR19 = 32
)(
input clk,
input reset,
input VAR6,
input VAR17,
input VAR4,
input VAR1,
input [VAR8-1:0] VAR3, output [VAR8-1:0] VAR11,
input [31:0] VAR10,
input VAR13,
output [31:0] VAR2
);
wire [VAR8-1:0] VAR23[VAR20-1:0];
wire ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0n/sky130_fd_sc_lp__iso0n.behavioral.pp.v | 1,907 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR1,
VAR2 ,
VAR13 ,
VAR4 ,
VAR11
);
output VAR6 ;
input VAR3 ;
input VAR1;
input VAR2 ;
input VAR13 ;
input VAR4 ;
input VAR11 ;
wire VAR12 ;
wire VAR7;
VAR10 VAR5 (VAR12 , VAR3, VAR2, VAR13 );
VAR10 VAR8 (VAR7, VAR1, VAR2, VAR13 );
and VAR9 (VAR6 , VAR12, VAR7);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4bb/sky130_fd_sc_hd__and4bb.blackbox.v | 1,330 | module MODULE1 (
VAR6 ,
VAR1,
VAR5,
VAR4 ,
VAR3
);
output VAR6 ;
input VAR1;
input VAR5;
input VAR4 ;
input VAR3 ;
supply1 VAR7;
supply0 VAR8;
supply1 VAR9 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
kielfriedt/ece472 | lab5/rom32.v | 1,797 | module MODULE1(address, VAR2);
input [31:0] address;
output [31:0] VAR2;
reg [31:0] VAR2;
parameter VAR4 = 25'd0;
wire [5:0] VAR3;
wire VAR5;
assign VAR3 = address[7:2];
assign VAR5 = (address[31:8] == VAR4);
always @(VAR5 or VAR3)
begin
if ((address % 4) != 0)
if (VAR5 == 1)
begin
case (VAR3)
5'd0 : VAR2 = { 6'd35, 5'... | gpl-3.0 |
sam-falvo/kestrel | cores/KCP53K/processor/bench/verilog/xrs.v | 1,552 | module MODULE1();
reg VAR9;
reg [15:0] VAR13;
wire [63:0] VAR12;
reg [63:0] VAR15;
reg [4:0] VAR7;
reg [3:0] VAR3;
VAR8 VAR4(
.VAR11(VAR9),
.VAR1(VAR7),
.VAR12(VAR15),
.VAR15(VAR12),
.VAR10(VAR3)
);
always begin
VAR9 <= ~VAR9;
end
task VAR14;
input [15:0] VAR6;
begin
VAR13 <= VAR6;
@(posedge VAR9);
@(negedge VAR9);
end... | mpl-2.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_tpram_32x32.v | 9,758 | module MODULE1(
VAR38, VAR124, VAR78, VAR21, VAR70, VAR96, VAR42, VAR65,
VAR110, VAR72, VAR14, VAR66, VAR8, VAR92, VAR25, VAR119
);
parameter VAR104 = 5;
parameter VAR74 = 32;
input VAR38; input VAR124; input VAR78; input VAR21; input VAR70; input [VAR104-1:0] VAR96; input [VAR74-1:0] VAR42; output [VAR74-1:0] VAR65; i... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr.symbol.v | 1,410 | module MODULE1 (
input VAR3,
output VAR2
);
supply1 VAR5 ;
supply0 VAR6 ;
supply1 VAR7;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/soc_system_hps_0.v | 26,999 | module MODULE1 #(
parameter VAR112 = 3,
parameter VAR37 = 2
) (
output wire VAR138, input wire VAR122, input wire [7:0] VAR149, input wire [31:0] VAR63, input wire [3:0] VAR31, input wire [2:0] VAR20, input wire [1:0] VAR120, input wire [1:0] VAR19, input wire [3:0] VAR57, input wire [2:0] VAR13, input wire VAR93, outp... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_4.behavioral.pp.v | 7,224 | module MODULE1( VAR1, VAR12, VAR3, VAR6, VAR2, VAR7, VAR11, VAR8, VAR4 );
input VAR7, VAR11, VAR6, VAR2, VAR1, VAR3;
inout VAR8, VAR4;
output VAR12;
VAR5 VAR10(.VAR1(VAR1),.VAR12(VAR12),.VAR3(VAR3),.VAR6(VAR6),.VAR2(VAR2),.VAR7(VAR7),.VAR11(VAR11),.VAR8(VAR8),.VAR4(VAR4));
VAR5 VAR9(.VAR1(VAR1),.VAR12(VAR12),.VAR3(VAR3... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_immu_top.v | 12,369 | module MODULE1(
clk, rst,
VAR11, VAR47, VAR16, VAR42, VAR12,
VAR26, VAR27, VAR8, VAR41,
VAR18, VAR15, VAR14, VAR19, VAR54,
VAR40, VAR55, VAR5,
VAR39, VAR43, VAR37, VAR33, VAR20, VAR45
);
parameter VAR13 = VAR21;
parameter VAR34 = VAR21;
input clk;
input rst;
input VAR11;
input VAR47;
input VAR16;
input [VAR34-1:0] VAR4... | apache-2.0 |
pwwu/FPGA | VGAbased/final/lcd_display.v | 2,322 | module MODULE1
(input clk,
input rst,
output VAR12,
output VAR3,
output VAR2,
output [3:0] VAR21,
input [7:0] VAR8,
input VAR5,
input [31:0] VAR18,
input VAR7,
output VAR19,
input VAR10);
reg [2:0] state;
reg VAR11;
reg [3:0] VAR16;
reg [31:0] VAR15;
reg ready;
reg VAR17;
parameter VAR14 = 3'b000,
VAR4 = 3'b001,
VAR1 =... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211a/sky130_fd_sc_lp__o211a.symbol.v | 1,367 | module MODULE1 (
input VAR1,
input VAR6,
input VAR7,
input VAR8,
output VAR5
);
supply1 VAR9;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_4.functional.pp.v | 1,864 | module MODULE1( VAR8, VAR26, VAR15, VAR24, VAR21, VAR14, VAR25, VAR22, VAR7 );
input VAR21, VAR14, VAR25, VAR15, VAR8, VAR26;
inout VAR22, VAR7;
output VAR24;
wire VAR12;
not VAR23( VAR12, VAR21 );
wire VAR19;
not VAR4( VAR19, VAR14 );
wire VAR2;
not VAR3( VAR2, VAR25 );
wire VAR16;
and VAR18( VAR16, VAR12, VAR19, VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.v | 2,325 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR2 ,
VAR8 ,
VAR10 ,
VAR7,
VAR6,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR4 ;
input VAR2 ;
input VAR8 ;
input VAR10 ;
input VAR7;
input VAR6;
input VAR1 ;
input VAR3 ;
VAR9 VAR11 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR... | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/dpRAM/core_peripheric.v | 3,193 | module MODULE1(clk, addr, din, dout, wr, rd);
input clk;
input [15:0]din;
output reg [15:0]dout;
output reg [7:0]addr;
output reg rd;
output reg wr;
reg [15:0] VAR6, VAR3, VAR7, VAR1, VAR4, VAR2; reg [3:0] VAR5; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a.pp.symbol.v | 1,372 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR4 ,
input VAR7 ,
output VAR2 ,
input VAR8 ,
input VAR9,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbp/sky130_fd_sc_hs__dlrbp.behavioral.pp.v | 2,392 | module MODULE1 (
VAR15 ,
VAR18 ,
VAR7 ,
VAR8 ,
VAR1,
VAR20 ,
VAR6
);
input VAR15 ;
input VAR18 ;
output VAR7 ;
output VAR8 ;
input VAR1;
input VAR20 ;
input VAR6 ;
wire VAR22 ;
reg VAR21 ;
wire VAR2 ;
wire VAR4 ;
wire VAR11 ;
wire VAR17;
wire VAR3 ;
wire VAR5 ;
wire VAR12 ;
wire VAR13 ;
not VAR16 (VAR22 , VAR17 );
VAR1... | apache-2.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system_backup/clocks.v | 10,576 | module MODULE1 (
VAR71,
reset,
address,
VAR12,
VAR66,
VAR32
);
parameter VAR97 = 1;
parameter VAR48 = 1;
input VAR71;
input reset;
input address;
output VAR12;
output VAR66;
output reg [ 7: 0] VAR32;
wire VAR104;
wire VAR24;
wire VAR40;
wire VAR69;
always @(posedge VAR71)
begin
if (reset)
VAR32 <= 8'h00;
end
else if (a... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_12.behavioral.pp.v | 1,179 | module MODULE1( VAR5, VAR6, VAR3, VAR4 );
input VAR5;
inout VAR3, VAR4;
output VAR6;
VAR2 VAR1(.VAR5(VAR5),.VAR6(VAR6),.VAR3(VAR3),.VAR4(VAR4));
VAR2 VAR7(.VAR5(VAR5),.VAR6(VAR6),.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
manu3193/GatoTDD | figuras_Gato.v | 32,496 | module MODULE1(
input wire VAR30,
input wire [3:0] VAR41,
input wire [1:0] VAR36, VAR19, VAR27,
input wire [2:0] VAR75,VAR38,VAR81,VAR59,VAR4,VAR9,VAR69,VAR7,VAR89,
input wire [9:0] VAR45, VAR35,
output reg [2:0] VAR20
);
localparam VAR76 = 4'd1;
localparam VAR50 = 4'd2;
localparam VAR2 = 4'd3;
localparam VAR58 = 4'd4;... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_008bits.v | 1,917 | module MODULE1 (
clk,
VAR27, VAR34, VAR29, VAR14, VAR6, VAR20, VAR32, VAR8,
sum,
);
input clk;
input [VAR2+0-1:0] VAR27, VAR34, VAR29, VAR14, VAR6, VAR20, VAR32, VAR8;
output [VAR2 :0] sum;
reg [VAR2 :0] sum;
wire [VAR2+3-1:0] VAR25;
wire [VAR2+2-1:0] VAR7, VAR26;
wire [VAR2+1-1:0] VAR10, VAR3, VAR5, VAR11;
reg [VAR2+0... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x8_125/example_design/PIO_64_RX_ENGINE.v | 20,890 | module MODULE1 (
clk,
VAR31,
VAR55,
VAR56,
VAR44,
VAR28,
VAR23,
VAR19,
VAR60,
VAR16,
VAR58,
VAR45, VAR32,
VAR36, VAR20, VAR10, VAR41, VAR3, VAR46, VAR29, VAR24, VAR18,
VAR9, VAR40, VAR39, VAR8, VAR6
);
input clk;
input VAR31;
input [63:0] VAR55;
input [7:0] VAR56;
input VAR44;
input VAR28;
input VAR23;
input VAR19;
inp... | lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_axi_basic_top.v | 10,988 | module MODULE1 #(
parameter VAR21 = 128, parameter VAR14 = "VAR34", parameter VAR50 = "VAR47", parameter VAR25 = "VAR47", parameter VAR48 = 1,
parameter VAR59 = (VAR21 == 128) ? 2 : 1, parameter VAR10 = VAR21 / 8 ) (
input [VAR21-1:0] VAR44, input VAR3, output VAR1, input [VAR10-1:0] VAR53, input VAR46, input [3:0] VAR... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_4.behavioral.pp.v | 1,239 | module MODULE1( VAR3, VAR7, VAR8, VAR2, VAR4 );
input VAR7, VAR3;
inout VAR2, VAR4;
output VAR8;
VAR5 VAR6(.VAR3(VAR3),.VAR7(VAR7),.VAR8(VAR8),.VAR2(VAR2),.VAR4(VAR4));
VAR5 VAR1(.VAR3(VAR3),.VAR7(VAR7),.VAR8(VAR8),.VAR2(VAR2),.VAR4(VAR4)); | apache-2.0 |
olajep/oh | src/adi/hdl/library/xilinx/common/ad_serdes_out.v | 4,306 | module MODULE1 #(
parameter VAR30 = 0,
parameter VAR28 = 1,
parameter VAR44 = 8,
parameter VAR45 = 16) (
input rst,
input clk,
input VAR22,
input VAR6,
input [(VAR45-1):0] VAR57,
input [(VAR45-1):0] VAR47,
input [(VAR45-1):0] VAR26,
input [(VAR45-1):0] VAR62,
input [(VAR45-1):0] VAR19,
input [(VAR45-1):0] VAR17,
input ... | mit |
twlostow/dsi-shield | hdl/rtl/hpdmc/spartan6/hpdmc_oddr32.v | 6,611 | module MODULE1 #(
parameter VAR11 = "VAR19",
parameter VAR30 = 1'b0,
parameter VAR27 = "VAR26"
) (
output [31:0] VAR43,
input VAR19,
input VAR13,
input VAR28,
input [31:0] VAR33,
input [31:0] VAR44,
input VAR23,
input VAR17
);
VAR7 #(
.VAR11(VAR11),
.VAR30(VAR30),
.VAR27(VAR27)
) VAR15 (
.VAR43(VAR43[0]),
.VAR19(VAR19)... | lgpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9250/axi_ad9250_if.v | 4,248 | module MODULE1 (
VAR5,
VAR3,
VAR7,
VAR8,
VAR1,
VAR12,
VAR11,
VAR10,
VAR13);
input VAR5;
input [63:0] VAR3;
output VAR7;
input VAR8;
output [27:0] VAR1;
output [27:0] VAR12;
output VAR11;
output VAR10;
output VAR13;
reg VAR13 = 'd0;
wire [15:0] VAR4;
wire [15:0] VAR6;
wire [15:0] VAR9;
wire [15:0] VAR2;
assign VAR7 = VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfstp/sky130_fd_sc_ms__sdfstp.behavioral.pp.v | 2,802 | module MODULE1 (
VAR11 ,
VAR30 ,
VAR22 ,
VAR2 ,
VAR14 ,
VAR26,
VAR24 ,
VAR10 ,
VAR25 ,
VAR8
);
output VAR11 ;
input VAR30 ;
input VAR22 ;
input VAR2 ;
input VAR14 ;
input VAR26;
input VAR24 ;
input VAR10 ;
input VAR25 ;
input VAR8 ;
wire VAR27 ;
wire VAR7 ;
wire VAR18 ;
reg VAR12 ;
wire VAR3 ;
wire VAR21 ;
wire VAR4 ;
... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_sequencer_ram.v | 4,385 | module MODULE1 (
address,
VAR3,
VAR14,
clk,
VAR33,
reset,
write,
VAR18,
VAR2
)
;
parameter VAR8 = "../MODULE1.VAR31";
output [ 31: 0] VAR2;
input [ 8: 0] address;
input [ 3: 0] VAR3;
input VAR14;
input clk;
input VAR33;
input reset;
input write;
input [ 31: 0] VAR18;
wire [ 31: 0] VAR2;
wire VAR13;
assign VAR13 = VAR14... | lgpl-3.0 |
queq/just-stuff | pov/TopFixed/ScanCodeControl.v | 1,147 | module MODULE1(VAR6,VAR3, VAR1 , VAR8, VAR9, VAR5, VAR7 , VAR12);
input VAR6, VAR9, VAR5, VAR7, VAR12;
output reg VAR3, VAR1 , VAR8;
reg [1:0]state;
parameter VAR2 = 3'h0;
parameter VAR4 = 3'h1;
parameter VAR10 = 3'h3;
parameter VAR11 = 3'h2;
always @(negedge VAR7) begin
if (VAR12)
state = VAR2;
end
else begin
case(sta... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211oi/sky130_fd_sc_lp__a211oi.functional.pp.v | 2,044 | module MODULE1 (
VAR10 ,
VAR11 ,
VAR12 ,
VAR2 ,
VAR17 ,
VAR5,
VAR15,
VAR3 ,
VAR16
);
output VAR10 ;
input VAR11 ;
input VAR12 ;
input VAR2 ;
input VAR17 ;
input VAR5;
input VAR15;
input VAR3 ;
input VAR16 ;
wire VAR1 ;
wire VAR14 ;
wire VAR9;
and VAR7 (VAR1 , VAR11, VAR12 );
nor VAR4 (VAR14 , VAR1, VAR2, VAR17 );
VAR13... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31o/sky130_fd_sc_lp__a31o.functional.pp.v | 2,026 | module MODULE1 (
VAR9 ,
VAR12 ,
VAR7 ,
VAR13 ,
VAR2 ,
VAR1,
VAR11,
VAR15 ,
VAR6
);
output VAR9 ;
input VAR12 ;
input VAR7 ;
input VAR13 ;
input VAR2 ;
input VAR1;
input VAR11;
input VAR15 ;
input VAR6 ;
wire VAR17 ;
wire VAR3 ;
wire VAR10;
and VAR4 (VAR17 , VAR13, VAR12, VAR7 );
or VAR16 (VAR3 , VAR17, VAR2 );
VAR5 VAR... | apache-2.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/nios_system_sdram.v | 24,497 | module MODULE1 (
clk,
rd,
VAR14,
wr,
VAR28,
VAR56,
VAR84,
VAR81,
VAR54,
VAR36
)
;
output VAR56;
output VAR84;
output VAR81;
output VAR54;
output [ 40: 0] VAR36;
input clk;
input rd;
input VAR14;
input wr;
input [ 40: 0] VAR28;
wire VAR56;
wire VAR84;
wire VAR81;
reg [ 1: 0] VAR26;
reg [ 40: 0] VAR48;
reg [ 40: 0] VAR83... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_top.v | 17,573 | module MODULE1(
clk ,
VAR135 ,
VAR55 ,
VAR100 ,
VAR111 ,
VAR30 ,
VAR148 ,
VAR102 ,
VAR26 ,
VAR129 ,
VAR39 ,
VAR93 ,
VAR38 ,
VAR86 ,
VAR116 ,
VAR122 ,
VAR73 ,
VAR69 ,
VAR51 ,
VAR159 ,
VAR146 ,
VAR20 ,
VAR94 ,
VAR88 ,
VAR125 ,
VAR85 ,
VAR127 ,
VAR50 ,
VAR1 ,
VAR154 ,
VAR96 ,
VAR36 ,
VAR27 ,
VAR153 ,
VAR2 ,
VAR87 ,
VAR103... | gpl-3.0 |
dengjeffrey/BirthdayClockVerilog | keyboard.v | 1,796 | module MODULE1(VAR6, VAR1, VAR12, reset, read, VAR9, VAR4);
input VAR6;
input VAR1;
input VAR12; input reset;
input read;
output VAR9;
output [7:0] VAR4;
reg VAR2;
reg [7:0] VAR4;
reg VAR9;
reg VAR5;
reg VAR3;
reg [3:0] VAR10;
reg [8:0] VAR7;
reg [7:0] VAR8;
reg VAR11;
always @ (posedge VAR2 or posedge read)
if (read =... | mit |
545/Atari7800 | lab3sound/lab3sound.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.v | 1,493 | module MODULE1(VAR7, VAR3, VAR2, VAR5, VAR6, VAR8, VAR9, VAR1, VAR4)
;
input VAR7;
input VAR3;
input [0:0]VAR2;
input [16:0]VAR5;
input [15:0]VAR6;
input VAR8;
input VAR9;
input [16:0]VAR1;
output [15:0]VAR4;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2/sky130_fd_sc_lp__nor2.behavioral.pp.v | 1,783 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR7 ,
VAR4,
VAR3,
VAR11 ,
VAR13
);
output VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR4;
input VAR3;
input VAR11 ;
input VAR13 ;
wire VAR9 ;
wire VAR10;
nor VAR2 (VAR9 , VAR5, VAR7 );
VAR6 VAR12 (VAR10, VAR9, VAR4, VAR3);
buf VAR1 (VAR8 , VAR10 );
endmodule | apache-2.0 |
fisherdj/avgai | src/avgai.v | 1,935 | module MODULE1(input clk, reset, input [9:0] VAR1,
output reg [9:0] VAR27,
output [3:0] VAR8, VAR19, VAR12, output VAR13, VAR26,
inout [31:0] VAR11);
wire [5:0] VAR3 = {VAR11[13],VAR11[11],VAR11[9],VAR11[7],VAR11[5],VAR11[3]};
wire VAR7 = VAR11[1];
wire ready;
wire VAR14;
assign VAR11[0] = ready;
wire [15:0] VAR17;
wir... | gpl-3.0 |
google/bbcpu | fadder.v | 1,331 | module MODULE1(
input [VAR8-1 : 0] VAR2,
input [VAR8 - 1 : 0] VAR7,
input VAR9,
input VAR6,
output [VAR8 - 1 : 0] VAR1,
output VAR4);
parameter VAR8 = 8;
wire [VAR8 - 1 : 0] VAR10;
wire [VAR8 - 1 : 0] VAR5;
assign VAR4 = VAR10[VAR8-1];
assign VAR5 = VAR9 ? ~(VAR7) : VAR7;
genvar VAR3;
generate
for (VAR3 = 0; VAR3 < VAR... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/4-way/src/ip_pcie/PCIeGen2x8If128_stub.v | 7,229 | module MODULE1(VAR31, VAR37, VAR85, VAR5, VAR45, VAR59, VAR83, VAR39, VAR63, VAR41, VAR54, VAR49, VAR53, VAR13, VAR72, VAR36, VAR60, VAR56, VAR71, VAR10, VAR79, VAR43, VAR24, VAR9, VAR20, VAR17, VAR22, VAR55, VAR65, VAR66, VAR82, VAR16, VAR86, VAR4, VAR35, VAR42, VAR84, VAR21, VAR70, VAR57, VAR78, VAR44, VAR14, VAR77, ... | mit |
OrganicMonkeyMotion/fpga_experiments | bmax10/j1/RAMB16_S2_S2.v | 20,017 | module MODULE1 (VAR76, VAR53, VAR150, VAR114, VAR22, VAR138, VAR103, VAR26, VAR77, VAR99, VAR143, VAR85, VAR147, VAR20);
parameter VAR154 = "VAR57";
parameter VAR159 = 2'h0;
parameter VAR149 = 2'h0;
parameter VAR7 = 2'h0;
parameter VAR160 = 2'h0;
parameter VAR75 = "VAR13";
parameter VAR23 = "VAR13";
parameter VAR119 = ... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4b/sky130_fd_sc_lp__nor4b.behavioral.pp.v | 1,988 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR14 ,
VAR9 ,
VAR13 ,
VAR3,
VAR5,
VAR15 ,
VAR6
);
output VAR8 ;
input VAR10 ;
input VAR14 ;
input VAR9 ;
input VAR13 ;
input VAR3;
input VAR5;
input VAR15 ;
input VAR6 ;
wire VAR1 ;
wire VAR12 ;
wire VAR2;
not VAR16 (VAR1 , VAR13 );
nor VAR4 (VAR12 , VAR10, VAR14, VAR9, VAR1 );
VAR11 VA... | apache-2.0 |
TonyBrewer/OpenHT | ht_lib/platform/convey/verilog/HtResetFlop1x2x.v | 1,434 | module MODULE1 (
input VAR8,
input VAR3,
input VAR7,
input VAR4,
output VAR1,
output VAR6
);
reg VAR10;
always @(posedge VAR8) begin
if (VAR4)
VAR10 <= 1'b1;
end
else
VAR10 <= 1'b0;
end
VAR15 rst (.VAR9(VAR8), .VAR5(VAR4), .VAR11(VAR10), .VAR12(!VAR10), .VAR13(VAR10));
reg VAR14;
always @(posedge VAR3) begin
VAR14 <= V... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.functional.pp.v | 1,184 | module MODULE1( VAR7, VAR11, VAR6, VAR10, VAR3 );
input VAR11, VAR7;
inout VAR10, VAR3;
output VAR6;
wire VAR9;
and VAR13( VAR9, VAR11, VAR7 );
wire VAR12;
not VAR2( VAR12, VAR11 );
wire VAR8;
not VAR4( VAR8, VAR7 );
wire VAR14;
and VAR1( VAR14, VAR12, VAR8 );
or VAR5( VAR6, VAR9, VAR14 );
endmodule | apache-2.0 |
kielfriedt/ece472 | lab2/ripple_adder.v | 1,316 | module MODULE1(VAR6,VAR2,VAR9, sum, VAR10);
input [7:0] VAR6,VAR2;
input VAR9;
output [7:0] sum;
output VAR10;
wire [7:0] VAR14;
VAR1 VAR4(VAR6[0], VAR2[0], VAR9, sum[0], VAR14[1]);
VAR1 VAR7(VAR6[1], VAR2[1], VAR14[1], sum[1], VAR14[2]);
VAR1 VAR11(VAR6[2], VAR2[2], VAR14[2], sum[2], VAR14[3]);
VAR1 VAR3(VAR6[3], VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtn/sky130_fd_sc_ms__dlxtn.behavioral.pp.v | 1,981 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR3,
VAR12 ,
VAR13 ,
VAR1 ,
VAR14
);
output VAR4 ;
input VAR8 ;
input VAR3;
input VAR12 ;
input VAR13 ;
input VAR1 ;
input VAR14 ;
wire VAR6 ;
wire VAR11 ;
wire VAR5;
wire VAR16 ;
reg VAR17 ;
wire VAR7 ;
not VAR10 (VAR6 , VAR5 );
VAR2 VAR15 (VAR11 , VAR16, VAR6, VAR17, VAR12, VAR13);
buf... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.v | 2,345 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR9 ,
VAR11 ,
VAR10 ,
VAR6,
VAR4,
VAR5 ,
VAR2
);
output VAR8 ;
input VAR1 ;
input VAR9 ;
input VAR11 ;
input VAR10 ;
input VAR6;
input VAR4;
input VAR5 ;
input VAR2 ;
VAR3 VAR7 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.... | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/tart_clk_generator.v | 4,637 | module MODULE1(
input wire VAR52, output wire VAR25, output wire VAR41, output VAR31
);
wire VAR26; assign VAR26 = 0;
wire VAR16;
VAR7 #(
.VAR18("VAR49")
) VAR48 (
.VAR35(VAR45), .VAR47(VAR52) );
VAR8 #(
.VAR40(1), .VAR27("VAR9"), .VAR17("VAR28"), .VAR32("VAR28") )
VAR15 (
.VAR2(VAR2), .VAR47(VAR45) );
VAR20 #(
.VAR39(... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcon/sky130_fd_sc_ls__fahcon.functional.v | 1,733 | module MODULE1 (
VAR4,
VAR14 ,
VAR6 ,
VAR11 ,
VAR13
);
output VAR4;
output VAR14 ;
input VAR6 ;
input VAR11 ;
input VAR13 ;
wire VAR1 ;
wire VAR9 ;
wire VAR16 ;
wire VAR8 ;
wire VAR10;
xor VAR3 (VAR1 , VAR6, VAR11, VAR13 );
buf VAR15 (VAR14 , VAR1 );
nor VAR12 (VAR9 , VAR6, VAR11 );
nor VAR17 (VAR16 , VAR6, VAR13 );
no... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311a/sky130_fd_sc_lp__o311a_1.v | 2,422 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR2 ,
VAR12 ,
VAR4 ,
VAR5 ,
VAR10,
VAR3,
VAR6 ,
VAR1
);
output VAR8 ;
input VAR11 ;
input VAR2 ;
input VAR12 ;
input VAR4 ;
input VAR5 ;
input VAR10;
input VAR3;
input VAR6 ;
input VAR1 ;
VAR9 VAR7 (
.VAR8(VAR8),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1... | apache-2.0 |
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