repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/SyncWire.v | 1,404 | module MODULE1( VAR1, VAR2 );
parameter VAR3 = 1;
input [VAR3 - 1 : 0] VAR1;
output [VAR3 - 1 : 0] VAR2;
assign VAR2 = VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2b/sky130_fd_sc_hdll__and2b.functional.pp.v | 1,954 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR5 ,
VAR15,
VAR6,
VAR11 ,
VAR8
);
output VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR15;
input VAR6;
input VAR11 ;
input VAR8 ;
wire VAR13 ;
wire VAR10 ;
wire VAR7;
not VAR4 (VAR13 , VAR1 );
and VAR9 (VAR10 , VAR13, VAR5 );
VAR2 VAR12 (VAR7, VAR10, VAR15, VAR6);
buf VAR14 (VAR3 , VAR7 );
... | apache-2.0 |
LSaldyt/qnp | output/vs/opt_var11_multi.v | 12,081 | module MODULE1(VAR11, VAR4, VAR2, VAR5, VAR9, VAR8, VAR1, VAR6, VAR3, VAR10, VAR12, valid);
wire 000;
wire 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
wire 020;
wire 021;
wire 022... | mit |
secworks/blake2 | src/rtl/blake2_m_select.v | 11,943 | module MODULE1(
input wire clk,
input wire VAR12,
input wire VAR41,
input wire [1023 : 0] VAR34,
input wire [3 : 0] VAR18,
input wire state,
output wire [63 : 0] VAR3,
output wire [63 : 0] VAR31,
output wire [63 : 0] VAR25,
output wire [63 : 0] VAR26,
output wire [63 : 0] VAR46,
output wire [63 : 0] VAR44,
output wire ... | bsd-2-clause |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/top/cur_mb.v | 17,900 | module MODULE1 (
clk ,
VAR62 ,
VAR37 ,
VAR70 ,
VAR59 ,
VAR3 ,
VAR51 ,
VAR25 ,
VAR16 ,
VAR10 ,
VAR43 ,
VAR30 ,
VAR53 ,
VAR4 ,
VAR63 ,
VAR50 ,
VAR31 ,
VAR1 ,
VAR48 ,
VAR64 ,
VAR60 ,
VAR35 ,
VAR20 ,
VAR27 ,
VAR58 ,
VAR41 ,
VAR2
);
input clk ; input VAR62 ; input [VAR38-1 : 0] VAR37 ; input [VAR18-1 : 0] VAR70 ; input VAR5... | gpl-3.0 |
jcrono/sd-host | src/register_set/remap.v | 4,761 | module MODULE1(
input logic [2047:0] VAR41,
output logic [15:0] VAR5,
output logic [15:0] VAR37,
output logic [15:0] VAR14,
output logic [15:0] VAR4,
output logic [15:0] VAR38,
output logic [15:0] VAR30,
output logic [15:0] VAR28,
output logic [15:0] VAR29,
output logic [15:0] VAR8,
output logic [15:0] VAR10,
output lo... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_4.functional.v | 1,378 | module MODULE1( VAR7, VAR12, VAR14, VAR2, VAR1 );
input VAR1, VAR2, VAR7, VAR14;
output VAR12;
wire VAR10;
not VAR4( VAR10, VAR1 );
wire VAR3;
not VAR8( VAR3, VAR2 );
wire VAR6;
not VAR11( VAR6, VAR7 );
wire VAR9;
not VAR5( VAR9, VAR14 );
and VAR13( VAR12, VAR10, VAR3, VAR6, VAR9 );
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_45.v | 29,457 | module MODULE5 (
clk,
reset,
VAR86,
VAR44,
VAR7,
VAR238,
VAR237
);
parameter VAR236 = 18;
parameter VAR205 = 45;
parameter VAR163 = 23;
localparam VAR142 = 46;
input clk;
input reset;
input VAR86;
input VAR44;
input [VAR236-1:0] VAR7; output VAR238;
output [VAR236-1:0] VAR237;
localparam VAR214 = 18; localparam VAR229 ... | mit |
ptracton/wb_soc_template | rtl/LM32/rtl/lm32_jtag.v | 16,522 | module MODULE1 (
VAR54,
VAR42,
VAR27,
VAR65,
VAR19,
VAR23,
VAR51,
VAR14,
VAR37,
VAR34,
VAR56,
VAR10,
VAR61,
VAR12,
VAR9,
VAR11,
VAR20,
VAR4,
VAR44,
VAR18,
VAR60,
VAR26,
VAR30,
VAR47,
VAR52,
VAR63
);
input VAR54; input VAR42;
input VAR27; input VAR65; input [VAR49] VAR19; input [2:0] VAR23;
input [VAR58] VAR51; input VA... | mit |
Valakor/EE201-Text-Editor | Altera_UP_PS2_Command_Out.v | 9,533 | module MODULE1 (
clk,
reset,
VAR6,
VAR7,
VAR15,
VAR1,
VAR2,
VAR20,
VAR3,
VAR11
);
parameter VAR33 = 5050;
parameter VAR9 = 13;
parameter VAR23 = 13'h0001;
parameter VAR22 = 750000;
parameter VAR16 = 20;
parameter VAR27 = 20'h00001;
parameter VAR28 = 100000;
parameter VAR26 = 17;
parameter VAR24 = 17'h00001;
input clk;
... | mit |
SymbiFlow/fpga-tool-perf | third_party/daisho-usb3/usb3_pipe.v | 24,414 | module MODULE1 (
input wire VAR137,
input wire VAR42,
input wire VAR56,
input wire VAR83,
output reg VAR185,
input wire [31:0] VAR181,
input wire [3:0] VAR77,
input wire [1:0] VAR81,
output wire [31:0] VAR201,
output wire [3:0] VAR135,
output wire VAR195,
output wire VAR141,
input wire VAR116,
input wire [5:0] VAR54,
o... | isc |
peteasa/oh | src/emailbox/dv/dut_emailbox.v | 1,920 | module MODULE1(
VAR26, VAR29, VAR22, VAR12, VAR21,
VAR17, VAR23, VAR32, VAR16, VAR10, VAR24, VAR14, VAR25
);
parameter VAR30 = 32;
parameter VAR7 = 12'h810;
parameter VAR33 = 12;
parameter VAR27 = 6;
parameter VAR4 = 2*VAR30 + 40;
parameter VAR8 = 1;
input VAR17;
input VAR23;
input VAR32;
input [VAR8*VAR8-1:0] VAR16;
i... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/Mibench/firmware/outputs/next_hop_ram.v | 52,817 | module MODULE1(clk, addr, VAR23, VAR2, VAR65, en, reset);
input clk;
input [13:2] addr;
input [31:0] VAR23;
output [31:0] VAR2;
input [3:0] VAR65;
input en;
input reset;
VAR21 VAR55(
.VAR54 (VAR2[3:0]),
.VAR34 (addr[13:2]),
.VAR12 (clk),
.VAR33 (VAR23[3:0]),
.VAR26 (en),
.VAR16 (reset),
.VAR61 (VAR65[0])
);
... | mit |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_daala_idct4_stream_0_1/hdl/daala_idct4_stream_v1_0_M00_AXIS.v | 14,375 | module MODULE1 #
(
parameter integer VAR9 = 32,
parameter integer VAR20 = 32
)
(
input wire VAR17,
input wire VAR23,
output wire VAR12,
output wire [VAR9-1 : 0] VAR13,
output wire [(VAR9/8)-1 : 0] VAR3,
output wire VAR7,
input wire VAR26
);
localparam VAR14 = 8;
function integer VAR21 (input integer VAR4);
begin
for(VA... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221a/sky130_fd_sc_hs__o221a_1.v | 2,317 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR10 ,
VAR4 ,
VAR7 ,
VAR9 ,
VAR6,
VAR5
);
output VAR1 ;
input VAR3 ;
input VAR10 ;
input VAR4 ;
input VAR7 ;
input VAR9 ;
input VAR6;
input VAR5;
VAR2 VAR8 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18_2.v | 2,163 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR7,
VAR6,
VAR2 ,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR7;
input VAR6;
input VAR2 ;
input VAR3 ;
VAR5 VAR8 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR4,
VAR1
);
output VAR4;
input VAR1;
supply1 VAR7;
supply0 VAR6;... | apache-2.0 |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/router_mmu.v | 25,305 | module MODULE1(
VAR33,
clk,
VAR19,
VAR43,
VAR4, VAR31,
VAR24,
VAR18,
VAR28,
VAR11, VAR51, VAR6,
VAR3, VAR39,
VAR17, VAR15,
VAR32,
VAR5,
VAR53,
VAR8,
VAR2,
VAR35,
VAR40 );
input VAR33;
input clk;
input [3:0] VAR19;
input VAR43;
input [VAR7-1:0] VAR4, VAR18;
input VAR24;
reg VAR49;
input [VAR48-1:0] VAR31;
output reg [VA... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/dram0_ddr0_rptr.v | 4,414 | module MODULE1(
VAR17, VAR16, VAR36,
VAR7, VAR6, VAR19,
VAR34, VAR9,
VAR33, VAR35,
VAR13, VAR8, VAR21,
VAR27, VAR3, VAR28,
VAR4, VAR23,
VAR10, VAR22, VAR12,
VAR5, VAR11, VAR29,
VAR24, VAR32, VAR30,
VAR25, VAR26, VAR20,
VAR1, VAR18, VAR15, VAR2,
VAR14, VAR31
);
output VAR17;
output [31:0] VAR16;
output [255:0] VAR36;
ou... | gpl-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_PPS_OPENFLOW/DISPATHER/DISPATHER.v | 2,885 | module MODULE1(
input clk,
input reset,
input VAR18,
input [133:0] VAR30,
input VAR14,
input VAR46,
output VAR25,
output VAR26,
output [133:0] VAR21,
output VAR17,
output VAR12,
input VAR20,
input [5:0] VAR28,
input VAR39,input [31:0] VAR11,
input VAR8,
input [133:0] VAR42,
input VAR7,
input VAR13,
output VAR41,
output... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s.pp.blackbox.v | 1,345 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR4,
VAR2,
VAR6 ,
VAR3
);
output VAR1 ;
input VAR5 ;
input VAR4;
input VAR2;
input VAR6 ;
input VAR3 ;
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/ssio_ddr_in_diff.v | 3,213 | module MODULE1 #
(
parameter VAR11 = "VAR29",
parameter VAR17 = "VAR5",
parameter VAR2 = "VAR23",
parameter VAR13 = 1
)
(
input wire VAR18,
input wire VAR14,
input wire [VAR13-1:0] VAR16,
input wire [VAR13-1:0] VAR19,
output wire VAR15,
output wire [VAR13-1:0] VAR22,
output wire [VAR13-1:0] VAR3
);
wire VAR1;
wire [VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a222o/sky130_fd_sc_ls__a222o_1.v | 2,529 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR8 ,
VAR13 ,
VAR4 ,
VAR7 ,
VAR11 ,
VAR6,
VAR12,
VAR2 ,
VAR5
);
output VAR3 ;
input VAR10 ;
input VAR8 ;
input VAR13 ;
input VAR4 ;
input VAR7 ;
input VAR11 ;
input VAR6;
input VAR12;
input VAR2 ;
input VAR5 ;
VAR9 VAR1 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR13(VAR13),
.VAR4(VAR... | apache-2.0 |
fpgasystems/caribou | hw/src/nukv/nukv_decompress.v | 7,419 | module MODULE1 #(
parameter VAR2 = 12,
parameter VAR12 = 9,
parameter VAR27 = 4
)
(
input wire clk,
input wire rst,
input wire [511:0] VAR26,
input wire VAR31,
input wire VAR3,
output reg VAR30,
output reg [511:0] VAR20,
output reg VAR9,
output reg VAR18,
input wire VAR22
);
reg[7:0] VAR15 [0:2**VAR12-1];
reg[VAR12-1:0... | gpl-3.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_kernel_done_detector.v | 4,330 | module MODULE1
parameter VAR15 = 32 )
(
input VAR6,
input VAR18,
input VAR5,
input VAR9,
input VAR4,
input VAR11,
input VAR13,
output VAR8
);
reg [VAR15-1:0] VAR17;
assign VAR7 = ~VAR4 & ~VAR9;
assign VAR8 = (VAR17 == {VAR15{1'b0}});
always @(posedge VAR6 or negedge VAR18)
begin
if ( ~VAR18 )
VAR17 <= {VAR15{1'b0}};
en... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep.behavioral.v | 1,794 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR16 ,
VAR7
);
output VAR8 ;
input VAR12 ;
input VAR16 ;
input VAR7;
supply1 VAR10 ;
supply0 VAR1 ;
supply1 VAR4;
supply1 VAR2 ;
supply0 VAR13 ;
wire VAR5;
wire VAR11 ;
wire VAR9 ;
nor VAR6 (VAR5, VAR16, VAR7 );
bufif1 VAR14 (VAR11 , VAR12, VAR10 );
bufif0 VAR3 (VAR9 , VAR11, VAR1 );
bu... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/saed_90/bsg_mem/bsg_mem_1r1w.v | 1,765 | if (VAR4 == VAR11 && VAR16 == VAR32) \
begin: VAR2 \
VAR21 VAR26 \
(.VAR7 (VAR25) \
,.VAR15 (1'b0) \
,.VAR3 (1'b0) \
,.VAR31 (VAR9) \
,.VAR13 (VAR28) \
,.VAR1 (VAR25) \
,.VAR18 (~VAR27) \
,.VAR29 (1'b0) \
,.VAR19 (VAR14) \
,.VAR30 (VAR6) \
); \
end
module MODULE1 #(parameter VAR33(VAR16)
, parameter VAR33(VAR4)
, param... | bsd-3-clause |
everskar2013/PentiumX | Hardware/Code/ctrl.v | 16,008 | module MODULE1(
clk,
reset,
VAR54,
VAR50,
VAR29,
VAR64,
VAR31,
VAR58,
VAR59,
VAR30,
VAR38,
VAR40,
VAR28,
VAR33,
VAR14,
VAR70,
VAR69,
VAR57,
VAR46,
VAR20,
VAR71,
VAR7,
VAR35,
VAR32,
VAR26,
VAR72,
VAR49,
VAR62,
VAR27,
VAR41,
VAR48,
VAR73,
VAR68
);
input wire clk, reset;
input wire [31: 0] VAR54;
input wire VAR50, VAR29, ... | mit |
myriadrf/A2300 | hdl/wca/hal/WcaLimeIF.v | 8,219 | module MODULE1
(
input VAR40, input VAR60, input VAR46, input reset, input VAR3,
input wire [23:0] VAR15, output reg [23:0] VAR9, output wire VAR13, output wire VAR19,
output wire VAR51, input wire VAR14,
output wire VAR53,
input wire [11:0] VAR20,
output wire VAR35, output wire VAR25,
output wire VAR16,
output wire [1... | gpl-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/dbg_interface/dbg_crc8_d1.v | 6,032 | module MODULE1 (VAR1, VAR4, VAR11, VAR10, VAR3, VAR7);
parameter VAR12 = 1;
input VAR1;
input VAR4;
input VAR11;
input VAR10;
input VAR7;
output [7:0] VAR3;
reg [7:0] VAR3;
function [7:0] VAR2;
input VAR1;
input [7:0] VAR9;
reg [0:0] VAR6;
reg [7:0] VAR8;
reg [7:0] VAR5;
begin
VAR6[0] = VAR1;
VAR8 = VAR9;
VAR5[0] = VAR... | gpl-3.0 |
somethingnew2-0/CS552-CPU | Execute.v | 2,346 | module MODULE1(VAR46, VAR19, VAR9, VAR30, VAR4, VAR14, VAR36, VAR39, VAR13, VAR44, VAR41, VAR17, VAR27, VAR6, VAR42, VAR2, VAR26, VAR12, VAR20, VAR18, VAR40, VAR48, VAR29, VAR16, VAR32, VAR34);
input[15:0] VAR46, VAR19, VAR9;
input[11:0] VAR30;
input [3:0] VAR4;
input [2:0] VAR14, VAR36;
input VAR39, VAR13, VAR44, VAR4... | mit |
olofk/wb_intercon | rtl/verilog/wb_arbiter.v | 3,797 | module MODULE1
parameter VAR11 = 32,
parameter VAR2 = 0)
(
input VAR33,
input VAR12,
input [VAR2*VAR11-1:0] VAR1,
input [VAR2*VAR17-1:0] VAR10,
input [VAR2*4-1:0] VAR27,
input [VAR2-1:0] VAR15,
input [VAR2-1:0] VAR19,
input [VAR2-1:0] VAR36,
input [VAR2*3-1:0] VAR3,
input [VAR2*2-1:0] VAR7,
output [VAR2*VAR17-1:0] VAR2... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxbp/sky130_fd_sc_ls__dfxbp_2.v | 2,226 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR2 ,
VAR10 ,
VAR9,
VAR1,
VAR7 ,
VAR5
);
output VAR3 ;
output VAR6 ;
input VAR2 ;
input VAR10 ;
input VAR9;
input VAR1;
input VAR7 ;
input VAR5 ;
VAR4 VAR8 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4bb/sky130_fd_sc_ls__nand4bb.blackbox.v | 1,336 | module MODULE1 (
VAR3 ,
VAR7,
VAR8,
VAR5 ,
VAR4
);
output VAR3 ;
input VAR7;
input VAR8;
input VAR5 ;
input VAR4 ;
supply1 VAR1;
supply0 VAR9;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxtp/sky130_fd_sc_ms__edfxtp.pp.symbol.v | 1,422 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR6 ,
input VAR8 ,
input VAR4 ,
input VAR7,
input VAR5,
input VAR3
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_banked.v | 4,510 | module MODULE1
, parameter VAR18(VAR44)
, parameter VAR22=0
, parameter VAR43=(VAR17>>3)
, parameter VAR28=1
, parameter VAR30=1
, parameter VAR1=VAR45(VAR44)
, parameter VAR20=(VAR44/VAR30)
, parameter VAR36=VAR45(VAR20)
, parameter VAR32=VAR45(VAR30)
, parameter VAR14=(VAR17/VAR28)
, parameter VAR37=(VAR14>>3)
)
(
in... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_4.behavioral.pp.v | 1,476 | module MODULE1( VAR7, VAR6, VAR8, VAR1, VAR3 );
input VAR6, VAR7;
inout VAR1, VAR3;
output VAR8;
VAR5 VAR4(.VAR7(VAR7),.VAR6(VAR6),.VAR8(VAR8),.VAR1(VAR1),.VAR3(VAR3));
VAR5 VAR2(.VAR7(VAR7),.VAR6(VAR6),.VAR8(VAR8),.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
iamllama/EE2020 | ee2020.cache/ip/50f89269c3fbefe4/dds_compiler_0_stub.v | 1,539 | module MODULE1(VAR5, VAR1,
VAR3, VAR2, VAR4)
;
input VAR5;
input VAR1;
input [23:0]VAR3;
output VAR2;
output [15:0]VAR4;
endmodule | gpl-3.0 |
fpgasystems/caribou | hw/src/nukv/nukv_top_module_v2.v | 39,401 | module MODULE1 #(
parameter VAR153 = 96,
parameter VAR209 = 512,
parameter VAR459 = 512,
parameter VAR347 = 128,
parameter VAR362 = 42,
parameter VAR455 = 24,
parameter VAR10 = 25,
parameter VAR429 = 1,
parameter VAR143 = 0,
parameter VAR95 = 4,
parameter VAR225 = 1,
parameter VAR442 = 0
)(
input wire clk,
input wire r... | gpl-3.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/en_decapsulate_LISP/action.v | 12,450 | module MODULE1(
input clk,
input reset,
input [7:0] VAR33,
input VAR19,
input [15:0] MODULE1,
input VAR5,
input [351:0] VAR4,
input [4:0] VAR25, input VAR12,
input [63:0] VAR52,
input VAR69,
output reg [3:0] VAR66,
output reg VAR30,
output reg [3:0] VAR31,
output reg VAR61,
output reg [10:0] VAR29,
output reg VAR27,
in... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v | 3,934 | module MODULE1 (
input wire VAR1;
input wire VAR12
input wire VAR10;
output wire do
);
wire VAR13 = 1'b1;
wire VAR7 = 1'b0;
wire VAR6 = 1'b0;
reg [7:0] VAR14 [7:0]; reg [2:0] VAR5; reg [7:0] VAR8;
reg [7:0] VAR9, VAR4;
reg [2:0] VAR2;
reg VAR3;
wire clk;
assign clk = VAR7 ^ VAR6 ^ VAR12;
always @(posedge clk)
VAR9 <= {... | gpl-2.0 |
brianbennett/fpga_nes | hw/src/cpu/apu/apu_length_counter.v | 4,104 | module MODULE1
(
input wire VAR6, input wire VAR3, input wire VAR5, input wire VAR10, input wire VAR9, input wire [4:0] VAR1, input wire VAR8, output wire VAR7 );
reg [7:0] VAR2, VAR4;
always @(posedge VAR6)
begin
if (VAR3)
begin
VAR2 <= 8'h00;
end
else
begin
VAR2 <= VAR4;
end
end
always @*
begin
VAR4 = VAR2;
if (!VAR5... | bsd-2-clause |
strigeus/fpganes | src/cpu.v | 11,039 | module MODULE4(input [7:0] VAR75,VAR4,
input VAR97,VAR68,
output [7:0] VAR113,
output VAR99,VAR86);
wire VAR39,VAR65,VAR92,VAR70,VAR69,VAR120,VAR117;
wire VAR37;
wire [7:0] VAR80 = VAR75 ^ VAR4 ^ {8{~VAR68}};
VAR46 VAR76 (.VAR119(VAR39),.VAR97(VAR97),.VAR20(VAR75[0]),.VAR113(VAR80[0]) );
VAR46 VAR25 (.VAR119(VAR65),.VA... | gpl-3.0 |
efabless/openlane | designs/jpeg_encoder/src/zigzag.v | 7,807 | module MODULE1(
clk,
VAR8,
VAR18,
VAR70, VAR31, VAR7, VAR56, VAR55, VAR57, VAR37, VAR13,
VAR61, VAR52, VAR3, VAR19, VAR41, VAR58, VAR39, VAR4,
VAR16, VAR14, VAR35, VAR9, VAR63, VAR11, VAR68, VAR22,
VAR21, VAR25, VAR30, VAR33, VAR45, VAR59, VAR28, VAR49,
VAR12, VAR34, VAR53, VAR64, VAR2, VAR32, VAR23, VAR60,
VAR5, VAR6,... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/synth/ghrd_10as066n2_hps_m.v | 2,056 | module MODULE1 (
input wire VAR16, input wire VAR15, output wire [31:0] VAR4, input wire [31:0] VAR7, output wire VAR2, output wire VAR9, output wire [31:0] VAR6, input wire VAR14, input wire VAR8, output wire [3:0] VAR12, output wire VAR3 );
VAR11 #(
.VAR1 (0),
.VAR13 (50000),
.VAR10 (2)
) VAR5 (
.VAR16 (VAR16), .VAR1... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_1.behavioral.pp.v | 1,254 | module MODULE1( VAR1, VAR4, VAR6, VAR8, VAR2 );
input VAR6, VAR1;
inout VAR8, VAR2;
output VAR4;
VAR5 VAR7(.VAR1(VAR1),.VAR4(VAR4),.VAR6(VAR6),.VAR8(VAR8),.VAR2(VAR2));
VAR5 VAR3(.VAR1(VAR1),.VAR4(VAR4),.VAR6(VAR6),.VAR8(VAR8),.VAR2(VAR2)); | apache-2.0 |
jacgoudsmit/P8X32A_Emulation | Altera/tim.v | 2,509 | module MODULE1
(
input clk, input VAR4, input [6:0] VAR5,
output VAR2, output VAR1 );
reg [6:0] VAR7;
reg [12:0] VAR6;
wire[4:0] VAR3 = {VAR7[6:5], VAR7[2:0]};
assign VAR2 = (VAR3 == 5'b11111) ? clk : VAR6[11];
assign VAR1 = VAR6[12];
always @ (posedge clk)
begin
VAR7 <= VAR5;
end
always @ (posedge clk)
begin
VAR6 <= V... | gpl-3.0 |
freecores/xtea | xtea.v | 8,735 | module MODULE1(VAR25, reset, VAR9, VAR12, VAR5, VAR11, VAR29, VAR13, VAR20);
parameter VAR30 = 8'd0, VAR2 = 8'd1, VAR26 = 8'd2, VAR19 = 8'd3, VAR6 = 8'd4, VAR35 = 8'd5, VAR10 = 8'd6, VAR15 = 8'd7, VAR21 = 8'd8, VAR24 = 8'd9, VAR32 = 8'd10,
VAR22 = 8'd11, VAR7 = 8'd12, VAR34 = 8'd13, VAR33 = 8'd14, VAR1 = 8'd15, VAR23 =... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor3/sky130_fd_sc_hd__xor3.behavioral.pp.v | 1,845 | module MODULE1 (
VAR6 ,
VAR13 ,
VAR7 ,
VAR2 ,
VAR12,
VAR3,
VAR8 ,
VAR11
);
output VAR6 ;
input VAR13 ;
input VAR7 ;
input VAR2 ;
input VAR12;
input VAR3;
input VAR8 ;
input VAR11 ;
wire VAR10 ;
wire VAR4;
xor VAR5 (VAR10 , VAR13, VAR7, VAR2 );
VAR14 VAR1 (VAR4, VAR10, VAR12, VAR3);
buf VAR9 (VAR6 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai.behavioral.v | 1,682 | module MODULE1 (
VAR2 ,
VAR11,
VAR10,
VAR13 ,
VAR3
);
output VAR2 ;
input VAR11;
input VAR10;
input VAR13 ;
input VAR3 ;
supply1 VAR15;
supply0 VAR6;
supply1 VAR14 ;
supply0 VAR7 ;
wire VAR1 ;
wire VAR4 ;
wire VAR9;
nand VAR5 (VAR1 , VAR10, VAR11 );
or VAR12 (VAR4 , VAR3, VAR13 );
nand VAR8 (VAR9, VAR1, VAR4);
buf VAR1... | apache-2.0 |
sabertazimi/hust-lab | architecture/design/fpga/src/max_comparator.v | 1,900 | module MODULE1
(
input [VAR11-1:0] VAR7,
input [VAR11-1:0] VAR2,
input [VAR11-1:0] VAR6,
input [VAR11-1:0] VAR10,
input [VAR11-1:0] VAR4,
input [VAR11-1:0] VAR13,
input [VAR11-1:0] VAR8,
input [VAR11-1:0] VAR3,
output reg [VAR11-1:0] VAR9
);
integer VAR1;
reg [VAR11-1:0] VAR5;
reg [VAR11-1:0] VAR12; | mit |
cpulabs/mist1032sa | src/dps/device/utim64/utim64.v | 8,287 | module MODULE1(
input wire VAR78, input wire VAR44,
input wire VAR42,
input wire VAR68,
output wire VAR38,
input wire VAR64,
input wire [3:0] VAR39,
input wire [31:0] VAR86,
output wire VAR96,
output wire [31:0] VAR14,
output wire [3:0] VAR23
);
wire VAR49;
wire VAR60;
wire VAR72;
wire [31:0] VAR94;
wire [3:0] VAR61;
w... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxtp/sky130_fd_sc_lp__sdfxtp.symbol.v | 1,410 | module MODULE1 (
input VAR6 ,
output VAR2 ,
input VAR8,
input VAR5,
input VAR9
);
supply1 VAR4;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2/sky130_fd_sc_ms__or2.symbol.v | 1,254 | module MODULE1 (
input VAR3,
input VAR7,
output VAR1
);
supply1 VAR4;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ddr3_source/ip_top/mig_7series_v1_9_memc_ui_top_std.v | 36,354 | module MODULE1 #
(
parameter VAR25 = 100,
parameter VAR82 = 64,
parameter VAR195 = "VAR156",
parameter VAR196 = "0", parameter VAR76 = 3, parameter VAR147 = 2, parameter VAR137 = "8", parameter VAR80 = "VAR62", parameter VAR49 = "VAR50", parameter VAR229 = 1, parameter VAR69 = 5,
parameter VAR16 = 12, parameter VAR17 =... | gpl-2.0 |
HashRatio/mm-hashratio | verilog/superkdf9/components/spi/wb_spi.v | 24,095 | module MODULE1 #(
parameter VAR46 = 0,
parameter VAR15 = 0,
parameter VAR29 = 0,
parameter VAR34 = 7,
parameter VAR74 = 1,
parameter VAR32 = 1,
parameter VAR11 = 32,
parameter VAR54 = 2,
parameter VAR31 = 5,
parameter VAR57 = 2)
(
VAR25, VAR7, VAR27,
VAR47,
VAR62,
VAR69,
VAR48,
VAR50,
VAR73,
VAR77, VAR39,
VAR2,
VAR72,
... | unlicense |
AngelTerrones/Antares | Hardware/verilog/antares_pc_register.v | 1,046 | module MODULE1 (
input clk,
input rst,
input [31:0] VAR1,
input VAR4,
output reg [31:0] VAR3
);
always @ ( posedge clk ) begin
VAR3 <= (rst) ? VAR2 : ((VAR4) ? VAR3 : VAR1);
end
endmodule | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/sgate.v | 30,162 | module MODULE1 ( VAR5, VAR8, VAR6, VAR9, VAR3 );
parameter VAR1 = 32;
parameter VAR4 = 32;
parameter VAR2 = 32;
parameter VAR7 = 1;
input [VAR1-1:0] VAR5;
input [VAR4-1:0] VAR8;
input VAR6;
output VAR9;
output [VAR2-1:0] VAR3;
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
end
begin
b... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_int_arb.v | 21,166 | module MODULE1 (
VAR58, VAR72, VAR39, VAR55,
VAR63, VAR46, VAR50, VAR18, VAR12,
VAR90, VAR29, VAR78, VAR57,
VAR97, VAR13, VAR93, VAR49,
VAR77, VAR35, VAR91, VAR5,
VAR53, VAR96, VAR19, VAR48,
VAR37, VAR14, VAR40, VAR8,
VAR27, VAR10, VAR32, VAR26, VAR1,
VAR68, VAR22, VAR3, VAR100,
VAR76, VAR70, VAR44,
VAR66, VAR69, clk, ... | gpl-2.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_slavearbiter.v | 14,312 | module MODULE1
(
input VAR9,
input VAR27,
input [3:0] VAR28,
input VAR21,
input VAR26,
input VAR10,
input VAR19,
input VAR8,
output reg [3:0] VAR1
);
localparam VAR32 = 4'b0000;
localparam VAR12 = 4'b0001;
localparam VAR16 = 4'b0010;
localparam VAR22 = 4'b0011;
localparam VAR23 = 4'b0100;
localparam VAR5 = 4'b0101;
loc... | gpl-3.0 |
tommythorn/yari | shared/rtl/soclib/rs232.v | 2,737 | module MODULE1(input wire clk,
input wire rst,
input wire VAR14 VAR8,
output wire VAR12 VAR6,
input wire VAR15,
input wire [7:0] VAR3,
input wire VAR24,
output wire VAR17,
output wire [7:0] VAR19);
parameter VAR13 = 1;
parameter VAR4 = "input.VAR1";
integer VAR16, VAR25 = 32, VAR26 = 0;
reg [31:0] VAR5 = 0; reg [ 7:0] ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211a/sky130_fd_sc_hdll__o211a.functional.v | 1,454 | module MODULE1 (
VAR9 ,
VAR4,
VAR7,
VAR10,
VAR3
);
output VAR9 ;
input VAR4;
input VAR7;
input VAR10;
input VAR3;
wire VAR6 ;
wire VAR1;
or VAR2 (VAR6 , VAR7, VAR4 );
and VAR8 (VAR1, VAR6, VAR10, VAR3);
buf VAR5 (VAR9 , VAR1 );
endmodule | apache-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/11-general/debugger_unit.v | 17,180 | module MODULE1
parameter VAR55=32,
parameter VAR98=5
)
(
input wire clk,
input wire reset,
output wire VAR22,
output wire [7:0] VAR51,
input wire VAR27,
output wire VAR47,
input wire [VAR55-1:0] VAR102,
input wire [VAR55-1:0] VAR103,
input wire [VAR55-1:0] VAR4,
input wire [VAR55-1:0] VAR97,
input wire [VAR55-1:0] VAR2... | gpl-3.0 |
Digilent/vivado-library | ip/Pmods/PmodMAXSONAR_v1_0/src/PmodMAXSONAR.v | 10,191 | module MODULE1
(VAR110,
VAR137,
VAR97,
VAR121,
VAR10,
VAR106,
VAR13,
VAR56,
VAR96,
VAR48,
VAR41,
VAR23,
VAR122,
VAR30,
VAR27,
VAR35,
VAR147,
VAR133,
VAR4,
VAR144,
VAR112,
VAR24,
VAR14,
VAR73,
VAR117,
VAR49,
VAR132,
VAR83,
VAR37,
VAR53,
VAR148,
VAR82,
VAR143,
VAR89,
VAR65,
VAR135,
VAR59,
VAR107,
VAR91,
VAR36,
VAR5,
VAR1... | mit |
linuxbest/lzs | pcores/comp_unit_v1_00_a/hdl/verilog/hdrram.v | 7,899 | module MODULE1 (
input clk,
input [3:0] VAR1,
input VAR33,
input [31:0] VAR46,
input [3:0] VAR5,
output [31:0] VAR44
);
wire [31:0] VAR7;
VAR42 VAR26 (
.VAR20(VAR1[0]), .VAR17(VAR1[1]), .VAR45(VAR1[2]), .VAR12(VAR1[3]),
.VAR19(VAR46[0]), .VAR47(clk), .VAR27(VAR33),
.VAR23(VAR5[0]), .VAR50(VAR5[1]), .VAR8(VAR5[2]),
.VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22oi/sky130_fd_sc_hdll__a22oi.functional.v | 1,553 | module MODULE1 (
VAR12 ,
VAR8,
VAR10,
VAR9,
VAR2
);
output VAR12 ;
input VAR8;
input VAR10;
input VAR9;
input VAR2;
wire VAR11 ;
wire VAR6 ;
wire VAR7;
nand VAR5 (VAR11 , VAR10, VAR8 );
nand VAR1 (VAR6 , VAR2, VAR9 );
and VAR3 (VAR7, VAR11, VAR6);
buf VAR4 (VAR12 , VAR7 );
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_sprs.v | 24,487 | module MODULE1(
clk, rst,
VAR43, VAR22, flag, VAR8, VAR122, VAR149,
VAR101, VAR84, VAR33,
VAR100, VAR137, VAR113, VAR108, VAR99,
VAR98,
VAR131, VAR44, VAR82, VAR20,
VAR94, VAR138, VAR41, VAR69, VAR118, VAR72, VAR148, VAR51,
VAR4, VAR88, VAR133, VAR112,
VAR34,
VAR57,
VAR52, VAR61, VAR38,
VAR105, VAR136, VAR65,
VAR25, VA... | mit |
asicguy/gplgpu | hdl/altera_project/fifo_128x512a/fifo_128x512a_bb.v | 5,807 | module MODULE1 (
VAR1,
VAR5,
VAR10,
VAR8,
VAR6,
VAR2,
VAR7,
VAR3,
VAR9,
VAR4);
input VAR1;
input [127:0] VAR5;
input VAR10;
input VAR8;
input VAR6;
input VAR2;
output [127:0] VAR7;
output VAR3;
output VAR9;
output [8:0] VAR4;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd.functional.pp.v | 1,200 | module MODULE1 (
VAR2,
VAR3,
VAR4 ,
VAR1
);
input VAR2;
input VAR3;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
pwwu/FPGA | VGAbased/final/vga_sync.v | 4,129 | module MODULE1
(
input wire clk, reset,
output wire VAR13, VAR10, VAR25, VAR8,
output wire [9:0] VAR2, VAR22
);
localparam VAR21 = 640; localparam VAR1 = 48 ; localparam VAR7 = 16 ; localparam VAR11 = 96 ; localparam VAR3 = 480; localparam VAR20 = 27; localparam VAR14 = 16; localparam VAR12 = 2;
reg VAR6;
wire VAR17;
r... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_1.behavioral.pp.v | 1,383 | module MODULE1( VAR1, VAR10, VAR6, VAR5, VAR7, VAR9, VAR2 );
input VAR1, VAR10, VAR6, VAR5;
inout VAR9, VAR2;
output VAR7;
VAR8 VAR4(.VAR1(VAR1),.VAR10(VAR10),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7),.VAR9(VAR9),.VAR2(VAR2));
VAR8 VAR3(.VAR1(VAR1),.VAR10(VAR10),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7),.VAR9(VAR9),.VAR2(VAR2)); | apache-2.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/common/priority_encoder_40to6.v | 1,498 | module MODULE1 (
VAR3,
valid,
VAR2,
enable
);
output[5:0] VAR3;
output valid;
input[39:0] VAR2;
input enable;
assign valid = (|VAR2) & enable;
assign VAR3 = (!enable) ? 6'd0 : (
(VAR2[0]) ? 6'd0 :
(VAR2[1]) ? 6'd1 :
(VAR2[2]) ? 6'd2 :
(VAR2[3]) ? 6'd3 :
(VAR2[4]) ? 6'd4 :
(VAR2[5]) ? 6'd5 :
(VAR2[6]) ? 6'd6 :
(VAR2[7])... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbp/sky130_fd_sc_ls__dlxbp.pp.blackbox.v | 1,336 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR8 ,
VAR7,
VAR3,
VAR6,
VAR1 ,
VAR5
);
output VAR4 ;
output VAR2 ;
input VAR8 ;
input VAR7;
input VAR3;
input VAR6;
input VAR1 ;
input VAR5 ;
endmodule | apache-2.0 |
ptracton/wb_soc_template | rtl/LM32/rtl/lm32_instruction_unit.v | 32,371 | module MODULE1 (
VAR115,
VAR34,
VAR39,
VAR81,
VAR136,
VAR108,
VAR63,
VAR85,
VAR60,
VAR100,
VAR146,
VAR134,
VAR87,
VAR67,
VAR120,
VAR105,
VAR33,
VAR125,
VAR72,
VAR149,
VAR5,
VAR14,
VAR78,
VAR80,
VAR107,
VAR157,
VAR161,
VAR95,
VAR86,
VAR53,
VAR91,
VAR77,
VAR70,
VAR21,
VAR98,
VAR19,
VAR75,
VAR144,
VAR18,
VAR48,
VAR140,
VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2b/sky130_fd_sc_hs__nor2b.symbol.v | 1,290 | module MODULE1 (
input VAR1 ,
input VAR5,
output VAR2
);
supply1 VAR4;
supply0 VAR3;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/ccx_arb_atomq.v | 3,112 | module MODULE1(
VAR7, VAR13,
VAR5, VAR16, VAR12, VAR14, VAR4, VAR18
);
output VAR7; output VAR13;
input VAR5; input VAR16; input VAR12;
input VAR14;
input VAR4;
input VAR18;
wire VAR11;
wire VAR1;
wire VAR3;
wire VAR3;
wire VAR7;
assign VAR1 = ~VAR5 ? VAR14 : VAR3;
VAR8 #(1) VAR6(
.din (VAR1),
.VAR17 (VAR3),
.clk (VAR4... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_led_controller_0_0/ip_design_led_controller_0_0_stub.v | 2,577 | module MODULE1(VAR18, VAR17, VAR19,
VAR3, VAR7, VAR4, VAR16, VAR15,
VAR2, VAR10, VAR6, VAR14, VAR12,
VAR5, VAR1, VAR13, VAR9, VAR21,
VAR8, VAR22, VAR11, VAR20)
;
output [7:0]VAR18;
input [3:0]VAR17;
input [2:0]VAR19;
input VAR3;
output VAR7;
input [31:0]VAR4;
input [3:0]VAR16;
input VAR15;
output VAR2;
output [1:0]VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41o/sky130_fd_sc_hd__a41o.pp.blackbox.v | 1,415 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR3 ,
VAR9 ,
VAR2 ,
VAR7 ,
VAR1,
VAR6,
VAR8 ,
VAR10
);
output VAR4 ;
input VAR5 ;
input VAR3 ;
input VAR9 ;
input VAR2 ;
input VAR7 ;
input VAR1;
input VAR6;
input VAR8 ;
input VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probec_p/sky130_fd_sc_hvl__probec_p_8.v | 2,072 | module MODULE2 (
VAR1 ,
VAR6 ,
VAR5,
VAR4,
VAR2 ,
VAR7
);
output VAR1 ;
input VAR6 ;
input VAR5;
input VAR4;
input VAR2 ;
input VAR7 ;
VAR3 VAR8 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR1,
VAR6
);
output VAR1;
input VAR6;
supply1 VAR5;
supply0 VAR4;... | apache-2.0 |
freecores/zet86 | impl/virtex4-ml403ep/dbg/hw_dbg.v | 11,367 | module MODULE1 (
input clk,
input VAR36,
output reg rst,
input VAR18,
input VAR22,
input VAR30,
input VAR32,
input VAR3,
output reg [15:0] VAR26,
output reg [11:1] VAR8,
output VAR7,
output VAR33,
output [ 1:0] VAR50,
output reg VAR43,
input VAR47,
input [15:0] VAR51,
output [19:1] VAR15,
output VAR31,
output [ 1:0] VA... | gpl-3.0 |
ElegantLin/My-CPU | Small Program/Small Program.srcs/sources_1/imports/new/VGA_Control.v | 2,056 | module MODULE1
(
input clk,
input rst,
input [7:0]VAR19,
input [7:0]VAR18,
input [7:0]VAR2,
output reg[9:0]VAR3,
output reg[9:0]VAR7,
output reg VAR14,
output reg VAR12,
output reg [11:0] VAR17
);
reg [19:0]VAR5;
reg [9:0]VAR9;
reg VAR11;
localparam VAR15 = 7'b0000000;
localparam VAR6 = 7'b0000001;
localparam VAR16 = 7... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor3/sky130_fd_sc_hdll__xnor3.pp.blackbox.v | 1,310 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR7 ,
VAR2 ,
VAR4,
VAR8,
VAR6 ,
VAR1
);
output VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR2 ;
input VAR4;
input VAR8;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22oi/sky130_fd_sc_lp__a22oi.blackbox.v | 1,364 | module MODULE1 (
VAR1 ,
VAR8,
VAR6,
VAR7,
VAR2
);
output VAR1 ;
input VAR8;
input VAR6;
input VAR7;
input VAR2;
supply1 VAR4;
supply0 VAR9;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfsbp/sky130_fd_sc_lp__sdfsbp.behavioral.pp.v | 2,949 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR12 ,
VAR16 ,
VAR14 ,
VAR2 ,
VAR30,
VAR28 ,
VAR8 ,
VAR22 ,
VAR27
);
output VAR1 ;
output VAR6 ;
input VAR12 ;
input VAR16 ;
input VAR14 ;
input VAR2 ;
input VAR30;
input VAR28 ;
input VAR8 ;
input VAR22 ;
input VAR27 ;
wire VAR33 ;
wire VAR15 ;
wire VAR32 ;
reg VAR25 ;
wire VAR29 ;
wire... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2o/sky130_fd_sc_hd__a2bb2o.symbol.v | 1,451 | module MODULE1 (
input VAR4,
input VAR1,
input VAR7 ,
input VAR9 ,
output VAR5
);
supply1 VAR3;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/011J1G2/hdl/periferico_audio/peripheral_audio.v | 1,709 | module MODULE1(clk , rst , din , VAR11,wr,rd , addr, dout, VAR13, VAR5, VAR7,VAR12 );
input clk;
input rst;
input [15:0] din;
input VAR11;
input wr;
input rd;
input [3:0]addr; output reg [15:0]dout;
output VAR5;
output VAR13;
output VAR7;
input VAR12;
wire VAR10;
wire VAR2;
wire VAR1;
reg enable;
reg [2:0] VAR3;
VAR8 V... | gpl-3.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T25-uart-rx/baudgen_rx.v | 1,964 | module MODULE1
parameter VAR1 = VAR5
)
(
input wire clk,
input wire VAR2,
output wire VAR8);
localparam VAR6 = VAR3(VAR1);
localparam VAR7 = (VAR1 >> 1);
reg [VAR6-1:0] VAR4 = 0;
always @(posedge clk)
if (VAR2)
VAR4 <= (VAR4 == VAR1 - 1) ? 0 : VAR4 + 1;
else
VAR4 <= VAR1 - 1;
assign VAR8 = (VAR4 == VAR7) ? VAR2 : 0;
en... | gpl-2.0 |
erwango/zephyr | arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da_top.v | 1,449 | module MODULE1 (
input wire VAR13,
input wire VAR6,
input wire VAR7,
output wire VAR11,
output wire [4:0] VAR5
);
reg [25:0] VAR10;
VAR4 VAR1 (
.VAR2 (VAR13),
.VAR9 (VAR6),
.VAR8 (VAR7), .VAR3 (VAR11), .VAR12 () );
always @(posedge VAR13 or negedge VAR6)
if (!VAR6)
VAR10 <= 26'h0; else
VAR10 <= VAR10 + 1'b1;
assign VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtp/sky130_fd_sc_hs__dlrtp.functional.v | 1,784 | module MODULE1 (
VAR4 ,
VAR10 ,
VAR9 ,
VAR7,
VAR1 ,
VAR8
);
input VAR4 ;
input VAR10 ;
output VAR9 ;
input VAR7;
input VAR1 ;
input VAR8 ;
wire VAR11;
wire VAR3;
not VAR12 (VAR11 , VAR7 );
VAR13 VAR2 VAR5 (VAR3 , VAR1, VAR8, VAR11, VAR4, VAR10);
buf VAR6 (VAR9 , VAR3 );
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9122_v6_00_a/hdl/verilog/axi_ad9122_channel.v | 5,787 | module MODULE1 (
VAR4,
VAR13,
VAR8,
VAR42,
VAR24,
VAR22,
VAR7,
VAR47,
VAR48,
VAR35,
VAR45,
VAR37,
VAR43,
VAR31,
VAR51,
VAR19,
VAR18);
parameter VAR53 = 32'h0;
input VAR4;
input VAR13;
output [15:0] VAR8;
output [15:0] VAR42;
output [15:0] VAR24;
output [15:0] VAR22;
input VAR7;
input VAR47;
input VAR48;
input VAR35;
in... | mit |
Digilent/vivado-library | ip/PWM_Analyzer_1.0/hdl/PWM_Analyzer_v1_0_S00_AXI.v | 15,330 | module MODULE1 #
(
parameter integer VAR9 = 32,
parameter integer VAR3 = 4
)
(
input wire VAR51,
input wire VAR13,
input wire VAR24,
input wire [VAR3-1 : 0] VAR30,
input wire [2 : 0] VAR26,
input wire VAR27,
output wire VAR25,
input wire [VAR9-1 : 0] VAR5,
input wire [(VAR9/8)-1 : 0] VAR8,
input wire VAR16,
output wire... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_2.functional.v | 1,384 | module MODULE1( VAR14, VAR3, VAR7, VAR20, VAR9, VAR19, VAR4 );
input VAR4, VAR19, VAR14, VAR7, VAR3, VAR9;
output VAR20;
wire VAR8;
not VAR18( VAR8, VAR3 );
wire VAR11;
not VAR1( VAR11, VAR9 );
wire VAR10;
and VAR13( VAR10, VAR8, VAR11, VAR4 );
wire VAR17;
and VAR6( VAR17, VAR11, VAR19, VAR3 );
wire VAR16;
and VAR12( V... | apache-2.0 |
olofk/oh | elink/hdl/etx_clocks.v | 9,096 | module MODULE1 (
VAR129, VAR91, VAR38, VAR44, VAR112, VAR130,
VAR1, VAR97, VAR87,
VAR113, VAR15, VAR61
);
parameter VAR90 = 4; else
parameter VAR90 = 8; VAR26
parameter VAR92 = 100;
parameter VAR55 = 300;
parameter VAR31 = 600;
parameter VAR74 = 90;
localparam real VAR85 = 1000.000000/VAR92;
localparam integer VAR125 =... | gpl-3.0 |
AmeerAbdelhadi/Switched-Multiported-RAM | mrram.v | 5,460 | module MODULE1
localparam VAR15 = VAR5(VAR7);
reg [VAR15-1:0] VAR25 [VAR22-1:0]; wire [VAR2-1:0] VAR4 [VAR22-1:0];
always @* begin
end
genvar VAR11;
generate
for (VAR11=0 ; VAR11<VAR22 ; VAR11=VAR11+1) begin: VAR21
VAR8 #( .VAR7 (VAR7 ), .VAR2 (VAR2 ), .VAR12 (VAR12 ), .VAR16 (VAR16 ), .VAR20 (VAR20 )) VAR19 ( .clk (cl... | bsd-3-clause |
chriswynnyk/american-put-verilog | american_put_cyclone/src/fp_add_v1.v | 147,342 | module MODULE1
(
VAR9,
VAR6,
VAR11,
VAR2,
VAR8,
VAR1) ;
input VAR9;
input VAR6;
input VAR11;
input [54:0] VAR2;
input [5:0] VAR8;
output [54:0] VAR1;
reg [54:0] VAR7;
wire VAR4;
wire [31:0] VAR5;
wire [384:0] VAR10;
wire [5:0] VAR3; | apache-2.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/spihub/spihub.v | 1,794 | module MODULE1(
input wire VAR22,
input wire VAR18,
output reg VAR7,
output wire VAR15,
output wire VAR21,
input wire VAR9,
input wire VAR25,
input wire VAR27,
input wire VAR24,
input wire [7:0] VAR20,
output wire [7:0] VAR2,
input wire VAR10,
output reg VAR12,
input wire VAR14,
input wire VAR26,
input wire [7:0] VAR4,... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v6es_gtx_x4_250/source/gtx_tx_sync_rate_v6.v | 14,057 | module MODULE1
parameter VAR33 = 1,
parameter VAR25 = 0 )
(
output reg VAR40 = 1'b0,
output reg VAR51 = 1'b0,
output reg VAR50 = 1'b0,
output reg VAR55 = 1'b0,
output reg VAR32 = 1'b0,
output reg VAR26 = 1'b0,
output reg VAR56 = 1'b0,
output reg VAR39 = 1'b0,
input VAR52,
input VAR8,
input VAR59,
input VAR29,
input VAR... | lgpl-3.0 |
cpulabs/mist1032sa | src/core/scheduler2/scheduler2_allocate_rsv_station.v | 5,074 | module MODULE1 #(
parameter VAR8 = 4'h0
)(
input wire VAR6,
input wire VAR52,
input wire VAR16,
input wire VAR27,
input wire VAR24,
input wire VAR2,
input wire VAR45,
input wire VAR26,
input wire VAR48,
input wire VAR25,
input wire VAR41,
input wire VAR50,
input wire VAR20,
input wire VAR22,
input wire VAR19,
input wir... | bsd-2-clause |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_alpha.v | 2,543 | module MODULE1 #(
parameter VAR11 = 26
) (
input VAR37,
input VAR16,
output VAR10,
input [5:0] VAR38,
input VAR12,
output VAR24,
input [15:0] VAR26,
input [VAR11-1-1:0] VAR4,
input [15:0] VAR18,
output VAR30,
input VAR31,
output reg [VAR11-1-1:0] VAR2,
output [15:0] VAR20
);
wire en;
reg VAR29;
reg VAR34;
reg VAR3;
alw... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_pktout_asm.v | 6,492 | module MODULE1 (
VAR35, VAR42, VAR3,
VAR20, VAR32, VAR34, VAR6,
VAR13, VAR1, VAR24, VAR8,
VAR9, VAR41, VAR21, VAR18,
VAR16, VAR22, VAR5, VAR23,
VAR40, VAR30, VAR19, VAR38,
VAR26, VAR7, VAR10, VAR4, VAR15,
VAR27, VAR36, VAR12, VAR14, VAR28,
VAR43, VAR17, VAR25, VAR2,
VAR37, VAR11, VAR33, VAR29,
clk
);
input [3:0] VAR20;... | gpl-2.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/PSelect/PSelect_stub.v | 1,258 | module MODULE1(VAR2, VAR3, VAR1)
;
input VAR2;
input [9:0]VAR3;
output [799:0]VAR1;
endmodule | gpl-3.0 |
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