repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxtp/sky130_fd_sc_hd__sdfxtp.blackbox.v | 1,344 | module MODULE1 (
VAR7 ,
VAR1,
VAR5 ,
VAR8,
VAR4
);
output VAR7 ;
input VAR1;
input VAR5 ;
input VAR8;
input VAR4;
supply1 VAR9;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/basys3/abacus/seg7decimal.v | 2,323 | module MODULE1(
input [15:0] VAR2,
input clk,
input VAR8,
output reg [6:0] VAR3,
output reg [3:0] VAR1,
output wire VAR5
);
wire [1:0] VAR6;
reg [3:0] VAR4;
wire [3:0] VAR7;
reg [19:0] VAR9;
assign VAR5 = 1;
assign VAR6 = VAR9[19:18];
assign VAR7 = 4'b1111;
always @(posedge clk)
case(VAR6)
0:VAR4 = VAR2[3:0]; 1:VAR4 = ... | apache-2.0 |
jameshegarty/rigel | platform/camera1x/vsrc/MMIO_slave.v | 9,900 | module MODULE1(
input VAR115,
input VAR14,
output VAR45,
input [31:0] VAR46,
input [11:0] VAR18,
output VAR120,
input VAR110,
input [31:0] VAR10,
input [11:0] VAR41,
output VAR53,
input VAR116,
output [11:0] VAR89,
input VAR68,
output [1:0] VAR108,
output VAR76,
output [31:0] VAR4,
output [11:0] VAR33,
output VAR77,
in... | mit |
ptracton/wb_soc_template | rtl/ALTERA/wb_rom_32x8192_bb.v | 5,097 | module MODULE1 (
address,
VAR2,
VAR1);
input [12:0] address;
input VAR2;
output [31:0] VAR1;
tri1 VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4bb/sky130_fd_sc_ms__or4bb_2.v | 2,314 | module MODULE2 (
VAR5 ,
VAR6 ,
VAR1 ,
VAR9 ,
VAR2 ,
VAR4,
VAR10,
VAR7 ,
VAR11
);
output VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR9 ;
input VAR2 ;
input VAR4;
input VAR10;
input VAR7 ;
input VAR11 ;
VAR3 VAR8 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VA... | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/pll.v | 4,224 | module MODULE1 (
address,
VAR3,
clk,
read,
VAR4,
write,
VAR17,
VAR6,
VAR16,
VAR13,
VAR9
)
;
output VAR6;
output VAR16;
output [ 15: 0] VAR13;
output VAR9;
input [ 2: 0] address;
input VAR3;
input clk;
input read;
input VAR4;
input write;
input [ 15: 0] VAR17;
wire VAR8;
wire VAR1;
wire VAR6;
wire VAR16;
wire VAR18;
wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill/sky130_fd_sc_ms__fill.symbol.v | 1,186 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
jairov4/accel-oil | solution_spartan6/syn/verilog/nfa_accept_samples_generic_hw_add_16ns_16ns_16_4.v | 5,914 | module MODULE1(clk, reset, VAR16, VAR22, VAR17, VAR38);
input clk;
input reset;
input VAR16;
input [16 - 1 : 0] VAR22;
input [16 - 1 : 0] VAR17;
output [16 - 1 : 0] VAR38;
wire [16 - 1 : 0] VAR10;
wire [16 - 1 : 0] VAR39;
wire [4 - 1 : 0] VAR46;
wire [4 - 1 : 0] VAR2;
wire [8 - 1 : 4] VAR18;
wire [8 - 1 : 4] VAR12;
wir... | lgpl-3.0 |
walkthetalk/fsref | ip/axis_scaler/src/axis_scaler.v | 9,416 | module MODULE1 #
(
parameter integer VAR22 = 8,
parameter integer VAR14 = 10,
parameter integer VAR104 = 10,
parameter integer VAR89 = 10,
parameter integer VAR11 = 10,
parameter integer VAR95 = 8,
parameter integer VAR72 = 0,
parameter integer VAR64 = 0,
parameter integer VAR6 = 1
) (
input wire clk,
input wire VAR13,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor2/sky130_fd_sc_hdll__xor2.symbol.v | 1,299 | module MODULE1 (
input VAR5,
input VAR7,
output VAR1
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21a/sky130_fd_sc_hdll__o21a_4.v | 2,264 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR1 ,
VAR3 ,
VAR10,
VAR7,
VAR9 ,
VAR5
);
output VAR2 ;
input VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR10;
input VAR7;
input VAR9 ;
input VAR5 ;
VAR4 VAR8 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3b/sky130_fd_sc_hdll__nand3b_1.v | 2,245 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR4 ,
VAR6 ,
VAR5,
VAR1,
VAR10 ,
VAR9
);
output VAR8 ;
input VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR5;
input VAR1;
input VAR10 ;
input VAR9 ;
VAR2 VAR7 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_2.functional.pp.v | 1,583 | module MODULE1( VAR15, VAR20, VAR4, VAR7, VAR11, VAR8 );
input VAR20, VAR15, VAR4;
inout VAR11, VAR8;
output VAR7;
wire VAR6;
and VAR21( VAR6, VAR20, VAR15, VAR4 );
wire VAR19;
not VAR9( VAR19, VAR15 );
wire VAR18;
not VAR12( VAR18, VAR4 );
wire VAR17;
and VAR1( VAR17, VAR19, VAR18, VAR20 );
wire VAR16;
not VAR3( VAR16... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/xilinx_lpddr/xilinx_ddr2_if.v | 44,896 | module MODULE2 (
input [31:0] VAR105,
input VAR190,
input VAR130,
input [2:0] VAR176,
input [1:0] VAR60,
input VAR55,
input [3:0] VAR180,
input [31:0] VAR127,
output [31:0] VAR120,
output VAR160,
input [31:0] VAR82,
input VAR27,
input VAR231,
input [2:0] VAR203,
input [1:0] VAR215,
input VAR123,
input [3:0] VAR245,
inp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.v | 2,290 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR1 ,
VAR9 ,
VAR6,
VAR3 ,
VAR4
);
output VAR7 ;
input VAR5 ;
input VAR1 ;
input VAR9 ;
input VAR6;
input VAR3 ;
input VAR4 ;
VAR2 VAR8 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR7,
VAR5
);
output VAR7;
inpu... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/rom_shared_ipv4.v | 10,659 | module MODULE1 (
VAR45,
VAR48,
VAR37,
VAR14,
VAR58,
VAR51,
VAR59,
VAR13);
input VAR45;
input [11:0] VAR48;
input [11:0] VAR37;
input VAR14;
input VAR58;
input VAR51;
output [31:0] VAR59;
output [31:0] VAR13;
tri0 VAR45;
tri1 VAR14;
tri1 VAR58;
tri1 VAR51;
wire [31:0] VAR31;
wire [31:0] VAR20;
wire VAR60 = 1'h0;
wire [3... | mit |
zKarp/Karpentium-Processor | src/verilog/instruction_register.v | 1,043 | module MODULE1(clk,in,out,VAR3,VAR2,enable,VAR4);
input clk,VAR4,VAR2,enable; input [15:0] in; output [15:0] out; output [3:0] VAR3; reg [15:0] VAR5;
VAR1 begin VAR5 = 16'VAR6; end
always @(posedge(clk))
begin
if(VAR4) begin
VAR5 = 16'VAR6;
end
else if (VAR2) begin
VAR5 = in;
end
else begin
VAR5 = VAR5;
end
end
assign ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4/sky130_fd_sc_ls__nand4.functional.pp.v | 1,846 | module MODULE1 (
VAR9 ,
VAR11 ,
VAR8 ,
VAR13 ,
VAR14 ,
VAR1,
VAR10,
VAR4 ,
VAR3
);
output VAR9 ;
input VAR11 ;
input VAR8 ;
input VAR13 ;
input VAR14 ;
input VAR1;
input VAR10;
input VAR4 ;
input VAR3 ;
wire VAR15 ;
wire VAR5;
nand VAR2 (VAR15 , VAR14, VAR13, VAR8, VAR11 );
VAR6 VAR12 (VAR5, VAR15, VAR1, VAR10);
buf VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux4/sky130_fd_sc_ms__mux4_1.v | 2,444 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR13 ,
VAR7 ,
VAR2 ,
VAR3 ,
VAR12 ,
VAR1,
VAR10,
VAR4 ,
VAR8
);
output VAR9 ;
input VAR6 ;
input VAR13 ;
input VAR7 ;
input VAR2 ;
input VAR3 ;
input VAR12 ;
input VAR1;
input VAR10;
input VAR4 ;
input VAR8 ;
VAR11 VAR5 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR13(VAR13),
.VAR7(VAR7),
.VAR2(VAR2),... | apache-2.0 |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/mouse_painter.v | 1,418 | module MODULE1(
input [4:0] VAR7,
output reg [7:0] VAR2
);
parameter [7:0] VAR3 = 8'h01;
parameter [7:0] VAR11 = 8'h03;
parameter [7:0] VAR8 = 8'h07;
parameter [7:0] VAR12 = 8'h0F;
parameter [7:0] VAR5 = 8'h1F;
parameter [7:0] VAR6 = 8'h3F;
parameter [7:0] VAR4 = 8'h7F;
parameter [7:0] VAR13 = 8'hFF;
parameter [7:0] VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_1.behavioral.v | 2,754 | module MODULE1( VAR3, VAR13, VAR23, VAR19 );
input VAR23, VAR13, VAR3;
output VAR19;
reg VAR8;
VAR1 VAR24(.VAR3(VAR3),.VAR13(VAR13),.VAR23(VAR23),.VAR19(VAR19),.VAR8(VAR8));
VAR1 VAR2(.VAR3(VAR3),.VAR13(VAR13),.VAR23(VAR23),.VAR19(VAR19),.VAR8(VAR8));
not VAR5(VAR20,VAR13);
not VAR16(VAR10,VAR3);
and VAR9(VAR6,VAR10,VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2o/sky130_fd_sc_hs__a2bb2o.functional.pp.v | 2,132 | module MODULE1 (
VAR13,
VAR14,
VAR8 ,
VAR4,
VAR7,
VAR9 ,
VAR5
);
input VAR13;
input VAR14;
output VAR8 ;
input VAR4;
input VAR7;
input VAR9 ;
input VAR5 ;
wire VAR5 VAR10 ;
wire VAR5 VAR17 ;
wire VAR15 ;
wire VAR16;
and VAR2 (VAR10 , VAR9, VAR5 );
nor VAR6 (VAR17 , VAR4, VAR7 );
or VAR12 (VAR15 , VAR17, VAR10 );
VAR3 V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdlclkp/sky130_fd_sc_lp__sdlclkp.blackbox.v | 1,297 | module MODULE1 (
VAR8,
VAR1 ,
VAR2,
VAR6
);
output VAR8;
input VAR1 ;
input VAR2;
input VAR6 ;
supply1 VAR5;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_onchip_memory2_0.v | 3,021 | module MODULE1 (
address,
VAR9,
VAR28,
clk,
VAR31,
reset,
VAR25,
write,
VAR29,
VAR2
)
;
parameter VAR6 = "MODULE1.VAR15";
output [ 31: 0] VAR2;
input [ 15: 0] address;
input [ 3: 0] VAR9;
input VAR28;
input clk;
input VAR31;
input reset;
input VAR25;
input write;
input [ 31: 0] VAR29;
wire VAR23;
wire [ 31: 0] VAR2;
wi... | gpl-2.0 |
AE9RB/peaberry | peaberry.cydsn/SyncSOF/SyncSOF.v | 3,862 | module MODULE1 (
input VAR24,
input VAR5,
input VAR9
);
wire [6:0] VAR10;
VAR7 #(.VAR8(7'b0111111))
VAR29 (
.VAR24(VAR24),
.reset(VAR5),
.VAR12(1'b0),
.enable(1'b1),
.VAR2(VAR10),
.VAR19(VAR6)
);
wire [6:0] VAR21;
VAR7 #(.VAR8(7'b0111111))
VAR16 (
.VAR24(VAR6),
.reset(VAR5),
.VAR12(1'b0),
.enable(1'b1),
.VAR2(VAR21),
.... | apache-2.0 |
DougFirErickson/parallella-hw | fpga/src/elink/hdl/ecfg.v | 9,307 | module MODULE1 (
VAR6, VAR52, VAR41, VAR21,
VAR35, VAR42, VAR33,
VAR13, VAR44, VAR47,
VAR27, VAR8, VAR10,
VAR1, VAR5, VAR25, VAR48, VAR2, VAR49, VAR56,
VAR4, VAR31, VAR29, VAR9,
VAR3
);
parameter VAR30 = 5; parameter VAR12 = 12'h808; parameter VAR16 = 16'h0000; parameter VAR38 = 4'd7;
input VAR1; output VAR6;
input VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrbp/sky130_fd_sc_hs__sdfrbp.blackbox.v | 1,445 | module MODULE1 (
VAR7,
VAR8 ,
VAR4 ,
VAR1 ,
VAR9 ,
VAR2 ,
VAR6
);
input VAR7;
input VAR8 ;
input VAR4 ;
output VAR1 ;
output VAR9 ;
input VAR2 ;
input VAR6 ;
supply1 VAR3;
supply0 VAR5;
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/reorder_queue_input.v | 17,754 | module MODULE1
parameter VAR26 = 5, parameter VAR39 = 8, parameter VAR84 = 5, parameter VAR74 = 10, parameter VAR46 = VAR32/32,
parameter VAR4 = VAR90(VAR46),
parameter VAR48 = VAR90(VAR46+1),
parameter VAR80 = 2**VAR26)
(input VAR17, input VAR79, input VAR9, input [VAR32-1:0] VAR3, input [(VAR32/32)-1:0] VAR66, input ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4bb/sky130_fd_sc_hdll__nand4bb.functional.pp.v | 2,020 | module MODULE1 (
VAR16 ,
VAR2 ,
VAR12 ,
VAR3 ,
VAR17 ,
VAR7,
VAR6,
VAR14 ,
VAR5
);
output VAR16 ;
input VAR2 ;
input VAR12 ;
input VAR3 ;
input VAR17 ;
input VAR7;
input VAR6;
input VAR14 ;
input VAR5 ;
wire VAR15 ;
wire VAR10 ;
wire VAR11;
nand VAR13 (VAR15 , VAR17, VAR3 );
or VAR4 (VAR10 , VAR12, VAR2, VAR15 );
VAR8 ... | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/led_green.v | 2,156 | module MODULE1 (
address,
VAR6,
clk,
VAR3,
VAR8,
VAR4,
VAR5,
VAR1
)
;
output [ 8: 0] VAR5;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR6;
input clk;
input VAR3;
input VAR8;
input [ 31: 0] VAR4;
wire VAR2;
reg [ 8: 0] VAR7;
wire [ 8: 0] VAR5;
wire [ 8: 0] VAR9;
wire [ 31: 0] VAR1;
assign VAR2 = 1;
assign VAR9 ... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/Multipliers/Karatsubas/Karatsubas.srcs/sources_1/imports/sine_cosine_CORDIC/sign_inverter.v | 1,509 | module MODULE1 #(parameter VAR3 = 32)
(
input wire [VAR3-1:0] VAR1,
input wire [1:0] VAR5,
input wire VAR2,
output reg [VAR3-1:0] VAR4
);
always@*
begin
if(VAR2 == 1'b0) begin
if(VAR5 == 2'b00 || VAR5 == 2'b11) begin
VAR4 = VAR1;
end
else
begin
if((VAR5 == 2'b01) && (VAR1[VAR3-1] == 1'b0))
begin
VAR4 = {1'b1,VAR1[VAR3-... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9361_v1_00_a/hdl/verilog/axi_ad9361_tx_channel.v | 5,811 | module MODULE1 (
VAR14,
VAR51,
VAR26,
VAR41,
VAR22,
VAR35,
VAR15,
VAR7,
VAR13,
VAR8,
VAR53,
VAR48,
VAR3,
VAR12,
VAR9,
VAR27,
VAR36);
parameter VAR28 = 32'h0;
parameter VAR46 = 0;
input VAR14;
input VAR51;
output [15:0] VAR26;
input VAR41;
input VAR22;
input VAR35;
input VAR15;
output VAR7;
output VAR13;
input VAR8;
inp... | mit |
ultraembedded/riscv | top_cache_axi/src_v/dcache_core.v | 31,420 | module MODULE1
(
input VAR44
,input VAR150
,input [ 31:0] VAR60
,input [ 31:0] VAR113
,input VAR142
,input [ 3:0] VAR126
,input VAR102
,input [ 10:0] VAR67
,input VAR16
,input VAR52
,input VAR15
,input VAR43
,input VAR36
,input VAR8
,input [ 31:0] VAR37
,output [ 31:0] VAR45
,output VAR136
,output VAR121
,output VAR29
... | bsd-3-clause |
HackSlash/SparcCool | cpu/SparCool.v | 1,262 | module MODULE1(); endmodule
module MODULE5(); endmodule
module MODULE4(VAR7,VAR8,VAR18);
inout VAR7;
input [64000:0]VAR8; output VAR18;
assign VAR18 = VAR8[VAR7];
assign VAR7 = VAR7+4;
endmodule
module MODULE2(VAR14,VAR15,VAR16,VAR20,b1,VAR6,VAR23,VAR9,VAR2);
output[64:0] VAR14, VAR15;
input[64:0] VAR16,VAR20,b1,VAR6;
... | unlicense |
osrf/wandrr | firmware/motor_controller/fpga/usb_crossbar.v | 1,261 | module MODULE1
(input VAR12,
input [15:0] sel, input [39:0] VAR16, input [4:0] VAR18, output [31:0] VAR14, output [3:0] VAR15);
wire [31:0] VAR7;
wire [ 3:0] VAR4;
VAR5 #(.VAR1(8), .VAR17(3)) VAR13
(.VAR16({24'h0, VAR16}), .sel(sel[2:0]), .VAR20(VAR7[7:0]));
VAR5 #(.VAR1(8), .VAR17(3)) VAR19
(.VAR16({24'h0, VAR16}), .s... | apache-2.0 |
danbone/core | riscv_core_ex.v | 2,563 | module MODULE1 (
input clk,
input VAR31,
input [31:0] VAR5,
input [31:0] VAR34,
input [9:0] VAR10,
input VAR36,
input [31:0] VAR29,
input VAR28,
input [31:0] VAR17,
output VAR15
);
localparam VAR4 = 10'b0000000000;
localparam VAR21 = 10'b0000000001;
localparam VAR35 = 10'b0000000010;
localparam VAR1 = 10'b0000000100;
l... | mit |
jtillma3/fpga_tutorial | projects/project1/src/mojo_top.v | 1,471 | module MODULE1(
input clk,
input VAR1,
input VAR12,
output[7:0]VAR5,
output VAR11,
input VAR4,
input VAR8,
input VAR3,
output [3:0] VAR13,
input VAR7, output VAR2, input VAR6 );
wire rst = ~VAR1; wire [9:0] VAR10;
assign VAR11 = 1'VAR14; assign VAR2 = 1'VAR14;
assign VAR13 = 4'VAR9;
assign VAR5[6:0] = 7'b0; assign VAR5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221o/sky130_fd_sc_hs__a221o.pp.blackbox.v | 1,375 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR7 ,
VAR1 ,
VAR5 ,
VAR4 ,
VAR2,
VAR6
);
output VAR8 ;
input VAR3 ;
input VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR2;
input VAR6;
endmodule | apache-2.0 |
cafe-alpha/wascafe | v11/fpga_firmware/wasca/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v | 36,494 | module MODULE1 (
VAR163,
VAR32,
VAR107,
VAR82,
VAR46,
VAR102,
VAR78,
VAR72,
VAR79,
VAR69,
VAR60,
VAR24,
VAR123,
VAR137,
VAR65,
VAR87,
VAR100,
VAR41,
VAR62,
VAR146,
VAR158,
VAR97,
VAR10,
VAR119,
VAR54,
VAR140,
VAR66
);
parameter VAR108 = 0;
parameter VAR143 = 0;
parameter VAR49 = 32;
parameter VAR96 = 20;
parameter VAR1... | gpl-2.0 |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter.v | 6,149 | module MODULE1 #(
parameter VAR10 = 18,
parameter VAR22 = 0,
parameter VAR21 = 18,
parameter VAR7 = 0,
parameter VAR3 = 0,
parameter VAR17 = 0,
parameter VAR11 = 1,
parameter VAR9 = 1,
parameter VAR16 = 0,
parameter VAR12 = 18,
parameter VAR2 = 0,
parameter VAR4 = 1,
parameter VAR25 = 0,
parameter VAR24 = 1,
parameter ... | gpl-2.0 |
asicguy/gplgpu | hdl/de_temp/de_top_misc.v | 7,651 | module MODULE1
( input VAR26,
input VAR15,
input VAR58,
input VAR48,
input [1:0] VAR6,
input VAR32,
input VAR41,
input VAR7,
input [4:0] VAR11,
input VAR12,
input VAR59,
input VAR24,
input VAR46,
input VAR20,
input VAR9,
input VAR39,
input VAR49,
input VAR2,
input [23:0] VAR38,
input VAR3,
input VAR57,
input VAR30,
out... | gpl-3.0 |
cafe-alpha/wascafe | v11/fpga_firmware/wasca/synthesis/submodules/altera_up_rs232_in_deserializer.v | 6,083 | module MODULE1 (
clk,
reset,
VAR19,
VAR5,
VAR22,
VAR31,
VAR15
);
parameter VAR26 = 9; parameter VAR20 = 433;
parameter VAR11 = 216;
parameter VAR17 = 11; parameter VAR10 = 9;
input clk;
input reset;
input VAR19;
input VAR5;
output reg [ 7: 0] VAR22;
output VAR31;
output [VAR10: 0] VAR15;
wire VAR3;
wire VAR29;
wire VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41ai/sky130_fd_sc_ms__o41ai.behavioral.v | 1,571 | module MODULE1 (
VAR12 ,
VAR7,
VAR1,
VAR14,
VAR2,
VAR8
);
output VAR12 ;
input VAR7;
input VAR1;
input VAR14;
input VAR2;
input VAR8;
supply1 VAR6;
supply0 VAR10;
supply1 VAR9 ;
supply0 VAR13 ;
wire VAR15 ;
wire VAR4;
or VAR11 (VAR15 , VAR2, VAR14, VAR1, VAR7 );
nand VAR5 (VAR4, VAR8, VAR15 );
buf VAR3 (VAR12 , VAR4 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpio_ovtv2/sky130_fd_io__top_gpio_ovtv2.blackbox.v | 3,111 | module MODULE1 (
VAR4 ,
VAR16 ,
VAR40 ,
VAR2 ,
VAR39 ,
VAR17 ,
VAR22 ,
VAR21,
VAR32 ,
VAR29 ,
VAR28 ,
VAR13 ,
VAR3 ,
VAR8 ,
VAR33 ,
VAR5 ,
VAR9 ,
VAR34 ,
VAR37 ,
VAR19 ,
VAR11 ,
VAR20 ,
VAR18 ,
VAR14 ,
VAR12 ,
VAR27 ,
VAR15 ,
VAR7 ,
VAR36 ,
VAR10
);
input VAR4 ;
input VAR16 ;
input VAR40 ;
input VAR2 ;
input VAR39 ;
in... | apache-2.0 |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/Loop_loop_height_fYi.v | 2,034 | module MODULE1 (
VAR7, VAR1, VAR6, VAR4, VAR11, VAR2, VAR9, VAR10, VAR12, clk);
parameter VAR13 = 8;
parameter VAR5 = 8;
parameter VAR8 = 256;
input[VAR5-1:0] VAR7;
input VAR1;
output reg[VAR13-1:0] VAR6;
input[VAR5-1:0] VAR4;
input VAR11;
output reg[VAR13-1:0] VAR2;
input[VAR5-1:0] VAR9;
input VAR10;
output reg[VAR13-... | mit |
alexforencich/xfcp | lib/eth/example/DE5-Net/fpga/rtl/si570_i2c_init.v | 15,822 | module MODULE1 (
input wire clk,
input wire rst,
output wire [6:0] VAR9,
output wire VAR11,
output wire VAR10,
output wire VAR6,
output wire VAR2,
output wire VAR14,
output wire VAR16,
input wire VAR4,
output wire [7:0] VAR13,
output wire VAR7,
input wire VAR3,
output wire VAR12,
output wire VAR15,
input wire VAR8
);
l... | mit |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_THRESHA.v | 2,226 | module MODULE1 (
address,
VAR2,
clk,
VAR5,
VAR8,
VAR3,
VAR6,
VAR4
)
;
output [ 6: 0] VAR6;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input VAR2;
input clk;
input VAR5;
input VAR8;
input [ 31: 0] VAR3;
wire VAR9;
reg [ 6: 0] VAR1;
wire [ 6: 0] VAR6;
wire [ 6: 0] VAR7;
wire [ 31: 0] VAR4;
assign VAR9 = 1;
assign VAR7 ... | gpl-2.0 |
Bjay1435/capstone | Geoff/Geoff.ip_user_files/ip/blk_mem_gen_0/blk_mem_gen_0_stub.v | 1,334 | module MODULE1(VAR4, VAR3, VAR5, VAR6, VAR1, VAR2)
;
input VAR4;
input VAR3;
input [0:0]VAR5;
input [18:0]VAR6;
input [12:0]VAR1;
output [12:0]VAR2;
endmodule | mit |
kyzhai/NUNY | src/hardware/stage1_bb.v | 4,992 | module MODULE1 (
address,
VAR2,
VAR1);
input [11:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_1.behavioral.v | 1,188 | module MODULE1( VAR5, VAR6, VAR2 );
input VAR2, VAR5;
output VAR6;
VAR3 VAR4(.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2));
VAR3 VAR1(.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2)); | apache-2.0 |
ridecore/ridecore | src/fpga/prioenc.v | 1,638 | module MODULE2 #(
parameter VAR4 = 4,
parameter VAR3 = 2
)
(
input wire [VAR4-1:0] in,
output reg [VAR3-1:0] out,
output reg en
);
integer VAR8;
always @ begin
out = 0;
for (VAR8 = 0 ; VAR8 < VAR4 ; VAR8 = VAR8+1) begin
out[VAR8] = (VAR16 < VAR8) ? 1'b0 : 1'b1;
end
end
endmodule
module MODULE1 #(
parameter VAR4 = 4,
pa... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4/sky130_fd_sc_ms__or4_1.v | 2,231 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR1 ,
VAR10 ,
VAR6 ,
VAR11,
VAR4,
VAR5 ,
VAR8
);
output VAR7 ;
input VAR9 ;
input VAR1 ;
input VAR10 ;
input VAR6 ;
input VAR11;
input VAR4;
input VAR5 ;
input VAR8 ;
VAR2 VAR3 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR5(VAR5),
.... | apache-2.0 |
MeshSr/onetswitch30 | ons30-app52-ref_ofshw/vivado/onets_7030_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/qos_wrr.v | 16,612 | module MODULE1
parameter VAR68 = 64,
parameter VAR82=VAR68/8,
parameter VAR61=2
)
(
input [VAR68-1:0] VAR60,
input [VAR82-1:0] VAR54,
output VAR44,
input VAR10,
input clk,
input reset,
output reg [VAR68-1:0] VAR70,
output reg [VAR82-1:0] VAR12,
input VAR98,
output reg VAR19,
input [5:0]VAR88,
input [5:0]VAR80,
input [5... | lgpl-2.1 |
olajep/oh | src/adi/hdl/library/util_cdc/sync_data.v | 2,824 | module MODULE1 #(
parameter VAR7 = 1,
parameter VAR13 = 1
) (
input VAR15,
input [VAR7-1:0] VAR17,
input VAR12,
output reg [VAR7-1:0] VAR10
);
generate
if (VAR13 == 1) begin
wire VAR2;
wire VAR8;
reg VAR1 = 1'b0;
reg VAR11 = 1'b0;
reg [VAR7-1:0] VAR5;
VAR14 VAR16 (
.in(VAR11),
.VAR12(VAR12),
.VAR6(1'b1),
.out(VAR2)
);
... | mit |
julioamerico/OpenCRC | src/SoC/component/work/crc_ahb_ip/crc_ahb_ip.v | 26,702 | module MODULE1(
VAR227,
VAR325,
VAR305
);
input VAR227;
input VAR325;
output VAR305;
wire [31:0] VAR404;
wire [2:0] VAR411;
wire VAR121;
wire [3:0] VAR396;
wire [31:0] VAR135;
wire VAR90;
wire VAR321;
wire VAR71;
wire [2:0] VAR156;
wire [1:0] VAR74;
wire [31:0] VAR39;
wire VAR75;
wire VAR343;
wire VAR260;
wire VAR173;
... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_100.v | 1,614 | module MODULE2 (
VAR10,
VAR3
);
input [31:0] VAR10;
output [31:0]
VAR3;
wire [31:0]
VAR2,
VAR6,
VAR1,
VAR14,
VAR5,
VAR8,
VAR7,
VAR12,
VAR16,
VAR15,
VAR9;
assign VAR2 = VAR10;
assign VAR7 = VAR8 << 6;
assign VAR16 = VAR12 << 2;
assign VAR15 = VAR12 + VAR16;
assign VAR14 = VAR2 << 4;
assign VAR8 = VAR2 + VAR14;
assign VA... | mit |
jameshegarty/rigel | platform/axi/ict106_axilite_conv.v | 5,024 | module MODULE1 #
(
parameter integer VAR9 = 12,
parameter integer VAR57 = 32,
parameter integer VAR19 = 32 )
(
input wire VAR18,
input wire VAR16,
input wire [VAR9-1:0] VAR13,
input wire [VAR57-1:0] VAR25,
input wire VAR43,
output wire VAR2,
input wire [VAR19-1:0] VAR10,
input wire [VAR19/8-1:0] VAR26,
input wire VAR3,... | mit |
hoangt/NOCulator | hring/hw/buffered/src/vcr_top.v | 31,851 | module MODULE1
(clk, reset, VAR203, VAR177, VAR96,
VAR94, VAR82, VAR206, VAR76,
VAR132);
parameter VAR52 = 8;
parameter VAR188 = 4;
parameter VAR62 = 2;
parameter VAR173 = 2;
localparam VAR12 = VAR62 * VAR173;
parameter VAR142 = 1;
localparam VAR65 = VAR12 * VAR142;
localparam VAR119 = VAR22(VAR65);
parameter VAR183 = ... | mit |
TalentlessAlpaca/Automated_Vacuum_Cleaner | I2C/top_tst.v | 1,774 | module MODULE1;
reg clk;
reg VAR1;
reg rst;
reg en;
reg VAR12;
reg VAR3;
reg VAR10;
reg VAR17;
reg [7:0] VAR16;
wire VAR14;
wire VAR15;
wire [7:0] VAR5;
wire VAR2;
wire VAR11;
reg VAR9, VAR13, VAR8;
assign VAR11 = VAR8? 1'VAR7 : VAR13;
VAR4 VAR6 (
.clk(clk),
.VAR1(VAR1),
.rst(rst),
.en(en),
.VAR12(VAR12),
.VAR3(VAR3),
... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Generate_Position_And_Voltage_Ramp.v | 4,257 | module MODULE1
(
VAR23,
reset,
VAR18,
VAR4,
VAR15,
VAR11,
VAR17,
VAR14,
VAR6
);
input VAR23;
input reset;
input VAR18;
input VAR4;
input signed [17:0] VAR15; input signed [17:0] VAR11; input signed [17:0] VAR17; output signed [17:0] VAR14; output signed [17:0] VAR6;
wire signed [31:0] VAR2; wire signed [17:0] VAR5; wir... | gpl-3.0 |
asicguy/gplgpu | hdl/dlp/dlp_top.v | 14,458 | module MODULE1
)
(
input VAR12, input VAR41, input [8:2] VAR4, input VAR79, input [3:0] VAR55, input VAR71, input [31:0] VAR78, input [3:0] VAR59, input VAR10, input VAR14, input VAR66, input VAR70, input VAR27, input [(VAR34*8)-1:0] VAR65, input VAR9, input VAR83, input [3:0] VAR31,
output [8:2] VAR74, output VAR30, o... | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ILC/interrupt_latency_counter_171/synth/interrupt_latency_counter.v | 12,267 | module MODULE1 #(
parameter VAR16 = 1'b1,
parameter VAR6 = 32'b1,
parameter VAR51 = 6'd32
)(
irq,
VAR5,
clk,
VAR7,
VAR18,
VAR27,
VAR23,
VAR56
);
input wire [VAR51-1:0] irq;
input wire VAR5;
input wire clk;
input wire VAR7;
input wire VAR18;
input wire [5:0] VAR27;
input wire [31:0] VAR23;
output reg [31:0] VAR56;
local... | mit |
olofk/oh | common/hdl/toggle2pulse.v | 1,122 | module MODULE1(
out,
clk, in, reset
);
input clk;
input in;
output out;
input reset;
reg VAR1;
always @ (posedge clk)
if(reset)
VAR1 <= 1'b0;
else
VAR1 <= in;
assign out = in ^ VAR1;
endmodule | gpl-3.0 |
secworks/rosc_entropy | src/rtl/rosc_entropy_core.v | 9,728 | module MODULE1(
input wire clk,
input wire VAR35,
input wire [31 : 0] VAR7,
input wire [31 : 0] VAR6,
input wire [31 : 0] VAR5,
input wire [7 : 0] VAR26,
output wire [31 : 0] VAR44,
output wire [31 : 0] VAR22,
output wire [31 : 0] VAR18,
output wire VAR20,
input wire VAR17,
output wire [7 : 0] VAR41,
input wire VAR45
)... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn_8.v | 2,150 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR1,
VAR6,
VAR5,
VAR3 ,
VAR8
);
output VAR4 ;
input VAR2 ;
input VAR1;
input VAR6;
input VAR5;
input VAR3 ;
input VAR8 ;
VAR9 VAR7 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR4 ,
VAR2 ,
VAR1
);
output VAR4 ;... | apache-2.0 |
everskar2013/PentiumX | Hardware/Code/Vram_B.v | 2,539 | module MODULE1(
VAR12,
VAR15,
VAR21,
VAR19,
VAR17,
VAR11,
VAR5,
VAR16,
clk
);
input wire [31:0] VAR12;
input wire [31:0] VAR15;
input wire VAR21;
input wire VAR19;
output reg [31:0] VAR17 = 0;
output VAR11;
input wire [10:0] VAR5;
output wire [31:0] VAR16;
input clk;
reg [10:0] VAR6;
wire VAR8;
reg [31:0] VAR4;
wire [3... | mit |
DougFirErickson/parallella-hw | fpga/old/hdl/elink-gold/axi_elink_if.v | 12,141 | module MODULE1 (
VAR79, VAR30, VAR96, VAR48,
VAR25, VAR49, VAR58,
VAR99, VAR47, VAR83,
VAR46, VAR72, VAR37,
VAR23, VAR53, VAR18,
VAR12, VAR80, VAR5,
VAR87, VAR44, VAR90,
VAR8, VAR74, VAR100,
VAR14, VAR92, VAR41,
VAR2, VAR34, VAR38,
VAR97, VAR32, reset, VAR40, VAR21,
VAR43, VAR69, VAR52,
VAR101, VAR56, VAR70,
VAR59, VAR... | gpl-3.0 |
Progressive-Learning-Platform/progressive-learning-platform | reference/hw/verilog/mod_switches.v | 1,439 | module MODULE1(rst, clk, VAR5, VAR3, VAR1, VAR9, VAR7, din, VAR2, dout, VAR6);
input rst;
input clk;
input VAR5,VAR3;
input [31:0] VAR1, VAR9;
input [1:0] VAR7;
input [31:0] din;
output [31:0] VAR2, dout;
input [7:0] VAR6;
wire [31:0] VAR8, VAR4;
assign VAR2 = VAR8;
assign dout = VAR4;
assign VAR8 = 32'h00000000;
assig... | gpl-3.0 |
dawsonjon/fpu | double_adder/file_writer.v | 1,228 | module MODULE1(VAR7,VAR3,clk,rst,VAR6);
integer VAR2;
integer VAR4;
input clk;
input rst;
input [63:0] VAR7;
input VAR3;
output VAR6;
reg VAR5;
reg state;
reg [63:0] VAR1;
begin
begin
begin
begin | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1.behavioral.v | 8,998 | module MODULE1( VAR35, VAR36, VAR47, VAR18, VAR74 );
input VAR35, VAR36, VAR18, VAR47;
output VAR74;
reg VAR33;
VAR31 VAR13(.VAR35(VAR35),.VAR36(VAR36),.VAR47(VAR47),.VAR18(VAR18),.VAR74(VAR74),.VAR33(VAR33));
VAR31 VAR16(.VAR35(VAR35),.VAR36(VAR36),.VAR47(VAR47),.VAR18(VAR18),.VAR74(VAR74),.VAR33(VAR33));
not VAR39(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor3/sky130_fd_sc_lp__xor3.pp.blackbox.v | 1,322 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR3 ,
VAR8 ,
VAR7,
VAR1,
VAR5 ,
VAR2
);
output VAR4 ;
input VAR6 ;
input VAR3 ;
input VAR8 ;
input VAR7;
input VAR1;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/ddr2/ddr2_usr_rd.v | 11,805 | module MODULE1 #
(
parameter VAR1 = 8,
parameter VAR71 = 9,
parameter VAR63 = 144,
parameter VAR28 = 72,
parameter VAR29 = 0
)
(
input VAR47,
input VAR22,
input [(VAR71*VAR1)-1:0] VAR42,
input [(VAR71*VAR1)-1:0] VAR45,
input [VAR71-1:0] VAR20,
input [VAR71-1:0] VAR11,
output reg [1:0] VAR24,
output VAR26,
output reg [(... | mit |
juan199/Lab_Digitales | exp2/MiniAlu.v | 4,842 | module MODULE1
(
input wire VAR26,
input wire VAR25,
output wire [7:0] VAR49
);
wire [15:0] VAR57,VAR30,VAR41;
wire [7:0] VAR38;
reg VAR23,VAR17;
wire [27:0] VAR60;
wire [3:0] VAR28;
reg signed [32:0] VAR33;
wire [7:0] VAR46,VAR32,VAR56;
wire signed [15:0] VAR52,VAR8,VAR20;
wire [15:0] VAR15;
wire [15:0] VAR9;
VAR10 VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22a/sky130_fd_sc_hd__o22a_1.v | 2,339 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR4 ,
VAR1 ,
VAR10 ,
VAR2,
VAR8,
VAR9 ,
VAR5
);
output VAR11 ;
input VAR3 ;
input VAR4 ;
input VAR1 ;
input VAR10 ;
input VAR2;
input VAR8;
input VAR9 ;
input VAR5 ;
VAR7 VAR6 (
.VAR11(VAR11),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(VAR9),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311ai/sky130_fd_sc_hd__o311ai.blackbox.v | 1,381 | module MODULE1 (
VAR3 ,
VAR9,
VAR8,
VAR10,
VAR7,
VAR4
);
output VAR3 ;
input VAR9;
input VAR8;
input VAR10;
input VAR7;
input VAR4;
supply1 VAR5;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
chaohu/Daily-Learning | Verilog/lab5/lab5_1/lab5_2_1/lab5_2_1.srcs/sources_1/new/lab5_2_1.v | 3,353 | module MODULE1(
input [1:0] VAR2,
input clk,reset,
output reg VAR5
);
reg [2:0] state,VAR3;
parameter VAR1 = 0,VAR4 = 1,VAR9 = 2,VAR8 = 3,VAR6 = 4,VAR10 = 5,VAR7 = 6;
always @(posedge clk or posedge reset)
if(reset)
begin
state <= VAR1;
VAR5 <= 0;
end
else
state <= VAR3;
always @(state)
begin
case(state)
VAR1:VAR5 = VA... | mit |
CatherineH/QubitekkCC | CC1/src/DE0Nano/verilog/chan_mux.v | 3,893 | module MODULE1 (
VAR17,
VAR6,
VAR5,
sel,
VAR19);
input [21:0] VAR17;
input [21:0] VAR6;
input [21:0] VAR5;
input [1:0] sel;
output [21:0] VAR19;
wire [21:0] VAR2;
wire [21:0] VAR9 = VAR5[21:0];
wire [21:0] VAR3 = VAR6[21:0];
wire [21:0] VAR19 = VAR2[21:0];
wire [21:0] VAR11 = VAR17[21:0];
wire [65:0] VAR18 = {VAR9, VAR... | mit |
hcabrera-/lancetfish | RTL/router/rtl/link_controller.v | 6,698 | module MODULE1 #(
parameter VAR20 = VAR23,
parameter VAR16 = 2,
parameter VAR7 = 2,
parameter VAR4 = 2,
parameter VAR31 = 2
)
(
input wire clk,
input wire reset,
input wire VAR9,
input wire VAR13,
input wire VAR29,
input wire VAR2,
input wire [VAR19-1:0] VAR1,
input wire [VAR19-1:0] VAR25,
input wire [VAR19-1:0] VAR14,... | gpl-3.0 |
ncos/Xilinx-Verilog | SINGEN/src/SPI/spi.v | 2,560 | module MODULE1#
(
parameter integer VAR27 = 15, parameter integer VAR34 = 100 )
(
output reg [127:0] VAR15 = " ",
output reg [127:0] VAR36 = " ",
output reg [127:0] VAR12 = " ",
output reg [127:0] VAR40 = " ",
input wire VAR41,
input wire VAR43,
input wire [7:0] VAR23,
input wire VAR29,
input wire VAR20,
output wire VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4b/sky130_fd_sc_lp__nor4b_lp.v | 2,310 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR6 ,
VAR3 ,
VAR4 ,
VAR1,
VAR11,
VAR10 ,
VAR8
);
output VAR5 ;
input VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR4 ;
input VAR1;
input VAR11;
input VAR10 ;
input VAR8 ;
VAR2 VAR9 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR10(VAR10),
.... | apache-2.0 |
SymbiFlow/fpga-tool-perf | third_party/picosoc_wrappers/picosoc_noflash.v | 6,003 | module MODULE1 (
input clk,
input VAR15,
output VAR33,
input VAR12,
output [ 3:0] VAR42,
output [31:0] VAR53,
output [31:0] VAR65,
input [31:0] VAR20,
input VAR25,
input VAR37,
input VAR52,
output VAR46,
input VAR21
);
parameter integer VAR32 = 256;
parameter [31:0] VAR47 = (4*VAR32); parameter [31:0] VAR17 = 32'VAR28 ... | isc |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/RAMB16_S4_altera.v | 7,739 | module MODULE1 (
address,
VAR41,
VAR50,
VAR38,
VAR4,
VAR40);
input [11:0] address;
input VAR41;
input VAR50;
input [3:0] VAR38;
input VAR4;
output [3:0] VAR40;
parameter VAR27 = "";
tri1 VAR41;
tri1 VAR50;
wire [3:0] VAR5;
wire [3:0] VAR40 = VAR5[3:0];
VAR29 VAR39 (
.VAR17 (address),
.VAR26 (VAR50),
.VAR1 (VAR38),
.VAR... | mit |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_axi_basic_top.v | 10,984 | module MODULE1 #(
parameter VAR55 = 128, parameter VAR53 = "VAR31", parameter VAR19 = "VAR54", parameter VAR24 = "VAR54", parameter VAR38 = 1,
parameter VAR16 = (VAR55 == 128) ? 2 : 1, parameter VAR2 = VAR55 / 8 ) (
input [VAR55-1:0] VAR12, input VAR50, output VAR40, input [VAR2-1:0] VAR59, input VAR20, input [3:0] VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ebufn/sky130_fd_sc_ls__ebufn.pp.symbol.v | 1,327 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR4,
input VAR5 ,
input VAR3,
input VAR7,
input VAR2
);
endmodule | apache-2.0 |
tanelikaivola/blinkenlichten | fpga/pixel_bit_counter.v | 1,049 | module MODULE1(
input VAR1,
input VAR5,
output reg [7:0] VAR2 = 0,
output reg [7:0] VAR8 = 0,
output reg [7:0] VAR7 = 0,
output reg VAR6
);
parameter VAR9 = 256;
parameter VAR4 = 24;
parameter VAR3 = 64;
always @(posedge VAR1) begin
if(VAR5) begin
VAR8 <= 0;
VAR2 <= 0;
VAR7 <= 0;
VAR6 <= 0;
end else
if(VAR7+1 == VAR3) ... | mit |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/ram_controller_alt_mem_ddrx_controller_top.v | 41,588 | module MODULE1(
clk,
VAR326,
VAR407,
VAR218,
VAR133,
VAR302,
VAR154,
VAR28,
VAR85,
VAR329,
VAR367,
VAR161,
VAR305,
VAR345,
VAR6,
VAR111,
VAR296,
VAR300,
VAR219,
VAR51,
VAR240,
VAR84,
VAR382,
VAR356,
VAR146,
VAR134,
VAR124,
VAR403,
VAR205,
VAR153,
VAR192,
VAR164,
VAR18,
VAR401,
VAR180,
VAR285,
VAR376,
VAR396,
VAR53,
VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211o/sky130_fd_sc_hdll__a211o.functional.pp.v | 2,052 | module MODULE1 (
VAR11 ,
VAR1 ,
VAR6 ,
VAR8 ,
VAR2 ,
VAR9,
VAR12,
VAR7 ,
VAR5
);
output VAR11 ;
input VAR1 ;
input VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR9;
input VAR12;
input VAR7 ;
input VAR5 ;
wire VAR14 ;
wire VAR13 ;
wire VAR10;
and VAR16 (VAR14 , VAR1, VAR6 );
or VAR15 (VAR13 , VAR14, VAR2, VAR8 );
VAR3 VAR17 ... | apache-2.0 |
Canaan-Creative/MM | verilog/xilinx/clkgen.v | 3,124 | module MODULE1(input wire VAR37, input wire VAR5, output wire VAR41, output wire [3:0] VAR27, output wire VAR19);
wire VAR24 ;
VAR13 VAR40 (
.VAR22 (VAR27[0]), .VAR31(VAR24), .VAR42(~VAR24), .VAR34(VAR5), .VAR33(0), .VAR3(1), .VAR11 (0), .VAR29 (0) );
VAR13 VAR8 (
.VAR22 (VAR27[1]), .VAR31(VAR24), .VAR42(~VAR24), .VAR3... | unlicense |
Fabeltranm/FPGA-Game-D1 | HW/RTL/10KEYBOARD/Version_01/02 verilog/Touch/MódulosBásicos/teclado/psdos.v | 1,351 | module MODULE1 ( input VAR3,
input VAR7,
output reg VAR8,
output [7:0] VAR10,
output reg VAR2
);
reg [8:0] VAR5;
reg [7:0] VAR6;
reg [3:0] VAR4;
reg [3:0] VAR1;
reg VAR9;
begin
begin
begin
begin
begin
begin
begin
end
begin | gpl-3.0 |
pavel-demin/red-pitaya-notes | cores/axi_bram_writer_v1_0/axi_bram_writer.v | 5,018 | module MODULE1 #
(
parameter integer VAR33 = 32,
parameter integer VAR32 = 16,
parameter integer VAR4 = 32,
parameter integer VAR44 = 10
)
(
input wire VAR42,
input wire VAR31,
input wire [VAR32-1:0] VAR37, input wire VAR5, output wire VAR10, input wire [VAR33-1:0] VAR39, input wire [VAR33/8-1:0] VAR27, input wire VAR2... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_serdes_clk.v | 4,919 | module MODULE1 (
VAR22,
VAR34,
VAR8,
clk,
VAR31,
VAR26,
VAR24,
VAR1,
VAR28,
VAR9,
VAR25,
VAR39,
VAR18,
VAR11);
parameter VAR12 = 1;
parameter VAR36 = 1;
parameter VAR27 = 0;
parameter VAR35 = 1.667;
parameter VAR3 = 6;
parameter VAR10 = 12.000;
parameter VAR7 = 2.000;
parameter VAR14 = 6;
input VAR22;
input VAR34;
inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi.behavioral.pp.v | 2,245 | module MODULE1 (
VAR1 ,
VAR9,
VAR6,
VAR2 ,
VAR12 ,
VAR3,
VAR5,
VAR4 ,
VAR13
);
output VAR1 ;
input VAR9;
input VAR6;
input VAR2 ;
input VAR12 ;
input VAR3;
input VAR5;
input VAR4 ;
input VAR13 ;
wire VAR16 ;
wire VAR14 ;
wire VAR10 ;
wire VAR7;
and VAR15 (VAR16 , VAR2, VAR12 );
nor VAR18 (VAR14 , VAR9, VAR6 );
nor VAR1... | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_axi_basic_top.v | 11,012 | module MODULE1 #(
parameter VAR29 = 128, parameter VAR20 = "VAR48", parameter VAR43 = "VAR55", parameter VAR42 = "VAR55", parameter VAR49 = 1,
parameter VAR47 = (VAR29 == 128) ? 2 : 1, parameter VAR50 = VAR29 / 8 ) (
input [VAR29-1:0] VAR46, input VAR28, output VAR15, input [VAR50-1:0] VAR23, input VAR10, input [3:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_mux_2to1_n/sky130_fd_sc_lp__udp_mux_2to1_n.blackbox.v | 1,236 | module MODULE1 (
VAR1 ,
VAR2,
VAR4,
VAR3
);
output VAR1 ;
input VAR2;
input VAR4;
input VAR3 ;
endmodule | apache-2.0 |
neale/CS-program | 474-VLSI/Lab_5/brightness_clk_2hz_bb.v | 11,329 | module MODULE1 (
VAR3,
VAR1,
VAR2,
VAR4);
input VAR3;
input VAR1;
output VAR2;
output VAR4;
tri0 VAR3;
endmodule | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_2.v | 2,477 | module MODULE1 (
VAR4 ,
VAR8,
VAR6,
VAR1 ,
VAR7 ,
VAR10,
VAR5,
VAR2 ,
VAR9
);
output VAR4 ;
input VAR8;
input VAR6;
input VAR1 ;
input VAR7 ;
input VAR10;
input VAR5;
input VAR2 ;
input VAR9 ;
VAR11 VAR3 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VA... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/Select_AB.v | 1,099 | module MODULE1
(
VAR2,
VAR6,
VAR5,
VAR1,
VAR7
);
input VAR2;
input VAR6;
input VAR5;
output VAR1;
output VAR7;
wire VAR4;
wire VAR3;
assign VAR4 = (VAR2 == 1'b0 ? VAR5 :
VAR6);
assign VAR1 = VAR4;
assign VAR3 = (VAR2 == 1'b0 ? VAR6 :
VAR5);
assign VAR7 = VAR3;
endmodule | gpl-3.0 |
niketancm/tsea26 | lab2-3/rtl/dsp_system_top.v | 3,763 | module MODULE1;
wire clk;
wire reset;
wire [15:0] VAR55;
wire VAR60;
wire [15:0] VAR32;
wire [7:0] VAR12;
wire VAR11;
wire [15:0] VAR46;
wire [31:0] VAR31;
wire [15:0] VAR26;
wire [15:0] VAR65;
wire [15:0] VAR52;
wire VAR70;
wire [15:0] VAR25;
wire [15:0] VAR23;
wire [15:0] VAR8;
wire VAR37;
VAR54 VAR53(
.VAR36 (clk)
)... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1.behavioral.pp.v | 1,768 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR4,
VAR6
);
output VAR9 ;
input VAR2 ;
input VAR4;
input VAR6;
wire VAR10 ;
wire VAR7;
not VAR3 (VAR10 , VAR2 );
VAR8 VAR5 (VAR7, VAR10, VAR4, VAR6);
buf VAR1 (VAR9 , VAR7 );
endmodule | apache-2.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/altera_avalon_st_jtag_interface.v | 7,782 | module MODULE1 #(
parameter VAR20 = 0, parameter VAR5 = 0,
parameter VAR70 = 0,
parameter VAR18 = -1,
parameter VAR59 = 0,
parameter VAR25 = 0, parameter VAR68 = 50000 ) (
input wire VAR19,
input wire VAR63,
input wire VAR32,
output wire VAR65,
input wire VAR44,
input wire VAR33,
input wire VAR69,
input wire VAR23,
inp... | epl-1.0 |
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