repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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olajep/oh | src/axi/dv/axislave_stub.v | 2,883 | module MODULE1 (
VAR9, VAR39, VAR21, VAR1, VAR7,
VAR26, VAR29, VAR20, VAR32, VAR25,
VAR14,
VAR38, VAR8, VAR24, VAR22, VAR23,
VAR12, VAR34, VAR17, VAR6,
VAR2, VAR4, VAR31, VAR10, VAR35,
VAR15, VAR36, VAR40, VAR11,
VAR13, VAR18, VAR19, VAR5,
VAR30, VAR41, VAR27, VAR33, VAR16,
VAR28, VAR37
);
parameter VAR3 = 12;
input VA... | mit |
lvd2/zxevo | fpga/baseconf/trunk/z80/zint.v | 1,710 | module MODULE1
(
input wire VAR2,
input wire VAR7,
input wire VAR5,
input wire VAR1,
input wire VAR3,
input wire VAR4,
input wire VAR8,
output reg VAR9
);
wire VAR6;
reg [9:0] VAR10;
reg [1:0] wr;
begin
begin
end
begin
end | gpl-3.0 |
aj-michael/Digital-Systems | Pong/Phase2/UniversalCounter10bitsV5.v | 1,057 | module MODULE1(VAR6,VAR5, VAR9, VAR10,VAR2,VAR8,VAR3, VAR1, VAR7) ;
parameter VAR11 = 10;
input VAR2, VAR8, VAR1, VAR7;
input [VAR11-1:0] VAR6, VAR5, VAR9;
output reg [VAR11-1:0] VAR10;
output reg VAR3; reg [VAR11-1:0] VAR4;
always @ (posedge VAR7 or posedge VAR1)
if(VAR1==1) VAR10 <= VAR5;
else VAR10<=VAR4;
always@(VA... | mit |
asciilifeform/Stierlitz | ml501/infer-sram.v | 2,569 | module MODULE1
VAR5=8,
VAR8=8,
VAR4=1024)
(input clk,
input [VAR5-1:0] address,
input VAR10,
input VAR1,
inout [VAR8-1:0] VAR7
);
reg [VAR8-1:0] VAR2 [0:VAR4-1];
wire [VAR8-1:0] VAR9;
reg [VAR5-1:0] VAR6;
always @(posedge clk)
if (VAR10) VAR2[address] <= VAR7 + 1;
always @(posedge clk)
if (VAR1) VAR6 <= address;
assign... | gpl-3.0 |
dcsun88/ntpserver-fpga | sv/ip/ocxo_clk_pll/ocxo_clk_pll_clk_wiz.v | 6,391 | module MODULE1
( input VAR65,
output VAR76,
input VAR69,
output VAR15
);
VAR57 VAR18
(.VAR48 (VAR59),
.VAR4 (VAR65));
wire [15:0] VAR53;
wire VAR73;
wire VAR70;
wire VAR43;
wire VAR75;
wire VAR33;
wire VAR24;
wire VAR28;
wire VAR51;
wire VAR62;
wire VAR11;
wire VAR19;
wire VAR64;
wire VAR54;
wire VAR72;
wire VAR27;
wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4/sky130_fd_sc_lp__or4.functional.pp.v | 1,828 | module MODULE1 (
VAR15 ,
VAR1 ,
VAR11 ,
VAR5 ,
VAR10 ,
VAR13,
VAR7,
VAR14 ,
VAR8
);
output VAR15 ;
input VAR1 ;
input VAR11 ;
input VAR5 ;
input VAR10 ;
input VAR13;
input VAR7;
input VAR14 ;
input VAR8 ;
wire VAR12 ;
wire VAR4;
or VAR3 (VAR12 , VAR10, VAR5, VAR11, VAR1 );
VAR6 VAR2 (VAR4, VAR12, VAR13, VAR7);
buf VAR9... | apache-2.0 |
ak-fau/fpga-cyclone_iv | bemicro/bemicro.v | 7,018 | module MODULE1
(
input wire VAR141, input wire VAR111, input wire VAR18, input wire VAR21, input wire VAR14, input wire VAR142, input wire VAR115,
output wire VAR83,
input wire VAR47,
inout wire VAR39,
inout wire VAR97,
inout wire VAR7,
inout wire VAR106,
inout wire VAR20,
inout wire VAR101,
inout wire VAR103,
inout wi... | bsd-2-clause |
DatanoiseTV/Parallax-Propeller-P8X32A-FPGA | P8X32A_Emulation/P8X32A_DE0_Nano/cog_ctr.v | 3,068 | module MODULE1
(
input VAR13,
input VAR7,
input VAR15,
input VAR12,
input VAR6,
input VAR3,
input [31:0] VAR11,
input [31:0] VAR2,
output reg [32:0] VAR4,
output [31:0] VAR16,
output VAR1
);
reg [31:0] VAR17;
reg [31:0] VAR5;
always @(posedge VAR13 or negedge VAR15)
if (!VAR15)
VAR17 <= 32'b0;
else if (VAR12)
VAR17 <= ... | gpl-3.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_pcie_bram_7x.v | 8,927 | module MODULE1
parameter [3:0] VAR12 = 4'h1, parameter [5:0] VAR8 = 6'h08, parameter VAR28 = "VAR14", parameter VAR27 = 0, parameter VAR11 = 0 )
(
input VAR21, input VAR22,
input VAR15, input [12:0] VAR2, input [VAR11 - 1:0] VAR10,
input VAR26, input VAR18, input [12:0] VAR6,
output [VAR11 - 1:0] VAR25 );
localparam VA... | mit |
olgirard/openmsp430 | core/synthesis/actel/src/omsp_dbg.v | 30,034 | module MODULE1 (
VAR49, VAR138, VAR5, VAR192, VAR81, VAR3, VAR90, VAR107, VAR70,
VAR116, VAR168, VAR142, VAR178, VAR143, VAR67, VAR69, VAR28, VAR59, VAR82, VAR13, VAR50, VAR128, VAR179, VAR1, VAR126, VAR114 );
output VAR49; output VAR138; output [15:0] VAR5; output [15:0] VAR192; output VAR81; output [1:0] VAR3; output... | bsd-3-clause |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/Loop_loop_height_pro.v | 30,648 | module MODULE1 (
VAR65,
VAR15,
VAR69,
VAR133,
VAR89,
VAR45,
VAR108,
VAR13,
VAR81,
VAR109,
VAR29,
VAR37,
VAR31,
VAR16,
VAR94,
VAR52,
VAR19,
VAR100,
VAR71,
VAR96,
VAR140,
VAR35,
VAR3,
VAR7,
VAR26,
VAR114,
VAR149,
VAR70,
VAR59,
VAR73,
VAR56,
VAR64,
VAR53,
VAR76
);
parameter VAR22 = 5'd1;
parameter VAR130 = 5'd2;
parameter... | mit |
MeshSr/onetswitch20 | ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/data_fifo.v | 2,674 | module MODULE1
parameter VAR4 = 256,
parameter VAR8 = 8
)
(
input [VAR5-1:0] din, input VAR13,
input VAR9,
output reg [VAR5-1:0] dout, output VAR3,
output VAR6,
output VAR10,
output VAR1,
output [5:0] VAR12,
input reset,
input clk
);
reg [VAR5-1:0] VAR14 [256 : 0];
reg [7 : 0] VAR2;
reg [7 : 0] VAR11;
reg [7 : 0] VAR7;... | lgpl-2.1 |
hydai/Verilog-Practice | HardwareLab/Lab8/KEYBOARD.v | 2,768 | module MODULE1 (VAR4, VAR2, VAR9, VAR8, reset, VAR1, clk);
input clk, VAR1;
input reset;
input [3:0] VAR8;
output [3:0] VAR4;
output [3:0] VAR2;
output VAR9;
reg [3:0] VAR4;
reg [3:0] VAR5;
reg [3:0] VAR6;
reg [4:0] VAR3;
reg [3:0] VAR2;
reg VAR7;
wire VAR9;
always @(posedge clk or negedge reset)
begin
if (!reset)
VAR6... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/acl_fp_sqrt_s5_double.v | 120,362 | module MODULE1
(
VAR69,
VAR174,
VAR203,
VAR222,
VAR12) ;
input VAR69;
input VAR174;
input VAR203;
input [54:0] VAR222;
output [53:0] VAR12;
tri0 VAR69;
tri1 VAR174;
tri0 VAR203;
reg [1:0] VAR59;
reg [51:0] VAR262;
reg [51:0] VAR273;
reg [51:0] VAR246;
reg [51:0] VAR129;
reg [51:0] VAR164;
reg [51:0] VAR167;
reg [51:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22a/sky130_fd_sc_hd__o22a.pp.blackbox.v | 1,385 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR2 ,
VAR9 ,
VAR7 ,
VAR6,
VAR3,
VAR8 ,
VAR5
);
output VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR9 ;
input VAR7 ;
input VAR6;
input VAR3;
input VAR8 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd/sky130_fd_sc_hdll__tapvgnd.behavioral.pp.v | 1,238 | module MODULE1 (
VAR1,
VAR2,
VAR4 ,
VAR3
);
input VAR1;
input VAR2;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
lloves/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/non_posted_pkt_slicer.v | 14,346 | module MODULE1(
input clk,
input rst,
input VAR31,
input VAR18,
input [31:0] VAR8,
input [31:0] VAR36,
input [63:0] VAR5,
input [2:0] VAR42, input VAR7,
input [63:0] VAR17,
output reg VAR46,
input ack,
output reg VAR21,
output reg [31:0] VAR2,
output reg [63:0] VAR16,
output [9:0] VAR37
);
localparam VAR4 = 4'h0;
local... | bsd-2-clause |
neilstockbridge/cores | UART/hello/UART.v | 2,806 | function [10:0] VAR5;
input [7:0] VAR14;
VAR5 = {2'b11, VAR14, 1'b0};
endfunction
module MODULE1 (
clk,
reset, VAR3, VAR10, VAR4, );
input clk;
input reset;
output VAR3;
input [7:0] VAR10;
input VAR4;
parameter VAR9 = 0;
parameter VAR6 = 1;
parameter VAR12 = 12*1000*1000;
parameter VAR1 = 9600;
parameter VAR2 = VAR12 /... | mit |
masc-ucsc/cmpe220fall16 | rtl/pfmonitor.v | 2,532 | module MODULE1(
input clk
,input reset
,input VAR19 VAR8
,input VAR25
,output VAR23
,output VAR1 VAR28
,output VAR13
,input VAR17
,input VAR10 VAR26
,input VAR4
,output VAR22
);
logic VAR24;
logic VAR2;
VAR19 VAR12;
VAR14 #(.VAR20(VAR27(VAR19))) VAR6 (
.clk (clk),
.reset (reset),
.din (VAR8),
.VAR3 (VAR25),
.VAR7 (VAR2... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_freeze.v | 8,297 | module MODULE1(
clk, rst,
VAR7, VAR18, VAR20, VAR13, VAR19,
VAR21, VAR5, VAR17,
VAR4, VAR2,
VAR9, VAR10, VAR1, VAR16, VAR6,
VAR11, VAR3
);
input clk;
input rst;
input [VAR14-1:0] VAR7;
input VAR18;
input VAR20;
input VAR13;
input VAR19;
input VAR21;
input VAR4;
input VAR2;
input VAR5;
input VAR17;
output VAR9;
output V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3/sky130_fd_sc_hd__or3_1.v | 2,153 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR9 ,
VAR2 ,
VAR3,
VAR5,
VAR6 ,
VAR8
);
output VAR4 ;
input VAR7 ;
input VAR9 ;
input VAR2 ;
input VAR3;
input VAR5;
input VAR6 ;
input VAR8 ;
VAR10 VAR1 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/ddr2_phy_alt_mem_phy_seq_wrapper.v | 20,002 | module MODULE1 (
VAR163,
VAR142,
VAR56,
VAR127,
VAR92,
VAR3,
VAR151,
VAR156,
VAR16,
VAR4,
VAR96,
VAR170,
VAR139,
VAR49,
VAR32,
VAR40,
VAR91,
VAR25,
VAR135,
VAR181,
VAR37,
VAR124,
VAR38,
VAR122,
VAR27,
VAR94,
VAR19,
VAR13,
VAR55,
VAR66,
VAR126,
VAR114,
VAR73,
VAR140,
VAR145,
VAR152,
VAR9,
VAR169,
VAR10,
VAR45,
VAR57,
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtn/sky130_fd_sc_ls__dlxtn_1.v | 2,204 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR5,
VAR4 ,
VAR1 ,
VAR3 ,
VAR7
);
output VAR2 ;
input VAR9 ;
input VAR5;
input VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR7 ;
VAR8 VAR6 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR2 ,
VAR9 ,
VAR5
);
output VA... | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/minimig_bankmapper.v | 5,106 | module MODULE1
(
input VAR3, input VAR10, input VAR8, input VAR12, input VAR5, input VAR6, input VAR14, input VAR9, input VAR13, input VAR2, input VAR7, input VAR1, input [3:0] VAR4, output reg [7:0] VAR11 );
always @(*)
begin
case ({VAR7,VAR4})
5'b00000 : VAR11 = { VAR9, VAR13, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, VAR12 | VA... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_sstl_bscan.v | 3,105 | module MODULE1(VAR4 ,VAR15 ,VAR5 ,VAR27 ,
VAR23 ,VAR35 ,VAR17 ,VAR2 ,VAR29 ,VAR36 ,VAR3 ,VAR9 ,
VAR30 ,VAR13 ,VAR26 );
output VAR15 ;
output VAR27 ;
output VAR17 ;
output VAR2 ;
output VAR29 ;
input VAR4 ;
input VAR5 ;
input VAR23 ;
input VAR35 ;
input VAR36 ;
input VAR3 ;
input VAR9 ;
input VAR30 ;
input VAR13 ;
input... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfstp/sky130_fd_sc_hvl__sdfstp.behavioral.pp.v | 2,904 | module MODULE1 (
VAR13 ,
VAR5 ,
VAR21 ,
VAR18 ,
VAR10 ,
VAR29,
VAR7 ,
VAR23 ,
VAR1 ,
VAR3
);
output VAR13 ;
input VAR5 ;
input VAR21 ;
input VAR18 ;
input VAR10 ;
input VAR29;
input VAR7 ;
input VAR23 ;
input VAR1 ;
input VAR3 ;
wire VAR20 ;
wire VAR12 ;
wire VAR28 ;
reg VAR19 ;
wire VAR22 ;
wire VAR15 ;
wire VAR6 ;
wi... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_1.functional.pp.v | 3,028 | module MODULE1( VAR23, VAR14, VAR10, VAR2, VAR3, VAR13, VAR20, VAR5, VAR21 );
input VAR20, VAR13, VAR10, VAR3, VAR14, VAR23;
inout VAR5, VAR21;
output VAR2;
wire VAR19;
not VAR28( VAR19, VAR20 );
wire VAR4;
not VAR17( VAR4, VAR10 );
wire VAR12;
not VAR36( VAR12, VAR14 );
wire VAR7;
and VAR18( VAR7, VAR19, VAR4, VAR12 )... | apache-2.0 |
xuwenyihust/MapReduce_NoC | RTL/mapreduce.v | 5,630 | module MODULE1(clk, rst, VAR10);
parameter VAR18=36;
parameter VAR6=8;
parameter VAR48=4;
parameter VAR65=5;
parameter VAR16=5;
input clk;
input rst;
input VAR10;
wire [VAR18-1:0] VAR46;
wire [VAR18-1:0] VAR80;
wire [VAR18-1:0] VAR4;
wire [VAR18-1:0] VAR50;
reg [1:0] VAR56;
reg [1:0] VAR9;
reg [1:0] VAR7;
reg [1:0] VAR... | mit |
mbuesch/pyprofibus | phy_fpga/sync_signal_mod.v | 1,479 | module MODULE1(
input clk,
input in,
output out,
output VAR1,
output VAR3,
);
reg [2:0] VAR2; | gpl-2.0 |
skyfex/svo-raycaster | raycaster2/matrix_mul.v | 8,751 | module MODULE1
(
input clk,
input VAR2,
input VAR47,
input VAR38,
input VAR68,
input signed [31:0] VAR23,
input signed [31:0] VAR69,
input signed [31:0] VAR17,
input signed [31:0] VAR64,
input signed [31:0] VAR80,
input signed [31:0] VAR57,
input signed [31:0] VAR11,
input signed [31:0] VAR14,
input signed [31:0] VAR12... | mit |
hoglet67/CoPro6502 | src/Tube/ph_reg3.v | 7,642 | module MODULE2 #
(
parameter VAR42 = 0, parameter VAR29 = 0 )
(
input clk,
input rst,
input VAR19,
output reg [VAR42-1:0] VAR32,
output reg [VAR42-1:0] VAR41
);
wire [VAR42-1:0] VAR12 = VAR32 + 1'b1;
wire [VAR42-1:0] VAR40 = VAR12 ^ (VAR12 >> 1);
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR32 <= VAR29;... | gpl-3.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/arbiter_for_OUT_req.v | 4,760 | module MODULE1( clk,
rst,
VAR14,
VAR2,
VAR3,
VAR9,
VAR4,
VAR13,
VAR11,
VAR16,
VAR12,
VAR7,
VAR5,
select
);
input clk;
input rst;
input VAR14;
input VAR2;
input VAR3;
input VAR9;
input [1:0] VAR4;
input [1:0] VAR13;
input [1:0] VAR11;
output VAR16;
output VAR12;
output VAR7;
output VAR5;
output [2:0] select; parameter V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp.behavioral.v | 1,377 | module MODULE1 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR5;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR9 ;
wire VAR2;
not VAR7 (VAR2, VAR1 );
buf VAR8 (VAR6 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_p_pp_sn/sky130_fd_sc_hs__udp_dlatch_p_pp_sn.symbol.v | 1,409 | module MODULE1 (
input VAR4 ,
output VAR3 ,
input VAR2 ,
input VAR5 ,
input VAR1
);
endmodule | apache-2.0 |
lvd2/ngs | fpga/obsolete/fpgaF_dma2/dma/dma_sd.v | 16,239 | module MODULE2(
input wire clk,
input wire VAR63,
output reg VAR64,
input wire VAR61,
input wire [7:0] VAR34,
output wire [7:0] VAR33,
output reg VAR68,
input wire [7:0] din, output reg [7:0] dout,
input wire VAR57, input wire VAR38, input wire [1:0] VAR39,
output reg [20:0] VAR17,
output wire [7:0] VAR22, input wire [... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_v1_00_a/hdl/verilog/cf_ddsx.v | 12,744 | module MODULE1 (
VAR65,
VAR15,
VAR46,
VAR74,
VAR20,
VAR43,
VAR48,
VAR16,
VAR32,
VAR28,
VAR27,
VAR69,
VAR33,
VAR64,
VAR62);
input VAR65;
output [13:0] VAR15;
output [13:0] VAR46;
output [13:0] VAR74;
output [13:0] VAR20;
output [13:0] VAR43;
output [13:0] VAR48;
output [13:0] VAR16;
output [13:0] VAR32;
output [13:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211a/sky130_fd_sc_lp__o211a_m.v | 2,345 | module MODULE2 (
VAR7 ,
VAR1 ,
VAR6 ,
VAR8 ,
VAR2 ,
VAR3,
VAR11,
VAR9 ,
VAR5
);
output VAR7 ;
input VAR1 ;
input VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR3;
input VAR11;
input VAR9 ;
input VAR5 ;
VAR10 VAR4 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR... | apache-2.0 |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/sfa_2x2_v1_0/sfa_switch.v | 5,466 | module MODULE1(
output wire VAR25 ,
input wire VAR40 ,
input wire [31 : 0] VAR58 ,
output wire VAR1 ,
input wire VAR22 ,
input wire [31 : 0] VAR16 ,
output wire VAR32 ,
input wire VAR44 ,
input wire [31 : 0] VAR5 ,
output wire VAR42 ,
input wire VAR10 ,
input wire [31 : 0] VAR49 ,
input wire VAR6 ,
output wire VAR19 ,
... | bsd-3-clause |
nyaxt/dmix | nkmd/arch/nkmd_arch.v | 2,404 | module MODULE1 #(
parameter VAR23 = 16*8
)(
input wire clk,
input wire rst,
input wire VAR18,
output wire VAR42,
input wire [23:0] VAR4,
input wire VAR10,
output wire [23:0] VAR44,
input wire VAR9,
output wire VAR24,
input wire [31:0] VAR1,
input wire [31:0] VAR56,
input wire VAR36,
output wire [(VAR23-1):0] VAR41,
inp... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_16.behavioral.v | 1,185 | module MODULE1( VAR2, VAR5, VAR6 );
input VAR2, VAR5;
output VAR6;
VAR3 VAR1(.VAR2(VAR2),.VAR5(VAR5),.VAR6(VAR6));
VAR3 VAR4(.VAR2(VAR2),.VAR5(VAR5),.VAR6(VAR6)); | apache-2.0 |
sh-chris110/chris | FPGA/chris.bak/Qsys/soc_design/synthesis/submodules/altera_up_rs232_in_deserializer.v | 6,083 | module MODULE1 (
clk,
reset,
VAR15,
VAR3,
VAR24,
VAR32,
VAR28
);
parameter VAR21 = 9; parameter VAR20 = 433;
parameter VAR27 = 216;
parameter VAR4 = 11; parameter VAR22 = 9;
input clk;
input reset;
input VAR15;
input VAR3;
output reg [ 7: 0] VAR24;
output VAR32;
output [VAR22: 0] VAR28;
wire VAR25;
wire VAR17;
wire VAR... | gpl-2.0 |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/arduino_io_switch_1.0/src/arduino_switch_digital_13_2_top.v | 14,510 | module MODULE1(
input [15:0] VAR22, input [15:0] VAR27, input [15:0] VAR5, input [11:0] VAR26, output [11:0] VAR18, output [11:0] VAR2, output [11:0] VAR20, input [11:0] VAR23, input [11:0] VAR17, output VAR15,
input VAR8,
input VAR25,
output VAR32,
input VAR37,
input VAR19,
output VAR41,
input VAR31,
input VAR9,
outpu... | bsd-3-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/yacc/pipelined_rfile.v | 10,331 | module MODULE1(VAR111,VAR79,
VAR60,VAR4,VAR50, VAR15,VAR121,
VAR104,VAR130,VAR131,VAR110,VAR35,VAR42,
VAR101,VAR88,VAR34,VAR144,VAR139,VAR53,
VAR99,VAR26,VAR55,VAR119,VAR129,
VAR94,VAR86,VAR71
);
parameter VAR23="VAR87";
input [11:0] VAR131;
input [25:0] VAR131;
input [15:0] VAR110; input [4:0] VAR60;
input [4:0] VAR4;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22oi/sky130_fd_sc_lp__a22oi_4.v | 2,352 | module MODULE2 (
VAR11 ,
VAR8 ,
VAR6 ,
VAR5 ,
VAR10 ,
VAR3,
VAR2,
VAR9 ,
VAR4
);
output VAR11 ;
input VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR10 ;
input VAR3;
input VAR2;
input VAR9 ;
input VAR4 ;
VAR7 VAR1 (
.VAR11(VAR11),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbn/sky130_fd_sc_ms__sdfbbn.functional.pp.v | 2,700 | module MODULE1 (
VAR17 ,
VAR20 ,
VAR6 ,
VAR11 ,
VAR4 ,
VAR1 ,
VAR12 ,
VAR8,
VAR23 ,
VAR22 ,
VAR27 ,
VAR19
);
output VAR17 ;
output VAR20 ;
input VAR6 ;
input VAR11 ;
input VAR4 ;
input VAR1 ;
input VAR12 ;
input VAR8;
input VAR23 ;
input VAR22 ;
input VAR27 ;
input VAR19 ;
wire VAR24 ;
wire VAR3 ;
wire VAR16 ;
wire VAR... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/ddr_ctrl_ip_phy_alt_mem_phy_seq_wrapper.v | 19,963 | module MODULE1 (
VAR134,
VAR36,
VAR109,
VAR172,
VAR142,
VAR106,
VAR8,
VAR176,
VAR11,
VAR17,
VAR149,
VAR87,
VAR67,
VAR112,
VAR82,
VAR34,
VAR62,
VAR139,
VAR146,
VAR127,
VAR104,
VAR156,
VAR180,
VAR130,
VAR122,
VAR4,
VAR105,
VAR42,
VAR99,
VAR10,
VAR133,
VAR24,
VAR31,
VAR117,
VAR88,
VAR75,
VAR55,
VAR118,
VAR9,
VAR53,
VAR147... | gpl-2.0 |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v | 9,139 | module MODULE1 #
(
parameter VAR71 = "VAR16",
parameter integer VAR43 = 1,
parameter integer VAR32 = 32,
parameter integer VAR22 = 32,
parameter integer VAR62 = 1,
parameter integer VAR47 = 1,
parameter integer VAR28 = 1,
parameter integer VAR12 = 1
)
(
input wire VAR46,
input wire VAR9,
input wire [VAR43-1:0] VAR38,
i... | mit |
fbalakirev/red-pitaya-notes | cores/axis_keyer_v1_0/axis_keyer.v | 2,519 | module MODULE1 #
(
parameter integer VAR12 = 32,
parameter integer VAR10 = 32,
parameter integer VAR3 = 10
)
(
input wire VAR4,
input wire VAR1,
input wire [VAR3-1:0] VAR2,
input wire VAR14,
input wire VAR17,
output wire [VAR12-1:0] VAR20,
output wire VAR11,
output wire VAR13,
output wire VAR6,
output wire [VAR3-1:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21a/sky130_fd_sc_ms__o21a.blackbox.v | 1,326 | module MODULE1 (
VAR5 ,
VAR1,
VAR4,
VAR7
);
output VAR5 ;
input VAR1;
input VAR4;
input VAR7;
supply1 VAR3;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
everskar2013/PentiumX | Hardware/Code/VGA_IO.v | 5,550 | module MODULE1(
VAR12,
rst,
VAR8,
VAR20,
VAR14,
VAR21,
VAR39,
VAR33,
VAR30,
VAR26,
VAR28,
VAR38,
VAR10
);
input VAR12, rst, VAR21, VAR20;
input [10: 0] VAR8;
input [12: 0] VAR14;
output wire [ 2: 0] VAR39;
output wire [ 2: 0] VAR33;
output wire [ 1: 0] VAR30;
output reg VAR26;
output reg VAR28;
output [10: 0] VAR38;
ou... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_profiler.v | 4,435 | module MODULE1
(
VAR9,
VAR10,
enable,
VAR5,
VAR13,
VAR17,
VAR12
);
parameter VAR6=64;
parameter VAR2=32;
parameter VAR7=4;
parameter VAR16=VAR2 * VAR7;
input VAR9;
input VAR10;
input enable;
input VAR5;
input [VAR7-1:0] VAR13;
input [VAR16-1:0] VAR17;
output VAR12;
wire [VAR7-2:0] VAR11;
wire [31:0] VAR3 [0:VAR7-1];
ge... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_4.behavioral.pp.v | 1,333 | module MODULE1( VAR5, VAR3, VAR7, VAR4, VAR2, VAR9 );
input VAR4, VAR5, VAR3;
inout VAR2, VAR9;
output VAR7;
VAR6 VAR8(.VAR5(VAR5),.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4),.VAR2(VAR2),.VAR9(VAR9));
VAR6 VAR1(.VAR5(VAR5),.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4),.VAR2(VAR2),.VAR9(VAR9)); | apache-2.0 |
asicguy/gplgpu | hdl/crt_sp/dc_contr.v | 16,252 | module MODULE1
(
input VAR13,
input VAR39,
input VAR34,
input VAR37,
input VAR2,
input VAR8,
input VAR40,
input [3:0] VAR26,
input [11:0] VAR61,
input [9:0] VAR57,
input VAR50,
input [9:0] VAR29, input [9:0] VAR4, input [9:0] VAR3, input [9:0] VAR5, input [1:0] VAR14,
input VAR41, input VAR45,
input VAR62,
input [9:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221ai/sky130_fd_sc_hd__o221ai_1.v | 2,457 | module MODULE1 (
VAR12 ,
VAR8 ,
VAR10 ,
VAR5 ,
VAR3 ,
VAR11 ,
VAR2,
VAR7,
VAR9 ,
VAR6
);
output VAR12 ;
input VAR8 ;
input VAR10 ;
input VAR5 ;
input VAR3 ;
input VAR11 ;
input VAR2;
input VAR7;
input VAR9 ;
input VAR6 ;
VAR4 VAR1 (
.VAR12(VAR12),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR11(VAR11),
.VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_4.behavioral.pp.v | 8,324 | module MODULE1( VAR1, VAR2, VAR4, VAR9, VAR3, VAR7, VAR10, VAR12, VAR11 );
input VAR10, VAR7, VAR1, VAR4, VAR2, VAR3;
inout VAR12, VAR11;
output VAR9;
VAR5 VAR8(.VAR1(VAR1),.VAR2(VAR2),.VAR4(VAR4),.VAR9(VAR9),.VAR3(VAR3),.VAR7(VAR7),.VAR10(VAR10),.VAR12(VAR12),.VAR11(VAR11));
VAR5 VAR6(.VAR1(VAR1),.VAR2(VAR2),.VAR4(VAR... | apache-2.0 |
jhol/butterflylogic | rtl/data_align.v | 4,632 | module MODULE1 #(
parameter integer VAR7 = 32, parameter integer VAR3 = VAR7/8 )(
input wire clk,
input wire rst,
input wire [3:0] VAR6,
input wire VAR2,
input wire [31:0] VAR1,
output reg VAR4,
output reg [31:0] VAR5
);
reg [1:0] VAR10;
reg [1:0] VAR9;
reg VAR8;
always @ (posedge clk)
begin
case (VAR10[1:0])
2'h3 : VA... | gpl-2.0 |
khldragon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/completion_timeout.v | 5,176 | module MODULE1(
input clk,
input rst,
input [31:0] VAR11,
output reg VAR16
);
reg [15:0] VAR28;
reg [17:0] VAR28; VAR31
wire [31:0] VAR20;
wire [31:0] VAR17;
reg [31:0] VAR10 = 0;
reg [4:0] VAR25[31:0];
wire [31:0] VAR22;
wire [31:0] VAR30;
reg [31:0] VAR27;
wire VAR9;
wire VAR29;
reg VAR15;
always@(posedge clk)begin
i... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2/sky130_fd_sc_hs__and2.behavioral.pp.v | 1,681 | module MODULE1 (
VAR2,
VAR1,
VAR4 ,
VAR7 ,
VAR11
);
input VAR2;
input VAR1;
output VAR4 ;
input VAR7 ;
input VAR11 ;
wire VAR8 ;
wire VAR9;
and VAR5 (VAR8 , VAR7, VAR11 );
VAR10 VAR3 (VAR9, VAR8, VAR2, VAR1);
buf VAR6 (VAR4 , VAR9 );
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/manage_md/command_parse.v | 25,744 | module MODULE1(
clk,
VAR31, VAR93, VAR76,
VAR46,
VAR101, VAR5,
VAR77,
VAR27, VAR95, VAR84, VAR92,
VAR26, VAR28, VAR98,
VAR94, VAR58, VAR62,
VAR97, VAR72,
VAR66,
VAR11, VAR10,
VAR50
);
input clk;
input VAR31;
output VAR27; output VAR95; output VAR84; output[31:0] VAR92;
input VAR26; input VAR28; input VAR98;
input [31:0... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311oi/sky130_fd_sc_hs__a311oi.functional.v | 1,968 | module MODULE1 (
VAR4,
VAR12,
VAR9 ,
VAR8 ,
VAR16 ,
VAR14 ,
VAR11 ,
VAR13
);
input VAR4;
input VAR12;
output VAR9 ;
input VAR8 ;
input VAR16 ;
input VAR14 ;
input VAR11 ;
input VAR13 ;
wire VAR11 VAR5 ;
wire VAR2 ;
wire VAR7;
and VAR1 (VAR5 , VAR14, VAR8, VAR16 );
nor VAR10 (VAR2 , VAR5, VAR11, VAR13 );
VAR15 VAR3 (VAR... | apache-2.0 |
johngtimms/parallel-accumulator | accumulator_memory.v | 4,706 | module MODULE1 (clk, reset, VAR13, VAR1, read, write, VAR16, VAR3, VAR8, VAR10, state);
input clk, reset, VAR16;
input [1:0] VAR13;
input [31:0] write;
output [31:0] read;
output [31:0] VAR10;
output VAR1, VAR3, state;
output [9:0] VAR8;
reg [31:0] VAR5 [0:1023];
reg [9:0] VAR7;
reg [4:0] state;
reg VAR1;
reg [31:0] re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a.functional.v | 1,570 | module MODULE1 (
VAR5 ,
VAR2,
VAR8,
VAR1 ,
VAR12
);
output VAR5 ;
input VAR2;
input VAR8;
input VAR1 ;
input VAR12 ;
wire VAR10 ;
wire VAR11 ;
wire VAR7;
nand VAR9 (VAR10 , VAR8, VAR2 );
or VAR4 (VAR11 , VAR12, VAR1 );
and VAR6 (VAR7, VAR10, VAR11);
buf VAR3 (VAR5 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3b/sky130_fd_sc_lp__or3b.symbol.v | 1,301 | module MODULE1 (
input VAR8 ,
input VAR2 ,
input VAR3,
output VAR1
);
supply1 VAR4;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.v | 2,154 | module MODULE1 (
VAR9,
VAR6,
VAR2 ,
VAR3,
VAR4,
VAR7 ,
VAR8
);
output VAR9;
input VAR6;
input VAR2 ;
input VAR3;
input VAR4;
input VAR7 ;
input VAR8 ;
VAR5 VAR1 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR9,
VAR6,
VAR2
);
output VAR9;
inpu... | apache-2.0 |
kierdavis/site | static/download/cordic.v | 5,844 | module MODULE1(
VAR20,
VAR18, reset, VAR24, VAR35, VAR26, VAR53 );
input VAR18;
input reset;
input VAR24;
input [31:0] VAR35;
output [31:0] VAR26;
output [31:0] VAR53;
wire [31:0] VAR26 = VAR6;
wire [31:0] VAR53 = VAR15;
reg [31:0] VAR6;
reg [31:0] VAR15;
reg [31:0] VAR20;
reg [4:0] VAR30;
reg state;
reg [31:0] VAR33;
... | mit |
peteasa/oh | src/common/hdl/oh_clockmux.v | 1,040 | module MODULE1 #(parameter VAR5 = 1) (
input [VAR5-1:0] en, input [VAR5-1:0] VAR1, output VAR3
);
localparam VAR6 = VAR7;
generate
if(VAR6)
begin : VAR2
VAR4 #(.VAR5(VAR5)) VAR4 (.VAR1(VAR1[VAR5-1:0]),
.en(en[VAR5-1:0]),
.VAR3(VAR3));
end
else
begin : VAR2
assign VAR3 = |(VAR1[VAR5-1:0] & en[VAR5-1:0]);
end
endgenerate... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41oi/sky130_fd_sc_hs__a41oi.behavioral.v | 1,964 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR4 ,
VAR14 ,
VAR9 ,
VAR1 ,
VAR16,
VAR11
);
output VAR5 ;
input VAR10 ;
input VAR4 ;
input VAR14 ;
input VAR9 ;
input VAR1 ;
input VAR16;
input VAR11;
wire VAR9 VAR15 ;
wire VAR8 ;
wire VAR13;
and VAR7 (VAR15 , VAR10, VAR4, VAR14, VAR9 );
nor VAR2 (VAR8 , VAR1, VAR15 );
VAR6 VAR3 (VAR13... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_1.behavioral.v | 1,108 | module MODULE1( VAR3, VAR5 );
input VAR3;
output VAR5;
VAR4 VAR1(.VAR3(VAR3),.VAR5(VAR5));
VAR4 VAR2(.VAR3(VAR3),.VAR5(VAR5)); | apache-2.0 |
ptracton/vscale_soc | rtl/uart16550-1.5.4/bench/verilog/uart_device.v | 22,793 | module MODULE1
(
VAR30,
VAR73,
VAR11,
VAR50,
VAR62,
VAR59,
VAR61,
VAR58
);
input VAR30;
output VAR73;
input VAR11;
output VAR50;
input VAR62;
output VAR59;
output VAR61;
output VAR58;
reg VAR25; reg VAR52; reg VAR47; reg VAR60 = 1'b1;
reg VAR12 = 1'b1;
reg VAR13 = 1'b1;
real VAR57 = 20;
real VAR42 = 0;
integer VAR14 = ... | mit |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/triple_speed_ethernet-library/altera_tse_rgmii_in4.v | 4,192 | module MODULE1 (
VAR3,
VAR4,
VAR13,
VAR9,
VAR2);
input VAR3;
input [3:0] VAR4;
input VAR13;
output [3:0] VAR9;
output [3:0] VAR2;
wire [3:0] VAR18;
wire [3:0] VAR1;
wire [3:0] VAR9 = VAR18[3:0];
wire [3:0] VAR2 = VAR1[3:0];
VAR17 VAR5 (
.VAR4 (VAR4),
.VAR13 (VAR13),
.VAR3 (VAR3),
.VAR9 (VAR18),
.VAR2 (VAR1),
.VAR15 (1'... | apache-2.0 |
anderson1008/NOCulator | hring/hw/bless_mc/rc.v | 1,909 | module MODULE3(
VAR6,
VAR7
);
input [VAR4-1:0] VAR6;
output [VAR2-1:0] VAR7;
VAR11 VAR11(
.VAR6 (VAR6),
.VAR7 (VAR7)
);
endmodule
module MODULE3(
VAR6,
VAR3,
VAR5,
VAR7
);
input [VAR4-1:0] VAR6;
input [VAR13-1:0] VAR3;
input VAR5;
output [VAR2-1:0] VAR7;
wire [VAR2-1:0] VAR1, VAR12;
VAR8 VAR8(
.VAR3 (VAR3),
.VAR7 (VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probe_p/sky130_fd_sc_hvl__probe_p.pp.symbol.v | 1,281 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR1 ,
input VAR4,
input VAR3,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi.blackbox.v | 1,463 | module MODULE1 (
VAR2 ,
VAR9,
VAR3,
VAR1 ,
VAR8
);
output VAR2 ;
input VAR9;
input VAR3;
input VAR1 ;
input VAR8 ;
supply1 VAR5;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
bunnie/novena-afe-hs-fpga | novena-afe-hs.srcs/sources_1/imports/imports/ddr3_eim_cs1.v | 5,547 | module MODULE1(
input wire clk,
input wire [63:0] VAR13,
input wire VAR5, output wire [63:0] VAR29,
input wire VAR11, output wire [63:0] VAR20,
output wire [2:0] VAR7,
output wire [5:0] VAR6,
output wire [29:0] VAR10,
output wire VAR21,
input wire VAR12,
input wire VAR28,
input wire [31:0] VAR3,
input wire [6:0] VAR8,
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32oi/sky130_fd_sc_ls__a32oi.behavioral.pp.v | 2,238 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR4 ,
VAR17 ,
VAR5 ,
VAR19 ,
VAR9,
VAR18,
VAR6 ,
VAR14
);
output VAR1 ;
input VAR2 ;
input VAR4 ;
input VAR17 ;
input VAR5 ;
input VAR19 ;
input VAR9;
input VAR18;
input VAR6 ;
input VAR14 ;
wire VAR11 ;
wire VAR8 ;
wire VAR7 ;
wire VAR16;
nand VAR10 (VAR11 , VAR4, VAR2, VAR17 );
nand VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbn/sky130_fd_sc_hd__dlxbn.behavioral.pp.v | 2,141 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR15 ,
VAR8,
VAR9 ,
VAR13 ,
VAR18 ,
VAR3
);
output VAR5 ;
output VAR1 ;
input VAR15 ;
input VAR8;
input VAR9 ;
input VAR13 ;
input VAR18 ;
input VAR3 ;
wire VAR4 ;
wire VAR7 ;
wire VAR19;
wire VAR2 ;
reg VAR17 ;
wire VAR10 ;
wire 1 ;
not VAR14 (VAR4 , VAR19 );
VAR12 VAR6 (VAR7 , VAR2, VA... | apache-2.0 |
efabless/openlane | designs/salsa20/src/salsa20.v | 69,874 | module MODULE1(
input wire [31 : 0] VAR383,
input wire [31 : 0] VAR394,
input wire [31 : 0] VAR261,
input wire [31 : 0] VAR204,
output wire [31 : 0] VAR25,
output wire [31 : 0] VAR61,
output wire [31 : 0] VAR354,
output wire [31 : 0] VAR285
);
reg [31 : 0] VAR253;
reg [31 : 0] VAR160;
reg [31 : 0] VAR267;
reg [31 : 0] ... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/pre_i/fetch8x8.v | 2,880 | module MODULE1(
clk,
VAR11,
enable,
addr,
VAR2,
VAR9,
VAR14,
VAR12,
VAR4,
VAR8,
VAR6,
VAR1,
VAR3,
VAR7,
VAR13,
VAR5
);
input clk;
input VAR11;
input enable;
output [31:0] VAR2;
output VAR4;
output [3:0] addr;
output [5:0] VAR9;
output [6:0] VAR14;
input VAR12;
output VAR8 ;
output VAR6 ;
output [1:0] VAR1 ;
output [3:0... | gpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/float_mega/float_div/float_div.v | 39,267 | module MODULE1
(
VAR5,
VAR39,
VAR164,
VAR73,
VAR63,
VAR25,
VAR75,
VAR98) ;
input VAR5;
input VAR39;
input VAR164;
input [31:0] VAR73;
input [31:0] VAR63;
output VAR25;
output VAR75;
output [31:0] VAR98;
tri0 VAR5;
tri1 VAR39;
wire [8:0] VAR44;
reg VAR117;
reg VAR21;
reg VAR128;
reg VAR55;
reg VAR89;
reg VAR129;
reg VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_refgen_new/sky130_fd_io__top_refgen_new.symbol.v | 2,340 | module MODULE1 (
input VAR20 ,
inout VAR18 ,
inout VAR6 ,
input VAR10 ,
input VAR23,
input VAR15 ,
input VAR21 ,
input [2:0] VAR26 ,
input [1:0] VAR14 ,
input VAR8 ,
input VAR13 ,
inout VAR17 ,
output VAR5 ,
inout VAR3 ,
input VAR12 ,
output VAR25 ,
inout VAR24
);
supply1 VAR11 ;
supply1 VAR1 ;
supply1 VAR19 ;
supply1 ... | apache-2.0 |
ultraembedded/altor32 | rtl/cpu/altor32_fetch.v | 7,029 | module MODULE1
(
input VAR13 ,
input VAR32 ,
output VAR25 ,
output reg [31:0] VAR34 ,
input [31:0] VAR30 ,
input VAR11,
input VAR3 ,
input [31:0] VAR7 ,
input VAR24 ,
output [31:0] VAR4 ,
output [31:0] VAR1 ,
output VAR28 ,
output [4:0] VAR10 ,
output [4:0] VAR20 ,
output [4:0] VAR22
);
parameter VAR23 = 32'h00000000;
... | lgpl-3.0 |
bluespec/Flute | src_bsc_lib_RTL/RegFileLoad.v | 4,211 | module MODULE1(VAR8,
VAR6, VAR3, VAR9,
VAR10, VAR2,
VAR17, VAR13,
VAR5, VAR7,
VAR15, VAR1,
VAR11, VAR19
);
parameter VAR14 = "";
parameter VAR18 = 1;
parameter VAR12 = 1;
parameter VAR4 = 0;
parameter VAR20 = 1;
parameter VAR21 = 0;
input VAR8;
input [VAR18 - 1 : 0] VAR6;
input [VAR12 - 1 : 0] VAR3;
input VAR9;
input [... | apache-2.0 |
Ribeiro/sd2snes | verilog/sd2snes_obc1/address.v | 3,753 | module MODULE1(
input VAR8,
input [7:0] VAR1, input [2:0] VAR19, input [23:0] VAR15, input [7:0] VAR20, output [23:0] VAR16, output VAR2, output VAR10, output VAR17, output VAR12, input [23:0] VAR11,
input [23:0] VAR7,
output VAR3,
output VAR21,
output VAR9,
output VAR4
);
parameter [2:0]
VAR14 = 3,
VAR18 = 4,
VAR6 = 5... | gpl-2.0 |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T29-tristate/dividerp1.v | 1,264 | module MODULE1(input wire clk,
output wire VAR1);
parameter VAR3 = VAR2;
localparam VAR5 = VAR4(VAR3);
reg [VAR5-1:0] VAR6 = 0;
always @(posedge clk)
VAR6 <= (VAR6 == VAR3 - 1) ? 0 : VAR6 + 1;
assign VAR1 = (VAR6 == 0) ? 1 : 0;
endmodule | gpl-2.0 |
alexforencich/verilog-axis | rtl/axis_ram_switch.v | 47,376 | module MODULE1 #
(
parameter VAR42 = 4096,
parameter VAR14 = 32,
parameter VAR11 = 0,
parameter VAR1 = 4,
parameter VAR48 = 4,
parameter VAR65 = 8,
parameter VAR10 = (VAR65>8),
parameter VAR27 = ((VAR65+7)/8),
parameter VAR28 = 8,
parameter VAR49 = (VAR28>8),
parameter VAR9 = ((VAR28+7)/8),
parameter VAR57 = 0,
paramet... | mit |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_gtp_pipe_reset.v | 19,964 | module MODULE1 #
(
parameter VAR12 = "VAR28", parameter VAR26 = 1, parameter VAR35 = 6'd63, parameter VAR34 = 1
)
(
input VAR1,
input VAR10,
input VAR69,
input VAR67,
input [VAR26-1:0] VAR13,
input [VAR26-1:0] VAR31,
input VAR71,
input [VAR26-1:0] VAR49,
input [VAR26-1:0] VAR29,
input VAR40,
input [VAR26-1:0] VAR64,
in... | mit |
lvd2/zxevo | unsupported/solegstar/fpga/current/video/video_top.v | 6,422 | module MODULE1(
input wire clk,
output wire [ 1:0] VAR5,
output wire [ 1:0] VAR20,
output wire [ 1:0] VAR74,
output wire VAR63,
output wire VAR34,
output wire VAR24,
input wire [ 3:0] VAR31,
input wire [ 1:0] VAR8,
input wire [ 2:0] VAR3,
input wire VAR13,
input wire VAR66,
input wire VAR25,
input wire VAR39,
input wir... | gpl-3.0 |
olgirard/openmsp430 | core/rtl/verilog/periph/template_periph_16b.v | 6,894 | module MODULE1 (
VAR23,
VAR36, VAR29, VAR4, VAR32, VAR17, VAR25 );
output [15:0] VAR23;
input VAR36; input [13:0] VAR29; input [15:0] VAR4; input VAR32; input [1:0] VAR17; input VAR25;
parameter [14:0] VAR11 = 15'h0190;
parameter VAR20 = 3;
parameter [VAR20-1:0] VAR28 = 'h0,
VAR27 = 'h2,
VAR3 = 'h4,
VAR30 = 'h6;
parame... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/fill/sky130_fd_sc_hvl__fill_4.v | 1,848 | module MODULE1 (
VAR1,
VAR6,
VAR4 ,
VAR3
);
input VAR1;
input VAR6;
input VAR4 ;
input VAR3 ;
VAR2 VAR5 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 ();
supply1 VAR1;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR3 ;
VAR2 VAR5 ();
endmodule | apache-2.0 |
charcole/NeoGeoHDMI | altera/13.0sp1/altpll_masterclk_bb.v | 13,099 | module MODULE1 (
VAR3,
VAR1,
VAR2,
VAR4);
input VAR3;
output VAR1;
output VAR2;
output VAR4;
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_4.functional.pp.v | 1,290 | module MODULE1( VAR2, VAR1, VAR13, VAR5, VAR7, VAR14 );
input VAR13, VAR2, VAR5;
inout VAR7, VAR14;
output VAR1;
wire VAR15;
not VAR9( VAR15, VAR13 );
wire VAR10;
not VAR4( VAR10, VAR2 );
wire VAR12;
and VAR6( VAR12, VAR15, VAR10 );
wire VAR8;
not VAR3( VAR8, VAR5 );
or VAR11( VAR1, VAR12, VAR8 );
endmodule | apache-2.0 |
GSejas/Karatsuba_FPU | my_sourcefiles/addsub/Tenth_Phase_v2.v | 3,173 | module MODULE1
(
input wire VAR13, input wire VAR18, input wire VAR14, input wire [VAR6-1:0] VAR9, input wire [VAR26-1:0] VAR17, output wire [VAR21-1:0] VAR4 );
wire [VAR26-1:0] VAR5;
wire [VAR6-1:0] VAR11;
wire VAR22;
wire [VAR21-1:0] VAR24;
wire VAR23;
wire [VAR6-1:0] VAR3;
wire [VAR26-1:0] VAR7;
assign VAR23 = VAR13... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fah/sky130_fd_sc_hs__fah.functional.v | 2,485 | module MODULE1 (
VAR12,
VAR13 ,
VAR8 ,
VAR10 ,
VAR14 ,
VAR17,
VAR1
);
output VAR12;
output VAR13 ;
input VAR8 ;
input VAR10 ;
input VAR14 ;
input VAR17;
input VAR1;
wire VAR24 ;
wire VAR22 ;
wire VAR6 ;
wire VAR9 ;
wire VAR20 ;
wire VAR7 ;
wire VAR16;
xor VAR19 (VAR24 , VAR8, VAR10, VAR14 );
VAR2 VAR4 (VAR22 , VAR24, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4bb/sky130_fd_sc_hdll__nand4bb.behavioral.pp.v | 2,020 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR6 ,
VAR2 ,
VAR13 ,
VAR7,
VAR9,
VAR5 ,
VAR3
);
output VAR8 ;
input VAR4 ;
input VAR6 ;
input VAR2 ;
input VAR13 ;
input VAR7;
input VAR9;
input VAR5 ;
input VAR3 ;
wire VAR11 ;
wire VAR17 ;
wire VAR14;
nand VAR10 (VAR11 , VAR13, VAR2 );
or VAR15 (VAR17 , VAR6, VAR4, VAR11 );
VAR1 VAR16 ... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_INVBUF_SLVT_TT_210930.v | 14,942 | module MODULE1 (VAR1, VAR2);
output VAR1;
input VAR2;
buf (VAR1, VAR2); | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s.symbol.v | 1,358 | module MODULE1 (
input VAR4,
output VAR6
);
supply1 VAR5;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
alankarkotwal/lc-3b-processor | lc_3b_processor.v | 23,167 | module MODULE1(clk,reset,VAR121);input clk,reset,VAR121;wire [15:0] VAR13;
wire VAR91, VAR54, VAR55;
wire [4:0] VAR124;
wire VAR35;
wire [1:0] VAR87;
wire [2:0] VAR44;
wire [1:0] VAR89;
wire [1:0] VAR39;
wire [1:0] VAR107;
wire [1:0] VAR74;
wire VAR14;
wire VAR56;
wire VAR23;
wire VAR6;
wire VAR37;
wire [1:0] VAR123;
w... | gpl-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/AddProcess.v | 2,729 | module MODULE1(
input [31:0] VAR2,
input [3:0] VAR8,
input VAR25,
input [35:0] VAR31,
input [35:0] VAR34,
input [31:0] VAR5,
input [7:0] VAR29,
input VAR22,
output reg VAR24,
output reg [31:0] VAR14,
output reg [27:0] VAR17,
output reg [3:0] VAR20,
output reg [31:0] VAR16,
output reg [7:0] VAR11
);
parameter VAR18 = 1'... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41ai/sky130_fd_sc_ms__o41ai.functional.v | 1,475 | module MODULE1 (
VAR7 ,
VAR11,
VAR2,
VAR5,
VAR3,
VAR9
);
output VAR7 ;
input VAR11;
input VAR2;
input VAR5;
input VAR3;
input VAR9;
wire VAR6 ;
wire VAR10;
or VAR8 (VAR6 , VAR3, VAR5, VAR2, VAR11 );
nand VAR1 (VAR10, VAR9, VAR6 );
buf VAR4 (VAR7 , VAR10 );
endmodule | apache-2.0 |
itpcc/FPGA-IA-Journy-game | verilog/enemyPosition (9).v | 5,412 | module MODULE1(
input clk,
input VAR9,
input VAR8,
input wire [7:0] VAR1,
input [3:0] VAR5,
output reg [9:0] VAR12,
output reg [8:0] VAR4
);
parameter VAR11 = 20;
parameter VAR3 = 440;
parameter VAR19 = 220;
parameter VAR18 = 20;
parameter VAR13 = 600;
parameter VAR10 = 300;
parameter VAR15 = 2'b00;
parameter VAR7 = 2'... | mit |
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