repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/sfa_2x2_v1_0/sfa_interconnect.v | 6,037 | module MODULE1(
output wire VAR90 ,
input wire VAR61 ,
input wire [31 : 0] VAR83 ,
output wire VAR15 ,
input wire VAR32 ,
input wire [31 : 0] VAR55 ,
output wire VAR1 ,
input wire VAR70 ,
input wire [31 : 0] VAR76 ,
output wire VAR78 ,
input wire VAR30 ,
input wire [31 : 0] VAR62 ,
input wire VAR45 ,
output wire VAR7 ,... | bsd-3-clause |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b_downsizer.v | 11,689 | module MODULE1 #
(
parameter VAR38 = "none",
parameter integer VAR31 = 4,
parameter integer VAR28 = 0,
parameter integer VAR19 = 1
)
(
input wire VAR10,
input wire VAR33,
input wire VAR37,
input wire VAR27,
input wire [4-1:0] VAR25,
output wire VAR8,
output wire [VAR31-1:0] VAR1,
output wire [2-1:0] VAR32,
output wire ... | gpl-3.0 |
carstenbru/fpga-log | spartanmc/hardware/uart_light/src/spmc_uart_light_peri.v | 8,802 | module MODULE1(
input wire VAR91, input wire [17:0] VAR36, output wire [17:0] VAR9, input wire [9:0] VAR40, input wire VAR21, input wire VAR47,
input wire reset, output wire VAR67, input wire VAR79,
output wire VAR34,
input wire VAR26
);
parameter
VAR24 = 10'h0,
VAR54 = 0,
VAR65 = 1,
VAR7 = 2,
VAR53 = 25000000,
VAR13 =... | gpl-3.0 |
m-labs/fjmem-m1 | fjmem/rtl/fjmem_core.v | 4,769 | module MODULE1 #(
parameter VAR9 = 24,
parameter VAR2 = 4'd6
) (
input VAR3,
input VAR28,
input VAR6,
input VAR18,
input VAR25,
input VAR34,
input VAR13,
output VAR14,
output [VAR9-1:0] VAR23,
inout [15:0] VAR20,
output reg VAR10,
output reg VAR12,
output VAR33
);
parameter VAR32 = 3'b000;
parameter VAR16 = 3'b111;
par... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221a/sky130_fd_sc_hdll__o221a_4.v | 2,460 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR8 ,
VAR4 ,
VAR6 ,
VAR11 ,
VAR10,
VAR3,
VAR1 ,
VAR12
);
output VAR9 ;
input VAR7 ;
input VAR8 ;
input VAR4 ;
input VAR6 ;
input VAR11 ;
input VAR10;
input VAR3;
input VAR1 ;
input VAR12 ;
VAR5 VAR2 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR10(... | apache-2.0 |
kammce/LPCXpresso-Nexys4-Servo-Commander | ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v | 1,995 | module MODULE1(
input wire [10:0] VAR9,
output reg [3:0] VAR1,
output reg [3:0] VAR7,
output reg [3:0] VAR4,
output reg [3:0] VAR5
);
parameter VAR2 = 1000;
parameter VAR3 = 100;
parameter VAR11 = 10;
parameter VAR10 = 1;
reg [10:0] buffer;
integer VAR6;
integer VAR8;
always @ (*)
begin
buffer = VAR9;
VAR1 = 4'd0;
VAR7... | bsd-3-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/triple_speed_ethernet-library/altera_tse_gxb_aligned_rxsync.v | 11,835 | module MODULE1 (
input clk,
input reset,
input [7:0] VAR36,
input VAR1,
input VAR18,
input VAR7,
input VAR3,
input VAR38,
input VAR12,
input VAR25,
input VAR29,
input VAR21,
output reg [7:0] VAR30,
output VAR37,
output reg VAR8,
output reg VAR35,
output reg VAR28,
output reg VAR16,
output reg VAR15,
output reg VAR13) ;... | mit |
fabianz66/cursos-tec | taller-digital/Lab4/lab_pong/Logica_Barra.v | 1,451 | module MODULE1(
input VAR9,
input reset,
input VAR3,
input VAR1,
input VAR6,
input VAR5,
output reg [8:0] VAR8);
parameter VAR7 = 480 - VAR4;
parameter VAR10 = VAR2;
begin
begin
begin
end else
begin
begin
begin
end | mit |
VerticalResearchGroup/miaow | src/verilog/rtl/fpga/fpga_memory.v | 3,237 | module MODULE1
(
VAR15, VAR24,
VAR21, VAR4, VAR28,
VAR30, VAR16, VAR19, VAR18,
clk, rst,
VAR2, VAR11, VAR5,
VAR14, VAR12, VAR23
);
input clk;
input rst;
input VAR15;
input VAR24;
input [31:0] VAR21;
input [31:0] VAR4;
input [6:0] VAR28;
input [31:0] VAR30;
input VAR16;
input VAR19;
input VAR18;
output [31:0] VAR11;
out... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3/sky130_fd_sc_hs__or3.pp.symbol.v | 1,241 | module MODULE1 (
input VAR2 ,
input VAR6 ,
input VAR3 ,
output VAR5 ,
input VAR4,
input VAR1
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/nukeint_mon.v | 7,863 | module MODULE1(
clk, VAR15, VAR19, VAR2, VAR7, VAR4, VAR1, VAR13, VAR3, VAR10, VAR6
);
input clk;
input VAR15;
input [4:0] VAR1;
input [4:0] VAR13;
input [4:0] VAR3;
input [4:0] VAR10;
input [3:0] VAR4;
input VAR19;
input VAR2;
input VAR7;
input [2:0] VAR6;
integer VAR18;
integer VAR8;
integer VAR5;
integer VAR11;
inte... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd/sky130_fd_sc_ls__tapvgnd.behavioral.v | 1,193 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/controller/bank_cntrl.v | 25,877 | module MODULE1 #
(
parameter VAR133 = 100,
parameter VAR121 = "1T",
parameter VAR86 = 3,
parameter VAR109 = 2,
parameter VAR68 = "8",
parameter VAR8 = 12,
parameter VAR97 = 5,
parameter VAR83 = 8,
parameter VAR113 = "VAR95",
parameter VAR28 = "VAR40",
parameter VAR116 = 4,
parameter VAR142 = 4,
parameter VAR102 = 2,
pa... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_1.functional.v | 1,384 | module MODULE1( VAR6, VAR17, VAR9, VAR15, VAR4, VAR3, VAR19 );
input VAR19, VAR3, VAR6, VAR9, VAR17, VAR4;
output VAR15;
wire VAR16;
not VAR7( VAR16, VAR17 );
wire VAR1;
not VAR10( VAR1, VAR4 );
wire VAR5;
and VAR20( VAR5, VAR16, VAR1, VAR19 );
wire VAR11;
and VAR2( VAR11, VAR1, VAR3, VAR17 );
wire VAR18;
and VAR12( VA... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/SSDS_misr.v | 1,069 | module MODULE1 #(parameter VAR3 = 32)
(input
VAR5,
reset,
enable,
input [VAR3-1:0]
VAR7,
VAR2,
in,
output
reg [VAR3-1:0] out
);
integer VAR6;
reg [VAR3-1:0] VAR1;
always @(posedge VAR5, posedge reset) begin
if (reset == 1'b1)
out <= VAR2;
end
else if (^in === 1'VAR4)
out <= VAR1;
else if (enable == 1'b1 && ^in !== 1'VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_2.behavioral.v | 3,634 | module MODULE1( VAR24, VAR5, VAR17, VAR23 );
input VAR24, VAR5, VAR17;
output VAR23;
reg VAR25;
VAR11 VAR27(.VAR24(VAR24),.VAR5(VAR5),.VAR17(VAR17),.VAR23(VAR23),.VAR25(VAR25));
VAR11 VAR12(.VAR24(VAR24),.VAR5(VAR5),.VAR17(VAR17),.VAR23(VAR23),.VAR25(VAR25));
not VAR19(VAR2,VAR5);
and VAR22(VAR9,VAR17,VAR2);
and VAR29(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1.pp.symbol.v | 1,357 | module MODULE1 (
input VAR2 ,
output VAR3 ,
input VAR4 ,
input VAR5,
input VAR1,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtp/sky130_fd_sc_hs__dlxtp.functional.v | 1,591 | module MODULE1 (
VAR10,
VAR5,
VAR8 ,
VAR2 ,
VAR7
);
input VAR10;
input VAR5;
output VAR8 ;
input VAR2 ;
input VAR7;
wire VAR6 VAR11;
wire VAR6 VAR4 ;
wire VAR6 ;
VAR3 VAR1 (VAR6 , VAR2, VAR7, VAR10, VAR5);
buf VAR9 (VAR8 , VAR6 );
endmodule | apache-2.0 |
carstenbru/fpga-log | spartanmc/hardware/uart_light/src/uart_light_rx.v | 3,758 | module MODULE1
parameter VAR8 = 15,
parameter VAR11 = 4,
parameter VAR5 = 8,
parameter VAR24 = 5
)(
input wire reset,
input wire VAR6,
input wire VAR16,
input wire VAR21,
input wire VAR20,
output wire [VAR5-1:0] VAR10,
output wire VAR27,
output wire VAR7
);
wire VAR15,VAR17,VAR14,VAR26,VAR25,VAR19,VAR9,VAR2,VAR13,VAR22... | gpl-3.0 |
AmeerAbdelhadi/Multiported-RAM | mpram_wrp.v | 5,856 | module MODULE1
MODULE1 #( .VAR12 (VAR12 ), .VAR14 (VAR14 ), .VAR13(VAR13), .VAR11(VAR11), .VAR10 (VAR10 ), .VAR1 (VAR1 ), .VAR7 ("" )) VAR2 ( .clk (clk ), .VAR8 (VAR8 ), .VAR4 (VAR4 ), .VAR3 (VAR3 ), .VAR5 (VAR5 ), .VAR6 (VAR6 ));
endmodule | bsd-3-clause |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x8_125/example_design/PIO_EP.v | 10,169 | module MODULE1 (
clk,
VAR51,
VAR69,
VAR15,
VAR45,
VAR82,
VAR23,
VAR70,
VAR86,
VAR17,
VAR2,
VAR49,
VAR44,
VAR60,
VAR77,
VAR28,
VAR38,
VAR46,
VAR5,
VAR68
);
input clk;
input VAR51;
output [( 64 - 1):0] VAR69;
output [7:0] VAR15;
output VAR45;
output VAR82;
output VAR23;
input VAR70;
input VAR86;
input [( 64 - 1):0] VAR17... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_4.functional.pp.v | 1,583 | module MODULE1( VAR7, VAR9, VAR5, VAR10, VAR14, VAR19 );
input VAR9, VAR7, VAR5;
inout VAR14, VAR19;
output VAR10;
wire VAR17;
and VAR6( VAR17, VAR9, VAR7, VAR5 );
wire VAR3;
not VAR20( VAR3, VAR7 );
wire VAR12;
not VAR2( VAR12, VAR5 );
wire VAR16;
and VAR15( VAR16, VAR3, VAR12, VAR9 );
wire VAR8;
not VAR1( VAR8, VAR9 ... | apache-2.0 |
theapi/de0-nano | vga/vga_800x480_buffered/vga_export.v | 2,294 | module MODULE1(
VAR6,
VAR32,
VAR18,
VAR15,
VAR31,
VAR4,
VAR5
);
input wire VAR6;
input wire [0:0] VAR32;
output wire VAR18;
output wire VAR15;
output wire VAR31;
output wire VAR4;
output wire VAR5;
wire VAR9;
wire VAR24;
wire VAR23;
wire VAR13;
wire [15:0] VAR19;
wire [10:0] VAR14;
wire [10:0] VAR33;
wire [15:0] VAR11;... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_26.v | 20,064 | module MODULE1 (
clk,
reset,
VAR126,
VAR146,
VAR145,
VAR51,
VAR9
);
parameter VAR97 = 18;
parameter VAR37 = 26;
parameter VAR47 = 13;
localparam VAR35 = 32;
input clk;
input reset;
input VAR126;
input VAR146;
input [VAR97-1:0] VAR145; output VAR51;
output [VAR97-1:0] VAR9;
localparam VAR40 = 18; localparam VAR142 = 36;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111a/sky130_fd_sc_hs__o2111a_1.v | 2,321 | module MODULE2 (
VAR6 ,
VAR2 ,
VAR10 ,
VAR7 ,
VAR4 ,
VAR5 ,
VAR8,
VAR9
);
output VAR6 ;
input VAR2 ;
input VAR10 ;
input VAR7 ;
input VAR4 ;
input VAR5 ;
input VAR8;
input VAR9;
VAR3 VAR1 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9)
);
endmodule
module MODUL... | apache-2.0 |
peteasa/parallella-fpga | AdaptevaLib/src/esaxi/hdl/esaxi_v1_0.v | 5,967 | module MODULE1 #
(
parameter [11:0] VAR47 = 12'h810,
parameter integer VAR96 = 1,
parameter integer VAR102 = 32,
parameter integer VAR124 = 30,
parameter integer VAR35 = 0,
parameter integer VAR87 = 0,
parameter integer VAR85 = 0,
parameter integer VAR117 = 0,
parameter integer VAR28 = 0
)
(
output wire [102:0] VAR33,
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41a/sky130_fd_sc_lp__o41a.pp.blackbox.v | 1,400 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR7 ,
VAR6 ,
VAR4 ,
VAR1 ,
VAR8,
VAR3,
VAR9 ,
VAR5
);
output VAR10 ;
input VAR2 ;
input VAR7 ;
input VAR6 ;
input VAR4 ;
input VAR1 ;
input VAR8;
input VAR3;
input VAR9 ;
input VAR5 ;
endmodule | apache-2.0 |
jakubfi/mera400f | src/pk.v | 2,841 | module MODULE1(
input VAR61,
input VAR45,
input VAR12,
output VAR40,
output VAR57,
output VAR46,
output VAR6,
output VAR18,
input VAR36,
output [0:15] VAR53,
output VAR43,
output VAR3,
output VAR34,
output VAR1,
output VAR42,
output VAR59,
output VAR20,
output VAR9,
output reg VAR66,
input VAR60,
input VAR47,
input VAR... | gpl-2.0 |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/Verilog_Source/Macros/clock_generator_ddr_s8_diff.v | 6,394 | module MODULE1 (VAR3, VAR25, VAR33, VAR15, VAR14, VAR22, VAR27, VAR19, VAR5) ;
parameter integer VAR23 = 8 ; parameter VAR16 = "VAR13" ;
input VAR3, VAR25 ; output VAR33 ; output VAR15 ; output VAR14 ; output VAR22 ; output VAR27 ; output VAR19 ; output VAR5 ;
wire VAR34 ; wire VAR10 ; wire VAR11 ; wire VAR17 ;
assign ... | apache-2.0 |
VitorCBSB/hw-verilog | C++/Verilog/circ_gen/sender.v | 1,790 | module MODULE1(VAR16, VAR10, VAR5, VAR1, VAR8, VAR15, VAR9);
parameter VAR17 = 3'b000,
VAR14 = 3'b001,
VAR3 = 3'b010, VAR12 = 3'b011,
VAR6 = 3'b100,
VAR2 = 3'b101;
input VAR16;
input VAR10;
input VAR5;
input VAR1;
output VAR9;
output VAR15;
output [15:0] VAR8;
reg [2:0] state = VAR17;
wire [2:0] VAR13;
assign VAR13 = V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21o/sky130_fd_sc_hs__a21o.symbol.v | 1,305 | module MODULE1 (
input VAR4,
input VAR5,
input VAR6,
output VAR1
);
supply1 VAR3;
supply0 VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv_4.v | 1,995 | module MODULE2 (
VAR4 ,
VAR8 ,
VAR2,
VAR6,
VAR7 ,
VAR5
);
output VAR4 ;
input VAR8 ;
input VAR2;
input VAR6;
input VAR7 ;
input VAR5 ;
VAR3 VAR1 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR4,
VAR8
);
output VAR4;
input VAR8;
supply1 VAR2;
supply0 VAR6;... | apache-2.0 |
ptracton/wb_dsp | rtl/wb_daq_bus_master.v | 13,546 | module MODULE1 (
VAR1, VAR2, VAR24, VAR55, VAR4, VAR62,
VAR5, VAR17, VAR27, VAR15,
VAR19, VAR48, VAR49, VAR12, VAR59, VAR75,
VAR36, VAR38, VAR32, VAR9,
VAR63, address, VAR56
) ;
parameter VAR54 = 32;
parameter VAR6 = 32;
parameter VAR34 = 0;
input VAR19;
input VAR48;
output wire [VAR6-1:0] VAR1;
output wire [VAR54-1:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22a/sky130_fd_sc_lp__o22a_0.v | 2,339 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR6 ,
VAR2 ,
VAR9 ,
VAR3,
VAR8,
VAR1 ,
VAR4
);
output VAR7 ;
input VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR3;
input VAR8;
input VAR1 ;
input VAR4 ;
VAR11 VAR10 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(V... | apache-2.0 |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/submodules/wasca_uart_0.v | 27,688 | module MODULE2 (
VAR61,
VAR97,
clk,
VAR22,
VAR72,
VAR38,
VAR17,
VAR57,
VAR47,
VAR11,
VAR70,
VAR84,
VAR77
)
;
output VAR11;
output VAR70;
output VAR84;
output VAR77;
input [ 15: 0] VAR61;
input VAR97;
input clk;
input VAR22;
input VAR72;
input VAR38;
input VAR17;
input [ 7: 0] VAR57;
input VAR47;
reg VAR100;
reg [ 15: 0... | gpl-2.0 |
gtaylormb/fpga_nes | hw/src/cmn/uart/uart_tx.v | 6,471 | module MODULE1
parameter VAR1 = 8,
parameter VAR5 = 1,
parameter VAR11 = 1, parameter VAR9 = 16
)
(
input wire clk, input wire reset, input wire VAR25, input wire VAR2, input wire [VAR1-1:0] VAR21, output wire VAR29, output wire VAR12 );
localparam [5:0] VAR18 = VAR5 * VAR9;
localparam [4:0] VAR28 = 5'h01,
VAR27 = 5'h0... | bsd-2-clause |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x1_125/source/pcie_mim_wrapper.v | 9,098 | module MODULE1 #(
parameter VAR39 = 4096,
parameter VAR45 = 0,
parameter VAR11 = 0,
parameter VAR25 = 0,
parameter VAR27 = 4096,
parameter VAR4 = 0,
parameter VAR42 = 0,
parameter VAR19 = 0,
parameter VAR36 = 3,
parameter VAR34 = 0,
parameter VAR32 = 9,
parameter VAR20 = 3,
parameter VAR9 = 0,
parameter VAR37 = 0,
para... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32a/sky130_fd_sc_hs__o32a.pp.blackbox.v | 1,364 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR7 ,
VAR5 ,
VAR1 ,
VAR2 ,
VAR8,
VAR6
);
output VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR5 ;
input VAR1 ;
input VAR2 ;
input VAR8;
input VAR6;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211ai/sky130_fd_sc_ls__o211ai_1.v | 2,361 | module MODULE2 (
VAR11 ,
VAR6 ,
VAR9 ,
VAR10 ,
VAR5 ,
VAR3,
VAR8,
VAR1 ,
VAR4
);
output VAR11 ;
input VAR6 ;
input VAR9 ;
input VAR10 ;
input VAR5 ;
input VAR3;
input VAR8;
input VAR1 ;
input VAR4 ;
VAR7 VAR2 (
.VAR11(VAR11),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_OA_RVT_FF_210930.v | 242,184 | module MODULE1 (VAR1, VAR6, VAR7, VAR4, VAR8, VAR5);
output VAR1;
input VAR6, VAR7, VAR4, VAR8, VAR5;
wire VAR12, VAR10, VAR3;
wire VAR9, VAR2, VAR11;
wire VAR13;
not (VAR2, VAR5);
not (VAR9, VAR8);
not (VAR3, VAR4);
and (VAR11, VAR3, VAR9);
not (VAR10, VAR7);
not (VAR12, VAR6);
and (VAR13, VAR12, VAR10, VAR9);
or (VAR... | bsd-3-clause |
binderclip/BCOpenMIPS | cpu-code/ctrl.v | 1,274 | module MODULE1 (
input wire rst,
input wire VAR12,
input wire VAR4,
input wire[VAR6] VAR7,
input wire[VAR6] VAR8,
output reg[5:0] VAR2,
output reg[VAR6] VAR14,
output reg VAR11
);
always @(*) begin
if (rst == VAR10) begin
VAR2 <= VAR13;
VAR14 <= VAR5;
VAR11 <= VAR3;
end
else if (VAR7 != VAR5) begin
VAR2 <= VAR13;
VAR11... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_dtl_pad.v | 5,047 | module MODULE1(VAR24 ,VAR16 ,VAR50 ,VAR17 ,VAR2 ,
VAR64 ,VAR47 ,clk ,VAR26 ,VAR51 ,VAR39 ,VAR14 ,
VAR27 ,VAR57 ,VAR23 ,VAR29 ,VAR37 ,VAR65 ,VAR4
,VAR30 ,VAR61 ,VAR35 ,VAR43 ,VAR49 ,VAR59 ,VAR45 ,VAR9 ,ref ,VAR20 ,
VAR38 ,VAR11 ,VAR62 ,VAR40 );
input [8:1] VAR11 ;
input [8:1] VAR62 ;
output VAR16 ;
output VAR29 ;
output... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd.symbol.v | 1,239 | module MODULE1 ();
supply1 VAR4;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
borti4938/n64rgb | advancedRGBmod/firmware/rtl/n64adv_clk_n_rst_hk.v | 3,716 | module MODULE1(
VAR14,
VAR19,
VAR23,
VAR17,
VAR21,
VAR27,
VAR18,
VAR3,
VAR15,
VAR2
);
input VAR14;
input VAR19;
input VAR23;
output VAR17;
output VAR21;
input [1:0] VAR27;
output VAR18;
output reg VAR3;
output [2:0] VAR15;
output [2:0] VAR2;
wire VAR29, VAR24;
VAR16 VAR28(
.VAR1(VAR14),
.VAR32(~VAR23),
.VAR20(VAR29),
.... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrbp/sky130_fd_sc_hd__dfrbp.symbol.v | 1,423 | module MODULE1 (
input VAR3 ,
output VAR5 ,
output VAR4 ,
input VAR1,
input VAR2
);
supply1 VAR6;
supply0 VAR9;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_4.behavioral.v | 6,154 | module MODULE1( VAR4, VAR25, VAR6, VAR49, VAR45 );
input VAR25, VAR4, VAR6, VAR49;
output VAR45;
reg VAR35;
VAR5 VAR39(.VAR4(VAR4),.VAR25(VAR25),.VAR6(VAR6),.VAR49(VAR49),.VAR45(VAR45),.VAR35(VAR35));
VAR5 VAR62(.VAR4(VAR4),.VAR25(VAR25),.VAR6(VAR6),.VAR49(VAR49),.VAR45(VAR45),.VAR35(VAR35));
and VAR56(VAR2,VAR49,VAR6)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufbuf/sky130_fd_sc_hs__bufbuf.pp.blackbox.v | 1,192 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR2,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR2;
input VAR1;
endmodule | apache-2.0 |
GSejas/Karatsuba_FPU | my_sourcefiles/cordic_jeffrey/FPU_Add_Subtract_Function.v | 12,627 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR23,
input wire VAR32,
input wire [VAR7-1:0] VAR17,
input wire [VAR7-1:0] VAR105,
input wire VAR5,
input wire [1:0] VAR16,
output wire VAR13,
output wire VAR28,
output wire ready,
output wire [VAR7-1:0] VAR139
);
wire VAR145,VAR89;
wire [VAR7-2:0] VAR143, VA... | gpl-3.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/mult_descale_pipeline.v | 3,428 | module MODULE1(
input [31:0] VAR3,
input [31:0] VAR37,
input [31:0] VAR28,
input [7:0] VAR6,
input VAR8,
input VAR14,
input reset,
input VAR39,
output [31:0] VAR33,
output VAR5,
output [7:0] VAR9,
output [31:0] VAR18
);
wire VAR36, VAR35, VAR42;
wire [32:0] VAR21,VAR7;
wire [32:0] VAR15,VAR19,VAR25;
wire [49:0] VAR38, ... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcjesdadc1/kc705/system_top.v | 11,179 | module MODULE1 (
VAR81,
VAR49,
VAR61,
VAR40,
VAR122,
VAR38,
VAR59,
VAR42,
VAR86,
VAR69,
VAR41,
VAR15,
VAR118,
VAR70,
VAR95,
VAR34,
VAR55,
VAR32,
VAR92,
VAR89,
VAR16,
VAR5,
VAR85,
VAR109,
VAR39,
VAR7,
VAR13,
VAR47,
VAR114,
VAR65,
VAR62,
VAR87,
VAR112,
VAR117,
VAR14,
VAR107,
VAR76,
VAR123,
VAR82,
VAR24,
VAR64,
VAR75,
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbp/sky130_fd_sc_hd__sdfbbp_1.v | 2,821 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR1 ,
VAR5 ,
VAR11 ,
VAR12 ,
VAR3 ,
VAR10,
VAR6 ,
VAR4 ,
VAR7 ,
VAR14
);
output VAR2 ;
output VAR8 ;
input VAR1 ;
input VAR5 ;
input VAR11 ;
input VAR12 ;
input VAR3 ;
input VAR10;
input VAR6 ;
input VAR4 ;
input VAR7 ;
input VAR14 ;
VAR9 VAR13 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.V... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v | 12,271 | module MODULE1
(
VAR36, VAR49, VAR60, VAR70, VAR51, VAR28,
VAR23, VAR6, VAR67, VAR56, VAR41, VAR21,
VAR14, VAR40, VAR26, VAR61
);
input VAR36; input VAR49; input [4:0] VAR60; input [32-1:0] VAR70; output [32-1:0] VAR51; input [3:0] VAR28; input VAR23; input VAR6; input VAR67; output VAR56; output VAR41; output VAR21;
o... | gpl-2.0 |
merckhung/zet | cores/speaker/wm8731/speaker.v | 2,433 | module MODULE1 (
input clk,
input rst,
input [7:0] VAR19,
output reg [7:0] VAR7,
input VAR5,
input VAR22,
input VAR13,
output VAR31,
input VAR9,
input VAR14,
input VAR15,
output VAR27,
inout VAR1,
input VAR4,
input VAR21,
output VAR30,
input VAR25
);
wire [15:0] VAR3;
wire [15:0] VAR16;
wire write;
wire VAR24;
VAR8 VAR... | gpl-3.0 |
ptracton/Picoblaze | library/timers/pb_timer.v | 2,441 | module MODULE1 (
VAR2, interrupt,
clk, reset, VAR15, VAR4, VAR8, VAR7, VAR9
) ;
parameter VAR11 = 8'h00;
input clk;
input reset;
input [7:0] VAR15;
input [7:0] VAR4;
output [7:0] VAR2;
input VAR8;
input VAR7;
output interrupt;
input VAR9;
wire [31:0] VAR6; wire VAR1; wire VAR5; wire VAR13;
VAR12 VAR10 (
.VAR2 (VAR2[7:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3.pp.symbol.v | 1,322 | module MODULE1 (
input VAR6 ,
output VAR1 ,
input VAR3 ,
input VAR5,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
Chapna/TTCache | src/cachek.v | 2,228 | module MODULE1 (enable, VAR16, word, VAR25,
write, VAR21, VAR24, VAR2,
rst, VAR26, VAR22, VAR5,
VAR18, valid, ack);
parameter VAR23 = 15;
reg [0:3] counter;
input enable;
input [0:3] VAR16;
input [0:1] word;
input VAR25;
input write;
input [0:4] VAR21;
input [0:15] VAR24;
input VAR2;
input rst;
output reg VAR26;
output... | gpl-2.0 |
eda-globetrotter/PicenoDecoders | final/src/shift.v | 99,440 | module MODULE1 (VAR10,VAR19,VAR31,VAR6,VAR32);
output [0:127] VAR32;
input [0:127] VAR10;
input [0:127] VAR19;
input [0:1] VAR31;
input [0:4] VAR6;
parameter VAR24 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR32;
reg [0:127] VAR4;
reg [0:15] VAR3;
reg [0:15] VAR14;
reg [0:15] VAR17;
reg [0:15] VAR27;
reg [0:... | mit |
krmarien/Proxmark | fpga/fpga.v | 4,715 | module MODULE1(
VAR6, VAR50, VAR11, VAR32,
VAR38, VAR19, VAR14,
VAR39, VAR33, VAR9, VAR53, VAR31, VAR4,
VAR52, VAR3, VAR57,
VAR56, VAR59, VAR12, VAR49,
VAR1, VAR27,
VAR28
);
input VAR6, VAR11, VAR32;
output VAR50;
input VAR38, VAR19, VAR14;
output VAR39, VAR33, VAR9, VAR53, VAR31, VAR4;
input [7:0] VAR52;
output VAR3, ... | gpl-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/verilog/FIFO_image_filter_p_src_data_stream_2_V.v | 3,017 | module MODULE1 (
clk,
VAR11,
VAR9,
VAR23,
VAR1);
parameter VAR19 = 32'd8;
parameter VAR13 = 32'd1;
parameter VAR10 = 32'd2;
input clk;
input [VAR19-1:0] VAR11;
input VAR9;
input [VAR13-1:0] VAR23;
output [VAR19-1:0] VAR1;
reg[VAR19-1:0] VAR8 [0:VAR10-1];
integer VAR21;
always @ (posedge clk)
begin
if (VAR9)
begin
for (... | gpl-3.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/video/video_palframe.v | 1,062 | module MODULE1(
input wire clk,
input wire VAR3,
input wire VAR1,
input wire VAR2,
input wire VAR10,
input wire [ 3:0] VAR12,
input wire [ 3:0] VAR11,
input wire VAR13,
input wire [ 5:0] VAR9,
output reg [ 5:0] VAR4,
output wire [ 5:0] VAR8
);
wire [ 3:0] VAR6;
reg VAR5;
reg [3:0] VAR7;
assign VAR6 = (VAR3&VAR1) ? VAR1... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_pipe_eq.v | 27,422 | module MODULE1
(
input VAR41,
input VAR16,
input VAR38,
input [ 1:0] VAR97,
input [ 3:0] VAR75,
input [ 3:0] VAR120,
input [ 5:0] VAR1,
input [ 1:0] VAR73,
input [ 2:0] VAR57,
input [ 5:0] VAR114,
input [ 3:0] VAR81,
output VAR42,
output [ 4:0] VAR105,
output [ 6:0] VAR106,
output [ 4:0] VAR51,
output [17:0] VAR25,
out... | lgpl-3.0 |
alexforencich/xfcp | lib/eth/rtl/gmii_phy_if.v | 4,024 | module MODULE1 #
(
parameter VAR33 = "VAR40",
parameter VAR22 = "VAR35",
parameter VAR31 = "VAR43"
)
(
input wire clk,
input wire rst,
output wire VAR41,
output wire VAR1,
output wire [7:0] VAR9,
output wire VAR27,
output wire VAR13,
output wire VAR5,
output wire VAR38,
input wire [7:0] VAR12,
input wire VAR7,
input wi... | mit |
grvmind/amber-cycloneiii | trunk/hw/vlog/system/ethmac_wb.v | 7,638 | module MODULE1 #(
parameter VAR28 = 32,
parameter VAR21 = 4
)(
input [31:0] VAR26,
input [3:0] VAR38,
input VAR2,
output [31:0] VAR4,
input [31:0] VAR30,
input VAR24,
input VAR12,
output VAR22,
output VAR35,
output [31:0] VAR29,
output [VAR21-1:0] VAR16,
output VAR8,
input [VAR28-1:0] VAR7,
output [VAR28-1:0] VAR25,
ou... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr_3.v | 2,126 | module MODULE2 (
VAR2 ,
VAR7,
VAR6 ,
VAR5 ,
VAR3
);
input VAR2 ;
input VAR7;
input VAR6 ;
input VAR5 ;
input VAR3 ;
VAR1 VAR4 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR2 ;
supply1 VAR7;
supply0 VAR6 ;
supply1 VAR5 ;
supply0 VAR3 ;
VAR1 VAR4 ();
endmodul... | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_49.v | 31,847 | module MODULE2 (
clk,
reset,
VAR3,
VAR184,
VAR208,
VAR196,
VAR265
);
parameter VAR125 = 18;
parameter VAR174 = 49;
parameter VAR159 = 25;
localparam VAR214 = 50;
input clk;
input reset;
input VAR3;
input VAR184;
input [VAR125-1:0] VAR208; output VAR196;
output [VAR125-1:0] VAR265;
localparam VAR206 = 18; localparam VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4bb/sky130_fd_sc_ls__and4bb.functional.pp.v | 1,998 | module MODULE1 (
VAR13 ,
VAR1 ,
VAR2 ,
VAR17 ,
VAR16 ,
VAR6,
VAR7,
VAR8 ,
VAR10
);
output VAR13 ;
input VAR1 ;
input VAR2 ;
input VAR17 ;
input VAR16 ;
input VAR6;
input VAR7;
input VAR8 ;
input VAR10 ;
wire VAR12 ;
wire VAR5 ;
wire VAR4;
nor VAR14 (VAR12 , VAR1, VAR2 );
and VAR11 (VAR5 , VAR12, VAR17, VAR16 );
VAR3 VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2b/sky130_fd_sc_hd__nor2b_4.v | 2,173 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR5 ,
VAR1,
VAR7,
VAR3 ,
VAR8
);
output VAR4 ;
input VAR2 ;
input VAR5 ;
input VAR1;
input VAR7;
input VAR3 ;
input VAR8 ;
VAR6 VAR9 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR4 ,
VAR2 ,
VAR5
);
output VAR4... | apache-2.0 |
Iuliiapl/schoolMIPS | board/de10_standard/de10_standard.v | 1,681 | module MODULE1
(
input VAR11,
input VAR12,
input VAR2,
input VAR19,
input [3:0] VAR1,
input [9:0] VAR14,
output [9:0] VAR10,
output [6:0] VAR16,
output [6:0] VAR26,
output [6:0] VAR13,
output [6:0] VAR22,
output [6:0] VAR15,
output [6:0] VAR4
);
wire clk;
wire VAR5 = VAR19;
wire VAR23 = VAR1[0];
wire VAR6 = VAR14 [9] |... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_19.v | 14,982 | module MODULE3 (
clk,
reset,
VAR89,
VAR86,
VAR60,
VAR120,
VAR105
);
parameter VAR76 = 18;
parameter VAR91 = 19;
parameter VAR106 = 10;
localparam VAR58 = 20;
input clk;
input reset;
input VAR89;
input VAR86;
input [VAR76-1:0] VAR60; output VAR120;
output [VAR76-1:0] VAR105;
localparam VAR107 = 18; localparam VAR85 = 36... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3b/sky130_fd_sc_ls__nand3b.symbol.v | 1,313 | module MODULE1 (
input VAR7,
input VAR4 ,
input VAR3 ,
output VAR2
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
SymbiFlow/symbiflow-arch-defs | xc/xc7/techmap/iobs.v | 20,474 | module MODULE1 (
input VAR2,
output VAR3
);
parameter VAR5 = "default";
parameter VAR1 = 0;
parameter VAR4 = "VAR6"; parameter VAR7 = "";
assign VAR3 = VAR2; | isc |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/hps_sdram_p0_reset.v | 4,395 | module MODULE1(
VAR23,
VAR14,
VAR4,
VAR2,
VAR27,
VAR37,
VAR1,
VAR25,
VAR18,
VAR33,
VAR16,
VAR38,
VAR11,
VAR20,
VAR12,
VAR5,
VAR8,
VAR24,
VAR34,
VAR40
);
parameter VAR22 = "";
parameter VAR15 = 1;
input VAR23;
input VAR14;
input VAR4;
input VAR2;
input VAR27;
input VAR37;
input VAR1;
output VAR25;
output VAR18;
input [V... | mit |
Jafet95/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales | Modificacion_Frec_Conmu.v | 1,806 | module MODULE1
(
input wire VAR11,
input wire VAR22,
input wire VAR16,
input wire VAR24,
input wire reset,
output wire VAR26,
output wire VAR21,
output wire [3:0] VAR8 );
wire VAR2; wire VAR17;
VAR25 VAR15(
.VAR6(VAR22), .VAR10(VAR16), .clk(VAR11), .reset(reset), .VAR4(~VAR24), .VAR20(VAR2), .VAR18(VAR17) );
VAR7 VAR1(... | apache-2.0 |
qeedquan/fpga | de2-115/uart_echo/2_debounce.v | 1,748 | module MODULE1
(
input wire clk,
input wire VAR8,
output reg VAR11,
output reg VAR6
);
localparam VAR9 = 21;
localparam VAR3 = 0;
localparam VAR1 = 1;
localparam VAR10 = 2;
localparam VAR4 = 3;
reg [1:0] VAR5, VAR2;
reg [VAR9-1:0] VAR12, VAR7;
always @ (posedge clk) begin
VAR5 <= VAR2;
VAR12 <= VAR7;
end
always @ (VAR5... | mit |
kyzhai/NUNY | src/hardware/bomb_bb.v | 4,976 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
TramyLee/cordic_base | cordic2/merge/merge_step.v | 2,352 | module MODULE1(VAR20,VAR23,VAR37,VAR13,VAR2,clk);
input clk;
input [VAR40-1:0] VAR20;
input [VAR40-1:0] VAR23;
input [7:0] VAR37;
output reg [VAR40-1:0] VAR13;
output reg [VAR40-1:0] VAR2;
wire [VAR40-1:0] VAR5;
wire [VAR40-1:0] VAR9;
wire [VAR40-1:0] VAR29;
wire [VAR40-1:0] VAR36;
wire [VAR40-1:0] VAR4;
wire [VAR40-1:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfstp/sky130_fd_sc_hs__sdfstp.functional.v | 2,012 | module MODULE1 (
VAR12 ,
VAR1 ,
VAR7 ,
VAR16 ,
VAR5 ,
VAR6 ,
VAR18 ,
VAR11
);
input VAR12 ;
input VAR1 ;
output VAR7 ;
input VAR16 ;
input VAR5 ;
input VAR6 ;
input VAR18 ;
input VAR11;
wire VAR9 ;
wire VAR15 ;
wire VAR17;
not VAR8 (VAR15 , VAR11 );
VAR10 VAR13 (VAR17, VAR5, VAR6, VAR18 );
VAR14 VAR2 VAR3 (VAR9 , VAR17... | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/akiko.v | 2,194 | module MODULE1
(
input clk,
input VAR4.
input reset,
input [23:1] VAR3,
input [15:0] VAR7,
output [15:0] VAR1,
input rd,
input VAR6 );
reg [127:0] VAR5;
reg [6:0] VAR2;
wire sel;
assign sel = VAR6 && VAR3[7:1]==8'b0011100;
always @(posedge clk)
if (VAR4) begin
if (reset)
VAR2 <= 0;
end
else if (!rd && sel) begin
case(V... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_012bits.v | 1,917 | module MODULE2 (
clk,
VAR31, VAR16, VAR10, VAR24, VAR7, VAR29, VAR34, VAR25,
sum,
);
input clk;
input [VAR30+0-1:0] VAR31, VAR16, VAR10, VAR24, VAR7, VAR29, VAR34, VAR25;
output [VAR30 :0] sum;
reg [VAR30 :0] sum;
wire [VAR30+3-1:0] VAR28;
wire [VAR30+2-1:0] VAR20, VAR14;
wire [VAR30+1-1:0] VAR6, VAR5, VAR17, VAR1;
reg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41oi/sky130_fd_sc_lp__a41oi.blackbox.v | 1,390 | module MODULE1 (
VAR4 ,
VAR9,
VAR8,
VAR7,
VAR6,
VAR3
);
output VAR4 ;
input VAR9;
input VAR8;
input VAR7;
input VAR6;
input VAR3;
supply1 VAR1;
supply0 VAR5;
supply1 VAR10 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
richard42/CoCo3FPGA | disk02_bb.v | 5,927 | module MODULE1 (
address,
VAR3,
VAR1,
VAR2,
VAR4);
input [10:0] address;
input VAR3;
input [7:0] VAR1;
input VAR2;
output [7:0] VAR4;
tri1 VAR3;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd.blackbox.v | 1,227 | module MODULE1 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41ai/sky130_fd_sc_ms__o41ai.pp.blackbox.v | 1,408 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR3 ,
VAR9 ,
VAR6 ,
VAR10 ,
VAR4,
VAR8,
VAR1 ,
VAR2
);
output VAR7 ;
input VAR5 ;
input VAR3 ;
input VAR9 ;
input VAR6 ;
input VAR10 ;
input VAR4;
input VAR8;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/i2c/bench/verilog/i2c_slave_model.v | 11,527 | module MODULE1 (VAR14, VAR1);
parameter VAR3 = 7'b0010000;
input VAR14;
inout VAR1;
wire VAR12 = 1'b1;
reg [7:0] VAR6 [3:0]; reg [7:0] VAR21; reg [7:0] VAR13;
reg VAR4, VAR18;
reg VAR5, VAR17;
reg [7:0] VAR24; reg VAR10;
wire VAR25; wire VAR19; reg [2:0] VAR20; wire VAR22; reg VAR8;
reg VAR7; wire VAR2;
parameter VAR26... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311o/sky130_fd_sc_lp__a311o_2.v | 2,437 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR11 ,
VAR4 ,
VAR5 ,
VAR2 ,
VAR10,
VAR3,
VAR7 ,
VAR9
);
output VAR6 ;
input VAR8 ;
input VAR11 ;
input VAR4 ;
input VAR5 ;
input VAR2 ;
input VAR10;
input VAR3;
input VAR7 ;
input VAR9 ;
VAR12 VAR1 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3/sky130_fd_sc_hdll__nand3.blackbox.v | 1,268 | module MODULE1 (
VAR7,
VAR2,
VAR8,
VAR5
);
output VAR7;
input VAR2;
input VAR8;
input VAR5;
supply1 VAR4;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/maj3/sky130_fd_sc_lp__maj3.blackbox.v | 1,264 | module MODULE1 (
VAR8,
VAR2,
VAR3,
VAR7
);
output VAR8;
input VAR2;
input VAR3;
input VAR7;
supply1 VAR1;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.v | 2,065 | module MODULE2 (
VAR2 ,
VAR6 ,
VAR1,
VAR5,
VAR4 ,
VAR8
);
output VAR2 ;
input VAR6 ;
input VAR1;
input VAR5;
input VAR4 ;
input VAR8 ;
VAR7 VAR3 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR2,
VAR6
);
output VAR2;
input VAR6;
supply1 VAR1;
supply0 VAR5;... | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/foc_cmd_rx.v | 1,901 | module MODULE1
(input VAR26,
input [7:0] VAR36,
input VAR20,
input VAR24,
output [ 7:0] VAR9,
output [31:0] VAR5,
output [31:0] VAR35,
output [31:0] VAR34,
output VAR21);
wire [7:0] VAR11;
d1 #(8) VAR38(.VAR26(VAR26), .VAR13(VAR36), .VAR4(VAR11));
wire VAR14;
d1 VAR16(.VAR26(VAR26), .VAR13(VAR20), .VAR4(VAR14));
wire V... | apache-2.0 |
cpulabs/mist1032sa | src/core/scheduler2/reservation_search16to2.v | 17,527 | module MODULE1(
input wire VAR3,
input wire VAR32,
input wire VAR1,
input wire VAR10,
input wire VAR43,
input wire VAR14,
input wire VAR9,
input wire VAR7,
input wire VAR26,
input wire VAR46,
input wire VAR20,
input wire VAR13,
input wire VAR38,
input wire VAR44,
input wire VAR21,
input wire VAR12,
output wire VAR11,
o... | bsd-2-clause |
myriadrf/A2300 | hdl/wca/hal/WcaAdc.v | 7,915 | module MODULE1
(
input VAR10,
input VAR43,
input reset,
input enable,
input wire [13:0] VAR22, inout wire [15:0] VAR33,
input wire VAR27,
input wire [11:0] VAR42,
input wire VAR44,
input wire [11:0] VAR15,
output reg [11:0] VAR2,
output wire VAR6,
output wire VAR34,
output wire VAR18,
output wire VAR28,
output wire VAR... | gpl-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/new/XADC_REG.v | 6,469 | module MODULE1 (
input VAR56, input VAR21,
input [3:0] VAR77,
input [3:0] VAR71, input VAR65, VAR37, output reg [15:0] VAR16,
output reg [15:0] VAR76,
output reg [15:0] VAR39,
output reg [15:0] VAR24,
output reg [15:0] VAR38,
output reg [15:0] VAR63,
output reg [15:0] VAR13,
output reg [15:0] VAR72,
output wire [7:0] V... | mit |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/clock_0.v | 28,024 | module MODULE7 (
clk,
VAR21,
VAR46,
VAR58
)
;
output VAR58;
input clk;
input VAR21;
input VAR46;
reg VAR47 ;
reg VAR58 ;
always @(posedge clk or negedge VAR46)
begin
if (VAR46 == 0)
VAR47 <= 0;
end
else if (1)
VAR47 <= VAR21;
end
always @(posedge clk or negedge VAR46)
begin
if (VAR46 == 0)
VAR58 <= 0;
end
else if (1)
V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3.pp.symbol.v | 1,330 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR5 ,
input VAR1,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/CPC2.v | 23,684 | module MODULE5(
input VAR137,
input VAR132,
input VAR109,
input VAR71,
inout VAR383,
inout VAR405,
output VAR152,
output VAR146,
output VAR403,
output VAR195,
output VAR209,
output [7:0] VAR409,
output [7:0] VAR368,
output [7:0] VAR326,
output [3:0] VAR101,
output VAR73,
output VAR219,
output VAR126,
input VAR9,
output... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2b/sky130_fd_sc_hs__nand2b_1.v | 2,020 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR1 ,
VAR7,
VAR2
);
output VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR7;
input VAR2;
VAR6 VAR4 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR5 ,
VAR3,
VAR1
);
output VAR5 ;
input VAR3;
input VAR1 ;
supply1 VAR7;
supply0 VAR2;
VAR6 VAR4 ... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA_2_cycles/integracion_fisica/front_end/source/RecursiveKOA.v | 5,719 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR11,
input wire [VAR5-1:0] VAR17,
input wire [VAR5-1:0] VAR27,
output reg [2*VAR5-1:0] VAR24
);
wire [1:0] VAR1;
wire [3:0] VAR4;
assign VAR1 = 2'b00;
assign VAR4 = 4'b0000;
wire [VAR5/2-1:0] VAR25;
wire [VAR5/2:0] VAR33;
wire [VAR5/2-3:0] VAR35;
wire [VAR5/... | gpl-3.0 |
hongyunnchen/miaow | src/verilog/rtl/common/queue_param_1r_1w.v | 1,084 | module MODULE1(
VAR8,
VAR14,
VAR9,
VAR12,
VAR17,
clk,
rst
);
parameter VAR16 = 2;
parameter VAR10 = 4;
parameter VAR2 = 32;
input VAR8;
input [VAR16 - 1:0] VAR14;
input [VAR2 - 1:0] VAR9;
input [VAR16 - 1:0] VAR12;
output [VAR2 - 1:0] VAR17;
input clk;
input rst;
wire [(VAR10 * VAR2) - 1:0] VAR3;
wire [VAR10 - 1:0] VAR... | bsd-3-clause |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/transform_memory.v | 50,911 | module MODULE1(
clk,
rst,
VAR261,
VAR87,
VAR239,
VAR292,
VAR62,
VAR308,
VAR123,
VAR15,
VAR243,
VAR271,
VAR328,
VAR199,
VAR148,
VAR52,
VAR313,
VAR284,
VAR145,
VAR168,
VAR170,
VAR276,
VAR98,
VAR95,
VAR298,
VAR232,
VAR201,
VAR101,
VAR340,
VAR205,
VAR291,
VAR120,
VAR192,
VAR212,
VAR53,
VAR325,
VAR78,
o0,
o1,
o2,
o3,
o4,
o5... | gpl-3.0 |
omicronns/studies-sys-rek | de1-soc-template/DE1_SoC_CAMERA.v | 13,822 | module MODULE1(
inout VAR111,
output VAR174,
input VAR78,
output VAR165,
input VAR144,
inout VAR63,
inout VAR248,
output VAR211,
inout VAR220,
output VAR39,
input VAR196,
input VAR72,
input VAR147,
input VAR204,
output [12:0] VAR185,
output [1:0] VAR71,
output VAR80,
output VAR137,
output VAR236,
output VAR225,
inout [... | mit |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.