repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
peteasa/oh | src/common/hdl/oh_add.v | 1,181 | module MODULE1 #(parameter VAR7 = 1 )
(
input [VAR7-1:0] VAR8, input [VAR7-1:0] VAR1, input VAR4, input VAR6, output [VAR7-1:0] sum, output VAR5, output VAR2, output neg, output VAR3 );
wire [VAR7-1:0] VAR9;
assign VAR9[VAR7-1:0] = {(VAR7){VAR4}} ^ VAR1[VAR7-1:0];
assign {VAR5,sum[VAR7-1:0]} = VAR8[VAR7-1:0] +
VAR9[VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a221oi/sky130_fd_sc_hdll__a221oi.pp.symbol.v | 1,417 | module MODULE1 (
input VAR3 ,
input VAR6 ,
input VAR5 ,
input VAR10 ,
input VAR7 ,
output VAR2 ,
input VAR9 ,
input VAR8,
input VAR4,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311oi/sky130_fd_sc_lp__a311oi.functional.v | 1,485 | module MODULE1 (
VAR11 ,
VAR1,
VAR9,
VAR10,
VAR5,
VAR2
);
output VAR11 ;
input VAR1;
input VAR9;
input VAR10;
input VAR5;
input VAR2;
wire VAR7 ;
wire VAR6;
and VAR4 (VAR7 , VAR10, VAR1, VAR9 );
nor VAR8 (VAR6, VAR7, VAR5, VAR2);
buf VAR3 (VAR11 , VAR6 );
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/nuny_new2_bb.v | 5,028 | module MODULE1 (
address,
VAR2,
VAR1);
input [14:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
firemark/katp91 | src/Gpu.v | 2,066 | module MODULE1(clk, reset, VAR4, VAR5, VAR6, VAR8, VAR3, VAR1, VAR13);
input clk ;
input reset;
input VAR6, VAR8;
inout [15:0] VAR4;
input [7:0] VAR5;
output reg VAR3, VAR1;
output reg [7:0] VAR13;
reg [10:0] VAR11;
reg [10:0] VAR2;
reg [7:0] VAR10;
reg [15:0] VAR9[11:0] ;
reg [7:0] VAR14[8:0] ;
reg [15:0] VAR12;
assig... | mit |
DougFirErickson/parallella-hw | fpga/old/emaxi/hdl/emaxi_v1_0_M00_AXI.v | 21,470 | module MODULE1 #
(
parameter VAR29 = 32'h40000000,
parameter integer VAR107 = 16,
parameter integer VAR45 = 1,
parameter integer VAR21 = 32,
parameter integer VAR102 = 64,
parameter integer VAR88 = 0,
parameter integer VAR85 = 0,
parameter integer VAR67 = 0,
parameter integer VAR76 = 0,
parameter integer VAR50 = 0
)
(
... | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_01/02 verilog/ultrasonido_modulo_1/Periferico/j1.v | 4,469 | module MODULE1#(
parameter VAR23 = "./VAR26.VAR18" )
(
VAR17, VAR6, VAR27,
VAR40, VAR34, VAR13, VAR12);
input VAR17; input VAR6; input [15:0] VAR27; output VAR40; output VAR34; output [15:0] VAR13; output [15:0] VAR12;
wire [15:0] VAR11;
wire [15:0] VAR39 = { 1'b0, VAR11[14:0] };
wire [15:0] VAR10;
reg [4:0] VAR22;
reg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.v | 2,262 | module MODULE1 (
VAR1,
VAR5 ,
VAR10,
VAR6 ,
VAR8,
VAR2,
VAR7 ,
VAR9
);
output VAR1;
input VAR5 ;
input VAR10;
input VAR6 ;
input VAR8;
input VAR2;
input VAR7 ;
input VAR9 ;
VAR3 VAR4 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/4-way/src/riffa/tx_port_monitor_32.v | 8,699 | module MODULE1 #(
parameter VAR38 = 9'd32,
parameter VAR45 = 512,
parameter VAR10 = (VAR45 - 4),
parameter VAR12 = VAR17((2**VAR17(VAR45))+1),
parameter VAR8 = 1
)
(
input VAR19,
input VAR27,
input [VAR38:0] VAR1, input VAR16, output VAR26,
output [VAR38-1:0] VAR11, output VAR43, input [VAR12-1:0] VAR24,
output VAR32, ... | mit |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_auto_us_0/synth/dma_loopback_auto_us_0.v | 9,765 | module MODULE1 (
VAR43,
VAR75,
VAR76,
VAR32,
VAR35,
VAR56,
VAR80,
VAR38,
VAR64,
VAR3,
VAR63,
VAR7,
VAR21,
VAR39,
VAR93,
VAR45,
VAR59,
VAR85,
VAR26,
VAR102,
VAR34,
VAR82,
VAR98,
VAR58,
VAR20,
VAR14,
VAR15,
VAR29,
VAR33,
VAR37,
VAR96,
VAR74,
VAR41,
VAR51
);
input wire VAR43;
input wire VAR75;
input wire [31 : 0] VAR76;
i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4bb/sky130_fd_sc_ls__nor4bb.pp.blackbox.v | 1,351 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR2 ,
VAR1 ,
VAR8 ,
VAR6,
VAR9,
VAR3 ,
VAR4
);
output VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR8 ;
input VAR6;
input VAR9;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxtp/sky130_fd_sc_ls__dfxtp.behavioral.v | 1,760 | module MODULE1 (
VAR9 ,
VAR1,
VAR13
);
output VAR9 ;
input VAR1;
input VAR13 ;
supply1 VAR15;
supply0 VAR8;
supply1 VAR11 ;
supply0 VAR12 ;
wire VAR7 ;
reg VAR2 ;
wire VAR4 ;
wire VAR3;
wire VAR10 ;
VAR5 VAR6 (VAR7 , VAR4, VAR3, VAR2, VAR15, VAR8);
assign VAR10 = ( VAR15 === 1'b1 );
buf VAR14 (VAR9 , VAR7 );
endmodule | apache-2.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | escritor_lector_rtc - copia.v | 3,662 | module MODULE1
(
input wire clk,reset,
input wire [7:0] VAR7, VAR11,
input wire VAR10, VAR9, VAR16,
output wire VAR6,VAR31,VAR25,VAR28,
output wire[7:0]VAR12,
output reg VAR3,
inout [7:0]VAR19
);
wire VAR18;
reg VAR30;
reg [7:0]VAR21,VAR17;
reg [7:0]VAR8, VAR1;
reg VAR14,VAR33;
reg VAR23,VAR32;
wire VAR20;VAR29 VAR27 (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211o/sky130_fd_sc_ls__a211o_4.v | 2,348 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR2 ,
VAR11 ,
VAR6 ,
VAR4,
VAR10,
VAR5 ,
VAR3
);
output VAR7 ;
input VAR9 ;
input VAR2 ;
input VAR11 ;
input VAR6 ;
input VAR4;
input VAR10;
input VAR5 ;
input VAR3 ;
VAR8 VAR1 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR5(VAR5),
.... | apache-2.0 |
phase4ground/DVB-receiver | modem/hdl/library/multiply_accumulate_behavioural/multiply_accumulate_behavioural.v | 4,018 | module MODULE1 #
(
parameter integer VAR22 = 16,
parameter integer VAR3 = 16,
parameter integer VAR6 = 48,
parameter integer VAR9 = 0,
parameter integer VAR23 = 1,
parameter integer VAR16 = 1,
parameter integer VAR8 = 1,
parameter integer VAR11 = 0,
parameter integer VAR5 = 0,
parameter integer VAR19 = 1
)
(
input wire... | gpl-3.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T29-tristate/error1.v | 1,470 | module MODULE1 (
input wire clk, output wire [1:0] VAR4);
wire VAR1 = 1'b1;
reg [1:0] VAR2;
always @(posedge clk)
VAR2 <= 2'b11;
assign VAR4 = (VAR1) ? VAR2 : 2'VAR3;
endmodule | gpl-2.0 |
ashikpoojari/NIDS-Wu-Manber | Wu_Manber_compare.v | 3,648 | module MODULE1 #(parameter VAR17=4, VAR10=3, VAR13=14,VAR23=VAR26(VAR13-VAR10+1)+1,VAR21=4) ( input clk,
input reset,
input VAR22,
input [VAR17*VAR13-1:0] VAR1,
input [VAR17*VAR13*VAR21-1:0] VAR28,
output reg [VAR23-1:0] VAR3,
output reg VAR27);
localparam VAR9 = VAR13 -VAR10+1;
wire [VAR9-1:1] VAR19, VAR12, VAR2;
wire... | mit |
ptracton/wb_soc_template | rtl/XILINX/RAMB16_S9.v | 30,270 | module MODULE1 (VAR12, VAR16, VAR28, VAR38, VAR94, VAR121, VAR21, VAR41, VAR50);
parameter VAR133 = 9'h0;
parameter VAR126 = 9'h0;
parameter VAR117 = "VAR32";
parameter VAR4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR75 = 256'h00000000000000000000000000000000000000000000000000... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai.functional.v | 1,481 | module MODULE1 (
VAR10 ,
VAR6,
VAR7,
VAR1,
VAR4,
VAR2
);
output VAR10 ;
input VAR6;
input VAR7;
input VAR1;
input VAR4;
input VAR2;
wire VAR8 ;
wire VAR9;
or VAR5 (VAR8 , VAR7, VAR6, VAR1 );
nand VAR3 (VAR9, VAR2, VAR8, VAR4);
buf VAR11 (VAR10 , VAR9 );
endmodule | apache-2.0 |
olofk/oh | elink/hdl/erx_arbiter.v | 3,957 | module MODULE1 (
VAR8, VAR17, VAR11, VAR5, VAR21,
VAR20, VAR2, VAR6, VAR12, VAR23,
VAR26, VAR16, VAR25, VAR24, VAR18,
VAR22, VAR4, VAR13, timeout, VAR17,
VAR8, VAR7
);
parameter VAR10 = 32;
parameter VAR19 = 32;
parameter VAR3 = 104;
parameter VAR1 = 12'h800; parameter VAR14 = 6;
input VAR26;
input [VAR3-1:0] VAR16;
ou... | gpl-3.0 |
bkboggy/MIPS | I_DECODE.v | 2,206 | module MODULE1(
input clk, VAR43,
input [31:0] VAR2, VAR34,
input [4:0] VAR38,
input [31:0] VAR47,
output [1:0] VAR10,
output [2:0] VAR31,
output [3:0] VAR16,
output [31:0] VAR11,
output [31:0] VAR25,
output [31:0] VAR7,
output [31:0] VAR35,
output [4:0] VAR18,
output [4:0] VAR44,
output [4:0] VAR48
);
wire [1:0] VAR29... | mit |
hanw/sonic-lite | hw/verilog/enc_dec/xgmii_loopback.v | 3,772 | module MODULE1 (
VAR1,
VAR19,
sel,
VAR13);
input [65:0] VAR1;
input [65:0] VAR19;
input sel;
output [65:0] VAR13;
wire [65:0] VAR20;
wire [65:0] VAR7 = VAR19[65:0];
wire [65:0] VAR13 = VAR20[65:0];
wire [65:0] VAR6 = VAR1[65:0];
wire [131:0] VAR5 = {VAR7, VAR6};
wire VAR12 = sel;
wire VAR16 = VAR12;
VAR17 VAR4 (
.VAR8 ... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_l2d_32k.v | 14,497 | module MODULE1 (
VAR16, VAR45, VAR27,
VAR74, VAR58, VAR75, VAR68, VAR22,
VAR41, VAR30, VAR35, VAR1, VAR34,
VAR29, VAR63, VAR11, VAR5, VAR38,
VAR50, VAR62, VAR25,
VAR46, VAR40
);
input [155:0] VAR74;
input [155:0] VAR58;
input [3:0] VAR75;
input [1:0] VAR68;
input [9:0] VAR22;
input VAR41;
input VAR30;
input VAR35;
inpu... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fme/fme_pred.v | 7,851 | module MODULE1 (
clk ,
VAR47 ,
VAR43 ,
VAR2 ,
VAR1 ,
VAR15 ,
VAR21 ,
VAR14 ,
VAR41 ,
VAR7 ,
VAR11 ,
VAR32 ,
VAR40 ,
VAR26 ,
VAR42 ,
VAR8 ,
VAR33 ,
VAR24 ,
VAR17 ,
VAR31 ,
VAR18 ,
VAR46 ,
VAR16 ,
VAR5 ,
VAR34 ,
VAR22 ,
VAR4 ,
VAR29 ,
VAR12 ,
VAR30
);
input [1-1:0] clk ; input [1-1:0] VAR47 ; input [1-1:0] VAR43 ; input ... | gpl-3.0 |
neale/CS-program | 474-VLSI/UART/Conversion_ROM.v | 6,465 | module MODULE1 (
address,
VAR29,
VAR4);
input [11:0] address;
input VAR29;
output [11:0] VAR4;
tri1 VAR29;
wire [11:0] VAR2;
wire [11:0] VAR4 = VAR2[11:0];
VAR42 VAR53 (
.VAR44 (address),
.VAR14 (VAR29),
.VAR30 (VAR2),
.VAR22 (1'b0),
.VAR43 (1'b0),
.VAR17 (1'b1),
.VAR51 (1'b0),
.VAR34 (1'b0),
.VAR11 (1'b1),
.VAR38 (1'b... | unlicense |
pollow/Multi_Cycle_CPU | src/comps.v | 9,667 | module MODULE1(
clk,
VAR4,
VAR1
);
input clk;
input VAR4;
output VAR1;
reg VAR5;
reg [31:0]VAR3, VAR2; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41oi/sky130_fd_sc_hd__a41oi.pp.blackbox.v | 1,423 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR8 ,
VAR10 ,
VAR1 ,
VAR7 ,
VAR4,
VAR2,
VAR9 ,
VAR5
);
output VAR6 ;
input VAR3 ;
input VAR8 ;
input VAR10 ;
input VAR1 ;
input VAR7 ;
input VAR4;
input VAR2;
input VAR9 ;
input VAR5 ;
endmodule | apache-2.0 |
kramble/FPGA-Litecoin-Miner | experimental/LX150-SPLIT/ltcminer_icarus.v | 7,683 | module MODULE1 (VAR70, VAR79, VAR40, VAR85, VAR71, VAR6, VAR18, VAR49, VAR74, VAR61);
parameter VAR9 = VAR9;
parameter VAR9 = 25;
parameter VAR45 = VAR7;
parameter VAR45 = 12500000; VAR12
parameter VAR78 = VAR78;
parameter VAR78 = 115200;
input VAR70;
wire VAR25, VAR24;
VAR46 # (.VAR9(VAR9)) VAR38 (.VAR86(VAR70), .VAR1... | gpl-3.0 |
freecores/raggedstone | source/pcidec.v | 1,504 | module MODULE1 (VAR4, VAR12, VAR7, VAR5, VAR1, VAR6, VAR10,
VAR2, VAR8, VAR9, VAR16, VAR11);
input VAR4;
input VAR12;
input [31:0] VAR7;
input [3:0] VAR5;
input VAR1;
input [31:25] VAR6;
input VAR10;
input VAR2;
output VAR8;
output VAR9;
output [24:1] VAR16;
output [3:0] VAR11;
reg [31:0] VAR3;
reg [3:0] VAR14;
reg VAR... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Lundgren FPU/tags/arelease/pipeline/fpu_mul.v | 13,931 | module MODULE1( clk, rst, enable, VAR151, VAR42, VAR131, ready, VAR54);
input clk;
input rst;
input enable;
input [1:0] VAR151;
input [63:0] VAR42, VAR131;
output ready;
output [63:0] VAR54;
reg VAR166;
reg [1:0] VAR170, VAR141, VAR144, VAR117, VAR113, VAR164, VAR22, VAR36, VAR169;
reg [1:0] VAR116, VAR57, VAR76, VAR11... | gpl-3.0 |
P3Stor/P3Stor | pcie/app/BAR1_WR_ARBITER.v | 4,041 | module MODULE1 (
VAR5,
VAR3,
VAR8,
VAR25,
VAR24,
VAR29,
VAR27,
VAR20,
VAR23,
VAR26,
VAR14,
VAR19,
VAR31,
VAR28,
VAR9,
VAR6,
VAR7,
VAR22,
VAR15,
VAR2,
VAR30,
VAR11,
VAR10,
VAR13,
VAR17,
VAR12,
VAR18,
VAR21,
VAR1,
VAR4,
VAR16
);
input VAR5;
input VAR3;
input VAR8;
input [6:0] VAR25;
input [3:0] VAR24;
input [31:0] VAR29;... | gpl-2.0 |
ejk43/rfnoc-neuralnet | rfnoc/fpga-src/nnet_vector_wrapper.v | 3,522 | module MODULE1 #(
parameter VAR40 = 16,
parameter VAR19 = 128,
parameter VAR14 = 3
)(
input clk, input reset, input VAR27,
input [15:0] VAR26,
input [15:0] VAR11, VAR12,
input [2*VAR40-1:0] VAR1, input VAR10, input VAR38, output VAR15, input [VAR19-1:0] VAR2,
output [2*VAR40-1:0] VAR39, output VAR6, output VAR7, input ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux4/sky130_fd_sc_lp__mux4_4.v | 2,444 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR6 ,
VAR2 ,
VAR9 ,
VAR4 ,
VAR5 ,
VAR10,
VAR7,
VAR1 ,
VAR3
);
output VAR8 ;
input VAR11 ;
input VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR4 ;
input VAR5 ;
input VAR10;
input VAR7;
input VAR1 ;
input VAR3 ;
VAR13 VAR12 (
.VAR8(VAR8),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
... | apache-2.0 |
terriblefire/tf530 | rtl/tf530bus/tf530_bus.v | 6,578 | module MODULE1(
input VAR40,
input VAR14,
input VAR24,
input [2:0] VAR2,
input [1:0] VAR9,
input VAR28,
input [23:12] VAR13,
input VAR8,
input VAR18,
input VAR3,
output [1:0] VAR10,
output VAR27,
output VAR30,
output VAR21,
input VAR22,
input VAR7,
output [1:0] VAR17, output VAR29, output VAR32, output VAR41,
output VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfsbp/sky130_fd_sc_ls__dfsbp.pp.symbol.v | 1,412 | module MODULE1 (
input VAR4 ,
output VAR2 ,
output VAR7 ,
input VAR8,
input VAR1 ,
input VAR9 ,
input VAR3 ,
input VAR5 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.v | 2,474 | module MODULE2 (
VAR10 ,
VAR1 ,
VAR4,
VAR3 ,
VAR8 ,
VAR6 ,
VAR5 ,
VAR7 ,
VAR2
);
output VAR10 ;
output VAR1 ;
input VAR4;
input VAR3 ;
input VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR2 ;
VAR9 VAR11 (
.VAR10(VAR10),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.... | apache-2.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_sysid.v | 1,415 | module MODULE1 (
address,
VAR1,
VAR2,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR1;
input VAR2;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1413429550 : -252645136;
endmodule | mit |
megari/sd2snes | verilog/sd2snes/main.v | 23,017 | module MODULE1(
input VAR358,
input [23:0] VAR190,
input VAR135,
input VAR181,
input VAR366,
inout [7:0] VAR134,
input VAR343,
input VAR15,
output VAR109,
output VAR244,
output VAR76,
input VAR152,
input [7:0] VAR176,
input VAR267,
input VAR172,
inout [15:0] VAR290,
output [22:0] VAR370,
output VAR85,
output VAR50,
out... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/softusb/rtl/softusb_dpram_11_16.v | 36,665 | module MODULE1 (
clk, VAR20, VAR1, VAR149, VAR113, VAR37, do, VAR95, VAR131, VAR106, VAR123
);
input clk;
input VAR20;
input VAR1;
input VAR149;
input VAR113;
output [15 : 0] VAR37;
output [15 : 0] do;
input [15 : 0] VAR95;
input [10 : 0] VAR131;
input [10 : 0] VAR106;
input [15 : 0] VAR123;
wire VAR71;
wire VAR68;
wir... | lgpl-3.0 |
titorgalaxy/Titor | rtl/verilog/core/Preshift.v | 2,998 | module MODULE1 (
VAR2,
VAR6,
VAR20,
VAR7,
VAR13,
VAR18,
VAR10,
VAR1,
VAR19,
VAR15,
VAR4,
VAR11,
VAR14,
enable
);
output reg [VAR17-1:0] VAR2; output reg [VAR17-1:0] VAR6; output reg [VAR17-1:0] VAR20; output reg [VAR17-1:0] VAR7;
input [VAR17-1:0] VAR13; input [VAR17-1:0] VAR18; input [VAR17-1:0] VAR10; input [VAR17-1:... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/triple_speed_ethernet-library/altera_tse_rgmii_in1.v | 4,277 | module MODULE1 (
VAR17,
VAR5,
VAR18,
VAR22,
VAR6);
input VAR17;
input VAR5;
input VAR18;
output VAR22;
output VAR6;
wire [0:0] VAR7;
wire [0:0] VAR20;
wire [0:0] VAR21 = VAR7[0:0];
wire VAR22 = VAR21;
wire [0:0] VAR12 = VAR20[0:0];
wire VAR6 = VAR12;
wire VAR2 = VAR5;
wire VAR10 = VAR2;
VAR14 VAR19 (
.VAR5 (VAR10),
.VA... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/sequencer_scc_reg_file.v | 2,545 | module MODULE1 (
VAR23,
VAR21,
VAR14,
VAR11,
VAR44,
VAR2);
parameter VAR24 = "";
parameter VAR3 = "";
input VAR23;
input [VAR24-1:0] VAR21;
input [VAR3-1:0] VAR14;
input [VAR3-1:0] VAR11;
input VAR44;
output [VAR24-1:0] VAR2;
tri0 VAR44;
wire [VAR24-1:0] VAR41;
wire [VAR24-1:0] VAR2 = VAR41[VAR24-1:0];
VAR42 VAR27 (
.V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2i/sky130_fd_sc_ls__mux2i_2.v | 2,214 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR8 ,
VAR10 ,
VAR4,
VAR6,
VAR2 ,
VAR3
);
output VAR1 ;
input VAR5 ;
input VAR8 ;
input VAR10 ;
input VAR4;
input VAR6;
input VAR2 ;
input VAR3 ;
VAR9 VAR7 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
asicguy/gplgpu | hdl/vga/cpu_rd.v | 5,284 | module MODULE1
(
input VAR20,
input VAR6,
input VAR32,
input VAR35,
input VAR28,
input VAR14,
input VAR19,
input VAR3,
input VAR29,
input VAR1,
input VAR33,
input [31:0] VAR31,
output reg VAR25,
output reg VAR34,
output reg [31:0] VAR16,
output VAR9,
output reg VAR8,
output reg VAR13,
output VAR7
);
reg VAR11;
reg VAR3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvp/sky130_fd_sc_hd__einvp_8.v | 2,130 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR9 ,
VAR3,
VAR6,
VAR4 ,
VAR8
);
output VAR1 ;
input VAR2 ;
input VAR9 ;
input VAR3;
input VAR6;
input VAR4 ;
input VAR8 ;
VAR7 VAR5 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR1 ,
VAR2 ,
VAR9
);
output VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxtp/sky130_fd_sc_hs__edfxtp.pp.symbol.v | 1,389 | module MODULE1 (
input VAR3 ,
output VAR6 ,
input VAR2 ,
input VAR1 ,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufbuf/sky130_fd_sc_lp__bufbuf.behavioral.pp.v | 1,768 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR3,
VAR10,
VAR1 ,
VAR8
);
output VAR4 ;
input VAR5 ;
input VAR3;
input VAR10;
input VAR1 ;
input VAR8 ;
wire VAR7 ;
wire VAR12;
buf VAR9 (VAR7 , VAR5 );
VAR11 VAR6 (VAR12, VAR7, VAR3, VAR10);
buf VAR2 (VAR4 , VAR12 );
endmodule | apache-2.0 |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodALS_v1_0/src/PmodALS.v | 10,442 | module MODULE1
(VAR39,
VAR76,
VAR168,
VAR9,
VAR114,
VAR157,
VAR52,
VAR111,
VAR37,
VAR117,
VAR156,
VAR65,
VAR155,
VAR127,
VAR94,
VAR161,
VAR97,
VAR55,
VAR30,
VAR61,
VAR129,
VAR110,
VAR69,
VAR100,
VAR77,
VAR49,
VAR123,
VAR135,
VAR165,
VAR92,
VAR139,
VAR28,
VAR4,
VAR35,
VAR57,
VAR164,
VAR120,
VAR58,
VAR167,
VAR163,
VAR48,... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s.pp.blackbox.v | 1,345 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR2,
VAR3,
VAR4 ,
VAR6
);
output VAR5 ;
input VAR1 ;
input VAR2;
input VAR3;
input VAR4 ;
input VAR6 ;
endmodule | apache-2.0 |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_2/synth/design_1_auto_pc_2.v | 13,287 | module MODULE1 (
VAR64,
VAR95,
VAR39,
VAR49,
VAR93,
VAR23,
VAR99,
VAR67,
VAR72,
VAR104,
VAR36,
VAR14,
VAR85,
VAR73,
VAR75,
VAR20,
VAR25,
VAR40,
VAR60,
VAR103,
VAR22,
VAR63,
VAR9,
VAR101,
VAR26,
VAR53,
VAR5,
VAR45,
VAR10,
VAR12,
VAR107,
VAR112,
VAR108,
VAR94,
VAR13,
VAR34,
VAR30,
VAR110,
VAR81,
VAR113,
VAR100,
VAR83,
VA... | gpl-3.0 |
QuantumQuadrate/HamamatsuCameralink | camera_serial_command_generator.v | 8,514 | module MODULE1
(
VAR50,
VAR34,
VAR46,
VAR43,
VAR23,
VAR5,
VAR40,
VAR22,
VAR39,
rst,
VAR12,
VAR51,
VAR42,
VAR21
);
input VAR50;
input VAR34;
input VAR46;
input VAR39;
input rst;
input VAR5;
output [7:0] VAR43;
output VAR23;
input [7:0] VAR40;
input VAR22;
output VAR12;
output [4:0] VAR51;
output [3:0] VAR42;
output [7:0... | bsd-3-clause |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/lsu_enabled.v | 8,196 | module MODULE1
(
clk, reset, VAR2, VAR34, VAR30, VAR26, VAR25, VAR14, VAR4,
VAR19, VAR28, VAR8, VAR9, VAR33, VAR39, VAR1,
VAR24,
VAR32
);
parameter VAR13=32; parameter VAR36=4; parameter VAR37=32; parameter VAR31=2; parameter VAR27=32; parameter VAR12=6;
localparam VAR3=2**(VAR12-1);
localparam VAR16=8*VAR36;
localpara... | mit |
tloinuy/opencpi-opencv | opencpi/components/framegate.hdl/framegate.v | 64,609 | module MODULE1(VAR30,
VAR278,
VAR150,
VAR109,
VAR242,
VAR182,
VAR318,
VAR365,
VAR116,
VAR368,
VAR326,
VAR358,
VAR66,
VAR389,
VAR172,
VAR260,
VAR402,
VAR284,
VAR398,
VAR298,
VAR142,
VAR47,
VAR433,
VAR165,
VAR13,
VAR383,
VAR72,
VAR345,
VAR233,
VAR102,
VAR377,
VAR99);
parameter [31 : 0] VAR386 = 32'b0;
parameter [0 : 0] V... | gpl-2.0 |
olajep/oh | src/adi/hdl/library/axi_dmac/2d_transfer.v | 6,422 | module MODULE1 #(
parameter VAR46 = 32,
parameter VAR42 = 24,
parameter VAR35 = 7,
parameter VAR19 = 3,
parameter VAR17 = 3)(
input VAR38,
input VAR22,
input VAR15,
output reg VAR26,
input [VAR46-1:VAR17] VAR10,
input [VAR46-1:VAR19] VAR11,
input [VAR42-1:0] VAR43,
input [VAR42-1:0] VAR7,
input [VAR42-1:0] VAR45,
input... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4/sky130_fd_sc_hd__nand4.functional.pp.v | 1,846 | module MODULE1 (
VAR13 ,
VAR7 ,
VAR6 ,
VAR9 ,
VAR2 ,
VAR1,
VAR11,
VAR3 ,
VAR15
);
output VAR13 ;
input VAR7 ;
input VAR6 ;
input VAR9 ;
input VAR2 ;
input VAR1;
input VAR11;
input VAR3 ;
input VAR15 ;
wire VAR5 ;
wire VAR10;
nand VAR8 (VAR5 , VAR2, VAR9, VAR6, VAR7 );
VAR12 VAR14 (VAR10, VAR5, VAR1, VAR11);
buf VAR4 (V... | apache-2.0 |
olajep/oh | src/adi/hdl/library/xilinx/common/ad_mul.v | 2,977 | module MODULE1 #(
parameter VAR20 = 17,
parameter VAR16 = 17,
parameter VAR10 = 16) (
input clk,
input [ VAR20-1:0] VAR18,
input [ VAR16-1:0] VAR4,
output [VAR20 + VAR16-1:0] VAR3,
input [(VAR10-1):0] VAR13,
output reg [(VAR10-1):0] VAR8);
reg [(VAR10-1):0] VAR2 = 'd0;
reg [(VAR10-1):0] VAR12 = 'd0;
always @(posedge cl... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31ai/sky130_fd_sc_ms__o31ai.behavioral.pp.v | 2,027 | module MODULE1 (
VAR15 ,
VAR4 ,
VAR11 ,
VAR10 ,
VAR16 ,
VAR1,
VAR14,
VAR12 ,
VAR8
);
output VAR15 ;
input VAR4 ;
input VAR11 ;
input VAR10 ;
input VAR16 ;
input VAR1;
input VAR14;
input VAR12 ;
input VAR8 ;
wire VAR7 ;
wire VAR17 ;
wire VAR3;
or VAR13 (VAR7 , VAR11, VAR4, VAR10 );
nand VAR2 (VAR17 , VAR16, VAR7 );
VAR5... | apache-2.0 |
mbus/mbus | m3_mbus_releases/r04p2g/source/lname_mbus_member_ctrl.v | 5,532 | module MODULE1 (
input VAR18,
input VAR36,
input VAR13,
input VAR27,
input VAR12,
output reg VAR19,
output reg VAR24,
input VAR37,
input VAR2,
output reg VAR23,
output VAR10,
output reg VAR7,
output VAR34,
output reg VAR1,
output VAR30,
input VAR26,
output reg VAR3,
input VAR32,
input VAR33,
input [VAR22-1:0] VAR25,
ou... | apache-2.0 |
marqs85/de2-vd | rtl/ir_rcv.v | 4,530 | module MODULE1 (
input VAR12,
input VAR2,
input VAR16,
output reg [31:0] VAR13,
output reg VAR9
);
parameter VAR1 = 230000; parameter VAR19 = 210000; parameter VAR11 = 105000; parameter VAR8 = 6000000; parameter VAR15 = 41500; parameter VAR18 = 20000; parameter VAR10 = 262143;
reg [1:0] state; reg [31:0] VAR6; reg [5:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufbuf/sky130_fd_sc_hs__bufbuf.behavioral.pp.v | 1,666 | module MODULE1 (
VAR3,
VAR1,
VAR7 ,
VAR5
);
input VAR3;
input VAR1;
output VAR7 ;
input VAR5 ;
wire VAR2 ;
wire VAR8;
buf VAR4 (VAR2 , VAR5 );
VAR9 VAR6 (VAR8, VAR2, VAR3, VAR1);
buf VAR10 (VAR7 , VAR8 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_impctl_clsm.v | 34,105 | module MODULE1(clk ,VAR21 ,VAR293 ,VAR16 ,VAR112 ,VAR326 ,
VAR106 ,VAR12 ,VAR258 ,VAR39 ,VAR101 ,VAR268 ,VAR318
,VAR98 ,VAR72 ,VAR204 ,VAR230 ,VAR323 ,VAR241 ,VAR9 );
output [7:0] VAR16 ;
output [7:0] VAR112 ;
output [7:0] VAR12 ;
input [7:0] VAR293 ;
input [7:0] VAR106 ;
output VAR21 ;
output VAR230 ;
input clk ;
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22o/sky130_fd_sc_hdll__a22o.blackbox.v | 1,364 | module MODULE1 (
VAR3 ,
VAR5,
VAR6,
VAR8,
VAR7
);
output VAR3 ;
input VAR5;
input VAR6;
input VAR8;
input VAR7;
supply1 VAR9;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GDA_St_N16_M4_P8_syn.v | 4,053 | module MODULE1 ( VAR56, VAR104, VAR41 );
input [15:0] VAR56;
input [15:0] VAR104;
output [16:0] VAR41;
wire VAR71, VAR72, VAR32, VAR58, VAR43,
VAR17, VAR5, VAR12, VAR16, VAR26, VAR121, VAR36, VAR125,
VAR40, VAR8, VAR124, VAR112, VAR89, VAR21, VAR117, VAR64, VAR73, VAR130, VAR101, VAR135, VAR129, VAR103,
VAR114, VAR98, ... | gpl-3.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkTLB.v | 30,931 | module MODULE1(VAR138,
VAR185,
VAR179,
VAR21,
VAR7,
VAR192,
VAR26,
VAR153,
VAR155,
VAR147,
VAR52,
VAR15,
VAR163,
VAR128,
VAR28);
parameter [0 : 0] VAR134 = 1'b0;
input VAR138;
input VAR185;
input VAR179;
output VAR21;
input [15 : 0] VAR7;
input [26 : 0] VAR192;
output [130 : 0] VAR26;
output VAR153;
input [15 : 0] VAR1... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9434_v1_00_a/hdl/verilog/axi_ad9434_if.v | 9,047 | module MODULE1 (
VAR30,
VAR5,
VAR3,
VAR11,
VAR59,
VAR49,
VAR70,
VAR20,
VAR10,
VAR79,
VAR82,
VAR53,
VAR78,
VAR41,
VAR48,
VAR33,
VAR42,
VAR52,
VAR19,
VAR50);
parameter VAR54 = 0;
parameter VAR23 = "VAR76";
localparam VAR51 = 0;
localparam VAR1 = 1;
input VAR30;
input VAR5;
input [11:0] VAR3;
input [11:0] VAR11;
input VAR... | mit |
m-labs/milkymist | cores/conbus/rtl/conbus5x6.v | 7,152 | module MODULE1 #(
parameter VAR15 = 3'b000,
parameter VAR85 = 3'b001,
parameter VAR27 = 3'b010,
parameter VAR83 = 3'b011,
parameter VAR84 = 2'b10,
parameter VAR100 = 2'b11
) (
input VAR80,
input VAR53,
input [31:0] VAR82,
output [31:0] VAR57,
input [31:0] VAR13,
input [2:0] VAR115,
input [3:0] VAR107,
input VAR65,
inpu... | lgpl-3.0 |
Digilent/vivado-library | ip/PWM_Analyzer_1.0/hdl/PWM_Analyzer_v1_0.v | 2,501 | module MODULE1 #
(
parameter integer VAR15 = 32,
parameter integer VAR5 = 4
)
(
input wire VAR4,
input wire VAR16,
input wire VAR38,
input wire [VAR5-1 : 0] VAR7,
input wire [2 : 0] VAR44,
input wire VAR43,
output wire VAR8,
input wire [VAR15-1 : 0] VAR35,
input wire [(VAR15/8)-1 : 0] VAR18,
input wire VAR1,
output wir... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_2.behavioral.pp.v | 1,561 | module MODULE1( VAR7, VAR5, VAR1, VAR4, VAR8, VAR6 );
input VAR4, VAR1, VAR7;
inout VAR8, VAR6;
output VAR5;
VAR3 VAR2(.VAR7(VAR7),.VAR5(VAR5),.VAR1(VAR1),.VAR4(VAR4),.VAR8(VAR8),.VAR6(VAR6));
VAR3 VAR9(.VAR7(VAR7),.VAR5(VAR5),.VAR1(VAR1),.VAR4(VAR4),.VAR8(VAR8),.VAR6(VAR6)); | apache-2.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/system/interrupt_controller.v | 13,016 | module MODULE4 #(
parameter VAR32 = 32,
parameter VAR64 = 4
)(
input VAR53,
input [31:0] VAR37,
input [VAR64-1:0] VAR62,
input VAR74,
output [VAR32-1:0] VAR35,
input [VAR32-1:0] VAR78,
input VAR66,
input VAR48,
output VAR57,
output VAR71,
output VAR17,
output VAR40,
input VAR69,
input VAR28,
input VAR11,
input VAR36,
i... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux4/sky130_fd_sc_ms__mux4.functional.pp.v | 1,983 | module MODULE1 (
VAR18 ,
VAR9 ,
VAR1 ,
VAR7 ,
VAR2 ,
VAR17 ,
VAR8 ,
VAR5,
VAR16,
VAR11 ,
VAR15
);
output VAR18 ;
input VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR17 ;
input VAR8 ;
input VAR5;
input VAR16;
input VAR11 ;
input VAR15 ;
wire VAR12 ;
wire VAR6;
VAR10 VAR14 (VAR12 , VAR9, VAR1, VAR7, VAR2, VAR17,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2.behavioral.pp.v | 1,733 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR5,
VAR1
);
output VAR6 ;
input VAR10 ;
input VAR5;
input VAR1;
wire VAR3 ;
wire VAR4;
buf VAR2 (VAR3 , VAR10 );
VAR9 VAR8 (VAR4, VAR3, VAR5, VAR1);
buf VAR7 (VAR6 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp.behavioral.v | 2,530 | module MODULE1 (
VAR18,
VAR20 ,
VAR16,
VAR4
);
output VAR18;
input VAR20 ;
input VAR16;
input VAR4 ;
supply1 VAR24;
supply0 VAR13;
supply1 VAR19 ;
supply0 VAR22 ;
wire VAR3 ;
wire VAR21 ;
wire VAR12 ;
wire VAR15 ;
wire VAR14 ;
wire VAR8 ;
wire VAR7;
reg VAR23 ;
wire VAR5 ;
wire VAR1 ;
wire VAR2 ;
not VAR9 (VAR21 , VAR3... | apache-2.0 |
fbalakirev/red-pitaya-notes | projects/red_pitaya_0_92/red_pitaya_pid.v | 12,135 | module MODULE1
(
input VAR7 , input VAR13 , input [ 14-1: 0] VAR51 , input [ 14-1: 0] VAR54 , output [ 14-1: 0] VAR21 , output [ 14-1: 0] VAR44 ,
input VAR47 , input VAR2 , input [ 32-1: 0] VAR55 , input [ 32-1: 0] VAR24 , input [ 4-1: 0] VAR62 , input VAR29 , input VAR12 , output [ 32-1: 0] VAR5 , output VAR42 , outpu... | mit |
cynngah/virtualsynthesizer | sound_files/Altera_UP_I2C.v | 11,287 | module MODULE1 (
clk,
reset,
VAR18,
VAR14,
VAR10,
VAR26,
VAR17,
VAR9,
VAR13,
VAR8,
VAR27,
VAR23,
VAR22,
VAR19,
VAR11,
VAR12,
ack,
VAR28,
VAR7
);
parameter VAR20 = 1'b0;
input clk;
input reset;
input VAR18;
input VAR14;
input VAR10;
input VAR26;
input VAR17;
input VAR9;
input [7:0] VAR13;
input VAR8;
input VAR27;
input ... | mit |
hcabrera-/lancetfish | RTL/processing_element/des_engine/rtl/des_sbox1.v | 3,552 | module MODULE1
(
input wire [0:5] VAR1,
output reg [0:3] VAR2
);
always @(*)
case ({VAR1[0], VAR1[5]})
2'b00:
case (VAR1[1:4])
4'd0: VAR2 = 4'd14;
4'd1: VAR2 = 4'd4;
4'd2: VAR2 = 4'd13;
4'd3: VAR2 = 4'd1;
4'd4: VAR2 = 4'd2;
4'd5: VAR2 = 4'd15;
4'd6: VAR2 = 4'd11;
4'd7: VAR2 = 4'd8;
4'd8: VAR2 = 4'd3;
4'd9: VAR2 = 4'd10... | gpl-3.0 |
lvd2/ngs | fpga/obsolete/fpgaE_dma/ports/ports.v | 14,464 | module MODULE1(
din, dout, VAR113, VAR28,
VAR9,VAR44,VAR35,VAR16,
VAR3, VAR58, VAR39,
VAR62, VAR99,
VAR119, VAR56,
VAR85, VAR98,
VAR97, VAR112,
VAR95, VAR71,
VAR27, VAR26,
VAR72, VAR68,
VAR64, VAR116, VAR1, VAR34,
VAR67, VAR66,
VAR63,
VAR75,
VAR20, VAR103,
VAR11,
VAR77,
VAR107,
VAR76,
VAR51,
VAR6, VAR120,
VAR23,
VAR60,... | gpl-3.0 |
bargei/NoC264 | NoC264_2x2/module_gen_grant_carry.v | 2,685 | module MODULE1(VAR4,
VAR1,
VAR3,
VAR2);
input VAR4;
input VAR1;
input VAR3;
output [1 : 0] VAR2;
wire [1 : 0] VAR2;
assign VAR2 =
{ VAR1 && (VAR4 || VAR3),
!VAR1 &&
(VAR4 || VAR3) } ;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31a/sky130_fd_sc_hs__o31a.pp.symbol.v | 1,318 | module MODULE1 (
input VAR3 ,
input VAR6 ,
input VAR2 ,
input VAR4 ,
output VAR1 ,
input VAR7,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3b/sky130_fd_sc_hd__nand3b.behavioral.v | 1,497 | module MODULE1 (
VAR10 ,
VAR5,
VAR12 ,
VAR9
);
output VAR10 ;
input VAR5;
input VAR12 ;
input VAR9 ;
supply1 VAR3;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR8 ;
wire VAR13 ;
wire VAR7;
not VAR11 (VAR13 , VAR5 );
nand VAR1 (VAR7, VAR12, VAR13, VAR9 );
buf VAR2 (VAR10 , VAR7 );
endmodule | apache-2.0 |
bargei/NoC264 | NoC264_3x3/module_gen_grant_carry.v | 2,685 | module MODULE1(VAR3,
VAR2,
VAR4,
VAR1);
input VAR3;
input VAR2;
input VAR4;
output [1 : 0] VAR1;
wire [1 : 0] VAR1;
assign VAR1 =
{ VAR2 && (VAR3 || VAR4),
!VAR2 &&
(VAR3 || VAR4) } ;
endmodule | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_MinMax.v | 1,702 | module MODULE1
(
VAR7,
VAR2,
VAR1,
VAR5
);
input signed [17:0] VAR7; input signed [17:0] VAR2; input signed [17:0] VAR1; output signed [17:0] VAR5;
wire signed [17:0] VAR6 [0:2]; wire signed [17:0] VAR3 [0:1]; wire signed [17:0] VAR4;
assign VAR6[0] = VAR7;
assign VAR6[1] = VAR2;
assign VAR6[2] = VAR1;
assign VAR3[0] =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp.behavioral.pp.v | 2,531 | module MODULE1 (
VAR18 ,
VAR6 ,
VAR5 ,
VAR22 ,
VAR1 ,
VAR24 ,
VAR26,
VAR15,
VAR17 ,
VAR4
);
output VAR18 ;
output VAR6 ;
input VAR5 ;
input VAR22 ;
input VAR1 ;
input VAR24 ;
input VAR26;
input VAR15;
input VAR17 ;
input VAR4 ;
wire VAR23 ;
wire VAR25 ;
reg VAR12 ;
wire VAR19 ;
wire VAR20;
wire VAR13;
wire VAR9;
wire V... | apache-2.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab08/lab08/Code/CPU/ARM_Int.v | 1,792 | module MODULE1(input wire clk,
input wire reset,
input wire VAR1,
input wire VAR3,
input wire[31:0] VAR2,
output reg [31:0] VAR4
);
reg VAR5=0,VAR8=0,VAR7=1;
reg [31:0] VAR6;
assign VAR9 = reset|VAR5; always @(posedge VAR1 or posedge VAR9 )begin if(VAR9==1 )VAR8<=0; else VAR8<=1; end
always @(posedge clk or posedge res... | gpl-3.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_static_mrdwr.v | 30,031 | module MODULE1 #
(
parameter VAR60 = 1 ,
parameter VAR77 = 8 ,
parameter VAR41 = 8 ,
parameter VAR5 = 32'h12A00000 ,
parameter VAR10 = 32'h13A00000 ,
parameter VAR123 = 32'h12A00FFF ,
parameter VAR19 = 32'h13A00FFF ,
parameter VAR38 = 0 ,
parameter VAR104 = 1 ,
parameter VAR78 = 1 ,
parameter VAR118 = 5 ,
parameter VAR... | mit |
martinmiranda14/Digitales | Lab_6/p_5_new/project_5/project_5.srcs/sources_1/new/Ps2display.v | 4,015 | module MODULE1(
input VAR14,
input VAR50,
input VAR62,
input VAR49,
output [7:0] VAR26,
output VAR4,VAR40,VAR7,VAR30,VAR33,VAR46,VAR57,VAR5,
output [31:0] VAR45,
input [3:0] VAR17,
input [3:0] VAR21
);
wire reset;
wire VAR29;
wire VAR12;
wire [7:0] VAR59;
wire [2:0] VAR31;
wire [4:0] VAR58;
wire [2:0] VAR19;
wire VAR18... | apache-2.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CORESPI/4.2.116/rtl/vlog/core/spi_fifo.v | 6,678 | module MODULE1( VAR8,
VAR19,
VAR18,
VAR6,
VAR4,
VAR26,
VAR27,
VAR15,
VAR11,
VAR10,
VAR13,
VAR7,
VAR5,
VAR14,
VAR16
);
parameter VAR21 = 4; parameter VAR28 = 4;
input VAR8;
input VAR19;
input VAR18;
input [VAR21-1:0] VAR6;
input VAR15;
input VAR11;
input VAR4;
output [VAR21-1:0] VAR26;
output VAR13;
output VAR10;
output... | mit |
merckhung/zet | cores/vdu/rtl/vdu_ram_2k_char.v | 1,248 | module MODULE1 (
input clk,
input rst,
input VAR1,
input [10:0] addr,
output [ 7:0] VAR5,
input [ 7:0] VAR2
);
reg [ 7:0] VAR4[0:2047];
reg [10:0] VAR3;
always @(posedge clk)
begin
if (VAR1) VAR4[addr] <= VAR2;
VAR3 <= addr;
end
assign VAR5 = VAR4[VAR3]; | gpl-3.0 |
chenm001/connectal | verilog/PositiveReset.v | 2,949 | module MODULE1 (
VAR5,
VAR4,
VAR8
);
parameter VAR9 = 1 ;
input VAR4 ;
input VAR5 ;
output VAR8 ;
reg VAR2 ;
reg [VAR9:1] VAR1 ;
wire [VAR9+1:0] VAR3 = {VAR1, VAR2, 1'b0} ;
assign VAR8 = VAR1[VAR9] ;
always @( posedge VAR4 ) begin
if (VAR5 == VAR6)
begin
VAR2 <= 1;
end
else
begin
VAR2 <= 0;
end
if (VAR2 == 1)
begin
VAR... | mit |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_alu_out.v | 1,943 | module MODULE1 (
address,
clk,
VAR6,
VAR4,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 31: 0] VAR6;
input VAR4;
wire VAR5;
wire [ 31: 0] VAR3;
wire [ 31: 0] VAR2;
reg [ 31: 0] VAR1;
assign VAR5 = 1;
assign VAR2 = {32 {(address == 0)}} & VAR3;
always @(posedge clk or negedge VAR4)
begin
if (... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr.pp.blackbox.v | 1,334 | module MODULE1 (
VAR4 ,
VAR1,
VAR2 ,
VAR3 ,
VAR5
);
input VAR4 ;
input VAR1;
input VAR2 ;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/m32632/TOP_MISC.v | 5,803 | module MODULE1 ( VAR21, VAR15, VAR25, VAR1, VAR19, VAR32, VAR47, VAR23, VAR16, VAR33, VAR40, VAR46,
VAR37, VAR5, VAR2, VAR36, VAR14, VAR20, VAR31, VAR45 );
input VAR21,VAR15;
input [31:0] VAR25,VAR1;
input VAR19;
input VAR32,VAR47;
input [3:0] VAR33;
input VAR23;
input [2:0] VAR16;
input VAR40;
input [1:0] VAR46;
outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxbp/sky130_fd_sc_ls__dfxbp.pp.symbol.v | 1,336 | module MODULE1 (
input VAR1 ,
output VAR8 ,
output VAR3 ,
input VAR2 ,
input VAR5 ,
input VAR6,
input VAR7,
input VAR4
);
endmodule | apache-2.0 |
sundw2014/carADS | fpga_firmware/mainlogic.v | 1,324 | module MODULE1(VAR4,VAR20,VAR11,VAR19,VAR23,VAR22,VAR16,VAR5,VAR7,VAR1,VAR15,clk,VAR18,VAR2);
input VAR20,VAR11,VAR19,VAR4,clk;
input [9:0]VAR23,VAR22;
input [15:0]VAR16;
output reg VAR5,VAR7,VAR15;
output reg[15:0]VAR1,VAR2;
parameter VAR3=0;
parameter VAR13=2000;
reg[9:0]VAR17;
wire[9:0]VAR14;
output reg[9:0]VAR18;
V... | lgpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/example_design/PIO_RX_ENGINE.v | 44,339 | module MODULE1 #(
parameter VAR40 = 1,
parameter VAR23 = 64,
parameter VAR46 = VAR23 / 8 ) (
input clk,
input VAR29,
input [VAR23-1:0] VAR48,
input [VAR46-1:0] VAR51,
input VAR37,
input VAR33,
output reg VAR53,
input [21:0] VAR7,
output reg VAR52,
output reg VAR39,
input VAR22,
output reg [2:0] VAR9, output reg VAR55, ... | lgpl-3.0 |
ShepardSiegel/ocpi | scripts/altera/cleaned_alst4/altpcierd_tl_cfg_sample.v | 6,251 | module MODULE1 #(
parameter VAR21 = 0
)(
input VAR16, input VAR3,
input [ 3: 0] VAR20, input [ 31: 0] VAR12, input VAR10, input [ 52: 0] VAR2, input VAR11, output reg [ 12: 0] VAR13, output reg [ 31: 0] VAR9, output reg [ 31: 0] VAR23, output reg [31:0] VAR14,
output reg [19:0] VAR5,
output reg [19:0] VAR24,
output reg... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2b/sky130_fd_sc_hs__nor2b.functional.pp.v | 1,868 | module MODULE1 (
VAR5,
VAR1,
VAR8 ,
VAR10 ,
VAR9
);
input VAR5;
input VAR1;
output VAR8 ;
input VAR10 ;
input VAR9 ;
wire VAR8 VAR13 ;
wire VAR2 ;
wire VAR11;
not VAR7 (VAR13 , VAR10 );
and VAR3 (VAR2 , VAR13, VAR9 );
VAR4 VAR12 (VAR11, VAR2, VAR5, VAR1);
buf VAR6 (VAR8 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2b/sky130_fd_sc_ms__nor2b.symbol.v | 1,326 | module MODULE1 (
input VAR2 ,
input VAR6,
output VAR5
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
darekb74/WSIZ_SW_Projekt1 | Maszyna_do_kawy.srcs/sources_1/new/top.v | 3,182 | module MODULE1(
input wire [2:0]VAR13,
input wire [2:0]VAR10,
input wire VAR35, VAR16, VAR14, VAR42, VAR53,
input wire clk,
output wire [2:0] VAR4, output wire [2:0] VAR33,
output wire [3:0] VAR8, output wire VAR40, output wire VAR20, output wire VAR18, output wire VAR48, output wire VAR41, output wire VAR39, output wi... | gpl-3.0 |
trun/fpgaboy | src/gb/timer.v | 2,560 | module MODULE1 (
input wire VAR6,
input wire reset,
input wire VAR23,
output reg VAR12,
input wire [15:0] VAR14,
input wire [7:0] VAR19,
output wire [7:0] VAR3,
input wire VAR20,
input wire VAR2,
input wire VAR11
);
reg[7:0] VAR1;
reg[7:0] VAR8;
reg[7:0] VAR9;
reg[7:0] VAR21;
reg[7:0] VAR7;
parameter VAR17 = 8'hFF;
wir... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_rst_ps7_0_100M_0/zybo_zynq_design_rst_ps7_0_100M_0_stub.v | 1,937 | module MODULE1(VAR10, VAR6, VAR8,
VAR5, VAR9, VAR2, VAR7, VAR4,
VAR1, VAR3)
;
input VAR10;
input VAR6;
input VAR8;
input VAR5;
input VAR9;
output VAR2;
output [0:0]VAR7;
output [0:0]VAR4;
output [0:0]VAR1;
output [0:0]VAR3;
endmodule | mit |
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