repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fahcin/sky130_fd_sc_hd__fahcin.pp.blackbox.v | 1,342 | module MODULE1 (
VAR5,
VAR6 ,
VAR8 ,
VAR1 ,
VAR2 ,
VAR3,
VAR4,
VAR9 ,
VAR7
);
output VAR5;
output VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR2 ;
input VAR3;
input VAR4;
input VAR9 ;
input VAR7 ;
endmodule | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_nios2_qsys_0_jtag_debug_module_sysclk.v | 6,992 | module MODULE1 (
clk,
VAR1,
VAR16,
VAR27,
VAR24,
VAR9,
VAR31,
VAR25,
VAR17,
VAR15,
VAR28,
VAR18,
VAR22,
VAR23,
VAR21,
VAR5,
VAR10,
VAR6,
VAR14
)
;
output [ 37: 0] VAR9;
output VAR31;
output VAR25;
output VAR17;
output VAR15;
output VAR28;
output VAR18;
output VAR22;
output VAR23;
output VAR21;
output VAR5;
output VAR10... | gpl-3.0 |
d16-processor/d16 | verilog/src/mmio.v | 4,725 | module MODULE1(
input clk,
input rst,
input en,
input VAR7,
input VAR36,
input VAR17,
input [15:0] addr,
input [15:0] VAR21,
input [3:0] VAR26,
output reg [15:0] VAR9,
output [7:0] VAR34,
output reg VAR12 = 0,
input VAR16,
output VAR14,
output VAR3,
output [3:0] VAR22,
output VAR13,
input VAR19);
wire [15:0] VAR38;
ass... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2i/sky130_fd_sc_ms__mux2i.functional.v | 1,558 | module MODULE1 (
VAR5 ,
VAR7,
VAR6,
VAR8
);
output VAR5 ;
input VAR7;
input VAR6;
input VAR8 ;
wire VAR2;
VAR1 VAR4 (VAR2, VAR7, VAR6, VAR8 );
buf VAR3 (VAR5 , VAR2);
endmodule | apache-2.0 |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_2/affine_block_ieee754_fp_multiplier_1_2_stub.v | 1,338 | module MODULE1(VAR2, VAR1, VAR3)
;
input [31:0]VAR2;
input [31:0]VAR1;
output [31:0]VAR3;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4bb/sky130_fd_sc_lp__or4bb_m.v | 2,311 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR8 ,
VAR2 ,
VAR5 ,
VAR4,
VAR11,
VAR1 ,
VAR10
);
output VAR7 ;
input VAR9 ;
input VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR4;
input VAR11;
input VAR1 ;
input VAR10 ;
VAR3 VAR6 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR1(VAR1),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32oi/sky130_fd_sc_hs__a32oi_4.v | 2,356 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR6 ,
VAR9 ,
VAR8 ,
VAR2 ,
VAR5,
VAR10
);
output VAR4 ;
input VAR1 ;
input VAR6 ;
input VAR9 ;
input VAR8 ;
input VAR2 ;
input VAR5;
input VAR10;
VAR3 VAR7 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10)
);
endmodule
module MODUL... | apache-2.0 |
q3k/q3kmips | rtl/verilog/qm_fetch.v | 2,030 | module MODULE1(
input wire [31:0] VAR3,
output reg [31:0] VAR5,
output reg [31:0] VAR2,
output wire [31:0] VAR4,
input wire VAR1,
input wire VAR6,
input wire [31:0] VAR7
);
assign VAR4 = VAR3;
always @(*) begin
if (VAR6 && !VAR1) begin
VAR2 = VAR3;
VAR5 = 0;
end else begin
VAR2 = VAR3 + 4;
VAR5 = VAR7;
end
end
endmodul... | bsd-2-clause |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_qpll_drp.v | 20,767 | module MODULE1 #
(
parameter VAR79 = "VAR21", parameter VAR63 = "3.0", parameter VAR45 = "VAR60", parameter VAR46 = 0, parameter VAR76 = 2'd3, parameter VAR66 = 3'd6
)
(
input VAR69,
input VAR52,
input VAR13,
input VAR36,
input VAR74,
input VAR49,
input [15:0] VAR24,
input VAR7,
output [ 7:0] VAR65,
output VAR32,
outpu... | gpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/ipcore_dir/data_fifo.v | 13,415 | module MODULE1(
rst,
VAR216,
VAR36,
din,
VAR406,
VAR249,
dout,
VAR140,
VAR72
);
input rst;
input VAR216;
input VAR36;
input [63 : 0] din;
input VAR406;
input VAR249;
output [255 : 0] dout;
output VAR140;
output VAR72;
VAR1 #(
.VAR354(0),
.VAR398(0),
.VAR60(0),
.VAR345(0),
.VAR210(0),
.VAR100(0),
.VAR399(0),
.VAR44(32),... | mit |
jhol/butterflylogic | rtl/flags.v | 1,706 | module MODULE1 (
input wire VAR1,
input wire VAR3,
input wire [31:0] VAR4,
input wire VAR5,
output reg [31:0] VAR7
);
reg [31:0] VAR6;
VAR2 VAR7 = 0;
always @(posedge VAR1)
VAR7 <= VAR6;
always @*
begin
VAR6 = (VAR3) ? VAR4 : VAR7;
if (VAR5) VAR6[8] = 1'b0;
end
endmodule | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/dct_top_2d.v | 22,868 | module MODULE1(
clk,
rst,
VAR161,
VAR100,
VAR63,
VAR32,
VAR180,
VAR70,
VAR34,
VAR208,
VAR107,
VAR207,
VAR146,
VAR11,
VAR187,
VAR125,
VAR39,
VAR158,
VAR139,
VAR20,
VAR89,
VAR47,
VAR6,
VAR72,
VAR119,
VAR27,
VAR75,
VAR104,
VAR210,
VAR192,
VAR166,
VAR204,
VAR182,
VAR136,
VAR133,
VAR83,
VAR153,
VAR65,
VAR49,
VAR205,
VAR90,
... | gpl-3.0 |
azonenberg/antikernel-ipcores | noc/rpcv3/RPCv3RouterReceiver_buffering.v | 7,935 | module MODULE1
parameter VAR6 = 16,
parameter VAR5 = 16
)
(
input wire clk,
input wire VAR10,
input wire[VAR5-1:0] VAR4,
output reg VAR7 = 0,
input wire VAR9,
output wire VAR2,
output reg VAR1 = 0,
output reg[VAR6-1:0] VAR3 = 0,
output reg VAR8 = 0
); | bsd-3-clause |
elegabriel/myzju | junior1/CA/LAB/lab6/lab6_gxl_3120102146/code/ME_WB.v | 1,097 | module MODULE1(
clk,rst,VAR3,
VAR4, VAR7, VAR6,
VAR2, VAR5, VAR1
);
input clk,rst,VAR3;
input wire [31:0] VAR4;
input wire [4:0] VAR7;
input wire VAR6;
output reg [31:0] VAR2;
output reg [4:0] VAR5;
output reg VAR1;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
VAR2 <= 0;
VAR5 <= 0;
VAR1 <= 0;
end
else if(VA... | gpl-2.0 |
neilstockbridge/cores | UART/hello/top.v | 1,570 | module MODULE1 (
clk, VAR2, );
input clk;
output VAR2;
wire reset;
reg [7:0] VAR7 = 8'h2e; wire VAR6;
assign reset = 0;
VAR9 VAR4 (
.clk (clk),
.reset (reset),
.VAR2 (VAR2),
.VAR7 (VAR7),
.VAR8 (VAR6),
);
VAR1 VAR3 (
.clk (clk),
.VAR6 (VAR6)
);
endmodule | mit |
fallen/milkymist-mmu | cores/bt656cap/rtl/bt656cap.v | 2,211 | module MODULE1 #(
parameter VAR21 = 4'h0,
parameter VAR18 = 27
) (
input VAR29,
input VAR11,
input [13:0] VAR19,
input VAR32,
input [31:0] VAR14,
output [31:0] VAR3,
output irq,
output [VAR18-1:0] VAR5,
output VAR10,
input VAR17,
output [63:0] VAR13,
input VAR28,
input [7:0] VAR20,
inout VAR8,
);
wire VAR24;
wire VAR2... | lgpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_mem/bsg_mem_1rw_sync.v | 4,415 | if (VAR14 == VAR7 && VAR43 == VAR22) \
begin: VAR3 \
VAR45 VAR17 \
(.VAR23 ( VAR31 ) \
,.VAR6 ( VAR35 ) \
,.VAR10 ( {VAR22{1'b0}} ) \
,.VAR33 ( ~VAR28 ) \
,.VAR2 ( ~VAR32 ) \
,.VAR25 ( VAR1 ) \
,.VAR40 ( VAR42 ) \
,.VAR20 ( 2'b0 ) \
,.VAR16 ( 2'b0 )); \
end
if (VAR14 == VAR7 && VAR43 == VAR22) \
begin: VAR3 \
VAR9 VAR1... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_1.behavioral.pp.v | 2,030 | module MODULE1( VAR10, VAR3, VAR8, VAR2, VAR5, VAR6, VAR1 );
input VAR8, VAR2, VAR5, VAR10;
inout VAR6, VAR1;
output VAR3;
VAR9 VAR4(.VAR10(VAR10),.VAR3(VAR3),.VAR8(VAR8),.VAR2(VAR2),.VAR5(VAR5),.VAR6(VAR6),.VAR1(VAR1));
VAR9 VAR7(.VAR10(VAR10),.VAR3(VAR3),.VAR8(VAR8),.VAR2(VAR2),.VAR5(VAR5),.VAR6(VAR6),.VAR1(VAR1)); | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/srl.v | 1,093 | module MODULE1
(input clk,
input write,
input [VAR12-1:0] in,
input [3:0] addr,
output [VAR12-1:0] out);
genvar VAR8;
generate
for (VAR8=0;VAR8<VAR12;VAR8=VAR8+1)
begin : VAR13
VAR10
VAR5(.VAR7(out[VAR8]),
.VAR11(addr[0]),.VAR4(addr[1]),.VAR9(addr[2]),.VAR1(addr[3]),
.VAR6(write),.VAR2(clk),.VAR3(in[VAR8]));
end
endgen... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311a/sky130_fd_sc_hd__o311a.pp.blackbox.v | 1,406 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR7 ,
VAR10 ,
VAR9 ,
VAR6 ,
VAR5,
VAR2,
VAR8 ,
VAR4
);
output VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR10 ;
input VAR9 ;
input VAR6 ;
input VAR5;
input VAR2;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_bridge_v1_20_a/hdl/verilog/radio_bridge.v | 14,023 | module MODULE1
(
VAR118,
VAR76,
VAR40,
VAR88,
VAR27,
VAR6,
VAR89,
VAR57,
VAR46,
VAR35,
VAR79,
VAR75,
VAR34,
VAR25,
VAR81,
VAR26,
VAR117,
VAR3,
VAR42,
VAR63,
VAR74,
VAR125,
VAR8,
VAR53,
VAR94,
VAR66,
VAR104,
VAR84,
VAR29,
VAR4,
VAR7,
VAR101,
VAR38,
VAR1,
VAR70,
VAR77,
VAR109,
VAR50,
VAR110,
VAR22,
VAR20,
VAR62,
VAR103,
... | bsd-2-clause |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/xadc_temp_sensor/xadc_temp_sensor.v | 8,601 | module MODULE1
(
VAR19, VAR80, VAR26, VAR66, VAR20, VAR70, VAR18, VAR29, VAR23, VAR28, VAR72, VAR45, VAR38, VAR5, VAR47, VAR2, VAR1, VAR3);
input [6:0] VAR19;
input VAR80;
input VAR26;
input [15:0] VAR66;
input VAR20;
input VAR1;
input VAR3;
output VAR70;
output [4:0] VAR18;
output [15:0] VAR29;
output VAR23;
output VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2.functional.v | 1,508 | module MODULE1 (
VAR6 ,
VAR4,
VAR7,
VAR8
);
output VAR6 ;
input VAR4;
input VAR7;
input VAR8 ;
wire VAR5;
VAR2 VAR3 (VAR5, VAR4, VAR7, VAR8 );
buf VAR1 (VAR6 , VAR5);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_16.behavioral.pp.v | 1,089 | module MODULE1( VAR1, VAR4 );
inout VAR1, VAR4;
VAR2 VAR5(.VAR1(VAR1),.VAR4(VAR4));
VAR2 VAR3(.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbn/sky130_fd_sc_ms__dfbbn.behavioral.v | 2,779 | module MODULE1 (
VAR30 ,
VAR15 ,
VAR2 ,
VAR12 ,
VAR13 ,
VAR4
);
output VAR30 ;
output VAR15 ;
input VAR2 ;
input VAR12 ;
input VAR13 ;
input VAR4;
supply1 VAR18;
supply0 VAR27;
supply1 VAR10 ;
supply0 VAR19 ;
wire VAR25 ;
wire VAR20 ;
wire VAR23 ;
wire VAR7 ;
wire VAR26 ;
wire VAR16;
wire VAR17 ;
reg VAR8 ;
wire VAR5 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decapkapwr/sky130_fd_sc_lp__decapkapwr.behavioral.v | 1,202 | module MODULE1 ();
supply1 VAR4;
supply1 VAR1 ;
supply0 VAR3 ;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/4-way/ise/ipcore_dir/dram/user_design/rtl/ecc/mig_7series_v1_9_ecc_buf.v | 6,293 | module MODULE1
parameter VAR12 = 100,
parameter VAR25 = 64,
parameter VAR23 = 4,
parameter VAR27 = 1,
parameter VAR43 = 64,
parameter VAR2 = 4
)
(
VAR14,
clk, rst, VAR16, VAR42, VAR32,
VAR35, VAR46, VAR4
);
input clk;
input rst;
input [VAR23-1:0] VAR16;
input [VAR27-1:0] VAR42;
wire [4:0] VAR44;
input [VAR23-1:0] VAR32... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/maj3/sky130_fd_sc_ls__maj3.functional.v | 1,485 | module MODULE1 (
VAR6,
VAR8,
VAR3,
VAR2
);
output VAR6;
input VAR8;
input VAR3;
input VAR2;
wire VAR5 ;
wire VAR10 ;
wire VAR4 ;
wire VAR12;
or VAR7 (VAR5 , VAR3, VAR8 );
and VAR11 (VAR10 , VAR5, VAR2 );
and VAR13 (VAR4 , VAR8, VAR3 );
or VAR1 (VAR12, VAR4, VAR10);
buf VAR9 (VAR6 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32oi/sky130_fd_sc_ms__a32oi.blackbox.v | 1,434 | module MODULE1 (
VAR8 ,
VAR7,
VAR1,
VAR10,
VAR4,
VAR3
);
output VAR8 ;
input VAR7;
input VAR1;
input VAR10;
input VAR4;
input VAR3;
supply1 VAR2;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ip/fmrv32im_artya7_xlconcat_0_0/synth/fmrv32im_artya7_xlconcat_0_0.v | 4,558 | module MODULE1 (
VAR48,
dout
);
input wire [0 : 0] VAR48;
output wire [0 : 0] dout;
VAR57 #(
.VAR4(1),
.VAR28(1),
.VAR38(1),
.VAR6(1),
.VAR18(1),
.VAR24(1),
.VAR30(1),
.VAR13(1),
.VAR36(1),
.VAR49(1),
.VAR23(1),
.VAR47(1),
.VAR14(1),
.VAR7(1),
.VAR68(1),
.VAR32(1),
.VAR1(1),
.VAR56(1),
.VAR40(1),
.VAR44(1),
.VAR42(1),
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbn/sky130_fd_sc_hs__dlrbn.pp.blackbox.v | 1,371 | module MODULE1 (
VAR7,
VAR6 ,
VAR4 ,
VAR3 ,
VAR5 ,
VAR2 ,
VAR1
);
input VAR7;
input VAR6 ;
input VAR4 ;
output VAR3 ;
output VAR5 ;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
HeberthVG/papiGB | rtl/pGB.v | 7,993 | module MODULE1
(
input wire VAR143,
output wire [3:0] VAR71,
output wire [3:0] VAR89,
output wire [3:0] VAR95,
output wire VAR163,
output wire VAR142,
input wire [5:0] VAR47,
output wire VAR121,
output wire [15:0] VAR64,
output wire [15:0] VAR61,
input wire VAR120
);
wire [15:0] VAR110, VAR165;
wire [7:0] VAR168, VAR15... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphe/sky130_fd_sc_ls__decaphe.pp.blackbox.v | 1,217 | module MODULE1 (
VAR2,
VAR3,
VAR4 ,
VAR1
);
input VAR2;
input VAR3;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
sudov/options-accel | xillinux-eval-zedboard-1.1/system/hdl/system_xillybus_lite_0_wrapper.v | 3,742 | module MODULE2
(
VAR7,
VAR8,
VAR4,
VAR21,
VAR26,
VAR20,
VAR11,
VAR5,
VAR14,
VAR22,
VAR25,
VAR24,
VAR9,
VAR3,
VAR15,
VAR6,
VAR23,
VAR1,
VAR16,
VAR13,
VAR17,
VAR12,
VAR10,
VAR18,
VAR28,
VAR19,
VAR2,
VAR29
);
input VAR7;
input VAR8;
input [31:0] VAR4;
input VAR21;
input [31:0] VAR26;
input [3:0] VAR20;
input VAR11;
input ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxbp/sky130_fd_sc_hd__dfxbp.behavioral.pp.v | 1,923 | module MODULE1 (
VAR15 ,
VAR13 ,
VAR4 ,
VAR1 ,
VAR6,
VAR10,
VAR2 ,
VAR5
);
output VAR15 ;
output VAR13 ;
input VAR4 ;
input VAR1 ;
input VAR6;
input VAR10;
input VAR2 ;
input VAR5 ;
wire VAR9 ;
reg VAR7 ;
wire VAR3 ;
wire VAR8;
wire VAR16 ;
VAR14 VAR12 (VAR9 , VAR3, VAR8, VAR7, VAR6, VAR10);
assign VAR16 = ( VAR6 === 1... | apache-2.0 |
freecores/altor32 | rtl/cpu/altor32_wb_fetch.v | 6,545 | module MODULE1
(
input VAR10 ,
input VAR14 ,
input VAR16 ,
input VAR4 ,
input [31:0] VAR18 ,
output [31:0] VAR20 ,
output [31:0] VAR8 ,
output VAR17 ,
output VAR2 ,
output reg [31:0] VAR11 ,
input [31:0] VAR25 ,
output reg [2:0] VAR13 ,
output reg VAR19 ,
output reg VAR1 ,
input VAR24,
input VAR15
);
parameter VAR7 = 3... | lgpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ethmac/eth_txstatem.v | 10,027 | module MODULE1 (VAR34, VAR11, VAR48, VAR27, VAR30, VAR17, VAR16,
VAR31, VAR22, VAR12, VAR9, VAR8, VAR46, VAR32,
VAR23, VAR41, VAR6, VAR19, VAR7, VAR43, VAR38,
VAR20, VAR26, VAR1, VAR3, VAR5, VAR28,
VAR24, VAR33, VAR39, VAR2, VAR37, VAR45,
VAR13, VAR42, VAR35, VAR10, VAR44, VAR14,
VAR47, VAR49, VAR36, VAR40, VAR29, VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4/sky130_fd_sc_ls__or4.functional.v | 1,286 | module MODULE1 (
VAR8,
VAR6,
VAR2,
VAR4,
VAR5
);
output VAR8;
input VAR6;
input VAR2;
input VAR4;
input VAR5;
wire VAR3;
or VAR1 (VAR3, VAR5, VAR4, VAR2, VAR6 );
buf VAR7 (VAR8 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21boi/sky130_fd_sc_lp__a21boi.behavioral.pp.v | 2,172 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR2 ,
VAR16,
VAR9,
VAR17,
VAR12 ,
VAR14
);
output VAR1 ;
input VAR10 ;
input VAR2 ;
input VAR16;
input VAR9;
input VAR17;
input VAR12 ;
input VAR14 ;
wire VAR4 ;
wire VAR18 ;
wire VAR5 ;
wire VAR8;
not VAR13 (VAR4 , VAR16 );
and VAR15 (VAR18 , VAR10, VAR2 );
nor VAR11 (VAR5 , VAR4, VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s.functional.pp.v | 1,865 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR10,
VAR9,
VAR7 ,
VAR12
);
output VAR1 ;
input VAR11 ;
input VAR10;
input VAR9;
input VAR7 ;
input VAR12 ;
wire VAR8 ;
wire VAR4;
buf VAR2 (VAR8 , VAR11 );
VAR6 VAR5 (VAR4, VAR8, VAR10, VAR9);
buf VAR3 (VAR1 , VAR4 );
endmodule | apache-2.0 |
drichmond/riffa | fpga/altera/de5/DE5QGen2x8If128/hdl/DE5QGen2x8If128.v | 17,456 | module MODULE1
parameter VAR102 = 8,
parameter VAR56 = 128,
parameter VAR51 = 256,
parameter VAR158 = 5
)
(
output [7:0] VAR141,
input VAR136,
input VAR55,
input [VAR102-1:0] VAR184,
output [VAR102-1:0] VAR209,
input VAR132
);
wire VAR199;
wire VAR79;
wire [3:0] VAR130;
wire [31:0] VAR178;
wire [52:0] VAR45;
wire [0:0]... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbp/sky130_fd_sc_hd__dfbbp.blackbox.v | 1,435 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR2 ,
VAR10 ,
VAR1 ,
VAR9
);
output VAR7 ;
output VAR3 ;
input VAR2 ;
input VAR10 ;
input VAR1 ;
input VAR9;
supply1 VAR8;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
peteasa/oh | src/common/hdl/oh_clockgate.v | 1,205 | module MODULE1 (
input clk, input VAR1, input en, output VAR7 );
localparam VAR11 = VAR10;
generate
if(VAR11)
begin : VAR2
VAR8 VAR8 (.en(en),
.VAR1(VAR1),
.clk(clk),
.VAR7(VAR7));
end
else
begin : VAR4
wire VAR5;
wire VAR9;
assign VAR9 = en | VAR1;
VAR3 VAR6 (.out (VAR5),
.in (VAR9),
.clk (clk));
assign VAR7 = clk & V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311o/sky130_fd_sc_hd__a311o.pp.blackbox.v | 1,421 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR2 ,
VAR5 ,
VAR4 ,
VAR6 ,
VAR10,
VAR9,
VAR1 ,
VAR3
);
output VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR5 ;
input VAR4 ;
input VAR6 ;
input VAR10;
input VAR9;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
hanyazou/vivado-ws | playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/bd/design_1/ip/design_1_debug_counter_0_0/synth/design_1_debug_counter_0_0.v | 2,947 | module MODULE1 (
VAR1,
VAR4
);
input wire VAR1;
output wire [3 : 0] VAR4;
VAR3 VAR2 (
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule | mit |
romovs/xula-lib-verilog | camera/OV7670Init.v | 6,693 | module MODULE1 (VAR1, VAR2);
input [5:0] VAR1; output reg [16:0] VAR2; always @* begin
case(VAR1)
6'd0 : VAR2 = {16'h1280, 1'b1}; 6'd1 : VAR2 = {16'hf0f0, 1'b1}; 6'd2 : VAR2 = {16'h1204, 1'b1}; 6'd3 : VAR2 = {16'h1100, 1'b1}; 6'd4 : VAR2 = {16'h0C00, 1'b1}; 6'd5 : VAR2 = {16'h3E00, 1'b1}; 6'd6 : VAR2 = {16'h8C00, 1'b1}... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.behavioral.v | 3,306 | module MODULE1( VAR7, VAR1, VAR4, VAR3, VAR6, VAR8 );
input VAR6, VAR8, VAR1, VAR4, VAR3;
output VAR7;
VAR5 VAR9(.VAR7(VAR7),.VAR1(VAR1),.VAR4(VAR4),.VAR3(VAR3),.VAR6(VAR6),.VAR8(VAR8));
VAR5 VAR2(.VAR7(VAR7),.VAR1(VAR1),.VAR4(VAR4),.VAR3(VAR3),.VAR6(VAR6),.VAR8(VAR8)); | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_sa1/sa1_iram.v | 10,664 | module MODULE1 (
VAR9,
VAR28,
VAR38,
VAR31,
VAR50,
VAR17,
VAR27,
VAR19,
VAR15);
input [10:0] VAR9;
input [10:0] VAR28;
input VAR38;
input [7:0] VAR31;
input [7:0] VAR50;
input VAR17;
input VAR27;
output [7:0] VAR19;
output [7:0] VAR15;
tri1 VAR38;
tri0 VAR17;
tri0 VAR27;
wire [7:0] VAR59;
wire [7:0] VAR20;
wire [7:0] V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21oi/sky130_fd_sc_hdll__a21oi.pp.symbol.v | 1,360 | module MODULE1 (
input VAR1 ,
input VAR6 ,
input VAR2 ,
output VAR4 ,
input VAR3 ,
input VAR8,
input VAR5,
input VAR7
);
endmodule | apache-2.0 |
rkrajnc/minimig-mist | lib/altera/220model.v | 232,146 | module MODULE3;
function [8:1] VAR7;
input [8:1] VAR127;
reg [8:1] VAR281;
begin
if ((VAR127 >= 65) && (VAR127 <= 90)) begin
VAR281 = VAR127 + 32; VAR7 = VAR281;
end
else
VAR7 = VAR127;
end
endfunction
task VAR286;
input[VAR87*8 : 1] VAR134;
input VAR165;
output [VAR87*8 : 1] VAR163;
reg [VAR87*8 : 1] VAR134;
reg [VAR8... | gpl-3.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/user_logic.v | 13,049 | module MODULE1
(
VAR47,
VAR68,
VAR4,
VAR62,
VAR54,
VAR28, VAR76, VAR77, VAR52, VAR32, VAR9, VAR45, VAR69, VAR29, VAR81, VAR37, VAR41, VAR26, VAR36, VAR30, VAR42, VAR38, VAR8, VAR75, VAR56, VAR21, VAR3, VAR40 );
parameter VAR80 = 32;
parameter VAR17 = 2;
parameter VAR7 = 32;
parameter VAR1 = 512;
parameter VAR79 = 32;
p... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill_diode/sky130_fd_sc_ms__fill_diode.behavioral.v | 1,141 | module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_p_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_p_pp_pkg_sn.blackbox.v | 1,477 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR5 ,
VAR4 ,
VAR8,
VAR3 ,
VAR2 ,
VAR6
);
output VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR8;
input VAR3 ;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
jouyang3/FMCW | DSP/Radar_DSP/FPGA/Individual Modules/Ram_example/Ram_example/windowing.v | 2,431 | module MODULE1(
input [11:0] VAR29,
input [11:0] VAR3,
input clk,
output reg[11:0] VAR4,
output reg[11:0] VAR28,
output reg VAR10,
output reg [2:0] state
);
reg [10:0] VAR6;
wire [10:0] VAR7, VAR20;
wire [7:0] VAR8, VAR23;
reg [2:0] VAR2; reg [13:0] VAR11;
reg VAR30, VAR5, VAR1,
VAR17, VAR22;
reg [19:0] VAR24, VAR18;
m... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4b/sky130_fd_sc_hs__or4b.functional.v | 1,871 | module MODULE1 (
VAR1,
VAR7,
VAR9 ,
VAR12 ,
VAR6 ,
VAR10 ,
VAR8
);
input VAR1;
input VAR7;
output VAR9 ;
input VAR12 ;
input VAR6 ;
input VAR10 ;
input VAR8 ;
wire VAR8 VAR3 ;
wire VAR4 ;
wire VAR5;
not VAR15 (VAR3 , VAR8 );
or VAR14 (VAR4 , VAR3, VAR10, VAR6, VAR12 );
VAR11 VAR2 (VAR5, VAR4, VAR1, VAR7);
buf VAR13 (VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311a/sky130_fd_sc_hs__o311a_1.v | 2,295 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR1 ,
VAR7 ,
VAR6 ,
VAR4 ,
VAR5,
VAR3
);
output VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR6 ;
input VAR4 ;
input VAR5;
input VAR3;
VAR2 VAR10 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 ... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v | 4,952 | module MODULE1
,parameter VAR15(VAR44 )
,parameter VAR53 = VAR25(VAR44)
)
(input VAR23
,input VAR41
,input VAR30
,input [VAR53-1:0] VAR6
,input [VAR3-1:0] VAR11
,output VAR22
,output VAR38
,output VAR31
,output [VAR44-1:0][VAR3-1:0] VAR52
,input VAR20
);
genvar VAR14;
logic VAR19;
assign VAR19 = VAR30 & VAR22;
logic [V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi.blackbox.v | 1,471 | module MODULE1 (
VAR8 ,
VAR6,
VAR2,
VAR9 ,
VAR7
);
output VAR8 ;
input VAR6;
input VAR2;
input VAR9 ;
input VAR7 ;
supply1 VAR1;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3b/sky130_fd_sc_hdll__nor3b.pp.blackbox.v | 1,356 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR8 ,
VAR3 ,
VAR6,
VAR4,
VAR7 ,
VAR1
);
output VAR2 ;
input VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR6;
input VAR4;
input VAR7 ;
input VAR1 ;
endmodule | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Position/RAM_tst.v | 1,912 | module MODULE1;
reg clk;
reg [7:0] VAR6;
reg [7:0] VAR9;
reg VAR4;
reg VAR10;
reg [31:0] VAR12;
wire [31:0] VAR11;
wire [15:0] VAR2;
reg [8:0] VAR1;
reg [15:0] VAR8;
reg [15:0] VAR3;
VAR7 VAR5 (
.clk(clk),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR11(VAR11),
.VAR2(VAR2)
); | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf.pp.blackbox.v | 1,257 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR2,
VAR3,
VAR4 ,
VAR1
);
output VAR5 ;
input VAR6 ;
input VAR2;
input VAR3;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlclkp/sky130_fd_sc_hs__dlclkp.pp.symbol.v | 1,237 | module MODULE1 (
input VAR1 ,
input VAR2,
output VAR4,
input VAR3,
input VAR5
);
endmodule | apache-2.0 |
hcabrera-/lancetfish | RTL/shared/rtl/fifo.v | 4,089 | module MODULE1
(
input wire clk,
input wire reset,
input wire VAR6,
input wire VAR1,
input wire [VAR17-1:0] VAR3,
output wire VAR8,
output wire VAR13,
output wire [VAR17-1:0] VAR12
);
localparam VAR15 = VAR20(VAR16);
wire [VAR15-1:0] VAR11;
wire [VAR15-1:0] VAR7;
wire VAR2;
VAR18 VAR18
(
.clk (clk),
.reset (reset),
.VA... | gpl-3.0 |
efabless/openlane | designs/jpeg_encoder/src/dctu.v | 3,857 | module MODULE1(clk, VAR3, VAR11, VAR8, VAR13, VAR15, dout);
parameter VAR2 = 16;
parameter VAR10 = 8;
parameter [2:0] VAR12 = 0;
parameter [2:0] VAR1 = 0;
input clk;
input VAR3;
input VAR11; input [2:0] VAR8, VAR13;
input [VAR10:1] VAR15; output [11:0] dout;
reg [ 31:0] VAR4;
wire [VAR2 +10:0] VAR9;
always @(posedge cl... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/altera_jtag_dc_streaming/altera_jtag_sld_node.v | 5,844 | module MODULE1 (
VAR56,
VAR73,
VAR66,
VAR11,
VAR68,
VAR61,
VAR12,
VAR45,
VAR44,
VAR13,
VAR35,
VAR51,
VAR65
);
parameter VAR4 = 20;
localparam VAR46 = (1000/VAR4)/2;
localparam VAR1 = 3;
input [VAR1 - 1:0] VAR56;
input VAR73;
output reg [VAR1 - 1:0] VAR66;
output VAR11;
output reg VAR68 = 1'b0;
output VAR61;
output VAR1... | mit |
Elphel/x393_sata | x393/util_modules/dly01_16.v | 2,495 | module MODULE1(
input clk,
input rst,
input [3:0] VAR2,
input din,
output dout
);
reg [15:0] VAR1=0;
always @ (posedge clk) begin
VAR1 <= {VAR1[14:0], din & ~rst};
end
always @ (posedge clk) begin
if (rst) VAR1 <=0;
end
else VAR1 <= {VAR1[14:0],din};
end
assign dout = (|VAR1) ? ((&VAR1) ? 1'b1 : VAR1[VAR2]) : 1'b0 ;
as... | gpl-3.0 |
bunnie/novena-sd-fpga | novena-sd.srcs/sources_1/ip/clk_wiz_v3_5_1/ddr3_clkgen.v | 6,142 | module MODULE1
( input VAR1,
output VAR38,
output VAR35,
output VAR17,
input VAR21,
output VAR37
);
VAR46 VAR43
(.VAR15 (VAR7),
.VAR20 (VAR1));
wire [15:0] VAR11;
wire VAR16;
wire VAR18;
wire VAR39;
wire VAR2;
wire VAR49;
wire VAR28;
VAR53
.VAR24 ("VAR33"),
.VAR8 ("VAR26"),
.VAR29 (1),
.VAR19 (8),
.VAR27 (0.000),
.VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4/sky130_fd_sc_hdll__or4_1.v | 2,247 | module MODULE2 (
VAR9 ,
VAR7 ,
VAR2 ,
VAR5 ,
VAR3 ,
VAR4,
VAR6,
VAR11 ,
VAR1
);
output VAR9 ;
input VAR7 ;
input VAR2 ;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR6;
input VAR11 ;
input VAR1 ;
VAR10 VAR8 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR... | apache-2.0 |
sudov/options-accel | xillinux-eval-zedboard-1.1/system/hdl/system_xillybus_0_wrapper.v | 10,578 | module MODULE1
(
VAR104,
VAR69,
VAR94,
VAR16,
VAR76,
VAR19,
VAR84,
VAR67,
VAR10,
VAR61,
VAR83,
VAR110,
VAR72,
VAR43,
VAR63,
VAR95,
VAR37,
VAR49,
VAR60,
VAR87,
VAR3,
VAR5,
VAR91,
VAR79,
VAR23,
VAR28,
VAR78,
VAR96,
VAR59,
VAR35,
VAR11,
VAR13,
VAR77,
VAR46,
VAR62,
VAR32,
VAR107,
VAR45,
VAR7,
VAR74,
VAR47,
VAR65,
VAR27,
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3b/sky130_fd_sc_hs__nand3b_4.v | 2,102 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR5 ,
VAR6 ,
VAR4,
VAR8
);
output VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR6 ;
input VAR4;
input VAR8;
VAR7 VAR3 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR2 ,
VAR1,
VAR5 ,
VAR6
);
output VAR2 ;
input VAR1;
input VAR5 ... | apache-2.0 |
hydai/Verilog-Practice | HardwareLab/Lab8/Lab8.v | 1,649 | module MODULE1(VAR15, VAR39, VAR20, VAR14, VAR1, VAR5, VAR17, VAR23, VAR9, VAR13, VAR2, VAR34, clk);
input clk, VAR34;
input [3:0] VAR2;
output VAR15, VAR39, VAR20, VAR14, VAR1, VAR5;
output [7:0] VAR17;
output [3:0] VAR23;
output [3:0] VAR9;
output [7:0] VAR13;
wire VAR44, VAR3, VAR16, VAR19, VAR43;
wire VAR26, VAR47;... | mit |
m13253/riscade | hdl/src/step_ex_im.v | 1,122 | module MODULE1(clk, rst, VAR5, VAR2,
VAR7, VAR8, VAR6,
VAR1, VAR3);
input clk;
input rst;
input VAR5;
output VAR2;
output[7:0] VAR7;
input[7:0] VAR8;
output VAR6;
input[3:0] VAR1;
input VAR3;
reg VAR10;
assign VAR2 = VAR10 ? 1'b0 : 1'VAR9;
reg VAR11;
assign VAR7 = VAR11 ?
VAR3 ? {VAR1, VAR8[3:0]} : {VAR8[7:4], VAR1} :
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/maj3/sky130_fd_sc_lp__maj3.pp.blackbox.v | 1,297 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR1 ,
VAR8 ,
VAR5,
VAR3,
VAR4 ,
VAR7
);
output VAR6 ;
input VAR2 ;
input VAR1 ;
input VAR8 ;
input VAR5;
input VAR3;
input VAR4 ;
input VAR7 ;
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_fp_fabs_double.v | 4,847 | module MODULE1
(
VAR1,
VAR6,
VAR4,
VAR2) ;
input VAR1;
input VAR6;
input [63:0] VAR4;
output [63:0] VAR2;
tri1 VAR1;
tri0 VAR6;
reg [62:0] VAR7;
wire VAR8;
wire [63:0] VAR5;
wire VAR3; | mit |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/refread_manager.v | 1,127 | module MODULE1 #(parameter VAR3 = 128, VAR6 = 8) (
input clk,
input rst,
input VAR2,
input[VAR3 - 1:0] VAR8,
output[VAR3 * VAR6 - 1 :0] VAR10
);
parameter VAR4 = VAR5(VAR6);
reg[VAR3 - 1:0] VAR1 [0:(VAR6 - 1)];
integer VAR9;
always@(posedge clk) begin
if(VAR2) begin
VAR1[VAR6 - 1] <= VAR8;
for(VAR9 = 0; VAR9 < (VAR6 - ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2_4.v | 2,097 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR7 ,
VAR4,
VAR9,
VAR6 ,
VAR3
);
output VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR4;
input VAR9;
input VAR6 ;
input VAR3 ;
VAR2 VAR8 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR1,
VAR5,
VAR7
);
output VAR1;
... | apache-2.0 |
emeb/iceRadio | FPGA/rxadc_2/verilog/src/tuner_2.v | 1,550 | module MODULE1 #(
parameter VAR5 = 10,
VAR6 = 26,
VAR4 = 12
)
(
input clk, reset,
input signed [VAR5-1:0] in,
input [VAR6-1:0] VAR3,
input VAR13,
output signed [VAR5-1:0] VAR2, VAR11
);
reg [VAR6-1:0] VAR1;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
VAR1 <= {VAR6{1'b0}};
end
else
begin
VAR1 <= VAR1 + VAR3;
end... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtn/sky130_fd_sc_ms__dlxtn.behavioral.v | 1,947 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR7
);
output VAR10 ;
input VAR2 ;
input VAR7;
supply1 VAR13;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR1 ;
wire VAR4 ;
wire VAR17 ;
wire VAR15;
wire VAR8 ;
reg VAR12 ;
wire VAR11 ;
not VAR6 (VAR4 , VAR15 );
VAR16 VAR9 (VAR17 , VAR8, VAR4, VAR12, VAR13, VAR3);
buf VAR14 (VAR10 , VAR17 );
... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/pre_i/hevc_md_top.v | 3,690 | module MODULE1(
clk,
VAR18,
VAR28,
VAR42,
VAR5,
VAR11,
VAR23,
VAR2,
VAR7,
VAR22,
VAR37,
VAR1,
enable,
VAR16
);
input clk ;
input VAR18 ;
output VAR28 ;
output VAR42 ;
output [1:0] VAR5 ;
output [3:0] VAR11 ;
output [3:0] VAR23 ;
output [4:0] VAR2 ;
input [255:0] VAR7 ;
output VAR22;
output [5:0] VAR1;
output [6:0] VAR3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3/sky130_fd_sc_ls__and3.behavioral.v | 1,371 | module MODULE1 (
VAR9,
VAR8,
VAR1,
VAR6
);
output VAR9;
input VAR8;
input VAR1;
input VAR6;
supply1 VAR5;
supply0 VAR11;
supply1 VAR2 ;
supply0 VAR10 ;
wire VAR3;
and VAR4 (VAR3, VAR6, VAR8, VAR1 );
buf VAR7 (VAR9 , VAR3 );
endmodule | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/Phy_int.v | 8,513 | module MODULE1 (
VAR6 ,
VAR19 ,
VAR30 ,
VAR25 ,
VAR2 ,
VAR5 ,
VAR13 ,
VAR12 ,
VAR3 ,
VAR22 ,
VAR24 ,
VAR4 ,
VAR11 ,
VAR29 ,
VAR14 ,
VAR10 ,
VAR7 ,
VAR27 ,
VAR20
);
input VAR6 ;
input VAR19 ;
input VAR30 ;
output VAR25 ;
output [7:0] VAR2 ;
output VAR5 ;
input [7:0] VAR13 ;
input VAR12 ;
output VAR3 ;
output VAR22 ;
out... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/DOUBLE/Exp_Operation_syn.v | 11,111 | module MODULE2 ( VAR114, VAR19, VAR119, VAR3, VAR57 );
input [8:0] VAR114;
input [8:0] VAR19;
output [8:0] VAR3;
input VAR119;
output VAR57;
wire VAR54, VAR150;
wire [8:1] VAR17;
VAR151 VAR72 ( .VAR114(VAR114[6]), .VAR19(VAR19[6]), .VAR81(VAR17[6]), .VAR57(VAR17[7]), .VAR23(VAR3[6]) );
VAR151 VAR86 ( .VAR114(VAR114[5])... | gpl-3.0 |
kyzhai/NUNY | src/hardware/lab3/synthesis/submodules/lab3_master_0_b2p_adapter.v | 1,488 | module MODULE1 (
input clk,
input VAR10,
output reg VAR6,
input VAR3,
input [ 7: 0] VAR8,
input [ 7: 0] VAR1,
input VAR7,
input VAR9,
input VAR13,
output reg VAR12,
output reg [ 7: 0] VAR2,
output reg VAR5,
output reg VAR11
);
reg VAR4;
always @* begin
VAR6 = VAR13;
VAR12 = VAR3;
VAR2 = VAR8;
VAR5 = VAR7;
VAR11 = VAR9;... | gpl-2.0 |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/syn/verilog/tri_intersect_data_array.v | 1,977 | module MODULE1 (VAR13, VAR6, VAR17, VAR4, VAR2, VAR16, VAR10, d1, VAR5, VAR11, clk);
parameter VAR7 = 576;
parameter VAR8 = 1;
parameter VAR15 = 2;
input[VAR8-1:0] VAR13;
input VAR6;
input[VAR7-1:0] VAR17;
input VAR4;
output reg[VAR7-1:0] VAR2;
input[VAR8-1:0] VAR16;
input VAR10;
input[VAR7-1:0] d1;
input VAR5;
output ... | mit |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodGPS_v1_1/src/PmodGPS.v | 12,731 | module MODULE1
(VAR29,
VAR136,
VAR185,
VAR104,
VAR23,
VAR174,
VAR173,
VAR58,
VAR171,
VAR45,
VAR107,
VAR133,
VAR6,
VAR183,
VAR72,
VAR42,
VAR79,
VAR87,
VAR179,
VAR48,
VAR24,
VAR102,
VAR9,
VAR35,
VAR189,
VAR169,
VAR100,
VAR25,
VAR98,
VAR53,
VAR101,
VAR90,
VAR81,
VAR128,
VAR158,
VAR140,
VAR11,
VAR3,
VAR176,
VAR170,
VAR149,... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4/sky130_fd_sc_hd__and4.pp.symbol.v | 1,297 | module MODULE1 (
input VAR3 ,
input VAR4 ,
input VAR6 ,
input VAR8 ,
output VAR9 ,
input VAR2 ,
input VAR1,
input VAR7,
input VAR5
);
endmodule | apache-2.0 |
DevD1092/v2NuSMV | Traffic_light_controller.v | 3,735 | module MODULE1 ( clk, reset, VAR103, VAR4 );
output [2:0] VAR103;
output [2:0] VAR4;
input clk, reset;
wire VAR25, VAR50, VAR36, VAR43, VAR126, VAR61, VAR42, VAR108, VAR122, VAR63, VAR9, VAR97, VAR52, VAR73,
VAR80, VAR35, VAR111, VAR69, VAR87, VAR3, VAR47, VAR70, VAR99, VAR116, VAR102, VAR95, VAR79, VAR88,
VAR11, VAR10... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0p/sky130_fd_sc_lp__inputiso0p.behavioral.pp.v | 1,849 | module MODULE1 (
VAR13 ,
VAR5 ,
VAR3,
VAR2 ,
VAR4 ,
VAR10 ,
VAR7
);
output VAR13 ;
input VAR5 ;
input VAR3;
input VAR2 ;
input VAR4 ;
input VAR10 ;
input VAR7 ;
wire VAR1 ;
wire VAR11;
not VAR9 (VAR1 , VAR3 );
and VAR12 (VAR11, VAR5, VAR1 );
VAR6 VAR8 (VAR13 , VAR11, VAR2, VAR4);
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_system/synthesis/submodules/niosII_system_video_scaler_0.v | 8,594 | module MODULE1 (
clk,
reset,
VAR10,
VAR29,
VAR35,
VAR9,
VAR23,
VAR18,
VAR3,
VAR16,
VAR7,
VAR17,
VAR27,
VAR28
);
parameter VAR22 = 29; parameter VAR13 = 1;
parameter VAR33 = 8; parameter VAR31 = 7; parameter VAR25 = 320;
parameter VAR34 = 4'b0000;
parameter VAR4 = 4'b0000;
parameter VAR12 = 8; parameter VAR30 = 320; par... | gpl-2.0 |
neale/MachX02 | SmartRemote/SmartRemote.v | 1,171 | module MODULE2(
input VAR3,VAR28,VAR14,
VAR29,
VAR11,
output VAR34,
VAR1,
VAR38,
VAR10
);
supply0 VAR2;
wire VAR7, VAR8, VAR17, VAR12; wire VAR9, VAR31, VAR36, VAR23;
assign VAR34 = VAR7;
assign VAR26 = VAR8;
assign VAR38 = VAR17;
assign VAR10 = VAR12;
VAR22 VAR18(
.VAR13(VAR3), .VAR40(VAR28),
.VAR20(VAR14),
.VAR5(VAR3... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v | 10,776 | module MODULE1 #
(parameter VAR13 = 3,
parameter VAR23 = 100,
parameter VAR76 = "8",
parameter VAR33 = 12,
parameter VAR78 = 8,
parameter VAR53 = "VAR73",
parameter VAR34 = 2,
parameter VAR63 = 4,
parameter VAR66 = 16)
(
VAR77, VAR48, VAR27, VAR21,
VAR1, VAR69, VAR43, VAR15, VAR5,
VAR32, VAR8, VAR25, VAR45, VAR75,
VAR5... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrbp/sky130_fd_sc_hvl__dfrbp.functional.v | 1,769 | module MODULE1 (
VAR13 ,
VAR1 ,
VAR9 ,
VAR7 ,
VAR12
);
output VAR13 ;
output VAR1 ;
input VAR9 ;
input VAR7 ;
input VAR12;
wire VAR10;
wire VAR2;
not VAR4 (VAR2 , VAR12 );
VAR8 VAR11 VAR3 (VAR10 , VAR7, VAR9, VAR2 );
buf VAR5 (VAR13 , VAR10 );
not VAR6 (VAR1 , VAR10 );
endmodule | apache-2.0 |
martinmiranda14/Digitales | Lab_6/project_7/project_7.srcs/sources_1/new/tx_control.v | 3,069 | module MODULE1
input VAR3,
input reset,
input VAR4, input VAR2, input [15:0] VAR12, output reg [7:0] VAR18, output reg VAR10, output reg VAR13 );
reg [2:0] VAR17, state;
reg [15:0] VAR8;
reg [31:0] VAR16;
localparam VAR1 = 3'd0; localparam VAR9 = 3'd1; localparam VAR15 = 3'd2; localparam VAR14 = 3'd3; localparam VAR7 =... | apache-2.0 |
maltanar/spmv-vector-cache | proj/ip/AXIOutputRegisters_1.0/hdl/AXIOutputRegisters_v1_0.v | 3,789 | module MODULE1 #
(
parameter integer VAR54 = 32,
parameter integer VAR20 = 6
)
(
output wire [VAR54-1 : 0] VAR41,
output wire [VAR54-1 : 0] VAR53,
output wire [VAR54-1 : 0] VAR59,
output wire [VAR54-1 : 0] VAR32,
output wire [VAR54-1 : 0] VAR22,
output wire [VAR54-1 : 0] VAR13,
output wire [VAR54-1 : 0] VAR28,
output w... | bsd-3-clause |
praveendath92/securePUF | source/puf_files/puf_intercon_network.v | 3,382 | module MODULE1(VAR11, VAR1, VAR6, VAR7, reset);
output [5:0] VAR6;
input [31:0] VAR11;
input [127:0] VAR1;
input VAR7;
input reset;
wire [31:0] VAR11;
wire [127:0] VAR1;
wire [5:0] VAR6;
VAR3 VAR10 ( .VAR5( {VAR11[31:0], VAR1[31:0]} ),
.VAR4( {VAR11[31:0], VAR1[95:64]} ),
.VAR12(VAR7),
.reset(reset),
.VAR9(VAR6[0]));
V... | gpl-2.0 |
hydai/Verilog-Practice | DigitalDesign/SYN/hw5/RAM32x8.v | 10,018 | module MODULE1 (
VAR7,
VAR28,
VAR13,
VAR49,
VAR25,
VAR27,
VAR54
);
parameter VAR48 = 8;
parameter VAR43 = 32;
parameter VAR35 = 5;
parameter VAR65 = {VAR48{1'VAR1}};
parameter VAR32 = {VAR35{1'VAR1}};
output [7:0] VAR7;
input VAR28;
input VAR13;
input VAR49;
input [4:0] VAR25;
input [7:0] VAR27;
input VAR54;
reg [VAR48... | mit |
Separius/Custom-Single-Cycle-MIPS | DataPath.v | 1,112 | module MODULE1(input clk,rst,VAR9,VAR10,VAR33,VAR4,input[1:0] VAR1,VAR26,output VAR18,VAR32,output[5:0] VAR3);
wire[2:0] VAR17;
wire[7:0] VAR27;
wire[7:0] VAR19,VAR2,VAR20,VAR24,VAR14;
wire[11:0] addr,VAR30,VAR22;
wire[18:0] VAR31;
wire[2:0] VAR23;
wire VAR15;
assign VAR23 = VAR9 ? VAR31[13:11] : VAR31[7:5];
assign VAR... | gpl-3.0 |
defano/digital-design | konami-acceptor/rtl/konamiacceptor.v | 6,127 | module MODULE1 (
clk,
reset,
VAR13,
VAR11,
VAR1,
VAR12,
VAR35,
VAR43
);
input clk;
input reset;
input VAR13;
input VAR11;
input VAR1;
input VAR12;
output [6:0] VAR35;
output [3:0] VAR43;
parameter VAR2 = 4'd0; parameter VAR4 = 4'd1; parameter VAR28 = 4'd2;
parameter VAR37 = 4'd3;
parameter VAR14 = 4'd4;
parameter VAR8 ... | mit |
TheMadSocrates/vercpu-project | rtl/fpga/sram.v | 1,353 | module MODULE1(
input wire [ 7 : 0] address,
input wire [ 7 : 0] VAR3,
input wire clk,
input wire VAR1,
output reg [ 7 : 0] VAR2
);
reg [ 7 : 0] memory [255 : 0];
always @(posedge clk) begin
if(VAR1)
memory[address] <= VAR3;
VAR2 <= memory[address];
end
endmodule | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_s6_x1_125/source/gtpa1_dual_wrapper_top.v | 7,962 | module MODULE1 #(
parameter VAR94 = 0
)
(
input wire VAR37,
input wire VAR24,
input wire VAR79,
input wire VAR66,
output wire VAR50,
output wire VAR35,
input wire VAR28,
output wire [1:0] VAR31,
output wire [15:0] VAR58,
output wire VAR2,
output wire [2:0] VAR46,
input wire VAR73,
input wire [1:0] VAR1,
input wire [1:0... | lgpl-3.0 |
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