repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
TalentlessAlpaca/Automated_Vacuum_Cleaner | Multiplier_V2/booth_tst.v | 1,540 | module MODULE1;
reg clk;
reg rst;
reg en;
reg [15:0] VAR2;
reg [15:0] VAR4;
wire VAR6;
wire [31:0] VAR1;
VAR3 VAR5 (
.clk(clk),
.rst(rst),
.en(en),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1)
); | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22oi/sky130_fd_sc_hd__a22oi.pp.symbol.v | 1,376 | module MODULE1 (
input VAR2 ,
input VAR9 ,
input VAR5 ,
input VAR4 ,
output VAR3 ,
input VAR6 ,
input VAR8,
input VAR7,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2/sky130_fd_sc_hs__nand2.functional.v | 1,681 | module MODULE1 (
VAR8,
VAR11,
VAR1 ,
VAR3 ,
VAR4
);
input VAR8;
input VAR11;
output VAR1 ;
input VAR3 ;
input VAR4 ;
wire VAR9 ;
wire VAR10;
nand VAR5 (VAR9 , VAR4, VAR3 );
VAR2 VAR7 (VAR10, VAR9, VAR8, VAR11);
buf VAR6 (VAR1 , VAR10 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_clk_gen/bsg_rp_clk_gen_fine_delay_tuner.v | 2,598 | module MODULE1
(input VAR26
, input VAR27
, input VAR30
, input [1:0] VAR45
, output VAR43
, output VAR11
, output VAR2
);
wire [1:0] VAR5;
wire [1:0] VAR47;
wire [3:0] VAR6;
wire VAR19;
VAR35 VAR22 (.VAR31(VAR6[1]),.VAR38());
VAR35 VAR44 (.VAR31(VAR6[2]),.VAR38());
VAR21 VAR25 (.VAR31(VAR6[2]),.VAR38());
VAR35 VAR40 (... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_1.behavioral.pp.v | 1,311 | module MODULE1( VAR4, VAR7, VAR3, VAR2, VAR9, VAR8 );
input VAR4, VAR7, VAR3;
inout VAR9, VAR8;
output VAR2;
VAR6 VAR1(.VAR4(VAR4),.VAR7(VAR7),.VAR3(VAR3),.VAR2(VAR2),.VAR9(VAR9),.VAR8(VAR8));
VAR6 VAR5(.VAR4(VAR4),.VAR7(VAR7),.VAR3(VAR3),.VAR2(VAR2),.VAR9(VAR9),.VAR8(VAR8)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211o/sky130_fd_sc_hdll__a211o_2.v | 2,364 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR6 ,
VAR3 ,
VAR10 ,
VAR2,
VAR4,
VAR5 ,
VAR9
);
output VAR8 ;
input VAR11 ;
input VAR6 ;
input VAR3 ;
input VAR10 ;
input VAR2;
input VAR4;
input VAR5 ;
input VAR9 ;
VAR7 VAR1 (
.VAR8(VAR8),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22ai/sky130_fd_sc_hvl__o22ai.behavioral.pp.v | 2,170 | module MODULE1 (
VAR17 ,
VAR3 ,
VAR16 ,
VAR19 ,
VAR14 ,
VAR13,
VAR9,
VAR15 ,
VAR8
);
output VAR17 ;
input VAR3 ;
input VAR16 ;
input VAR19 ;
input VAR14 ;
input VAR13;
input VAR9;
input VAR15 ;
input VAR8 ;
wire VAR12 ;
wire VAR7 ;
wire VAR10 ;
wire VAR1;
nor VAR5 (VAR12 , VAR19, VAR14 );
nor VAR2 (VAR7 , VAR3, VAR16 )... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axis_broadcaster_v1_1/hdl/verilog/axis_broadcaster_v1_1_core.v | 8,713 | module MODULE1 #(
parameter VAR29 = "VAR37",
parameter integer VAR30 = 32,
parameter integer VAR13 = 1,
parameter integer VAR17 = 1,
parameter integer VAR12 = 1,
parameter [31:0] VAR25 = 32'hFF,
parameter integer VAR9 = 2
) (
input wire VAR51,
input wire VAR5,
input wire VAR53,
input wire VAR6,
output wire VAR41,
input... | gpl-3.0 |
UviDTE-UviSpace/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/avalon_camera.v | 8,705 | module MODULE1 (
input clk,
input VAR45,
input [4:0] VAR3,
input VAR7,
output reg [31:0] VAR16,
input VAR4,
input [31:0] VAR32,
output VAR24,
output [23:0] VAR9,
output [31:0] VAR37,
input VAR34,
input VAR38,
output [15:0] VAR5,
output [15:0] VAR26,
output [15:0] VAR8,
output [15:0] VAR29,
output [15:0] VAR17,
output [... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/FPU_Multiplication_Function.v | 10,256 | module MODULE1
wire VAR113; wire VAR114; wire VAR16;
wire VAR106;
wire VAR47;
wire VAR123;
wire VAR127;
wire VAR37;
wire [VAR62-1:0] VAR9;
wire [VAR62-1:0] VAR94;
wire VAR90;
wire [VAR107:0] VAR71;
wire [1:0] VAR93;
wire [VAR107-1:0] VAR6;
wire VAR129;
wire [VAR107:0] VAR30;
wire [2*VAR115+1:0] VAR100;
wire[VAR115:0] V... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController4L/src/m_axi_read.v | 9,665 | module MODULE1 # (
parameter VAR60 = 32,
parameter VAR27 = 64,
parameter VAR70 = 1,
parameter VAR50 = 1,
parameter VAR10 = 1
)
(
input VAR57,
input VAR71,
output [VAR70-1:0] VAR45,
output [VAR60-1:0] VAR67,
output [7:0] VAR6,
output [2:0] VAR42,
output [1:0] VAR66,
output [1:0] VAR18,
output [3:0] VAR35,
output [2:0] V... | gpl-3.0 |
osrf/wandrr | firmware/motor_controller/fpga/uart_tx.v | 1,637 | module MODULE1
parameter VAR5=8,
parameter VAR21=8) (input VAR13,
input [VAR21-1:0] in,
input VAR2,
output VAR15,
output out,
output VAR16);
wire VAR19, VAR25;
wire [VAR21+1:0] VAR18;
VAR23 #(VAR21+2) VAR10
(.VAR13(VAR13), .en(VAR19), .rst(1'b0), .VAR8(VAR18),
.VAR6(VAR25 ? {1'b1, in, 1'b0} : {1'b0, VAR18[VAR21+1:1]}))... | apache-2.0 |
azonenberg/antikernel-ipcores | debug/JtagUserIdentifier.v | 4,863 | module MODULE1 #(
parameter VAR21 = 24'h000000,
parameter VAR19 = 8'h00
)();
reg[31:0] VAR30 = 0;
wire VAR1;
wire VAR11;
wire VAR24;
wire VAR18;
wire VAR15;
VAR10 #(
.VAR29(1)
) VAR5 (
.VAR20(VAR1),
.VAR26(VAR24),
.VAR6(),
.VAR28(),
.VAR14(VAR11),
.VAR31(),
.VAR27(VAR18),
.VAR8(),
.VAR25(),
.VAR22(),
.VAR12(VAR30[0])
)... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isolatch/sky130_fd_sc_lp__isolatch.behavioral.pp.v | 1,881 | module MODULE1 (
VAR8 ,
VAR14 ,
VAR10,
VAR15 ,
VAR7 ,
VAR12 ,
VAR11 ,
VAR5
);
output VAR8 ;
input VAR14 ;
input VAR10;
input VAR15 ;
input VAR7 ;
input VAR12 ;
input VAR11 ;
input VAR5 ;
wire VAR1 ;
wire VAR3;
wire VAR13 ;
reg VAR6 ;
VAR4 VAR2 (VAR1 , VAR13, VAR3, VAR6, VAR15, VAR12, VAR7);
buf VAR9 (VAR8 , VAR1 );
end... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_bfm/bench/wb_master.v | 3,471 | module MODULE1
parameter VAR6 = 32,
parameter VAR11 = 0,
parameter VAR20 = 500)
(input VAR16,
input VAR19,
output [VAR15-1:0] VAR9,
output [VAR6-1:0] VAR5,
output [3:0] VAR10,
output VAR7,
output VAR4,
output VAR18,
output [2:0] VAR13,
output [1:0] VAR2,
input [VAR6-1:0] VAR17,
input VAR3,
input VAR1,
input VAR8);
inte... | gpl-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_hps_only_master_p2b_adapter.v | 1,341 | module MODULE1 (
input clk,
input VAR3,
output reg VAR2,
input VAR9,
input [ 7: 0] VAR1,
input VAR11,
input VAR4,
input VAR12,
output reg VAR5,
output reg [ 7: 0] VAR13,
output reg VAR7,
output reg VAR10,
output reg [ 7: 0] VAR8
);
reg VAR6 = 0;
always @* begin
VAR2 = VAR12;
VAR5 = VAR9;
VAR13 = VAR1;
VAR7 = VAR11;
VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4b/sky130_fd_sc_lp__or4b.pp.symbol.v | 1,318 | module MODULE1 (
input VAR7 ,
input VAR3 ,
input VAR5 ,
input VAR9 ,
output VAR1 ,
input VAR4 ,
input VAR2,
input VAR8,
input VAR6
);
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9361/axi_ad9361_tx.v | 11,317 | module MODULE1 (
VAR85,
VAR55,
VAR86,
VAR76,
VAR5,
VAR46,
VAR9,
VAR50,
VAR58,
VAR36,
VAR51,
VAR60,
VAR31,
VAR67,
VAR14,
VAR83,
VAR16,
VAR69,
VAR43,
VAR35,
VAR39,
VAR30,
VAR41,
VAR17,
VAR57,
VAR19,
VAR3,
VAR11,
VAR49,
VAR64,
VAR61,
VAR26,
VAR29,
VAR70,
VAR40,
VAR78,
VAR74,
VAR71,
VAR27);
parameter VAR52 = 0;
parameter V... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/CY7C1356C/cy1356.v | 12,138 | module MODULE1 ( VAR34, clk, VAR14, VAR18, VAR4, VAR24, VAR29, VAR40, VAR25, VAR42, VAR27, VAR12);
inout [VAR13:0] VAR34;
input clk, VAR4, VAR24, VAR29, VAR40, VAR25, VAR42, VAR27, VAR12; input [1:0] VAR18; input [18:0] VAR14;
reg VAR30; reg VAR50;
reg VAR36;
reg VAR15;
reg VAR6;
reg VAR53;
reg VAR32;
reg VAR10;
reg VA... | gpl-2.0 |
8l/kestrel | 2/nexys2/computer/M_mem.v | 6,476 | module MODULE1(
input [13:1] VAR21,
output [15:0] VAR62,
input VAR9,
input VAR58,
output VAR55,
input [13:1] VAR56,
output [15:0] VAR30,
input [15:0] VAR71,
input VAR64,
input VAR5,
input VAR13,
output VAR24,
input VAR40,
input VAR23
);
wire VAR57 = VAR9 & VAR58;
wire VAR46 = VAR5 & VAR13;
reg VAR22;
reg VAR54;
assign ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2/sky130_fd_sc_ls__and2_1.v | 2,086 | module MODULE2 (
VAR1 ,
VAR8 ,
VAR9 ,
VAR6,
VAR3,
VAR5 ,
VAR2
);
output VAR1 ;
input VAR8 ;
input VAR9 ;
input VAR6;
input VAR3;
input VAR5 ;
input VAR2 ;
VAR7 VAR4 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR1,
VAR8,
VAR9
);
output VAR1;
... | apache-2.0 |
hydai/Verilog-Practice | HardwareLab/Upload/101062124_戴宏穎_Lab8/GameCtr.v | 2,794 | module MODULE1(
output reg [3:0] VAR20,
output reg [3:0] VAR13,
output reg [15:0] VAR14,
input [3:0] VAR11,
input VAR8,
input VAR6,
input VAR7,
input VAR19,
input VAR18
);
parameter VAR4 = 2'b00;
parameter VAR12 = 2'b01;
parameter VAR17 = 2'b10;
reg [3:0] VAR1, VAR3;
wire [3:0]VAR2;
reg [1:0] VAR15, VAR10;
VAR9 VAR5(VA... | mit |
marmolejo/zet | cores/vga/rtl/fml/vga_pal_dac_fml.v | 4,746 | module MODULE1 (
input clk, input rst,
input VAR15,
input VAR42,
input VAR29,
input VAR19,
input VAR43,
input [7:0] VAR31,
input VAR13, input VAR10,
input [3:0] VAR35,
input VAR37,
output [7:0] VAR4,
input [7:0] VAR23,
input VAR8,
input [1:0] VAR6,
input [7:0] VAR40,
output [3:0] VAR17,
input [1:0] VAR5,
input [7:0] VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.blackbox.v | 1,485 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
wire VAR3;
supply1 VAR6 ;
supply0 VAR7 ;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31a/sky130_fd_sc_lp__o31a.functional.v | 1,425 | module MODULE1 (
VAR10 ,
VAR3,
VAR2,
VAR5,
VAR8
);
output VAR10 ;
input VAR3;
input VAR2;
input VAR5;
input VAR8;
wire VAR9 ;
wire VAR1;
or VAR4 (VAR9 , VAR2, VAR3, VAR5 );
and VAR7 (VAR1, VAR9, VAR8 );
buf VAR6 (VAR10 , VAR1 );
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_HLS_accel_0_0/synth/system_HLS_accel_0_0.v | 10,375 | module MODULE1 (
VAR12,
VAR24,
VAR36,
VAR39,
VAR26,
VAR7,
VAR16,
VAR29,
VAR13,
VAR40,
VAR32,
VAR28,
VAR22,
VAR33,
VAR8,
VAR37,
VAR30,
VAR3,
VAR41,
interrupt,
VAR4,
VAR25,
VAR19,
VAR14,
VAR11,
VAR35,
VAR5,
VAR1,
VAR10,
VAR31,
VAR23,
VAR17,
VAR20,
VAR6,
VAR38,
VAR15,
VAR18,
VAR34
);
input wire [4 : 0] VAR12;
input wire V... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1.functional.pp.v | 1,745 | module MODULE1( VAR9, VAR12, VAR1, VAR18, VAR14, VAR26, VAR16, VAR2, VAR25 );
input VAR18, VAR1, VAR14, VAR9, VAR12, VAR16, VAR2, VAR25;
output VAR26;
not VAR22( VAR13, VAR14 );
wire VAR17;
not VAR24( VAR17, VAR1 );
wire VAR20;
not VAR3( VAR20, VAR9 );
wire VAR23;
and VAR11( VAR23, VAR17, VAR20 );
wire VAR5;
not VAR6( ... | apache-2.0 |
Kipsora/MIPS-CPU | source/machine/cpu/stages/mem.v | 14,832 | module MODULE1(
input wire reset,
input wire VAR29,
input wire[VAR25] VAR20,
input wire[VAR17] VAR3,
input wire VAR16,
input wire[VAR17] VAR23,
input wire[VAR17] VAR1,
input wire[VAR28] VAR30,
input wire[VAR17] VAR5,
input wire[VAR17] VAR8,
input wire[VAR17] VAR13,
output reg VAR12,
output reg[VAR25] VAR11,
output reg[... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2.blackbox.v | 1,287 | module MODULE1 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
supply1 VAR1;
supply0 VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21a/sky130_fd_sc_hvl__o21a.pp.blackbox.v | 1,355 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR5 ,
VAR6 ,
VAR4,
VAR3,
VAR7 ,
VAR1
);
output VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR6 ;
input VAR4;
input VAR3;
input VAR7 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3b/sky130_fd_sc_lp__or3b.pp.symbol.v | 1,301 | module MODULE1 (
input VAR5 ,
input VAR3 ,
input VAR7 ,
output VAR4 ,
input VAR8 ,
input VAR1,
input VAR6,
input VAR2
);
endmodule | apache-2.0 |
wgml/sysrek | rgb2hsv/delay.v | 1,305 | module MODULE1 #
(
parameter VAR8 = 8,
parameter VAR6 = 0
)
(
input [VAR8 - 1:0] VAR5,
input VAR1,
input clk,
output [VAR8 - 1:0] VAR4
);
wire [VAR8 - 1:0] VAR2 [VAR6:0];
assign VAR2[0] = VAR5;
genvar VAR7;
generate
for(VAR7 = 0; VAR7 < VAR6; VAR7 = VAR7 + 1)
begin: VAR3
register #
(
.VAR8(VAR8)
)
VAR9
(
.clk(clk),
.VA... | gpl-2.0 |
pollow/Multi_Cycle_CPU | src/all.v | 20,423 | module MODULE1(
clk,
reset,
VAR28,
VAR24,
VAR22,
VAR20,
VAR29,
VAR16,
VAR33,
VAR4,
VAR34,
VAR13,
VAR14,
VAR30,
VAR3,
VAR2,
VAR5,
VAR27,
VAR11,
VAR26,
VAR32,
VAR1
);
input clk, reset;
input VAR28, VAR24, VAR22, VAR29, VAR33, VAR13, VAR14, VAR30;
input [1:0] VAR20, VAR16, VAR4, VAR34;
input [2:0] VAR3;
input [31:0] VAR5;... | gpl-3.0 |
zeldin/iceGDROM | fpga/source/vexriscv/vexriscv_wrapper.v | 8,199 | module MODULE1 (
input clk,
output VAR36,
inout[7:0] VAR9,
inout[7:0] VAR43,
input VAR15,
input VAR20,
output VAR23,
input VAR13,
output reg VAR3,
output wire[15:0] VAR16,
input wire[31:0] VAR4,
output wire[31:0] VAR53,
output wire VAR31,
output wire VAR8,
output wire[3:0] VAR44,
input wire VAR49
);
parameter VAR11 = 5... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/source/GDA_St_N8_M4_P2.v | 1,582 | module MODULE1(
input [7:0] VAR14,
input [7:0] VAR25,
output [8:0] VAR28
);
wire [2:0] VAR18, VAR33, VAR4, VAR8;
wire VAR15,VAR32,VAR2,VAR34;
wire VAR20;
wire VAR12;
and VAR16(VAR15,VAR14[0],VAR25[0]);
and VAR26(VAR32,VAR14[1],VAR25[1]);
xor VAR22(VAR2,VAR14[0],VAR25[0]);
xor VAR29(VAR34,VAR14[1],VAR25[1]);
and VAR5(VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.v | 2,262 | module MODULE1 (
VAR1,
VAR5 ,
VAR2,
VAR10 ,
VAR9,
VAR6,
VAR4 ,
VAR8
);
output VAR1;
input VAR5 ;
input VAR2;
input VAR10 ;
input VAR9;
input VAR6;
input VAR4 ;
input VAR8 ;
VAR7 VAR3 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapmet1/sky130_fd_sc_ms__tapmet1.behavioral.pp.v | 1,204 | module MODULE1 (
VAR4,
VAR1,
VAR3 ,
VAR2
);
input VAR4;
input VAR1;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
jotego/jt51 | ver/common/sep32.v | 3,670 | module MODULE1 #(parameter VAR7=10, parameter VAR2=5'd0)
(
input clk,
input VAR29,
input [VAR7-1:0] VAR4,
input [4:0] VAR5,
output reg [VAR7-1:0] VAR16,
output reg [VAR7-1:0] VAR11,
output reg [VAR7-1:0] VAR12,
output reg [VAR7-1:0] VAR24,
output reg [VAR7-1:0] VAR23,
output reg [VAR7-1:0] VAR8,
output reg [VAR7-1:0] V... | gpl-3.0 |
ncos/Xilinx-Verilog | GYRACC/src/GYRO/digit_select.v | 1,601 | module MODULE1(
VAR3,
VAR4,
VAR6,
VAR5,
VAR2,
VAR1
);
input [3:0] VAR3;
input [3:0] VAR4;
input [3:0] VAR6;
input [3:0] VAR5;
input [1:0] VAR2;
output [3:0] VAR1;
assign VAR1 = (VAR2 == 2'b11) ? VAR3 :
(VAR2 == 2'b10) ? VAR4 :
(VAR2 == 2'b01) ? VAR6 :
VAR5;
endmodule | mit |
Vadman97/ImageAES | vga/vga_bsprite.v | 2,261 | module MODULE1(hc, VAR19, VAR8, VAR6, VAR9, VAR14, VAR10, VAR23, VAR22);
input [10:0] hc, VAR19; input [7:0] VAR8; input VAR23;
output reg [14:0] VAR6; output reg [2:0] VAR9, VAR14;
output reg [1:0] VAR10; output reg VAR22;
parameter [10:0] VAR1 = 640;
parameter [10:0] VAR20 = 480;
parameter [7:0] VAR5 = 175;
parameter... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3/sky130_fd_sc_ms__or3.behavioral.pp.v | 1,801 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR3 ,
VAR14 ,
VAR12,
VAR9,
VAR6 ,
VAR10
);
output VAR8 ;
input VAR4 ;
input VAR3 ;
input VAR14 ;
input VAR12;
input VAR9;
input VAR6 ;
input VAR10 ;
wire VAR7 ;
wire VAR5;
or VAR2 (VAR7 , VAR3, VAR4, VAR14 );
VAR11 VAR1 (VAR5, VAR7, VAR12, VAR9);
buf VAR13 (VAR8 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkinvkapwr/sky130_fd_sc_hd__lpflow_clkinvkapwr.pp.symbol.v | 1,366 | module MODULE1 (
input VAR3 ,
output VAR7 ,
input VAR6,
input VAR1 ,
input VAR4 ,
input VAR2 ,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4b/sky130_fd_sc_hdll__or4b.pp.blackbox.v | 1,343 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR2 ,
VAR8 ,
VAR9 ,
VAR5,
VAR4,
VAR7 ,
VAR1
);
output VAR6 ;
input VAR3 ;
input VAR2 ;
input VAR8 ;
input VAR9 ;
input VAR5;
input VAR4;
input VAR7 ;
input VAR1 ;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_RKOA/integracion_fisica/front_end/source/RKOA_Recursive.v | 5,513 | module MODULE1
(
input wire [VAR1-1:0] VAR10,
input wire [VAR1-1:0] VAR11,
output reg [2*VAR1-1:0] VAR8
);
wire [1:0] VAR23;
wire [3:0] VAR30;
assign VAR23 = 2'b00;
assign VAR30 = 4'b0000;
wire [VAR1/2-1:0] VAR13;
wire [VAR1/2:0] VAR25;
wire [VAR1/2-3:0] VAR5;
wire [VAR1/2-4:0] VAR28;
reg [4*(VAR1/2)-1:0] VAR31 = 0;
as... | gpl-3.0 |
flycrow/pyxdl | logicanalyzer/serial_wb_top.v | 2,248 | module MODULE1(
input wire VAR39,VAR3,VAR2,
output wire VAR42,
input wire [31:0] VAR44,
output wire [31:0] VAR17,
output wire VAR14,
output wire VAR1,
input wire [31:0] VAR13,
output wire [31:0] VAR31,
input wire VAR26,
output wire [31:0] VAR32,
output wire VAR25,
input wire VAR23,
output wire VAR20,
input wire VAR4,
o... | gpl-2.0 |
peteg944/music-fpga | Experimental/Zedboard UART/SystolicFilter.v | 5,078 | module MODULE1(clk, VAR2, VAR7, VAR1);
input clk;
input VAR2;
reg VAR12;
wire VAR10;
input [15:0] VAR7;
output [15:0] VAR1;
wire [31:0] VAR11 [0:57+1];
wire [31:0] VAR5 [0:57+1];
reg [2:0] state;
localparam VAR6 = 3'd0,
VAR9 = 3'd1,
VAR4 = 3'd2,
VAR8 = 3'd3,
VAR3 = 3'd4; | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_vuaddp_ctl.v | 17,235 | module MODULE1
(
VAR59, VAR9, VAR101, VAR55, VAR62,
VAR22, VAR27, VAR114,
VAR84, VAR64, VAR109, VAR41,
VAR126, VAR87, VAR105, VAR33,
VAR124, VAR6, VAR19,
VAR43, VAR36, VAR104,
VAR95, VAR38, VAR30,
VAR40, VAR12, VAR31, VAR100, VAR11, VAR88,
VAR8, VAR90, VAR23,
VAR44, VAR4, VAR53, VAR14,
VAR94, VAR80, VAR72, VAR128,
VAR7... | gpl-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_081.v | 1,507 | module MODULE1 (
VAR13,
VAR10
);
input [31:0] VAR13;
output [31:0]
VAR10;
wire [31:0]
VAR9,
VAR7,
VAR11,
VAR5,
VAR6,
VAR8,
VAR14,
VAR1,
VAR4;
assign VAR9 = VAR13;
assign VAR11 = VAR7 - VAR9;
assign VAR7 = VAR9 << 10;
assign VAR1 = VAR9 << 4;
assign VAR8 = VAR9 << 8;
assign VAR5 = VAR9 << 6;
assign VAR4 = VAR14 - VAR1;
... | mit |
bigeagle/riffa | fpga/riffa_hdl/demux.v | 2,687 | module MODULE1
parameter VAR5 = 12,
parameter VAR3 = 1
)
(
input [VAR3-1:0] VAR7, input [VAR2(VAR5)-1:0] VAR6, output [VAR5*VAR3-1:0] VAR1 );
genvar VAR4;
reg [VAR5*VAR3-1:0] VAR8;
assign VAR1 = VAR8;
always @(*) begin
VAR8 = 0;
VAR8[VAR3*VAR6 +: VAR3] = VAR7;
end
endmodule | bsd-3-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodJSTK_v1_0/src/PmodJSTK_pmod_bridge_0_0/synth/PmodJSTK_pmod_bridge_0_0.v | 7,925 | module MODULE1 (
VAR63,
VAR49,
VAR52,
VAR33,
VAR59,
VAR32,
VAR70,
VAR22,
VAR24,
VAR37,
VAR26,
VAR29,
VAR20,
VAR9,
VAR66,
VAR64,
VAR7,
VAR43,
VAR36,
VAR38,
VAR68,
VAR2,
VAR5,
VAR48,
VAR72,
VAR55,
VAR28,
VAR56,
VAR46,
VAR42,
VAR1,
VAR21,
VAR67,
VAR17,
VAR73,
VAR71
);
output wire VAR63;
output wire VAR49;
output wire VAR5... | bsd-3-clause |
ankitshah009/Double_base_Number_system_parallel_adder | DBNS_Project_files_ISE/addn.v | 29,831 | module MODULE1(
VAR29,
VAR10,
VAR24,
VAR17,
VAR12,
VAR4,
VAR23,
VAR13,
VAR11,
VAR2,
VAR27,
VAR3,
VAR20,
VAR19,
VAR8,
VAR7,
VAR14,
VAR1,
VAR22
);
input [3:0] VAR29;
input [3:0] VAR10;
input [3:0] VAR24;
input [3:0] VAR17;
input [3:0] VAR12;
input [3:0] VAR4;
input [3:0] VAR23;
input [3:0] VAR13;
input [3:0] VAR11;
input... | apache-2.0 |
efabless/openlane | designs/cic_decimator/src/cic_decimator.v | 4,852 | module MODULE1 #(
parameter VAR13 = 16,
parameter VAR22 = 2,
parameter VAR6 = 1,
parameter VAR1 = 2,
parameter VAR17 = VAR13+VAR20((VAR22*VAR6)**VAR1)
)
(
input wire clk,
input wire rst,
input wire [VAR13-1:0] VAR15,
input wire VAR24,
output wire VAR4,
output wire [VAR17-1:0] VAR11,
output wire VAR14,
input wire VAR10,... | apache-2.0 |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/1a38f03650b0a66f/mult16_16_stub.v | 1,311 | module MODULE1(VAR1, VAR4, VAR2, VAR3)
;
input VAR1;
input [15:0]VAR4;
input [15:0]VAR2;
output [7:0]VAR3;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221o/sky130_fd_sc_ms__a221o.functional.pp.v | 2,199 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR18 ,
VAR8 ,
VAR2 ,
VAR1 ,
VAR3,
VAR7,
VAR16 ,
VAR11
);
output VAR9 ;
input VAR5 ;
input VAR18 ;
input VAR8 ;
input VAR2 ;
input VAR1 ;
input VAR3;
input VAR7;
input VAR16 ;
input VAR11 ;
wire VAR13 ;
wire VAR6 ;
wire VAR17 ;
wire VAR14;
and VAR20 (VAR13 , VAR8, VAR2 );
and VAR12 (VAR6 ... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/8d6f9c45e1ea3378/zynq_design_1_auto_pc_1_stub.v | 5,767 | module MODULE1(VAR79, VAR21, VAR19, VAR39,
VAR33, VAR44, VAR49, VAR63, VAR69, VAR58,
VAR46, VAR76, VAR14, VAR23, VAR71, VAR11, VAR38,
VAR34, VAR67, VAR47, VAR32, VAR43, VAR26, VAR25,
VAR35, VAR54, VAR65, VAR66, VAR77, VAR51,
VAR62, VAR78, VAR68, VAR37, VAR70, VAR7, VAR18,
VAR12, VAR42, VAR15, VAR56, VAR13, VAR4, VAR55,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux4/sky130_fd_sc_hd__mux4.pp.symbol.v | 1,376 | module MODULE1 (
input VAR1 ,
input VAR8 ,
input VAR4 ,
input VAR2 ,
output VAR6 ,
input VAR7 ,
input VAR11 ,
input VAR5 ,
input VAR3,
input VAR10,
input VAR9
);
endmodule | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/acl_ic_wrp_reg.v | 1,349 | module MODULE1
(
input logic VAR6,
input logic VAR2,
VAR7 VAR3,
VAR7 VAR4
);
always @(posedge VAR6 or negedge VAR2)
if( ~VAR2 ) begin
VAR4.ack <= 1'b0;
VAR4.VAR5 <= 'VAR1;
end
else begin
VAR4.ack <= VAR3.ack;
VAR4.VAR5 <= VAR3.VAR5;
end
endmodule | mit |
P3Stor/P3Stor | DDR3/controller/arb_select.v | 19,071 | module MODULE1 #
(
parameter VAR76 = 100,
parameter VAR39 = "1T",
parameter VAR14 = 11,
parameter VAR41 = 3,
parameter VAR74 = "8",
parameter VAR12 = 4,
parameter VAR104 = 31,
parameter VAR95 = 8,
parameter VAR68 = "VAR27",
parameter VAR101 = "VAR38",
parameter VAR112 = "VAR38",
parameter VAR23 = 4,
parameter VAR109 = ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxtp/sky130_fd_sc_ls__sedfxtp.functional.pp.v | 2,122 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR10 ,
VAR2 ,
VAR19 ,
VAR4 ,
VAR6,
VAR12,
VAR7 ,
VAR9
);
output VAR5 ;
input VAR3 ;
input VAR10 ;
input VAR2 ;
input VAR19 ;
input VAR4 ;
input VAR6;
input VAR12;
input VAR7 ;
input VAR9 ;
wire VAR13 ;
wire VAR8;
wire VAR15 ;
VAR16 VAR17 (VAR8, VAR15, VAR19, VAR4 );
VAR16 VAR14 (VAR15 , ... | apache-2.0 |
secworks/aes | src/rtl/aes_key_mem.v | 12,766 | module MODULE1(
input wire clk,
input wire VAR62,
input wire [255 : 0] VAR69,
input wire VAR2,
input wire VAR36,
input wire [3 : 0] VAR65,
output wire [127 : 0] VAR5,
output wire ready,
output wire [31 : 0] VAR60,
input wire [31 : 0] VAR27
);
localparam VAR13 = 1'h0;
localparam VAR34 = 1'h1;
localparam VAR11 = 10;
loca... | bsd-2-clause |
keith-epidev/VHDL-lib | top/mono_radio/ip/fir_lp_15kHz_0/fir_lp_15kHz_stub.v | 1,495 | module MODULE1(VAR3, VAR2, VAR6, VAR1, VAR4, VAR5)
;
input VAR3;
input VAR2;
output VAR6;
input [15:0]VAR1;
output VAR4;
output [47:0]VAR5;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22oi/sky130_fd_sc_hvl__a22oi.pp.blackbox.v | 1,397 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR2 ,
VAR9,
VAR6,
VAR8 ,
VAR1
);
output VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR2 ;
input VAR9;
input VAR6;
input VAR8 ;
input VAR1 ;
endmodule | apache-2.0 |
omicronns/studies-sys-rek | lab4/abc/src/abc.v | 1,475 | module MODULE1(
input clk,
input VAR6,
input [11:0] VAR11,
input [11:0] VAR8,
input [11:0] VAR12,
output [24:0] VAR15
);
wire signed [12:0] VAR13;
wire signed [11:0] VAR9;
VAR16 #(
.VAR14(2),
.VAR10(12)
) VAR3 (
.clk(clk),
.VAR6(VAR6),
.in(VAR12),
.out(VAR9),
.rst(0)
);
sum VAR2 (
.VAR11(VAR11), .VAR8(VAR8), .clk(clk),... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4b/sky130_fd_sc_hd__nand4b.behavioral.pp.v | 1,998 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR7 ,
VAR6 ,
VAR11 ,
VAR14,
VAR9,
VAR2 ,
VAR4
);
output VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR6 ;
input VAR11 ;
input VAR14;
input VAR9;
input VAR2 ;
input VAR4 ;
wire VAR1 ;
wire VAR10 ;
wire VAR12;
not VAR17 (VAR1 , VAR3 );
nand VAR16 (VAR10 , VAR11, VAR6, VAR7, VAR1 );
VAR15 VAR13... | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_rfram_generic.v | 10,468 | module MODULE1(
clk, rst,
VAR11, VAR7, VAR2,
VAR17, VAR1, VAR12,
VAR8, VAR9, VAR14, VAR15
);
parameter VAR16 = VAR6;
parameter VAR5 = VAR13;
input clk;
input rst;
input VAR11;
input [VAR5-1:0] VAR7;
output [VAR16-1:0] VAR2;
input VAR17;
input [VAR5-1:0] VAR1;
output [VAR16-1:0] VAR12;
input VAR8;
input VAR9;
input [VAR... | gpl-2.0 |
oddball/genMem | vendorMemModels/someTwoPortVendorMem_128_8_0.v | 1,127 | module MODULE1 (VAR15,
VAR7,
VAR3,
VAR14,
VAR12,
VAR2,
VAR11,
VAR1,
VAR13,
VAR9,
VAR10,
VAR6,
VAR8,
VAR4);
output [7:0] VAR15;
input VAR7;
input VAR3;
input VAR14;
input [6:0] VAR12;
input [7:0] VAR2;
input VAR11;
output [7:0] VAR1;
input VAR13;
input VAR9;
input VAR10;
input [6:0] VAR6;
input [7:0] VAR8;
input VAR4;
r... | lgpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/Count_Up_Down.v | 2,359 | module MODULE1
(
VAR3,
reset,
VAR11,
VAR1,
VAR8,
VAR2
);
input VAR3;
input reset;
input VAR11;
input VAR1;
input [7:0] VAR8; output VAR2;
reg VAR6;
reg [7:0] VAR10; reg VAR12;
reg VAR9;
reg [7:0] VAR5; reg VAR4;
reg [8:0] VAR7;
always @(posedge VAR3)
begin : VAR13
if (reset == 1'b1) begin
VAR6 <= 1'b0;
VAR10 <= 8'd0;
V... | gpl-3.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_dc_top.v | 10,592 | module MODULE1(
clk, rst,
VAR19, VAR50, VAR42, VAR76, VAR7, VAR53, VAR10,
VAR3, VAR52, VAR11,
VAR35,
VAR62, VAR24, VAR59,
VAR2, VAR29, VAR39, VAR56,
VAR70, VAR46, VAR14, VAR37, VAR32,
VAR1, VAR47, VAR17,
VAR45, VAR28, VAR75
);
parameter VAR58 = VAR69;
input clk;
input rst;
output [VAR58-1:0] VAR19;
output [31:0] VAR50;... | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/if_reg.v | 1,104 | module MODULE1 (
input wire clk,
input wire reset,
input wire [VAR3] VAR9,
input wire VAR17,
input wire VAR4,
input wire [VAR12] VAR1,
input wire VAR6,
input wire [VAR12] VAR16,
output reg [VAR12] VAR11,
output reg [VAR3] VAR7,
output reg VAR5
);
always @(posedge clk or VAR13 reset) begin
if (reset == VAR10) begin
VAR1... | apache-2.0 |
ZiCog/xoro | qram32_bb.v | 6,095 | module MODULE1 (
address,
VAR4,
VAR3,
VAR5,
VAR2,
VAR1);
input [13:0] address;
input [3:0] VAR4;
input VAR3;
input [31:0] VAR5;
input VAR2;
output [31:0] VAR1;
tri1 [3:0] VAR4;
tri1 VAR3;
endmodule | mit |
wgml/sysrek | skin_color_segm/delayLinieBRAM_WP.v | 1,476 | module MODULE1
VAR7 = 10
)
(
input clk,
input rst,
input VAR10,
input [VAR9-1:0] din ,
output[VAR9-1:0] dout,
input [VAR7-1:0] VAR1
);
reg [VAR7-1:0] VAR3 = 0;
wire [16:0] VAR12;
wire [16:0] VAR11;
always @(posedge clk)
begin
if ( VAR10 == 1'b1)
begin
if (rst == 1'b1)
begin
VAR3 <= 0;
end
else
begin
VAR3 <= VAR3+1;
if ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai.pp.blackbox.v | 1,408 | module MODULE1 (
VAR3 ,
VAR7,
VAR2,
VAR6 ,
VAR1 ,
VAR9,
VAR4,
VAR5 ,
VAR8
);
output VAR3 ;
input VAR7;
input VAR2;
input VAR6 ;
input VAR1 ;
input VAR9;
input VAR4;
input VAR5 ;
input VAR8 ;
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/4-way/ise/ipcore_dir/dram/user_design/rtl/ip_top/mig_7series_v1_9_memc_ui_top_std.v | 36,359 | module MODULE1 #
(
parameter VAR106 = 100,
parameter VAR260 = 64,
parameter VAR152 = "VAR242",
parameter VAR231 = "0", parameter VAR233 = 3, parameter VAR274 = 2, parameter VAR299 = "8", parameter VAR9 = "VAR198", parameter VAR51 = "VAR150", parameter VAR74 = 1, parameter VAR262 = 5,
parameter VAR8 = 12, parameter VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2b/sky130_fd_sc_ms__or2b_4.v | 2,127 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR2 ,
VAR5,
VAR9,
VAR6 ,
VAR1
);
output VAR8 ;
input VAR4 ;
input VAR2 ;
input VAR5;
input VAR9;
input VAR6 ;
input VAR1 ;
VAR3 VAR7 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR8 ,
VAR4 ,
VAR2
);
output VAR8... | apache-2.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkDM_System_Bus.v | 56,921 | module MODULE1(VAR18,
VAR265,
VAR115,
VAR73,
VAR50,
VAR108,
VAR208,
VAR216,
VAR203,
VAR157,
VAR198,
VAR38,
VAR106,
VAR41,
VAR263,
VAR223,
VAR196,
VAR59,
VAR253,
VAR192,
VAR9,
VAR211,
VAR111,
VAR180,
VAR13,
VAR205,
VAR188,
VAR190,
VAR90,
VAR91,
VAR247,
VAR261,
VAR3,
VAR163,
VAR153,
VAR267,
VAR197,
VAR64,
VAR155,
VAR12,
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22oi/sky130_fd_sc_ms__a22oi.behavioral.pp.v | 2,164 | module MODULE1 (
VAR11 ,
VAR6 ,
VAR13 ,
VAR1 ,
VAR18 ,
VAR5,
VAR16,
VAR12 ,
VAR14
);
output VAR11 ;
input VAR6 ;
input VAR13 ;
input VAR1 ;
input VAR18 ;
input VAR5;
input VAR16;
input VAR12 ;
input VAR14 ;
wire VAR10 ;
wire VAR3 ;
wire VAR4 ;
wire VAR7;
nand VAR19 (VAR10 , VAR13, VAR6 );
nand VAR2 (VAR3 , VAR18, VAR1 ... | apache-2.0 |
scollinson/xc3sprog | bscan_spi/xc3s250e_godil.v | 1,777 | module MODULE1
(
output wire VAR38,
output wire VAR16,
output wire VAR33,
input VAR9
);
wire VAR41;
wire VAR17;
wire VAR22;
wire VAR37;
reg [47:0] VAR25;
reg [15:0] VAR2;
reg VAR21 = 0;
assign VAR38 = VAR22 ;
wire VAR35;
wire VAR18;
wire VAR20;
reg VAR26 = 0;
reg VAR32 = 0;
reg VAR1 = 0;
reg VAR27 = 0;
reg [13:0] VAR39... | gpl-2.0 |
mda-ut/Tempest | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/slave_controller.v | 1,844 | module MODULE1(input clk, input reset, input VAR9, input write, input [3:0]addr, input [31:0] VAR1, output [23:0] VAR3);
reg [11:0] in = 12'd0;
reg [6*VAR6-1:0] VAR2 = 0;
reg [15:0] period = 16'd0;
always @(posedge clk)
if (VAR9 & write)
casex (addr)
4'b0000:
in[1:0] <= VAR1[1:0];
4'b0001:
in[3:2] <= VAR1[1:0];
4'b0010... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/maj3/sky130_fd_sc_lp__maj3_2.v | 2,174 | module MODULE2 (
VAR2 ,
VAR4 ,
VAR3 ,
VAR5 ,
VAR10,
VAR9,
VAR6 ,
VAR7
);
output VAR2 ;
input VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR10;
input VAR9;
input VAR6 ;
input VAR7 ;
VAR1 VAR8 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
dutra/vgacontroller | pll.v | 15,424 | module MODULE1 (
input wire VAR3, input wire rst, output wire VAR4, output wire VAR2 );
VAR5 VAR1 (
.VAR3 (VAR3), .rst (rst), .VAR4 (VAR4), .VAR2 (VAR2) );
endmodule | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/pcie_bram_v6.v | 11,310 | module MODULE1
parameter VAR13 = 0, parameter VAR4 = 0 )
(
input VAR15, input VAR7,
input VAR17, input [12:0] VAR1, input [VAR4 - 1:0] VAR11,
input VAR9, input VAR6, input [12:0] VAR14,
output [VAR4 - 1:0] VAR18 );
localparam VAR5 = ((VAR4 == 4) ? 12 :
(VAR4 == 9) ? 11 :
(VAR4 == 18) ? 10 :
(VAR4 == 36) ? 9 :
8
);
loca... | mit |
hoglet67/CoPro6502 | src/Tube/hp_byte.v | 2,519 | module MODULE1 (
input VAR15,
input VAR6,
input VAR5,
input VAR3,
input [7:0] VAR16,
input VAR18,
input VAR14,
input VAR21,
output [7:0] VAR2,
output VAR11,
output VAR8
);
reg [7:0] VAR23 ;
wire [7:0] VAR13 ;
assign VAR2 = VAR23;
assign VAR13 = ( VAR5 & !VAR6 ) ? VAR16 : VAR23;
VAR20 VAR7 (
.VAR10(VAR15),
.VAR22( VAR6)... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ha/sky130_fd_sc_hd__ha.pp.symbol.v | 1,269 | module MODULE1 (
input VAR4 ,
input VAR6 ,
output VAR5,
output VAR7 ,
input VAR1 ,
input VAR8,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_4.behavioral.pp.v | 8,324 | module MODULE1( VAR10, VAR12, VAR3, VAR4, VAR6, VAR5, VAR9, VAR7, VAR11 );
input VAR9, VAR5, VAR10, VAR3, VAR12, VAR6;
inout VAR7, VAR11;
output VAR4;
VAR1 VAR2(.VAR10(VAR10),.VAR12(VAR12),.VAR3(VAR3),.VAR4(VAR4),.VAR6(VAR6),.VAR5(VAR5),.VAR9(VAR9),.VAR7(VAR7),.VAR11(VAR11));
VAR1 VAR8(.VAR10(VAR10),.VAR12(VAR12),.VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.symbol.v | 1,478 | module MODULE1 (
input VAR5 ,
output VAR4 ,
input VAR7 ,
input VAR2 ,
input VAR6,
input VAR3 ,
input VAR1
);
endmodule | apache-2.0 |
petrmikheev/miksys | verilog/MULT_bb.v | 3,690 | module MODULE1 (
VAR2,
VAR3,
VAR1);
input [16:0] VAR2;
input [16:0] VAR3;
output [33:0] VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21ai/sky130_fd_sc_hvl__o21ai.blackbox.v | 1,338 | module MODULE1 (
VAR7 ,
VAR3,
VAR6,
VAR2
);
output VAR7 ;
input VAR3;
input VAR6;
input VAR2;
supply1 VAR8;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_ctrl.v | 23,934 | module MODULE1(
clk, rst,
VAR17, VAR40, VAR13, VAR101, VAR35, VAR76, VAR23, VAR2,
VAR70, VAR90, VAR14, VAR49, VAR52, VAR53, VAR80, VAR57, VAR1, VAR21,
VAR88, VAR7, VAR28, VAR16, VAR50, VAR65, VAR92,
VAR112, VAR66,
VAR30, VAR68, VAR72, VAR74, VAR5, VAR22,
VAR109, VAR63, VAR81, VAR107, VAR86, VAR56, VAR85
);
input clk;
i... | gpl-3.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/NIOS_Sys_performance_counter.v | 8,115 | module MODULE1 (
address,
VAR6,
clk,
VAR15,
write,
VAR5,
VAR26
)
;
output [ 31: 0] VAR26;
input [ 3: 0] address;
input VAR6;
input clk;
input VAR15;
input write;
input [ 31: 0] VAR5;
wire VAR28;
reg [ 63: 0] VAR20;
reg [ 63: 0] VAR9;
reg [ 63: 0] VAR7;
reg [ 63: 0] VAR2;
wire VAR25;
wire VAR10;
wire VAR22;
wire VAR19;
... | gpl-2.0 |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_slice_17_13_0/RAT_slice_17_13_0_stub.v | 1,226 | module MODULE1(VAR1, VAR2)
;
input [17:0]VAR1;
output [1:0]VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32ai/sky130_fd_sc_ms__o32ai_1.v | 2,441 | module MODULE1 (
VAR12 ,
VAR8 ,
VAR1 ,
VAR3 ,
VAR2 ,
VAR7 ,
VAR5,
VAR4,
VAR6 ,
VAR9
);
output VAR12 ;
input VAR8 ;
input VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR5;
input VAR4;
input VAR6 ;
input VAR9 ;
VAR10 VAR11 (
.VAR12(VAR12),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_logic_analyzer/rtl/logic_analyzer.v | 6,379 | module MODULE1 # (
parameter VAR36 = 32,
parameter VAR10 = 10
) (
input clk,
input rst,
input VAR1,
input VAR52,
input [31:0] VAR7,
input [31:0] VAR13,
input [31:0] VAR41,
input [31:0] VAR25,
input [31:0] VAR38,
input [31:0] VAR22,
input [31:0] VAR28,
input VAR55,
input VAR4,
input VAR27,
output reg [31:0] VAR37,
outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21bo/sky130_fd_sc_hd__a21bo_4.v | 2,318 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR7 ,
VAR6,
VAR8,
VAR4,
VAR2 ,
VAR1
);
output VAR9 ;
input VAR10 ;
input VAR7 ;
input VAR6;
input VAR8;
input VAR4;
input VAR2 ;
input VAR1 ;
VAR3 VAR5 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4bb/sky130_fd_sc_ms__nor4bb.behavioral.pp.v | 1,998 | module MODULE1 (
VAR17 ,
VAR11 ,
VAR1 ,
VAR15 ,
VAR5 ,
VAR7,
VAR16,
VAR6 ,
VAR4
);
output VAR17 ;
input VAR11 ;
input VAR1 ;
input VAR15 ;
input VAR5 ;
input VAR7;
input VAR16;
input VAR6 ;
input VAR4 ;
wire VAR10 ;
wire VAR9 ;
wire VAR12;
nor VAR3 (VAR10 , VAR11, VAR1 );
and VAR13 (VAR9 , VAR10, VAR15, VAR5 );
VAR8 VA... | apache-2.0 |
tmolteno/TART | hardware/FPGA/fifo/fifo_dc_gray.v | 9,854 | module MODULE1 (
VAR13,
VAR33,
rst,
VAR20,
din,
VAR15,
dout,
VAR26,
VAR4,
VAR34,
VAR39,
VAR32
);
parameter VAR19=16;
parameter VAR29=4;
parameter VAR36=16;
input VAR13, VAR33, rst, VAR20;
input [VAR19-1:0] din;
input VAR15;
output [VAR19-1:0] dout;
input VAR26;
output VAR4;
output VAR34;
output [1:0] VAR39;
output [1:0... | lgpl-3.0 |
rkrajnc/minimig-mist | rtl/minimig/minimig_m68k_bridge.v | 10,265 | module MODULE1
(
input clk, input VAR54,
input VAR50,
input VAR52,
input VAR53, input VAR21, input [9:0] VAR1, input VAR17, input VAR20, input VAR44, input VAR11, input VAR40, output VAR22, input VAR7, input VAR10, input [3:0] VAR33, output reg VAR8, input VAR31, input VAR55, input VAR38, input VAR6, output VAR9, outpu... | gpl-3.0 |
MeshSr/onetswitch30 | ons30-app21-ref_switch/vivado/onets_7030_4x_ref_switch/ip/ref_switch_core/src/udp/output_queues.v | 9,186 | module MODULE1
parameter VAR1=VAR89/8,
parameter VAR70 = 2,
parameter VAR25 = 4,
parameter VAR53 = 8)
( output [VAR89-1:0] VAR37,
output [VAR1-1:0] VAR14,
input VAR31,
output reg VAR29,
output [VAR89-1:0] VAR44,
output [VAR1-1:0] VAR90,
input VAR32,
output reg VAR61,
output [VAR89-1:0] VAR2,
output [VAR1-1:0] VAR19,
in... | lgpl-2.1 |
alexforencich/xfcp | lib/eth/rtl/ip_eth_tx.v | 19,179 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR26,
output wire VAR30,
input wire [47:0] VAR13,
input wire [47:0] VAR39,
input wire [15:0] VAR53,
input wire [5:0] VAR32,
input wire [1:0] VAR44,
input wire [15:0] VAR68,
input wire [15:0] VAR19,
input wire [2:0] VAR43,
input wire [12:0] VAR69,
input wire [... | mit |
tuura/fantasi | dependencies/Altera_DE4/niosII/synthesis/submodules/system1_input0.v | 1,892 | module MODULE1 (
address,
clk,
VAR3,
VAR2,
VAR6
)
;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input clk;
input [ 31: 0] VAR3;
input VAR2;
wire VAR4;
wire [ 31: 0] VAR1;
wire [ 31: 0] VAR5;
reg [ 31: 0] VAR6;
assign VAR4 = 1;
assign VAR5 = {32 {(address == 0)}} & VAR1;
always @(posedge clk or negedge VAR2)
begin
if (... | mit |
DreamSourceLab/DSLogic-hdl | src/trigger.v | 52,709 | module MODULE1(
input VAR424,
input VAR347,
input VAR128,
input VAR373,
input [3:0] VAR264,
input [1:0] VAR350,
input VAR35,
input VAR124,
input VAR143,
input VAR109,
input VAR31,
input [15:0] VAR48,
input [15:0] VAR297,
input [15:0] VAR310,
input [15:0] VAR390,
input [1:0] VAR270,
input VAR32,
input VAR213,
input [15:... | gpl-2.0 |
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