repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2_1.v | 2,037 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR3,
VAR4
);
output VAR6 ;
input VAR1 ;
input VAR3;
input VAR4;
VAR2 VAR5 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR3;
supply0 VAR4;
VAR2 VAR5 (
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3b/sky130_fd_sc_hdll__nor3b.blackbox.v | 1,339 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR6 ,
VAR7
);
output VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR7;
supply1 VAR5;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31ai/sky130_fd_sc_lp__o31ai_m.v | 2,332 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR4 ,
VAR2 ,
VAR6 ,
VAR1,
VAR5,
VAR8 ,
VAR9
);
output VAR3 ;
input VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR1;
input VAR5;
input VAR8 ;
input VAR9 ;
VAR11 VAR10 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(V... | apache-2.0 |
briburrell/amica | device/scrypt_salsa8/salsaengine.v | 20,388 | module MODULE1 (VAR95, reset, din, dout, VAR46, VAR11, VAR4, VAR42 );
input VAR95;
input reset; input VAR46;
input VAR11; output VAR4;
output reg VAR42 = 1'b0;
parameter VAR50 = 8; input [VAR50-1:0] din;
output [VAR50-1:0] dout;
parameter VAR58 = 11;
parameter VAR8 = 8;
function integer VAR5; input integer VAR67;
begin... | gpl-3.0 |
jordens/redpid | verilog/red_pitaya_asg_ch.v | 6,757 | module MODULE1
parameter VAR28 = 14
)
(
output reg [ 14-1: 0] VAR5 , input VAR31 , input VAR2 ,
input VAR21 , input VAR38 , input [ 3-1: 0] VAR23 , output VAR29 ,
input VAR19 , input [ 14-1: 0] VAR34 , input [ 14-1: 0] VAR8 , output reg [ 14-1: 0] VAR1 , output reg [VAR28-1: 0] VAR11 ,
input [VAR28+15: 0] VAR37 , input... | gpl-3.0 |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/Rasterizer.v | 48,231 | module MODULE1
VAR4=0, VAR221=0)
(
input wire VAR218,
input wire VAR187,
input wire VAR61,
input wire VAR223,
output reg VAR235,
input wire VAR186,
input wire [63:0] VAR115,
output reg VAR243,
output reg VAR50,
input wire VAR201,
output reg [28:0] VAR102,
output wire [7:0] VAR65,
input wire VAR117,
input wire [63:0] VA... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_qspi_4cs_top.v | 8,260 | module MODULE1(
input clk,
input VAR68,
input VAR35,
output VAR12,
input [32-1:0] VAR55,
input VAR21,
input [32-1:0] VAR56,
output VAR54,
input VAR16,
output [32-1:0] VAR17,
output VAR27,
input VAR38,
output VAR65,
output VAR8,
input VAR46,
output VAR18,
output VAR45,
input VAR10,
output VAR6,
output VAR62,
input VAR49... | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/ip/SOC/submodules/SOC_NIOS_II_jtag_debug_module_tck.v | 8,047 | module MODULE1 (
VAR11,
VAR8,
VAR10,
VAR22,
VAR19,
VAR37,
VAR32,
VAR18,
VAR25,
VAR33,
VAR7,
VAR34,
VAR28,
VAR36,
VAR4,
VAR26,
VAR40,
VAR31,
VAR5,
VAR23,
VAR27,
VAR39,
VAR30,
VAR9,
VAR20,
VAR3,
VAR29,
VAR24,
VAR16,
VAR14,
VAR21
)
;
output [ 1: 0] VAR29;
output VAR24;
output [ 37: 0] VAR16;
output VAR14;
output VAR21;
in... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311oi/sky130_fd_sc_ls__a311oi.pp.symbol.v | 1,402 | module MODULE1 (
input VAR2 ,
input VAR1 ,
input VAR7 ,
input VAR10 ,
input VAR8 ,
output VAR4 ,
input VAR5 ,
input VAR6,
input VAR9,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbp/sky130_fd_sc_hs__dlxbp.functional.pp.v | 1,756 | module MODULE1 (
VAR7,
VAR10,
VAR2 ,
VAR4 ,
VAR1 ,
VAR13
);
input VAR7;
input VAR10;
output VAR2 ;
output VAR4 ;
input VAR1 ;
input VAR13;
wire VAR11 VAR6;
wire VAR11 VAR12 ;
wire VAR11 ;
VAR9 VAR14 VAR3 (VAR11 , VAR1, VAR13, VAR7, VAR10);
buf VAR5 (VAR2 , VAR11 );
not VAR8 (VAR4 , VAR11 );
endmodule | apache-2.0 |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux2x1_8_0_0/RAT_Mux2x1_8_0_0_stub.v | 1,275 | module MODULE1(VAR4, VAR2, VAR1, VAR3)
;
input [7:0]VAR4;
input [7:0]VAR2;
input VAR1;
output [7:0]VAR3;
endmodule | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcomms2_pr/common/prcfg_system_top.v | 5,037 | module MODULE1 (
clk,
VAR27,
VAR4,
VAR26,
VAR22,
VAR9,
VAR5,
VAR14,
VAR12,
VAR3,
VAR2,
VAR7,
VAR8,
VAR20,
VAR17,
VAR11,
VAR21,
VAR25,
VAR6,
VAR13,
VAR10
);
input clk;
input [31:0] VAR26;
output [31:0] VAR22;
input [31:0] VAR27;
output [31:0] VAR4;
output VAR9;
input VAR5;
input [63:0] VAR14;
input VAR12;
input VAR3;
ou... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4_1.v | 2,275 | module MODULE1 (
VAR9 ,
VAR11 ,
VAR8 ,
VAR10 ,
VAR4 ,
VAR3,
VAR5,
VAR2 ,
VAR1
);
output VAR9 ;
input VAR11 ;
input VAR8 ;
input VAR10 ;
input VAR4 ;
input VAR3;
input VAR5;
input VAR2 ;
input VAR1 ;
VAR6 VAR7 (
.VAR9(VAR9),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b_4.v | 2,147 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR9 ,
VAR3,
VAR2,
VAR7 ,
VAR1
);
output VAR8 ;
input VAR4 ;
input VAR9 ;
input VAR3;
input VAR2;
input VAR7 ;
input VAR1 ;
VAR5 VAR6 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR8 ,
VAR4,
VAR9
);
output VAR8 ... | apache-2.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_s_w_channel.v | 29,130 | module MODULE1 #(
parameter VAR80 = 32'hffffffff,
parameter VAR136 = 32'h00000000,
parameter VAR148 = 1 ,
parameter VAR9 = 32 ,
parameter VAR221 = 8 ,
parameter VAR12 = 1 ,
parameter VAR102 = 0 ,
parameter VAR108 = 1 ,
parameter VAR183 = 0
) (
input VAR182 ,
input VAR69 ,
input [VAR148-1:0] VAR78 ,
input [31:0] VAR48 ,... | mit |
P3Stor/P3Stor | ftl/Dynamic_Controller/code/Scheduler.v | 8,206 | module MODULE1(clk,VAR28,
VAR2,VAR15,VAR18,VAR17,VAR9,VAR30,VAR19,VAR12,VAR35,VAR1,
VAR22,VAR32,VAR6,VAR26,VAR27,VAR31,
VAR21
);
input clk;input VAR28;
output reg VAR2;
output reg [3:0] VAR15;
output reg VAR18;
output reg [2:0] VAR17;
input VAR9;
input [ 127: 0] VAR30;
output reg [3:0] VAR19;
output reg VAR12;
input VA... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/rtl_model/ram_dp_be.v | 4,855 | module MODULE1 (
VAR23 ,
VAR25 ,
VAR12 ,
VAR5 ,
VAR7 ,
VAR16 ,
VAR9 ,
VAR8 ,
VAR26 ,
VAR10 ,
VAR14 ,
VAR17 ,
VAR21 ,
VAR1
);
parameter VAR11=32;
parameter VAR18=8;
localparam VAR6=(VAR11>>3);
input VAR23; input VAR25; input VAR12; input [VAR6-1:0] VAR5; input [VAR18-1:0] VAR7; input [VAR11-1:0] VAR9; output [VAR11-1:0]... | gpl-3.0 |
jeffkub/n64-cart-reader | old/n64cartridge/src/sdram/sdram_controller.v | 11,262 | module MODULE1 (
VAR43, VAR37, VAR68, VAR60, VAR53,
VAR57, VAR67, VAR46, VAR45,
VAR22, VAR23, VAR25, VAR1, VAR69,
VAR58, VAR21,
VAR35,
VAR61,
VAR11,
VAR9,
VAR13, VAR8, VAR52, VAR75, VAR24,
VAR3, VAR39, VAR33, VAR55, VAR74, VAR72, VAR73, VAR44
);
input [26:0] VAR13; input VAR8; input VAR52; input VAR75; input VAR24; inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxbp/sky130_fd_sc_hd__sdfxbp_2.v | 2,443 | module MODULE2 (
VAR2 ,
VAR8 ,
VAR1 ,
VAR6 ,
VAR7 ,
VAR11 ,
VAR12,
VAR10,
VAR3 ,
VAR4
);
output VAR2 ;
output VAR8 ;
input VAR1 ;
input VAR6 ;
input VAR7 ;
input VAR11 ;
input VAR12;
input VAR10;
input VAR3 ;
input VAR4 ;
VAR9 VAR5 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR12... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlrtp/sky130_fd_sc_lp__srdlrtp.behavioral.pp.v | 2,404 | module MODULE1 (
VAR14 ,
VAR11,
VAR6 ,
VAR8 ,
VAR10,
VAR15 ,
VAR12 ,
VAR1 ,
VAR7 ,
VAR20
);
output VAR14 ;
input VAR11;
input VAR6 ;
input VAR8 ;
input VAR10;
input VAR15 ;
input VAR12 ;
input VAR1 ;
input VAR7 ;
input VAR20 ;
wire VAR17 ;
wire VAR21 ;
reg VAR13 ;
wire VAR22 ;
wire VAR19 ;
wire VAR24 ;
wire VAR2;
wire ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2b/sky130_fd_sc_ls__and2b.symbol.v | 1,291 | module MODULE1 (
input VAR2,
input VAR6 ,
output VAR4
);
supply1 VAR5;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21boi/sky130_fd_sc_lp__a21boi.blackbox.v | 1,392 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR7 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR7 ;
input VAR1;
supply1 VAR6;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/16-way/ise/ipcore_dir/dram/example_design/rtl/traffic_gen/mig_7series_v1_9_read_posted_fifo.v | 7,842 | module MODULE1 #
(
parameter VAR3 = 100,
parameter VAR14 = "VAR45",
parameter VAR1 = 4,
parameter VAR23 = 4,
parameter VAR5 = 32,
parameter VAR48 = 6
)
(
input VAR16,
input VAR19,
output reg VAR28,
input VAR39,
input VAR22,
input VAR47,
input VAR44,
input [VAR5-1:0] VAR24,
input [VAR48-1:0] VAR30,
input [2:0] VAR25,
in... | mit |
alexandruioanp/Open-Logic-Analyzer | src/INSTRUCTION_DECODER.v | 2,052 | module MODULE1(input VAR13, input [7:0] VAR2, input VAR1, input VAR8, output VAR11, output reg VAR12,
output reg [9:0] VAR14, output reg [31:0] VAR10, output reg VAR6, output reg VAR7);
reg [2:0] VAR4=0;
reg [1:0] VAR9; reg [23:0] VAR3;
reg VAR5;
assign VAR11=VAR5;
always@(posedge VAR13)
case(VAR4)
0: begin
VAR5<=0;
VA... | gpl-2.0 |
lvd2/zxevo | unsupported/flasher/fpga/lpm_ram_dp0.v | 1,646 | module MODULE1 (
VAR21,
VAR27,
VAR15,
VAR23,
VAR24);
input [6:0] VAR21;
input [9:0] VAR27;
input [9:0] VAR15;
input VAR23;
output [6:0] VAR24;
wire [6:0] VAR22;
wire [6:0] VAR24 = VAR22[6:0];
VAR25 VAR17 (
.VAR23 (VAR23),
.VAR21 (VAR21),
.VAR27 (VAR27),
.VAR15 (VAR15),
.VAR24 (VAR22),
.VAR9 (1'b1),
.VAR7 (1'b1),
.VAR18... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/premuat3_4.v | 1,064 | module MODULE1(
VAR2,
VAR4,
VAR3,
VAR1,
o0,
o1,
o2,
o3
);
input signed [27:0] VAR2;
input signed [27:0] VAR4;
input signed [27:0] VAR3;
input signed [27:0] VAR1;
output signed [27:0] o0;
output signed [27:0] o1;
output signed [27:0] o2;
output signed [27:0] o3;
assign o0=VAR2;
assign o1=VAR3;
assign o2=VAR4;
assign o3=... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_led_controller_0_0/led_controller_design_led_controller_0_0_stub.v | 2,629 | module MODULE1(VAR7, VAR11, VAR13,
VAR19, VAR10, VAR14, VAR1, VAR9,
VAR12, VAR3, VAR6, VAR16, VAR15,
VAR17, VAR18, VAR2, VAR4, VAR22,
VAR8, VAR20, VAR5, VAR21)
;
output [7:0]VAR7;
input [3:0]VAR11;
input [2:0]VAR13;
input VAR19;
output VAR10;
input [31:0]VAR14;
input [3:0]VAR1;
input VAR9;
output VAR12;
output [1:0]VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrtp/sky130_fd_sc_hvl__dfrtp.pp.blackbox.v | 1,371 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR8 ,
VAR6,
VAR4 ,
VAR3 ,
VAR1 ,
VAR7
);
output VAR5 ;
input VAR2 ;
input VAR8 ;
input VAR6;
input VAR4 ;
input VAR3 ;
input VAR1 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xor2/sky130_fd_sc_hvl__xor2_1.v | 2,125 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR8 ,
VAR9,
VAR2,
VAR1 ,
VAR6
);
output VAR5 ;
input VAR3 ;
input VAR8 ;
input VAR9;
input VAR2;
input VAR1 ;
input VAR6 ;
VAR7 VAR4 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR5,
VAR3,
VAR8
);
output VAR5;
... | apache-2.0 |
Canaan-Creative/MM | verilog/superkdf9/components/twi/shift.v | 1,782 | module MODULE1(
input clk ,
input rst ,
input VAR5 ,
input [1:0] VAR3 ,
input VAR11 ,
input [7:0] din ,
output VAR1 ,
output VAR2 ,
output VAR12 ,
output VAR7 ,
output VAR8 ,
output VAR9
);
reg VAR8 ;
reg VAR9 ;
always @ ( posedge clk or posedge rst ) begin
if( rst )
VAR8 <= 1'b1 ;
end
else if( VAR5 && VAR3 == 2'b00 )
... | unlicense |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/yf32/yf32_core.v | 3,927 | module MODULE1 (VAR7, VAR14, VAR4, VAR5, VAR24, VAR1, VAR17,
VAR11, VAR3, VAR13, VAR2,VAR6,VAR18, VAR10,VAR15);
input VAR7;
input VAR14;
input [31:0] VAR5;
input VAR3;
input VAR2;
output [31:0] VAR4;
output [31:0] VAR24;
output VAR1;
output [ 3:0] VAR17;
output VAR11;
output VAR13;
output [31:0] VAR6;
output [31:0] VAR... | mit |
chadharrington/all_spark_cube | fpga/panel_driver.v | 2,545 | module MODULE1
(
input clk,
input VAR13,
input VAR11,
input VAR3,
input VAR12,
input VAR9,
input [7:0] VAR16,
input [31:0] VAR6,
input [3:0] VAR24,
input VAR18,
input [3:0] VAR26,
input [3:0] VAR23,
output [2:0] VAR5
);
wire [15:0] VAR33;
wire [383:0] VAR20;
decoder #(.VAR17(4)) VAR1
(.addr(VAR24), .VAR10(VAR33));
genv... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/wb_conmax/wb_conmax_slave_if.v | 14,963 | module MODULE1(
VAR5, VAR10, VAR1,
VAR60, VAR11, VAR112, VAR18, VAR93, VAR54,
VAR31, VAR41, VAR22, VAR114,
VAR66, VAR75, VAR115, VAR56, VAR27, VAR73,
VAR105, VAR61, VAR25, VAR3,
VAR79, VAR78, VAR15, VAR80, VAR35, VAR44,
VAR113, VAR97, VAR14, VAR86,
VAR72, VAR48, VAR84, VAR39, VAR111, VAR52,
VAR74, VAR17, VAR24, VAR59,
... | gpl-2.0 |
tommythorn/yari | shared/rtl/soclib/vga.v | 13,455 | module MODULE1( input wire VAR47, input wire rst,
output wire [7:0] VAR7,
output wire [7:0] VAR51,
output wire [7:0] VAR55,
output wire VAR15,
output wire VAR39,
output wire VAR25,
output wire VAR27,
output wire VAR48,
output reg VAR52 = 0,
output reg VAR54 = 0,
input wire [31:0] VAR12,
output reg VAR33 VAR42 = 0,
inpu... | gpl-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v | 11,747 | module MODULE1 (
output wire [14:0] VAR56, output wire [2:0] VAR38, output wire VAR50, output wire VAR48, output wire VAR47, output wire VAR37, output wire VAR33, output wire VAR3, output wire VAR23, output wire VAR53, inout wire [31:0] VAR6, inout wire [3:0] VAR44, inout wire [3:0] VAR68, output wire VAR26, output wir... | gpl-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_us_1/axi_clock_converter_v2_1/hdl/verilog/axi_clock_converter_v2_1_axic_sync_clock_converter.v | 10,397 | module MODULE1 # (
parameter VAR22 = "VAR36",
parameter integer VAR24 = 32,
parameter integer VAR50 = 1,
parameter integer VAR1 = 1 ,
parameter integer VAR38 = 0 )
(
input wire VAR31,
input wire VAR40,
input wire VAR3,
input wire VAR25,
input wire [VAR24-1:0] VAR10,
input wire VAR34,
output wire VAR17,
input wire VAR16... | mit |
freecores/raggedstone | source/pciwbsequ.v | 6,766 | module MODULE1 ( VAR4, VAR23, VAR24, VAR32, VAR8, VAR21, VAR14,
VAR27, VAR7, VAR31, VAR12, VAR9, VAR6, VAR25,
VAR11, VAR20, VAR1, VAR28, VAR29, VAR13, VAR2,
VAR22, VAR16, VAR30, VAR10, VAR19 );
input VAR4;
input VAR23;
input [3:0] VAR24;
input [3:0] VAR32;
input VAR8;
input VAR21;
output VAR14;
output VAR27;
input VAR7... | gpl-2.0 |
jamesbowman/swapforth | j1a/icestorm/j1a8k.v | 12,899 | module MODULE4(
output [1:0] VAR110,
input VAR109, VAR58, VAR51,
input [10:0] VAR133,
input VAR95, VAR122, VAR76,
input [10:0] VAR39,
input [1:0] VAR124, VAR65
);
parameter VAR63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR2 = 256'h0000000000000000000000000000000000000000000000... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_2.behavioral.v | 3,306 | module MODULE1( VAR8, VAR9, VAR4, VAR6, VAR2, VAR5 );
input VAR2, VAR5, VAR6, VAR9, VAR4;
output VAR8;
VAR7 VAR1(.VAR8(VAR8),.VAR9(VAR9),.VAR4(VAR4),.VAR6(VAR6),.VAR2(VAR2),.VAR5(VAR5));
VAR7 VAR3(.VAR8(VAR8),.VAR9(VAR9),.VAR4(VAR4),.VAR6(VAR6),.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a221oi/sky130_fd_sc_hdll__a221oi.pp.blackbox.v | 1,444 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR9 ,
VAR2 ,
VAR5 ,
VAR4 ,
VAR8,
VAR3,
VAR6 ,
VAR10
);
output VAR7 ;
input VAR1 ;
input VAR9 ;
input VAR2 ;
input VAR5 ;
input VAR4 ;
input VAR8;
input VAR3;
input VAR6 ;
input VAR10 ;
endmodule | apache-2.0 |
Kumikomi/openreroc_accelsensor | hardware/src/sensor_ctl.v | 3,403 | module MODULE1(
input [0:0] clk,
input VAR3,
input [31:0] VAR42,
input [0:0] VAR32,
input [0:0] VAR6,
output [31:0] VAR10,
output [0:0] VAR43,
output [0:0] VAR5,
input [0:0] VAR1,
output [0:0] VAR30,
output [0:0] VAR15,
output [0:0] VAR34
);
parameter VAR14 = 0,
VAR24 = 1,
VAR11 = 2,
VAR20 = 3,
VAR4 = 4,
VAR37 = 5,
VAR... | bsd-3-clause |
cynngah/virtualsynthesizer | recorder.v | 3,491 | module MODULE1(VAR21, reset, VAR4, VAR8, VAR3, VAR7);
input VAR21, reset, VAR4;
input [3:0] VAR3;
output [1:0] VAR8;
output [3:0] VAR7;
wire [1:0] VAR13;
wire [4:0] VAR17;
wire [25:0] VAR12;
wire [25:0] VAR1;
MODULE2 MODULE1(
.VAR21(VAR21),
.reset(reset),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR13),
.VAR17(VAR17),
.VAR12(VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4/sky130_fd_sc_ms__or4.behavioral.v | 1,382 | module MODULE1 (
VAR9,
VAR8,
VAR4,
VAR5,
VAR10
);
output VAR9;
input VAR8;
input VAR4;
input VAR5;
input VAR10;
supply1 VAR11;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR2 ;
wire VAR12;
or VAR7 (VAR12, VAR10, VAR5, VAR4, VAR8 );
buf VAR3 (VAR9 , VAR12 );
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/nes_top.v | 11,350 | module MODULE1 #(
parameter VAR29 = 100000000,
parameter VAR72 = 60,
parameter VAR34 = 480,
parameter VAR122 = 272,
parameter VAR138 = 112,
parameter VAR124 = 6,
parameter VAR80 = 8'h00
)(
input clk, input rst, input VAR79, input [3:0] VAR135,
output VAR53, output VAR31, output [2:0] VAR154, output [2:0] VAR139, output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3b/sky130_fd_sc_lp__nor3b.blackbox.v | 1,331 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR8 ,
VAR6
);
output VAR1 ;
input VAR7 ;
input VAR8 ;
input VAR6;
supply1 VAR2;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/pre_i/mode_write.v | 1,544 | module MODULE1(
clk ,
VAR3 ,
VAR4 ,
VAR6 ,
VAR7 ,
VAR9 ,
VAR5 ,
VAR1 ,
VAR8 ,
VAR10 ,
VAR2
);
input VAR3;
input clk;
input [5:0] VAR4;
input [6:0] VAR6;
input [5:0] VAR7;
input [5:0] VAR9;
input [5:0] VAR5;
input VAR1;
output VAR8;
output [5:0] VAR2;
output [6:0] VAR10;
reg VAR8;
reg [5:0] VAR2;
reg [6:0] VAR10;
always... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor3/sky130_fd_sc_ms__xnor3_2.v | 2,184 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR1 ,
VAR5 ,
VAR3,
VAR10,
VAR6 ,
VAR9
);
output VAR7 ;
input VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR3;
input VAR10;
input VAR6 ;
input VAR9 ;
VAR8 VAR4 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
combinatorylogic/soc | backends/small1/hw/rtl/stack.v | 2,359 | module MODULE2 (input clk,
input [31:0] VAR4,
output [31:0] VAR12,
input [31:0] VAR8,
input VAR10,
input [31:0] VAR11,
output [31:0] VAR13
);
parameter VAR15 = VAR15;
reg [31:0] VAR3 [0:VAR15-1];
assign VAR12 = VAR10?VAR8:VAR3[VAR4];
assign VAR13 = VAR3[VAR11];
always @(posedge clk)
begin
if (VAR10) begin
VAR3[VAR4] <=... | mit |
julioamerico/OpenCRC | src/SoC/component/work/crc_ahb_ip_MSS/mss_tshell.v | 11,985 | module MODULE1
(
VAR91,
VAR98,
VAR49,
VAR182,
VAR150,
VAR20,
VAR92,
VAR178,
VAR186,
VAR126,
VAR118,
VAR58,
VAR143,
VAR33,
VAR101,
VAR133,
VAR32,
VAR222,
VAR104,
VAR184,
VAR67,
VAR21,
VAR194,
VAR41,
VAR196,
VAR39,
VAR45,
VAR139,
VAR28,
VAR218,
VAR145,
VAR185,
VAR221,
VAR213,
VAR136,
VAR189,
VAR144,
VAR85,
VAR22,
VAR160,... | gpl-3.0 |
SymbiFlow/yosys | techlibs/nexus/arith_map.v | 2,766 | module MODULE1(
module 80nexusalu (VAR15, VAR20, VAR32, VAR30, VAR12, VAR8, VAR38);
parameter VAR21 = 0;
parameter VAR16 = 0;
parameter VAR1 = 1;
parameter VAR42 = 1;
parameter VAR14 = 1;
input [VAR1-1:0] VAR15;
input [VAR42-1:0] VAR20;
output [VAR14-1:0] VAR12, VAR8;
input VAR32, VAR30;
output [VAR14-1:0] VAR38;
wire ... | isc |
nikhilghanathe/HLS-for-EMTF | verilog/sp_mux_6to1_sel3_7_1.v | 1,571 | module MODULE1 #(
parameter
VAR4 = 0,
VAR1 = 1,
VAR23 = 32,
VAR14 = 32,
VAR11 = 32,
VAR20 = 32,
VAR5 = 32,
VAR21 = 32,
VAR7 = 32,
VAR9 = 32
)(
input [6 : 0] VAR2,
input [6 : 0] VAR15,
input [6 : 0] VAR19,
input [6 : 0] VAR16,
input [6 : 0] VAR8,
input [6 : 0] VAR3,
input [2 : 0] VAR6,
output [6 : 0] dout);
wire [2 : 0]... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3/sky130_fd_sc_hd__or3.behavioral.v | 1,361 | module MODULE1 (
VAR9,
VAR8,
VAR7,
VAR11
);
output VAR9;
input VAR8;
input VAR7;
input VAR11;
supply1 VAR3;
supply0 VAR1;
supply1 VAR10 ;
supply0 VAR4 ;
wire VAR6;
or VAR2 (VAR6, VAR7, VAR8, VAR11 );
buf VAR5 (VAR9 , VAR6 );
endmodule | apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/submodules/niosII_system_generic_tristate_controller_0.v | 29,685 | module MODULE1 #(
parameter VAR72 = 22,
parameter VAR61 = 8,
parameter VAR60 = 1,
parameter VAR32 = 160,
parameter VAR4 = 160,
parameter VAR5 = 40,
parameter VAR20 = 40,
parameter VAR59 = 2,
parameter VAR39 = 0,
parameter VAR27 = 2,
parameter VAR17 = 1,
parameter VAR21 = 1,
parameter VAR77 = 1,
parameter VAR46 = 1,
par... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15.pp.blackbox.v | 1,343 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR1,
VAR6,
VAR2 ,
VAR5
);
output VAR4 ;
input VAR3 ;
input VAR1;
input VAR6;
input VAR2 ;
input VAR5 ;
endmodule | apache-2.0 |
JohnOrlando/gnuradio-bitshark | gr-radar-mono/src/fpga/top/usrp_radar_mono.v | 7,667 | module MODULE1
(output VAR1,
input VAR26,
input VAR25,
input VAR41,
inout VAR144,
input VAR132,
input VAR57,
output VAR106,
output VAR44,
input wire [11:0] VAR121,
input wire [11:0] VAR2,
input wire [11:0] VAR150,
input wire [11:0] VAR149,
output wire [13:0] VAR33,
output wire [13:0] VAR96,
output wire VAR59,
output wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1.symbol.v | 1,286 | module MODULE1 (
input VAR3,
output VAR1
);
supply1 VAR2;
supply0 VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2/sky130_fd_sc_hd__mux2_8.v | 2,187 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR9 ,
VAR2 ,
VAR5,
VAR7,
VAR10 ,
VAR8
);
output VAR3 ;
input VAR6 ;
input VAR9 ;
input VAR2 ;
input VAR5;
input VAR7;
input VAR10 ;
input VAR8 ;
VAR1 VAR4 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/NormaliseAdderProcess.v | 6,155 | module MODULE1(
input [31:0] VAR6,
input [3:0] VAR13,
input VAR26,
input [31:0] VAR4,
input [27:0] VAR14,
input [7:0] VAR3,
input VAR1,
output reg VAR12,
output reg [31:0] VAR23,
output reg [27:0] VAR21,
output reg [3:0] VAR2,
output reg [31:0] VAR24,
output reg [7:0] VAR17
);
parameter VAR25 = 1'b0,
VAR10 = 1'b1;
wire... | apache-2.0 |
alexforencich/verilog-axis | rtl/axis_tap.v | 11,838 | module MODULE1 #
(
parameter VAR25 = 8,
parameter VAR41 = (VAR25>8),
parameter VAR42 = ((VAR25+7)/8),
parameter VAR48 = 0,
parameter VAR15 = 8,
parameter VAR35 = 0,
parameter VAR1 = 8,
parameter VAR19 = 1,
parameter VAR56 = 1,
parameter VAR14 = 1'b1,
parameter VAR31 = 1'b1
)
(
input wire clk,
input wire rst,
input wire... | mit |
asicguy/gplgpu | hdl/de3d/des_grad.v | 22,086 | module MODULE1
(
input VAR137,
input VAR135,
input [5:0] VAR26,
input [447:0] VAR89,
input [447:0] VAR65,
input [447:0] VAR1,
input VAR194,
input VAR73,
input VAR28,
input VAR82,
output reg [29:0] VAR64,
output [31:0] VAR182,
output reg [2:0] VAR125,
output [31:0] VAR146,
output reg VAR160,
output reg VAR120,
output VA... | gpl-3.0 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/UART/FPU_UART.v | 4,297 | module MODULE1 #(parameter VAR2 = 32, parameter VAR51 = 8, parameter VAR43 = 23, parameter VAR38=26, parameter VAR45 = 5)(/*#(parameter VAR2 = 64, parameter VAR51 = 11, parameter VAR43 = 52, parameter VAR38 = 55, parameter VAR45 = 6)
input wire clk,
input wire rst,
output wire VAR46
);
localparam VAR11 = 2; localparam ... | gpl-3.0 |
lvd2/zxevo | avrboot/trunk/fpga/main.v | 2,930 | module MODULE1(
input VAR11,
output VAR70,
input VAR59,
input VAR9,
input VAR73,
input VAR76,
input VAR28,
input VAR3,
input VAR8,
input VAR10,
input VAR34,
input VAR66,
output VAR68,
input [7:0] VAR78,
input [15:0] VAR56,
output VAR49,
output VAR12,
output VAR36,
input VAR47,
input VAR38, input VAR39,
input VAR48,
inp... | gpl-3.0 |
vvk/sysrek | or_gate/or_gate.v | 1,878 | module MODULE1
(
input [9:0] VAR2,
output VAR1
);
wire [4095:0]VAR3=4096'hf5ffe6ecf6c7fd7c7577ec5e5f46e55ef474ee66444ff77d756475fde5d76f6fd7ced54c7f67476cdf5fed477ff4644fdf4eee4e476f776665e4fefd7ee5f4f5def75ce5fe4d75ffcc7f47ffcfcffde657cd5475dfc566f66d7cdc675cd655cdf46fd476f7cdddd7fe4dd7e4f545d4c467ee457c5f654664cc6f45... | gpl-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/hostController/hctxportarbiter.v | 8,296 | module MODULE1 (VAR8, VAR14, VAR28, VAR29, VAR36, VAR16, VAR21, VAR34, clk, VAR25, VAR32, VAR39, VAR38, VAR5, rst, VAR13, VAR35, VAR6, VAR15, VAR1);
input [7:0] VAR29;
input [7:0] VAR36;
input VAR21;
input VAR34;
input clk;
input [7:0] VAR25;
input [7:0] VAR32;
input VAR38;
input VAR5;
input rst;
input [7:0] VAR13;
inp... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_4.behavioral.pp.v | 5,425 | module MODULE1( VAR3, VAR1, VAR2, VAR9, VAR4, VAR5, VAR11, VAR12, VAR7 );
input VAR4, VAR5, VAR11, VAR2, VAR3, VAR1;
inout VAR12, VAR7;
output VAR9;
VAR6 VAR8(.VAR3(VAR3),.VAR1(VAR1),.VAR2(VAR2),.VAR9(VAR9),.VAR4(VAR4),.VAR5(VAR5),.VAR11(VAR11),.VAR12(VAR12),.VAR7(VAR7));
VAR6 VAR10(.VAR3(VAR3),.VAR1(VAR1),.VAR2(VAR2),... | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/paula_floppy.v | 23,861 | module MODULE1
(
input clk, input VAR23,
input VAR17,
input reset, input VAR28, input VAR92, input enable, input [8:1] VAR113, input [15:0] VAR66, output [15:0] VAR85, output VAR57, output VAR55, input VAR2, input VAR105, input [3:0] sel, input VAR93, input VAR90, output VAR44, output VAR13, output ready, output VAR95,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr_1.v | 2,265 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR9,
VAR7 ,
VAR4 ,
VAR6 ,
VAR1
);
output VAR3 ;
input VAR5 ;
input VAR9;
input VAR7 ;
input VAR4 ;
input VAR6 ;
input VAR1 ;
VAR8 VAR2 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3,
VAR5
);
output VAR3;
inpu... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_comm_link/master_calib_skip/bsg_source_sync_channel_control_master.v | 4,914 | module MODULE1 #(parameter VAR48( VAR25 )
, parameter VAR15 = 6
, parameter VAR53 = 6
, parameter VAR2 = 5'b0
, parameter VAR55 = 5
, parameter VAR26 = 1
)
( input VAR30
, input VAR45
, input [VAR11(VAR55+1)-1:0] VAR35
, input VAR44
, input VAR16
, output VAR52
, output [VAR25+1-1:0] VAR39
, input VAR37
, output [VAR55... | bsd-3-clause |
tejchava1460/Evaluation-Project-for-ASIC-FPGA-Design-Engineer | Verilog_Noise_generator/sqrt_unit.v | 1,141 | module MODULE1(VAR1, VAR12, clk, VAR8, VAR7, VAR8, VAR7, VAR6, VAR6);
input [30:0]VAR1; input [15:0]VAR8, VAR7; input [1:0]VAR6;
input clk;
output [16:0]VAR12; reg [16:0]VAR12; output [15:0]VAR8, VAR7; reg [15:0]VAR8, VAR7; output [1:0]VAR6; reg [1:0]VAR6;
reg [5:0]VAR10;
reg [30:0]VAR2, VAR2;
reg [41:0]VAR13, VAR11, V... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/clock/amiga_clk.v | 4,687 | module MODULE1 (
input wire rst, input wire VAR6, output wire VAR10, output wire VAR4, output wire VAR14, output wire VAR11, output wire VAR3, output wire VAR9, output wire VAR8, output wire VAR1, output wire VAR5, output wire [ 10-1:0] VAR15, output wire VAR12 );
reg VAR16;
reg VAR13;
reg VAR2;
reg VAR7; | gpl-3.0 |
hydai/Verilog-Practice | DigitalDesign/Final/single_cycle/Processor.v | 5,319 | module MODULE1 (
output reg [31:0] VAR45,
output reg [31:0] VAR31,
output reg [31:0] address,
output reg VAR21,
input [31:0] VAR28,
input [31:0] VAR44,
input clk,
input VAR6
);
reg [31:0] VAR32, counter, VAR1, VAR30, VAR16;
reg [31:0] VAR15[0:31];
reg VAR11;
wire [14:0] VAR29;
wire [4:0] VAR41, VAR38, VAR39;
wire [6:0]... | mit |
ElegantLin/My-CPU | Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/LLbit_reg.v | 2,434 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR5,
input wire VAR4,
input wire VAR1,
output reg VAR6
);
always @ (posedge clk) begin
if (rst == VAR2) begin
VAR6 <= 1'b0;
end else if((VAR5 == 1'b1)) begin
VAR6 <= 1'b0;
end else if((VAR1 == VAR3)) begin
VAR6 <= VAR4;
end
end
endmodule | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/minimac/rtl/minimac_rx.v | 4,546 | module MODULE1(
input VAR28,
input VAR44,
input VAR35,
output [31:0] VAR1,
output VAR16,
output VAR45,
input VAR26,
output reg [31:0] VAR2,
input VAR25,
input [29:0] VAR27,
output VAR40,
output VAR47,
output VAR7,
output VAR8,
input VAR22,
input [3:0] VAR15,
input VAR31,
input VAR37
);
reg VAR36;
reg VAR17;
assign VAR4... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2/sky130_fd_sc_ls__and2.pp.symbol.v | 1,263 | module MODULE1 (
input VAR6 ,
input VAR5 ,
output VAR7 ,
input VAR4 ,
input VAR2,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
rporter/verilog_integration | verilog/example.v | 4,822 | module MODULE1 (
output reg VAR1 VAR6,
output VAR3 VAR6
);
import "VAR2-VAR4" context task VAR5 ();
export "VAR2-VAR4" task VAR7;
task VAR7;
VAR1
=
<=
~VAR1;
endtask : VAR7
begin
end
begin
begin
begin
begin
end
begin | mit |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/pll_reconfig/altera_pll_reconfig_core.v | 81,754 | module MODULE2
parameter VAR97 = 64,
parameter VAR257 = "VAR38 VAR150",
parameter VAR131 = 6,
parameter VAR93 = 32,
parameter VAR239 = 9,
parameter VAR15 = 32,
parameter VAR256 = 512
) (
input wire VAR216,
input wire VAR250,
output wire [VAR97-1:0] VAR161,
input wire [VAR97-1:0] VAR175,
output wire [31:0] VAR199,
outpu... | mit |
glennchid/font5-firmware | src/verilog/synthesis/uart_rx.v | 7,966 | module MODULE1 (
input reset,
input clk,
input [1:0] VAR12,
input VAR9,
output reg [7:0] VAR7,
input VAR2,
input VAR3,
output reg VAR10
);
parameter VAR14 = 0;
reg [7:0] VAR5 ;
reg [9:0] VAR11 ;
reg [3:0] VAR13 ;
reg VAR8 ;
reg VAR1;
reg VAR4 ;
reg VAR6 ;
always @ (posedge clk) begin
if (reset) begin
VAR5 <= 8'd0;
VAR7... | gpl-3.0 |
windelbouwman/ppci-mirror | tools/fatfs/picorv32.v | 93,331 | module MODULE1 #(
parameter [ 0:0] VAR51 = 1,
parameter [ 0:0] VAR12 = 1,
parameter [ 0:0] VAR18 = 1,
parameter [ 0:0] VAR66 = 1,
parameter [ 0:0] VAR65 = 0,
parameter [ 0:0] VAR58 = 1,
parameter [ 0:0] VAR7 = 0,
parameter [ 0:0] VAR110 = 0,
parameter [ 0:0] VAR73 = 0,
parameter [ 0:0] VAR99 = 1,
parameter [ 0:0] VAR80... | bsd-2-clause |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_tck.v | 8,183 | module MODULE1 (
VAR33,
VAR36,
VAR21,
VAR38,
VAR19,
VAR2,
VAR34,
VAR26,
VAR35,
VAR27,
VAR4,
VAR18,
VAR23,
VAR11,
VAR37,
VAR31,
VAR15,
VAR39,
VAR6,
VAR8,
VAR20,
VAR22,
VAR7,
VAR13,
VAR40,
VAR10,
VAR24,
VAR17,
VAR16,
VAR28,
VAR25
)
;
output [ 1: 0] VAR24;
output VAR17;
output [ 37: 0] VAR16;
output VAR28;
output VAR25;
i... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fah/sky130_fd_sc_hd__fah.pp.symbol.v | 1,291 | module MODULE1 (
input VAR2 ,
input VAR6 ,
input VAR3 ,
output VAR4,
output VAR9 ,
input VAR5 ,
input VAR8,
input VAR7,
input VAR1
);
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/16-way_2-tree/src/ip_dram/clocking/mig_7series_v2_3_tempmon.v | 15,167 | module MODULE1 #
(
parameter VAR39 = 100, parameter VAR19 = "VAR16", parameter VAR85 = 5000, parameter VAR12 = 10000000 )
(
input clk, input VAR83,
input rst, input [11:0] VAR43, output [11:0] VAR30 );
function integer VAR32 (input integer VAR37, input integer VAR9);
begin
VAR32 = (VAR37/VAR9) + (((VAR37%VAR9)>0) ? 1 :... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ghrd_a10_top.v | 11,031 | module MODULE1 (
input wire [3:0] VAR154,
output wire [3:0] VAR171,
input wire [3:0] VAR111,
output wire VAR179,
output wire VAR159,
output wire VAR53,
input wire VAR81,
inout wire [4-1:0] VAR91,
output wire [16:0] VAR82,
output wire [1:0] VAR195,
output wire VAR130,
output wire VAR45,
output wire VAR164,
output wire V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbp/sky130_fd_sc_hd__dlxbp_1.v | 2,262 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR6 ,
VAR4,
VAR8,
VAR5,
VAR7 ,
VAR3
);
output VAR9 ;
output VAR2 ;
input VAR6 ;
input VAR4;
input VAR8;
input VAR5;
input VAR7 ;
input VAR3 ;
VAR10 VAR1 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch2/FPU_Add_Subtract_Function.v | 14,715 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR21,
input wire VAR109,
input wire [VAR142-1:0] VAR18,
input wire [VAR142-1:0] VAR141,
input wire VAR137,
input wire [1:0] VAR158,
output wire VAR80,
output wire VAR131,
output wire ready,
output wire [VAR142-1:0] VAR86
);
wire VAR37,VAR40;
wire [VAR142-2:0]... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_phy_bb.v | 4,221 | module MODULE1 (
VAR26,
VAR52,
VAR14,
VAR30,
VAR18,
VAR54,
VAR11,
VAR33,
VAR1,
VAR60,
VAR31,
VAR23,
VAR44,
VAR6,
VAR20,
VAR43,
VAR4,
VAR41,
VAR50,
VAR9,
VAR42,
VAR15,
VAR39,
VAR16,
VAR51,
VAR3,
VAR36,
VAR55,
VAR61,
VAR59,
VAR45,
VAR32,
VAR10,
VAR53,
VAR19,
VAR7,
VAR5,
VAR37,
VAR13,
VAR27,
VAR2,
VAR57,
VAR28,
VAR35,
VAR... | gpl-3.0 |
chaohu/Daily-Learning | Verilog/lab5/lab5_1/lab5_1_1/lab5_1_1.srcs/sources_1/new/lab5_1_1.v | 2,041 | module MODULE1(
input VAR6,clk,reset,
output reg [3:0] VAR5,
output reg VAR3
);
reg [1:0] state,VAR4;
parameter VAR8 = 0,VAR1 = 1,VAR7 = 2,VAR2 = 3;
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
begin
end
begin
end
begin
end
begin
end | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/i2c_master_byte_ctrl.v | 12,967 | module MODULE1 (
clk, rst, VAR31, VAR3, VAR24, VAR13, VAR29, read, write, VAR27, din,
VAR25, VAR15, dout, VAR16, VAR36, VAR33, VAR11, VAR14, VAR22, VAR28, VAR1 );
input clk; input rst; input VAR31; input VAR3;
input [15:0] VAR24;
input VAR13;
input VAR29;
input read;
input write;
input VAR27;
input [7:0] din;
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill/sky130_fd_sc_ms__fill_2.v | 1,840 | module MODULE2 (
VAR6,
VAR2,
VAR4 ,
VAR1
);
input VAR6;
input VAR2;
input VAR4 ;
input VAR1 ;
VAR5 VAR3 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE2 ();
supply1 VAR6;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
VAR5 VAR3 ();
endmodule | apache-2.0 |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/03_usb/usb_gpif_ctrl.v | 12,350 | module MODULE1(
input VAR11 ,
input VAR20 ,
input VAR15 ,
input VAR32 ,
input VAR41 ,
input VAR75 ,
input [15: 0] VAR23 ,
output VAR22 ,
output [12: 0] VAR47 ,
input VAR49 ,
output [31: 0] VAR45 ,
output VAR48 ,
output VAR44 ,
output VAR46 ,
input VAR43 ,
input VAR80 ,
output VAR18 ,
output VAR9 ,
output VAR19 ,
output... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21oi/sky130_fd_sc_hd__a21oi.behavioral.v | 1,516 | module MODULE1 (
VAR6 ,
VAR4,
VAR3,
VAR8
);
output VAR6 ;
input VAR4;
input VAR3;
input VAR8;
supply1 VAR2;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR9 ;
wire VAR12 ;
wire VAR11;
and VAR10 (VAR12 , VAR4, VAR3 );
nor VAR1 (VAR11, VAR8, VAR12 );
buf VAR13 (VAR6 , VAR11 );
endmodule | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_1/hdl/verilog/feedforward_dexp_64ns_64ns_64_18_full_dsp.v | 1,661 | module MODULE1
VAR18 = 4,
VAR5 = 18,
VAR10 = 64,
VAR12 = 64,
VAR11 = 64
)(
input wire clk,
input wire reset,
input wire VAR8,
input wire [VAR10-1:0] VAR14,
input wire [VAR12-1:0] VAR4,
output wire [VAR11-1:0] dout
);
wire VAR16;
wire VAR22;
wire VAR19;
wire [63:0] VAR1;
wire VAR13;
wire [63:0] VAR2;
reg [VAR12-1:0] VAR... | gpl-3.0 |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/pll.v | 20,180 | module MODULE1 (
VAR24,
VAR90,
VAR83,
VAR50,
VAR87,
VAR111,
VAR102);
input VAR24;
output VAR90;
output VAR83;
output VAR50;
output VAR87;
output VAR111;
output VAR102;
wire [4:0] VAR58;
wire VAR41;
wire [0:0] VAR66 = 1'h0;
wire [4:4] VAR104 = VAR58[4:4];
wire [2:2] VAR3 = VAR58[2:2];
wire [0:0] VAR45 = VAR58[0:0];
wire... | gpl-3.0 |
hakehuang/pycpld | ips/ip/uart7bit/uart_rx7to7.v | 3,776 | module MODULE1(
clk,
VAR18,
VAR2,
VAR7,
VAR3,
VAR10
);
input clk;
input VAR18;
input [2:0] VAR2;
input VAR7;
output [6:0] VAR3;
output VAR10;
parameter VAR4 = 13'd2604,
VAR12 = 13'd1301,
VAR8 = 13'd650,
VAR6 = 13'd433,
VAR14 = 13'd217,
VAR1 = 13'd97;
parameter VAR16 = 2'b01,
VAR5 = 2'b10;
reg [1:0] state;
reg VAR9, VAR... | mit |
YosysHQ/yosys | techlibs/machxo2/brams_map.v | 9,158 | module MODULE2 (...);
parameter VAR87 = 0;
parameter VAR167 = "VAR38";
parameter VAR32 = 18;
parameter VAR53 = "VAR81";
input VAR136;
input VAR13;
input VAR25;
input VAR128;
input VAR162;
input [12:0] VAR9;
input [VAR32-1:0] VAR37;
output [VAR32-1:0] VAR168;
parameter VAR47 = 18;
parameter VAR66 = "VAR81";
input VAR12;... | isc |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/v6_mig37_patch20110411.v | 23,207 | module MODULE1 #
(
parameter VAR99 = 200,
parameter VAR130 = "VAR16",
parameter VAR177 = 6, parameter VAR103 = 1,
parameter VAR89 = 3,
parameter VAR75 = 2,
parameter VAR136 = 2500,
parameter VAR135 = "VAR25",
parameter VAR122 = "VAR157",
parameter VAR17 = "VAR157",
parameter VAR185 = 1,
parameter VAR97 = 3,
parameter V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn.functional.v | 2,113 | module MODULE1 (
VAR6 ,
VAR13 ,
VAR5 ,
VAR9 ,
VAR10 ,
VAR11
);
output VAR6 ;
input VAR13 ;
input VAR5 ;
input VAR9 ;
input VAR10 ;
input VAR11;
wire VAR12 ;
wire VAR3 ;
wire VAR16 ;
wire VAR8;
not VAR15 (VAR3 , VAR11 );
not VAR18 (VAR16 , VAR13 );
VAR14 VAR17 (VAR8, VAR5, VAR9, VAR10 );
VAR1 VAR2 VAR4 (VAR12 , VAR8, VA... | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/nf10_oped.v | 13,292 | module MODULE1 #
( parameter VAR8 = 32,
parameter VAR21 = 32,
parameter VAR30 = 128,
parameter VAR40 = 128,
parameter VAR53 = 0,
parameter VAR49 = 0,
parameter VAR47 = 0)
( input VAR36, input VAR44,
input VAR29,
input [7:0] VAR13,
input [7:0] VAR43,
output [7:0] VAR14,
output [7:0] VAR24,
input VAR2,
input VAR11,
outpu... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinvlp/sky130_fd_sc_hd__clkinvlp.functional.pp.v | 1,796 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR6,
VAR9,
VAR8 ,
VAR12
);
output VAR1 ;
input VAR4 ;
input VAR6;
input VAR9;
input VAR8 ;
input VAR12 ;
wire VAR11 ;
wire VAR5;
not VAR7 (VAR11 , VAR4 );
VAR10 VAR2 (VAR5, VAR11, VAR6, VAR9);
buf VAR3 (VAR1 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvn/sky130_fd_sc_hs__einvn_2.v | 2,020 | module MODULE1 (
VAR5 ,
VAR2,
VAR6 ,
VAR3,
VAR1
);
input VAR5 ;
input VAR2;
output VAR6 ;
input VAR3;
input VAR1;
VAR7 VAR4 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR5 ,
VAR2,
VAR6
);
input VAR5 ;
input VAR2;
output VAR6 ;
supply1 VAR3;
supply0 VAR1;
VAR7 VAR4 (
... | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/overflow_detector.v | 1,038 | module MODULE1(
input clk,
input VAR2,
input VAR4,
input VAR3,
output reg VAR6 = 1'b0
);
reg VAR5 = 1'b0, VAR1 = 1'b0;
always @(posedge clk) begin
VAR5 <= VAR3;
VAR1 <= VAR5;
if (~VAR6) VAR6 <= (VAR1) ? VAR4 : VAR6;
end
else VAR6 <= (VAR2) ? 1'b0 : VAR6;
end
endmodule | gpl-3.0 |
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