repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/yf32/mult.v | 11,995 | module MODULE1 (clk, reset, VAR50, VAR40, VAR27, VAR48, VAR12);
input clk;
input reset;
input [31:0] VAR50;
input [31:0] VAR40;
input [ 3:0] VAR27;
output [31:0] VAR48;
output VAR12;
wire [31:0] VAR48;
reg VAR12;
reg VAR14;
reg VAR55;
reg [ 5:0] VAR21;
reg [31:0] VAR58;
reg [63:0] VAR23;
reg [31:0] VAR51;
reg [33:0] VA... | mit |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_tag_set.v | 4,455 | module MODULE1
(
input VAR24,
input VAR6,
input VAR15,
input VAR19,
input VAR20,
input VAR9,
input VAR22,
input VAR11,
input VAR14,
input VAR13,
input [4:0] VAR18,
input [4:0] VAR16,
input [4:0] VAR25,
input [4:0] VAR27,
input [4:0] VAR12,
input [4:0] VAR10,
input [4:0] VAR4,
input [4:0] VAR7,
output VAR21,
output VAR3... | gpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_pm.v | 7,426 | module MODULE1(
clk, rst, VAR8, VAR23, VAR10, VAR24, VAR6,
VAR2, VAR27, VAR26, VAR14, VAR17,
VAR28, VAR4, VAR22, VAR21, VAR1
);
input clk; input rst; input VAR8; input VAR23; input [31:0] VAR10; input [31:0] VAR24; output [31:0] VAR6;
input VAR27; output [3:0] VAR2; output VAR26; output VAR14; output VAR17; output VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgndnovpb/sky130_fd_sc_ls__tapvgndnovpb.pp.blackbox.v | 1,227 | module MODULE1 (
VAR2,
VAR1,
VAR4 ,
VAR3
);
input VAR2;
input VAR1;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
SiLab-Bonn/monopix_daq | firmware/src/timestamp640/timestamp640_core.v | 9,177 | module MODULE1
parameter VAR94 = 16,
parameter VAR118 = 4'b0001,
parameter VAR44 = 4
)(
input wire VAR14,
input wire [VAR94-1:0] VAR76,
input wire [7:0] VAR84,
output reg [7:0] VAR13,
input wire VAR111,
input wire VAR42,
input wire VAR26,
input wire VAR37,
input wire VAR58,
input wire VAR82,
input wire VAR24,
input wir... | gpl-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v | 3,965 | module MODULE1
(
VAR32,
VAR30,
VAR1) ;
input [0:0] VAR32;
output [0:0] VAR30;
output [0:0] VAR1;
wire [0:0] VAR33;
wire [0:0] VAR4;
wire [0:0] VAR7;
wire [0:0] VAR26;
wire [0:0] VAR17;
wire [0:0] VAR25;
wire [0:0] VAR2;
wire [0:0] VAR5;
wire [0:0] VAR12;
wire [0:0] VAR10;
VAR15 VAR22
(
.VAR6(VAR25),
.VAR35(VAR33[0:0]),... | mit |
Giako68/SD_RAM_VIDEO | CLOCK.v | 2,097 | module MODULE1
( input VAR42,
output VAR10,
output VAR40,
output VAR22,
output VAR30
);
wire VAR9; wire VAR33; wire VAR6; wire VAR26; wire VAR35;
VAR27 #(.VAR17(2), .VAR37(10), .VAR14(20), .VAR43(26), .VAR32(1), .VAR39(31.25) ) VAR13(.VAR23(VAR42),
.VAR12(VAR9),
.VAR41(1'b0),
.VAR25(VAR33),
.VAR8(VAR6),
.VAR1(VAR26),
.... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_axis_xx_v1_00_a/hdl/verilog/axi_axis_xx.v | 8,517 | module MODULE1 (
VAR41,
VAR80,
VAR90,
VAR53,
VAR37,
VAR74,
VAR10,
VAR16,
VAR91,
VAR15,
VAR93,
VAR29,
VAR17,
VAR52,
VAR7,
VAR85,
VAR21,
VAR65,
VAR33,
VAR25,
VAR20,
VAR64,
VAR50,
VAR58,
VAR82,
VAR68,
VAR30,
VAR84,
VAR36,
VAR35,
VAR11,
VAR79,
VAR4,
VAR78,
VAR1,
VAR44,
VAR40,
VAR39,
VAR28);
parameter VAR19 = 0;
parameter V... | mit |
Triple-Z/COExperiment_Repo | Project_1/mips.v | 1,885 | module MODULE1 (clk, rst);
input clk;
input rst;
wire [31:0] VAR37;
wire [31:0] VAR33;
wire [31:0] VAR47;
wire [31:0] VAR9;
wire [31:0] VAR48;
wire [31:0] VAR38;
wire [31:0] VAR24;
wire [31:0] VAR12;
wire [31:0] VAR42;
wire [31:0] VAR6;
wire [4:0] VAR36;
wire [3:0] VAR13;
wire VAR39;
wire VAR34;
wire VAR15;
wire VAR50;... | mit |
Elphel/x353 | compressor/encoderDCAC353.v | 7,575 | module MODULE1(clk,
en,
VAR17, VAR40, VAR38, VAR31, VAR37, VAR27, VAR29, VAR1, VAR2, VAR39, VAR30, do,
VAR16
);
input clk;
input en;
input VAR17;
input VAR40; input [2:0] VAR38; input VAR31; input VAR37; input VAR27; input VAR29;
input [12:0] VAR1;
input VAR2; input VAR39;
output VAR30;
output [15:0] do;
output VAR16;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor3/sky130_fd_sc_ms__xor3.symbol.v | 1,309 | module MODULE1 (
input VAR4,
input VAR1,
input VAR7,
output VAR8
);
supply1 VAR6;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
igalanommatis/zdma | hw/oled/hdl/ZedboardOLED_v1_0.v | 3,054 | module MODULE1 #
(
parameter integer VAR43 = 32,
parameter integer VAR38 = 7
)
(
output wire VAR44,
output wire VAR53,
output wire VAR37,
output wire VAR10,
output wire VAR15,
output wire VAR8,
input wire VAR22,
input wire VAR18,
input wire [VAR38-1 : 0] VAR49,
input wire [2 : 0] VAR29,
input wire VAR23,
output wire VA... | gpl-3.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_txcounters.v | 8,981 | module MODULE1 (VAR35, VAR9, VAR34, VAR19, VAR39, VAR36,
VAR22, VAR11, VAR4, VAR8, VAR37, VAR20,
VAR2, VAR17, VAR24, VAR3, VAR21, VAR32, VAR23, VAR16,
VAR14, VAR6, VAR31, VAR5, VAR30, VAR15,
VAR33, VAR26, VAR27, VAR1, VAR18, VAR38
);
parameter VAR7 = 1;
input VAR3; input VAR21; input VAR35; input VAR9; input [1:0] VAR3... | gpl-2.0 |
ammelto/FPGAdventure | Adventure/StartCastle.v | 1,102 | module MODULE1(VAR1, VAR5, VAR3, VAR2, VAR4);
input VAR1;
input [9:0]VAR5;
input [8:0]VAR3;
input [7:0]VAR4;
output [7:0]VAR2;
reg [7:0]VAR6;
always @(posedge VAR1) begin
if(VAR3 < 40) begin
VAR6[7:0] <= VAR4;
end
else if(VAR5 < 40) begin
VAR6[7:0] <= VAR4;
end
else if(~(VAR5 < 600)) begin
VAR6[7:0] <= VAR4;
end
else i... | mit |
ServerTech/neptune | code/stack_core.v | 2,231 | module MODULE1(clk, rst, VAR1, VAR8, wr, VAR6, rd);
parameter VAR3 = 'd16; parameter VAR2 = 'd256; parameter VAR7 = 'd8;
input wire clk , rst ; input wire VAR1 , VAR8 ; input wire [VAR3-1:0] wr ;
output reg VAR6 ;
output reg [VAR3-1:0] rd ;
reg [VAR7-1:0] VAR5 ;
reg [VAR3-1:0] VAR4 ;
reg [VAR3-1:0] VAR9 [0:VAR2-1] ;
al... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ncio/rtl/jbi_ncio_prqq_ctl.v | 23,726 | module MODULE1 (
VAR73, VAR106, VAR74,
VAR100, VAR69, VAR17,
VAR131, VAR120, VAR136,
VAR172, VAR127, VAR125, VAR162,
VAR154, VAR116, VAR84, VAR8, VAR164,
VAR122, VAR75, VAR41, VAR63, VAR40,
VAR28, VAR90, VAR52, VAR124,
clk, VAR95, VAR169, VAR119,
VAR61, VAR151, VAR97, VAR166,
VAR18, VAR55, VAR96, VAR148,
VAR26, VAR105,... | gpl-2.0 |
Willster419/ELEC3725_vivado_projects | assignment_8_p1/cpu5.v | 21,047 | module MODULE1(VAR87,clk,VAR94,VAR62,reset,VAR35);
input clk;
input reset;
output [31:0] VAR35; wire [31:0] VAR22; wire [31:0] VAR3; wire [31:0] VAR12; reg [1:0] VAR47;
wire [1:0] VAR7;
wire [1:0] VAR16;
wire VAR66; wire [31:0] VAR37; wire [31:0] VAR61;
wire [31:0] VAR46;
wire VAR67;
reg [1:0] VAR52;
wire [1:0] VAR34;
... | gpl-3.0 |
yipenghuang0302/csee4840_14 | software/peripheral/db/ip/ik_swift/submodules/ik_swift_hps_0_hps_io.v | 10,888 | module MODULE1 (
output wire [14:0] VAR14, output wire [2:0] VAR57, output wire VAR30, output wire VAR29, output wire VAR40, output wire VAR43, output wire VAR24, output wire VAR58, output wire VAR33, output wire VAR55, inout wire [31:0] VAR45, inout wire [3:0] VAR54, inout wire [3:0] VAR28, output wire VAR62, output w... | mit |
SiLab-Bonn/basil | basil/firmware/modules/fast_spi_rx/fast_spi_rx.v | 1,575 | module MODULE1 #(
parameter VAR18 = 16'h0000,
parameter VAR23 = 16'h0000,
parameter VAR16 = 16,
parameter VAR15 = 4'b0001
) (
input wire VAR9,
input wire [VAR16-1:0] VAR27,
inout wire [7:0] VAR13,
input wire VAR7,
input wire VAR25,
input wire VAR2,
input wire VAR22,
input wire VAR12,
input wire VAR11,
input wire VAR5,
... | bsd-3-clause |
mrehkopf/sd2snes | verilog/sd2snes_sa1/ipcore_dir/sa1_mult.v | 9,820 | module MODULE1 (
clk, VAR40, VAR107, VAR63
);
input clk;
output [31 : 0] VAR40;
input [15 : 0] VAR107;
input [15 : 0] VAR63;
wire \VAR87/VAR92 ;
wire \VAR87/VAR99 ;
wire \VAR87/VAR85 ;
wire \VAR87/VAR37 ;
wire \VAR87/VAR42 ;
wire \VAR87/VAR54 ;
wire \VAR87/VAR95 ;
wire \VAR87/VAR22 ;
wire \VAR87/VAR67 ;
wire \VAR87/VAR... | gpl-2.0 |
ychaim/FPGA-Litecoin-Miner | experimental/LX150-SLOWSIXTEEN-A/pbkdfengine.v | 20,439 | module MODULE1
(VAR55, VAR76, VAR61, VAR19, VAR49, VAR103, VAR69, VAR105, VAR9, VAR29, VAR7,
VAR91, VAR96, VAR72, VAR40, VAR24, VAR73, VAR101);
input VAR55; input VAR76;
input [255:0] VAR61;
input [255:0] VAR19;
input [127:0] VAR49;
input [31:0] VAR103;
input [3:0] VAR69;
output [31:0] VAR105;
output [31:0] VAR9;
outpu... | gpl-3.0 |
ShepardSiegel/ocpi | rtl/mkTLPSM.v | 6,314 | module MODULE1(VAR2,
VAR39,
VAR21,
VAR48,
VAR60,
VAR32,
VAR9,
VAR8,
VAR57,
VAR17,
VAR14,
VAR1,
VAR54,
VAR58,
VAR28,
VAR12,
VAR20,
VAR31,
VAR34,
VAR47,
VAR63);
input [13 : 0] VAR2;
input VAR39;
input VAR21;
input [152 : 0] VAR48;
input VAR60;
output VAR32;
input VAR9;
output [152 : 0] VAR8;
output VAR57;
input VAR17;
ou... | lgpl-3.0 |
vvk/sysrek | fsm2/fsm.v | 1,341 | module MODULE1(
input clk,
input rst,
input VAR11,
input [7:0] VAR9,
output VAR8
);
localparam VAR3 = 2'b00;
localparam VAR7 = 2'b01;
localparam VAR5 = 2'b10;
localparam VAR10 = 2'b11;
reg [1:0] state = VAR3;
reg [7:0] VAR2;
reg VAR6 = 1'b0;
reg [2:0] VAR4;
reg VAR1 = 1'b0;
always @(posedge clk)
begin
if(rst)
begin
VAR... | gpl-2.0 |
mbus/mbus | m3_mbus_releases/r04p2g/source/lname_mbus_master_ctrl.tsmc180.v | 10,540 | module MODULE1 (
input VAR19,
input VAR5,
input VAR82,
input VAR119,
input VAR130,
input VAR37,
output VAR140,
output VAR93,
input VAR137,
input VAR88,
input VAR113,
input VAR112,
input VAR62,
input VAR92,
output VAR33,
output VAR59,
output VAR76,
output VAR70,
output VAR7,
output VAR138,
input VAR133,
output VAR63,
in... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21bai/sky130_fd_sc_hd__o21bai.symbol.v | 1,394 | module MODULE1 (
input VAR7 ,
input VAR4 ,
input VAR6,
output VAR2
);
supply1 VAR5;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1n/sky130_fd_sc_lp__iso1n.pp.blackbox.v | 1,297 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR7,
VAR3 ,
VAR1 ,
VAR6 ,
VAR5
);
output VAR2 ;
input VAR4 ;
input VAR7;
input VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR5 ;
endmodule | apache-2.0 |
eda-globetrotter/PicenoDecoders | final/src/datamem.v | 2,674 | module MODULE1 (VAR1,VAR2,VAR3,clk,VAR4);
output [0:127] VAR1;
input [0:127] VAR2;
input [0:31] VAR3;
input clk;
input [0:1] VAR4;
reg [0:127] VAR1;
reg [127:0] MODULE1 [255:0];
begin
begin
begin
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3b/sky130_fd_sc_hd__or3b.symbol.v | 1,301 | module MODULE1 (
input VAR4 ,
input VAR7 ,
input VAR2,
output VAR1
);
supply1 VAR6;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxtp/sky130_fd_sc_ms__sdfxtp.functional.pp.v | 1,947 | module MODULE1 (
VAR7 ,
VAR13 ,
VAR1 ,
VAR16 ,
VAR5 ,
VAR11,
VAR8,
VAR3 ,
VAR14
);
output VAR7 ;
input VAR13 ;
input VAR1 ;
input VAR16 ;
input VAR5 ;
input VAR11;
input VAR8;
input VAR3 ;
input VAR14 ;
wire VAR12 ;
wire VAR6;
VAR10 VAR17 (VAR6, VAR1, VAR16, VAR5 );
VAR4 VAR2 VAR15 (VAR12 , VAR6, VAR13, , VAR11, VAR8);... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_CKINVDC_SLVT_FF_210930.v | 11,799 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
not (VAR2, VAR1); | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2o/sky130_fd_sc_ls__a2bb2o.functional.pp.v | 2,231 | module MODULE1 (
VAR9 ,
VAR17,
VAR7,
VAR12 ,
VAR2 ,
VAR8,
VAR13,
VAR4 ,
VAR6
);
output VAR9 ;
input VAR17;
input VAR7;
input VAR12 ;
input VAR2 ;
input VAR8;
input VAR13;
input VAR4 ;
input VAR6 ;
wire VAR5 ;
wire VAR11 ;
wire VAR10 ;
wire VAR19;
and VAR1 (VAR5 , VAR12, VAR2 );
nor VAR15 (VAR11 , VAR17, VAR7 );
or VAR3... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/serialInterfaceEngine/processTxByte.v | 15,318 | module MODULE1 (VAR27, VAR38, VAR72, VAR28, VAR13, VAR63, VAR57, VAR56, VAR19, VAR1, VAR8, VAR71, clk, VAR30, VAR51, rst);
input [1:0] VAR27;
input [1:0] VAR38;
input [7:0] VAR72;
input VAR28;
input [7:0] VAR13;
input VAR19;
input VAR1;
input clk;
input VAR51;
input rst;
output VAR63;
output [1:0] VAR57;
output VAR56;
... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_tdd_cntrl.v | 15,995 | module MODULE1 (
clk,
rst,
VAR41,
VAR36,
VAR64,
VAR50,
VAR25,
VAR55,
VAR63,
VAR76,
VAR28,
VAR83,
VAR45,
VAR5,
VAR8,
VAR49,
VAR62,
VAR78,
VAR68,
VAR80,
VAR86,
VAR88,
VAR46,
VAR27,
VAR6,
VAR22,
VAR39,
VAR58,
VAR7,
VAR34,
VAR37,
VAR82,
VAR16,
VAR54,
VAR15,
VAR65,
VAR81,
VAR31,
VAR38,
VAR30,
VAR19,
VAR51,
VAR90);
localpara... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/SHDCollector.v | 1,869 | module MODULE1 #(parameter VAR12 = 128, VAR14 = 8, VAR1 = 8) (
input clk,
input rst,
output reg[VAR14 - 1:0] VAR9,
input[VAR14 * VAR1 - 1:0] VAR6,
input[VAR14 - 1:0] VAR5,
input VAR8,
output VAR4,
output[VAR1 - 1:0] VAR11
);
wire VAR3;
parameter VAR7 = VAR2(VAR14);
reg[VAR7 - 1:0] VAR17 = 0;
wire VAR10;
always@(posedge... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1n/sky130_fd_sc_lp__inputiso1n.behavioral.v | 1,455 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR2
);
output VAR8 ;
input VAR1 ;
input VAR2;
supply1 VAR9;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR7 ;
wire VAR3;
not VAR10 (VAR3 , VAR2 );
or VAR5 (VAR8 , VAR1, VAR3 );
endmodule | apache-2.0 |
rkrajnc/minimig-de1 | lib/io/generic_output.v | 1,083 | module MODULE1 #(
parameter VAR6 = 1, parameter VAR3 = 1'b0, parameter VAR2 = 0 )(
output wire [ VAR6-1:0] VAR4
);
reg [ VAR6-1:0] VAR5 = {VAR6{VAR3}};
always @ (VAR4) begin
if (VAR4 != VAR5) begin
if (VAR2)
VAR5 = VAR4;
end
end
task read;
output [ VAR6-1:0] VAR1;
begin
VAR1 = VAR5;
end
endtask
endmodule | gpl-3.0 |
dries007/Basys3 | VGA/VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v | 1,199 | module MODULE1(VAR1, VAR2, reset, VAR3)
;
input VAR1;
output VAR2;
input reset;
output VAR3;
endmodule | mit |
davidkoltak/tawas-core | ip/enet/rtl/sgmii_8b10b_decode.v | 30,297 | module MODULE1
(
input clk,
input rst,
input VAR6,
input [9:0] VAR4,
output reg [7:0] VAR8,
output reg VAR1,
output reg VAR5
);
reg [9:0] VAR10;
reg [9:0] VAR9;
reg [9:0] VAR3;
always @ (posedge clk)
begin
VAR10 <= VAR4;
VAR9 <= VAR10;
VAR3 <= VAR9;
end
reg [4:0] VAR7;
wire [3:0] VAR2;
assign VAR2 = {3'd0, VAR3[9]} + {... | mit |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/xilinx/MUX8.v | 2,875 | module MODULE1
input [VAR22:0] VAR13,
input [VAR22:0] VAR15,
input [VAR22:0] VAR16,
input [VAR22:0] VAR12,
input [VAR22:0] VAR23,
input [VAR22:0] VAR21,
input [VAR22:0] VAR26,
input [VAR22:0] VAR20,
input [2:0] VAR10,
output [VAR22:0] VAR24
);
reg [VAR22:0] VAR2, VAR25;
assign VAR24 = VAR10[2] ? VAR25 : VAR2;
always @*... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21oi/sky130_fd_sc_hvl__a21oi.pp.symbol.v | 1,356 | module MODULE1 (
input VAR4 ,
input VAR2 ,
input VAR3 ,
output VAR1 ,
input VAR7 ,
input VAR8,
input VAR5,
input VAR6
);
endmodule | apache-2.0 |
praveendath92/DDR2_Interface_Xilinx_XUPV5 | source/ddr2_infrastructure.v | 12,952 | module MODULE1 #
(
parameter VAR87 = 3000,
parameter VAR17 = "VAR131",
parameter VAR80 = "VAR38",
parameter VAR41 = 0,
parameter VAR39 = 1
)
(
input VAR130,
input VAR105,
input VAR67,
input VAR44,
input VAR18,
input VAR95,
output VAR100,
output VAR73,
output VAR30,
output VAR59,
input VAR54,
input VAR124,
output VAR116... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ai/sky130_fd_sc_ls__o21ai.symbol.v | 1,349 | module MODULE1 (
input VAR7,
input VAR6,
input VAR3,
output VAR2
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3b/sky130_fd_sc_hs__nor3b_1.v | 2,127 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR1 ,
VAR4 ,
VAR6,
VAR5
);
output VAR7 ;
input VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR6;
input VAR5;
VAR3 VAR8 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR7 ,
VAR2 ,
VAR1 ,
VAR4
);
output VAR7 ;
input VAR2 ;
input VAR... | apache-2.0 |
ptracton/pmodacl2 | soc/xilinx/MUXCY.v | 1,735 | module MODULE1 (VAR2, VAR5, VAR3, VAR6);
parameter VAR4 = "VAR7";
output VAR2;
input VAR5, VAR3, VAR6;
reg VAR1;
always @(VAR5 or VAR3 or VAR6)
if (VAR6)
VAR1 = VAR5;
else
VAR1 = VAR3;
assign VAR2 = VAR1; | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_fp_cmp.v | 25,220 | module MODULE1
(
VAR103,
VAR90,
VAR87,
VAR65,
VAR2,
VAR88,
VAR52,
VAR83,
VAR27,
VAR63,
VAR121) ;
output VAR103;
output VAR90;
output VAR87;
output VAR65;
output VAR2;
output VAR88;
input VAR52;
input VAR83;
input [31:0] VAR27;
input [31:0] VAR63;
output VAR121;
tri1 VAR52;
reg VAR41;
reg VAR67;
reg VAR85;
reg VAR116;
r... | mit |
jas0n1ee/THU-DSD | FB/kernel_clock_0.v | 22,670 | module MODULE2 (
VAR42,
VAR58,
VAR8,
VAR51
)
;
output VAR51;
input VAR42;
input VAR58;
input VAR8;
reg VAR35;
wire VAR51;
always @(posedge VAR42 or negedge VAR8)
begin
if (VAR8 == 0)
VAR35 <= 0;
end
else
VAR35 <= VAR58;
end
assign VAR51 = VAR58 ^ VAR35;
endmodule
module MODULE5 (
VAR71,
VAR48,
VAR43,
VAR4,
VAR41,
VAR40... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v | 59,367 | module MODULE1
(
VAR93,
VAR166) ;
input [6:0] VAR93;
output [127:0] VAR166;
tri0 [6:0] VAR93;
wire [5:0] VAR13;
wire VAR249;
wire VAR243;
wire [127:0] VAR254;
wire [63:0] VAR68;
wire [63:0] VAR58;
wire [3:0] VAR140;
wire [3:0] VAR247;
wire [3:0] VAR52;
wire [3:0] VAR210;
wire [3:0] VAR111;
wire [3:0] VAR15;
wire [3:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311o/sky130_fd_sc_ls__a311o_2.v | 2,437 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR3 ,
VAR5 ,
VAR10 ,
VAR2 ,
VAR11,
VAR12,
VAR8 ,
VAR9
);
output VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR10 ;
input VAR2 ;
input VAR11;
input VAR12;
input VAR8 ;
input VAR9 ;
VAR1 VAR7 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR11(... | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/up_clock_mon.v | 4,898 | module MODULE1 #(
parameter VAR15 = 32
) (
input VAR13,
input VAR8,
output reg [VAR15-1:0] VAR14,
input VAR6,
input VAR7);
reg [15:0] VAR10 = 'd1;
reg VAR12 = 'd0;
reg VAR17 = 'd0;
reg VAR5 = 'd0;
reg VAR4 = 'd0;
reg VAR9 = 'd0;
reg VAR16 = 'd0;
reg VAR2 = 'd0;
reg [VAR15:0] VAR1 = 'd0;
wire VAR3;
wire VAR11;
assign VA... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_008bits.v | 1,917 | module MODULE2 (
clk,
VAR6, VAR5, VAR8, VAR30, VAR26, VAR32, VAR17, VAR15,
sum,
);
input clk;
input [VAR1+0-1:0] VAR6, VAR5, VAR8, VAR30, VAR26, VAR32, VAR17, VAR15;
output [VAR1 :0] sum;
reg [VAR1 :0] sum;
wire [VAR1+3-1:0] VAR34;
wire [VAR1+2-1:0] VAR29, VAR31;
wire [VAR1+1-1:0] VAR14, VAR2, VAR28, VAR4;
reg [VAR1+0-... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32ai/sky130_fd_sc_lp__o32ai.pp.blackbox.v | 1,425 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR7 ,
VAR5 ,
VAR3 ,
VAR8 ,
VAR2,
VAR10,
VAR6 ,
VAR4
);
output VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR3 ;
input VAR8 ;
input VAR2;
input VAR10;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
dries007/Basys3 | VGA_text/VGA_text.srcs/sources_1/ip/FiFo/FiFo_stub.v | 1,305 | module MODULE1(clk, din, VAR3, VAR2, dout, VAR4, VAR1)
;
input clk;
input [7:0]din;
input VAR3;
input VAR2;
output [7:0]dout;
output VAR4;
output VAR1;
endmodule | mit |
trivoldus28/pulsarch-verilog | verif/env/cmp/cmp_pcxandcpx.v | 4,059 | module MODULE1 (
clk, VAR24, VAR5, VAR4, VAR30, VAR22
);
input clk;
input VAR24;
input [4:0] VAR5;
input [VAR27-1:0] VAR4;
input [VAR26-1:0] VAR30;
input [31:0] VAR22;
reg [127:0] VAR12;
reg VAR31;
always @(posedge clk)begin
VAR31 <= |VAR5[4:0];
if(VAR4[VAR29] &&
(VAR19.VAR6 != VAR19.VAR3) &&
(VAR13.VAR15 == 0)) begin
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcin/sky130_fd_sc_lp__fahcin.symbol.v | 1,330 | module MODULE1 (
input VAR5 ,
input VAR9 ,
input VAR6 ,
output VAR2,
output VAR7
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
liqimai/Assignment1-Calculator | Integer-Arithmetic/IntegerDivision/IntegerDivision.v | 1,301 | module MODULE1(
input [63:0] VAR3,
input [31:0] VAR8,
output[63:0] VAR6,
output[31:0] VAR9,
input VAR2,
input clk
);
reg [8:0] VAR10;
reg [96:0] VAR5;
reg VAR11;
wire [33:0] VAR4;
wire [33:0] VAR1;
wire [63:0] VAR7;
wire [33:0] VAR12; | gpl-2.0 |
n8thenetninja/Cloud-Car | VeriLog/QuartusProjects/ServoController/i2cslave/trunk/rtl/registerInterface.v | 3,842 | module MODULE1 (
clk,
addr,
VAR5,
VAR10,
VAR7,
VAR11,
VAR3,
VAR6,
VAR9,
VAR8,
VAR4,
VAR2,
VAR1
);
input clk;
input [7:0] addr;
input [7:0] VAR5;
input VAR10;
output [7:0] VAR7;
output [7:0] VAR11;
output [7:0] VAR3;
output [7:0] VAR6;
output [7:0] VAR9;
input [7:0] VAR8;
input [7:0] VAR4;
input [7:0] VAR2;
input [7:0] ... | gpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/syncflop.v | 4,930 | module MODULE1(
VAR3,
VAR1,
VAR4,
VAR6,
VAR10,
VAR7
);
input VAR3;
input VAR1;
input VAR4;
input VAR6;
input VAR10;
output VAR7;
reg VAR2;
reg VAR8;
reg VAR12;
reg VAR9;
wire VAR11;
wire VAR5;
wire VAR7;
assign VAR11 = VAR8 ^ VAR12;
assign VAR5 = VAR11 | VAR1;
assign VAR7 = VAR9 | VAR11;
always @ (posedge VAR3 or posed... | mit |
slongfield/StereoCensus | verilog/stereo/census_basic.v | 3,120 | module MODULE1 (
input wire clk,
input wire rst,
input wire [7:0] VAR29,
input wire [7:0] VAR34,
output wire [5:0] VAR6
);
wire [(8*20*20-1):0] VAR23;
wire [(8*20*20-1):0] VAR33;
VAR10#(.VAR14(8), .VAR15(450), .VAR5(20), .VAR28(20))
VAR9(clk, rst, VAR29, VAR23);
VAR10#(.VAR14(8), .VAR15(450), .VAR5(20), .VAR28(20))
VAR... | gpl-3.0 |
neale/CS-program | 474-VLSI/Lab_ADC/db/ADC_PLL_altpll.v | 4,531 | module MODULE1
(
VAR4,
clk,
VAR3,
VAR7) ;
input VAR4;
output [4:0] clk;
input [1:0] VAR3;
output VAR7;
tri0 VAR4;
tri0 [1:0] VAR3;
reg VAR6;
wire [4:0] VAR1;
wire VAR2;
wire VAR5; | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22a/sky130_fd_sc_lp__o22a_1.v | 2,339 | module MODULE1 (
VAR3 ,
VAR9 ,
VAR4 ,
VAR11 ,
VAR6 ,
VAR10,
VAR8,
VAR5 ,
VAR2
);
output VAR3 ;
input VAR9 ;
input VAR4 ;
input VAR11 ;
input VAR6 ;
input VAR10;
input VAR8;
input VAR5 ;
input VAR2 ;
VAR1 VAR7 (
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR5(VAR5),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2/sky130_fd_sc_ls__nor2.behavioral.v | 1,350 | module MODULE1 (
VAR2,
VAR6,
VAR7
);
output VAR2;
input VAR6;
input VAR7;
supply1 VAR9;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR8 ;
wire VAR3;
nor VAR1 (VAR3, VAR6, VAR7 );
buf VAR10 (VAR2 , VAR3 );
endmodule | apache-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/db/ip/ik_swift/submodules/ik_swift_master_0_p2b_adapter.v | 1,332 | module MODULE1 (
input clk,
input VAR3,
output reg VAR10,
input VAR11,
input [ 7: 0] VAR4,
input VAR1,
input VAR5,
input VAR13,
output reg VAR8,
output reg [ 7: 0] VAR6,
output reg VAR2,
output reg VAR7,
output reg [ 7: 0] VAR9
);
reg VAR12 = 0;
always @* begin
VAR10 = VAR13;
VAR8 = VAR11;
VAR6 = VAR4;
VAR2 = VAR1;
VAR... | mit |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_dmmu_top.v | 10,332 | module MODULE1(
clk, rst,
VAR28, VAR30, VAR2, VAR45, VAR41, VAR6,
VAR38, VAR17,
VAR1, VAR24, VAR29, VAR48, VAR32,
VAR47, VAR5, VAR16,
VAR50, VAR40, VAR31, VAR36, VAR44
);
parameter VAR25 = VAR21;
parameter VAR46 = VAR21;
input clk;
input rst;
input VAR28;
input VAR30;
input VAR2;
input [VAR46-1:0] VAR45;
input VAR41;
i... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1p/sky130_fd_sc_hdll__inputiso1p.functional.v | 1,279 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3
);
output VAR2 ;
input VAR1 ;
input VAR3;
or VAR4 (VAR2 , VAR1, VAR3 );
endmodule | apache-2.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | escritor_lector_rtc.v | 2,934 | module MODULE1(
input clk,reset,
input [7:0]VAR1,VAR7,
input VAR30,VAR22,
output VAR29,VAR5,VAR27,VAR26,
output reg[7:0]VAR23,
output VAR2,
inout [7:0]VAR24
);
reg VAR25;
reg [7:0]VAR8,VAR13;
wire [7:0]VAR11;
reg [7:0]VAR21;
reg [7:0]VAR18, VAR32,VAR4;
reg VAR10,VAR12;
wire VAR31;
VAR16 VAR14 (
.VAR19(~VAR26),
.VAR3(~V... | mit |
8l/soc | backends/small1/hw/rtl/cpu.v | 4,809 | module MODULE1(
input clk, input rst,
input [31:0] VAR15, input VAR35, input VAR23,
output VAR40, output VAR22, output [31:0] VAR32, output [31:0] VAR18,
input irq, input [3:0] VAR6, output VAR43, output VAR27,
output [31:0] VAR46,
input [3:0] VAR8,
input VAR47,
input VAR41,
output VAR48,
input VAR9
);
wire [31:0] VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/buf/sky130_fd_sc_hdll__buf.pp.blackbox.v | 1,231 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR3,
VAR6,
VAR1 ,
VAR4
);
output VAR5 ;
input VAR2 ;
input VAR3;
input VAR6;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfstp/sky130_fd_sc_hs__sdfstp.behavioral.pp.v | 2,704 | module MODULE1 (
VAR18 ,
VAR7 ,
VAR5 ,
VAR2 ,
VAR26 ,
VAR12 ,
VAR4 ,
VAR29
);
input VAR18 ;
input VAR7 ;
output VAR5 ;
input VAR2 ;
input VAR26 ;
input VAR12 ;
input VAR4 ;
input VAR29;
wire VAR17 ;
wire VAR10 ;
wire VAR21 ;
reg VAR25 ;
wire VAR19 ;
wire VAR16 ;
wire VAR27 ;
wire VAR11;
wire VAR1 ;
wire VAR20 ;
wire VA... | apache-2.0 |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlslice_0_0/RAT_xlslice_0_0_stub.v | 1,216 | module MODULE1(VAR2, VAR1)
;
input [17:0]VAR2;
output [9:0]VAR1;
endmodule | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_pad_txrx.v | 2,052 | module MODULE1(
out,
VAR2,
VAR9, VAR8, VAR7, VAR3, VAR1, VAR6, VAR5
);
input [7:0] VAR9; input VAR5; input VAR8; input [8:1] VAR7; input [8:1] VAR3; input VAR1; input VAR6; inout VAR2;
output out;
assign VAR2 = VAR6 ? VAR1 : 1'VAR4;
assign out = VAR2;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221ai/sky130_fd_sc_lp__o221ai_2.v | 2,457 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR11 ,
VAR9 ,
VAR5 ,
VAR2 ,
VAR10,
VAR8,
VAR1 ,
VAR4
);
output VAR7 ;
input VAR6 ;
input VAR11 ;
input VAR9 ;
input VAR5 ;
input VAR2 ;
input VAR10;
input VAR8;
input VAR1 ;
input VAR4 ;
VAR3 VAR12 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(V... | apache-2.0 |
Gifts/descrypt-ztex-bruteforcer | user_cores/des/src/IP.v | 2,269 | module MODULE2(
input [63:0] VAR2,
output [63:0] VAR1
);
assign VAR1 = {VAR2[6], VAR2[14], VAR2[22], VAR2[30], VAR2[38], VAR2[46], VAR2[54], VAR2[62], VAR2[4], VAR2[12], VAR2[20], VAR2[28], VAR2[36], VAR2[44], VAR2[52], VAR2[60], VAR2[2], VAR2[10], VAR2[18], VAR2[26], VAR2[34], VAR2[42], VAR2[50], VAR2[58], VAR2[0], VA... | gpl-3.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/lsu_mon.v | 768,297 | module MODULE1 ( clk, VAR1);
input clk; input VAR1;
reg VAR2;
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
end
begin
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ai/sky130_fd_sc_hs__o21ai_1.v | 2,134 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR5 ,
VAR3 ,
VAR1,
VAR6
);
output VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR3 ;
input VAR1;
input VAR6;
VAR4 VAR7 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR2 ,
VAR8,
VAR5,
VAR3
);
output VAR2 ;
input VAR8;
input VAR5;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21a/sky130_fd_sc_hvl__o21a.blackbox.v | 1,330 | module MODULE1 (
VAR1 ,
VAR3,
VAR2,
VAR7
);
output VAR1 ;
input VAR3;
input VAR2;
input VAR7;
supply1 VAR6;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/ui/ui_top.v | 13,779 | module MODULE1 #
(
parameter VAR56 = 100,
parameter VAR67 = 256,
parameter VAR26 = 32,
parameter VAR32 = 3,
parameter VAR41 = 12,
parameter VAR47 = 5,
parameter VAR10 = "VAR14",
parameter VAR57 = "VAR14",
parameter VAR17 = "VAR49",
parameter VAR40 = 4,
parameter VAR28 = 2,
parameter VAR19 = 16,
parameter VAR22 = "VAR62... | lgpl-3.0 |
alexforencich/xfcp | lib/i2c/rtl/i2c_init.v | 17,275 | module MODULE1 (
input wire clk,
input wire rst,
output wire [6:0] VAR1,
output wire VAR15,
output wire VAR2,
output wire VAR6,
output wire VAR4,
output wire VAR11,
output wire VAR3,
input wire VAR14,
output wire [7:0] VAR8,
output wire VAR9,
input wire VAR10,
output wire VAR7,
output wire VAR13,
input wire VAR5
);
loc... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/alt_mem_ddrx_rdwr_data_tmg.v | 128,658 | module MODULE1
VAR85 = 2,
VAR70 = 8,
VAR63 = 1,
VAR167 = 1,
VAR27 = 6,
VAR103 = 1,
VAR128 = 10,
VAR92 = 0,
VAR20 = 0,
VAR31 = 2,
VAR48 = 1,
VAR157 = 1
)
(
VAR21,
VAR53,
VAR114,
VAR66,
VAR108,
VAR22,
VAR44,
VAR68, VAR148,
VAR178,
VAR96,
VAR126,
VAR83,
VAR32,
VAR156, VAR52,
VAR141,
VAR33,
VAR55,
VAR18,
VAR36,
VAR99,
VAR8... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkinv/sky130_fd_sc_ls__clkinv.behavioral.pp.v | 1,774 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR8,
VAR5,
VAR10 ,
VAR9
);
output VAR6 ;
input VAR7 ;
input VAR8;
input VAR5;
input VAR10 ;
input VAR9 ;
wire VAR3 ;
wire VAR12;
not VAR11 (VAR3 , VAR7 );
VAR4 VAR1 (VAR12, VAR3, VAR8, VAR5);
buf VAR2 (VAR6 , VAR12 );
endmodule | apache-2.0 |
DreamSourceLab/DSLogic-hdl | src/ipcore_dir/core_dcm.v | 6,555 | module MODULE1
( input VAR21,
output VAR52,
output VAR49,
output VAR57,
output VAR36,
output VAR33,
input VAR30,
output VAR47
);
VAR3 VAR20
(.VAR17 (VAR8),
.VAR1 (VAR21));
wire [15:0] VAR23;
wire VAR50;
wire VAR10;
wire VAR9;
wire VAR18;
VAR56
.VAR44 ("VAR54"),
.VAR35 ("VAR48"),
.VAR4 (1),
.VAR13 (20),
.VAR34 (0.000),
... | gpl-2.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/amber23/a23_coprocessor.v | 8,904 | module MODULE1
(
input VAR8,
input VAR3, input [2:0] VAR20,
input [2:0] VAR6,
input [3:0] VAR14, input [3:0] VAR11,
input [3:0] VAR10,
input [1:0] VAR16,
input [31:0] VAR18,
input VAR23, input [7:0] VAR17,
input [31:0] VAR5,
output reg [31:0] VAR13,
output VAR22,
output VAR15,
output [31:0] VAR9
);
reg [2:0] VAR25 = 3'... | gpl-2.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/ip_dram/phy/mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay.v | 8,817 | module MODULE1 #
(
parameter VAR28 = 100,
parameter VAR6 = 3636,
parameter VAR13 = 3,
parameter VAR22 = 3,
parameter VAR2 = "VAR1"
)
(
input clk,
input rst,
input VAR17,
output reg [VAR22-1:0] VAR29,
output reg VAR25,
output reg VAR10,
output reg VAR18,
output reg VAR24,
output VAR14
);
localparam VAR9 = 63;
localparam... | mit |
Jafet95/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales | Control_visualizador_numerico.v | 1,248 | module MODULE1
(
input wire [3:0] VAR4,
input wire [3:0] VAR8,
input wire VAR5,
input wire reset,
input wire VAR2,
output wire [7:0] VAR3, output wire [3:0] VAR17 );
wire [3:0] VAR16;
VAR11 VAR6
(
.clk(VAR5),
.rst(reset),
.VAR12(VAR2),
.VAR15(VAR8),
.VAR14(VAR4),
.VAR9(VAR16),
.VAR18(VAR17)
);
VAR1 VAR10
(
.VAR7(VAR16)... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_8.behavioral.v | 1,116 | module MODULE1( VAR3, VAR1 );
input VAR3;
output VAR1;
VAR4 VAR5(.VAR3(VAR3),.VAR1(VAR1));
VAR4 VAR2(.VAR3(VAR3),.VAR1(VAR1)); | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkFrameGate16B.v | 56,595 | module MODULE1(VAR341,
VAR51,
VAR241,
VAR342,
VAR129,
VAR316,
VAR320,
VAR131,
VAR216,
VAR25,
VAR324,
VAR95,
VAR351,
VAR295,
VAR117,
VAR84,
VAR150,
VAR309,
VAR279,
VAR32,
VAR171,
VAR4,
VAR147,
VAR328,
VAR264,
VAR298,
VAR152,
VAR90,
VAR28,
VAR86,
VAR327,
VAR105);
parameter [31 : 0] VAR142 = 32'b0;
parameter [0 : 0] VAR16... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211ai/sky130_fd_sc_ms__o211ai.behavioral.pp.v | 2,048 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR3 ,
VAR16 ,
VAR8 ,
VAR11,
VAR9,
VAR2 ,
VAR5
);
output VAR1 ;
input VAR10 ;
input VAR3 ;
input VAR16 ;
input VAR8 ;
input VAR11;
input VAR9;
input VAR2 ;
input VAR5 ;
wire VAR6 ;
wire VAR14 ;
wire VAR17;
or VAR4 (VAR6 , VAR3, VAR10 );
nand VAR7 (VAR14 , VAR8, VAR6, VAR16 );
VAR12 VAR15... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.functional.pp.v | 1,168 | module MODULE1( VAR8, VAR4, VAR13, VAR3, VAR12 );
input VAR4, VAR8;
inout VAR3, VAR12;
output VAR13;
wire VAR9;
not VAR5( VAR9, VAR8 );
wire VAR2;
and VAR11( VAR2, VAR9, VAR4 );
wire VAR6;
not VAR14( VAR6, VAR4 );
wire VAR1;
and VAR7( VAR1, VAR6, VAR8 );
or VAR10( VAR13, VAR2, VAR1 );
endmodule | apache-2.0 |
bluecmd/mexiko | rtl/gic/gic_master.v | 8,064 | module MODULE1 #(
parameter VAR13 = 4'b1111
) (
input VAR32,
input VAR6,
input [31:0] VAR38,
input [31:0] VAR14,
input [3:0] VAR11,
input VAR33,
input [1:0] VAR41,
input [2:0] VAR40,
input VAR39,
input VAR5,
output VAR22,
output VAR19,
output VAR47,
output [31:0] VAR1,
input [3:0] VAR9,
output [3:0] VAR10,
output VAR46... | gpl-3.0 |
hakehuang/pycpld | ips/ip/uart7bit/data_deal.v | 1,629 | module MODULE1(
clk,
VAR4,
VAR9,
VAR5,
VAR7,
VAR1,
VAR3,
VAR8
);
input clk;
input VAR4;
input [6:0] VAR9;
input VAR5;
output [6:0] VAR7;
output VAR1;
input VAR3;
output VAR8;
reg [6:0] VAR6;
reg [3:0] VAR2;
reg VAR8;
reg [6:0] VAR7;
reg VAR1;
always @(posedge clk or negedge VAR4)begin
if(!VAR4)begin
VAR6 <= 7'h0;
VAR2 ... | mit |
archlabo/Frix | fpga/nexys4_ddr/rtl/clock/clk_wiz_0_clk_wiz.v | 7,502 | module MODULE1
( input VAR19,
output VAR64,
output VAR57,
output VAR12,
output VAR13
);
VAR32 VAR72
(.VAR90 (VAR83),
.VAR79 (VAR19));
wire [15:0] VAR52;
wire VAR28;
wire VAR75;
wire VAR36;
wire VAR18;
wire VAR31;
wire VAR69;
wire VAR81;
wire VAR26;
wire VAR46;
wire VAR49;
wire VAR30;
wire VAR51;
wire VAR15;
wire VAR80;... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/conb/sky130_fd_sc_hs__conb.symbol.v | 1,234 | module MODULE1 (
output VAR2,
output VAR1
);
supply1 VAR4;
supply0 VAR3;
endmodule | apache-2.0 |
gitpan/SystemC-Vregs | t/vregs_enums.v | 1,648 | module MODULE1 ();
reg [3:0] VAR3;
reg [63:0] VAR4; always @(VAR3) begin
case ({VAR3})
VAR2: VAR4 = "VAR8 ";
VAR9: VAR4 = "VAR11 ";
VAR5: VAR4 = "VAR1 ";
VAR6: VAR4 = "VAR7";
default: VAR4 = "%VAR10 ";
endcase
end | artistic-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/Allign.v | 5,730 | module MODULE1(
input [1:0] VAR9,
input [35:0] VAR11,
input [35:0] VAR24,
input [31:0] VAR18,
input [1:0] VAR12,
input VAR8,
input VAR26,
input [49:0] VAR23,
input [7:0] VAR20,
input VAR1,
output reg [1:0] VAR29,
output reg [35:0] VAR4,
output reg [35:0] VAR3,
output reg [31:0] VAR14,
output reg [1:0] VAR25,
output reg... | apache-2.0 |
walkthetalk/fsref | ip/fifo/src/fifo_fwft_adapter.v | 1,252 | module MODULE1 # (
parameter VAR10 = 0
) (
input wire clk,
input wire rst,
input wire VAR2,
input wire VAR8,
output wire VAR5,
input wire [VAR10-1:0] VAR4,
output reg [VAR10-1:0] dout,
output wire VAR1,
output wire valid
);
reg VAR9, VAR11, VAR3;
reg [VAR10-1:0] VAR7;
assign VAR5 = (!VAR8) && !(VAR11 && VAR3 && VAR9);
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor2/sky130_fd_sc_ms__xor2.symbol.v | 1,291 | module MODULE1 (
input VAR1,
input VAR3,
output VAR4
);
supply1 VAR6;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
ehliar/schematic_gui | mux6.v | 1,387 | module MODULE1 #(parameter VAR7 = 1) (input wire [2:0] VAR2,
input wire [VAR7:0] VAR8, VAR4, VAR5,VAR1, VAR9,VAR6,
output reg [VAR7:0] VAR3); | gpl-3.0 |
zhelnio/ahb_lite_eic | src/mfp_eic_handler.v | 2,409 | module MODULE1
(
input [ 7 : 0 ] VAR9,
input VAR2,
output [ 17 : 1 ] VAR4,
output [ 3 : 0 ] VAR7,
output [ 7 : 0 ] VAR8,
output [ 5 : 0 ] VAR1
);
assign VAR7 = 4'b0;
assign VAR8 = VAR2 ? VAR9 + 1 : 8'b0;
parameter VAR6 = 17'h100;
parameter VAR10 = 4;
assign VAR4 = VAR6 + (VAR9 << VAR10);
assign VAR1 = 6'b0;
assign VAR4... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/conb/sky130_fd_sc_hvl__conb.behavioral.pp.v | 1,900 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR14,
VAR6,
VAR5 ,
VAR2
);
output VAR8 ;
output VAR12 ;
input VAR14;
input VAR6;
input VAR5 ;
input VAR2 ;
wire VAR1 ;
wire VAR3;
pullup VAR10 (VAR1 );
VAR13 VAR9 (VAR8 , VAR1, VAR14 );
pulldown VAR11 (VAR3);
VAR4 VAR7 (VAR12 , VAR3, VAR6);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor3/sky130_fd_sc_ls__xor3.blackbox.v | 1,289 | module MODULE1 (
VAR2,
VAR7,
VAR6,
VAR3
);
output VAR2;
input VAR7;
input VAR6;
input VAR3;
supply1 VAR5;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2b/sky130_fd_sc_ls__nand2b.functional.pp.v | 1,936 | module MODULE1 (
VAR15 ,
VAR4 ,
VAR3 ,
VAR6,
VAR10,
VAR12 ,
VAR7
);
output VAR15 ;
input VAR4 ;
input VAR3 ;
input VAR6;
input VAR10;
input VAR12 ;
input VAR7 ;
wire VAR1 ;
wire VAR8 ;
wire VAR2;
not VAR5 (VAR1 , VAR3 );
or VAR14 (VAR8 , VAR1, VAR4 );
VAR11 VAR13 (VAR2, VAR8, VAR6, VAR10);
buf VAR9 (VAR15 , VAR2 );
end... | apache-2.0 |
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