repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
mammenx/pegasus | wxp/dgn/rtl/l2/mac/peg_l2_mac_tx_framer.v | 15,448 | module MODULE1 #(
parameter VAR62 = 8,
parameter VAR15 = 16
)
(
input clk,
input VAR60,
input VAR65,
input VAR43,
input VAR50,
input [47:0] VAR36,
input VAR19,
input [15:0] VAR20,
output [3:0] VAR56,
input VAR40,
input VAR63,
input VAR48,
input VAR39,
input [VAR62-1:0] VAR2,
output VAR32,
input VAR4,
output VAR12,
outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2i/sky130_fd_sc_ls__mux2i.functional.pp.v | 1,934 | module MODULE1 (
VAR13 ,
VAR5 ,
VAR12 ,
VAR2 ,
VAR6,
VAR11,
VAR10 ,
VAR14
);
output VAR13 ;
input VAR5 ;
input VAR12 ;
input VAR2 ;
input VAR6;
input VAR11;
input VAR10 ;
input VAR14 ;
wire VAR15;
wire VAR8;
VAR9 VAR7 (VAR15, VAR5, VAR12, VAR2 );
VAR4 VAR1 (VAR8, VAR15, VAR6, VAR11);
buf VAR3 (VAR13 , VAR8 );
endmodule | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_top.v | 26,401 | module MODULE1(
VAR345,
VAR196, VAR154, VAR327, VAR253,
VAR302, VAR303, VAR110, VAR39, VAR116, VAR203,
VAR67, VAR34, VAR201, VAR139, VAR231, VAR404,
VAR251,
VAR257, VAR235,
VAR22, VAR209, VAR254, VAR83, VAR20, VAR117,
VAR212, VAR241, VAR53, VAR244, VAR137, VAR191,
VAR183,
VAR47, VAR243,
VAR246, VAR395, VAR193, VAR400, ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o_2.v | 2,348 | module MODULE2 (
VAR11 ,
VAR2 ,
VAR5 ,
VAR9 ,
VAR7 ,
VAR8,
VAR6,
VAR10 ,
VAR3
);
output VAR11 ;
input VAR2 ;
input VAR5 ;
input VAR9 ;
input VAR7 ;
input VAR8;
input VAR6;
input VAR10 ;
input VAR3 ;
VAR1 VAR4 (
.VAR11(VAR11),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.... | apache-2.0 |
spesialstyrker/boula | gen/PCIe/example_design/PIO.v | 5,965 | module MODULE1 #(
parameter VAR30 = 64,
parameter VAR29 = VAR30 / 8 )(
input VAR6,
input VAR7,
input VAR9,
input VAR11,
output [VAR30-1:0] VAR5,
output [VAR29-1:0] VAR20,
output VAR15,
output VAR2,
output VAR4,
input [VAR30-1:0] VAR13,
input [VAR29-1:0] VAR18,
input VAR28,
input VAR17,
output VAR16,
input [21:0] VAR14,... | gpl-2.0 |
OpticalMeasurementsSystems/2DImageProcessing | src/linescanner_image_capture_unit.v | 5,858 | module MODULE1(
input wire enable,
input wire[7:0] VAR31,
output reg VAR3,
output reg VAR26,
output reg VAR7,
input wire VAR18,
input wire VAR32,
input wire VAR13,
input wire VAR16,
output wire VAR4,
input wire VAR8,
output reg VAR28,
output wire[7:0] VAR14,
output wire VAR29);
assign VAR4 = VAR16;
assign VAR29 = VAR32... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd_1.v | 1,944 | module MODULE2 (
VAR3,
VAR1,
VAR4 ,
VAR2
);
input VAR3;
input VAR1;
input VAR4 ;
input VAR2 ;
VAR6 VAR5 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
VAR6 VAR5 ();
endmodule | apache-2.0 |
PeterMagnusson/modexp | src/rtl/adder32.v | 2,188 | module MODULE1(
input [31 : 0] VAR1,
input [31 : 0] VAR2,
input VAR4,
output wire [31 : 0] sum,
output wire VAR5);
reg [32 : 0] VAR3;
assign sum = VAR3[31:0];
assign VAR5 = VAR3[32];
always @(VAR1, VAR2, VAR4)
VAR3 = {1'b0, VAR1} + {1'b0, VAR2} + {32'b0, VAR4};
endmodule | bsd-2-clause |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/eth_parser.v | 7,517 | module MODULE1
parameter VAR28 = 8,
parameter VAR18 = VAR14(VAR28)
)
( input [VAR6-1:0] VAR3,
output VAR16,
output VAR12,
output VAR2,
output VAR42,
output [VAR18-1:0] VAR26,
input VAR7,
output VAR4,
input VAR41,
input VAR22,
input VAR5,
input [47:0] VAR13, input [47:0] VAR1, input [47:0] VAR8, input [47:0] VAR15,
inpu... | apache-2.0 |
Jawanga/ece385final | finalproject/synthesis/submodules/finalproject_cpu_jtag_debug_module_sysclk.v | 7,104 | module MODULE1 (
clk,
VAR8,
VAR14,
VAR33,
VAR18,
VAR10,
VAR24,
VAR15,
VAR28,
VAR32,
VAR30,
VAR13,
VAR3,
VAR29,
VAR5,
VAR7,
VAR6,
VAR26,
VAR20
)
;
output [ 37: 0] VAR10;
output VAR24;
output VAR15;
output VAR28;
output VAR32;
output VAR30;
output VAR13;
output VAR3;
output VAR29;
output VAR5;
output VAR7;
output VAR6;
o... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/tc_top.v | 41,431 | module MODULE1 (
VAR48,
VAR41,
VAR101,
VAR269,
VAR273,
VAR69,
VAR64,
VAR279,
VAR28,
VAR152,
VAR283,
VAR29,
VAR170,
VAR182,
VAR270,
VAR97,
VAR43,
VAR282,
VAR166,
VAR77,
VAR135,
VAR38,
VAR68,
VAR115,
VAR61,
VAR57,
VAR42,
VAR183,
VAR3,
VAR219,
VAR7,
VAR180,
VAR130,
VAR175,
VAR163,
VAR227,
VAR94,
VAR235,
VAR242,
VAR291,
VA... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ncio/rtl/jbi_ncio_mrqq_buf.v | 3,063 | module MODULE1(
VAR9,
clk, VAR7, VAR1, VAR4, VAR3, VAR2, VAR21,
VAR16, VAR22
);
input clk;
input VAR7;
input VAR1;
input VAR4;
input VAR3;
input VAR2;
input [VAR20-1:0] VAR21;
input [VAR20-1:0] VAR16;
input [VAR14-1:0] VAR22;
output [VAR14-1:0] VAR9;
wire [VAR14-1:0] VAR9;
wire [160-VAR14-1:0] VAR19;
VAR12 VAR5
( .dout... | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/05MicroSD/Version_02/02 verilog/peripheral_SD.v | 1,651 | module MODULE1(clk , reset , din , VAR3 , addr , rd , wr, dout );
input clk;
input rst;
input [15:0]din;
input VAR3;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
reg [5:0] VAR2;
reg [15:0] VAR7=0;reg enable=0;
wire [15:0] VAR6; wire VAR1;
VAR4 VAR8 ( .clk(clk), .reset(reset), .VAR7(VAR7), .enable(en), .V... | gpl-3.0 |
jayrandez/Processor | object_store.v | 1,784 | module MODULE1(
input wire VAR4,
input wire VAR12,
input wire reset,
output reg[31:0] VAR3 = 0,
output reg[31:0] VAR16,
input wire[31:0] VAR14,
output reg VAR2 = 0,
output reg VAR13 = 0,
input wire [4:0] VAR15,
output wire[31:0] VAR18,
output reg VAR7 = 0
);
parameter VAR5 = 2'b00;
parameter VAR9 = 2'b01;
parameter VAR... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/vgafb/rtl/vgafb_asfifo.v | 4,304 | module MODULE1
VAR24 = 4,
VAR19 = (1 << VAR24))
(output wire [VAR7-1:0] VAR5,
output reg VAR15,
input wire VAR25,
input wire VAR26,
input wire [VAR7-1:0] VAR13,
output reg VAR27,
input wire VAR11,
input wire VAR20,
input wire VAR23);
reg [VAR7-1:0] VAR29 [VAR19-1:0];
wire [VAR24-1:0] VAR21, VAR6;
wire VAR8;
wire VAR16,... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221oi/sky130_fd_sc_hs__a221oi.pp.blackbox.v | 1,383 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR6 ,
VAR2 ,
VAR4 ,
VAR3 ,
VAR1,
VAR7
);
output VAR8 ;
input VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR4 ;
input VAR3 ;
input VAR1;
input VAR7;
endmodule | apache-2.0 |
hcabrera-/lancetfish | RTL/processing_element/des_engine/rtl/des_sbox3.v | 3,336 | module MODULE1
(
input wire [0:5] VAR1,
output reg [0:3] VAR2
);
always @(*)
case ({VAR1[0], VAR1[5]})
2'b00:
case (VAR1[1:4])
4'd0: VAR2 = 4'd10;
4'd1: VAR2 = 4'd0;
4'd2: VAR2 = 4'd9;
4'd3: VAR2 = 4'd14;
4'd4: VAR2 = 4'd6;
4'd5: VAR2 = 4'd3;
4'd6: VAR2 = 4'd15;
4'd7: VAR2 = 4'd5;
4'd8: VAR2 = 4'd1;
4'd9: VAR2 = 4'd13;... | gpl-3.0 |
idgaf/Verilog_codes | Submit Folder/EX3/LookAheadAdder.v | 1,208 | module MODULE1(VAR7,VAR4,VAR1,VAR2,VAR11);
input wire [3:0]VAR7;
input wire [3:0]VAR4;
input wire VAR1;
output wire [3:0]VAR2;
output wire VAR11;
wire [3:0]VAR10;
wire [3:0]VAR5;
wire [3:0]VAR12;
assign VAR5[3]=VAR7[3]&&VAR4[3];
assign VAR5[2]=VAR7[2]&&VAR4[2];
assign VAR5[1]=VAR7[1]&&VAR4[1];
assign VAR5[0]=VAR7[0]&&V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor3/sky130_fd_sc_ls__xnor3.functional.v | 1,300 | module MODULE1 (
VAR1,
VAR7,
VAR5,
VAR3
);
output VAR1;
input VAR7;
input VAR5;
input VAR3;
wire VAR2;
xnor VAR4 (VAR2, VAR7, VAR5, VAR3 );
buf VAR6 (VAR1 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221oi/sky130_fd_sc_hs__a221oi.functional.v | 2,099 | module MODULE1 (
VAR16,
VAR1,
VAR18 ,
VAR17 ,
VAR15 ,
VAR4 ,
VAR7 ,
VAR5
);
input VAR16;
input VAR1;
output VAR18 ;
input VAR17 ;
input VAR15 ;
input VAR4 ;
input VAR7 ;
input VAR5 ;
wire VAR7 VAR11 ;
wire VAR7 VAR13 ;
wire VAR10 ;
wire VAR6;
and VAR3 (VAR11 , VAR4, VAR7 );
and VAR2 (VAR13 , VAR17, VAR15 );
nor VAR9 (V... | apache-2.0 |
jayant-sharma/dac | hdl/dac.v | 2,049 | module MODULE1 #(
parameter VAR7 = 8
)(
input clk,
input rst,
input VAR4,
input [VAR7-1:0] VAR6,
output reg VAR2
);
wire [VAR7+1:0] VAR1;
wire [VAR7+1:0] VAR5;
reg [VAR7+1:0] VAR3;
reg [VAR7+1:0] VAR9;
assign VAR5 = VAR4 ? ((VAR9[9] << 9) | (VAR9[VAR7+1] << 8) | VAR6) : 0; assign VAR1 = VAR3 + VAR9; | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxbp/sky130_fd_sc_hd__edfxbp.behavioral.v | 2,290 | module MODULE1 (
VAR1 ,
VAR23,
VAR20,
VAR19 ,
VAR5
);
output VAR1 ;
output VAR23;
input VAR20;
input VAR19 ;
input VAR5 ;
supply1 VAR7;
supply0 VAR12;
supply1 VAR3 ;
supply0 VAR10 ;
wire VAR14 ;
reg VAR16 ;
wire VAR13 ;
wire VAR22 ;
wire VAR11;
wire VAR17 ;
wire VAR21 ;
wire VAR8 ;
VAR9 VAR6 (VAR17, VAR14, VAR13, VAR22... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/RAMB16_S4_2_altera.v | 9,652 | module MODULE1 (
VAR58,
VAR38,
VAR19,
VAR2,
VAR11,
VAR57);
input VAR58;
input [3:0] VAR38;
input [11:0] VAR19;
input [11:0] VAR2;
input VAR11;
output [3:0] VAR57;
parameter VAR32 = "";
tri1 VAR58;
tri0 VAR11;
wire [3:0] VAR1;
wire [3:0] VAR57 = VAR1[3:0];
VAR39 VAR48 (
.VAR25 (VAR2),
.VAR53 (VAR58),
.VAR44 (VAR38),
.VA... | mit |
nsauzede/cpu86 | papilio2/ipcore_dir/clk32to40/example_design/clk32to40_exdes.v | 4,909 | module MODULE1
parameter VAR21 = 100
)
( input VAR1,
input VAR15,
output [1:1] VAR17,
output VAR9
);
localparam VAR20 = 16;
wire VAR10 = VAR15;
reg VAR13;
reg VAR24;
reg VAR3;
reg VAR18;
wire VAR8;
wire VAR14;
wire clk;
reg [VAR20-1:0] counter;
VAR25 VAR26
( .VAR1 (VAR1),
.VAR22 (VAR8));
assign VAR14 = ~clk;
VAR23 VAR6... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111ai/sky130_fd_sc_hs__o2111ai.pp.blackbox.v | 1,382 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR6 ,
VAR7 ,
VAR5 ,
VAR8 ,
VAR3,
VAR4
);
output VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR7 ;
input VAR5 ;
input VAR8 ;
input VAR3;
input VAR4;
endmodule | apache-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/wb32_bridge.v | 2,380 | module MODULE1(
VAR17,
VAR10,
VAR11,
VAR18,
VAR3,
VAR15,
VAR1,
VAR12,
VAR6,
VAR9,
VAR8,
VAR5,
VAR2,
VAR7,
VAR14,
VAR16,
VAR4
);
input VAR17, VAR10;
input [22:0] VAR11;
input [15:0] VAR18;
output [15:0] VAR3;
input VAR15, VAR1, VAR12;
output VAR6;
output [21:0] VAR9;
output [3:0] VAR4;
input [31:0] VAR5;
output [31:0] V... | gpl-2.0 |
AngelTerrones/MUSB | Boards/xilinx_diligent_s3/rtl/verilog/clk_generator/clk_generator.v | 5,836 | module MODULE1(
input VAR7, output VAR44, output VAR15 );
localparam real VAR46 = 50.0; localparam integer VAR28 = 4; localparam integer VAR3 = 2; localparam integer VAR42 = 2;
wire clk;
wire VAR50;
wire VAR52;
wire VAR22;
wire VAR6;
wire VAR19;
wire VAR11;
VAR12 VAR59(
.VAR53 ( VAR7 ),
.VAR45 ( clk )
);
VAR29 VAR56(
.... | mit |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/sha256_dsp48e1.v | 9,629 | module MODULE2 (
input clk,
input [511:0] VAR80,
input [255:0] VAR94,
output reg [255:0] VAR54,
output [31:0] VAR55
);
localparam VAR1 = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74,... | gpl-3.0 |
theapi/de1-soc | ps2/DE1_SOC/DE1_SOC.v | 1,976 | module MODULE1(
input VAR22,
input VAR18,
input VAR29,
input VAR21,
input [3:0] VAR12,
output [9:0] VAR1,
inout VAR19,
inout VAR5,
inout VAR11,
inout VAR16,
output [6:0] VAR23,
output [6:0] VAR33,
output [6:0] VAR34,
output [6:0] VAR24,
output [6:0] VAR30,
output [6:0] VAR25
);
wire VAR4;
wire [7:0] VAR13;
wire [11:0] ... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/acl_fp_fptoui.v | 4,316 | module MODULE1( VAR4, enable, VAR11, VAR5, VAR14);
input VAR4;
input enable, VAR11;
input [31:0] VAR5;
output [31:0] VAR14;
wire VAR12;
wire [7:0] VAR7;
wire [22:0] VAR3;
wire [23:0] VAR10;
assign {VAR12, VAR7, VAR3} = VAR5;
assign VAR10 = {1'b1, VAR3};
reg VAR8;
reg [31:0] VAR13;
reg [7:0] VAR1;
always @( posedge VAR4... | mit |
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/BRAM2.v | 3,783 | module MODULE1(VAR19,
VAR9,
VAR3,
VAR14,
VAR12,
VAR1,
VAR2,
VAR8,
VAR15,
VAR18,
VAR6,
VAR5
);
parameter VAR17 = 0;
parameter VAR10 = 1;
parameter VAR13 = 1;
parameter VAR22 = 1;
input VAR19;
input VAR9;
input VAR3;
input [VAR10-1:0] VAR14;
input [VAR13-1:0] VAR12;
output [VAR13-1:0] VAR1;
input VAR2;
input VAR8;
input ... | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_gsu/msu.v | 5,870 | module MODULE1(
input VAR9,
input enable,
input [13:0] VAR1,
input [7:0] VAR44,
input VAR27,
input [2:0] VAR15,
input [7:0] VAR4,
output [7:0] VAR13,
input VAR36,
input VAR43,
input VAR45,
output [7:0] VAR6,
output [7:0] VAR23,
output VAR29,
output [31:0] VAR3,
output [15:0] VAR25,
input [5:0] VAR40,
input [5:0] VAR33,... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/cabac_mvd_left_2p_18x4.v | 2,521 | module MODULE1(
clk ,
VAR18 ,
VAR15 ,
VAR1 ,
VAR16 ,
VAR11 ,
VAR9
);
input clk ; input VAR18 ; input [1:0] VAR15 ; input VAR1 ; input [1:0] VAR16 ; input [2*(VAR12+1)-1:0] VAR11 ;
output [2*(VAR12+1)-1:0] VAR9 ;
VAR13 #(.VAR17(2), .VAR19(18))
VAR20 (
.VAR5 ( clk ),
.VAR8 ( ~VAR18 ),
.VAR4 ( VAR15 ),
.VAR14 ( VAR9 ),
.V... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_dma_reader/rtl/ppfifo_data_generator.v | 1,369 | module MODULE1 (
input clk,
input rst,
input VAR6,
input [1:0] VAR2,
output reg [1:0] VAR3,
input [23:0] VAR4,
output reg VAR5,
output reg [31:0] VAR7
);
reg [23:0] VAR1;
always @ (posedge clk) begin
if (rst) begin
VAR3 <= 0;
VAR5 <= 0;
VAR7 <= 0;
VAR1 <= 0;
end
else begin
VAR5 <= 0;
if (VAR6) begin
if ((VAR2 > 0) && (... | mit |
bgamari/timetag-fpga | event_tagger.v | 1,490 | module MODULE1(
VAR5,
VAR2,
clk,
VAR7,
VAR8, VAR3,
VAR4,
ready
);
input [3:0] VAR5;
input [3:0] VAR2;
input clk;
input VAR7;
input VAR8;
input VAR3;
output ready;
output [46:0] VAR4;
reg [35:0] VAR9 = 36'b0;
reg [3:0] VAR6 = 3'b0;
reg ready = 0;
reg [46:0] VAR4 = 47'b0;
always @(posedge clk)
begin
if (VAR2 != VAR6) beg... | gpl-3.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/IFID_Stage.v | 3,436 | module MODULE1(
input VAR6,
input reset,
input VAR4,
input VAR8,
input VAR9,
input [31:0] VAR18,
input [31:0] VAR12,
input [31:0] VAR3,
input VAR7,
input [31:0] VAR15,
input [31:0] VAR1,
input [31:0] VAR11,
input VAR14,
input VAR17,
output reg [31:0] VAR2,
output reg [31:0] VAR16,
output reg [31:0] VAR10,
output reg VA... | lgpl-3.0 |
olajep/oh | src/adi/hdl/library/common/ad_dds_sine.v | 6,805 | module MODULE1 #(
parameter VAR3 = 16) (
input clk,
input [15:0] VAR16,
output [15:0] VAR9,
input [(VAR3-1):0] VAR4,
output [(VAR3-1):0] VAR12);
reg [33:0] VAR38 = 'd0;
reg [33:0] VAR15 = 'd0;
reg [15:0] VAR47 = 'd0;
reg [(VAR3-1):0] VAR48 = 'd0;
reg [18:0] VAR14 = 'd0;
reg [18:0] VAR43 = 'd0;
reg [(VAR3-1):0] VAR24 = ... | mit |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/clocking/mig_7series_v1_8_infrastructure.v | 18,039 | module MODULE1 #
(
parameter VAR12 = "VAR13", parameter VAR6 = 100, parameter VAR14 = 3000, parameter VAR4 = 2, parameter VAR36 = "VAR25",
parameter VAR20 = 4, parameter VAR28 = 1, parameter VAR3 = 45.0, parameter VAR37 = 16, parameter VAR22 = 4, parameter VAR31 = 64, parameter VAR18 = 16, parameter VAR10 = 1
)
(
input... | lgpl-3.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/amber23/a23_ram_register_bank.v | 11,464 | module MODULE1 (
input VAR21,
input VAR64,
input [1:0] VAR71, input [1:0] VAR61, input [1:0] VAR22, input VAR31,
input [3:0] VAR38,
input [3:0] VAR74,
input [3:0] VAR34,
input VAR39,
input [3:0] VAR51,
input [23:0] VAR68, input [31:0] VAR50,
input [3:0] VAR37,
input VAR67,
input VAR55,
output [31:0] VAR2,
output [31:0]... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkbuf/sky130_fd_sc_ms__clkbuf.functional.v | 1,249 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
wire VAR3;
buf VAR1 (VAR3, VAR2 );
buf VAR5 (VAR4 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdlclkp/sky130_fd_sc_hs__sdlclkp.behavioral.v | 2,415 | module MODULE1 (
VAR14,
VAR11,
VAR22 ,
VAR12 ,
VAR8,
VAR20
);
output VAR14;
input VAR11;
input VAR22 ;
input VAR12 ;
input VAR8;
input VAR20;
wire VAR1 ;
wire VAR13 ;
wire VAR6 ;
wire VAR17 ;
wire VAR10 ;
wire VAR3 ;
wire VAR15;
reg VAR4 ;
wire VAR21 ;
wire VAR23 ;
wire VAR7 ;
not VAR2 (VAR13 , VAR1 );
not VAR5 (VAR6 ,... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcadc2/vc707/system_top.v | 8,584 | module MODULE1 (
VAR52,
VAR106,
VAR49,
VAR54,
VAR32,
VAR70,
VAR30,
VAR58,
VAR110,
VAR11,
VAR3,
VAR24,
VAR84,
VAR46,
VAR13,
VAR88,
VAR42,
VAR91,
VAR90,
VAR82,
VAR23,
VAR16,
VAR114,
VAR112,
VAR37,
VAR4,
VAR107,
VAR2,
VAR10,
VAR62,
VAR14,
VAR96,
VAR68,
VAR100,
VAR27,
VAR44,
VAR73,
VAR105,
VAR89,
VAR92,
VAR40,
VAR61,
VAR53... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/yf32/mem_ctrl.v | 13,750 | module MODULE1 (clk, reset, VAR13, VAR18, VAR43, VAR8,
VAR11, VAR23, VAR32, VAR17, VAR35,
VAR31, VAR1, VAR6, VAR3, VAR27,VAR40);
parameter VAR10 = 1'b0;
parameter VAR39 = 2'b00;
parameter VAR28 = 2'b01;
parameter VAR16 = 2'b10;
parameter VAR20 = 2'b11;
input clk;
input reset;
input VAR13;
input VAR18;
input [31:0] VAR4... | mit |
m-labs/milkymist | cores/rc5/rtl/rc5.v | 3,078 | module MODULE1 #(
parameter VAR18 = 4'h0,
parameter VAR15 = 100000000
) (
input VAR2,
input VAR13,
input [13:0] VAR20,
input VAR21,
input [31:0] VAR8,
output reg [31:0] VAR14,
output reg VAR10,
input VAR11
);
parameter VAR1 = VAR15/596/16;
reg [15:0] VAR17;
wire VAR6;
assign VAR6 = (VAR17 == 16'd0);
always @(posedge VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr.blackbox.v | 1,315 | module MODULE1 ();
supply1 VAR1 ;
supply1 VAR2;
supply0 VAR5 ;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ba/sky130_fd_sc_hs__o21ba.pp.blackbox.v | 1,337 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR5 ,
VAR6,
VAR1,
VAR2
);
output VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR6;
input VAR1;
input VAR2;
endmodule | apache-2.0 |
lokisz/openzcore | pippo-riscv/rtl/verilog/pippo_lsu.v | 9,233 | module MODULE1(
clk, rst,
VAR27, VAR51, VAR50, VAR40,
VAR23, VAR38,
VAR5, VAR13,
VAR26,
VAR17, VAR31,
VAR9,
VAR12,
VAR41,
VAR18, VAR2,
VAR4, VAR29, VAR44, VAR42, VAR19,
VAR28, VAR11, VAR16
);
parameter VAR35 = VAR30;
input clk;
input rst;
input [31:0] VAR51;
input [31:0] VAR50;
input [VAR35-1:0] VAR23;
input [VAR46-1:0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2b/sky130_fd_sc_lp__and2b_1.v | 2,136 | module MODULE2 (
VAR9 ,
VAR7 ,
VAR6 ,
VAR1,
VAR2,
VAR4 ,
VAR3
);
output VAR9 ;
input VAR7 ;
input VAR6 ;
input VAR1;
input VAR2;
input VAR4 ;
input VAR3 ;
VAR8 VAR5 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR9 ,
VAR7,
VAR6
);
output VAR9 ... | apache-2.0 |
skarpenko/ultiparc | rtl/src/ibus2ocp2.v | 3,029 | module MODULE1(
clk,
VAR7,
VAR17,
VAR24,
VAR11,
VAR13,
VAR20,
VAR5,
VAR19,
VAR23,
VAR21,
VAR4,
VAR6,
VAR22
);
input wire clk;
input wire VAR7;
input wire [VAR9-1:0] VAR17;
input wire VAR24;
output reg [VAR12-1:0] VAR11;
output reg VAR13;
output reg VAR20;
output reg [VAR9-1:0] VAR5;
output reg [2:0] VAR19;
output reg [... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3b/sky130_fd_sc_ls__nor3b.behavioral.pp.v | 1,995 | module MODULE1 (
VAR15 ,
VAR3 ,
VAR2 ,
VAR8 ,
VAR5,
VAR11,
VAR12 ,
VAR6
);
output VAR15 ;
input VAR3 ;
input VAR2 ;
input VAR8 ;
input VAR5;
input VAR11;
input VAR12 ;
input VAR6 ;
wire VAR4 ;
wire VAR10 ;
wire VAR14;
nor VAR9 (VAR4 , VAR3, VAR2 );
and VAR13 (VAR10 , VAR8, VAR4 );
VAR1 VAR7 (VAR14, VAR10, VAR5, VAR11);... | apache-2.0 |
ptracton/pmodacl2 | soc/uart_pb/uart.v | 3,069 | module MODULE1(
VAR25, VAR13, VAR7, VAR23,
VAR6, VAR21, VAR27,
VAR24,
clk, reset, VAR17, VAR4, VAR26, VAR5
);
input clk;
input reset;
input VAR17;
output VAR25;
output [7:0] VAR13;
input VAR4;
output VAR7;
output VAR23;
output VAR6;
input [7:0] VAR26;
input VAR5;
output VAR21;
output VAR27;
output VAR24;
wire [7:0] VAR... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_cclk_scanlasr_2x.v | 1,231 | module MODULE1 (VAR3, VAR2, VAR1, VAR5);
output VAR3;
input VAR2, VAR1, VAR5;
reg VAR4;
assign VAR3 = ~VAR4;
always @ ( VAR1 or VAR2 or VAR5 )
if (~(VAR1 & VAR5)) VAR4 <= ~VAR2 ;
endmodule | gpl-2.0 |
Fairyland0902/BlockyRoads | src/BlockyRoads/vga_sync.v | 1,537 | module MODULE1(
input wire clk, VAR4,
output reg VAR12, VAR7,
output wire VAR9,
output wire [9:0] VAR1, VAR11
);
parameter VAR6 = 800;
parameter VAR5 = 525;
parameter VAR13 = 144;
parameter VAR3 = 784;
parameter VAR8 = 35;
parameter VAR10 = 515;
reg [9:0] hc, VAR2;
assign VAR1 = hc - VAR13 - 1;
assign VAR11 = VAR2 - VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ai/sky130_fd_sc_hd__o21ai.pp.symbol.v | 1,352 | module MODULE1 (
input VAR1 ,
input VAR2 ,
input VAR6 ,
output VAR4 ,
input VAR5 ,
input VAR7,
input VAR3,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/conb/sky130_fd_sc_hs__conb.functional.v | 1,571 | module MODULE1 (
VAR8,
VAR9,
VAR3 ,
VAR1
);
input VAR8;
input VAR9;
output VAR3 ;
output VAR1 ;
wire VAR5;
pullup VAR7 (VAR5);
VAR4 VAR6 (VAR3 , VAR5, VAR8, VAR9);
pulldown VAR2 (VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdriver2/sky130_fd_sc_lp__busdriver2.behavioral.pp.v | 1,887 | module MODULE1 (
VAR12 ,
VAR2 ,
VAR5,
VAR9,
VAR11,
VAR6 ,
VAR1
);
output VAR12 ;
input VAR2 ;
input VAR5;
input VAR9;
input VAR11;
input VAR6 ;
input VAR1 ;
wire VAR10 ;
wire VAR13;
VAR8 VAR3 (VAR10 , VAR2, VAR9, VAR11 );
VAR8 VAR4 (VAR13, VAR5, VAR9, VAR11 );
bufif0 VAR7 (VAR12 , VAR10, VAR13);
endmodule | apache-2.0 |
SymbiFlow/nextpnr | ice40/benchmark/picosoc.v | 6,259 | module MODULE1 (
input clk,
input VAR13,
output VAR7,
input VAR4,
output [ 3:0] VAR11,
output [31:0] VAR74,
output [31:0] VAR16,
input [31:0] VAR72,
input VAR45,
input VAR2,
input VAR12,
output VAR25,
input VAR19,
output VAR38,
output VAR14,
output VAR63,
output VAR34,
output VAR10,
output VAR42,
output VAR49,
output V... | isc |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_adcfifo/axi_adcfifo_adc.v | 5,691 | module MODULE1 (
VAR19,
VAR3,
VAR2,
VAR22,
VAR16,
VAR4,
VAR21,
VAR9,
VAR14,
VAR24);
parameter VAR11 = 128;
parameter VAR17 = 512;
localparam VAR12 = VAR17/VAR11;
input VAR19;
input VAR3;
input VAR2;
input [VAR11-1:0] VAR22;
output VAR16;
output VAR4;
output [VAR17-1:0] VAR21;
input VAR14;
input VAR9;
input [ 3:0] VAR24... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s.behavioral.v | 1,441 | module MODULE1 (
VAR1,
VAR6
);
output VAR1;
input VAR6;
supply1 VAR9;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR4 ;
wire VAR3;
buf VAR7 (VAR3, VAR6 );
buf VAR5 (VAR1 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probec_p/sky130_fd_sc_hd__probec_p.behavioral.pp.v | 1,793 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR3,
VAR6 ,
VAR4 ,
VAR9
);
output VAR10 ;
input VAR8 ;
input VAR3;
input VAR6 ;
input VAR4 ;
input VAR9;
wire VAR5 ;
wire VAR12;
buf VAR11 (VAR5 , VAR8 );
VAR1 VAR7 (VAR12, VAR5, VAR9, VAR3);
buf VAR2 (VAR10 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxbp/sky130_fd_sc_hs__edfxbp.symbol.v | 1,412 | module MODULE1 (
input VAR2 ,
output VAR5 ,
output VAR4,
input VAR3 ,
input VAR6
);
supply1 VAR7;
supply0 VAR1;
endmodule | apache-2.0 |
VCTLabs/DE1_SOC_Linux_FB | ip/my_log_generator/log_rom.v | 6,322 | module MODULE1 (
address,
VAR46,
VAR43);
input [16:0] address;
input VAR46;
output [0:0] VAR43;
tri1 VAR46;
wire [0:0] VAR41;
wire [0:0] VAR43 = VAR41[0:0];
VAR48 VAR1 (
.VAR9 (address),
.VAR18 (VAR46),
.VAR33 (VAR41),
.VAR28 (1'b0),
.VAR10 (1'b0),
.VAR25 (1'b1),
.VAR31 (1'b0),
.VAR51 (1'b0),
.VAR52 (1'b1),
.VAR6 (1'b1... | epl-1.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3b/sky130_fd_sc_ls__and3b_1.v | 2,218 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR3 ,
VAR2 ,
VAR6,
VAR9,
VAR8 ,
VAR5
);
output VAR10 ;
input VAR7 ;
input VAR3 ;
input VAR2 ;
input VAR6;
input VAR9;
input VAR8 ;
input VAR5 ;
VAR1 VAR4 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_odt_gen.v | 15,027 | module MODULE1
VAR6 = 2,
VAR14 = 1,
VAR32 = 2, VAR31 = 2,
VAR25 = 1,
VAR13 = 4,
VAR2 = 4,
VAR27 = 3,
VAR34 = 3,
VAR42 = 4,
VAR36 = 4
)
(
VAR46,
VAR29,
VAR45,
VAR23,
VAR35,
VAR33,
VAR43,
VAR9,
VAR11,
VAR3,
VAR41,
VAR16,
VAR38,
VAR22,
VAR15
);
input VAR46;
input VAR29;
input [VAR34 -1:0] VAR45;
input [VAR2 -1:0] VAR23;
i... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxtp/sky130_fd_sc_hd__dfxtp.symbol.v | 1,314 | module MODULE1 (
input VAR7 ,
output VAR5 ,
input VAR6
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
willianzocolau/Raiden | DeBounce.v | 2,539 | module MODULE1
(
input clk, VAR2, VAR8, output reg VAR3 );
parameter VAR6 = 11 ; reg [VAR6-1 : 0] VAR10; reg [VAR6-1 : 0] VAR9;
reg VAR4, VAR1; wire VAR7; wire VAR5;
assign VAR5 = (VAR4 ^ VAR1); assign VAR7 = ~(VAR10[VAR6-1]);
always @ ( VAR5, VAR7, VAR10)
begin
case( {VAR5 , VAR7})
2'b00 :
VAR9 <= VAR10;
2'b01 :
VAR9 ... | gpl-3.0 |
ptracton/wb_soc_template | rtl/lm32_top/rtl/verilog/lm32_decoder.v | 19,768 | module MODULE1 (
VAR62,
VAR38,
VAR101,
VAR98,
VAR151,
VAR91,
VAR10,
VAR16,
VAR152,
VAR84,
VAR42,
VAR135,
VAR128,
VAR64,
VAR82,
VAR164,
VAR56,
VAR52,
VAR40,
VAR76,
VAR20,
VAR65,
VAR120,
VAR51,
VAR30,
VAR115,
VAR31,
VAR83,
VAR123,
VAR54,
VAR36,
VAR154,
VAR106,
VAR94,
VAR109,
VAR165,
VAR137,
VAR161,
VAR85,
VAR111,
VAR158,... | mit |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T28-ram/baudgen_rx.v | 1,951 | module MODULE1(input wire clk,
input wire VAR8,
output wire VAR2);
parameter VAR7 = VAR5;
localparam VAR1 = VAR3(VAR7);
localparam VAR4 = (VAR7 >> 1);
reg [VAR1-1:0] VAR6 = 0;
always @(posedge clk)
if (VAR8)
VAR6 <= (VAR6 == VAR7 - 1) ? 0 : VAR6 + 1;
else
VAR6 <= VAR7 - 1;
assign VAR2 = (VAR6 == VAR4) ? VAR8 : 0;
endmo... | gpl-2.0 |
secworks/aes | src/rtl/aes_encipher_block.v | 14,356 | module MODULE1(
input wire clk,
input wire VAR69,
input wire VAR60,
input wire VAR64,
output wire [3 : 0] VAR73,
input wire [127 : 0] VAR74,
output wire [31 : 0] VAR8,
input wire [31 : 0] VAR9,
input wire [127 : 0] VAR11,
output wire [127 : 0] VAR25,
output wire ready
);
localparam VAR59 = 1'h0;
localparam VAR32 = 1'h1... | bsd-2-clause |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/hostController/sofcontroller.v | 6,541 | module MODULE1 (VAR19, VAR20, VAR15, VAR3, VAR10, VAR9, VAR24, VAR14, VAR12, clk, rst);
input VAR15;
input VAR3;
input VAR24;
input VAR14;
input clk;
input rst;
output [7:0] VAR19;
output [7:0] VAR20;
output VAR10;
output VAR9;
output [15:0] VAR12;
reg [7:0] VAR19, VAR5;
reg [7:0] VAR20, VAR6;
wire VAR15;
wire VAR3;
re... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41oi/sky130_fd_sc_hd__a41oi.blackbox.v | 1,390 | module MODULE1 (
VAR10 ,
VAR2,
VAR4,
VAR1,
VAR5,
VAR8
);
output VAR10 ;
input VAR2;
input VAR4;
input VAR1;
input VAR5;
input VAR8;
supply1 VAR7;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
genkilife/miaow | src/verilog/rtl/decode/decode_core.v | 14,286 | module MODULE1(
VAR6,
VAR14,
VAR10,
VAR9,
VAR2,
VAR17,
VAR16,
VAR23,
VAR5,
VAR12,
VAR21,
VAR19,
VAR13
);
input [63:0] VAR6;
input VAR14;
output VAR10;
output [1:0] VAR9;
output [31:0] VAR2;
output [15:0] VAR17;
output [31:0] VAR16;
output [9:0] VAR23;
output [9:0] VAR5;
output [9:0] VAR12;
output [9:0] VAR21;
output [9... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_mesh_router.v | 4,688 | module MODULE1
import VAR67::*;
import VAR59::*;
, parameter VAR21(VAR37 )
, parameter VAR21(VAR23 )
, parameter VAR56 = 0
, parameter VAR5 = 0
, parameter VAR25 = 2
, parameter VAR72 = (2*VAR25)+1
, parameter VAR3 = 1
, parameter bit [VAR72-1:0][VAR72-1:0] VAR22 =
(VAR25 == 2) ? (VAR3 ? VAR30 : VAR42) : (
(VAR25 == 3)... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_2.behavioral.v | 2,309 | module MODULE1( VAR8, VAR7, VAR6, VAR2, VAR3 );
input VAR3, VAR2, VAR7, VAR8;
output VAR6;
VAR4 VAR1(.VAR8(VAR8),.VAR7(VAR7),.VAR6(VAR6),.VAR2(VAR2),.VAR3(VAR3));
VAR4 VAR5(.VAR8(VAR8),.VAR7(VAR7),.VAR6(VAR6),.VAR2(VAR2),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrbp/sky130_fd_sc_lp__dfrbp.pp.blackbox.v | 1,408 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR9 ,
VAR5 ,
VAR1,
VAR8 ,
VAR6 ,
VAR4 ,
VAR3
);
output VAR7 ;
output VAR2 ;
input VAR9 ;
input VAR5 ;
input VAR1;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
KestrelComputer/kestrel | cores/SIA/rtl/verilog/sia_txq.v | 1,668 | module MODULE1(
input VAR34,
input VAR36,
input [VAR38:0] VAR4,
input VAR42,
input [VAR43:0] VAR2,
input [VAR37:0] VAR10,
input [2:0] VAR14,
output VAR41,
output VAR28,
output VAR13,
output VAR15,
output VAR3
);
parameter VAR5 = 16;
parameter VAR21 = 5;
parameter VAR25 = 32;
parameter VAR40 = 4;
parameter VAR31 = VAR5;... | mpl-2.0 |
DreamSourceLab/DSLogic-hdl | src/ipcore_dir/int_skew_dcm.v | 5,719 | module MODULE1
( input VAR3,
output VAR45,
input VAR20,
output VAR39
);
assign VAR25 = VAR3;
wire VAR34;
wire VAR6;
wire [7:0] VAR32;
wire VAR31;
wire VAR5;
VAR44
.VAR7 (1),
.VAR10 (4),
.VAR2 ("VAR43"),
.VAR18 (8.333),
.VAR24 ("VAR12"),
.VAR40 ("1X"),
.VAR23 ("VAR21"),
.VAR26 (0),
.VAR29 ("VAR43"))
VAR9
(.VAR27 (VAR25)... | gpl-2.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/ethmac/eth_receivecontrol.v | 13,872 | module MODULE1 (VAR47, VAR60, VAR55, VAR34, VAR16, VAR39, VAR3,
VAR30, VAR1, VAR59, VAR29, VAR19, VAR42,
VAR13, VAR54, VAR49, VAR21,
VAR41, VAR5, VAR58, VAR9,
VAR56, VAR44, VAR7
);
parameter VAR6 = 1;
input VAR47;
input VAR60;
input VAR55;
input VAR34;
input [7:0] VAR16;
input VAR39;
input VAR3;
input VAR30;
input VAR1... | gpl-2.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_clamp.v | 1,828 | module MODULE1(
input VAR14,
input VAR19,
output VAR12,
input VAR11,
output VAR2,
input signed [11:0] VAR16,
input signed [11:0] VAR18,
input signed [17:0] VAR15,
input signed [17:0] VAR5,
input [10:0] VAR7,
input [10:0] VAR4,
input [10:0] VAR8,
input [10:0] VAR10,
output reg VAR3,
input VAR17,
output reg [10:0] VAR13,... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1.functional.v | 1,344 | module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
wire VAR2;
not VAR4 (VAR2, VAR3 );
buf VAR5 (VAR1 , VAR2 );
endmodule | apache-2.0 |
AngelTerrones/MUSB | Hardware/musb/musb_alu.v | 19,916 | module MODULE1#(
parameter VAR47 = 1, parameter VAR74 = 1, parameter VAR121 = 1 )(
input clk, input rst, input [31:0] VAR77, input [31:0] VAR33, input [4:0] VAR52, input VAR2, input VAR18, output VAR14, output reg [31:0] VAR117, output VAR119, output reg VAR113 );
reg [63:0] VAR21; reg VAR86; reg VAR118; reg [5:0] VAR1... | mit |
borti4938/sd2snes | verilog/sd2snes_gsu/main.v | 32,913 | module MODULE1(
output [22:0] VAR380,
output VAR315,
input VAR149,
output VAR373,
input VAR410,
output [21:0] VAR380,
output VAR401,
output VAR328,
output VAR65,
output VAR408,
output VAR245,
input VAR3,
input VAR48,
input [23:0] VAR198,
input VAR186,
input VAR123,
input VAR313,
inout [7:0] VAR55,
input VAR61,
input VA... | gpl-2.0 |
vr3d/miaow | src/verilog/rtl/alu/shift_in.v | 1,506 | module MODULE1 (
VAR5,
VAR10,
VAR15,
VAR8,
clk,
rst
);
parameter VAR12=1;
input [(64*VAR12)-1:0] VAR5;
input VAR10;
input VAR15;
output [(16*VAR12)-1:0] VAR8;
input clk;
input rst;
wire [(64*VAR12)-1:0] VAR6;
wire [(64*VAR12)-1:0] VAR1;
reg VAR3;
reg VAR7;
always @ (VAR15 or VAR10)
begin
casex({VAR15,VAR10})
2'b00:
beg... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcin/sky130_fd_sc_ms__fahcin.behavioral.pp.v | 2,782 | module MODULE1 (
VAR9,
VAR21 ,
VAR18 ,
VAR16 ,
VAR28 ,
VAR20,
VAR1,
VAR23 ,
VAR15
);
output VAR9;
output VAR21 ;
input VAR18 ;
input VAR16 ;
input VAR28 ;
input VAR20;
input VAR1;
input VAR23 ;
input VAR15 ;
wire VAR6 ;
wire VAR17 ;
wire VAR22 ;
wire VAR25 ;
wire VAR13 ;
wire VAR5 ;
wire VAR24 ;
wire VAR10;
not VAR8 (V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcin/sky130_fd_sc_ls__fahcin.blackbox.v | 1,332 | module MODULE1 (
VAR8,
VAR5 ,
VAR4 ,
VAR7 ,
VAR9
);
output VAR8;
output VAR5 ;
input VAR4 ;
input VAR7 ;
input VAR9 ;
supply1 VAR6;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
parallella/oh | elink/hdl/erx_fifo.v | 4,604 | module MODULE1 (
VAR2, VAR23, VAR19, VAR20, VAR26,
VAR15, VAR7, VAR38, VAR28,
VAR17, VAR30, VAR25, VAR35, VAR12, VAR6,
VAR4, VAR9, VAR5,
VAR1, VAR22, VAR33
);
parameter VAR8 = 32;
parameter VAR40 = 32;
parameter VAR27 = 104;
parameter VAR13 = 6;
parameter VAR24 = "VAR34";
input VAR17;
input VAR30;
input VAR25;
output V... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/image_to_ppfifo.v | 3,328 | module MODULE1 #(
parameter VAR6 = 10
)(
input clk,
input rst,
input VAR26,
input VAR21, input VAR12, input [2:0] VAR15, input [2:0] VAR40, input [1:0] VAR36,
output reg VAR38,
output VAR35,
input VAR31,
input VAR11,
output [31:0] VAR17,
output [23:0] VAR16
);
localparam VAR30 = 4'h0;
localparam VAR3 = 4'h1;
reg VAR2;
... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/V2NFC100DDR/src/NPhy_Toggle_Pinpad.v | 6,635 | module MODULE1
(
parameter VAR4 = 4
)
(
VAR49 ,
VAR16 ,
VAR9 ,
VAR2 ,
VAR32 ,
VAR35 ,
VAR11 ,
VAR13 ,
VAR33 ,
VAR28 ,
VAR24 ,
VAR14 ,
VAR22 ,
VAR26 ,
VAR40 ,
VAR38 ,
VAR7 ,
VAR27 ,
VAR41 ,
VAR47 ,
VAR23 ,
VAR21 ,
VAR29 ,
VAR50
);
input VAR49 ;
input VAR16 ;
output VAR9 ;
input [7:0] VAR2 ;
input [7:0] VAR32 ;
output [7... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211a/sky130_fd_sc_hs__o211a.blackbox.v | 1,324 | module MODULE1 (
VAR4 ,
VAR2,
VAR7,
VAR3,
VAR5
);
output VAR4 ;
input VAR2;
input VAR7;
input VAR3;
input VAR5;
supply1 VAR6;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvn/sky130_fd_sc_ls__einvn.behavioral.pp.v | 1,872 | module MODULE1 (
VAR11 ,
VAR13 ,
VAR5,
VAR1,
VAR12,
VAR3 ,
VAR2
);
output VAR11 ;
input VAR13 ;
input VAR5;
input VAR1;
input VAR12;
input VAR3 ;
input VAR2 ;
wire VAR7 ;
wire VAR4;
VAR10 VAR6 (VAR7 , VAR13, VAR1, VAR12 );
VAR10 VAR9 (VAR4, VAR5, VAR1, VAR12 );
notif0 VAR8 (VAR11 , VAR7, VAR4);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_vref_logic_high.v | 1,170 | module MODULE1(in,VAR1,VAR2);
input VAR2;
input [7:1] in;
output [7:0] VAR1;
assign VAR1[7:0] = {in[7:1],1'b0};
endmodule | gpl-2.0 |
marmolejo/zet | cores/serial/rtl/serial_arx.v | 3,770 | module MODULE1 (
input clk,
input VAR1,
input VAR5,
output reg [7:0] VAR7,
output reg VAR4,
output reg VAR8, output VAR11 );
reg [1:0] VAR12; always @(posedge clk) if(VAR5) VAR12 <= {VAR12[0], ~VAR1};
reg [1:0] VAR10;
reg VAR6;
always @(posedge clk)
if(VAR5) begin
if( VAR12[1] && VAR10!=2'b11) VAR10 <= VAR10 + 2'h1;
en... | gpl-3.0 |
rfotino/consolite-hardware | src/uart.v | 2,556 | module MODULE1
(
input clk,
input rst, input VAR3, output reg VAR1, output reg [VAR4-1:0] VAR2 ); | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor2/sky130_fd_sc_hd__xnor2_1.v | 2,132 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR6 ,
VAR9,
VAR8,
VAR5 ,
VAR2
);
output VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR9;
input VAR8;
input VAR5 ;
input VAR2 ;
VAR7 VAR4 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR3,
VAR1,
VAR6
);
output VAR3;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31a/sky130_fd_sc_hs__o31a.behavioral.v | 1,909 | module MODULE1 (
VAR15 ,
VAR10 ,
VAR8 ,
VAR2 ,
VAR5 ,
VAR6,
VAR1
);
output VAR15 ;
input VAR10 ;
input VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR6;
input VAR1;
wire VAR5 VAR9 ;
wire VAR12 ;
wire VAR13;
or VAR14 (VAR9 , VAR8, VAR10, VAR2 );
and VAR7 (VAR12 , VAR9, VAR5 );
VAR4 VAR3 (VAR13, VAR12, VAR6, VAR1);
buf VAR11 ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.functional.v | 1,158 | module MODULE1( VAR6, VAR2, VAR9 );
input VAR2, VAR6;
output VAR9;
wire VAR8;
and VAR10( VAR8, VAR2, VAR6 );
wire VAR3;
not VAR4( VAR3, VAR2 );
wire VAR7;
not VAR1( VAR7, VAR6 );
wire VAR11;
and VAR12( VAR11, VAR3, VAR7 );
or VAR5( VAR9, VAR8, VAR11 );
endmodule | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/tx_engine_classic.v | 36,759 | module MODULE4
parameter VAR171 = 128,
parameter VAR58 = 1,
parameter VAR152 = 1,
parameter VAR83 = 256,
parameter VAR107 = "VAR34"
)
(
input VAR73,
input VAR49,
input [VAR167-1:0] VAR135,
input VAR79,
output [VAR171-1:0] VAR87,
output VAR94,
output VAR84,
output [VAR53(VAR171/32)-1:0] VAR123,
output VAR97,
output [VAR... | bsd-3-clause |
cafe-alpha/wasca | v12/fpga_firmware/wasca/synthesis/submodules/altera_up_audio_bit_counter.v | 4,948 | module MODULE1 (
clk,
reset,
VAR1,
VAR3,
VAR5,
VAR7,
VAR2
);
parameter VAR8 = 5'h0F;
input clk;
input reset;
input VAR1;
input VAR3;
input VAR5;
input VAR7;
output reg VAR2;
wire VAR6;
reg [ 4: 0] VAR4;
always @(posedge clk)
begin
if (reset == 1'b1)
VAR4 <= 5'h00;
end
else if (VAR6 == 1'b1)
VAR4 <= VAR8;
else if ((VAR3... | gpl-2.0 |
r2apu/Labo_Digitales | L2/codigo/IMUL2.v | 1,195 | module MODULE2 (VAR15,VAR7,VAR12,VAR11, sel, out);
input wire [7:0] VAR15,VAR7,VAR12,VAR11;
input wire [1:0] sel;
output reg [7:0] out;
always @ (*)
begin
case (sel)
0: out<=VAR15;
1: out<=VAR7;
2: out<=VAR12;
3: out<=VAR11;
default: out<=0;
endcase
end
endmodule
module MODULE1 (VAR1,VAR16,VAR6);
input wire [3:0] VAR16... | gpl-3.0 |
valkwarble/finalProject | BWIMAGE/display_16hex.v | 6,819 | module MODULE1 (reset, VAR11, VAR9,
VAR15, VAR6, VAR13, VAR10,
VAR12, VAR16);
input reset, VAR11; input [63:0] VAR9;
output VAR15, VAR6, VAR16, VAR13, VAR10,
VAR12;
reg VAR16, VAR13, VAR10, VAR12;
reg [5:0] VAR2;
reg [7:0] VAR14;
wire VAR7;
wire VAR17 = (VAR2<27) ? 0 : 1;
always @(posedge VAR11)
begin
VAR2 <= reset ? 0... | gpl-2.0 |
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