repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
chcbaram/Altera_DE0_nano_Exam | prj_niosii_sdram/niosii/synthesis/submodules/niosii_nios2_gen2_0.v | 6,214 | module MODULE1 (
input wire clk, input wire VAR5, input wire VAR21, output wire [17:0] VAR27, output wire [3:0] VAR22, output wire VAR10, input wire [31:0] VAR15, input wire VAR11, output wire VAR9, output wire [31:0] VAR16, input wire VAR24, output wire VAR26, output wire [17:0] VAR23, output wire VAR17, input wire [3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric.behavioral.v | 1,418 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
supply1 VAR7;
supply1 VAR6 ;
supply0 VAR5 ;
buf VAR8 (VAR4 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3.functional.pp.v | 2,136 | module MODULE1 (
VAR1,
VAR9,
VAR10 ,
VAR7 ,
VAR4 ,
VAR6
);
input VAR1;
input VAR9;
output VAR10 ;
input VAR7 ;
input VAR4 ;
input VAR6 ;
wire VAR12, VAR11 ;
wire VAR12, VAR2 ;
wire VAR3 ;
wire VAR8 ;
wire VAR16;
or VAR17 (VAR3 , VAR4, VAR7 );
and VAR13 (VAR11 , VAR3, VAR6 );
and VAR18 (VAR2 , VAR7, VAR4 );
or VAR15 (VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0p/sky130_fd_sc_lp__inputiso0p.pp.blackbox.v | 1,368 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR6,
VAR3 ,
VAR2 ,
VAR7 ,
VAR5
);
output VAR1 ;
input VAR4 ;
input VAR6;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR5 ;
endmodule | apache-2.0 |
EmbeddedANT/ALTERA_DE0-Nano | DE0Nano_Button/DeBounce_v.v | 2,674 | module MODULE1
(
input clk, VAR5, VAR3, output reg VAR10 );
parameter VAR2 = 11 ; reg [VAR2-1 : 0] VAR6; reg [VAR2-1 : 0] VAR7;
reg VAR9, VAR4; wire VAR8; wire VAR1;
assign VAR1 = (VAR9 ^ VAR4); assign VAR8 = ~(VAR6[VAR2-1]);
always @ ( VAR1, VAR8, VAR6)
begin
case( {VAR1 , VAR8})
2'b00 :
VAR7 <= VAR6;
2'b01 :
VAR7 <= ... | gpl-3.0 |
jeffkub/n64-cart-reader | old/fpga/soc_system/soc_system/synthesis/submodules/altera_avalon_st_bytes_to_packets.v | 8,099 | module MODULE1
parameter VAR18 = 0 )
(
input clk,
input VAR17,
input VAR7,
output reg VAR14,
output reg [7: 0] VAR8,
output reg [VAR16-1: 0] VAR1,
output reg VAR5,
output reg VAR9,
output reg VAR11,
input VAR2,
input [7: 0] VAR21
);
reg VAR20, VAR6, VAR12;
wire VAR13, VAR3, VAR15, VAR19, VAR4;
wire [7:0] VAR10;
assign ... | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_led_pio.v | 2,192 | module MODULE1 (
address,
VAR9,
clk,
VAR3,
VAR8,
VAR4,
VAR2,
VAR5
)
;
output [ 9: 0] VAR2;
output [ 31: 0] VAR5;
input [ 1: 0] address;
input VAR9;
input clk;
input VAR3;
input VAR8;
input [ 31: 0] VAR4;
wire VAR7;
reg [ 9: 0] VAR1;
wire [ 9: 0] VAR2;
wire [ 9: 0] VAR6;
wire [ 31: 0] VAR5;
assign VAR7 = 1;
assign VAR6 ... | gpl-2.0 |
freecores/zet86 | rtl-model/cpu.v | 8,040 | module MODULE1 (
output [15:0] VAR25,
output [15:0] VAR56,
output [ 2:0] state,
output [ 2:0] VAR68,
output [ 5:0] VAR29,
output [15:0] VAR23,
output [15:0] VAR86,
output [15:0] VAR17,
output [15:0] VAR13,
output [15:0] VAR21,
output [15:0] VAR85,
output [15:0] VAR41,
output [15:0] VAR18,
output [15:0] VAR30,
input VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvp/sky130_fd_sc_hs__einvp.behavioral.v | 1,757 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR2 ,
VAR6,
VAR7
);
input VAR1 ;
input VAR11 ;
output VAR2 ;
input VAR6;
input VAR7;
wire VAR4 ;
wire VAR5;
VAR3 VAR10 (VAR4 , VAR1, VAR6, VAR7 );
VAR3 VAR8 (VAR5, VAR11, VAR6, VAR7 );
notif1 VAR9 (VAR2 , VAR4, VAR5);
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/txr_engine_ultrascale.v | 26,188 | module MODULE1
parameter VAR30 = 1,
parameter VAR99 = 1,
parameter VAR76 = 10,
parameter VAR81 = 256)
( input VAR153,
input VAR138, input VAR60, output VAR115,
input [VAR40-1:0] VAR20,
input VAR50,
output VAR103,
output VAR12,
output [VAR155-1:0] VAR186,
output [(VAR155/32)-1:0] VAR49,
output [VAR88-1:0] VAR101,
input ... | gpl-3.0 |
svenstaro/uni-projekt | verilog/disppll_bb.v | 10,924 | module MODULE1 (
VAR3,
VAR1,
VAR2);
input VAR3;
input VAR1;
output VAR2;
tri0 VAR3;
endmodule | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/synth/ghrd_10as066n2_pb_lwh2f.v | 4,513 | module MODULE1 #(
parameter VAR5 = 32,
parameter VAR7 = 8,
parameter VAR25 = 12,
parameter VAR26 = 1,
parameter VAR14 = 1,
parameter VAR15 = 1
) (
input wire clk, input wire VAR6, input wire [VAR5-1:0] VAR9, input wire VAR2, output wire [VAR26-1:0] VAR21, output wire [VAR5-1:0] VAR23, output wire [VAR25-1:0] VAR18, out... | mit |
jotego/jt51 | hdl/filter/jt51_fir.v | 4,410 | module MODULE1
MODULE1=7, VAR1=81, VAR42=1)
(
input clk,
input rst,
input VAR12,
input signed [VAR25-1:0] VAR9,
input signed [VAR25-1:0] VAR22,
input signed [VAR39-1:0] VAR44,
output reg [MODULE1-1:0] VAR10,
output reg signed [VAR26-1:0] VAR11,
output reg signed [VAR26-1:0] VAR18,
output reg VAR24
);
wire signed [VAR25... | gpl-3.0 |
mballance/oc_wb_ip | rtl/wb_uart/uart_regs.v | 29,876 | module MODULE1 (clk,
VAR62, VAR16, VAR42, VAR50, VAR59, VAR109,
VAR161,
VAR108, VAR81,
VAR24, VAR141, VAR17, VAR120, VAR140, VAR118, VAR89, VAR19, VAR21, VAR128, VAR47,
VAR139, VAR124, VAR154,
VAR58,
VAR92
, VAR56
);
input clk;
input VAR62;
input [VAR138-1:0] VAR16;
input [7:0] VAR42;
output [7:0] VAR50;
input VAR59;
i... | apache-2.0 |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v | 4,036 | module MODULE1
(
VAR22,
VAR13,
VAR7) ;
input [0:0] VAR22;
output [0:0] VAR13;
output [0:0] VAR7;
wire [0:0] VAR20;
wire [0:0] VAR24;
wire [0:0] VAR5;
wire [0:0] VAR6;
wire [0:0] VAR21;
wire [0:0] VAR35;
wire [0:0] VAR23;
wire [0:0] VAR15;
wire [0:0] VAR17;
wire [0:0] VAR14;
VAR30 VAR33
(
.VAR16(VAR35),
.VAR32(VAR20[0:0... | gpl-3.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/MUL_FPU_FUNCIONAL_v1/MUL_FPU_FUNCIONAL_v1.srcs/sources_1/imports/rtl/KOA_c_v3.v | 7,390 | module MODULE1
(
input wire [VAR19-1:0] VAR17,
input wire [VAR19-1:0] VAR5,
output wire [2*VAR19-1:0] VAR11
);
wire [VAR19/2+1:0] VAR20;
wire [VAR19/2+1:0] VAR28;
wire [2*(VAR19/2)-1:0] VAR7;
wire [2*(VAR19/2+1)-1:0] VAR2;
wire [2*(VAR19/2+2)-1:0] VAR10;
wire [2*(VAR19/2+2)-1:0] VAR4;
wire [2*(VAR19/2+2)-1:0] VAR25;
wi... | gpl-3.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_normalizer_block.v | 6,372 | module MODULE1
parameter VAR11 = 24,
parameter VAR5 = 14, parameter VAR3 = 16 )
(
input VAR15,
input VAR19 ,
input [VAR12:0] VAR9,
input VAR26,
input VAR30,
input signed [VAR5-1:0] VAR29,
input signed [VAR5-1:0] VAR21,
input [VAR5-2:0] VAR22,
input signed [VAR3-1:0] VAR16,
output signed [VAR5-1:0] VAR13
);
wire signed ... | mit |
scalable-networks/ext | uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v | 5,441 | module MODULE1(
din,
VAR63,
VAR94,
rst,
VAR98,
VAR1,
dout,
VAR53,
VAR11,
VAR75,
VAR7);
input [35 : 0] din;
input VAR63;
input VAR94;
input rst;
input VAR98;
input VAR1;
output [35 : 0] dout;
output VAR53;
output VAR11;
output [11 : 0] VAR75;
output [11 : 0] VAR7;
VAR74 #(
.VAR32(0),
.VAR24(0),
.VAR82(12),
.VAR25("VAR16... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tap/sky130_fd_sc_hs__tap.blackbox.v | 1,172 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
endmodule | apache-2.0 |
bigeagle/riffa | fpga/xilinx/vc707/VC707_Gen1x8If64/hdl/VC707Gen1x8If64.v | 20,968 | module MODULE1
parameter VAR32 = 8,
parameter VAR145 = 64,
parameter VAR21 = 256,
parameter VAR142 = 5
)
(output [(VAR32 - 1) : 0] VAR37,
output [(VAR32 - 1) : 0] VAR7,
input [(VAR32 - 1) : 0] VAR96,
input [(VAR32 - 1) : 0] VAR112,
output [3:0] VAR183,
input VAR4,
input VAR15,
input VAR80
);
wire VAR177;
wire VAR40;
wi... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_link/bsg_link_source_sync_downstream.v | 6,769 | module MODULE1
,parameter VAR29 = 6
,parameter VAR38 = 3
,parameter VAR34 = 0
,parameter VAR4 = 0
)
( input VAR47
,input VAR49
,input VAR25
,input VAR58 ,input [VAR39-1:0] VAR30 ,input VAR2 ,output VAR6
,output [VAR39-1:0] VAR44
,output VAR14
,input VAR54
);
wire VAR11, VAR62;
logic VAR21, VAR8;
logic [VAR39-1:0] VAR20... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_buf.v | 3,374 | if (VAR11 && (VAR4==VAR9) && VAR13) \
begin: VAR16 \
VAR17 VAR12 (.VAR10(VAR6),.VAR5); \
end \
else \
if (VAR11 && (VAR4==VAR9) && ~VAR13) \
begin: VAR16 \
VAR14 VAR12 (.VAR10(VAR6),.VAR5);\
end
module MODULE1 #(parameter VAR1(VAR4)
, parameter VAR11=1
, parameter VAR13=1
)
(input [VAR4-1:0] VAR6
, output [VAR4-1:0] VA... | bsd-3-clause |
SI-RISCV/e200_opensource | rtl/e203/perips/i2c_master_bit_ctrl.v | 20,190 | module MODULE1(
clk, rst, VAR25,
VAR33, VAR23, VAR27, VAR2, VAR3, VAR15, din, dout,
VAR43, VAR8, VAR44, VAR1, VAR16, VAR19
);
input clk;
input rst;
input VAR25;
input VAR23;
input [15:0] VAR33;
input [3:0] VAR27;
output VAR2; reg VAR2;
output VAR3; reg VAR3;
output VAR15; reg VAR15;
input din;
output dout;
reg dout;
in... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd.blackbox.v | 1,219 | module MODULE1 ();
supply1 VAR3;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41o/sky130_fd_sc_hs__a41o.symbol.v | 1,345 | module MODULE1 (
input VAR7,
input VAR2,
input VAR8,
input VAR6,
input VAR3,
output VAR4
);
supply1 VAR5;
supply0 VAR1;
endmodule | apache-2.0 |
uwsampa/zynqWrapper | hardware/BRAMFIFO.v | 2,856 | module MODULE1
parameter VAR22 = 32,
parameter VAR31 = 1024,
parameter VAR5 = 10
)
(
input VAR23,
input VAR9,
input [VAR22-1:0] VAR6,
output [VAR22-1:0] VAR28,
input VAR18,
input VAR3,
output VAR12,
output VAR20,
output [VAR5-1:0] VAR1,
input VAR8
);
reg [VAR5-1:0] VAR2, VAR11, VAR29; reg [VAR5-1:0] VAR25, VAR30, VAR17... | mit |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_gtp_wrapper.v | 29,802 | module MODULE1 #
(
parameter VAR293= 0, parameter VAR369 = 9'h14d, parameter VAR8 = "VAR42",
parameter VAR224 = "VAR42",
parameter VAR137 = "VAR47"
)
(
VAR136,
VAR226,
VAR95,
VAR156,
VAR72,
VAR390,
VAR235,
VAR227,
VAR48,
VAR248,
VAR352,
VAR186,
VAR37,
VAR300,
VAR102,
VAR228,
VAR121,
VAR237,
VAR258,
VAR265,
VAR20,
VAR19... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkinvkapwr/sky130_fd_sc_hd__lpflow_clkinvkapwr_16.v | 2,267 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR7,
VAR2 ,
VAR1 ,
VAR9 ,
VAR4
);
output VAR3 ;
input VAR8 ;
input VAR7;
input VAR2 ;
input VAR1 ;
input VAR9 ;
input VAR4 ;
VAR6 VAR5 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR3,
VAR8
);
output VAR3;
inpu... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch2/Mux_Array_DW_SHF.v | 2,843 | module MODULE1
(
input wire VAR17,
input wire [VAR20-1:0] VAR15,
input wire [VAR20-1:0] VAR19,
output reg [VAR20-1:0] VAR26
);
always @(VAR17, VAR15, VAR19)
case (VAR17)
1'b0: VAR26 <= VAR15;
1'b1: VAR26 <= VAR19;
endcase
endmodule
module MODULE2
(
input wire [VAR16-1:0] VAR11,
input wire VAR10,
output wire [VAR16-1:0]... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_2.behavioral.pp.v | 1,561 | module MODULE1( VAR1, VAR9, VAR3, VAR7, VAR8, VAR4 );
input VAR7, VAR3, VAR1;
inout VAR8, VAR4;
output VAR9;
VAR2 VAR5(.VAR1(VAR1),.VAR9(VAR9),.VAR3(VAR3),.VAR7(VAR7),.VAR8(VAR8),.VAR4(VAR4));
VAR2 VAR6(.VAR1(VAR1),.VAR9(VAR9),.VAR3(VAR3),.VAR7(VAR7),.VAR8(VAR8),.VAR4(VAR4)); | apache-2.0 |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/altera_up_character_lcd_communication.v | 10,248 | module MODULE1 (
clk,
reset,
VAR16,
enable,
VAR1,
VAR34,
VAR28,
VAR20,
VAR9,
VAR10,
VAR26,
VAR23,
VAR17,
VAR11,
VAR18,
VAR14
);
parameter VAR31 = 7'h7F; parameter VAR32 = 7; parameter VAR2 = 7'h01;
parameter VAR30 = 3; parameter VAR12 = 15; parameter VAR25 = 1; parameter VAR24 = 4; parameter VAR29 = 4'h1;
input clk;
in... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_2.behavioral.pp.v | 2,375 | module MODULE1( VAR6, VAR10, VAR2, VAR4, VAR8, VAR3, VAR7 );
input VAR8, VAR4, VAR10, VAR6;
inout VAR3, VAR7;
output VAR2;
VAR5 VAR9(.VAR6(VAR6),.VAR10(VAR10),.VAR2(VAR2),.VAR4(VAR4),.VAR8(VAR8),.VAR3(VAR3),.VAR7(VAR7));
VAR5 VAR1(.VAR6(VAR6),.VAR10(VAR10),.VAR2(VAR2),.VAR4(VAR4),.VAR8(VAR8),.VAR3(VAR3),.VAR7(VAR7)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2.blackbox.v | 1,323 | module MODULE1 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
supply1 VAR4;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_37.v | 27,299 | module MODULE5 (
clk,
reset,
VAR165,
VAR224,
VAR46,
VAR127,
VAR146
);
parameter VAR111 = 18;
parameter VAR182 = 37;
parameter VAR104 = 19;
localparam VAR16 = 44;
input clk;
input reset;
input VAR165;
input VAR224;
input [VAR111-1:0] VAR46; output VAR127;
output [VAR111-1:0] VAR146;
localparam VAR163 = 18; localparam VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfsbp/sky130_fd_sc_hd__dfsbp.symbol.v | 1,413 | module MODULE1 (
input VAR8 ,
output VAR4 ,
output VAR1 ,
input VAR5,
input VAR6
);
supply1 VAR2;
supply0 VAR9;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
alexforencich/verilog-axis | rtl/axis_register.v | 10,298 | module MODULE1 #
(
parameter VAR21 = 8,
parameter VAR27 = (VAR21>8),
parameter VAR46 = ((VAR21+7)/8),
parameter VAR24 = 1,
parameter VAR3 = 0,
parameter VAR36 = 8,
parameter VAR7 = 0,
parameter VAR37 = 8,
parameter VAR1 = 1,
parameter VAR6 = 1,
parameter VAR16 = 2
)
(
input wire clk,
input wire rst,
input wire [VAR21-1... | mit |
aquaxis/FPGAMAG18 | fmrv32im-artya7.nonos/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ip/fmrv32im_artya7_fmrv32im_timer_0_0/synth/fmrv32im_artya7_fmrv32im_timer_0_0.v | 3,383 | module MODULE1 (
VAR2,
VAR5,
VAR4,
VAR8,
VAR1,
VAR7,
VAR6
);
input wire VAR2;
input wire VAR5;
input wire VAR4;
input wire [3 : 0] VAR8;
input wire [31 : 0] VAR1;
output wire [31 : 0] VAR7;
output wire VAR6;
VAR3 VAR9 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodu... | mit |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/phy/mig_7series_v4_0_ddr_if_post_fifo.v | 8,567 | module MODULE1 #
(
parameter VAR1 = 100, parameter VAR29 = 4, parameter VAR12 = 32 )
(
input clk, input rst, input [3:0] VAR4,
input VAR15,
input [VAR12-1:0] din, output VAR9,
output VAR7,
output [VAR12-1:0] dout );
localparam VAR5
= (VAR29 == 2) ? 1 :
(((VAR29 == 3) || (VAR29 == 4)) ? 2 : 'VAR8);
integer VAR27;
reg [V... | mit |
sudov/options-accel | zedboard/xillinux-eval-zedboard-1.1/verilog/src/xillybus_core.v | 2,975 | module MODULE1
(
input VAR36,
input VAR47,
input [1:0] VAR26,
input VAR50,
input [31:0] VAR97,
input VAR53,
input [1:0] VAR64,
input VAR78,
input VAR44,
input [31:0] VAR89,
input VAR12,
input [31:0] VAR90,
input VAR66,
input VAR63,
input VAR38,
input [31:0] VAR22,
input [3:0] VAR39,
input VAR18,
input VAR72,
input VAR2... | apache-2.0 |
alonso193/proyecto1 | Pruebas/DATA_SD/DATA_PHYSICAL.v | 13,192 | module MODULE1(
input wire VAR10,
input wire VAR30,
input wire VAR25,
input wire VAR35,
input wire [15:0] VAR17,
input wire [3:0] VAR28,
input wire VAR37,
input wire VAR34,
input wire VAR12,
input wire VAR26,
input wire VAR41,
input wire [31:0] VAR6,
input wire [31:0] VAR32,
output reg VAR14,
output reg VAR36,
output r... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxbp/sky130_fd_sc_hd__sedfxbp.behavioral.v | 2,734 | module MODULE1 (
VAR12 ,
VAR25,
VAR3,
VAR22 ,
VAR18 ,
VAR14,
VAR5
);
output VAR12 ;
output VAR25;
input VAR3;
input VAR22 ;
input VAR18 ;
input VAR14;
input VAR5;
supply1 VAR2;
supply0 VAR24;
supply1 VAR17 ;
supply0 VAR26 ;
wire VAR20 ;
reg VAR31 ;
wire VAR29 ;
wire VAR9 ;
wire VAR27;
wire VAR1;
wire VAR10;
wire VAR7 ;... | apache-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_align.v | 2,500 | module MODULE1
(VAR5, VAR7, VAR3);
parameter VAR8 = 32;
parameter VAR6 = 32;
parameter VAR2 = 0;
input [0:VAR8-1] VAR5;
input [0:VAR6-1] VAR7;
output [0:VAR6-1] VAR3;
wire [0:VAR6-1] VAR3;
genvar VAR1;
generate
for(VAR1 = 0; VAR1 < VAR6; VAR1 = VAR1 + 1)
begin:VAR4
if((VAR1 < VAR2) || (VAR1 >= (VAR2 + VAR8)))
assign VA... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/ram_1clk_1w_1r.v | 3,218 | module MODULE1
parameter VAR10 = 32,
parameter VAR2 = 1024
)
(
input VAR6,
input [VAR11(VAR2)-1:0] VAR4,
input VAR7,
input [VAR11(VAR2)-1:0] VAR9,
input [VAR10-1:0] VAR8,
output [VAR10-1:0] VAR12
);
localparam VAR1 = VAR11(VAR2);
reg [VAR10-1:0] VAR3 [VAR2-1:0];
reg [VAR10-1:0] VAR5;
assign VAR12 = VAR5;
always @(posed... | gpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/v5_mig34.v | 18,818 | module MODULE1 #
(
parameter VAR144 = 2,
parameter VAR116 = 2, parameter VAR7 = 2,
parameter VAR52 = 10,
parameter VAR95 = 1,
parameter VAR90 = 2,
parameter VAR68 = 0,
parameter VAR4 = 4,
parameter VAR58 = 32,
parameter VAR78 = 8,
parameter VAR57 = 4,
parameter VAR110 = 5,
parameter VAR103 = 2,
parameter VAR142 = 2,
pa... | lgpl-3.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_top.v | 26,355 | module MODULE1(
VAR395, VAR57, VAR145, VAR90,
VAR116, VAR144, VAR232, VAR278, VAR75, VAR276,
VAR228, VAR6, VAR202, VAR236, VAR373, VAR24,
VAR298,
VAR104, VAR27,
VAR158, VAR182, VAR52, VAR248, VAR213, VAR21,
VAR258, VAR146, VAR396, VAR194, VAR13, VAR391,
VAR41,
VAR360, VAR299,
VAR246, VAR302, VAR79, VAR323, VAR174, VAR5... | gpl-2.0 |
qmn/riscv-invicta | hardware/src/branch_jump.v | 2,600 | module MODULE1 (
output VAR10,
output [31:0] VAR6,
output VAR1,
output [31:0] VAR17,
input [31:0] VAR8,
input [31:0] VAR15,
input [31:0] VAR5,
input [31:0] VAR16
);
wire [6:0] VAR9 = VAR8[6:0];
wire [2:0] VAR3 = VAR8[9:7];
wire [11:0] VAR14 = {VAR8[31:27], VAR8[16:10]};
wire [31:0] VAR11 = VAR14[11] ? {20'hFFFFF, VAR14... | bsd-2-clause |
dennis-musk/socfpga | interrupt/fpga/rtl/sockit_top.v | 1,682 | module MODULE1 (
input VAR3,
input VAR2,
input [3:0] VAR8,
input [3:0] VAR34,
output [3:0] VAR27,
output [14:0] VAR42,
output [2:0] VAR20,
output VAR22,
output VAR6,
output VAR24,
output VAR32,
output VAR17,
output VAR37,
output VAR25,
output VAR1,
inout [39:0] VAR21,
inout [4:0] VAR40,
inout [4:0] VAR11,
output VAR18,... | gpl-3.0 |
Blunk-electronic/M-1 | HW/ise/trc_mini/src/main.v | 7,872 | module MODULE1 (
input VAR40,
input VAR70,
input VAR49,
input VAR29,
input VAR22,
input VAR34,
input VAR54,
input VAR7,
input VAR12,
output VAR56,
output VAR16,
inout VAR65,
input VAR43,
output [7:0] VAR59, output [7:0] VAR5,
input VAR52,
input VAR44,
output reg VAR21,
output reg VAR23,
output reg VAR24,
output reg VAR... | gpl-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_14.v | 11,696 | module MODULE4 (
clk,
reset,
VAR89,
VAR82,
VAR44,
VAR75,
VAR7
);
parameter VAR15 = 18;
parameter VAR97 = 14;
parameter VAR71 = 7;
localparam VAR24 = 15;
input clk;
input reset;
input VAR89;
input VAR82;
input [VAR15-1:0] VAR44; output VAR75;
output [VAR15-1:0] VAR7;
localparam VAR9 = 18; localparam VAR30 = 36; localpar... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlrtp/sky130_fd_sc_hvl__dlrtp.functional.v | 1,710 | module MODULE1 (
VAR6 ,
VAR4,
VAR10 ,
VAR8
);
output VAR6 ;
input VAR4;
input VAR10 ;
input VAR8 ;
wire VAR5;
wire VAR2;
not VAR1 (VAR5 , VAR4 );
VAR11 VAR3 VAR9 (VAR2 , VAR10, VAR8, VAR5 );
buf VAR7 (VAR6 , VAR2 );
endmodule | apache-2.0 |
mshaklunov/mips_onemore | rtl/mips_greg.v | 1,029 | module MODULE1 (
input clk,
input rst,
input[4:0] VAR4,
input[4:0] VAR3,
output[31:0] VAR9,
output[31:0] VAR7,
input[4:0] VAR5,
input VAR8,
input[31:0] VAR10
);
reg[31:0] VAR11[31:1];
integer VAR2;
assign VAR9= VAR4==5'd0 ? 32'd0 : VAR11[VAR4];
assign VAR7= VAR3==5'd0 ? 32'd0 : VAR11[VAR3];
generate
genvar VAR6;
for(VA... | mit |
aben20807/bomb | bomb.v | 20,443 | module MODULE1(reset, VAR12, VAR48, VAR68, VAR54, VAR79, VAR21, VAR75, VAR80, VAR5, VAR32, VAR46, VAR69, VAR17, VAR25, VAR65, VAR89, VAR43, VAR7, VAR39, VAR41, VAR53, VAR20, VAR81, VAR72);
input VAR12, reset, VAR68, VAR21, VAR79, VAR54;
input [3:0]VAR48;
input [3:0]VAR32;
output [3:0]VAR46;
output [15:0]VAR69;
output [... | mit |
SI-RISCV/e200_opensource | rtl/e203/soc/e203_soc_top.v | 29,264 | module MODULE1(
input VAR15,
output VAR171,
input VAR114,
output VAR297,
input VAR258,
input VAR344,
input VAR273,
output VAR330,
output VAR325,
input VAR228,
output VAR79,
output VAR124,
output VAR48,
output VAR336,
output VAR316,
input VAR329,
output VAR322,
output VAR176,
output VAR22,
output VAR137,
output VAR31,
i... | apache-2.0 |
Ribeiro/sd2snes | verilog/sd2snes/mcu_cmd.v | 16,322 | module MODULE1(
input clk,
input VAR1,
input VAR51,
input [7:0] VAR14,
input [7:0] VAR40,
output [2:0] VAR30,
output VAR7,
output VAR54,
output VAR52,
input VAR60,
output [7:0] VAR39,
input [7:0] VAR3,
output [7:0] VAR58,
input [31:0] VAR47,
input [2:0] VAR63,
output [23:0] VAR46,
output [23:0] VAR56,
output [23:0] VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbn/sky130_fd_sc_ms__dlrbn.symbol.v | 1,454 | module MODULE1 (
input VAR3 ,
output VAR9 ,
output VAR5 ,
input VAR8,
input VAR7
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_pipe_reset.v | 22,132 | module MODULE1 #
(
parameter VAR34 = "VAR30", parameter VAR25 = "VAR23",
parameter VAR68 = "VAR53", parameter VAR18 = "VAR56", parameter VAR69 = "VAR30", parameter VAR51 = 1, parameter VAR57 = 6'd63, parameter VAR65 = 1
)
(
input VAR31,
input VAR52,
input VAR6,
input VAR13,
input [VAR51-1:0] VAR37,
input [VAR51-1:0] VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2.behavioral.pp.v | 1,681 | module MODULE1 (
VAR5,
VAR2,
VAR4 ,
VAR1 ,
VAR3
);
input VAR5;
input VAR2;
output VAR4 ;
input VAR1 ;
input VAR3 ;
wire VAR9 ;
wire VAR8;
nor VAR11 (VAR9 , VAR1, VAR3 );
VAR7 VAR10 (VAR8, VAR9, VAR5, VAR2);
buf VAR6 (VAR4 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21bai/sky130_fd_sc_hs__o21bai.functional.v | 2,056 | module MODULE1 (
VAR15,
VAR5,
VAR6 ,
VAR8 ,
VAR14 ,
VAR7
);
input VAR15;
input VAR5;
output VAR6 ;
input VAR8 ;
input VAR14 ;
input VAR7;
wire VAR3 ;
wire VAR10 ;
wire VAR4 ;
wire VAR1;
not VAR13 (VAR3 , VAR7 );
or VAR16 (VAR10 , VAR14, VAR8 );
nand VAR11 (VAR4 , VAR3, VAR10 );
VAR9 VAR2 (VAR1, VAR4, VAR15, VAR5);
buf ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111o/sky130_fd_sc_ls__a2111o.pp.blackbox.v | 1,427 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR5 ,
VAR4 ,
VAR10 ,
VAR1 ,
VAR8,
VAR9,
VAR6 ,
VAR7
);
output VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR10 ;
input VAR1 ;
input VAR8;
input VAR9;
input VAR6 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbp/sky130_fd_sc_lp__dlrbp.blackbox.v | 1,407 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR7,
VAR3 ,
VAR9
);
output VAR6 ;
output VAR5 ;
input VAR7;
input VAR3 ;
input VAR9 ;
supply1 VAR2;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/seq_gen/seq_gen_core.v | 8,656 | module MODULE1 #(
parameter VAR70 = 16,
parameter VAR37 = 16384,
parameter VAR32 = 8
) (
VAR9,
VAR74,
VAR26,
VAR60,
VAR5,
VAR8,
VAR54,
VAR23,
VAR44,
VAR24
);
localparam VAR31 = 3;
localparam VAR38 = 64;
input wire VAR9;
input wire VAR74;
input wire [VAR70-1:0] VAR26;
input wire [7:0] VAR60;
input wire VAR5;
input wire ... | bsd-3-clause |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_cntlr.v | 9,807 | module MODULE1 #
(parameter VAR34 = 100,
parameter VAR5 = 3,
parameter VAR28 = 8)
(
VAR23, VAR20, VAR33,
VAR2, VAR37, VAR6,
VAR44, VAR30, VAR10,
VAR16, VAR50, VAR49,
VAR1,
clk, rst, VAR26, VAR39,
VAR18, VAR29, VAR8,
VAR36, VAR43, VAR31
);
localparam VAR42 = 1;
input clk;
input rst;
output VAR23, VAR20;
reg VAR7, VAR22,... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_064.v | 1,438 | module MODULE1 (
VAR12,
VAR10
);
input [31:0] VAR12;
output [31:0]
VAR10;
wire [31:0]
VAR2,
VAR3,
VAR9,
VAR5,
VAR11,
VAR4,
VAR7;
assign VAR2 = VAR12;
assign VAR3 = VAR2 << 8;
assign VAR9 = VAR2 + VAR3;
assign VAR11 = VAR9 + VAR5;
assign VAR4 = VAR11 << 4;
assign VAR7 = VAR11 + VAR4;
assign VAR5 = VAR2 << 6;
assign VAR1... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_csc_1_mul.v | 6,879 | module MODULE1 (
clk,
VAR25,
VAR2,
VAR24,
VAR1,
VAR20);
parameter VAR18 = 16;
parameter VAR16 = VAR18 - 1;
input clk;
input [16:0] VAR25;
input [ 7:0] VAR2;
output [24:0] VAR24;
input [VAR16:0] VAR1;
output [VAR16:0] VAR20;
reg VAR15 = 'd0;
reg [VAR16:0] VAR4 = 'd0;
reg [23:0] VAR3 = 'd0;
reg [23:0] VAR23 = 'd0;
reg [2... | mit |
peteasa/parallella-fpga | AdaptevaLib/elink-gold/ewrapper_link_top.v | 15,626 | module MODULE1 (
VAR4, VAR34, VAR162,
VAR48, VAR148, VAR44,
VAR89, VAR51, VAR169,
VAR59, VAR141, VAR12, VAR100,
VAR21, VAR14, VAR126, VAR144, VAR149,
VAR76, VAR107, VAR95, VAR143,
reset, VAR86, VAR70, VAR74, VAR117,
VAR20, VAR177, VAR7,
VAR175, VAR164, VAR5,
VAR10, VAR77, VAR109,
VAR170, VAR91, VAR132, VAR58, VAR106,
V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.v | 2,289 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR1 ,
VAR8,
VAR7,
VAR2,
VAR6 ,
VAR4
);
output VAR3 ;
output VAR10 ;
input VAR1 ;
input VAR8;
input VAR7;
input VAR2;
input VAR6 ;
input VAR4 ;
VAR9 VAR5 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE1... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab3/fir_prj/solution2/syn/verilog/fir.v | 10,380 | module MODULE1 (
VAR52,
VAR23,
VAR45,
VAR21,
VAR26,
VAR7,
VAR25,
VAR41,
VAR14,
VAR48,
VAR4,
VAR3,
VAR56
);
parameter VAR19 = 7'd1;
parameter VAR38 = 7'd2;
parameter VAR58 = 7'd4;
parameter VAR11 = 7'd8;
parameter VAR42 = 7'd16;
parameter VAR57 = 7'd32;
parameter VAR40 = 7'd64;
input VAR52;
input VAR23;
input VAR45;
out... | mit |
monotone-RK/FACE | IEICE-Trans/8-way_2-tree/src/ip_dram/phy/mig_7series_v2_3_ddr_phy_rdlvl.v | 145,954 | module MODULE1 #
(
parameter VAR139 = 100, parameter VAR309 = 2, parameter VAR264 = 3333, parameter VAR30 = 64, parameter VAR208 = 3, parameter VAR158 = 8, parameter VAR252 = 8, parameter VAR231 = 1, parameter VAR68 = "VAR140", parameter VAR207 = "VAR288", parameter VAR393 = "VAR120", parameter VAR130 = "VAR95", parame... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.cache/ip/2018.2/abb00b3e1f316b47/gcd_zynq_snick_rst_ps7_0_49M_0_stub.v | 1,885 | module MODULE1(VAR6, VAR8, VAR5,
VAR9, VAR2, VAR10, VAR7, VAR1,
VAR3, VAR4)
;
input VAR6;
input VAR8;
input VAR5;
input VAR9;
input VAR2;
output VAR10;
output [0:0]VAR7;
output [0:0]VAR1;
output [0:0]VAR3;
output [0:0]VAR4;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf.behavioral.pp.v | 1,790 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR5,
VAR2,
VAR7 ,
VAR12
);
output VAR8 ;
input VAR11 ;
input VAR5;
input VAR2;
input VAR7 ;
input VAR12 ;
wire VAR3 ;
wire VAR1;
buf VAR9 (VAR3 , VAR11 );
VAR10 VAR4 (VAR1, VAR3, VAR5, VAR2);
buf VAR6 (VAR8 , VAR1 );
endmodule | apache-2.0 |
linuxbest/lzs | pcores/comp_unit_v1_00_a/hdl/verilog/ch.v | 6,814 | module MODULE1(
VAR60, VAR67, VAR38, VAR7, VAR36,
VAR45, VAR24, VAR40, VAR62, VAR69,
VAR37, VAR17, VAR18, VAR64,
VAR65, VAR48, VAR59,
VAR52, VAR63, VAR19, VAR42, VAR50,
VAR33, VAR68, VAR41, VAR57, VAR25,
VAR26, VAR43, VAR34, VAR4, VAR61, VAR22,
VAR14
);
input VAR52;
input VAR63;
input VAR19,
VAR42;
input VAR50,
VAR33;
... | gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_if.v | 8,724 | module MODULE1(
clk, rst,
VAR4, VAR10, VAR14, VAR16, VAR1,
VAR6, VAR2, VAR15, VAR21,
VAR12, VAR18, VAR8, VAR3,
VAR13, VAR19, VAR5
);
input clk;
input rst;
input [31:0] VAR4;
input VAR10;
input VAR14;
input [31:0] VAR16;
input [3:0] VAR1;
input VAR6;
output [31:0] VAR2;
output [31:0] VAR15;
input VAR21;
output VAR12;
in... | gpl-2.0 |
SymbiFlow/yosys | techlibs/efinix/arith_map.v | 2,442 | module MODULE1(
module 80efinixalu (VAR20, VAR11, VAR3, VAR23, VAR7, VAR30, VAR32);
parameter VAR21 = 0;
parameter VAR27 = 0;
parameter VAR4 = 1;
parameter VAR14 = 1;
parameter VAR22 = 1;
input [VAR4-1:0] VAR20;
input [VAR14-1:0] VAR11;
output [VAR22-1:0] VAR7, VAR30;
input VAR3, VAR23;
output [VAR22-1:0] VAR32;
wire V... | isc |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_inv.v | 3,301 | if (VAR18 && (VAR19==VAR20) && VAR11) \
begin: VAR16 \
VAR17 VAR2 (.VAR3(VAR1),.VAR10); \
end \
else \
if (VAR18 && (VAR19==VAR20) && ~VAR11) \
begin: VAR16 \
VAR13 VAR2 (.VAR3(VAR1),.VAR10); \
end
module MODULE1 #(parameter VAR4(VAR19)
, parameter VAR18=1
, parameter VAR11=1
)
(input [VAR19-1:0] VAR1
, output [VAR19-1... | bsd-3-clause |
peteasa/oh | src/common/hdl/oh_stretcher.v | 1,118 | module MODULE1 #(parameter VAR2 = 5) ( input clk, input in, input VAR1, output out );
reg [VAR2-1:0] valid;
always @ (posedge clk or negedge VAR1)
if(!VAR1)
valid[VAR2-1:0] <='b0;
else if(in)
valid[VAR2-1:0] <={(VAR2){1'b1}};
else
valid[VAR2-1:0] <={valid[VAR2-2:0],1'b0};
assign out = valid[VAR2-1];
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4b/sky130_fd_sc_ls__nand4b.behavioral.v | 1,528 | module MODULE1 (
VAR4 ,
VAR14,
VAR13 ,
VAR2 ,
VAR9
);
output VAR4 ;
input VAR14;
input VAR13 ;
input VAR2 ;
input VAR9 ;
supply1 VAR12;
supply0 VAR1;
supply1 VAR11 ;
supply0 VAR8 ;
wire VAR7 ;
wire VAR6;
not VAR3 (VAR7 , VAR14 );
nand VAR5 (VAR6, VAR9, VAR2, VAR13, VAR7);
buf VAR10 (VAR4 , VAR6 );
endmodule | apache-2.0 |
zhijian-liu/mips-cpu | src/cpu/stage/stage_id.v | 42,167 | module MODULE1(
input reset ,
input [31:0] VAR12 ,
output [31:0] VAR14 ,
output reg [ 7:0] VAR23 ,
output reg [ 2:0] VAR37 ,
output reg [31:0] VAR42 ,
output reg [31:0] VAR21 ,
output reg VAR16 ,
output reg [ 4:0] VAR44 ,
input [31:0] VAR10 ,
output reg VAR28 ,
output reg [ 4:0] VAR3 ,
input [31:0] VAR35 ,
output reg V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/ha/sky130_fd_sc_hs__ha_1.v | 2,057 | module MODULE1 (
VAR8,
VAR5 ,
VAR2 ,
VAR7 ,
VAR6,
VAR4
);
output VAR8;
output VAR5 ;
input VAR2 ;
input VAR7 ;
input VAR6;
input VAR4;
VAR1 VAR3 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR8,
VAR5 ,
VAR2 ,
VAR7
);
output VAR8;
output VAR5 ;
input VAR2 ... | apache-2.0 |
which0326/ca_project2 | code/ID_EX.v | 2,170 | module MODULE1(input clk,
input reset,
input [1:0] VAR19,
input [1:0] VAR23,
input [3:0] VAR7,
input [31:0] VAR16,
input [31:0] VAR3,
input [31:0] VAR14,
input [4:0] VAR1,
input [4:0] VAR5,
input [4:0] VAR10,
input [5:0] VAR22,
input [31:0] VAR6,
input VAR24,
output reg[1:0] VAR8,
output reg[1:0] VAR2,
output reg VAR13... | cc0-1.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_gt.v | 7,737 | module MODULE1 (
VAR31,
VAR10,
VAR19,
VAR18,
VAR30,
VAR4,
VAR12,
VAR25,
VAR23,
VAR24,
VAR9,
VAR17,
VAR15,
VAR5,
VAR6,
VAR27,
VAR22,
VAR20,
VAR13,
VAR21,
VAR11,
VAR3);
parameter integer VAR8 = 0;
output VAR31;
output VAR10;
output [11:0] VAR19;
output [15:0] VAR18;
input [15:0] VAR30;
input VAR4;
output VAR12;
output VA... | lgpl-3.0 |
sirchuckalot/zet | cores/ps2/rtl/ps2_mouse_nofifo.v | 2,064 | module MODULE1 (
input clk,
input reset,
input [7:0] VAR1, input write, input VAR2,
output [7:0] VAR9, output irq,
output VAR5,
output VAR14,
output VAR6,
inout VAR15,
inout VAR7
);
wire VAR11;
wire VAR8;
VAR4 VAR12 (
.clk (clk),
.reset (reset),
.VAR13 (VAR1),
.VAR16 (write),
.VAR10 (VAR9),
.VAR3 (irq),
.VAR2 (VAR2),
.... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_csc_1_add.v | 5,885 | module MODULE1 (
clk,
VAR23,
VAR17,
VAR4,
VAR24,
VAR7,
VAR12,
VAR29);
parameter VAR18 = 16;
parameter VAR27 = VAR18 - 1;
input clk;
input [24:0] VAR23;
input [24:0] VAR17;
input [24:0] VAR4;
input [24:0] VAR24;
output [ 7:0] VAR7;
input [VAR27:0] VAR12;
output [VAR27:0] VAR29;
reg [VAR27:0] VAR8 = 'd0;
reg [24:0] VAR5 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111o/sky130_fd_sc_ls__a2111o.pp.symbol.v | 1,400 | module MODULE1 (
input VAR10 ,
input VAR8 ,
input VAR3 ,
input VAR9 ,
input VAR5 ,
output VAR4 ,
input VAR2 ,
input VAR6,
input VAR1,
input VAR7
);
endmodule | apache-2.0 |
timtian090/Playground | UVM/UVMPlayground/Lab3/Lab3-Project/LED_Segment_Mapper.v | 3,911 | module MODULE1
(
input VAR3,
input VAR7,
input [15:0] VAR5,
input [15:0] VAR12,
output [6:0] VAR1,
output [6:0] VAR6,
output [6:0] VAR2,
output [6:0] VAR8,
output [6:0] VAR10,
output [6:0] VAR9,
input VAR11
);
reg [15:0] VAR4;
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_hvc_wpad/sky130_fd_io__top_power_hvc_wpad.symbol.v | 1,667 | module MODULE1 (
inout VAR2 ,
inout VAR1,
inout VAR5
);
supply1 VAR17 ;
supply1 VAR6 ;
supply0 VAR10;
supply1 VAR4 ;
supply1 VAR8 ;
supply1 VAR9 ;
supply1 VAR14 ;
supply1 VAR3 ;
supply1 VAR7 ;
supply1 VAR11 ;
supply0 VAR15 ;
supply0 VAR12 ;
supply0 VAR13 ;
supply0 VAR16 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2/sky130_fd_sc_hdll__and2_8.v | 2,102 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR1 ,
VAR6,
VAR9,
VAR5 ,
VAR8
);
output VAR4 ;
input VAR3 ;
input VAR1 ;
input VAR6;
input VAR9;
input VAR5 ;
input VAR8 ;
VAR2 VAR7 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR4,
VAR3,
VAR1
);
output VAR4;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o.pp.blackbox.v | 1,473 | module MODULE1 (
VAR8 ,
VAR6,
VAR9,
VAR7 ,
VAR2 ,
VAR1,
VAR4,
VAR3 ,
VAR5
);
output VAR8 ;
input VAR6;
input VAR9;
input VAR7 ;
input VAR2 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/Fetch.v | 3,634 | module MODULE1(
input [15:0] VAR11,
input VAR14,
input VAR22,
output reg [31:0] VAR15 = 32'h00000000,
output reg [31:0] VAR21 = 32'h00000000,
output reg [31:0] VAR3 = 32'h00000000,
output reg [1:0] VAR2,
output reg VAR17,
output reg VAR9 = 1'b0
);
wire [3:0] VAR23;
wire [3:0] VAR4;
wire [3:0] VAR5;
wire [3:0] VAR10;
as... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/ps2/verilog/ps2_wb.v | 3,737 | module MODULE1( input wire VAR14,
input wire VAR26,
input wire [7:0] VAR7,
output wire [7:0] VAR43,
input wire [0:0] VAR15,
input wire VAR19,
input wire VAR10,
output wire VAR5,
output wire VAR9,
inout wire VAR34,
inout wire VAR3
);
wire VAR24;
wire [7:0] VAR17;
wire [7:0] VAR8;
wire VAR13;
wire VAR30;
wire VAR6;
wire ... | gpl-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cpu/apu/apu_mixer.v | 6,648 | module MODULE1
(
input wire VAR5, input wire VAR19, input wire [3:0] VAR2, input wire [3:0] VAR6, input wire [3:0] VAR13, input wire [3:0] VAR15, input wire [3:0] VAR8, output wire VAR10 );
wire [3:0] VAR4;
wire [3:0] VAR3;
wire [3:0] VAR16;
wire [3:0] VAR12;
reg [4:0] VAR20;
reg [5:0] VAR17;
reg [6:0] VAR14;
reg [5:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41o/sky130_fd_sc_hd__a41o.blackbox.v | 1,382 | module MODULE1 (
VAR1 ,
VAR7,
VAR9,
VAR10,
VAR4,
VAR8
);
output VAR1 ;
input VAR7;
input VAR9;
input VAR10;
input VAR4;
input VAR8;
supply1 VAR3;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtp/sky130_fd_sc_hdll__dlrtp.behavioral.v | 2,308 | module MODULE1 (
VAR7 ,
VAR14,
VAR19 ,
VAR1
);
output VAR7 ;
input VAR14;
input VAR19 ;
input VAR1 ;
supply1 VAR9;
supply0 VAR16;
supply1 VAR12 ;
supply0 VAR18 ;
wire VAR13 ;
reg VAR11 ;
wire VAR4 ;
wire VAR15 ;
wire VAR20 ;
wire VAR17;
wire VAR6 ;
wire VAR8 ;
wire VAR2 ;
wire VAR5 ;
not VAR21 (VAR13 , VAR17 );
VAR22 V... | apache-2.0 |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_arb_rd_4.v | 6,386 | module MODULE1(
VAR29,
VAR21,
VAR39,
VAR19,
VAR38,
VAR11,
VAR27,
VAR5,
VAR41,
VAR3,
VAR14,
VAR34,
VAR18,
VAR10,
VAR1,
VAR25,
VAR9,
VAR40,
VAR31,
VAR32,
VAR36,
VAR8,
VAR24,
VAR23,
VAR30,
VAR13,
VAR16,
VAR17,
VAR20,
VAR28,
VAR2,
VAR22
);
input VAR29, VAR21;
input [VAR15-1:0] VAR39,VAR19,VAR38,VAR11;
input VAR27, VAR5,VAR... | gpl-3.0 |
plindstroem/oh | edma/hdl/edma.v | 7,586 | module MODULE1 (
VAR7, VAR11, VAR9,
reset, clk, VAR5, VAR1, VAR3, VAR10, VAR6
);
parameter VAR4 = 6;
parameter VAR12 = 32;
parameter VAR2 = 32;
parameter VAR8 = 104;
input reset;
input clk;
input VAR5;
input VAR1;
input [VAR4+1:0] VAR3;
input [63:0] VAR10;
output [31:0] VAR7;
output VAR11;
output [VAR8-1:0] VAR9;
input... | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/synth/pr_region_default_Top_0.v | 8,222 | module MODULE1 (
input wire VAR45, output wire [5:0] VAR13, output wire [31:0] VAR5, output wire [31:0] VAR47, output wire [7:0] VAR34, output wire [2:0] VAR11, output wire [1:0] VAR27, output wire VAR16, output wire [3:0] VAR15, output wire [2:0] VAR21, output wire [3:0] VAR18, output wire VAR9, input wire VAR7, outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31o/sky130_fd_sc_hd__a31o.symbol.v | 1,361 | module MODULE1 (
input VAR3,
input VAR9,
input VAR7,
input VAR1,
output VAR6
);
supply1 VAR4;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pr_pp_pkg_sn/sky130_fd_sc_hs__udp_dff_pr_pp_pkg_sn.blackbox.v | 1,519 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR5 ,
VAR2 ,
VAR6 ,
VAR3,
VAR1 ,
VAR9 ,
VAR8
);
output VAR4 ;
input VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR3;
input VAR1 ;
input VAR9 ;
input VAR8 ;
endmodule | apache-2.0 |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodTMP3_v1_0/src/PmodTMP3.v | 9,441 | module MODULE1
(VAR55,
VAR58,
VAR73,
VAR48,
VAR144,
VAR39,
VAR33,
VAR108,
VAR80,
VAR2,
VAR109,
VAR70,
VAR38,
VAR154,
VAR71,
VAR46,
VAR23,
VAR147,
VAR122,
VAR20,
VAR139,
VAR84,
VAR148,
VAR110,
VAR25,
VAR91,
VAR101,
VAR134,
VAR135,
VAR26,
VAR115,
VAR123,
VAR149,
VAR53,
VAR132,
VAR102,
VAR42,
VAR127,
VAR78,
VAR98,
VAR129,... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decap/sky130_fd_sc_ls__decap.functional.pp.v | 1,172 | module MODULE1 (
VAR2,
VAR1,
VAR4 ,
VAR3
);
input VAR2;
input VAR1;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
cpulabs/mist1032sa | src/endian_controller.v | 2,383 | module MODULE1(
input wire [3:0] VAR3,
input wire [31:0] VAR6,
output wire [3:0] VAR4,
output wire [31:0] VAR2
);
assign VAR4 = VAR3;
assign VAR2 = VAR7(VAR3, VAR6);
function [31:0] VAR7;
input [3:0] VAR5;
input [31:0] VAR1;
begin
if(VAR5 == 4'hf)begin
VAR7 = {VAR1[7:0], VAR1[15:8], VAR1[23:16], VAR1[31:24]};
end
else ... | bsd-2-clause |
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