repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
m-labs/milkymist | cores/vgafb/rtl/vgafb.v | 5,010 | module MODULE1 #(
parameter VAR9 = 4'h0,
parameter VAR69 = 26
) (
input VAR61,
input VAR38,
input [13:0] VAR42,
input VAR45,
input [31:0] VAR13,
output [31:0] VAR29,
output [VAR69-1:0] VAR51,
output VAR6,
input VAR53,
input [63:0] VAR60,
output VAR28,
output [VAR69-1:0] VAR30,
input [63:0] VAR52,
input VAR34,
input VAR... | lgpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/dest_ip_filter.v | 9,925 | module MODULE1
parameter VAR35 = VAR31,
parameter VAR21 = VAR33(VAR35)
)
( input [VAR14-1:0] VAR58,
output VAR32,
output VAR28,
input VAR42,
input VAR11,
input VAR34,
input [VAR21-1:0] VAR27, input VAR1, output [31:0] VAR78, output VAR39,
input [VAR21-1:0] VAR82,
input VAR36,
input [31:0] VAR71, output VAR4,
input rese... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_1.behavioral.v | 1,267 | module MODULE1( VAR4, VAR6, VAR5, VAR2 );
input VAR2, VAR5, VAR4;
output VAR6;
VAR3 VAR7(.VAR4(VAR4),.VAR6(VAR6),.VAR5(VAR5),.VAR2(VAR2));
VAR3 VAR1(.VAR4(VAR4),.VAR6(VAR6),.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3b/sky130_fd_sc_hd__nand3b.pp.blackbox.v | 1,320 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR2 ,
VAR1 ,
VAR8,
VAR5,
VAR6 ,
VAR4
);
output VAR3 ;
input VAR7 ;
input VAR2 ;
input VAR1 ;
input VAR8;
input VAR5;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
sudov/options-accel | xillinux-eval-zedboard-1.1/system/hdl/system_xillyvga_0_wrapper.v | 5,294 | module MODULE1
(
VAR38,
VAR2,
VAR12,
VAR35,
VAR66,
VAR27,
VAR32,
VAR39,
VAR5,
VAR62,
VAR23,
VAR36,
VAR17,
VAR43,
VAR9,
VAR7,
VAR8,
VAR24,
VAR64,
VAR46,
VAR13,
VAR20,
VAR6,
VAR69,
VAR22,
VAR28,
VAR53,
VAR49,
VAR57,
VAR45,
VAR71,
VAR44,
VAR50,
VAR59,
VAR3,
VAR68,
VAR70,
VAR14,
VAR40,
VAR15,
VAR11,
VAR47,
VAR25,
VAR56,
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2.behavioral.v | 1,759 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR1,
VAR2
);
output VAR3 ;
input VAR6 ;
input VAR1;
input VAR2;
wire VAR10 ;
wire VAR5;
not VAR8 (VAR10 , VAR6 );
VAR4 VAR9 (VAR5, VAR10, VAR1, VAR2);
buf VAR7 (VAR3 , VAR5 );
endmodule | apache-2.0 |
maijohnson/comp3601_blue_15s2 | AudioController/bpmcalculator.v | 3,089 | module MODULE1(
input wire clk, input wire VAR5, input wire [7:0] VAR12, output wire [7:0] VAR10 );
parameter VAR3 = 32'd23529;
parameter VAR1 = 32'd200000;
parameter VAR11 = 8'd80;
reg [31:0] counter;
wire [7:0] VAR8;
reg [7:0] buffer[0:3];
reg [1:0] VAR9;
reg [9:0] VAR7;
reg VAR6;
assign VAR10 = VAR7[9:2];
VAR2 VAR4 ... | mit |
MarcoVogt/basil | firmware/modules/gpio/gpio.v | 2,990 | module MODULE1
parameter VAR21 = 0,
parameter VAR24 = 0,
parameter VAR29 = 16,
parameter VAR9 = 8,
parameter VAR6 = 0,
parameter VAR7 = 0
)(
VAR30,
VAR27,
VAR10,
VAR26,
VAR23,
VAR1,
VAR13
);
localparam VAR3 = 0;
input wire VAR30;
input wire VAR27;
input wire [VAR29-1:0] VAR10;
inout wire [7:0] VAR26;
input wire VAR23;
... | bsd-3-clause |
csturton/wirepatch | system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/xsv_fpga_top.v | 20,913 | module MODULE1 (
VAR276, VAR128
);
input VAR128;
output VAR276;
wire clk;
wire VAR262;
wire [31:0] VAR374;
wire [31:0] VAR286;
wire [31:0] VAR345;
wire [3:0] VAR335;
wire VAR314;
wire VAR55;
wire VAR51;
wire VAR187;
wire VAR393;
wire [3:0] VAR199;
wire [1:0] VAR203;
wire [10:0] VAR309;
wire VAR98;
wire [31:0] VAR338;
w... | mit |
jairov4/accel-oil | solution_spartan6/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/verilog/sample_iterator_get_offset.v | 36,471 | module MODULE1 (
VAR122,
VAR86,
VAR70,
VAR110,
VAR33,
VAR38,
VAR77,
VAR75,
VAR116,
VAR67,
VAR120,
VAR91,
VAR95,
VAR69,
VAR27,
VAR118,
VAR108,
VAR40,
VAR13,
VAR87,
VAR117,
VAR84,
VAR94,
VAR1,
VAR3,
VAR71,
VAR104,
VAR97,
VAR80,
VAR9,
VAR92,
VAR12,
VAR41,
VAR109,
VAR82,
VAR102,
VAR114,
VAR119,
VAR14
);
input VAR122;
input... | lgpl-3.0 |
kkthx/mycpu | cpu_last.v | 2,525 | module MODULE1(clk, rst, VAR6, VAR15, VAR5, VAR12, VAR4, VAR11);
input clk;
input rst;
output [7:0] VAR6;
output [7:0] VAR15;
output [9:0] VAR5;
output [13:0] VAR12;
output VAR4;
output VAR11;
reg [7:0] VAR7;
reg [7:0] VAR1;
reg [9:0] VAR8;
reg [13:0] VAR17;
reg VAR13;
reg VAR2;
reg [7:0] VAR10[0:15];
reg [13:0] VAR9[0... | mit |
walkthetalk/fsref | ip/axis_scaler/src/include/scaler_relay.v | 1,792 | module MODULE1 # (
parameter integer VAR6 = 12,
parameter integer VAR3 = 0
) (
input wire clk,
input wire VAR9,
input wire VAR12,
input wire [VAR6-1:0] VAR14 ,
output wire VAR8,
output wire VAR7,
output wire [VAR6-1:0] VAR5 ,
input wire VAR10
);
generate
if (VAR3) begin
assign VAR7 = VAR12;
assign VAR5 = VAR14;
assign ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4/sky130_fd_sc_hs__and4.behavioral.v | 1,729 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR10 ,
VAR13 ,
VAR2 ,
VAR7,
VAR12
);
output VAR4 ;
input VAR3 ;
input VAR10 ;
input VAR13 ;
input VAR2 ;
input VAR7;
input VAR12;
wire VAR9 ;
wire VAR6;
and VAR5 (VAR9 , VAR3, VAR10, VAR13, VAR2 );
VAR11 VAR1 (VAR6, VAR9, VAR7, VAR12);
buf VAR8 (VAR4 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_1.v | 2,271 | module MODULE2 (
VAR9 ,
VAR3,
VAR4,
VAR2 ,
VAR8 ,
VAR5,
VAR1
);
output VAR9 ;
input VAR3;
input VAR4;
input VAR2 ;
input VAR8 ;
input VAR5;
input VAR1;
VAR7 VAR6 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR9 ,
VAR3,
VAR4,
VAR2 ,
VAR8
);
ou... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Otros/Prueba4.1/fifo.v | 3,734 | module MODULE1 # (parameter VAR23 = 20, VAR21 = 8)(
input reset, VAR25,
input rd, wr,
input [VAR21-1:0] din,
output [VAR21-1:0] dout,
output VAR16,
output VAR3,
output reg VAR7
);
wire VAR17;
wire VAR20;
reg VAR9, VAR10;
reg [VAR21-1:0] out;
VAR4 VAR7 = 0;
reg [1:0] VAR18;
reg [1:0] VAR12;
assign VAR17 = VAR9;
assign V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/diode/sky130_fd_sc_hdll__diode_6.v | 1,994 | module MODULE2 (
VAR7,
VAR2 ,
VAR3 ,
VAR5 ,
VAR6
);
input VAR7;
input VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR6 ;
VAR1 VAR4 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7
);
input VAR7;
supply1 VAR2;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR6 ;
VAR1 VAR4 (
.VAR7(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufbuf/sky130_fd_sc_ms__bufbuf.symbol.v | 1,258 | module MODULE1 (
input VAR3,
output VAR4
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
ThomasLee969/verilog-homework | exp3/freq_meter/freq_meter.v | 1,381 | module MODULE1
(
VAR15, VAR3, VAR14,
VAR10,
VAR12, clk
);
output [3:0] VAR15;
output [7:0] VAR3;
output VAR14;
input VAR10, VAR12, clk;
assign VAR14 = VAR12;
wire VAR20;
VAR16 VAR5(VAR20, VAR12, VAR10);
wire VAR7, VAR22;
VAR18 #(100000000) VAR17(VAR7, clk);
VAR18 #(100000) VAR11(VAR22, clk);
wire [15:0] VAR19;
wire VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_1.behavioral.v | 1,495 | module MODULE1( VAR1, VAR3, VAR5, VAR4 );
input VAR5, VAR1, VAR4;
output VAR3;
VAR7 VAR2(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4));
VAR7 VAR6(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s.blackbox.v | 1,324 | module MODULE1 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
supply1 VAR1;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
emeb/iceRadio | FPGA/rxadc_2/verilog/src/tuner_slice.v | 2,009 | module MODULE1 #(
parameter VAR4 = 10,
VAR1 = 10
)
(
input clk, reset, VAR2,
input signed [VAR4-1:0] in,
input [VAR1-1:0] VAR9,
output reg signed [VAR4-1:0] out
);
wire [1:0] VAR5 = VAR9[VAR1-1:VAR1-2] + {1'b0,VAR2};
reg [1:0] VAR7;
reg [VAR1-3:0] addr;
reg VAR8;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
VAR7... | mit |
benjaminfjones/fpga-tunes | src/mojo_top.v | 3,745 | module MODULE1(
input clk,
input VAR8,
input VAR37,
output [7:0] VAR14,
output VAR24,
input VAR48,
input VAR20,
input VAR21,
output [3:0] VAR23,
input VAR9, output VAR22, input VAR11, output [7:0] VAR41, input [4:0] VAR4 );
wire rst = ~VAR8;
wire [3:0] VAR19;
assign VAR24 = 1'VAR16;
assign VAR22 = 1'VAR16;
assign VAR23... | gpl-3.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/ip/opencores_i2c/opencores_i2c.v | 2,023 | module MODULE1
(
VAR15, VAR23, VAR21, VAR4, VAR1,
VAR18, VAR22, VAR17, VAR6, VAR9,
VAR14, VAR8
);
input VAR15; input VAR23;
input [2:0] VAR21; input [7:0] VAR4; output [7:0] VAR1; input VAR18;
input VAR22;
input VAR17; output VAR6; output VAR9;
inout VAR14; inout VAR8;
wire VAR18;
wire VAR22;
wire VAR10;
wire VAR13;
as... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/fill/sky130_fd_sc_hvl__fill.functional.v | 1,114 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor2/sky130_fd_sc_ms__xnor2.symbol.v | 1,301 | module MODULE1 (
input VAR6,
input VAR7,
output VAR3
);
supply1 VAR5;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrckapwr/sky130_fd_sc_hd__lpflow_isobufsrckapwr.pp.blackbox.v | 1,507 | module MODULE1 (
VAR5 ,
VAR2,
VAR3 ,
VAR6,
VAR7 ,
VAR8 ,
VAR1 ,
VAR4
);
output VAR5 ;
input VAR2;
input VAR3 ;
input VAR6;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
thurday/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_TrainingPattern.v | 1,785 | module MODULE1(
VAR3,
VAR2,
VAR1);
input VAR3, VAR2;
output reg [7:0] VAR1;
always @ (posedge VAR3)
begin
if(VAR2)
begin
VAR1 <= 0;
end
else
begin
if(VAR1 == 8'hf4)
VAR1 <= 8'hc2;
end
else
VAR1 <= 8'hf4;
end
end
endmodule | bsd-2-clause |
ZiCog/xoro | rtl/hello.v | 1,479 | module MODULE1 (
input VAR3, input clk,
output VAR4 );
reg wr;
wire [7:0] VAR6;
reg [3:0] state;
wire VAR9;
reg [3:0] VAR11;
VAR7 VAR10 (
.addr(VAR11),
.clk(clk),
.VAR2(VAR6)
);
VAR5 VAR1 (
.VAR3(VAR3), .clk(clk), .wr(wr), .VAR8(VAR6), .VAR4(VAR4), .VAR9(VAR9) );
always @(posedge clk or negedge VAR3)
begin
if (!VAR3) b... | mit |
jcrono/sd-host | src/buffer/fifo.v | 14,601 | module MODULE1 (
VAR4, VAR58, VAR13, VAR7, VAR56, VAR17, VAR43, VAR57, reset, VAR22, VAR37, VAR14, VAR50, VAR54, VAR36, VAR35, VAR42 );
input [1:0] VAR17;
input [VAR48:0] VAR7;
input [VAR60:0] VAR4;
input [2:0] VAR58;
input [2:0] VAR36;
input VAR13,
VAR22,
reset,
VAR56,
VAR50,
VAR35;
output [VAR48:0] VAR37;
output [1:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p.functional.v | 1,701 | module MODULE1 (
VAR2 ,
VAR1,
VAR5
);
output VAR2 ;
input VAR1;
input VAR5 ;
wire VAR3 ;
wire VAR4;
wire VAR7 ;
wire VAR8 ;
not VAR10 (VAR3 , VAR1 );
and VAR11 (VAR4, VAR3, VAR5 );
VAR9 VAR6 (VAR2 , VAR4, VAR7, VAR8);
endmodule | apache-2.0 |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T21-baud-tx/divider.v | 1,116 | module MODULE1(input wire VAR6, output wire VAR2);
parameter VAR4 = 104;
localparam VAR3 = VAR5(VAR4);
reg [VAR3-1:0] VAR1 = 0;
always @(posedge VAR6)
VAR1 <= (VAR1 == VAR4 - 1) ? 0 : VAR1 + 1;
assign VAR2 = VAR1[VAR3-1];
endmodule | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_auto_pc_0/ip_design_auto_pc_0_stub.v | 4,409 | module MODULE1(VAR24, VAR25, VAR13, VAR27,
VAR45, VAR57, VAR8, VAR2, VAR29, VAR33,
VAR41, VAR19, VAR42, VAR52, VAR39, VAR51, VAR17,
VAR10, VAR50, VAR38, VAR20, VAR26, VAR43, VAR31,
VAR37, VAR59, VAR21, VAR44, VAR46, VAR55,
VAR54, VAR6, VAR18, VAR12, VAR16, VAR32, VAR11,
VAR36, VAR28, VAR48, VAR22, VAR5, VAR40,
VAR1, VA... | mit |
oblivioncth/DE0-Verilog-Processor | src/ALU_Cell_4bit.v | 2,084 | module MODULE1(
VAR11,
VAR9,
VAR14,
VAR16,
VAR3,
VAR6,
VAR2
);
input wire VAR11;
input wire VAR9;
input wire [3:0] VAR14;
input wire [3:0] VAR16;
input wire [4:0] VAR3;
output wire VAR6;
output wire [3:0] VAR2;
wire [3:0] VAR10;
wire VAR8;
wire VAR1;
wire VAR7;
VAR5 VAR12(
.VAR14(VAR14[3]),
.VAR16(VAR16[3]),
.VAR9(VAR8... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/yf32/yf32_core.v | 3,556 | module MODULE1 (VAR11, VAR15, VAR18, VAR9, VAR10, VAR13, VAR16,
VAR12, VAR4, VAR2, VAR17);
input VAR11;
input VAR15;
input [31:0] VAR9;
input VAR4;
input VAR17;
output [31:0] VAR18;
output [31:0] VAR10;
output VAR13;
output [ 3:0] VAR16;
output VAR12;
output VAR2;
wire VAR12 = ~VAR15;
wire VAR2 = ~VAR15;
VAR14 VAR8(
.c... | mit |
thurday/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RXMSG_ACK_Decoder.v | 7,047 | module MODULE1(
input clk,
input enable, input [7:0] VAR2,
output reg VAR16,
output reg VAR15
);
reg [7:0] VAR17; reg [7:0] VAR13; reg [7:0] VAR5; reg [2:0] VAR8; reg VAR1; reg [7:0] VAR11; reg [2:0] VAR6;
reg [7:0] VAR12; reg VAR3;
reg [7:0] VAR7;
reg [7:0] VAR9; reg VAR10;
reg VAR14;
reg [39:0] VAR4;
always @(negedge... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221a/sky130_fd_sc_hdll__o221a.pp.blackbox.v | 1,436 | module MODULE1 (
VAR10 ,
VAR3 ,
VAR7 ,
VAR5 ,
VAR8 ,
VAR9 ,
VAR4,
VAR6,
VAR2 ,
VAR1
);
output VAR10 ;
input VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR8 ;
input VAR9 ;
input VAR4;
input VAR6;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtp/sky130_fd_sc_hs__sdfrtp.functional.pp.v | 2,063 | module MODULE1 (
VAR18 ,
VAR10 ,
VAR15 ,
VAR2 ,
VAR11 ,
VAR14 ,
VAR13 ,
VAR1
);
input VAR18 ;
input VAR10 ;
output VAR15 ;
input VAR2 ;
input VAR11 ;
input VAR14 ;
input VAR13 ;
input VAR1;
wire VAR16 ;
wire VAR17 ;
wire VAR8;
not VAR5 (VAR17 , VAR1 );
VAR4 VAR3 (VAR8, VAR11, VAR14, VAR13 );
VAR6 VAR7 VAR12 (VAR16 , VA... | apache-2.0 |
chiralhat/fpga-pulses-ice | HX8K/pulse_gen.v | 2,764 | module MODULE1(
input clk, input VAR3, output VAR29, output VAR23, output VAR12, output VAR8
);
wire [23:0] period;
wire [15:0] VAR2;
wire [15:0] delay;
wire [15:0] VAR1;
wire VAR33;
wire [7:0] VAR4;
wire VAR20;
wire VAR27;
wire VAR32;
wire VAR24;
wire VAR15;
VAR19 VAR14(
.VAR5(clk),
.VAR17(VAR32),
.VAR28(VAR15)
);
VAR... | bsd-3-clause |
devinacker/sd2snes | verilog/sd2snes_cx4/address.v | 2,697 | module MODULE1(
input VAR22,
input [7:0] VAR20,
input [2:0] VAR4, input [23:0] VAR2, input [7:0] VAR23, output [23:0] VAR26, output VAR21, output VAR9, output VAR17, output VAR18, input [23:0] VAR16,
input [23:0] VAR8,
output VAR13,
output VAR7,
output VAR5,
output VAR14,
output VAR15,
output VAR10,
output VAR11,
outpu... | gpl-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/fallthrough_small_fifo_v2.v | 5,329 | module MODULE2
parameter VAR13 = 3,
parameter VAR3 = 2**VAR13 - 1)
(
input [VAR6-1:0] din, input VAR9,
input VAR10,
output [VAR6-1:0] dout, output VAR11,
output VAR15,
output VAR1,
output reg VAR7,
input reset,
input clk
);
reg VAR14, VAR5;
VAR12
.VAR13 (VAR13),
.VAR3 (VAR3))
VAR4
(.din (din),
.VAR9 (VAR9),
.VAR10 (VAR... | apache-2.0 |
Huyuwei/tvm | vta/hardware/chisel/src/main/resources/verilog/VTAMemDPI.v | 3,104 | module MODULE1 #
( parameter VAR5 = 8,
parameter VAR16 = 64,
parameter VAR29 = 64
)
(
input VAR18,
input reset,
input VAR28,
input VAR19,
input [VAR5-1:0] VAR17,
input [VAR16-1:0] VAR21,
input VAR12,
input [VAR29-1:0] VAR23,
output logic VAR27,
output logic [VAR29-1:0] VAR10,
input VAR25
);
import "VAR22-VAR15" functio... | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_FIFO_SUM_SQ_DATA.v | 2,336 | module MODULE1 (
address,
VAR5,
clk,
VAR4,
VAR3,
VAR2,
VAR1,
VAR7
)
;
output [ 25: 0] VAR1;
output [ 31: 0] VAR7;
input [ 1: 0] address;
input VAR5;
input clk;
input VAR4;
input VAR3;
input [ 31: 0] VAR2;
wire VAR9;
reg [ 25: 0] VAR8;
wire [ 25: 0] VAR1;
wire [ 25: 0] VAR6;
wire [ 31: 0] VAR7;
assign VAR9 = 1;
assign V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfstp/sky130_fd_sc_hdll__sdfstp.pp.symbol.v | 1,505 | module MODULE1 (
input VAR7 ,
output VAR9 ,
input VAR1,
input VAR5 ,
input VAR8 ,
input VAR10 ,
input VAR2 ,
input VAR4 ,
input VAR6 ,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2/sky130_fd_sc_hd__mux2.functional.pp.v | 1,902 | module MODULE1 (
VAR13 ,
VAR11 ,
VAR6 ,
VAR14 ,
VAR8,
VAR15,
VAR5 ,
VAR10
);
output VAR13 ;
input VAR11 ;
input VAR6 ;
input VAR14 ;
input VAR8;
input VAR15;
input VAR5 ;
input VAR10 ;
wire VAR2 ;
wire VAR7;
VAR9 VAR3 (VAR2 , VAR11, VAR6, VAR14 );
VAR12 VAR4 (VAR7, VAR2, VAR8, VAR15);
buf VAR1 (VAR13 , VAR7 );
endmodul... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3b/sky130_fd_sc_hdll__or3b.symbol.v | 1,309 | module MODULE1 (
input VAR8 ,
input VAR7 ,
input VAR5,
output VAR6
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/verilog/sha.v | 38,061 | module MODULE1 (VAR17, VAR49, VAR38, VAR26, VAR10, VAR53, VAR57);
input VAR17; input VAR49;
input [31:0] VAR38; output [31:0] VAR26;
input [2:0] VAR10; input VAR53; output [3:0] VAR57;
reg [3:0] VAR32;
wire [3:0] VAR57;
reg [31:0] VAR26;
reg [6:0] VAR41;
wire [6:0] VAR51;
reg [2:0] VAR31;
reg [31:0] VAR39,VAR15,VAR9,VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fahcin/sky130_fd_sc_hd__fahcin.behavioral.v | 1,848 | module MODULE1 (
VAR1,
VAR13 ,
VAR2 ,
VAR19 ,
VAR4
);
output VAR1;
output VAR13 ;
input VAR2 ;
input VAR19 ;
input VAR4 ;
supply1 VAR22;
supply0 VAR6;
supply1 VAR20 ;
supply0 VAR7 ;
wire VAR23 ;
wire VAR11;
wire VAR16 ;
wire VAR3 ;
wire VAR21 ;
wire VAR10;
not VAR15 (VAR23 , VAR4 );
xor VAR9 (VAR11, VAR2, VAR19, VAR23 ... | apache-2.0 |
545/Atari7800 | new_atari/project_1/project_1.srcs/sources_1/imports/sources_1/new/cpu.v | 33,098 | module MODULE1( clk, reset, VAR35, VAR47, VAR53, VAR79, VAR12, VAR55, VAR51 );
input clk; input reset; output reg [15:0] VAR35; input [7:0] VAR47; output [7:0] VAR53; output VAR79; input VAR12; input VAR55; input VAR51;
reg [15:0] VAR141; reg [7:0] VAR11; reg [7:0] VAR158; wire [7:0] VAR205;
reg [7:0] VAR208; reg VAR96... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.v | 2,068 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR5,
VAR2,
VAR6 ,
VAR1
);
output VAR7 ;
input VAR3 ;
input VAR5;
input VAR2;
input VAR6 ;
input VAR1 ;
VAR4 VAR8 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR7,
VAR3
);
output VAR7;
input VAR3;
supply1 VAR5;
supply0 VAR2;... | apache-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_frame_length_adjust.v | 25,091 | module MODULE1 #
(
parameter VAR12 = 8,
parameter VAR1 = (VAR12>8),
parameter VAR21 = (VAR12/8),
parameter VAR33 = 0,
parameter VAR34 = 8,
parameter VAR5 = 0,
parameter VAR18 = 8,
parameter VAR19 = 1,
parameter VAR13 = 1
)
(
input wire clk,
input wire rst,
input wire [VAR12-1:0] VAR6,
input wire [VAR21-1:0] VAR3,
input... | mit |
alexforencich/verilog-dsp | rtl/dsp_mult.v | 3,025 | module MODULE1 #
(
parameter VAR15 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR15-1:0] VAR12,
input wire VAR1,
output wire VAR9,
input wire [VAR15-1:0] VAR13,
input wire VAR2,
output wire VAR10,
output wire [(VAR15*2)-1:0] VAR8,
output wire VAR4,
input wire VAR16
);
reg [VAR15-1:0] VAR5 = 0;
reg [VAR15-1:0]... | mit |
alexforencich/verilog-ethernet | rtl/ssio_ddr_out.v | 2,279 | module MODULE1 #
(
parameter VAR13 = "VAR7",
parameter VAR4 = "VAR5",
parameter VAR8 = "VAR11",
parameter VAR3 = 1
)
(
input wire clk,
input wire VAR1,
input wire [VAR3-1:0] VAR14,
input wire [VAR3-1:0] VAR12,
output wire VAR15,
output wire [VAR3-1:0] VAR18
);
wire VAR16 = VAR8 == "VAR11" ? VAR1 : clk;
VAR19 #(
.VAR13(... | mit |
ncos/Xilinx-Verilog | GYRACC/src/ACC/slaveselect.v | 2,281 | module MODULE1(
rst,
clk,
VAR2,
VAR4,
VAR1
);
input rst;
input clk;
input VAR2;
input VAR4;
output VAR1;
reg VAR1 = 1'b1;
always @(posedge clk)
begin: VAR3
begin
if (rst == 1'b1)
VAR1 <= 1'b1;
end
else if (VAR2 == 1'b1)
VAR1 <= 1'b0;
end
else if (VAR4 == 1'b1)
VAR1 <= 1'b1;
end
end
endmodule | mit |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/syn/verilog/ANN_ddiv_64ns_64ns_64_31.v | 1,903 | module MODULE1
VAR24 = 8,
VAR4 = 31,
VAR2 = 64,
VAR14 = 64,
VAR20 = 64
)(
input wire clk,
input wire reset,
input wire VAR6,
input wire [VAR2-1:0] VAR1,
input wire [VAR14-1:0] VAR17,
output wire [VAR20-1:0] dout
);
wire VAR19;
wire VAR3;
wire VAR22;
wire [63:0] VAR15;
wire VAR27;
wire [63:0] VAR23;
wire VAR8;
wire [63:... | gpl-3.0 |
sabertazimi/hust-lab | digitalLogic/design/washmach_design/src/ring.v | 3,495 | module MODULE1
(
input [(VAR11-1):0] VAR3,
input VAR5,
input VAR4,
input VAR6,
input [2:0] VAR7,
output reg VAR8
);
reg [(VAR11-1):0] VAR10;
reg [1:0] state, VAR12;
parameter VAR9 = 0, VAR1 = 1, VAR2 = 2; | mit |
MarcoVogt/basil | firmware/modules/m26_rx/m26_rx_ch.v | 1,155 | module MODULE1
(
input wire VAR9,
input wire VAR5,
input wire VAR6,
input wire VAR11,
output wire VAR1, VAR4,
output wire [15:0] VAR8
);
reg [15:0] VAR3;
always@(posedge VAR5)
VAR3[15:0] <= {VAR3[14:0], VAR6};
reg [15:0] VAR2;
always@(posedge VAR5)
VAR2[15:0] <= {VAR11, VAR2[15:1]};
assign VAR4 = (VAR3[15:12] == 4'b111... | bsd-3-clause |
sehugg/8bitworkshop | presets/verilog/tank.v | 5,618 | module MODULE1(VAR5, VAR7, VAR3);
input [8:0] VAR5;
input [8:0] VAR7;
output VAR3;
reg [3:0] VAR1 [0:15];
reg [15:0] VAR2;
wire VAR4 = ~(VAR5[0] ^ VAR5[1]) ^ (VAR7[0] ^ VAR7[1])
&& VAR5[2] && VAR7[2];
wire MODULE1 = (VAR5 >= 64 && VAR5 < 160)
&& (VAR7 >= 48 && VAR7 < 176)
&& VAR4;
wire [3:0] VAR8 = VAR7[6:3]^8;
wire VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21bai/sky130_fd_sc_ms__o21bai.pp.symbol.v | 1,391 | module MODULE1 (
input VAR8 ,
input VAR2 ,
input VAR3,
output VAR7 ,
input VAR5 ,
input VAR4,
input VAR1,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrbp/sky130_fd_sc_hd__sdfrbp.pp.blackbox.v | 1,515 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR11 ,
VAR4 ,
VAR10 ,
VAR2 ,
VAR3,
VAR9 ,
VAR8 ,
VAR6 ,
VAR7
);
output VAR1 ;
output VAR5 ;
input VAR11 ;
input VAR4 ;
input VAR10 ;
input VAR2 ;
input VAR3;
input VAR9 ;
input VAR8 ;
input VAR6 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2b/sky130_fd_sc_ms__nor2b.functional.pp.v | 1,969 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR13 ,
VAR9,
VAR12,
VAR5 ,
VAR2
);
output VAR7 ;
input VAR11 ;
input VAR13 ;
input VAR9;
input VAR12;
input VAR5 ;
input VAR2 ;
wire VAR3 ;
wire VAR4 ;
wire VAR6;
not VAR15 (VAR3 , VAR11 );
and VAR8 (VAR4 , VAR3, VAR13 );
VAR10 VAR1 (VAR6, VAR4, VAR9, VAR12);
buf VAR14 (VAR7 , VAR6 );
e... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ebufn/sky130_fd_sc_ls__ebufn.behavioral.pp.v | 1,870 | module MODULE1 (
VAR11 ,
VAR8 ,
VAR7,
VAR6,
VAR10,
VAR13 ,
VAR2
);
output VAR11 ;
input VAR8 ;
input VAR7;
input VAR6;
input VAR10;
input VAR13 ;
input VAR2 ;
wire VAR3 ;
wire VAR1;
VAR5 VAR12 (VAR3 , VAR8, VAR6, VAR10 );
VAR5 VAR9 (VAR1, VAR7, VAR6, VAR10 );
bufif0 VAR4 (VAR11 , VAR3, VAR1);
endmodule | apache-2.0 |
GSejas/Karatsuba_FPU | my_sourcefiles/cordic_jeffrey/Mux_Array.v | 1,774 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR16,
input wire [VAR18-1:0] VAR1,
input wire VAR14,
input wire [VAR17-1:0] VAR15,
input wire VAR9,
output wire [VAR18-1:0] VAR21
);
wire [VAR18-1:0] VAR22[VAR17+1:0];
genvar VAR13;VAR5 #(.VAR18(VAR18)) VAR6(
.VAR1(VAR1),
.VAR4(VAR14),
.VAR21(VAR22 [0][VAR18-... | gpl-3.0 |
freecores/sha3 | low_throughput_core/rtl/keccak.v | 3,126 | module MODULE1(clk, reset, in, VAR21, VAR8, VAR22, VAR12, out, VAR11);
input clk, reset;
input [31:0] in;
input VAR21, VAR8;
input [1:0] VAR22;
output VAR12;
output [511:0] out;
output reg VAR11;
reg state;
wire [575:0] VAR9,
VAR15;
wire VAR5;
wire VAR23;
wire [1599:0] VAR16;
wire VAR4;
wire [511:0] VAR2;
reg [22:0] VA... | apache-2.0 |
Elphel/x393_sata | ahci/ahci_dma_wr_fifo.v | 24,872 | module MODULE1#(
parameter VAR24 = 21,
parameter VAR58 = 3
)(
input VAR42,
input VAR55,
input VAR30,
input VAR3,
input [VAR24-1:0] VAR23, input [1:0] VAR26, input VAR36, input VAR56, output reg [63:0] dout, input VAR63, input VAR20, output VAR17,
output reg [3:0] VAR29, output reg VAR28, output VAR71,
output reg VAR8, ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s.behavioral.pp.v | 1,865 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR11,
VAR2,
VAR7 ,
VAR10
);
output VAR6 ;
input VAR3 ;
input VAR11;
input VAR2;
input VAR7 ;
input VAR10 ;
wire VAR9 ;
wire VAR1;
buf VAR4 (VAR9 , VAR3 );
VAR8 VAR5 (VAR1, VAR9, VAR11, VAR2);
buf VAR12 (VAR6 , VAR1 );
endmodule | apache-2.0 |
cliffordwolf/yosys | techlibs/gatemate/lut_map.v | 1,558 | module MODULE1 (VAR13, VAR16);
parameter VAR2 = 0;
parameter VAR10 = 0;
input [VAR2-1:0] VAR13;
output VAR16;
generate
if (VAR2 == 1) begin
VAR8 #(.VAR12(VAR10)) VAR5 (.VAR15(VAR16), .VAR1(VAR13[0]));
end
else if (VAR2 == 2) begin
VAR14 #(.VAR12(VAR10)) VAR5 (.VAR15(VAR16), .VAR1(VAR13[0]), .VAR4(VAR13[1]));
end
else i... | isc |
whitequark/bfcpu2 | verilog/StageWriteback.v | 1,395 | module MODULE1 (
clk,
reset,
VAR4,
VAR10,
VAR7,
VAR20,
VAR2,
VAR11,
VAR3,
VAR12,
VAR18,
VAR1,
VAR14,
ack
);
parameter VAR9 = 12;
parameter VAR6 = 8;
input clk;
input reset;
input [VAR9 - 1:0] VAR4;
output VAR10;
output [VAR9 - 1:0] VAR7;
output [VAR6 - 1:0] VAR20;
output [7:0] VAR2;
output VAR11;
input VAR3;
input [VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2a/sky130_fd_sc_hd__o2bb2a.functional.pp.v | 2,171 | module MODULE1 (
VAR12 ,
VAR1,
VAR16,
VAR18 ,
VAR6 ,
VAR8,
VAR7,
VAR14 ,
VAR5
);
output VAR12 ;
input VAR1;
input VAR16;
input VAR18 ;
input VAR6 ;
input VAR8;
input VAR7;
input VAR14 ;
input VAR5 ;
wire VAR17 ;
wire VAR2 ;
wire VAR15 ;
wire VAR3;
nand VAR13 (VAR17 , VAR16, VAR1 );
or VAR9 (VAR2 , VAR6, VAR18 );
and VA... | apache-2.0 |
OrganicMonkeyMotion/fpga_experiments | bmax10/BeMicro_full_reference_project/ip/i2c_opencores/i2c_master_top.v | 9,912 | module MODULE1(
VAR44, VAR48, VAR38, VAR31, VAR6, VAR54,
VAR22, VAR42, VAR29, VAR15, VAR8,
VAR46, VAR52, VAR21, VAR19, VAR33, VAR10 );
parameter VAR37 = 1'b0;
input VAR44; input VAR48; input VAR38; input [2:0] VAR31; input [7:0] VAR6; output [7:0] VAR54; input VAR22; input VAR42; input VAR29; output VAR15; output VAR8;... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbp/sky130_fd_sc_ls__dfbbp.behavioral.pp.v | 2,712 | module MODULE1 (
VAR19 ,
VAR18 ,
VAR20 ,
VAR12 ,
VAR15 ,
VAR17,
VAR10 ,
VAR24 ,
VAR13 ,
VAR9
);
output VAR19 ;
output VAR18 ;
input VAR20 ;
input VAR12 ;
input VAR15 ;
input VAR17;
input VAR10 ;
input VAR24 ;
input VAR13 ;
input VAR9 ;
wire VAR5 ;
wire VAR26 ;
wire VAR16 ;
wire VAR22 ;
wire VAR23;
wire VAR6 ;
reg VAR7 ... | apache-2.0 |
atti92/heterogenhomework | project1/solution1/syn/verilog/fir_hw_smpl_V.v | 1,418 | module MODULE1 (VAR1, VAR2, VAR9, VAR5, VAR6, clk);
parameter VAR7 = 18;
parameter VAR4 = 7;
parameter VAR3 = 128;
input[VAR4-1:0] VAR1;
input VAR2;
input[VAR7-1:0] VAR9;
input VAR5;
output reg[VAR7-1:0] VAR6;
input clk;
reg [VAR7-1:0] VAR8[VAR3-1:0];
begin
begin
begin
end | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_hip_s4gx_gen2_x4_128/pci_express_compiler-library/altpcie_serdes_1sgx_x1_12500.v | 19,463 | module MODULE1 (
VAR58,
VAR103,
VAR90,
VAR59,
VAR52,
VAR106,
VAR60,
VAR84,
VAR32,
VAR92,
VAR4,
VAR48,
VAR114,
VAR69,
VAR98,
VAR26,
VAR110,
VAR12,
VAR8,
VAR81);
input [0:0] VAR58;
input [0:0] VAR103;
input [0:0] VAR90;
input [0:0] VAR59;
input [0:0] VAR52;
input [0:0] VAR106;
input [0:0] VAR60;
input [0:0] VAR84;
input ... | lgpl-3.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/NIOS_Sys/synthesis/submodules/NIOS_Sys_PIO0.v | 5,529 | module MODULE1 (
address,
VAR4,
clk,
VAR10,
VAR12,
VAR11,
VAR17,
irq,
VAR13
)
;
inout [ 4: 0] VAR17;
output irq;
output [ 31: 0] VAR13;
input [ 1: 0] address;
input VAR4;
input clk;
input VAR10;
input VAR12;
input [ 31: 0] VAR11;
wire [ 4: 0] VAR17;
wire VAR5;
reg [ 4: 0] VAR15;
reg [ 4: 0] VAR16;
reg [ 4: 0] VAR8;
wir... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn_lp.v | 2,156 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR3,
VAR9,
VAR7,
VAR6 ,
VAR2
);
output VAR8 ;
input VAR4 ;
input VAR3;
input VAR9;
input VAR7;
input VAR6 ;
input VAR2 ;
VAR5 VAR1 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR8 ,
VAR4 ,
VAR3
);
output VAR8 ;... | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/lpddr2_cntrlr_p0_generic_ddio.v | 2,318 | module MODULE1(
VAR20,
VAR10,
VAR22,
VAR2,
VAR15
);
parameter VAR24 = 1;
localparam VAR11 = 4 * VAR24;
localparam VAR26 = VAR24;
input [VAR11-1:0] VAR20;
input VAR10;
input [VAR24-1:0] VAR2;
input [VAR24-1:0] VAR15;
output [VAR26-1:0] VAR22;
generate
genvar VAR14;
for (VAR14 = 0; VAR14 < VAR24; VAR14 = VAR14 + 1)
begin... | gpl-3.0 |
ZenoFuturista/fpga-shovel-and-pickaxe | verilog/sha_miner/sha.v | 19,871 | module MODULE3(input clk, input [7:0] in[0:79], input [31:0] VAR77, input VAR13, output reg[7:0] VAR84[0:31], output reg[31:0] VAR74, output reg[31:0] VAR48, output reg VAR68);
parameter VAR1 = 4;
wire [31:0] VAR9 [0:7];
assign VAR9 = '{32'h6a09e667, 32'hbb67ae85, 32'h3c6ef372, 32'ha54ff53a, 32'h510e527f, 32'h9b05688c,... | apache-2.0 |
dekuNukem/FAP_Z80 | FAP_modules/video_card/FPGA_code/src/temp.v | 5,026 | VAR27 "VAR10<0>" VAR28 = VAR23 | VAR25 = VAR22;
VAR27 "VAR10<1>" VAR28 = VAR32 | VAR25 = VAR22;
VAR27 "VAR12<0>" VAR28 = VAR33 | VAR25 = VAR22;
VAR27 "VAR12<1>" VAR28 = VAR2 | VAR25 = VAR22;
VAR27 "VAR31<0>" VAR28 = VAR7 | VAR25 = VAR22;
VAR27 "VAR31<1>" VAR28 = VAR13 | VAR25 = VAR22;
module MODULE2(
input wire clk,
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/buf/sky130_fd_sc_ms__buf.blackbox.v | 1,202 | module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR5;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32ai/sky130_fd_sc_ms__o32ai.blackbox.v | 1,392 | module MODULE1 (
VAR5 ,
VAR2,
VAR3,
VAR1,
VAR7,
VAR8
);
output VAR5 ;
input VAR2;
input VAR3;
input VAR1;
input VAR7;
input VAR8;
supply1 VAR6;
supply0 VAR4;
supply1 VAR10 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_pr/sky130_fd_sc_lp__udp_dff_pr.blackbox.v | 1,249 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR1 ,
VAR2
);
output VAR4 ;
input VAR3 ;
input VAR1 ;
input VAR2;
endmodule | apache-2.0 |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/WB_Serial.v | 22,242 | module MODULE1(
input VAR47, input VAR35, input [15:0] VAR48, output [15:0] VAR67, input VAR4, input VAR71, input [ 1:0] VAR44, input [ 1:0] VAR83, input VAR77, output reg VAR24, output VAR87,
output VAR82, input VAR5 );
reg [7:0] VAR94;
wire [7:0] VAR74 = VAR83[0] ? VAR48[7:0] : VAR48[15:8]; assign VAR67 = VAR83[0] ? ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4bb/sky130_fd_sc_ls__and4bb.symbol.v | 1,333 | module MODULE1 (
input VAR3,
input VAR5,
input VAR7 ,
input VAR4 ,
output VAR8
);
supply1 VAR1;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/soc_system_FPGA_SDRAM.v | 23,299 | module MODULE2 (
clk,
rd,
VAR63,
wr,
VAR32,
VAR12,
VAR38,
VAR43,
VAR57,
VAR15
)
;
output VAR12;
output VAR38;
output VAR43;
output VAR57;
output [ 43: 0] VAR15;
input clk;
input rd;
input VAR63;
input wr;
input [ 43: 0] VAR32;
wire VAR12;
wire VAR38;
wire VAR43;
reg [ 1: 0] VAR26;
reg [ 43: 0] VAR13;
reg [ 43: 0] VAR41... | gpl-2.0 |
MarcoVogt/basil | firmware/modules/utils/cdc_syncfifo.v | 5,329 | module MODULE1 #(
parameter VAR9 = 34,
parameter VAR14 = 2
) (
output wire [VAR9-1:0] VAR2,
output wire VAR16,
output wire VAR31,
input wire [VAR9-1:0] VAR27,
input wire VAR26, VAR36, VAR10,
input wire VAR15, VAR28, VAR30
);
wire [VAR14-1:0] VAR6, VAR23;
wire [VAR14:0] VAR17, VAR34, VAR38, VAR1;
MODULE2 #(.VAR20(VAR14)... | bsd-3-clause |
Canaan-Creative/MM | verilog/superkdf9/components/alink/alink.v | 10,250 | module MODULE1(
input VAR60 ,
input VAR31 ,
input VAR5 , input VAR69 ,
input VAR26 ,
input VAR73, input [2:0] VAR30 , input [1:0] VAR59 , input [5:0] VAR70 ,
input [31:0] VAR52 ,
input [3:0] VAR66 ,
output VAR54 ,
output VAR67 , output VAR50 , output [31:0] VAR56 ,
output [VAR6-1:0] VAR44 ,
output [VAR6-1:0] VAR74 ,
in... | unlicense |
codustry/cuckoo | cuckooExten/t_clock.v | 1,398 | module MODULE1;
reg VAR12;
reg VAR11;
reg VAR3;
reg VAR1;
reg VAR2;
reg VAR7;
wire [3:0] VAR13;
wire [3:0] VAR6;
wire [3:0] VAR4;
wire [3:0] VAR8;
wire VAR10;
VAR5 VAR9 (
.VAR13(VAR13),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR12(VAR12),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR7(VAR7)... | mit |
Gilberto-Lopez/Arquitectura-Computadoras | Practica1/mult4.v | 2,193 | module MODULE1(
input VAR33,
input VAR67,
input VAR11,
input VAR35,
input VAR4,
input VAR12,
input VAR64,
input VAR26,
output VAR34,
output VAR17,
output VAR30,
output VAR42,
output VAR32,
output VAR29,
output VAR49,
output VAR19
);
wire VAR40;
wire VAR14;
wire VAR43;
wire VAR55;
wire VAR68;
wire VAR46;
wire VAR3;
wire... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv_1.v | 2,264 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR5 ,
VAR8 ,
VAR1,
VAR3 ,
VAR6
);
output VAR2 ;
input VAR9 ;
input VAR5 ;
input VAR8 ;
input VAR1;
input VAR3 ;
input VAR6 ;
VAR7 VAR4 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR2,
VAR9
);
output VAR2;
inpu... | apache-2.0 |
adbrant/zuma-fpga | verilog/generic/elut_custom.v | 2,015 | module MODULE1 #(
parameter VAR11 = 0,
parameter VAR22={2**VAR23{1'b0}}
) (
VAR29,
VAR15,
VAR14,
clk,
VAR10,
VAR6,
VAR13,
VAR12,
VAR9);
input [5 : 0] VAR29;
input [0 : 0] VAR15;
input [5 : 0] VAR14;
input clk;
input VAR10;
input VAR13;
input VAR12;
output VAR6;
output VAR9;
wire VAR28;
wire VAR8;
generate
if( VAR11 == ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.v | 2,329 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR8 ,
VAR4,
VAR10 ,
VAR3 ,
VAR7 ,
VAR1
);
output VAR6 ;
input VAR9 ;
input VAR8 ;
input VAR4;
input VAR10 ;
input VAR3 ;
input VAR7 ;
input VAR1 ;
VAR2 VAR5 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31oi/sky130_fd_sc_hs__a31oi.behavioral.v | 1,932 | module MODULE1 (
VAR13 ,
VAR7 ,
VAR11 ,
VAR14 ,
VAR6 ,
VAR15,
VAR4
);
output VAR13 ;
input VAR7 ;
input VAR11 ;
input VAR14 ;
input VAR6 ;
input VAR15;
input VAR4;
wire VAR6 VAR5 ;
wire VAR2 ;
wire VAR3;
and VAR12 (VAR5 , VAR14, VAR7, VAR11 );
nor VAR10 (VAR2 , VAR6, VAR5 );
VAR9 VAR8 (VAR3, VAR2, VAR15, VAR4);
buf VAR... | apache-2.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_axis_data_fifo_1_0/synth/design_SWandHW_standalone_axis_data_fifo_1_0.v | 5,893 | module MODULE1 (
VAR5,
VAR24,
VAR27,
VAR32,
VAR38,
VAR14,
VAR1,
VAR26,
VAR22,
VAR4,
VAR2,
VAR30,
VAR23,
VAR37,
VAR9
);
input wire VAR5;
input wire VAR24;
input wire VAR27;
output wire VAR32;
input wire [31 : 0] VAR38;
input wire [3 : 0] VAR14;
input wire VAR1;
output wire VAR26;
input wire VAR22;
output wire [31 : 0] V... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/capture/signal_capture.v | 11,957 | module MODULE1
parameter VAR39 = VAR45>>1, parameter VAR40 = VAR39-1,
parameter VAR20 = 1, parameter VAR37 = 1, parameter VAR42 = 1, parameter VAR14 = 0,
parameter VAR5 = 0, parameter VAR38 = 3) (
input VAR3, input VAR59,
input VAR46, input VAR12, input VAR8, output VAR51,
output [VAR36:0] VAR24,
output VAR29,
output V... | lgpl-3.0 |
Elphel/x353 | compressor/quantizator353.v | 16,984 | module MODULE1(clk, en, VAR12, VAR59, VAR2, VAR120, VAR57,
VAR36, VAR48, VAR6, VAR15, VAR86, VAR74, VAR46, VAR51, VAR37, do, VAR61, VAR50, VAR30, VAR60, VAR100, VAR66, VAR25, VAR41, VAR38, VAR96, VAR89);
input clk;
input en;
input VAR12;
input VAR59;
input VAR2;
input [ 8:0] VAR120;
input [15:0] VAR57;
input VAR36;
inp... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1.functional.v | 1,728 | module MODULE1( VAR24, VAR15, VAR12, VAR9, VAR14, VAR6, VAR16 );
input VAR9, VAR12, VAR14, VAR24, VAR15, VAR16;
output VAR6;
not VAR25( VAR7, VAR14 );
wire VAR20;
not VAR13( VAR20, VAR12 );
wire VAR3;
not VAR2( VAR3, VAR24 );
wire VAR8;
and VAR19( VAR8, VAR20, VAR3 );
wire VAR1;
not VAR26( VAR1, VAR15 );
wire VAR5;
and... | apache-2.0 |
ASP-SoC/ASP-SoC | libASP/grpPlatform/unitPlatformHps/synlayQuartus/AudioCodecSubSytem/Platform_bb.v | 4,851 | module MODULE1 (
VAR72,
VAR16,
VAR40,
VAR3,
VAR66,
VAR47,
VAR19,
VAR15,
VAR7,
VAR26,
VAR71,
VAR53,
VAR17,
VAR13,
VAR49,
VAR50,
VAR27,
VAR24,
VAR62,
VAR5,
VAR38,
VAR2,
VAR42,
VAR31,
VAR22,
VAR11,
VAR6,
VAR25,
VAR34,
VAR20,
VAR61,
VAR43,
VAR28,
VAR79,
VAR52,
VAR12,
VAR68,
VAR39,
VAR10,
VAR69,
VAR9,
VAR44,
VAR78,
VAR14,
V... | gpl-3.0 |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_nios2_qsys_0_jtag_debug_module_wrapper.v | 10,308 | module MODULE1 (
VAR43,
VAR15,
clk,
VAR41,
VAR4,
VAR47,
VAR35,
VAR7,
VAR24,
VAR54,
VAR13,
VAR6,
VAR1,
VAR46,
VAR39,
VAR10,
VAR32,
VAR19,
VAR26,
VAR8,
VAR40,
VAR50,
VAR2,
VAR56,
VAR12,
VAR29,
VAR45,
VAR11,
VAR27,
VAR18,
VAR55,
VAR25,
VAR34,
VAR38,
VAR22,
VAR9
)
;
output [ 37: 0] VAR40;
output VAR50;
output VAR2;
output ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4bb/sky130_fd_sc_ls__nor4bb.functional.v | 1,427 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR4 ,
VAR1,
VAR3
);
output VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR1;
input VAR3;
wire VAR6 ;
wire VAR10;
nor VAR5 (VAR6 , VAR8, VAR4 );
and VAR2 (VAR10, VAR6, VAR1, VAR3);
buf VAR7 (VAR9 , VAR10 );
endmodule | apache-2.0 |
secworks/fpga_eth_filter | src/rtl/fpga_eth_filter.v | 7,745 | module MODULE1(
input wire clk,
input wire VAR42,
input wire VAR30,
output wire VAR12,
output wire VAR43,
input wire [7 : 0] VAR16,
input wire VAR13,
input wire VAR11,
output wire [7 : 0] VAR34,
output wire VAR31,
output wire VAR15,
input wire [7 : 0] VAR32,
input wire VAR23,
input wire VAR8,
output wire [7 : 0] VAR2,
... | bsd-2-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Calculate_Rotor_Velocity.v | 4,268 | module MODULE1
(
VAR22,
reset,
VAR1,
valid,
VAR3,
VAR6
);
input VAR22;
input reset;
input VAR1;
input valid;
input signed [17:0] VAR3; output signed [17:0] VAR6;
reg signed [17:0] VAR26; wire signed [18:0] VAR12; wire signed [18:0] VAR23; wire signed [18:0] VAR27; wire signed [17:0] VAR31; wire [17:0] VAR30; wire signe... | gpl-3.0 |
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