repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/Tiger4NSC/src/CRC_parallel_m_lfs_XOR.v | 2,853 | module MODULE1
parameter VAR5 = 32,
parameter VAR4 = 64
)
(
VAR10 ,
VAR1 ,
VAR7
);
input [VAR5-1:0] VAR10 ;
input [VAR4-1:0] VAR1 ;
output [VAR4-1:0] VAR7 ;
wire [VAR4*(VAR5+1)-1:0] VAR3;
genvar VAR8;
generate
for (VAR8=0; VAR8<VAR5; VAR8=VAR8+1)
begin: VAR2
VAR9
.VAR4(VAR4)
)
VAR6(
.VAR10 (VAR10[VAR8]),
.VAR1 (VAR3[VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxbp/sky130_fd_sc_hs__dfxbp.pp.symbol.v | 1,303 | module MODULE1 (
input VAR2 ,
output VAR3 ,
output VAR4 ,
input VAR6 ,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
mwswartwout/EECS318 | hw2/problem3/handshake.v | 1,084 | module MODULE1(VAR1, clk, req, ack, reset);
output reg VAR1;
input clk, req, ack, reset;
reg [2:0] state;
begin
begin
begin
end
begin
begin
end
begin
begin
end
begin
begin
end
begin
begin
begin
begin | mit |
queq/just-stuff | pov/TopFixed/MaquinaDeControl.v | 1,652 | module MODULE1(
input VAR11,
input VAR1,
input VAR3,
input VAR7,
output reg VAR9,
output reg VAR10,
output reg VAR6
);
reg [1:0]state;
parameter VAR5 = 3'h0;
parameter VAR2 = 3'h1;
parameter VAR8 = 3'h3;
parameter VAR4 = 3'h2;
always @(negedge VAR11) begin
if (VAR1)
state = VAR5;
end
else begin
case(state)
VAR5:begin
i... | mit |
civol/HDLRuby | lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_222.v | 16,293 | module MODULE1(
module 00003aT0( );
reg rst;
reg VAR5;
reg VAR2;
reg VAR6;
reg [7:0] VAR9;
reg [7:0] VAR16;
wire [7:0] VAR13;
reg [3:0] counter;
wire 00003a13;
wire [1:0] 00003a14;
reg 00003a8;
wire [7:0] 00003a9;
reg [1:0] 00003a10;
reg 00003a11;
reg [7:0] 00003a12 [0:2];
wire [7:0] 00003a4;
wire 00003a5;
wire [1:0] 0... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_049.v | 1,510 | module MODULE1 (
VAR3,
VAR11
);
input [31:0] VAR3;
output [31:0]
VAR11;
wire [31:0]
VAR2,
VAR6,
VAR10,
VAR13,
VAR14,
VAR5,
VAR9,
VAR12,
VAR4;
assign VAR2 = VAR3;
assign VAR10 = VAR6 - VAR2;
assign VAR6 = VAR2 << 7;
assign VAR4 = VAR12 - VAR9;
assign VAR12 = VAR10 << 4;
assign VAR13 = VAR2 << 8;
assign VAR14 = VAR2 + VA... | mit |
yard2010/Arducar | Car/Modules/Video-and-Image-Processing-Design-Using-FPGAs-master/de1_ov7670/SRC/Sdram_Control_4Port/control_interface.v | 7,395 | module MODULE1(
VAR3,
VAR1,
VAR12,
VAR4,
VAR5,
VAR21,
VAR20,
VAR7,
VAR15,
VAR10,
VAR14,
VAR2,
VAR22,
VAR16,
VAR18,
VAR19,
VAR17
);
input VAR3; input VAR1; input [2:0] VAR12; input [VAR6-1:0] VAR4; input VAR5; input VAR21; input VAR20; output VAR7; output VAR15; output VAR10; output VAR14; output VAR2; output VAR22; out... | apache-2.0 |
briburrell/amica | device/natura_salsa8/base/ztex_ufm1_15y1.v | 4,432 | module MODULE1 (VAR5, reset, select, VAR42, VAR67, VAR64, VAR80, VAR43, VAR20, VAR12, VAR56, read, write);
input VAR5, select, reset, VAR42, VAR67, VAR64, VAR80, VAR43, VAR20, VAR12, VAR56;
input [7:0] read;
output [7:0] write;
reg [3:0] VAR50, VAR11;
reg VAR45, VAR23, VAR51, VAR39 = 1, VAR30 = 1, VAR57;
reg VAR29, VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor2/sky130_fd_sc_ls__xor2.functional.pp.v | 1,814 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR13 ,
VAR9,
VAR4,
VAR2 ,
VAR8
);
output VAR10 ;
input VAR1 ;
input VAR13 ;
input VAR9;
input VAR4;
input VAR2 ;
input VAR8 ;
wire VAR5 ;
wire VAR7;
xor VAR11 (VAR5 , VAR13, VAR1 );
VAR6 VAR3 (VAR7, VAR5, VAR9, VAR4);
buf VAR12 (VAR10 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311o/sky130_fd_sc_hd__a311o.pp.symbol.v | 1,394 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR7 ,
input VAR1 ,
input VAR5 ,
output VAR8 ,
input VAR9 ,
input VAR10,
input VAR2,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcin/sky130_fd_sc_lp__fahcin.pp.symbol.v | 1,325 | module MODULE1 (
input VAR3 ,
input VAR5 ,
input VAR7 ,
output VAR2,
output VAR1 ,
input VAR4 ,
input VAR9,
input VAR6,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isobufsrc/sky130_fd_sc_lp__isobufsrc.pp.symbol.v | 1,351 | module MODULE1 (
input VAR7 ,
output VAR2 ,
input VAR3,
input VAR1 ,
input VAR5 ,
input VAR6 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxbp/sky130_fd_sc_hd__edfxbp.functional.pp.v | 2,082 | module MODULE1 (
VAR3 ,
VAR15 ,
VAR13 ,
VAR2 ,
VAR5 ,
VAR1,
VAR12,
VAR4 ,
VAR16
);
output VAR3 ;
output VAR15 ;
input VAR13 ;
input VAR2 ;
input VAR5 ;
input VAR1;
input VAR12;
input VAR4 ;
input VAR16 ;
wire VAR8 ;
wire VAR17;
VAR9 VAR10 (VAR17, VAR8, VAR2, VAR5 );
VAR14 VAR18 VAR6 (VAR8 , VAR17, VAR13, , VAR1, VAR12)... | apache-2.0 |
praveendath92/DDR2_Interface_Xilinx_XUPV5 | source/ddr2_phy_ctl_io.v | 9,970 | module MODULE1 #
(
parameter VAR29 = 2,
parameter VAR18 = 1,
parameter VAR7 = 10,
parameter VAR47 = 1,
parameter VAR49 = 0,
parameter VAR3 = 1,
parameter VAR12 = 1,
parameter VAR64 = 14,
parameter VAR32 = 1
)
(
input VAR68,
input VAR6,
input VAR55,
input VAR4,
input [VAR64-1:0] VAR34,
input [VAR29-1:0] VAR57,
input VAR... | mit |
alexforencich/xfcp | lib/eth/rtl/eth_phy_10g_rx_if.v | 7,027 | module MODULE1 #
(
parameter VAR5 = 64,
parameter VAR16 = 2,
parameter VAR18 = 0,
parameter VAR1 = 0,
parameter VAR11 = 0,
parameter VAR8 = 0,
parameter VAR13 = 1,
parameter VAR14 = 8,
parameter VAR9 = 125000/6.4
)
(
input wire clk,
input wire rst,
output wire [VAR5-1:0] VAR10,
output wire [VAR16-1:0] VAR3,
input wire ... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min_wdq_buf.v | 3,286 | module MODULE1(
VAR14,
clk, VAR4, VAR23, VAR5, VAR16, VAR24, VAR22,
VAR2, VAR8, VAR18, VAR11, VAR1,
VAR15, VAR20
);
input clk;
input VAR4;
input VAR23;
input VAR5;
input VAR16;
input VAR24;
input VAR22;
input [VAR26-1:0] VAR2;
input [VAR26-1:0] VAR8;
input [127:0] VAR18;
input [6:0] VAR11;
input [6:0] VAR1;
input [6:0]... | gpl-2.0 |
sirchuckalot/zet | cores/zet/rtl/zet_rxr16.v | 2,271 | module MODULE1 (
input [15:0] VAR3,
input VAR5,
input [ 4:0] VAR6,
input VAR4,
output reg [15:0] VAR1,
output reg VAR2
);
always @(VAR3 or VAR5 or VAR6 or VAR4)
case (VAR6)
default: {VAR2,VAR1} <= {VAR5,VAR3};
5'd01: {VAR2,VAR1} <= VAR4 ? {VAR3[0], VAR5, VAR3[15:1]} : {VAR5, VAR3[0], VAR3[15:1]};
5'd02: {VAR2,VAR1} <= ... | gpl-3.0 |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_kon.v | 1,480 | module MODULE1(
input rst,
input clk,
input [3:0] VAR7,
input [2:0] VAR3,
input [1:0] VAR9,
input [2:0] VAR14,
input VAR10,
input VAR6,
input VAR11,
output reg VAR5
);
reg din;
wire VAR8;
reg [3:0] VAR13;
always @(posedge clk)
VAR5 <= (VAR6&&VAR11) || VAR8;
always @(*) begin
case( VAR9 )
2'd0: VAR13 = 4'b0001; 2'd1: VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor3/sky130_fd_sc_hd__xnor3.functional.pp.v | 1,828 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR14 ,
VAR8 ,
VAR7,
VAR1,
VAR12 ,
VAR5
);
output VAR9 ;
input VAR2 ;
input VAR14 ;
input VAR8 ;
input VAR7;
input VAR1;
input VAR12 ;
input VAR5 ;
wire VAR4 ;
wire VAR11;
xnor VAR3 (VAR4 , VAR2, VAR14, VAR8 );
VAR10 VAR13 (VAR11, VAR4, VAR7, VAR1);
buf VAR6 (VAR9 , VAR11 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_hip_s4gx_gen2_x4_128/pci_express_compiler-library/altpcie_phasefifo.v | 5,839 | module MODULE1 (
VAR16,
VAR57,
VAR41,
VAR12,
VAR40
);
parameter VAR37 = 20;
parameter VAR28 = 0;
input VAR16;
input VAR57;
input[VAR37 - 1:0] VAR41;
input VAR12;
output [VAR37 - 1:0] VAR40;
wire [VAR37 - 1:0] VAR40;
reg VAR9;
reg[3-VAR28:0] VAR49;
reg[3:0] VAR61;
reg VAR17;
reg VAR24;
reg VAR51 ;
reg VAR18 ;
reg VAR31 ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31a/sky130_fd_sc_lp__o31a_lp.v | 2,330 | module MODULE1 (
VAR11 ,
VAR6 ,
VAR5 ,
VAR7 ,
VAR1 ,
VAR8,
VAR9,
VAR2 ,
VAR3
);
output VAR11 ;
input VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR8;
input VAR9;
input VAR2 ;
input VAR3 ;
VAR4 VAR10 (
.VAR11(VAR11),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/ipcore_dir/ddr_wr_stream_fifo.v | 13,858 | module MODULE1(
VAR43,
VAR250,
VAR96,
VAR135,
VAR94,
VAR264,
VAR393,
VAR384
);
input VAR43;
input VAR250;
input VAR96;
output VAR135;
input [511 : 0] VAR94;
output VAR264;
input VAR393;
output [511 : 0] VAR384;
VAR272 #(
.VAR126(0),
.VAR25(0),
.VAR365(0),
.VAR19(0),
.VAR249(0),
.VAR111(0),
.VAR115(0),
.VAR273(32),
.VAR... | mit |
jotego/jt51 | syn/xilinx/contra_snd/hdl/clocks.v | 1,817 | module MODULE1(
input rst,
input VAR16,
input VAR27,
input VAR7,
output VAR15,
output VAR8,
output VAR12,
output reg VAR22,
output VAR1,
output VAR2
);
wire VAR4; reg [1:0] VAR11;
reg VAR19, VAR29;
reg VAR3, VAR31;
always @(negedge VAR4)
VAR3 <= VAR7;
reg VAR28;
always @(posedge VAR4 or posedge rst)
if( rst )
VAR28 <= ... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/nios_solo_bb.v | 1,129 | module MODULE1 (
VAR18,
VAR3,
VAR10,
VAR25,
VAR20,
VAR5,
VAR9,
VAR23,
VAR12,
VAR6,
VAR15,
VAR7,
VAR17,
VAR2,
VAR16,
VAR14,
VAR19,
VAR1,
VAR4,
VAR24,
VAR21,
VAR22,
VAR11,
VAR26,
VAR8,
VAR13);
input VAR18;
input VAR3;
input [7:0] VAR10;
output VAR25;
output [7:0] VAR20;
output VAR5;
output [19:0] VAR9;
input VAR23;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4bb/sky130_fd_sc_lp__or4bb.pp.symbol.v | 1,328 | module MODULE1 (
input VAR7 ,
input VAR5 ,
input VAR3 ,
input VAR6 ,
output VAR2 ,
input VAR1 ,
input VAR9,
input VAR8,
input VAR4
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_pcie_bram_7x.v | 9,032 | module MODULE1
parameter [3:0] VAR22 = 4'h1, parameter [5:0] VAR14 = 6'h08, parameter VAR2 = "VAR3", parameter VAR9 = 0, parameter VAR15 = 0 )
(
input VAR13, input VAR19,
input VAR16, input [12:0] VAR27, input [VAR15 - 1:0] VAR7,
input VAR24, input VAR28, input [12:0] VAR26,
output [VAR15 - 1:0] VAR1 );
localparam VAR1... | lgpl-3.0 |
jotego/jt12 | hdl/jt12_pm.v | 5,589 | module MODULE1 (
input [4:0] VAR6,
input [10:0] VAR2,
input [2:0] VAR12,
output reg signed [8:0] VAR3
);
reg [7:0] VAR7;
reg [7:0] VAR10;
reg [9:0] VAR4;
wire [2:0] VAR9 = VAR6[3] ? (~VAR6[2:0]) : VAR6[2:0];
reg [2:0] VAR8 [0:63];
reg [2:0] VAR1 [0:63];
reg [2:0] VAR11, VAR5; | gpl-3.0 |
sudov/options-accel | final_design/fifo.prj/sol/syn/verilog/dut_dmul_64ns_64ns_64_6_max_dsp.v | 1,903 | module MODULE1
VAR25 = 1,
VAR11 = 6,
VAR16 = 64,
VAR14 = 64,
VAR20 = 64
)(
input wire clk,
input wire reset,
input wire VAR8,
input wire [VAR16-1:0] VAR7,
input wire [VAR14-1:0] VAR19,
output wire [VAR20-1:0] dout
);
wire VAR22;
wire VAR5;
wire VAR1;
wire [63:0] VAR23;
wire VAR10;
wire [63:0] VAR13;
wire VAR17;
wire [6... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mux_one_hot.v | 1,305 | if (VAR13 && VAR6 == VAR2 && VAR12 == VAR18) \
begin: VAR11 \
VAR16 VAR17 \
(.* \
); \
end
module MODULE1 #(parameter VAR19(VAR12)
, VAR6=1
, VAR13=1
)
(
input [VAR6-1:0][VAR12-1:0] VAR7
,input [VAR6-1:0] VAR3
,output [VAR12-1:0] VAR1
);
wire [VAR6-1:0][VAR12-1:0] VAR8;
genvar VAR10,VAR14;
else
else
begin : VAR4
for (V... | bsd-3-clause |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_axi.v | 57,400 | module MODULE1 #
(
parameter VAR318 = 100,
parameter VAR7 = "135", parameter VAR58 = 64,
parameter VAR338 = "VAR176",
parameter VAR448 = "0", parameter VAR124 = 3, parameter VAR111 = 2, parameter VAR310 = "8", parameter VAR335 = "VAR403", parameter VAR388 = "VAR451", parameter VAR259 = 1, parameter VAR242 = 5,
paramete... | mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/Controller.v | 31,377 | module MODULE1(
input wire clk, VAR47,
input wire VAR32, VAR61,
output reg [ 3:0] VAR21,
output wire VAR6, VAR15,
output wire [ 9:0] VAR44, VAR35,
output reg VAR59, VAR4,
output reg signed [31:0] VAR28,
output wire VAR52,
output wire VAR39, VAR18, VAR31, VAR25, VAR2,
output wire VAR57, VAR10, VAR33, VAR19, VAR3,
output... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/spw_babasu_bb.v | 1,667 | module MODULE1 (
VAR7,
VAR20,
VAR1,
VAR3,
VAR5,
VAR8,
VAR13,
VAR21,
VAR19,
VAR4,
VAR10,
VAR18,
VAR9,
VAR17,
VAR16,
VAR6,
VAR11,
VAR14,
VAR12,
VAR15,
VAR2);
output VAR7;
input VAR20;
input [2:0] VAR1;
output [8:0] VAR3;
input [8:0] VAR5;
input [10:0] VAR8;
output VAR13;
output VAR21;
output VAR19;
output VAR4;
output VA... | gpl-3.0 |
cpulabs/mist1032sa | src/core/execute/execute_port3.v | 12,025 | module MODULE1(
input wire VAR20,
input wire VAR139,
input wire VAR15,
input wire VAR64,
input wire VAR91,
input wire [31:0] VAR50,
input wire [31:0] VAR108,
input wire [31:0] VAR16,
input wire [31:0] VAR57,
output wire [31:0] VAR90,
output wire VAR124,
input wire VAR24,
output wire [1:0] VAR9, output wire [3:0] VAR58,... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3b/sky130_fd_sc_hdll__nand3b.functional.pp.v | 1,991 | module MODULE1 (
VAR2 ,
VAR15 ,
VAR8 ,
VAR11 ,
VAR14,
VAR7,
VAR6 ,
VAR9
);
output VAR2 ;
input VAR15 ;
input VAR8 ;
input VAR11 ;
input VAR14;
input VAR7;
input VAR6 ;
input VAR9 ;
wire VAR12 ;
wire VAR4 ;
wire VAR13;
not VAR5 (VAR12 , VAR15 );
nand VAR1 (VAR4 , VAR8, VAR12, VAR11 );
VAR16 VAR10 (VAR13, VAR4, VAR14, VA... | apache-2.0 |
davidkoltak/tawas-core | ip/rcn/rtl/rcn_master_buf.v | 2,460 | module MODULE1
(
input rst,
input clk,
input [68:0] VAR15,
output [68:0] VAR23,
input VAR17,
input [1:0] VAR24,
output VAR8,
input wr,
input [3:0] VAR20,
input [23:0] addr,
input [31:0] VAR22,
output VAR25,
output [1:0] VAR16,
output VAR1,
output VAR3,
output [1:0] VAR9,
output [3:0] VAR10,
output [23:0] VAR4,
output [... | mit |
polysome/hydra | implementation/I_Cache.v | 70,062 | module MODULE1 (
VAR134,
VAR52,
VAR7,
VAR154,
VAR172,
VAR117,
VAR208
);
parameter VAR106 = 32;
parameter VAR123 = 128;
parameter VAR64 = 7;
parameter VAR90 = {VAR106{1'VAR30}};
parameter VAR199 = {VAR106{1'b1}};
parameter VAR45 = {VAR64{1'VAR30}};
parameter VAR75 = {VAR64{1'b1}};
parameter VAR118 = 1;
parameter VAR127 ... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_data_shift.v | 13,735 | module MODULE1
parameter VAR73 = 1,
parameter VAR8 = 1,
parameter VAR38 = 128,
parameter VAR44 = "VAR9"
)
(
input VAR65,
input VAR54,
input VAR4,
input [VAR38-1:0] VAR35,
input VAR28,
input [VAR76(VAR38/32)-1:0] VAR34,
input VAR69,
input [VAR76(VAR38/32)-1:0] VAR83,
output VAR32,
input VAR85,
output [VAR38-1:0] VAR19,
... | gpl-3.0 |
denis4net/hw_design | 2/altera-project/src/clkdiv.v | 1,399 | module MODULE1(input in, output out);
parameter VAR3 = VAR3;
parameter VAR1 = VAR1;
reg [VAR3-1:0] VAR2;
reg VAR4;
assign out = VAR4; | mit |
sirchuckalot/zet | cores/vga/rtl/fml/vga_palette_regs_fml.v | 1,532 | module MODULE1 (
input clk,
input [3:0] VAR5,
output reg [7:0] VAR1,
input [3:0] address,
input write,
output reg [7:0] VAR3,
input [7:0] VAR2
);
reg [7:0] VAR4 [0:15];
always @(posedge clk) VAR1 <= VAR4[VAR5];
always @(posedge clk) VAR3 <= VAR4[address];
always @(posedge clk)
if (write) VAR4[address] <= VAR2;
endmodul... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/hpdmc_ddr32/rtl/spartan6/hpdmc_oddr4.v | 1,846 | module MODULE1 #(
parameter VAR1 = "VAR11",
parameter VAR4 = 1'b0,
parameter VAR14 = "VAR12"
) (
output [3:0] VAR16,
input VAR11,
input VAR7,
input VAR13,
input [3:0] VAR2,
input [3:0] VAR5,
input VAR17,
input VAR15
);
VAR10 #(
.VAR1(VAR1),
.VAR4(VAR4),
.VAR14(VAR14)
) VAR3 (
.VAR16(VAR16[0]),
.VAR11(VAR11),
.VAR7(VAR7... | lgpl-3.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_lite_i2c/rtl/i2c_master_top.v | 10,081 | module MODULE1(
VAR27, VAR46, VAR39, VAR53, VAR26, VAR55,
VAR1, VAR38, VAR7, VAR47, VAR3,
VAR8, VAR14, VAR19, VAR9, VAR42, VAR4 );
parameter VAR22 = 1'b0;
input VAR27; input VAR46; input VAR39; input [2:0] VAR53; input [7:0] VAR26; output [7:0] VAR55; input VAR1; input VAR38; input VAR7; output VAR47; output VAR3;
reg ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv_16.v | 2,001 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR2,
VAR3,
VAR5 ,
VAR8
);
output VAR6 ;
input VAR1 ;
input VAR2;
input VAR3;
input VAR5 ;
input VAR8 ;
VAR7 VAR4 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR2;
supply0 VAR3;... | apache-2.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/xadc_temp_sensor/xadc_temp_sensor.v | 8,585 | module MODULE1
(
VAR58, VAR59, VAR80, VAR20, VAR46, VAR30, VAR72, VAR7, VAR14, VAR1, VAR6, VAR32, VAR26, VAR65, VAR17, VAR81, VAR53, VAR27);
input [6:0] VAR58;
input VAR59;
input VAR80;
input [15:0] VAR20;
input VAR46;
input VAR53;
input VAR27;
output VAR30;
output [4:0] VAR72;
output [15:0] VAR7;
output VAR14;
output ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3_2.v | 2,047 | module MODULE2 (
VAR3 ,
VAR4 ,
VAR5 ,
VAR7 ,
VAR1,
VAR2
);
output VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR7 ;
input VAR1;
input VAR2;
VAR6 VAR8 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR3,
VAR4,
VAR5,
VAR7
);
output VAR3;
input VAR4;
input VAR5;
in... | apache-2.0 |
balanx/laotzu | RTL/stream_asyn_fifo_read.v | 4,219 | module MODULE1 #(
parameter VAR15 = 1, parameter VAR5 = 6,
parameter [VAR5:0] VAR21 = 44,
parameter [VAR5:0] VAR10 = 0,
parameter [VAR5:0] VAR22 = 7
) (
input wire VAR19 ,
input wire VAR11 ,
input wire VAR14 ,
input wire [VAR5:0] VAR3 ,
output reg [VAR5-1:0] VAR18 ,
output reg [VAR5:0] VAR1 ,
output VAR6 ,
output reg V... | apache-2.0 |
merckhung/zet | cores/flash/flash8.v | 3,110 | module MODULE1 (
input VAR22,
input VAR9,
input [15:0] VAR14,
output [15:0] VAR13,
input VAR21,
input VAR1,
input [ 1:0] VAR16,
input VAR17,
input VAR5,
output VAR20,
output [21:0] VAR4,
input [ 7:0] VAR2,
output VAR3,
output VAR6,
output VAR7,
output VAR19
);
wire VAR8;
wire VAR11;
reg [20:0] address;
wire word;
wire ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_2.behavioral.pp.v | 1,164 | module MODULE1( VAR5, VAR2, VAR4, VAR3 );
input VAR5;
inout VAR4, VAR3;
output VAR2;
VAR6 VAR1(.VAR5(VAR5),.VAR2(VAR2),.VAR4(VAR4),.VAR3(VAR3));
VAR6 VAR7(.VAR5(VAR5),.VAR2(VAR2),.VAR4(VAR4),.VAR3(VAR3)); | apache-2.0 |
sh-chris110/chris | FPGA/HPS/db/ip/hps_design/submodules/hps_design_SMP_HPS_hps_io.v | 1,931 | module MODULE1 (
output wire [14:0] VAR3, output wire [2:0] VAR2, output wire VAR15, output wire VAR11, output wire VAR7, output wire VAR12, output wire VAR6, output wire VAR8, output wire VAR13, output wire VAR16, inout wire [31:0] VAR18, inout wire [3:0] VAR4, inout wire [3:0] VAR14, output wire VAR10, output wire [3... | gpl-2.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/alt_vipvfr131_common_avalon_mm_slave.v | 4,632 | module MODULE1
VAR6 = 5,
VAR23 = 16,
VAR7 = 1,
VAR29 = 1, VAR30 = 4,
VAR11 = 0) (
input wire rst,
input wire clk,
input wire [VAR6-1:0] VAR22,
input wire VAR19,
output reg [VAR23-1:0] VAR13,
input wire VAR14,
input wire [VAR23-1:0] VAR24,
output VAR12,
output reg enable,
input VAR20, output reg [VAR30-1:0] VAR4,
output... | gpl-3.0 |
fabianz66/cursos-tec | taller-digital/Lab2/laboratorio2/FSM_semaforo.v | 4,568 | module MODULE1(clk, reset, VAR25, VAR27, VAR28, VAR19, VAR22, VAR15, VAR29, VAR20, VAR1, VAR10, VAR8, VAR3, VAR4, VAR17);
input clk, VAR28, VAR27, VAR19, VAR25, reset;
output VAR22, VAR20, VAR1, VAR10, VAR8, VAR3, VAR4, VAR17, VAR29;
output reg [1:0] VAR15;
reg [3:0] state;
parameter VAR2 = 0;
parameter VAR9 = 1;
param... | mit |
gralco/click-clock-board | myhdl/clock.v | 3,245 | module MODULE1 (
clk,
reset,
en,
VAR1,
VAR4,
VAR6
);
input clk;
input reset;
input en;
input [23:0] VAR1;
output VAR4;
reg VAR4;
input [41:0] VAR6;
reg [3:0] VAR5 [0:6-1];
reg [6:0] VAR2 [0:6-1];
always @(posedge clk, posedge reset) begin: VAR3
if (reset == 1) begin
VAR5[0] <= 0;
VAR5[1] <= 0;
VAR5[2] <= 0;
VAR5[3] <= ... | gpl-3.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/rli/pkt_insert.v | 12,860 | module MODULE1(
clk,
reset,
VAR14,
VAR37,
VAR27,
VAR32,
VAR44,
VAR5,
VAR17,
VAR46,
VAR2,
VAR23,
VAR3,
VAR45
);
input clk;
input reset;
input VAR14; input [138:0]VAR37;
output [7:0]VAR27;
input VAR32;
input VAR44;
output VAR5; output [138:0]VAR17;
input [7:0]VAR46;
output VAR2;
output VAR23;
input [31:0]VAR3; input [31:... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtp/sky130_fd_sc_ls__dlrtp.functional.pp.v | 1,928 | module MODULE1 (
VAR5 ,
VAR7,
VAR9 ,
VAR10 ,
VAR4 ,
VAR2 ,
VAR1 ,
VAR12
);
output VAR5 ;
input VAR7;
input VAR9 ;
input VAR10 ;
input VAR4 ;
input VAR2 ;
input VAR1 ;
input VAR12 ;
wire VAR13;
wire VAR3;
not VAR11 (VAR13 , VAR7 );
VAR15 VAR8 VAR14 (VAR3 , VAR9, VAR10, VAR13, , VAR4, VAR2);
buf VAR6 (VAR5 , VAR3 );
endm... | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/ethmac/eth_maccontrol.v | 11,662 | module MODULE1 (VAR45, VAR28, VAR12, VAR56, VAR39, VAR52, VAR24, VAR19,
VAR47, VAR35, VAR37, VAR53, VAR11, VAR20, VAR38, VAR1,
VAR30, VAR54, VAR22, VAR27, VAR55, VAR57,
VAR25, VAR42, VAR50, VAR16, VAR41, VAR32, VAR36, VAR34,
VAR21, VAR31, VAR8, VAR48, VAR5,
VAR13, VAR4, VAR2, VAR46, VAR49
);
parameter VAR23 = 1;
input ... | lgpl-3.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/rom.v | 4,982 | module MODULE1
parameter VAR13 = 0)
(
input VAR9,
input VAR17,
input [(VAR10+2)-1:2] VAR16,
input VAR12,
input VAR5,
input [2:0] VAR2,
input [1:0] VAR1,
output reg [31:0] VAR6,
output reg VAR19);
reg [VAR10-1:0] VAR3;
always @ (posedge VAR9 or posedge VAR17)
if (VAR17)
VAR6 <= 32'h15000000;
else
case (VAR3)
case(VAR16)... | gpl-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir/qmfir_eth/qmfir_udp/EDK_project/hdl/qmfir_0_wrapper.v | 4,112 | module MODULE1
(
VAR15,
VAR4,
VAR65,
VAR48,
VAR50,
VAR10,
VAR12,
VAR5,
VAR7,
VAR63,
VAR8,
VAR30,
VAR31,
VAR13,
VAR49,
VAR58,
VAR6,
VAR38,
VAR34,
VAR20,
VAR25,
VAR26,
VAR39,
VAR23,
VAR37,
VAR27,
VAR47,
VAR45,
VAR46,
VAR64,
VAR60,
VAR17,
VAR16,
VAR52,
VAR14,
VAR29,
VAR51,
VAR21,
VAR28,
VAR35,
VAR62,
VAR33,
VAR40
);
input... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfsbp/sky130_fd_sc_hvl__dfsbp.behavioral.pp.v | 2,611 | module MODULE1 (
VAR21 ,
VAR3 ,
VAR13 ,
VAR16 ,
VAR22,
VAR20 ,
VAR15 ,
VAR23 ,
VAR25
);
output VAR21 ;
output VAR3 ;
input VAR13 ;
input VAR16 ;
input VAR22;
input VAR20 ;
input VAR15 ;
input VAR23 ;
input VAR25 ;
wire VAR24 ;
wire VAR5 ;
reg VAR17 ;
wire VAR8 ;
wire VAR14 ;
wire VAR26;
wire VAR9 ;
wire VAR11 ;
wire VA... | apache-2.0 |
lvd2/ngs | fpga/current/interrupts/interrupts.v | 1,875 | module MODULE1
(
input wire clk,
input wire VAR13,
input wire VAR18,
input wire VAR3,
output reg VAR19,
input wire [7:0] din,
output wire [7:0] VAR1,
output wire [2:0] VAR9,
input wire VAR14,
input wire VAR10,
input wire [2:0] VAR7
);
reg VAR5, VAR11;
wire VAR12;
reg VAR4, VAR6;
wire VAR8;
reg [2:0] VAR17;
reg [2:0] re... | gpl-3.0 |
Valakor/EE201-Text-Editor | text_editor_keyboard_controller.v | 4,430 | module MODULE1(
input VAR23,
input VAR24,
input VAR6,
inout VAR10,
inout VAR12,
output reg [7:0] VAR16,
output reg VAR3
);
reg [1:0] state;
localparam
VAR18 = 2'b00,
VAR9 = 2'b01,
VAR7 = 2'b10,
VAR2 = 2'VAR28;
wire [7:0] VAR17;
wire VAR22;
reg [7:0] VAR19;
reg VAR4;
reg [7:0] VAR5;
wire VAR27;
VAR25 VAR1(
.VAR15(VAR24)... | mit |
ShirmanXia/EE469SPRING16 | lab3/db/ip/nios_system/submodules/nios_system_nios2_qsys_0.v | 5,818 | module MODULE1 (
input wire clk, input wire VAR8, input wire VAR22, output wire [18:0] VAR13, output wire [3:0] VAR12, output wire VAR19, input wire [31:0] VAR14, input wire VAR9, output wire VAR25, output wire [31:0] VAR18, output wire VAR2, output wire [18:0] VAR7, output wire VAR21, input wire [31:0] VAR15, input wi... | gpl-3.0 |
DreamSourceLab/DSLogic-hdl | src/reset.v | 3,275 | module MODULE1(
input VAR17,
input VAR2,
input VAR11,
input VAR19,
input VAR9,
input VAR12,
output VAR1,
output VAR18,
output VAR4,
output VAR16,
output VAR24,
output VAR23
);
wire VAR3;
assign VAR3 = VAR9 | VAR12;
reg [3:0] VAR5;
wire [3:0] VAR15;
assign VAR1 = VAR5[3];
assign VAR15 = {VAR5[2:0], 1'b0};
always @(posed... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtn/sky130_fd_sc_hd__dlrtn.behavioral.pp.v | 2,446 | module MODULE1 (
VAR20 ,
VAR14,
VAR16 ,
VAR10 ,
VAR17 ,
VAR18 ,
VAR4 ,
VAR7
);
output VAR20 ;
input VAR14;
input VAR16 ;
input VAR10 ;
input VAR17 ;
input VAR18 ;
input VAR4 ;
input VAR7 ;
wire VAR23 ;
wire VAR19 ;
reg VAR6 ;
wire VAR22 ;
wire VAR15 ;
wire VAR2 ;
wire VAR9;
wire VAR8 ;
wire VAR13 ;
wire VAR21 ;
wire VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtp/sky130_fd_sc_hs__dlxtp.behavioral.v | 1,763 | module MODULE1 (
VAR12 ,
VAR6 ,
VAR11,
VAR13,
VAR4
);
output VAR12 ;
input VAR6 ;
input VAR11;
input VAR13;
input VAR4;
wire VAR5 VAR3;
wire VAR5 VAR8 ;
reg VAR2 ;
wire VAR5 ;
wire VAR1 ;
VAR9 VAR7 (VAR5 , VAR8, VAR3, VAR2, VAR13, VAR4);
buf VAR10 (VAR12 , VAR5 );
assign VAR1 = ( VAR13 === 1'b1 );
endmodule | apache-2.0 |
aj-michael/Lab1SN74LS195A | SN74LS195AAbsoluteTime.v | 1,215 | module MODULE1;
reg [3:0] VAR8;
reg VAR15, VAR10, VAR1, VAR6, VAR7;
wire VAR14, VAR11;
wire [3:0] VAR2, VAR5;
VAR4 VAR9 (VAR5, VAR8, VAR14, VAR15, VAR10, VAR1, VAR6, VAR7);
VAR12 VAR3 (VAR2, VAR8, VAR11, VAR15, VAR10, VAR1, VAR6, VAR7);
always VAR6 = ~VAR6;
VAR13 fork
VAR7 = 1; VAR8 = 4'b1010; VAR15=0; VAR10 = 0; VAR1 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.behavioral.pp.v | 1,914 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR5,
VAR14 ,
VAR4 ,
VAR8 ,
VAR1
);
output VAR9 ;
input VAR3 ;
input VAR5;
input VAR14 ;
input VAR4 ;
input VAR8 ;
input VAR1 ;
wire VAR10 ;
reg VAR2 ;
wire VAR6;
wire VAR7 ;
VAR11 VAR12 (VAR10 , VAR7, VAR6, VAR2, VAR14, VAR4);
buf VAR13 (VAR9 , VAR10 );
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_axi.v | 8,715 | module MODULE1 (
VAR3,
VAR36,
VAR27,
VAR19,
VAR5,
VAR4,
VAR1,
VAR10,
VAR34,
VAR38,
VAR16,
VAR17,
VAR15,
VAR13,
VAR25,
VAR2,
VAR8,
VAR22,
VAR23,
VAR21,
VAR18,
VAR24,
VAR14,
VAR35,
VAR11,
VAR31,
VAR7);
parameter VAR37 = 14;
localparam VAR9 = VAR37 - 1;
input VAR3;
input VAR36;
input VAR27;
input [31:0] VAR19;
output VAR5... | lgpl-3.0 |
pseudoincorrect/FPGA_MCU_wifi | FPGA/src/SRAM_modules/fifo_SRAM.v | 11,683 | module MODULE1(
input wire clk,
input wire VAR23,
output wire [19:0] VAR15,
inout [15:0] VAR13,
output reg VAR42, output reg VAR6, output wire VAR20, output wire VAR8, output wire VAR35, input wire [31:0] VAR46,
output wire [31:0] VAR36,
input wire VAR43,
input wire VAR7,
output reg VAR2,
output reg VAR47,
output reg V... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/Tiger4NSC/src/d_BCH_encoder_top.v | 7,838 | module MODULE1
(
input wire VAR19,
input wire VAR15,
input wire VAR2, input wire VAR10, input wire [VAR34-1:0] VAR17, output reg VAR38,
output wire VAR12, output wire VAR26, output wire VAR18,
input wire VAR16,
output wire VAR27, output wire VAR35, output wire VAR8,
output wire [VAR34-1:0] VAR31 );
parameter VAR3 = 7;
... | gpl-3.0 |
tloinuy/opencpi-opencv | opencpi/hdl/prims/bsv/SyncReset0.v | 1,417 | module MODULE1 (
VAR1,
VAR2
);
input VAR1 ;
output VAR2 ;
assign VAR2 = VAR1 ;
endmodule | gpl-2.0 |
dawsonjon/fpu | double_divider/double_divider.v | 7,506 | module MODULE1(
VAR3,
VAR11,
VAR42,
VAR39,
VAR25,
clk,
rst,
VAR1,
VAR34,
VAR18,
VAR21);
input clk;
input rst;
input [63:0] VAR3;
input VAR42;
output VAR18;
input [63:0] VAR11;
input VAR39;
output VAR21;
output [63:0] VAR1;
output VAR34;
input VAR25;
reg VAR33;
reg [63:0] VAR24;
reg VAR38;
reg VAR44;
reg [3:0] state;
pa... | mit |
pwwu/FPGA | VGAbased/final/vga_game_graph.v | 13,377 | module MODULE1
(
input wire clk, reset,
input wire VAR9,
input wire [2:0] VAR22,
input wire VAR52,
input wire [9:0] VAR26, VAR43,
output reg VAR57, VAR28, VAR24,
output wire VAR45,
output reg [2:0] VAR10
);
localparam VAR32 = 640;
localparam VAR20 = 480;
wire VAR31;
localparam VAR7 = 20;
localparam VAR30 = 25;
localpar... | mit |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0/synth/design_1_auto_us_0.v | 10,216 | module MODULE1 (
VAR44,
VAR62,
VAR42,
VAR68,
VAR15,
VAR96,
VAR7,
VAR23,
VAR12,
VAR77,
VAR18,
VAR27,
VAR22,
VAR48,
VAR52,
VAR58,
VAR87,
VAR40,
VAR11,
VAR93,
VAR32,
VAR65,
VAR97,
VAR6,
VAR79,
VAR76,
VAR84,
VAR13,
VAR72,
VAR73,
VAR50,
VAR36,
VAR70,
VAR1,
VAR60,
VAR91,
VAR56,
VAR55
);
input wire VAR44;
input wire VAR62;
in... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/rxc_engine_classic.v | 20,979 | module MODULE1
parameter VAR21 = 128,
parameter VAR108 = 10)
( input VAR68,
input VAR98, input VAR80, output VAR130,
input [VAR21-1:0] VAR46,
input VAR27,
input VAR143,
input [VAR18-1:0] VAR28,
input VAR96,
input [VAR18-1:0] VAR99,
input [VAR19-1:0] VAR76,
output [VAR21-1:0] VAR51,
output VAR140,
output [(VAR21/32)-1:0... | gpl-3.0 |
MCDELTAT/CSE311 | lab3/bin2sevenSeg.v | 3,146 | module MODULE1 (
input wire clk,
input wire [13:0] din, output reg [15:0] VAR8, output reg [3:0] VAR2,
output reg [3:0] VAR4,
output reg [3:0] VAR6,
output reg [3:0] VAR7,
output reg [13:0] dout
);
reg [13:0] VAR1;
reg [15:0] VAR5;
reg VAR3;
begin
begin
begin
begin
end | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21o/sky130_fd_sc_lp__a21o.blackbox.v | 1,326 | module MODULE1 (
VAR7 ,
VAR5,
VAR3,
VAR6
);
output VAR7 ;
input VAR5;
input VAR3;
input VAR6;
supply1 VAR2;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bushold/sky130_fd_sc_lp__bushold_1.v | 2,161 | module MODULE2 (
VAR3 ,
VAR8,
VAR5 ,
VAR7 ,
VAR4 ,
VAR6
);
inout VAR3 ;
input VAR8;
input VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR6 ;
VAR2 VAR1 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR3 ,
VAR8
);
inout VAR3 ;
input VAR8;
supply1 VAR5;
supply0 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21oi/sky130_fd_sc_hs__a21oi.symbol.v | 1,313 | module MODULE1 (
input VAR3,
input VAR6,
input VAR1,
output VAR2
);
supply1 VAR4;
supply0 VAR5;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_1.behavioral.v | 1,802 | module MODULE1( VAR5, VAR6, VAR3, VAR7, VAR2 );
input VAR3, VAR5, VAR7, VAR2;
output VAR6;
VAR4 VAR1(.VAR5(VAR5),.VAR6(VAR6),.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2));
VAR4 VAR8(.VAR5(VAR5),.VAR6(VAR6),.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_lpddr2_addr_cmd.v | 15,387 | module MODULE1
VAR20 = 1,
VAR29 = 1,
VAR39 = 1, VAR28 = 20,
VAR9 = 15, VAR22 = 12, VAR47 = 3, VAR21 = 2
)
(
VAR7,
VAR41,
VAR34,
VAR6,
VAR4,
VAR12,
VAR24,
VAR15,
VAR25,
VAR42,
VAR18,
VAR13,
VAR43,
VAR3,
VAR17, VAR48, VAR45, VAR10,
VAR19, VAR35,
VAR26,
VAR1,
VAR2,
VAR46,
VAR14,
VAR31,
VAR33,
VAR8
);
input VAR7;
input VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311oi/sky130_fd_sc_ls__a311oi.functional.pp.v | 2,076 | module MODULE1 (
VAR16 ,
VAR8 ,
VAR7 ,
VAR4 ,
VAR15 ,
VAR6 ,
VAR1,
VAR18,
VAR3 ,
VAR11
);
output VAR16 ;
input VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR15 ;
input VAR6 ;
input VAR1;
input VAR18;
input VAR3 ;
input VAR11 ;
wire VAR5 ;
wire VAR9 ;
wire VAR2;
and VAR12 (VAR5 , VAR4, VAR8, VAR7 );
nor VAR17 (VAR9 , VAR5, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufbuf/sky130_fd_sc_hs__bufbuf.blackbox.v | 1,188 | module MODULE1 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
supply1 VAR1;
supply0 VAR3;
endmodule | apache-2.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/z80/zwait.v | 1,059 | module MODULE1(
input wire VAR5,
input wire VAR2,
input wire VAR4,
input wire VAR3,
output reg [6:0] VAR1,
output wire VAR6,
output wire VAR7
);
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor3/sky130_fd_sc_ms__xnor3.behavioral.pp.v | 1,828 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR7 ,
VAR13 ,
VAR1,
VAR2,
VAR4 ,
VAR5
);
output VAR8 ;
input VAR3 ;
input VAR7 ;
input VAR13 ;
input VAR1;
input VAR2;
input VAR4 ;
input VAR5 ;
wire VAR11 ;
wire VAR10;
xnor VAR9 (VAR11 , VAR3, VAR7, VAR13 );
VAR14 VAR12 (VAR10, VAR11, VAR1, VAR2);
buf VAR6 (VAR8 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill_diode/sky130_fd_sc_ms__fill_diode.functional.pp.v | 1,178 | module MODULE1 (
VAR3,
VAR1,
VAR2 ,
VAR4
);
input VAR3;
input VAR1;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31o/sky130_fd_sc_ls__a31o_4.v | 2,337 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR3 ,
VAR6 ,
VAR5 ,
VAR11,
VAR1,
VAR8 ,
VAR10
);
output VAR7 ;
input VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR5 ;
input VAR11;
input VAR1;
input VAR8 ;
input VAR10 ;
VAR4 VAR9 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR8(VAR8),
.VA... | apache-2.0 |
rkrajnc/minimig-mist | rtl/or1200/or1200_spram_32x24.v | 7,244 | module MODULE1(
VAR24, VAR14, VAR10,
clk, rst, VAR9, VAR8, VAR12, addr, VAR13, VAR2
);
parameter VAR18 = 5;
parameter VAR16 = 24;
input VAR24;
input [VAR21 - 1:0] VAR10;
output VAR14;
input clk; input rst; input VAR9; input VAR8; input VAR12; input [VAR18-1:0] addr; input [VAR16-1:0] VAR13; output [VAR16-1:0] VAR2;
wir... | gpl-3.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/error_detect_4byte.v | 12,255 | module MODULE1
(
VAR18,
VAR16,
VAR9,
VAR7,
VAR11,
VAR15,
VAR10,
VAR6,
VAR12,
VAR5,
VAR13
);
input VAR18;
output VAR16;
output [0:1] VAR9;
output VAR7;
input [3:0] VAR11;
input [3:0] VAR15;
input [3:0] VAR10;
input VAR6;
input VAR12;
input VAR5;
input VAR13;
reg [0:1] VAR9;
reg VAR7;
reg [0:1] VAR2;
reg [0:1] VAR4;
reg ... | bsd-2-clause |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_SEQ_LVT_TT_210930.v | 73,172 | module MODULE1 (VAR6, VAR8, VAR11, VAR4);
output VAR6;
input VAR8, VAR11, VAR4;
reg VAR5;
wire VAR7, VAR10;
wire VAR16, VAR2, VAR9;
wire VAR3;
not (VAR16, VAR7);
not (VAR9, VAR11);
VAR13 (VAR3, VAR10, VAR16, VAR9);
VAR1 (VAR2, VAR5, VAR10, VAR16, VAR9, VAR3);
buf (VAR6, VAR2);
wire VAR15, VAR12, VAR14;
and (VAR15, VAR8... | bsd-3-clause |
monotone-RK/FACE | MCSoC-15/8-way_4-parallel/ise/ipcore_dir/dram/example_design/rtl/traffic_gen/mig_7series_v1_9_tg_prbs_gen.v | 11,144 | module MODULE1 #
(
parameter VAR10 = 100, parameter VAR5 = 10, parameter VAR6 = 4 )
(
input VAR3, input VAR9, input VAR20, input [VAR5-1:0] VAR13, output [2*VAR6-1:0] VAR15, output [31:0] VAR24
);
function integer VAR17 (input integer VAR19);
begin
VAR19 = VAR19 - 1;
for (VAR17=1; VAR19>1; VAR17=VAR17+1)
VAR19 = VAR19 ... | mit |
open-power/snap | actions/hdl_helloworld/hw/hdl/axi_master_wr.v | 9,312 | module MODULE1 #(
parameter VAR35 = 2,
parameter VAR48 = 64,
parameter VAR22 = 512,
parameter VAR1 = 8,
parameter VAR52 = 8,
parameter VAR50 = 1,
parameter VAR18 = 1,
parameter VAR32 = 1
)
(
input clk ,
input VAR41 ,
input VAR30 ,
input [031:0] VAR13,
output [VAR35 - 1:0] VAR46 ,
output reg[VAR48 - 1:0] VAR65 ,
output ... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/nios_system.v | 80,036 | module MODULE1 (
output wire [31:0] VAR342, output wire [31:0] VAR158, input wire VAR312, output wire [2:0] VAR347, input wire VAR90, input wire [31:0] VAR106, input wire VAR224, input wire VAR318, input wire VAR49, output wire [3:0] VAR216, output wire [3:0] VAR26, output wire [3:0] VAR14, output wire [3:0] VAR181, ou... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_ground_lvc_wpad/sky130_fd_io__top_ground_lvc_wpad.functional.v | 1,159 | module MODULE1 ( VAR19, VAR10, VAR13
);
inout VAR19;
inout VAR10;
inout VAR13;
supply0 VAR12;
supply0 VAR6;
supply1 VAR11;
supply1 VAR7;
supply1 VAR21;
supply0 VAR1;
supply0 VAR9;
supply1 VAR8;
supply1 VAR14;
supply1 VAR15;
supply1 VAR20;
supply1 VAR3;
supply1 VAR16;
supply1 VAR22;
supply1 VAR5;
supply0 VAR17;
supply0 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221o/sky130_fd_sc_lp__a221o_1.v | 2,444 | module MODULE1 (
VAR1 ,
VAR12 ,
VAR5 ,
VAR6 ,
VAR2 ,
VAR11 ,
VAR8,
VAR10,
VAR9 ,
VAR4
);
output VAR1 ;
input VAR12 ;
input VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR11 ;
input VAR8;
input VAR10;
input VAR9 ;
input VAR4 ;
VAR7 VAR3 (
.VAR1(VAR1),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR8... | apache-2.0 |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/gfx_wbm_read_arbiter.v | 3,309 | module MODULE1
(
VAR10,
VAR4,
VAR7,
VAR2,
VAR16,
VAR21,
VAR5,
VAR27,
VAR17,
VAR24,
VAR1,
VAR18,
VAR22,
VAR15,
VAR26,
VAR20,
VAR6,
VAR8,
VAR11,
VAR12,
VAR14
);
output VAR10;
output VAR4;
output [31:2] VAR7;
output [3:0] VAR2;
input [31:0] VAR16;
input VAR21;
input VAR5;
input [31:2] VAR27;
input [3:0] VAR17;
output [31:... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/tq_top.v | 25,878 | module MODULE1(
clk ,
rst ,
VAR186 ,
VAR84 ,
VAR85 ,
VAR121 ,
VAR96 ,
VAR153 ,
VAR159 ,
VAR2 ,
VAR133 ,
VAR43 ,
VAR188 ,
VAR168 ,
VAR164 ,
VAR13 ,
VAR70 ,
VAR31
);
input clk ;
input rst ;
input VAR186 ;
input [5:0] VAR84 ;
input VAR85 ;
input [1:0] VAR121 ;
input [1:0] VAR96 ;
input [4:0] VAR153 ;
input [287:0] VAR159 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fah/sky130_fd_sc_hd__fah.behavioral.v | 1,744 | module MODULE1 (
VAR12,
VAR4 ,
VAR14 ,
VAR17 ,
VAR3
);
output VAR12;
output VAR4 ;
input VAR14 ;
input VAR17 ;
input VAR3 ;
supply1 VAR18;
supply0 VAR13;
supply1 VAR5 ;
supply0 VAR15 ;
wire VAR16;
wire VAR6 ;
wire VAR21 ;
wire VAR1 ;
wire VAR8;
xor VAR19 (VAR16, VAR14, VAR17, VAR3 );
buf VAR2 (VAR4 , VAR16 );
and VAR20... | apache-2.0 |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_auto_pc_1/synth/dma_loopback_auto_pc_1.v | 15,761 | module MODULE1 (
VAR17,
VAR96,
VAR109,
VAR21,
VAR60,
VAR7,
VAR49,
VAR22,
VAR5,
VAR110,
VAR92,
VAR104,
VAR59,
VAR98,
VAR37,
VAR42,
VAR23,
VAR53,
VAR27,
VAR77,
VAR54,
VAR73,
VAR64,
VAR111,
VAR47,
VAR15,
VAR43,
VAR41,
VAR107,
VAR88,
VAR19,
VAR10,
VAR25,
VAR91,
VAR35,
VAR71,
VAR68,
VAR103,
VAR12,
VAR45,
VAR81,
VAR11,
VAR55... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_1.behavioral.v | 1,410 | module MODULE1( VAR1, VAR2, VAR5 );
input VAR2, VAR1;
output VAR5;
VAR6 VAR4(.VAR1(VAR1),.VAR2(VAR2),.VAR5(VAR5));
VAR6 VAR3(.VAR1(VAR1),.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s.functional.pp.v | 1,868 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR8,
VAR5,
VAR2 ,
VAR12
);
output VAR10 ;
input VAR6 ;
input VAR8;
input VAR5;
input VAR2 ;
input VAR12 ;
wire VAR11 ;
wire VAR3;
buf VAR4 (VAR11 , VAR6 );
VAR7 VAR9 (VAR3, VAR11, VAR8, VAR5);
buf VAR1 (VAR10 , VAR3 );
endmodule | apache-2.0 |
horia141/bachelor-thesis | prj/applications/BigSDRAM/BigSDRAM.v | 2,573 | module MODULE1(VAR18,VAR39,VAR10,reset,VAR8,VAR14,VAR47,VAR27,VAR17,VAR36,VAR21,VAR13,VAR20,VAR11,VAR15,VAR30,VAR3,VAR32);
input wire VAR18;
input wire VAR39;
input wire VAR10;
input wire reset;
output wire [7:0] VAR8;
input wire VAR14;
input wire VAR47;
input wire VAR27;
output wire VAR17;
output wire VAR36;
output wi... | mit |
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