repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
moizumi99/brainf__k_CPU | hdl/brainfuck_top.v | 3,674 | module MODULE1
(
input clk, VAR60,
output VAR17, output VAR18, output VAR8, output VAR6, inout [7:0] VAR48, input [7:0] VAR2,
input VAR50,
output VAR64,
input VAR30,
output VAR69
);
wire [31:0] VAR58;
reg VAR67;
wire [11:0] VAR54;
wire [15:0] do;
wire VAR16, VAR38, VAR20;
wire [15:0] VAR59;
wire VAR1, VAR72, VAR34;
wir... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221oi/sky130_fd_sc_lp__a221oi.functional.v | 1,582 | module MODULE1 (
VAR6 ,
VAR3,
VAR2,
VAR4,
VAR11,
VAR13
);
output VAR6 ;
input VAR3;
input VAR2;
input VAR4;
input VAR11;
input VAR13;
wire VAR7 ;
wire VAR5 ;
wire VAR8;
and VAR10 (VAR7 , VAR4, VAR11 );
and VAR12 (VAR5 , VAR3, VAR2 );
nor VAR1 (VAR8, VAR7, VAR13, VAR5);
buf VAR9 (VAR6 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4b/sky130_fd_sc_lp__and4b.behavioral.v | 1,508 | module MODULE1 (
VAR11 ,
VAR13,
VAR5 ,
VAR6 ,
VAR14
);
output VAR11 ;
input VAR13;
input VAR5 ;
input VAR6 ;
input VAR14 ;
supply1 VAR7;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR8 ;
wire VAR10 ;
wire VAR9;
not VAR12 (VAR10 , VAR13 );
and VAR2 (VAR9, VAR10, VAR5, VAR6, VAR14);
buf VAR1 (VAR11 , VAR9 );
endmodule | apache-2.0 |
ptracton/vscale_soc | rtl/wb_intercon-1.0/rtl/verilog/wb_arbiter.v | 4,803 | module MODULE1
parameter VAR7 = 32,
parameter VAR31 = 2)
(
input VAR29,
input VAR20,
input [VAR31*VAR7-1:0] VAR8,
input [VAR31*VAR22-1:0] VAR35,
input [VAR31*4-1:0] VAR16,
input [VAR31-1:0] VAR10,
input [VAR31-1:0] VAR34,
input [VAR31-1:0] VAR6,
input [VAR31*3-1:0] VAR33,
input [VAR31*2-1:0] VAR15,
output [VAR31*VAR22-... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/io_queues/ethernet_mac/megafunctions/rxlengthfifo_128x13_bb.v | 6,212 | module MODULE1 (
VAR1,
VAR3,
VAR5,
VAR9,
VAR4,
VAR8,
VAR2,
VAR7,
VAR6);
input VAR1;
input [14:0] VAR3;
input VAR5;
input VAR9;
input VAR4;
input VAR8;
output [14:0] VAR2;
output VAR7;
output VAR6;
tri0 VAR1;
endmodule | mit |
joaocarlos/udlx-verilog | rtl/common/edge_detect.v | 1,151 | module MODULE1
(
input clk,
input VAR2,
input VAR4,
output reg VAR1
);
reg VAR3,VAR5;
always @(posedge clk or negedge VAR2) begin
if (!VAR2) begin
VAR3 <= 1'b0;
VAR5 <= 1'b0;
end
else begin
VAR3 <= VAR4;
VAR5 <= VAR3;
end
end
always @(posedge clk or negedge VAR2) begin
if (!VAR2) begin
VAR1 <= 1'b0;
end
else begin
if (... | lgpl-3.0 |
mlarouche/sd2snes | verilog/sd2sneslite/data.v | 2,153 | module MODULE1(
input VAR7,
input VAR23,
input VAR10,
input VAR20,
input VAR6,
inout [7:0] VAR12,
inout [15:0] VAR13,
input [7:0] VAR5,
output [7:0] VAR19,
input VAR9,
input VAR3,
input VAR4,
input VAR14,
input VAR2,
input VAR11,
input VAR8,
output [7:0] VAR17,
input [7:0] VAR21
);
reg [7:0] VAR1;
reg [7:0] VAR24;
reg ... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Reset_Delay.v | 2,029 | module MODULE1
(
VAR10,
reset,
VAR5,
VAR12,
VAR6,
VAR4
);
input VAR10;
input reset;
input VAR5;
input VAR12;
input signed [31:0] VAR6; output signed [31:0] VAR4;
wire signed [31:0] VAR1; wire signed [31:0] VAR7; reg signed [31:0] VAR11; wire signed [31:0] VAR2; wire signed [31:0] VAR3;
assign VAR1 = 32'VAR9;
assign VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21o/sky130_fd_sc_lp__a21o_lp.v | 2,256 | module MODULE2 (
VAR8 ,
VAR5 ,
VAR2 ,
VAR1 ,
VAR4,
VAR9,
VAR3 ,
VAR7
);
output VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR4;
input VAR9;
input VAR3 ;
input VAR7 ;
VAR6 VAR10 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE2 (... | apache-2.0 |
gbraad/minimig-de1 | rtl/audio/audio_shifter.v | 1,392 | module MODULE1(
input wire clk, input wire VAR15,
input wire VAR10,
input wire [ 15-1:0] VAR11,
input wire [ 15-1:0] VAR1,
input wire VAR14,
output wire VAR12,
output wire VAR2,
output wire VAR8,
output wire VAR3
);
wire [ 16-1:0] VAR7;
wire [ 16-1:0] VAR9;
assign VAR7 = {VAR11[14], VAR11} + {{2{VAR1[14]}}, VAR1[14:1]}... | gpl-3.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/HDLNeuralNetwork/ALUNeuralNetwork.v | 10,014 | module MODULE1#(parameter VAR1 = 32,VAR52=0, VAR145 = 9, VAR161 = 22, VAR20 = 1, VAR117= 0,
VAR129= 1, VAR80 = 2, VAR55 = 3, VAR151 = 4, VAR78 = 5, VAR60 = 6, VAR175 = 7, VAR119 = 8, VAR122 = 9,
VAR8= 10, VAR131= 11, VAR132 = 12, VAR40 = 13, VAR172 = 14, VAR141 = 15, VAR180 = 16, VAR37 = 17, VAR110 = 18, VAR164 = 19,
V... | gpl-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_fp_exp_double.v | 298,492 | module MODULE2
(
VAR32,
VAR9,
VAR1,
VAR4,
VAR20,
VAR25) ;
input VAR32;
input VAR9;
input VAR1;
input [89:0] VAR4;
input [89:0] VAR20;
output [89:0] VAR25;
tri0 VAR32;
tri1 VAR9;
tri0 VAR1;
tri0 [89:0] VAR4;
tri0 [89:0] VAR20;
wire [89:0] VAR57;
wire [89:0] VAR44;
VAR5 VAR29
(
.VAR32(VAR32),
.VAR9(VAR9),
.VAR1(VAR1),
.V... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_015.v | 1,459 | module MODULE1 (
VAR10,
VAR11
);
input [31:0] VAR10;
output [31:0]
VAR11;
wire [31:0]
VAR4,
VAR6,
VAR7,
VAR12,
VAR2,
VAR9,
VAR3,
VAR5;
assign VAR4 = VAR10;
assign VAR2 = VAR7 - VAR12;
assign VAR6 = VAR4 << 4;
assign VAR7 = VAR4 + VAR6;
assign VAR5 = VAR3 << 3;
assign VAR12 = VAR4 << 2;
assign VAR9 = VAR2 << 5;
assign V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211ai/sky130_fd_sc_lp__o211ai_1.v | 2,361 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR10 ,
VAR7 ,
VAR6 ,
VAR8,
VAR5,
VAR2 ,
VAR11
);
output VAR9 ;
input VAR3 ;
input VAR10 ;
input VAR7 ;
input VAR6 ;
input VAR8;
input VAR5;
input VAR2 ;
input VAR11 ;
VAR1 VAR4 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221oi/sky130_fd_sc_hs__a221oi.behavioral.v | 2,101 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR2 ,
VAR9 ,
VAR13 ,
VAR7 ,
VAR16,
VAR17
);
output VAR11 ;
input VAR3 ;
input VAR2 ;
input VAR9 ;
input VAR13 ;
input VAR7 ;
input VAR16;
input VAR17;
wire VAR13 VAR6 ;
wire VAR13 VAR18 ;
wire VAR12 ;
wire VAR8;
and VAR15 (VAR6 , VAR9, VAR13 );
and VAR14 (VAR18 , VAR3, VAR2 );
nor VAR1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlstp/sky130_fd_sc_lp__srdlstp.behavioral.v | 2,193 | module MODULE1 (
VAR12 ,
VAR5 ,
VAR10 ,
VAR21 ,
VAR19
);
output VAR12 ;
input VAR5 ;
input VAR10 ;
input VAR21 ;
input VAR19;
supply1 VAR1;
supply1 VAR22 ;
supply0 VAR7 ;
supply1 VAR14 ;
supply0 VAR11 ;
wire VAR9 ;
reg VAR17 ;
wire VAR6 ;
wire VAR13 ;
wire VAR20;
wire VAR3;
wire VAR15 ;
wire VAR18 ;
wire VAR16 ;
VAR8 V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221oi/sky130_fd_sc_hs__a221oi.behavioral.pp.v | 2,108 | module MODULE1 (
VAR13,
VAR7,
VAR11 ,
VAR2 ,
VAR18 ,
VAR17 ,
VAR4 ,
VAR8
);
input VAR13;
input VAR7;
output VAR11 ;
input VAR2 ;
input VAR18 ;
input VAR17 ;
input VAR4 ;
input VAR8 ;
wire VAR4 VAR16 ;
wire VAR4 VAR14 ;
wire VAR6 ;
wire VAR1;
and VAR10 (VAR16 , VAR17, VAR4 );
and VAR3 (VAR14 , VAR2, VAR18 );
nor VAR9 (V... | apache-2.0 |
hanw/sonic-lite | hw/verilog/scramble/descrambler.v | 2,195 | module MODULE1 # (
parameter VAR5 = 512
)(
input clk,VAR1,VAR8,
input [VAR5-1:0] din, output reg [VAR5-1:0] dout
);
reg [57:0] VAR6;
wire [VAR5+58-1:0] VAR7;
wire [VAR5-1:0] VAR3;
assign VAR7 = {din,VAR6};
genvar VAR4;
generate
for (VAR4=0; VAR4<VAR5; VAR4=VAR4+1) begin : VAR2
assign VAR3[VAR4] = VAR7[58+VAR4-58] ^ VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.behavioral.v | 1,469 | module MODULE1 (
VAR5,
VAR1
);
output VAR5;
input VAR1;
supply1 VAR4;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR6 ;
buf VAR2 (VAR5 , VAR1 );
endmodule | apache-2.0 |
alexforencich/verilog-flowgen | rtl/fg_packet_gen.v | 10,153 | module MODULE1 #(
parameter VAR15 = 8,
parameter VAR11 = 64,
parameter VAR24 = (VAR11/8)
)
(
input wire clk,
input wire rst,
input wire VAR36,
output wire VAR37,
input wire [VAR15-1:0] VAR39,
input wire [31:0] VAR32,
output wire VAR20,
input wire VAR44,
output wire [VAR15-1:0] VAR45,
output wire [15:0] VAR22,
output wi... | mit |
kwantam/multiexp-a5gx | ddr3/ddr3_x32.v | 33,558 | module MODULE1 (
input wire VAR37, input wire VAR54, input wire VAR32, output wire VAR45, output wire VAR20, output wire VAR4, output wire VAR43, output wire [12:0] VAR31, output wire [2:0] VAR19, output wire [0:0] VAR25, output wire [0:0] VAR11, output wire [0:0] VAR38, output wire [0:0] VAR44, output wire [3:0] VAR53... | gpl-3.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/rx_data_fifo.v | 13,517 | module MODULE1(
clk,
VAR256,
din,
VAR338,
VAR334,
dout,
VAR279,
VAR124,
VAR123,
VAR306,
VAR88
);
input clk;
input VAR256;
input [31 : 0] din;
input VAR338;
input VAR334;
output [31 : 0] dout;
output VAR279;
output VAR124;
output VAR123;
output VAR306;
output [6 : 0] VAR88;
VAR329 #(
.VAR148(0),
.VAR311(0),
.VAR171(0),
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2/sky130_fd_sc_ls__nand2_2.v | 2,097 | module MODULE2 (
VAR5 ,
VAR9 ,
VAR3 ,
VAR4,
VAR1,
VAR7 ,
VAR2
);
output VAR5 ;
input VAR9 ;
input VAR3 ;
input VAR4;
input VAR1;
input VAR7 ;
input VAR2 ;
VAR6 VAR8 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR5,
VAR9,
VAR3
);
output VAR5;
... | apache-2.0 |
Anirudh94/Connect4-FPGA | Connect4/Grid.v | 6,183 | module MODULE1 (
address,
VAR3,
VAR49);
input [14:0] address;
input VAR3;
output [2:0] VAR49;
tri1 VAR3;
wire [2:0] VAR42;
wire [2:0] VAR49 = VAR42[2:0];
VAR27 VAR23 (
.VAR14 (address),
.VAR4 (VAR3),
.VAR33 (VAR42),
.VAR48 (1'b0),
.VAR18 (1'b0),
.VAR29 (1'b1),
.VAR17 (1'b0),
.VAR30 (1'b0),
.VAR41 (1'b1),
.VAR31 (1'b1),... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fsb/bsg_fsb.v | 14,171 | module MODULE2 #(parameter VAR45( VAR54 )
,parameter VAR45(VAR27 )
, parameter VAR50 = (VAR27) ' (0)
, parameter VAR47 = (VAR27) ' (0)
, parameter VAR18 = VAR3(VAR27)
)
(input VAR16
, input VAR25
, input VAR30
, input [VAR54-1:0] VAR28
, output VAR2
, output VAR13
, output [VAR54-1:0] VAR24
, input VAR55
, output [VAR2... | bsd-3-clause |
somethingnew2-0/CS552-CPU | RoadRunner/off_by_one.tar.gz_extracted/ALU.v | 2,013 | module MODULE1(VAR9, VAR7, VAR19, VAR18, VAR6, VAR21, VAR12, VAR4);
input [15:0] VAR9, VAR7;
input [2:0] VAR19;
input [3:0] VAR18;
output [15:0] VAR6;
output VAR21, VAR12, VAR4;
wire [15:0] VAR3, VAR11;
localparam VAR22 = 3'b000; localparam VAR13 = 3'b001;
localparam VAR14 = 3'b010;
localparam VAR20 = 3'b011;
localpara... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_50.v | 32,117 | module MODULE5 (
clk,
reset,
VAR222,
VAR10,
VAR117,
VAR134,
VAR208
);
parameter VAR286 = 18;
parameter VAR178 = 50;
parameter VAR129 = 25;
localparam VAR30 = 51;
input clk;
input reset;
input VAR222;
input VAR10;
input [VAR286-1:0] VAR117; output VAR134;
output [VAR286-1:0] VAR208;
localparam VAR35 = 18; localparam VAR... | mit |
walkthetalk/fsref | ip/fsa_v2/src/fsa_v2.v | 12,877 | module MODULE1 #(
parameter integer VAR157 = 0,
parameter integer VAR190 = 24, parameter integer VAR53 = 1,
parameter integer VAR163 = 8,
parameter integer VAR202 = 12,
parameter integer VAR92 = 12,
parameter integer VAR167 = 4,
parameter integer VAR173 = 12, parameter integer VAR43 = 51, parameter integer VAR8 = 8,
pa... | gpl-3.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/VGA_OSD_RAM.v | 1,497 | module MODULE1 ( VAR16,
VAR20,
VAR11,
VAR3,
VAR17,
VAR2,
VAR23,
VAR9,
VAR26,
VAR1,
VAR8,
VAR15,
VAR14,
VAR18,
VAR4,
VAR5 );
output reg [9:0] VAR16;
output reg [9:0] VAR20;
output reg [9:0] VAR11;
input [18:0] VAR3;
input VAR17;
input [18:0] VAR23;
input VAR2;
input VAR9;
input VAR26;
input [9:0] VAR1;
input [9:0] VAR8;... | gpl-3.0 |
secworks/avalanche_entropy | src/rtl/avalanche_entropy.v | 8,011 | module MODULE1(
input wire clk,
input wire VAR2,
input wire VAR4,
input wire VAR18,
input wire VAR1,
input wire [7 : 0] address,
input wire [31 : 0] VAR23,
output wire [31 : 0] VAR9,
output wire VAR21,
input wire VAR36,
input wire VAR26,
output wire VAR34,
output wire VAR17,
output wire [31 : 0] VAR35,
output wire VAR2... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.behavioral.pp.v | 1,089 | module MODULE1( VAR1, VAR5 );
inout VAR1, VAR5;
VAR3 VAR2(.VAR1(VAR1),.VAR5(VAR5));
VAR3 VAR4(.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
hakehuang/pycpld | ips/ip/i2c_slave_for_case_two_ad/i2c_slave_op.v | 16,133 | module MODULE1(
VAR12,
VAR13,
VAR45,
VAR40,
VAR11,
VAR55,
VAR20
);
input VAR13;
input VAR20;
input VAR12;
input VAR40;
input VAR11;
output VAR55;
reg VAR55;
output VAR45;
reg VAR28;
reg VAR25;
reg VAR53;
reg VAR23;
reg VAR30;
reg VAR17;
reg VAR58;
reg VAR22;
reg [7:0] VAR52;
reg [7:0] VAR1;
reg [7:0] VAR60;
reg [7:0] V... | mit |
rakeshkadamati/MIPS-32-Bit-Verilog | dataMem.v | 1,547 | module MODULE1(VAR2,VAR3,addr,clk,out);
input [5:0] VAR2;
input [31:0] addr, VAR3;
input clk;
output [31:0] out;
reg [31:0] VAR1 [255:0];
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41o/sky130_fd_sc_lp__a41o.pp.symbol.v | 1,388 | module MODULE1 (
input VAR4 ,
input VAR2 ,
input VAR10 ,
input VAR5 ,
input VAR7 ,
output VAR8 ,
input VAR6 ,
input VAR3,
input VAR1,
input VAR9
);
endmodule | apache-2.0 |
chriz2600/DreamcastHDMI | Core/source/ram2video.v | 15,818 | module MODULE1(
input [23:0] VAR65,
input VAR59,
input VAR78,
input reset,
input VAR50,
input VAR101,
output [VAR24-1:0] VAR2 ,
input [7:0] VAR45,
output [9:0] VAR123,
output [23:0] VAR1,
output VAR30,
output VAR57,
output VAR29,
input VAR99,
input [7:0] VAR124,
input VAR131 VAR31 ,
input VAR136 VAR19,
output reg VAR23... | mit |
SeanZarzycki/openSPARC-FPU | project/src/fpu_denorm_3b.v | 1,852 | module MODULE1 (
VAR2,
VAR3,
VAR4,
VAR5
);
input [2:0] VAR2; input [2:0] VAR3;
output VAR4; output VAR5;
wire [2:0] VAR1;
wire VAR4;
wire VAR5;
assign VAR1[2:0]= (~(VAR2 | VAR3));
assign VAR4= (!(&VAR1[2:0]));
assign VAR5= VAR3[2]
|| (VAR1[2] && VAR3[1])
|| ((&VAR1[2:1]) && VAR3[0]);
endmodule | gpl-3.0 |
richard42/CoCo3FPGA | 6551rx.v | 5,578 | module MODULE1(
VAR9,
VAR1,
VAR14,
VAR8,
VAR4,
VAR12,
VAR10,
VAR13,
VAR6,
VAR11
);
input VAR9;
input VAR1;
input VAR14;
output [7:0] VAR8;
reg [7:0] VAR8;
input [1:0] VAR4;
input VAR12;
input [1:0] VAR10;
output VAR13;
reg VAR13;
output VAR6;
reg VAR6;
output VAR11;
reg VAR11;
reg [5:0] VAR2;
reg [2:0] VAR5;
reg VAR7;
... | bsd-3-clause |
praveendath92/DDR2_Interface_Xilinx_XUPV5 | source/ddr2_phy_top.v | 17,174 | module MODULE1 #
(
parameter VAR89 = 2,
parameter VAR14 = 1,
parameter VAR86 = 1,
parameter VAR68 = 10,
parameter VAR61 = 0,
parameter VAR93 = 1,
parameter VAR1 = 1,
parameter VAR92 = 1,
parameter VAR11 = 9,
parameter VAR8 = 72,
parameter VAR31 = 7,
parameter VAR70 = 8,
parameter VAR117 = 9,
parameter VAR116 = 4,
param... | mit |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v | 6,389 | module MODULE1;
parameter VAR22 = 750*2;
reg [19:0] VAR10;
reg VAR6, VAR16, VAR8, VAR2,VAR5;
wire [31:0] VAR23,VAR3,VAR9,VAR7,in;
VAR13 VAR17(in,in,VAR10,VAR6, VAR16, VAR8, VAR2,VAR5, VAR23,VAR3,VAR9,VAR7);
reg [31:0] VAR14;
wire VAR20;
wire [31:0] VAR25;
wire [3:0] VAR1;
wire [3:0] VAR15;
VAR21 VAR18(VAR9,VAR3,VAR14,V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxbp/sky130_fd_sc_hs__edfxbp.behavioral.pp.v | 2,083 | module MODULE1 (
VAR9 ,
VAR11 ,
VAR4 ,
VAR2 ,
VAR13 ,
VAR18,
VAR10
);
output VAR9 ;
output VAR11 ;
input VAR4 ;
input VAR2 ;
input VAR13 ;
input VAR18;
input VAR10;
wire VAR6 ;
reg VAR14 ;
wire VAR3 ;
wire VAR16 ;
wire VAR12;
wire VAR17 ;
wire VAR15 ;
VAR7 VAR5 (VAR6 , VAR3, VAR12, VAR16, VAR14, VAR18, VAR10);
assign V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111o/sky130_fd_sc_ms__a2111o.functional.pp.v | 2,070 | module MODULE1 (
VAR17 ,
VAR13 ,
VAR4 ,
VAR11 ,
VAR8 ,
VAR5 ,
VAR2,
VAR10,
VAR14 ,
VAR16
);
output VAR17 ;
input VAR13 ;
input VAR4 ;
input VAR11 ;
input VAR8 ;
input VAR5 ;
input VAR2;
input VAR10;
input VAR14 ;
input VAR16 ;
wire VAR18 ;
wire VAR1 ;
wire VAR12;
and VAR3 (VAR18 , VAR13, VAR4 );
or VAR15 (VAR1 , VAR8, ... | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_fp_uitofp.v | 32,863 | module MODULE1
(
VAR14,
VAR16,
VAR13,
VAR11,
VAR9,
VAR17) ;
input VAR14;
input VAR16;
input VAR13;
input [32:0] VAR11;
input [5:0] VAR9;
output [32:0] VAR17;
tri0 VAR14;
tri1 VAR16;
tri0 VAR13;
reg [1:0] VAR5;
reg [32:0] VAR6;
reg [32:0] VAR18;
reg VAR4;
reg VAR15;
reg VAR10;
wire [6:0] VAR8;
wire VAR7;
wire [31:0] VAR... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/acl_fp_sincos_s5.v | 1,257 | module MODULE1(VAR4, VAR5, VAR7, VAR6, VAR11, enable);
input VAR4, VAR5, enable;
input [31:0] VAR7;
output [31:0] VAR6; output [31:0] VAR11;
VAR3 VAR8(
.clk(VAR4),
.VAR10(1'b0),
.en(enable),
.VAR1(VAR7),
.VAR9(VAR6),
.VAR2(VAR11));
endmodule | mit |
scalable-networks/ext | uhd/fpga/usrp2/gpmc/cross_clock_reader.v | 1,366 | module MODULE1
parameter VAR4 = 1,
parameter VAR5 = 0
)
(
input clk, input rst,
input [VAR4-1:0] in,
output reg [VAR4-1:0] out
);
reg [VAR4-1:0] VAR1, VAR2;
reg [2:0] VAR3;
always @(posedge clk) begin
if (rst) begin
out <= VAR5;
VAR1 <= VAR5;
VAR2 <= VAR5;
VAR3 <= 0;
end
else if (VAR1 == VAR2) VAR3 <= VAR3 + 1;
end
els... | gpl-2.0 |
mindstation/TrafficLightFPGA | Svetofors_025/time_signal.v | 3,188 | module MODULE1 ( input wire clk,
input wire reset,
output wire timeout
);
reg [24:0] VAR1; reg [0:0] VAR2;
assign timeout = VAR2;
always @(posedge clk) begin
if (!reset) begin VAR1 <= 25'd0;
VAR2 <= 1'd0; end
else begin
end
if (VAR1 <= 25'd25000000) VAR1 <= VAR1 + 25'd1; else VAR1 <= 25'd0;
end
if (VAR1 > 25'd12500000)... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v | 15,975 | module MODULE1 #
( parameter
VAR41 = 40,
VAR48 = 8,
VAR32 = 1,
VAR50 = 0,
VAR15 = 0,
VAR14 = 7,
VAR42 = 7,
VAR43 = 1
)
(
VAR53,
VAR47,
VAR8,
VAR23,
VAR44,
VAR4,
VAR25,
VAR38,
VAR45,
VAR34,
VAR51,
VAR36,
VAR19,
VAR7
);
localparam VAR26 = (VAR41 > 8) ? (VAR41 - VAR48) : (VAR41);
input VAR53;
input VAR47;
input [VAR14 - 1... | gpl-3.0 |
mogorman/papyrus | gateware/spiflasher/src/bscan_s6_spi_isf_ext.v | 1,240 | module MODULE1
(
output wire VAR21,
output wire VAR42,
output wire VAR29,
input VAR39
);
wire VAR14;
wire VAR2;
wire VAR45;
wire VAR5;
reg [47:0] VAR47;
reg [15:0] VAR43;
reg VAR17 = 0;
assign VAR21 = VAR45 ;
wire VAR44;
wire VAR35;
wire VAR6;
reg VAR33 = 0;
reg VAR19 = 0;
reg VAR1 = 0;
reg VAR25 = 0;
reg [13:0] VAR16;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux2/sky130_fd_sc_hvl__mux2.blackbox.v | 1,273 | module MODULE1 (
VAR1 ,
VAR5,
VAR4,
VAR7
);
output VAR1 ;
input VAR5;
input VAR4;
input VAR7 ;
supply1 VAR3;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Lan-Hekary/ARM | shift.v | 1,069 | module MODULE1(VAR1,VAR7,VAR4,VAR5);
input [7:0] VAR1;
input VAR7;
input [31:0] VAR4;
output [31:0] VAR5;
wire [4:0] VAR3;
assign VAR3[4:0]=(VAR1[0]==0)? VAR1[7:3] :5'b00000;
wire [1:0] VAR6;
assign VAR6[1:0]=VAR1[2:1];
wire [31:0] VAR2;
assign VAR2= (VAR6[1]==1) ? ( (VAR6[0]==1)? ( (VAR4>>VAR3)|(VAR4<<32-VAR3) ):( (VA... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ncio/rtl/jbi_ncio_prqq_buf.v | 3,560 | module MODULE1(
VAR19,
clk, VAR17, VAR11, VAR4, VAR25, VAR21,
VAR10, VAR14, VAR20, VAR24
);
input clk;
input VAR17;
input VAR11;
input VAR4;
input [4:0] VAR25;
input VAR21;
input VAR10;
input [VAR8-1:0] VAR14;
input [VAR8-1:0] VAR20;
input [VAR2-1:0] VAR24;
output [VAR2-1:0] VAR19;
wire [VAR2-1:0] VAR19;
wire [81-VAR2-... | gpl-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/rule_access.v | 7,446 | module MODULE1(
input clk,
input VAR41,
input VAR52,
input [15:0] VAR14,
output VAR12, output [31:0] VAR17,
input VAR34, output VAR18, input VAR22, input [15:0] VAR28,
input [31:0] VAR39,
output [31:0] VAR31
);
reg VAR33;
wire [15:0] VAR7;
wire VAR21;
wire VAR30;
wire VAR15;
wire [7:0] VAR49;
reg [7:0] VAR55;
wire [31:... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/hps_sdram_p0_iss_probe.v | 1,729 | module MODULE1 (
VAR8
);
parameter VAR11 = 1;
parameter VAR31 = "VAR2";
input [VAR11-1:0] VAR8;
VAR21 VAR23 (
.VAR33 (VAR8),
.VAR15 ()
,
.VAR29 (),
.VAR14 (),
.VAR4 (),
.VAR22 (),
.VAR18 (),
.VAR5 (),
.VAR12 (),
.VAR1 (),
.VAR6 (),
.VAR26 (),
.VAR7 (),
.VAR25 (),
.VAR13 (),
.VAR3 (),
.VAR16 (),
.VAR9 (),
.VAR10 ()
);
... | gpl-3.0 |
anderson1008/NOCulator | hring/hw/buffered/src/vcr_ugal_source.v | 8,194 | module MODULE1(
VAR13, VAR47,
clk, reset, VAR48, VAR4, VAR55, VAR79,
VAR22
);
parameter VAR53 = 3;
parameter VAR50 = 8;
parameter VAR35 = 1;
parameter VAR9 = 2;
localparam VAR8 = VAR35 * VAR9;
parameter VAR25 = 1;
localparam VAR41 = VAR8 * VAR25;
parameter VAR56 = 6;
parameter VAR12 = 4;
localparam VAR80 = VAR70(VAR12)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21bo/sky130_fd_sc_hd__a21bo.functional.v | 1,483 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR5 ,
VAR6
);
output VAR9 ;
input VAR7 ;
input VAR5 ;
input VAR6;
wire VAR4 ;
wire VAR2;
nand VAR3 (VAR4 , VAR5, VAR7 );
nand VAR8 (VAR2, VAR6, VAR4);
buf VAR1 (VAR9 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfstp/sky130_fd_sc_hdll__sdfstp.pp.blackbox.v | 1,442 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR8 ,
VAR6 ,
VAR9 ,
VAR4,
VAR5 ,
VAR10 ,
VAR1 ,
VAR3
);
output VAR2 ;
input VAR7 ;
input VAR8 ;
input VAR6 ;
input VAR9 ;
input VAR4;
input VAR5 ;
input VAR10 ;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipitc131_common_trigger_sync.v | 1,380 | module MODULE1(
input wire VAR6,
input wire VAR10,
input wire rst,
input wire VAR5,
input wire VAR13,
input wire VAR4,
output wire VAR11);
parameter VAR14 = 0;
generate
if(VAR14)
assign VAR11 = VAR13;
else begin
reg VAR2;
reg VAR1;
reg VAR3;
wire VAR15;
always @ (posedge VAR6 or posedge VAR10) begin
if(VAR6) begin
VAR2... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_2.behavioral.pp.v | 3,372 | module MODULE1( VAR3, VAR10, VAR9, VAR7, VAR6, VAR11, VAR8, VAR1 );
input VAR6, VAR11, VAR10, VAR3, VAR7;
inout VAR8, VAR1;
output VAR9;
VAR4 VAR2(.VAR3(VAR3),.VAR10(VAR10),.VAR9(VAR9),.VAR7(VAR7),.VAR6(VAR6),.VAR11(VAR11),.VAR8(VAR8),.VAR1(VAR1));
VAR4 VAR5(.VAR3(VAR3),.VAR10(VAR10),.VAR9(VAR9),.VAR7(VAR7),.VAR6(VAR6)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dlatch_p/sky130_fd_sc_hvl__udp_dlatch_p.blackbox.v | 1,251 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR1;
endmodule | apache-2.0 |
tommythorn/yari | shared/rtl/soclib/rs232out.v | 2,078 | module MODULE1
( input wire VAR6,
output wire VAR8,
input wire [7:0] VAR4,
input wire VAR10,
output wire VAR13);
parameter VAR2 = 0;
parameter VAR1 = 0;
parameter period = (VAR1 + VAR2/2) / VAR2;
parameter period = 0;
parameter VAR12 = 16; parameter VAR5 = 4;
reg [VAR12:0] VAR3 = 0; wire [31:0] VAR7 = period - 2;
reg [... | gpl-2.0 |
mbuesch/pyprofibus | phy_fpga/spi_slave_mod.v | 4,314 | module MODULE1 #(
parameter VAR18 = 8,
parameter VAR29 = 0,
parameter VAR23 = 0,
parameter VAR19 = 1,
) (
input clk,
input VAR1,
output VAR15,
input VAR5,
input VAR4,
output VAR13,
output [VAR18 - 1 : 0] VAR17,
input [VAR18 - 1 : 0] VAR3,
);
wire VAR16;
wire VAR26;
wire VAR10;
wire VAR6;
VAR11 VAR12(.clk(clk), .in(VAR1... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_2/synth/design_1_auto_pc_2.v | 16,145 | module MODULE1 (
VAR38,
VAR22,
VAR73,
VAR39,
VAR7,
VAR84,
VAR41,
VAR96,
VAR48,
VAR94,
VAR25,
VAR55,
VAR33,
VAR70,
VAR6,
VAR98,
VAR79,
VAR82,
VAR74,
VAR40,
VAR34,
VAR80,
VAR92,
VAR52,
VAR26,
VAR21,
VAR75,
VAR54,
VAR91,
VAR72,
VAR20,
VAR1,
VAR13,
VAR9,
VAR8,
VAR86,
VAR45,
VAR36,
VAR60,
VAR32,
VAR31,
VAR100,
VAR102,
VAR50... | mit |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/SDRAM_PLL.v | 17,424 | module MODULE1 (
VAR83,
VAR8,
VAR15,
VAR51);
input VAR83;
output VAR8;
output VAR15;
output VAR51;
wire [5:0] VAR56;
wire [0:0] VAR97 = 1'h0;
wire [2:2] VAR77 = VAR56[2:2];
wire [0:0] VAR2 = VAR56[0:0];
wire [1:1] VAR13 = VAR56[1:1];
wire VAR15 = VAR13;
wire VAR8 = VAR2;
wire VAR51 = VAR77;
wire VAR113 = VAR83;
wire [1... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_project/fifo_32x64a/fifo_32x64a_bb.v | 6,012 | module MODULE1 (
VAR5,
VAR3,
VAR1,
VAR8,
VAR2,
VAR9,
VAR6,
VAR4,
VAR7);
input VAR5;
input [31:0] VAR3;
input VAR1;
input VAR8;
input VAR2;
input VAR9;
output [31:0] VAR6;
output VAR4;
output VAR7;
tri0 VAR5;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2/sky130_fd_sc_hdll__nor2.functional.pp.v | 1,801 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR10 ,
VAR4,
VAR2,
VAR5 ,
VAR13
);
output VAR6 ;
input VAR9 ;
input VAR10 ;
input VAR4;
input VAR2;
input VAR5 ;
input VAR13 ;
wire VAR8 ;
wire VAR11;
nor VAR7 (VAR8 , VAR9, VAR10 );
VAR1 VAR12 (VAR11, VAR8, VAR4, VAR2);
buf VAR3 (VAR6 , VAR11 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/pickle_40/bsg_mem/bsg_mem_2r1w_sync.v | 4,326 | if (VAR19 == VAR14 && VAR47 == VAR2) \
begin: VAR44 \
VAR45 \
VAR31 \
(.VAR29 ( VAR29 ) \
,.VAR10 ( VAR10 ) \
,.VAR42 ( VAR42 ) \
,.VAR4( VAR4 ) \
,.VAR25( VAR25 ) \
,.VAR49 ( VAR36 ) \
,.VAR40( VAR7 ) \
,.VAR39( VAR6 ) \
); \
VAR45 \
VAR33 \
(.VAR29 ( VAR29 ) \
,.VAR10 ( VAR10 ) \
,.VAR42 ( VAR42 ) \
,.VAR4( VAR4 ) \
... | bsd-3-clause |
seyedmaysamlavasani/GorillaPP | chisel/Gorilla++/verilog/problems/Top.v | 50,144 | module MODULE8(
input VAR317,
output VAR79,
input VAR41);
wire VAR329;
assign VAR79 = VAR329;
assign VAR329 = VAR317 ? 1'h0 : 1'h1;
endmodule
module MODULE1(
input VAR317,
output VAR79,
input VAR41);
wire VAR329;
assign VAR79 = VAR329;
assign VAR329 = VAR317 ? 1'h0 : 1'h1;
endmodule
module MODULE4(
input VAR317,
output... | bsd-3-clause |
mgohde/MiniMicroII | RevisionB/instructioncache.v | 2,240 | module MODULE1(VAR1, addr, clk, rst, VAR5, VAR3, VAR8, VAR2);
input [15:0] VAR1;
input [31:0] addr;
input clk;
input rst;
input VAR5;
output [63:0] VAR3;
output [31:0] VAR8;
output VAR2;
reg [31:0] VAR4;
assign VAR8=VAR4;
reg [63:0] VAR9 [0:63];
reg [31:0] VAR12 [0:63];
wire [5:0] VAR6;
VAR11 VAR13(addr, VAR6);
wire [3... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211a/sky130_fd_sc_hd__o211a_1.v | 2,348 | module MODULE2 (
VAR9 ,
VAR8 ,
VAR4 ,
VAR10 ,
VAR5 ,
VAR3,
VAR1,
VAR7 ,
VAR11
);
output VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR10 ;
input VAR5 ;
input VAR3;
input VAR1;
input VAR7 ;
input VAR11 ;
VAR6 VAR2 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VA... | apache-2.0 |
siamumar/TinyGarbled | circuit_synthesis/aes/ShiftRows.v | 2,291 | module MODULE1(
VAR101,
VAR28);
input [127:0] VAR101;
output [127:0] VAR28;
wire [127:0] VAR83;
wire [127:0] VAR18;
generate
genvar VAR81;
for (VAR81 = 0; VAR81 < 128; VAR81 = VAR81 + 1) begin:VAR64
assign VAR83[127-VAR81] = VAR101[VAR81];
assign VAR28[VAR81] = VAR18[127-VAR81];
end
endgenerate
wire VAR85, VAR5, VAR54,... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/hostController/sendpacket.v | 11,636 | module MODULE1 (VAR19, VAR56, VAR26, VAR32, VAR58, VAR31, VAR29, VAR1, VAR57, clk, VAR9, VAR20, VAR60, VAR18, VAR6, rst, VAR23, VAR10);
input VAR26;
input VAR32;
input [3:0] VAR29;
input [6:0] VAR1;
input [3:0] VAR57;
input clk;
input [7:0] VAR9;
input VAR20;
input VAR6;
input rst;
input VAR10;
output [7:0] VAR19;
outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ai/sky130_fd_sc_lp__o21ai_2.v | 2,261 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR3 ,
VAR5 ,
VAR8,
VAR6,
VAR10 ,
VAR9
);
output VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR8;
input VAR6;
input VAR10 ;
input VAR9 ;
VAR7 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
alexforencich/xfcp | lib/eth/example/S10DX_DK/fpga_10g/rtl/avst2axis.v | 2,663 | module MODULE1 #(
parameter VAR7 = 8,
parameter VAR19 = (VAR7/8),
parameter VAR22 = (VAR7>8),
parameter VAR10 = VAR1(VAR19),
parameter VAR6 = 0
)
(
input wire clk,
input wire rst,
output wire VAR20,
input wire VAR8,
input wire [VAR7-1:0] VAR5,
input wire VAR15,
input wire VAR2,
input wire [VAR10-1:0] VAR17,
input wire ... | mit |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_auto_cc_0/synth/bd_auto_cc_0.v | 16,252 | module MODULE1 (
VAR41,
VAR33,
VAR61,
VAR77,
VAR44,
VAR45,
VAR87,
VAR83,
VAR115,
VAR55,
VAR71,
VAR54,
VAR78,
VAR72,
VAR88,
VAR28,
VAR70,
VAR111,
VAR91,
VAR21,
VAR6,
VAR98,
VAR9,
VAR5,
VAR62,
VAR19,
VAR75,
VAR2,
VAR35,
VAR110,
VAR4,
VAR58,
VAR81,
VAR67,
VAR34,
VAR48,
VAR82,
VAR11,
VAR12,
VAR47,
VAR49,
VAR106,
VAR15,
VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4b/sky130_fd_sc_ls__nand4b_1.v | 2,311 | module MODULE2 (
VAR3 ,
VAR4 ,
VAR8 ,
VAR7 ,
VAR6 ,
VAR9,
VAR2,
VAR11 ,
VAR5
);
output VAR3 ;
input VAR4 ;
input VAR8 ;
input VAR7 ;
input VAR6 ;
input VAR9;
input VAR2;
input VAR11 ;
input VAR5 ;
VAR10 VAR1 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2oi/sky130_fd_sc_hd__a2bb2oi.pp.symbol.v | 1,457 | module MODULE1 (
input VAR9,
input VAR2,
input VAR1 ,
input VAR6 ,
output VAR7 ,
input VAR3 ,
input VAR8,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2b/sky130_fd_sc_hs__nand2b.functional.v | 1,824 | module MODULE1 (
VAR7,
VAR2,
VAR6 ,
VAR8 ,
VAR9
);
input VAR7;
input VAR2;
output VAR6 ;
input VAR8 ;
input VAR9 ;
wire VAR6 VAR11 ;
wire VAR1 ;
wire VAR3;
not VAR4 (VAR11 , VAR9 );
or VAR10 (VAR1 , VAR11, VAR8 );
VAR5 VAR13 (VAR3, VAR1, VAR7, VAR2);
buf VAR12 (VAR6 , VAR3 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4.functional.pp.v | 1,751 | module MODULE1( VAR6, VAR17, VAR21, VAR28, VAR3, VAR5, VAR14, VAR10, VAR9 );
input VAR28, VAR21, VAR6, VAR3, VAR17, VAR14, VAR10, VAR9;
output VAR5;
not VAR2( VAR4, VAR3 );
wire VAR22;
not VAR15( VAR22, VAR21 );
wire VAR18;
not VAR19( VAR18, VAR6 );
wire VAR25;
and VAR12( VAR25, VAR22, VAR18 );
wire VAR1;
not VAR24( VA... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_5/ab882192/src/SCFIFO_128x64_withCount.v | 2,701 | module MODULE1
(
input VAR5 ,
input VAR8 ,
input [127:0] VAR9 ,
input VAR4 ,
output VAR11 ,
output [127:0] VAR13 ,
input VAR2 ,
output VAR6 ,
output [5:0] VAR15
);
VAR17
VAR3
(
.clk (VAR5 ),
.VAR1 (VAR8 ),
.din (VAR9 ),
.VAR12 (VAR4 ),
.VAR16 (VAR11 ),
.dout (VAR13 ),
.VAR14 (VAR2 ),
.VAR10 (VAR6 ),
.VAR7 (VAR15 )
);
e... | gpl-3.0 |
AmeerAbdelhadi/Switched-Multiported-RAM | mpram_lvt.v | 12,759 | module MODULE1
localparam VAR47 = VAR24+VAR45 ; localparam VAR27 = VAR43+VAR37 ; localparam VAR39 = VAR28(VAR3) ; localparam VAR51 = VAR28(VAR47) ; localparam VAR10 = (VAR4=="VAR13")?VAR47:VAR51;
reg [VAR39 -1:0] VAR7 [VAR47-1:0] ; reg [VAR53 -1:0] VAR31 [VAR47-1:0] ; wire [VAR53*VAR27-1:0] VAR34 [VAR47-1:0] ; reg [VAR... | bsd-3-clause |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/counter.v | 3,287 | module MODULE1
parameter VAR4 = 10,
parameter VAR5 = 0)
(
input VAR2,
input VAR1,
input VAR10,
output [VAR6(VAR7+1)-1:0] VAR8
);
wire VAR11;
reg [VAR6(VAR7+1)-1:0] VAR9;
reg [VAR6(VAR7+1)-1:0] VAR3;
assign VAR11 = VAR10 & (VAR4 > VAR3);
assign VAR8 = VAR3;
always @(posedge VAR2) begin
if(VAR1) begin
VAR3 <= VAR5[VAR6(V... | gpl-3.0 |
cpulabs/mist1032sa | src/core/scheduler1/scheduler1_commit_entry.v | 5,672 | module MODULE1 #(
parameter VAR34 = 6'h00
)(
input wire VAR37,
input wire VAR31,
input wire VAR41,
input wire VAR20,
input wire [5:0] VAR13,
input wire VAR22,
input wire VAR54,
input wire VAR30,
input wire [3:0] VAR35,
input wire [5:0] VAR33,
input wire [4:0] VAR40,
input wire VAR28,
input wire VAR6,
input wire VAR53,
... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3b/sky130_fd_sc_lp__nand3b.blackbox.v | 1,301 | module MODULE1 (
VAR5 ,
VAR3,
VAR1 ,
VAR2
);
output VAR5 ;
input VAR3;
input VAR1 ;
input VAR2 ;
supply1 VAR4;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
AngelTerrones/ADA | rtl/ada_core.v | 20,938 | module MODULE1(
input clk,
input rst,
input [31:0] VAR231, input [31:0] VAR198, input VAR25, output [31:0] VAR114, output [31:0] VAR213, output VAR123, output VAR185, input [31:0] VAR11, input VAR61, output [31:0] VAR220, output VAR60, output VAR157, input [31:0] VAR147, input VAR127, output [31:0] VAR125, output [31:0... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_01_a/hdl/verilog/user_logic.v | 13,942 | module MODULE1
(
VAR53,
VAR43,
VAR46,
VAR16,
VAR28,
VAR18,
VAR55,
VAR3,
VAR12,
VAR48,
VAR57,
VAR62,
VAR19,
VAR49,
VAR6,
VAR11,
VAR23,
VAR45,
VAR33,
VAR60,
VAR20,
VAR32,
VAR25,
VAR14,
VAR31,
VAR37,
VAR39,
VAR9,
VAR59,
VAR56,
VAR26,
VAR8,
VAR41,
VAR13,
VAR5,
VAR40,
VAR50, VAR7, VAR15, VAR51, VAR4, VAR44, VAR27, VAR2, VAR... | bsd-2-clause |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/NIOSCar.v | 8,675 | module MODULE1(
VAR31,
VAR36,
VAR2,
VAR81,
VAR30,
VAR21,
VAR10,
VAR11,
VAR62,
VAR3,
VAR83,
VAR90,
VAR24,
VAR9,
VAR75,
VAR84,
VAR87,
VAR78,
VAR55,
VAR53,
VAR16,
VAR71,
VAR23,
VAR85,
VAR18,
VAR40,
VAR45,
VAR60,
VAR25,
VAR69,
VAR88,
VAR47,
VAR7,
VAR4,
VAR5,
VAR8,
VAR28,
VAR37,
VAR26,
VAR35,
VAR34,
VAR49,
VAR14,
VAR91
);
i... | gpl-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v | 13,538 | module MODULE1(
clk, rst,
VAR32, VAR12, VAR48,
VAR55,
VAR34,
VAR68,
VAR16,
VAR21,
VAR75,
VAR52,
VAR63,
VAR74,
VAR57,
VAR43,
VAR72,
VAR46,
VAR65,
VAR73,
VAR47,
VAR22,
VAR7,
VAR18,
VAR29,
VAR50,
VAR10,
VAR44,
VAR35,
VAR70,
VAR58,
VAR14,
VAR26,
VAR20,
VAR67,
VAR24,
VAR41,
VAR64, VAR49, VAR38,
VAR56, VAR17, VAR31, VAR11,
V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr_4.v | 2,112 | module MODULE2 (
VAR1 ,
VAR3,
VAR2 ,
VAR6 ,
VAR7
);
input VAR1 ;
input VAR3;
input VAR2 ;
input VAR6 ;
input VAR7 ;
VAR5 VAR4 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE2 ();
supply1 VAR1 ;
supply1 VAR3;
supply0 VAR2 ;
supply1 VAR6 ;
supply0 VAR7 ;
VAR5 VAR4 ();
endmodul... | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/HDLNeuralNetwork/DecoEscrituraRegistros.v | 2,757 | module MODULE1(VAR1,VAR3,VAR4,VAR2
);
input VAR3;
input [8:0] VAR1;
output [21:0] VAR2 ;
output VAR4;
assign VAR4 = (VAR1==9'h08C) ? 1'b1 : 1'b0 ;
assign VAR2[0] = (VAR1==9'h00C)&VAR3 ? 1'b1 : 1'b0 ; assign VAR2[1] = (VAR1==9'h010)&VAR3 ? 1'b1 : 1'b0 ; assign VAR2[2] = (VAR1==9'h014)&VAR3 ? 1'b1 : 1'b0 ; assign VAR2[3]... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/89a153629b0ea294/ip_design_processing_system7_0_0_stub.v | 5,531 | module MODULE1(VAR15, VAR6, VAR24, VAR7,
VAR17, VAR42, VAR47, VAR26, VAR71, VAR73,
VAR25, VAR44, VAR58, VAR29,
VAR59, VAR23, VAR10, VAR74, VAR4,
VAR34, VAR3, VAR16, VAR72, VAR28,
VAR38, VAR41, VAR46, VAR54,
VAR2, VAR1, VAR8, VAR21, VAR22,
VAR48, VAR49, VAR69, VAR60, VAR63,
VAR39, VAR52, VAR9, VAR57, VAR40,
VAR36, VAR75... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probe_p/sky130_fd_sc_hvl__probe_p.functional.v | 1,268 | module MODULE1 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
wire VAR5;
buf VAR3 (VAR5, VAR4 );
buf VAR1 (VAR2 , VAR5 );
endmodule | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Video_In/synthesis/submodules/altera_up_video_decoder_add_endofpacket.v | 5,718 | module MODULE1 (
clk,
reset,
VAR9,
VAR5,
VAR7,
VAR14,
VAR8,
VAR4,
VAR13,
VAR1,
VAR6,
VAR3
);
parameter VAR15 = 15;
input clk;
input reset;
input [VAR15: 0] VAR9;
input VAR5;
input VAR7;
input VAR14;
input VAR8;
output VAR4;
output reg [VAR15: 0] VAR13;
output reg VAR1;
output reg VAR6;
output reg VAR3;
wire VAR11;
reg ... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type_block.v | 1,159 | module MODULE1
(
VAR3,
VAR1
);
input signed [31:0] VAR3; output signed [17:0] VAR1;
wire signed [17:0] VAR2;
assign VAR2 = VAR3[31:14];
assign VAR1 = VAR2;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fa/sky130_fd_sc_hd__fa.pp.blackbox.v | 1,303 | module MODULE1 (
VAR1,
VAR5 ,
VAR2 ,
VAR4 ,
VAR6 ,
VAR8,
VAR9,
VAR3 ,
VAR7
);
output VAR1;
output VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR6 ;
input VAR8;
input VAR9;
input VAR3 ;
input VAR7 ;
endmodule | apache-2.0 |
manu3193/TextEditor | SVN/Altera_UP_PS2_Command_Out.v | 8,985 | module MODULE1 (
clk,
reset,
VAR28,
VAR16,
VAR14,
VAR21,
VAR11,
VAR9,
VAR22,
VAR5
);
parameter VAR23 = 5050;
parameter VAR25 = 13;
parameter VAR18 = 13'h0001;
parameter VAR2 = 750000;
parameter VAR20 = 20;
parameter VAR29 = 20'h00001;
parameter VAR33 = 100000;
parameter VAR3 = 17;
parameter VAR31 = 17'h00001;
input clk... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_ram_contro.v | 76,816 | module MODULE1 (
clk ,
VAR239 ,
VAR78 ,
VAR5 ,
VAR254 ,
VAR84 ,
VAR153 ,
VAR249 ,
VAR109 ,
VAR2 ,
VAR26 , VAR15 , VAR201 , VAR141 , VAR82 ,
VAR132 ,
VAR20 ,
VAR131 ,
VAR216 ,
VAR25 ,
VAR171 ,
VAR227 , VAR77 ,
VAR81 ,
VAR203 , VAR230 , VAR228 , VAR205 , VAR146 , VAR51 , VAR13 ,
VAR129 , VAR48 , VAR11 , VAR73 ,
VAR219 ,
... | gpl-3.0 |
Marcoslz22/Tercer_Proyecto | PICOBLAZE.v | 1,398 | module MODULE1(
input interrupt,
input VAR3,
input clk,
input [7:0]VAR10,
input rst,
output VAR14,
output VAR2,
output VAR6,
output [7:0]VAR8,
output [7:0]VAR13,
output VAR16
);
wire VAR5;
wire [7:0] VAR11,VAR1;
wire [11:0] address;
wire VAR7;
wire [17:0] VAR12;
wire reset;
assign reset= VAR7 || rst;
VAR4 VAR4 (
.addre... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputisolatch/sky130_fd_sc_lp__inputisolatch.blackbox.v | 1,347 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR1
);
output VAR3 ;
input VAR5 ;
input VAR1;
supply1 VAR7;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/chris.sdram.ok/db/ip/soc_design/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR1,
VAR2,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR1;
input VAR2;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1500364641 : 255;
endmodule | gpl-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_int_div32s.v | 4,790 | module MODULE1 (
enable,
VAR5,
VAR16,
VAR15,
VAR3,
VAR12);
input enable;
input VAR5;
input [31:0] VAR16;
input [31:0] VAR15;
output [31:0] VAR3;
output [31:0] VAR12;
wire [31:0] VAR8;
wire [31:0] VAR9;
wire [31:0] VAR12 = VAR8[31:0];
wire [31:0] VAR3 = VAR9[31:0];
VAR7 VAR17 (
.VAR5 (VAR5),
.VAR4 (enable),
.VAR16 (VAR1... | mit |
lvd2/ngs | fpga/obsolete/fpgaC_release/ports/ports.v | 12,702 | module MODULE1(
din, dout, VAR25, VAR63,
VAR82,VAR50,VAR52,VAR89,
VAR18, VAR81, VAR102,
VAR5, VAR51,
VAR38, VAR24,
VAR106, VAR34,
VAR54, VAR58,
VAR75, VAR105,
VAR70, VAR80,
VAR91, VAR40,
VAR76, VAR86, VAR108, VAR36,
VAR44, VAR90,
VAR97,
VAR71,
VAR43, VAR39,
VAR64,
VAR104,
VAR84,
VAR62,
VAR72, VAR10,
VAR79,
VAR65,
VAR19... | gpl-3.0 |
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