repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/conb/sky130_fd_sc_hd__conb.symbol.v | 1,270 | module MODULE1 (
output VAR6,
output VAR4
);
supply1 VAR5;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/nios_system_nios2_qsys_0_jtag_debug_module_sysclk.v | 7,288 | module MODULE1 (
clk,
VAR22,
VAR11,
VAR14,
VAR23,
VAR15,
VAR5,
VAR29,
VAR17,
VAR18,
VAR6,
VAR8,
VAR19,
VAR31,
VAR16,
VAR33,
VAR7,
VAR21,
VAR3
)
;
output [ 37: 0] VAR15;
output VAR5;
output VAR29;
output VAR17;
output VAR18;
output VAR6;
output VAR8;
output VAR19;
output VAR31;
output VAR16;
output VAR33;
output VAR7;
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211o/sky130_fd_sc_ms__a211o.behavioral.v | 1,539 | module MODULE1 (
VAR4 ,
VAR9,
VAR5,
VAR7,
VAR6
);
output VAR4 ;
input VAR9;
input VAR5;
input VAR7;
input VAR6;
supply1 VAR10;
supply0 VAR12;
supply1 VAR3 ;
supply0 VAR13 ;
wire VAR14 ;
wire VAR11;
and VAR1 (VAR14 , VAR9, VAR5 );
or VAR8 (VAR11, VAR14, VAR6, VAR7);
buf VAR2 (VAR4 , VAR11 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/temac_v6/example_design/v6_emac_v1_3_locallink.v | 15,743 | module MODULE1
(
VAR118,
VAR54,
VAR57,
VAR27,
VAR99,
VAR108,
VAR77,
VAR107,
VAR103,
VAR75,
VAR52,
VAR70,
VAR114,
VAR40,
VAR39,
VAR95,
VAR92,
VAR120,
VAR112,
VAR36,
VAR50,
VAR46,
VAR76,
VAR74,
VAR66,
VAR104,
VAR100,
VAR8,
VAR86,
VAR12,
VAR2,
VAR72,
VAR105,
VAR15,
VAR21,
VAR85,
VAR59,
VAR53,
VAR49,
VAR67,
VAR56,
VAR51,
V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv.pp.blackbox.v | 1,225 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR4,
VAR1,
VAR2 ,
VAR5
);
output VAR3 ;
input VAR6 ;
input VAR4;
input VAR1;
input VAR2 ;
input VAR5 ;
endmodule | apache-2.0 |
kgugala/axi-coprocessor-interface-hw | project_1.srcs/sources_1/edk/module_1/hdl/module_1_stub.v | 5,823 | module MODULE1
(
VAR17,
VAR3,
VAR20,
VAR13,
VAR11,
VAR21,
VAR23,
VAR9,
VAR4,
VAR18,
VAR19,
VAR12,
VAR6,
VAR5,
VAR1,
VAR2,
VAR8,
VAR14,
VAR16,
VAR15,
VAR10,
VAR22,
VAR25,
VAR24
);
inout [53:0] VAR17;
input VAR3;
input VAR20;
input VAR13;
inout VAR11;
inout VAR21;
inout VAR23;
inout VAR9;
inout VAR4;
inout VAR18;
output ... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/acl_fp_sin_s5.v | 1,183 | module MODULE1 (
enable,
VAR6,
VAR5,
VAR8);
input enable;
input VAR6;
input [31:0] VAR5;
output [31:0] VAR8;
wire [31:0] VAR2;
wire [31:0] VAR8 = VAR2[31:0];
VAR9 VAR4(
.en (enable),
.clk (VAR6),
.VAR1 (VAR5),
.VAR7 (VAR2),
.VAR3(1'b0));
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3b/sky130_fd_sc_ls__nand3b_1.v | 2,229 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR9 ,
VAR1 ,
VAR10,
VAR2,
VAR5 ,
VAR8
);
output VAR4 ;
input VAR7 ;
input VAR9 ;
input VAR1 ;
input VAR10;
input VAR2;
input VAR5 ;
input VAR8 ;
VAR6 VAR3 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/mig_mig.v | 52,736 | module MODULE1 #
(
parameter VAR305 = 0,
parameter VAR93 = 3,
parameter VAR310 = 1,
parameter VAR13 = 10,
parameter VAR342 = 1,
parameter VAR148 = 1,
parameter VAR30 = 1,
parameter VAR102 = 5,
parameter VAR15 = 4,
parameter VAR340 = 8,
parameter VAR221 = 2,
parameter VAR286 = 16,
parameter VAR12 = 2,
parameter VAR121 =... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtn/sky130_fd_sc_lp__dlrtn.functional.v | 1,806 | module MODULE1 (
VAR4 ,
VAR2,
VAR10 ,
VAR8
);
output VAR4 ;
input VAR2;
input VAR10 ;
input VAR8 ;
wire VAR13 ;
wire VAR3;
wire VAR6 ;
not VAR9 (VAR13 , VAR2 );
not VAR11 (VAR3, VAR8 );
VAR12 VAR5 VAR1 (VAR6 , VAR10, VAR3, VAR13);
buf VAR7 (VAR4 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/buf/sky130_fd_sc_hvl__buf.functional.pp.v | 1,755 | module MODULE1 (
VAR7 ,
VAR12 ,
VAR9,
VAR6,
VAR2 ,
VAR10
);
output VAR7 ;
input VAR12 ;
input VAR9;
input VAR6;
input VAR2 ;
input VAR10 ;
wire VAR3 ;
wire VAR4;
buf VAR11 (VAR3 , VAR12 );
VAR8 VAR5 (VAR4, VAR3, VAR9, VAR6);
buf VAR1 (VAR7 , VAR4 );
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/moon_bb.v | 4,968 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
prernaa/CPUVerilog | ex_mem.v | 3,030 | module MODULE1(clk,VAR6, VAR4, VAR42, VAR21,
VAR43,VAR32, flag, VAR20, VAR5, VAR44, VAR7,
VAR30, VAR17, VAR22, VAR39, VAR11,
VAR10, VAR38, VAR37, VAR24, VAR9, VAR35,
VAR34,VAR29, VAR14, VAR19,
VAR3, VAR27,
VAR28, VAR26
);
input clk;
input VAR6;
input VAR4;
input VAR42;
input VAR43;
input VAR21;
input [15:0] VAR32;
inpu... | mit |
horia141/bachelor-thesis | prj/components/Rotary/Rotary.v | 8,678 | module MODULE1(VAR5,reset,VAR33,VAR18,VAR19,VAR32,VAR10);
input wire VAR5;
input wire reset;
input wire [11:0] VAR33;
input wire VAR18;
input wire [1:0] VAR19;
output wire VAR32;
output wire VAR10;
reg [1:0] VAR25;
reg VAR22;
reg VAR4;
reg VAR15;
reg VAR34;
wire [3:0] VAR26;
wire VAR2;
wire VAR17;
reg [256*8-1:0] VAR35... | mit |
miamiasheep/nctu-dlab-99 | lab5/PGM.v | 3,111 | module MODULE1(
input VAR14, VAR2, VAR10, VAR19,
input [1:0] VAR21,
output reg VAR9,
output reg [1:0] VAR27,
output reg [3:0] VAR5,
output reg [3:0] VAR20
);
parameter VAR3 = 10;
parameter VAR7 = 3'b000;
parameter VAR16 = 3'b001;
parameter VAR17 = 3'b010;
parameter VAR12 = 3'b011;
parameter VAR13 = 3'b100;
parameter VA... | gpl-3.0 |
Jawanga/ece385lab8 | lab8_usb/db/altera_mult_add_s1u2.v | 18,123 | module MODULE1
(
VAR264,
VAR127,
VAR140,
VAR11,
VAR217) ;
input VAR264;
input VAR127;
input [15:0] VAR140;
input [15:0] VAR11;
output [15:0] VAR217;
tri0 VAR264;
tri1 VAR127;
tri0 [15:0] VAR140;
tri0 [15:0] VAR11;
wire [15:0] VAR316;
VAR235 VAR87
(
.VAR264(VAR264),
.VAR256(),
.VAR127(VAR127),
.VAR140(VAR140),
.VAR11(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32ai/sky130_fd_sc_ls__o32ai.pp.symbol.v | 1,398 | module MODULE1 (
input VAR8 ,
input VAR1 ,
input VAR6 ,
input VAR7 ,
input VAR9 ,
output VAR4 ,
input VAR2 ,
input VAR3,
input VAR5,
input VAR10
);
endmodule | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_m00_data_fifo_0/synth/zc702_m00_data_fifo_0.v | 15,930 | module MODULE1 (
VAR36,
VAR78,
VAR42,
VAR49,
VAR87,
VAR32,
VAR108,
VAR93,
VAR67,
VAR71,
VAR37,
VAR51,
VAR86,
VAR50,
VAR4,
VAR26,
VAR17,
VAR70,
VAR85,
VAR9,
VAR28,
VAR62,
VAR44,
VAR72,
VAR58,
VAR23,
VAR10,
VAR29,
VAR57,
VAR97,
VAR53,
VAR47,
VAR38,
VAR91,
VAR25,
VAR40,
VAR73,
VAR109,
VAR75,
VAR3,
VAR31,
VAR114,
VAR107,
V... | mit |
lokisz/openzcore | pippo-0.9/rtl/verilog/imx_umc.v | 10,149 | module MODULE1(
clk, rst,
VAR21, VAR37,
VAR22, VAR28, VAR32, VAR49, VAR4,
VAR10, VAR51, VAR17, VAR39, VAR54,
VAR30, VAR19, VAR11,
VAR56, VAR47, VAR50, VAR31,
VAR6
);
parameter VAR27 = 32;
input clk;
input rst;
input [31:0] VAR21;
input VAR37;
output [31:0] VAR49;
output VAR28;
output VAR32;
output [31:0] VAR4;
output V... | gpl-2.0 |
efabless/openlane | designs/ldpcenc/src/ldpcenc.v | 52,796 | module MODULE1 (
input clk, input VAR24, input VAR18,
input VAR39, input VAR51, input [3:0] VAR9, input [26:0] VAR100, output VAR12, output VAR25, output VAR38, output [26:0] VAR7 );
wire [1:0] state;
wire [3:0] VAR50;
wire [4:0] VAR99;
wire [1:0] VAR61;
wire [1:0] VAR98;
wire VAR97;
wire VAR67;
wire [26:0] VAR74;
wire... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/controller/round_robin_arb.v | 7,537 | module MODULE1
parameter VAR13 = 100,
parameter VAR14 = 3
)
(
VAR18, VAR1,
clk, rst, req, VAR4, VAR3, VAR5
);
input clk;
input rst;
input [VAR14-1:0] req;
wire [VAR14-1:0] VAR15;
reg [VAR14*2-1:0] VAR9;
always @(VAR15)
VAR9 = {VAR15, VAR15};
reg [VAR14*2-1:0] VAR2;
always @(req) VAR2 = {req, req};
reg [VAR14-1:0] VAR10... | lgpl-3.0 |
Gilberto-Lopez/Arquitectura-Computadoras | Practica2/mult4.v | 2,233 | module MODULE1(
input VAR47,
input VAR46,
input VAR61,
input VAR4,
input VAR5,
input VAR18,
input VAR52,
input VAR45,
output VAR71,
output VAR7,
output VAR35,
output VAR30,
output VAR22,
output VAR3,
output VAR57,
output VAR59
);
wire VAR31;
wire VAR41;
wire VAR10;
wire VAR26;
wire VAR16;
wire VAR25;
wire VAR50;
wire V... | lgpl-3.0 |
lee-dohm/atom-linguist | samples/Verilog/sign_extender.v | 1,616 | module MODULE1
parameter
VAR6 = 8,
VAR2 = 16
)
(
input [VAR6-1:0] VAR4,
output reg [VAR2-1:0] VAR3
);
wire [VAR2-VAR6-1:0] VAR5;
generate
genvar VAR7;
for (VAR7 = 0; VAR7 < VAR2-VAR6; VAR7 = VAR7 + 1) begin : VAR1
assign VAR5[VAR7] = (VAR4[VAR6-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
VAR3 = {VAR5,VAR4};
end... | mit |
alanachtenberg/CSCE-350 | Project3/ALU_bhav.v | 5,487 | module MODULE1( VAR8, VAR14, VAR6, VAR3, VAR10, VAR7, VAR23, VAR13 );
parameter VAR4 = 32, VAR1 = 4;
input VAR7;
input [VAR1-1:0] VAR6;
input [VAR4-1:0] VAR8, VAR14;
output [VAR4-1:0] VAR3;
reg [VAR4-1:0] VAR3, VAR2;
output VAR23, VAR10, VAR13;
reg VAR23, VAR10, VAR13;
always @(VAR6 or VAR8 or VAR14 or VAR7)
begin
case... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_2.behavioral.pp.v | 1,388 | module MODULE1( VAR5, VAR4, VAR7, VAR10, VAR2, VAR6, VAR9 );
input VAR5, VAR4, VAR7, VAR10;
inout VAR6, VAR9;
output VAR2;
VAR1 VAR8(.VAR5(VAR5),.VAR4(VAR4),.VAR7(VAR7),.VAR10(VAR10),.VAR2(VAR2),.VAR6(VAR6),.VAR9(VAR9));
VAR1 VAR3(.VAR5(VAR5),.VAR4(VAR4),.VAR7(VAR7),.VAR10(VAR10),.VAR2(VAR2),.VAR6(VAR6),.VAR9(VAR9)); | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_adcfifo/axi_adcfifo.v | 10,092 | module MODULE1 (
VAR38,
VAR46,
VAR10,
VAR66,
VAR86,
VAR55,
VAR35,
VAR11,
VAR32,
VAR45,
VAR19,
VAR59,
VAR44,
VAR82,
VAR69,
VAR13,
VAR54,
VAR77,
VAR34,
VAR67,
VAR20,
VAR3,
VAR27,
VAR75,
VAR84,
VAR48,
VAR79,
VAR22,
VAR68,
VAR7,
VAR62,
VAR41,
VAR28,
VAR81,
VAR1,
VAR78,
VAR6,
VAR14,
VAR39,
VAR52,
VAR72,
VAR16,
VAR18,
VAR40,... | gpl-3.0 |
rkrajnc/minimig-de1 | lib/altera/cycloneiv_atoms.v | 257,486 | module MODULE1(
primitive VAR11 (VAR1, VAR9, VAR7, VAR13, VAR19, VAR10, VAR18);
input VAR7;
input VAR19;
input VAR10;
input VAR13;
input VAR9;
input VAR18;
output VAR1; reg VAR1;
VAR2 VAR1 = 1'b0;
VAR14
(??) ? ? 1 1 ? : ? : -; VAR20 ? ? 1 1 ? : ? : -; 1 1 (01) 1 1 ? : ? : 1; 1 1 (01) 1 VAR20 ? : ? : 1;
1 1 ? 1 VAR20 ? ... | gpl-3.0 |
olajep/oh | src/adi/hdl/library/xilinx/common/ad_iobuf.v | 2,400 | module MODULE1 #(
parameter VAR1 = 1) (
input [(VAR1-1):0] VAR6,
input [(VAR1-1):0] VAR3,
output [(VAR1-1):0] VAR8,
inout [(VAR1-1):0] VAR2);
genvar VAR5;
generate
for (VAR5 = 0; VAR5 < VAR1; VAR5 = VAR5 + 1) begin: VAR4
assign VAR8[VAR5] = VAR2[VAR5];
assign VAR2[VAR5] = (VAR6[VAR5] == 1'b1) ? 1'VAR7 : VAR3[VAR5];
end... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor3/sky130_fd_sc_lp__xnor3.pp.blackbox.v | 1,302 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR8 ,
VAR6 ,
VAR3,
VAR2,
VAR5 ,
VAR7
);
output VAR4 ;
input VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR3;
input VAR2;
input VAR5 ;
input VAR7 ;
endmodule | apache-2.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | generador_imagenes.v | 7,684 | module MODULE1
(
input wire VAR35,input wire [9:0] VAR43, VAR46,
output wire VAR10, VAR11,
output wire VAR39,
output wire [7:0] VAR36
);
localparam VAR19 = 9'd256; localparam VAR27 = 9'd384; localparam VAR34 = 7'd64; localparam VAR4 = 14'd8192;localparam VAR55 = 7'd64;
localparam VAR26 = 8'd128; localparam VAR50 = 8'd2... | mit |
kkiningh/cs231n-project | src/rtl/MultiplyAccumulateMatrix.v | 2,156 | module MODULE1 #(
parameter VAR19 = 8,
parameter VAR13 = 8,
parameter VAR6 = 16,
parameter VAR5 = 256
) (
input VAR24,
input reset,
input [VAR19-1:0] VAR9 [0:VAR5-1],
input VAR23,
input [VAR13-1:0] VAR25 [0:VAR5-1],
input VAR14
);
genvar VAR1, VAR18;
generate for (VAR1 = 0; VAR1 < VAR5; VAR1 = VAR1 + 1) begin : VAR16
f... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2.behavioral.pp.v | 18,950 | module MODULE1( VAR112, VAR173, VAR165, VAR261, VAR137, VAR20, VAR178, VAR140 );
input VAR261, VAR165, VAR112, VAR137, VAR173;
inout VAR178, VAR140;
output VAR20;
reg VAR250;
VAR15 VAR101(.VAR112(VAR112),.VAR173(VAR173),.VAR165(VAR165),.VAR261(VAR261),.VAR137(VAR137),.VAR20(VAR20),.VAR178(VAR178),.VAR140(VAR140),.VAR25... | apache-2.0 |
AngelTerrones/ADA | rtl/ada_ifid_stage.v | 2,923 | module MODULE1(
input clk, input rst, input [31:0] VAR3, input [31:0] VAR6, input [31:0] VAR2, input VAR10, input VAR5, input VAR9, input VAR4, output reg [31:0] VAR1, output reg [31:0] VAR7, output reg [31:0] VAR8, output reg VAR11 );
always @(posedge clk) begin
VAR1 <= (rst) ? 32'b0 : ((VAR9) ? VAR1 : ((VAR10 | VAR5|... | mit |
silverneko/dsdl | lab1/seg7.v | 1,292 | module MODULE1(VAR8 , VAR5);
input [3:0] VAR8;
output [7:0] VAR5;
reg [7:0] VAR6;
assign VAR5 = VAR6;
always @(VAR8) begin
case (VAR8)
4'b0000: VAR6 = 8'b00111111;
4'b0001: VAR6 = 8'b00000110;
4'b0010: VAR6 = 8'b01011011;
4'b0011: VAR6 = 8'b01001111;
4'b0100: VAR6 = 8'b01100110;
4'b0101: VAR6 = 8'b01101101;
4'b0110: VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s.pp.symbol.v | 1,358 | module MODULE1 (
input VAR4 ,
output VAR3 ,
input VAR6 ,
input VAR5,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/altera_reset_synchronizer.v | 3,479 | module MODULE1
parameter VAR4 = 1,
parameter VAR3 = 2
)
(
input VAR6 ,
input clk,
output VAR5
);
reg [VAR3-1:0] VAR2;
reg VAR1;
generate if (VAR4) begin
always @(posedge clk or posedge VAR6) begin
if (VAR6) begin
VAR2 <= {VAR3{1'b1}};
VAR1 <= 1'b1;
end
else begin
VAR2[VAR3-2:0] <= VAR2[VAR3-1:1];
VAR2[VAR3-1] <= 0;
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtp/sky130_fd_sc_ls__dfrtp.symbol.v | 1,395 | module MODULE1 (
input VAR8 ,
output VAR4 ,
input VAR7,
input VAR3
);
supply1 VAR5;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii/altera_tse_rgmii_out4.v | 5,146 | module MODULE1 (
VAR8,
VAR7,
VAR11,
VAR6,
VAR12);
input VAR8;
input [3:0] VAR7;
input [3:0] VAR11;
input VAR6;
output [3:0] VAR12;
wire [3:0] VAR4;
wire [3:0] VAR12 = VAR4[3:0];
VAR3 VAR18 (
.VAR6 (VAR6),
.VAR7 (VAR7),
.VAR8 (VAR8),
.VAR11 (VAR11),
.VAR12 (VAR4),
.VAR14 (1'b0),
.VAR1 (1'b1),
.VAR13 (1'b1));
VAR18.VAR5... | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/sync_spram_40W_256D.v | 7,161 | module MODULE1 (
address,
VAR6,
VAR48,
VAR16,
VAR37);
input [7:0] address;
input VAR6;
input [39:0] VAR48;
input VAR16;
output [39:0] VAR37;
tri1 VAR6;
wire [39:0] VAR20;
wire [39:0] VAR37 = VAR20[39:0];
VAR29 VAR12 (
.VAR41 (address),
.VAR50 (VAR6),
.VAR17 (VAR48),
.VAR44 (VAR16),
.VAR33 (VAR20),
.VAR13 (1'b0),
.VAR56... | gpl-3.0 |
sarchar/uart_de0_nano | uart_system.v | 4,467 | module MODULE1
parameter VAR11 = 144000000,
parameter VAR25 = 115200,
parameter VAR4 = 5,
parameter VAR2 = 200,
parameter VAR56 = 1,
parameter VAR40 = 0,
parameter VAR26 = 8
)
(
input VAR20,
input VAR8,
output wire VAR3,
input [7:0] VAR9,
input VAR5,
input VAR55,
output wire [7:0] VAR12,
output wire VAR39,
input VAR50,... | mit |
edgd1er/M1S1_INFO | S1_AEO/TP3_Roulette/ipcore_dir/timer/example_design/timer_exdes.v | 4,338 | module MODULE1
parameter VAR10 = 100
)
( input VAR1,
input VAR13,
output [2:1] VAR3
);
localparam VAR11 = 16;
localparam VAR12 = 2;
genvar VAR14;
wire VAR9 = VAR13;
wire [VAR12:1] VAR2;
wire [VAR12:1] clk;
reg [VAR11-1:0] counter [VAR12:1];
VAR4 VAR8
( .VAR1 (VAR1),
.VAR7 (VAR2[1]),
.VAR6 (VAR2[2]));
assign clk[1] = VA... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/zynq_design_1_system_ila_0_stub.v | 5,502 | module MODULE1(clk, VAR25, VAR8,
VAR46, VAR38, VAR34, VAR52,
VAR31, VAR39, VAR14, VAR42,
VAR36, VAR29, VAR1, VAR16,
VAR2, VAR30, VAR55, VAR53,
VAR51, VAR6, VAR56, VAR59,
VAR33, VAR58, VAR11, VAR60,
VAR35, VAR24, VAR19, VAR54,
VAR4, VAR9, VAR18, VAR40, VAR26,
VAR32, VAR27, VAR57, VAR50,
VAR3, VAR23, VAR7, VAR47,
VAR41, ... | mit |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_switches.v | 1,952 | module MODULE1 (
address,
clk,
VAR4,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input [ 9: 0] VAR4;
input VAR1;
wire VAR6;
wire [ 9: 0] VAR2;
wire [ 9: 0] VAR5;
reg [ 31: 0] VAR3;
assign VAR6 = 1;
assign VAR5 = {10 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR1)
begin
if (VAR... | gpl-3.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/MULT/MULT.v | 3,965 | module MODULE1 (
VAR10,
VAR13);
input [12:0] VAR10;
output [25:0] VAR13;
wire [25:0] VAR3;
wire [25:0] VAR13 = VAR3[25:0];
VAR5 VAR15 (
.VAR2 (VAR10),
.VAR13 (VAR3),
.VAR6 (1'b0),
.VAR11 (1'b1),
.VAR7 (1'b1));
VAR15.VAR9 = 13,
VAR15.VAR1 = "VAR14",
VAR15.VAR16 = 0,
VAR15.VAR12 = "VAR4",
VAR15.VAR8 = 26;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtn/sky130_fd_sc_hs__sdfrtn.behavioral.pp.v | 2,891 | module MODULE1 (
VAR10 ,
VAR31 ,
VAR1 ,
VAR24 ,
VAR4 ,
VAR18 ,
VAR28 ,
VAR27
);
input VAR10 ;
input VAR31 ;
output VAR1 ;
input VAR24 ;
input VAR4 ;
input VAR18 ;
input VAR28 ;
input VAR27;
wire VAR17 ;
wire VAR7 ;
wire VAR15 ;
wire VAR13 ;
reg VAR26 ;
wire VAR16 ;
wire VAR14 ;
wire VAR5 ;
wire VAR22;
wire VAR25 ;
wire... | apache-2.0 |
olgirard/openmsp430 | fpga/OBSOLETE/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v | 6,916 | module MODULE1 (
VAR22,
VAR31, VAR17, VAR38, VAR3, VAR34, VAR37 );
output [15:0] VAR22;
input VAR31; input [13:0] VAR17; input [15:0] VAR38; input VAR3; input [1:0] VAR34; input VAR37;
parameter [14:0] VAR20 = 15'h0190;
parameter VAR6 = 3;
parameter [VAR6-1:0] VAR19 = 'h0,
VAR8 = 'h2,
VAR27 = 'h4,
VAR9 = 'h6;
parameter... | bsd-3-clause |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/Video_System_Video_In_Decoder.v | 8,262 | module MODULE1 (
clk,
reset,
VAR14,
VAR27,
VAR19,
VAR39,
VAR21,
VAR32,
VAR16,
VAR38,
VAR30,
VAR10,
VAR7,
VAR5
);
parameter VAR28 = 7;
parameter VAR4 = 15;
parameter VAR29 = 17;
parameter VAR13 = 1280;
input clk;
input reset;
input VAR14;
input [ 7: 0] VAR27;
input VAR19;
input VAR39;
input VAR21;
output VAR32;
output r... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_dp_macb_l.v | 4,615 | module MODULE1(
VAR22, VAR31, VAR13,
VAR10, VAR16, VAR18,
VAR9, VAR25, VAR32,
VAR11, VAR24, VAR5, VAR23
);
output [129:0] VAR22; output VAR31;
output VAR13;
input VAR10; input VAR16; input VAR18; input VAR9; input VAR25;
input [129:0] VAR32; input [129:0] VAR11;
input VAR24;
input VAR5;
input VAR23;
wire VAR8;
wire [12... | gpl-2.0 |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.v | 3,950 | module MODULE1(
addr,
clk,
din,
dout,
en,
VAR28);
input [10 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input VAR28;
VAR38 #(
.VAR32(11),
.VAR3("0"),
.VAR20(2048),
.VAR21(0),
.VAR10(1),
.VAR4(1),
.VAR23(1),
.VAR42(0),
.VAR14(0),
.VAR45(0),
.VAR35(0),
.VAR15(0),
.VAR40(1),
.VAR41(18),
.VAR18(... | bsd-3-clause |
andrzej-r/wb_sseg_ctrl | rtl/wb_sseg_ctrl.v | 8,174 | module MODULE1
parameter VAR14 = 8,
parameter VAR30 = 8,
parameter VAR26 = 128,
parameter VAR4 = 16,
parameter VAR25 = 4
)
(
input VAR18,
input VAR23,
input VAR2,
input [VAR25-1:0] VAR11,
input [VAR4-1:0] VAR12,
input [3:0] VAR31,
input VAR17,
input VAR8,
input VAR1,
input [2:0] VAR28,
input [1:0] VAR21,
output reg [VA... | bsd-2-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Double_Range.v | 1,730 | module MODULE1
(
VAR5,
VAR3,
VAR8,
VAR6,
VAR4,
VAR1
);
input signed [17:0] VAR5; input signed [17:0] VAR3; input signed [17:0] VAR8; output signed [17:0] VAR6; output signed [17:0] VAR4; output signed [17:0] VAR1;
wire signed [17:0] VAR2 [0:2]; wire signed [17:0] VAR7 [0:2];
assign VAR2[0] = VAR5;
assign VAR2[1] = VAR3... | gpl-3.0 |
SergKolo/msudenver_eet_4020_verilog | Homework_1.v | 1,642 | module MODULE3(VAR2,VAR23,VAR6);
output VAR2;
input VAR23,VAR6;
wire VAR3;
nand VAR20(VAR3,VAR23,VAR6);
nand VAR1(VAR2,VAR3,VAR3);
endmodule
module MODULE4(VAR2,VAR23,VAR6);
output VAR2;
input VAR23,VAR6;
wire VAR4;
wire VAR26;
nand VAR5(VAR4,VAR23,VAR23);
nand VAR24(VAR26,VAR6,VAR6);
nand VAR1(VAR2,VAR4,VAR26);
endmod... | mit |
mdsalman729/flexpret_project | src/uart/UART.v | 6,721 | module MODULE1(VAR17, VAR10, VAR3, VAR15, VAR6, VAR11, VAR8, VAR9, VAR19, VAR2);
parameter VAR16 = 27000000,
VAR1 = 115200,
VAR18 = 8,
VAR7 = 0,
VAR5 = 1;
input VAR17, VAR10;
input [VAR18-1:0] VAR3;
input VAR15;
output VAR6;
output [VAR18-1:0] VAR11;
output VAR8;
input VAR9;
input VAR19;
output VAR2;
VAR14 VAR4( .VAR17... | bsd-3-clause |
tdene/synth_opt_adders | src/pptrees/mappings/GTECH_map.v | 3,846 | module MODULE10
(
VAR29, VAR16
);
output VAR29;
input VAR16;
assign VAR29 = ~VAR16;
endmodule
module MODULE18
(
VAR29, VAR16
);
output VAR29;
input VAR16;
VAR15 MODULE18(.VAR16(VAR16), .VAR3(VAR29));
endmodule
module MODULE9
(
VAR29, VAR16, VAR23
);
output VAR29;
input VAR16, VAR23;
VAR21 MODULE9(.VAR16(VAR16), .VAR23(... | apache-2.0 |
Giako68/SD_RAM_VIDEO | MemoryAdapter.v | 5,138 | module MODULE1
( input VAR15,
output reg [23:0] VAR16,
output reg [15:0] VAR10,
output reg [1:0] VAR7,
input [15:0] VAR1,
output reg VAR19,
output reg VAR2,
input VAR18,
input [24:0] VAR12,
input [31:0] VAR9,
output reg [31:0] VAR17,
input [1:0] VAR4, input VAR5,
input VAR20,
output reg VAR13
);
integer VAR3;
reg [24:0... | gpl-2.0 |
oblivioncth/DE0-Verilog-Processor | src/mux_8to1_16bit.v | 1,536 | module MODULE1(VAR13, VAR17, VAR23, VAR5, VAR6, VAR20, VAR3, VAR22, VAR27, VAR21);
input [0:15] VAR23, VAR5, VAR6, VAR20, VAR3, VAR22, VAR27, VAR21;
input [0:2] VAR17;
output [0:15] VAR13;
VAR11 VAR19(VAR13[0], VAR17, VAR23[0], VAR5[0], VAR6[0], VAR20[0], VAR3[0], VAR22[0], VAR27[0], VAR21[0]);
VAR11 VAR2(VAR13[1], VAR... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/mcm_8.v | 12,864 | module MODULE1(
clk,
rst,
VAR18,
VAR35,
VAR84,
VAR23,
VAR130,
VAR119,
VAR90,
VAR72,
VAR89,
VAR105,
VAR5,
VAR63,
VAR70,
VAR115,
VAR44,
VAR109,
VAR43
);
input clk;
input rst;
input VAR18;
input signed [17:0] VAR35;
input signed [17:0] VAR84;
input signed [17:0] VAR23;
input signed [17:0] VAR130;
input signed [17:0] VAR11... | gpl-3.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/alt_ddrx_bank_timer.v | 61,618 | module MODULE1 #
( parameter
VAR208 = 2,
VAR247 = 4,
VAR87 = 16, VAR102 = 3, VAR10 = "VAR228",
VAR200 = 2, VAR151 = 1,
VAR193 = 1,
VAR51 = 4,
VAR163 = 4,
VAR178 = 8,
VAR134 = 0, VAR40 = 0,
VAR216 = 4,
VAR61 = 4,
VAR48 = 3,
VAR106 = 4,
VAR210 = 10,
VAR209 = 4,
VAR111 = 5,
VAR213 = 6,
VAR56 = 3,
VAR159 = 5,
VAR140 = 4,
V... | apache-2.0 |
peteasa/oh | src/gpio/hdl/gpio.v | 8,280 | module MODULE1 #( parameter integer VAR23 = 24, parameter integer VAR53 = 32, parameter integer VAR12 = 104 )
(
input VAR44, input clk, input VAR24, input [VAR12-1:0] VAR22, output VAR28, output VAR65, output [VAR12-1:0] VAR61, input VAR35, output reg [VAR23-1:0] VAR55, output reg [VAR23-1:0] VAR30, input [VAR23-1:0] V... | mit |
Nrpickle/ECE272 | Lab6_FinalDesign/Section6_SM.v | 1,204 | module MODULE1(
input VAR4,
input VAR7,
output reg [2:0] sel
);
reg [1:0] state;
reg [1:0] VAR8;
reg [3:0] VAR1;
parameter VAR6 = 2'b00; parameter VAR3 = 2'b01; parameter VAR5 = 2'b10; parameter VAR2 = 2'b11;
always @ (posedge VAR4, negedge VAR7)
begin
if(!VAR7)
state <= VAR6;
end
else
state <= VAR8;
end
always @
begin... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2.blackbox.v | 1,252 | module MODULE1 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_fp_sin.v | 1,522 | module MODULE1 (
enable,
VAR12,
VAR8,
VAR9,
VAR11);
input enable;
input VAR12;
input VAR9;
input [31:0] VAR8;
output [31:0] VAR11;
wire [31:0] VAR13;
wire [31:0] VAR11 = VAR13[31:0];
VAR14 VAR5(
.VAR4(VAR12),
.reset(~VAR9),
.enable(enable),
.VAR10(VAR8[31]),
.VAR6(VAR8[30:23]),
.VAR2(VAR8[22:0]),
.VAR3(VAR13[31]),
.VAR... | mit |
mrehkopf/sd2snes | verilog/sd2snes_sgb/main.v | 37,671 | module MODULE1(
output [22:0] VAR73,
output VAR458,
input VAR164,
output VAR405,
input VAR143,
output [21:0] VAR73,
output VAR352,
output VAR338,
output VAR35,
output VAR354,
output VAR456,
input VAR495,
input VAR482,
input [23:0] VAR270,
input VAR88,
input VAR41,
input VAR284,
inout [7:0] VAR412,
input VAR262,
input V... | gpl-2.0 |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/db/comm_pll_altpll.v | 3,973 | module MODULE1
(
clk,
VAR33) ;
output [4:0] clk;
input [1:0] VAR33;
tri0 [1:0] VAR33;
wire [4:0] VAR37;
wire VAR2;
VAR5 VAR26
(
.VAR18(),
.clk(VAR37),
.VAR24(),
.VAR32(VAR2),
.VAR22(VAR2),
.VAR33(VAR33),
.VAR13(),
.VAR15(),
.VAR17(),
.VAR36(),
.VAR7(),
.VAR21()
,
.VAR25(1'b0),
.VAR28(1'b0),
.VAR4(1'b0),
.VAR27(1'b1),
.... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/16-way/src/vivado_ip_dram/phy/mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v | 20,829 | module MODULE1 #
(parameter VAR74 = 3,
parameter VAR92 = 8,
parameter VAR72 = 4,
parameter VAR76 = 100)
(
VAR63, VAR40, VAR13,
VAR38, VAR117, VAR37,
VAR39, VAR54, VAR89, VAR56, VAR41,
VAR102, VAR82, VAR114,
VAR24, VAR17, VAR103, VAR127,
VAR109, VAR10, VAR70,
clk, rst, VAR100, VAR23, VAR64,
VAR115, VAR112,
VAR80, VAR88,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tap/sky130_fd_sc_ms__tap_1.v | 1,877 | module MODULE2 (
VAR3,
VAR6,
VAR1 ,
VAR2
);
input VAR3;
input VAR6;
input VAR1 ;
input VAR2 ;
VAR4 VAR5 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 ();
supply1 VAR3;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR2 ;
VAR4 VAR5 ();
endmodule | apache-2.0 |
ptracton/vscale_soc | rtl/wb_riscvscale/vscale_core.v | 7,696 | module MODULE1(
input clk,
input [VAR53-1:0] VAR20,
output [VAR52-1:0] VAR55,
output VAR23,
output [VAR68-1:0] VAR49,
output [VAR5-1:0] VAR31,
output VAR50,
output [VAR26-1:0] VAR77,
output [VAR35-1:0] VAR13,
output [VAR44-1:0] VAR1,
input [VAR44-1:0] VAR82,
input VAR56,
input [VAR6-1:0] VAR43,
output [VAR52-1:0] VAR42... | mit |
eda-globetrotter/MarcheProcessor | processor/spare/build2/alu_my.v | 331,118 | module MODULE1 (VAR4,VAR2,VAR1,VAR3,VAR7,VAR6,VAR5);
output [0:127] VAR6;
input [0:127] VAR4;
input [0:127] VAR2;
input [0:2] VAR1;
input [0:1] VAR3;
input [0:4] VAR7;
input [15:0] VAR5;
parameter VAR8 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR6;
always @(VAR4 or VAR2 or VAR1 or VAR3 or VAR7 or VAR5)
begi... | mit |
joaocarlos/udlx-verilog | rtl/decode/instruction_decode.v | 9,398 | module MODULE1
parameter VAR28 = 20,
parameter VAR79 = 32,
parameter VAR61 = 32,
parameter VAR25 = 5,
parameter VAR43 = 6,
parameter VAR27 = 6,
parameter VAR17 = 16,
parameter VAR35 = 26
)
(
input clk,
input VAR26,
input en,
input [VAR61-1:0] VAR72,
input [VAR25-1:0] VAR65,
input [VAR25-1:0] VAR48,
input [VAR79-1:0] VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvp/sky130_fd_sc_hd__einvp_2.v | 2,130 | module MODULE2 (
VAR1 ,
VAR5 ,
VAR4 ,
VAR7,
VAR2,
VAR8 ,
VAR3
);
output VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR7;
input VAR2;
input VAR8 ;
input VAR3 ;
VAR6 VAR9 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR1 ,
VAR5 ,
VAR4
);
output VAR1... | apache-2.0 |
bsteinsbo/DE1-SoC-Sound | cores/i2s/i2s_clkctrl_apb.v | 4,804 | module MODULE3 (
input clk, input VAR9, input [4:0] VAR49, input VAR46, input VAR24, input [31:0] VAR15, input VAR18, output reg [31:0] VAR29, output VAR12, input VAR1, input VAR6,
input VAR5,
input VAR43,
input VAR17,
output VAR31, output VAR34, output VAR42,
output VAR14,
output VAR28,
output VAR13
);
reg [31:0] VAR4... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.symbol.v | 1,413 | module MODULE1 (
input VAR6 ,
output VAR3 ,
input VAR2 ,
input VAR1,
input VAR5 ,
input VAR4
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/controller/bank_compare.v | 10,783 | module MODULE1 #
(parameter VAR6 = 3,
parameter VAR61 = 100,
parameter VAR67 = "8",
parameter VAR48 = 12,
parameter VAR12 = 8,
parameter VAR16 = "VAR5",
parameter VAR80 = 2,
parameter VAR7 = 4,
parameter VAR11 = 16)
(
VAR46, VAR52, VAR55, VAR78,
VAR26, VAR49, VAR30, VAR23, VAR39,
VAR44, VAR75, VAR71, VAR35, VAR40,
VAR5... | lgpl-3.0 |
ad510/ee201l_cpu | CpuHardcoded.v | 2,261 | module MODULE1
(clk, reset, VAR2, ack, VAR11, VAR14,
VAR18, VAR25, VAR4, VAR6, VAR10, VAR13);
localparam VAR7 = 32, VAR12 = 8;
input clk, reset, VAR2, ack;
input [3:0] VAR11;
input [7:0] VAR14;
output VAR18;
output [7:0] VAR25;
output [3:0] VAR4;
output [3:0] VAR6;
output [3:0] VAR10;
output [3:0] VAR13;
wire [(VAR7 - ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_4.functional.v | 1,209 | module MODULE1( VAR8, VAR5, VAR7, VAR2 );
input VAR2, VAR8, VAR7;
output VAR5;
wire VAR1;
not VAR4( VAR1, VAR2 );
wire VAR6;
not VAR3( VAR6, VAR8 );
wire VAR9;
not VAR11( VAR9, VAR7 );
and VAR10( VAR5, VAR1, VAR6, VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211oi/sky130_fd_sc_hdll__a211oi.blackbox.v | 1,376 | module MODULE1 (
VAR2 ,
VAR3,
VAR4,
VAR9,
VAR8
);
output VAR2 ;
input VAR3;
input VAR4;
input VAR9;
input VAR8;
supply1 VAR5;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
cliffordwolf/yosys | manual/PRESENTATION_ExAdv/red_or3x1_map.v | 1,244 | module \VAR2 (VAR6, VAR9);
parameter VAR8 = 0;
parameter VAR10 = 0;
parameter VAR7 = 0;
input [VAR10-1:0] VAR6;
output [VAR7-1:0] VAR9;
function integer VAR18;
input integer VAR14, VAR17;
begin
if (VAR14 < VAR17)
VAR18 = VAR14;
end
else
VAR18 = VAR17;
end
endfunction
genvar VAR13;
generate begin
if (VAR10 == 0) begin
a... | isc |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/counter_neg.v | 2,375 | module MODULE1(
input VAR1,
input VAR5,
input VAR4,
output reg VAR2,
output reg [5:0] MODULE1
);
reg VAR3;
always@(posedge VAR1 or negedge VAR5)
begin
if(!VAR5)
begin
VAR2 <= 1'b0;
VAR3 <= 1'b0;
MODULE1 <= 6'd1;
end
else
begin
VAR3 <= VAR4;
case(MODULE1)
6'd1:
begin
MODULE1 <= 6'd2;
end
6'd2:
begin
if(VAR3)
begin
VAR2 ... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/minimig/agnus_copper.v | 17,323 | module MODULE1
(
input clk, input VAR48,
input reset, input VAR13, output VAR52, input VAR24, input VAR27, input VAR5, input VAR1, input [7:0] VAR45, input [8:0] VAR11, input [15:0] VAR47, input [8:1] VAR39, output reg [8:1] VAR31, output reg [20:1] VAR42 );
parameter VAR2 = 9'h080;
parameter VAR36 = 9'h082;
parameter ... | gpl-3.0 |
antmicro/yosys | techlibs/intel/cycloneiv/cells_map.v | 2,302 | module \VAR14 (input VAR4, output VAR12);
VAR22 VAR8 (.VAR20(VAR12), .VAR10(VAR4), .VAR5(1'b0));
endmodule
module \VAR7 (input VAR4, output VAR12);
VAR15 VAR8 (.VAR20(VAR12), .VAR10(VAR4), .VAR24(1'b1));
endmodule
module MODULE3 (VAR2, VAR9);
parameter VAR18 = 0;
parameter VAR1 = 0;
input [VAR18-1:0] VAR2;
output VAR9;... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxbp/sky130_fd_sc_ls__sdfxbp.pp.symbol.v | 1,434 | module MODULE1 (
input VAR1 ,
output VAR7 ,
output VAR9 ,
input VAR6 ,
input VAR8 ,
input VAR4 ,
input VAR5 ,
input VAR2,
input VAR3,
input VAR10
);
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_qpll_wrapper.v | 29,075 | module MODULE1 #
(
parameter VAR11 = "VAR97", parameter VAR46 = "VAR57", parameter VAR134 = "3.0", parameter VAR17 = "VAR127", parameter VAR49 = 0
)
(
input VAR55,
input VAR61,
output VAR5,
output VAR142,
output VAR42,
input VAR111,
input VAR107,
input VAR15,
input [ 7:0] VAR94,
input VAR28,
input [15:0] VAR45,
input V... | gpl-2.0 |
ammelto/FPGAdventure | Adventure/NCenterMaze.v | 3,000 | module MODULE1(VAR3, VAR4, VAR5, VAR6, VAR1);
input VAR3;
input [9:0] VAR4;
input [8:0] VAR5;
input [7:0] VAR1;
output [7:0] VAR6;
reg [7:0] VAR2;
always @(posedge VAR3) begin
if((VAR4 >= 0 && VAR4 <=63) && (
(VAR5 <= 39) ||
(VAR5 >= 120 && VAR5 <= 359) ||
(VAR5 >= 441) ) )
VAR2[7:0] <= VAR1;
end
else if( (VAR4 >= 64 &... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfstp/sky130_fd_sc_hdll__dfstp.behavioral.pp.v | 2,175 | module MODULE1 (
VAR7 ,
VAR12 ,
VAR15 ,
VAR4,
VAR2 ,
VAR13 ,
VAR17 ,
VAR14
);
output VAR7 ;
input VAR12 ;
input VAR15 ;
input VAR4;
input VAR2 ;
input VAR13 ;
input VAR17 ;
input VAR14 ;
wire VAR8 ;
wire VAR16 ;
reg VAR20 ;
wire VAR11 ;
wire VAR19;
wire VAR3 ;
wire VAR5 ;
wire VAR10 ;
wire VAR6 ;
not VAR1 (VAR16 , VAR1... | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/trig_event.v | 105,701 | module MODULE1(
clk
);
input clk;
integer VAR4;
reg [63:0] VAR2;
reg VAR5;
reg [7:0] VAR3;
reg VAR1;
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | gpl-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/atlys/rtl/verilog/xilinx_ddr2/iodrp_mcb_controller.v | 15,423 | module MODULE1(
input wire [7:0] VAR52,
input wire [7:0] VAR53,
output reg [7:0] VAR40 = 0,
input wire VAR39,
input wire VAR33,
output wire VAR36,
input wire VAR16,
input wire [4:0] VAR13,
input wire VAR59,
input wire VAR22,
output reg VAR6,
output wire VAR50, output reg VAR14,
output reg VAR49,
input wire VAR29, outpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311o/sky130_fd_sc_hs__a311o.functional.v | 1,956 | module MODULE1 (
VAR14,
VAR13,
VAR5 ,
VAR11 ,
VAR7 ,
VAR16 ,
VAR12 ,
VAR6
);
input VAR14;
input VAR13;
output VAR5 ;
input VAR11 ;
input VAR7 ;
input VAR16 ;
input VAR12 ;
input VAR6 ;
wire VAR12 VAR8 ;
wire VAR3 ;
wire VAR15;
and VAR10 (VAR8 , VAR16, VAR11, VAR7 );
or VAR1 (VAR3 , VAR8, VAR6, VAR12 );
VAR9 VAR4 (VAR15... | apache-2.0 |
skarpenko/ultiparc | rtl/src/cpu/uparc_execute.v | 7,626 | module MODULE1(
clk,
VAR46,
VAR29,
VAR45,
VAR62,
VAR20,
VAR74,
VAR75,
VAR71,
VAR53,
VAR9,
VAR14,
VAR28,
VAR17,
VAR4,
VAR25,
VAR31,
VAR34,
VAR78,
VAR10,
VAR24,
VAR39,
VAR77,
VAR26,
VAR58,
VAR37,
VAR76,
VAR12,
VAR63,
VAR66,
VAR68,
VAR70,
VAR23,
VAR18,
VAR16,
VAR38,
VAR21,
VAR56,
VAR5
);
input wire clk;
input wire VAR46;
... | bsd-2-clause |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_AO_SRAM_SS_210930.v | 231,431 | module MODULE1 (VAR7, VAR4, VAR6, VAR5, VAR2);
output VAR7;
input VAR4, VAR6, VAR5, VAR2;
wire VAR3, VAR8, VAR10;
wire VAR1, VAR11, VAR9;
not (VAR1, VAR2);
not (VAR10, VAR5);
not (VAR8, VAR6);
and (VAR11, VAR8, VAR10);
not (VAR3, VAR4);
and (VAR9, VAR3, VAR10);
or (VAR7, VAR9, VAR11, VAR1); | bsd-3-clause |
FuzzyLogic/Trivium | hdl/ip/axi_trivium_v1_0.v | 2,225 | module MODULE1 #
(
parameter integer VAR14 = 32,
parameter integer VAR34 = 6
)
(
input wire VAR41,
input wire VAR2,
input wire [VAR34-1 : 0] VAR23,
input wire [2 : 0] VAR4,
input wire VAR15,
output wire VAR10,
input wire [VAR14-1 : 0] VAR43,
input wire [(VAR14/8)-1 : 0] VAR39,
input wire VAR7,
output wire VAR6,
output ... | lgpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_clk_gen/bsg_clk_gen_osc.v | 6,320 | module MODULE1
import VAR17::VAR18;
(
input VAR18 VAR20
,input VAR18 VAR6
,input VAR33
,output VAR35
);
wire VAR2;
wire VAR28 = ~VAR33;
VAR8 VAR34;
wire VAR21;
wire VAR12, VAR7;
VAR19
,.VAR31(1)
) VAR27
(.VAR20(VAR20)
,.VAR25(VAR34)
);
VAR19
,.VAR31(1)
) VAR10
(.VAR20(VAR6)
,.VAR25(VAR21)
);
wire VAR13, VAR22;
wire VAR... | bsd-3-clause |
kielfriedt/ece472 | lab3/ALU16_LA.v | 1,546 | module MODULE1(VAR14, VAR18, sel, out);
input [15:0] VAR14, VAR18;
input [2:0] sel;
wire [3:0] VAR11, VAR9;
output [15:0] out;
assign VAR4 = 1'b0;
wire [2:0] VAR5;
wire VAR17, VAR15, VAR1, VAR16;
wire VAR2[3:0];
VAR3 VAR13(VAR14[3:0], VAR18[3:0], sel[2], VAR2[0], VAR1, sel, out[3:0], VAR11[0], VAR9[0]);
VAR3 VAR8(VAR14... | gpl-3.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/vgpr/wr_port_mux_9to1.v | 5,581 | module MODULE1
(
VAR34, VAR12, VAR25,
VAR15,
VAR19, VAR30, VAR9, VAR24,
VAR21, VAR11, VAR35, VAR28,
VAR17, VAR36, VAR41, VAR33,
VAR1, VAR26, VAR3, VAR20,
VAR27, VAR16, VAR31, VAR2,
VAR39, VAR5, VAR6, VAR13,
VAR29, VAR40, VAR14, VAR8,
VAR7, VAR4, VAR10, VAR38,
VAR32, VAR23, VAR22, VAR42,
VAR37
);
output[3:0] VAR34;
outp... | bsd-3-clause |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/MAC_top.v | 22,795 | module MODULE1(
input VAR75 ,
input VAR84 ,
input VAR112 ,
input VAR72 ,
output [2:0] VAR14 ,
output VAR62 ,
input VAR16 ,
output [31:0] VAR32 ,
output [1:0] VAR140 ,
output VAR96 ,
output VAR64 ,
output VAR25 ,
output VAR92 ,
input VAR147 ,
input [31:0] VAR89 ,
input [1:0] VAR52 ,input VAR87 ,
input VAR55 ,
input VAR7... | apache-2.0 |
dries007/Basys3 | VGA_text/VGA_text.ip_user_files/ip/rom/rom_stub.v | 1,200 | module MODULE1(VAR2, VAR1, VAR3)
;
input VAR2;
input [14:0]VAR1;
output [7:0]VAR3;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtp/sky130_fd_sc_ls__dfrtp.blackbox.v | 1,337 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR7 ,
VAR3
);
output VAR4 ;
input VAR8 ;
input VAR7 ;
input VAR3;
supply1 VAR2;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_demux_4.v | 9,456 | module MODULE1 #
(
parameter VAR46 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR46-1:0] VAR26,
input wire VAR40,
output wire VAR48,
input wire VAR4,
input wire VAR14,
output wire [VAR46-1:0] VAR47,
output wire VAR50,
input wire VAR51,
output wire VAR17,
output wire VAR3,
output wire [VAR46-1:0] VAR11,
output ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.behavioral.v | 5,359 | module MODULE1( VAR10, VAR4, VAR8, VAR7, VAR3, VAR2, VAR5 );
input VAR3, VAR2, VAR5, VAR8, VAR4, VAR10;
output VAR7;
VAR1 VAR9(.VAR10(VAR10),.VAR4(VAR4),.VAR8(VAR8),.VAR7(VAR7),.VAR3(VAR3),.VAR2(VAR2),.VAR5(VAR5));
VAR1 VAR6(.VAR10(VAR10),.VAR4(VAR4),.VAR8(VAR8),.VAR7(VAR7),.VAR3(VAR3),.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/fmlarb/rtl/fmlarb.v | 4,515 | module MODULE1 #(
parameter VAR41 = 26
) (
input VAR35,
input VAR38,
input [VAR41-1:0] VAR17,
input VAR11,
input VAR22,
output VAR40,
input [7:0] VAR42,
input [63:0] VAR1,
output [63:0] VAR31,
input [VAR41-1:0] VAR49,
input VAR46,
input VAR2,
output VAR5,
input [7:0] VAR28,
input [63:0] VAR18,
output [63:0] VAR37,
inpu... | lgpl-3.0 |
freecores/eco32 | fpga/src/ser/rcv.v | 1,026 | module MODULE1(clk, reset, VAR7, VAR3, VAR2);
input clk;
input reset;
output reg VAR7;
output [7:0] VAR3;
input VAR2;
reg VAR6;
reg VAR5;
reg [3:0] state;
reg [8:0] VAR4;
reg [10:0] VAR1;
assign VAR3[7:0] = VAR4[7:0];
always @(posedge clk) begin
VAR6 <= VAR2;
VAR5 <= VAR6;
end
always @(posedge clk) begin
if (reset == 1... | bsd-2-clause |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.