repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22a/sky130_fd_sc_lp__o22a.functional.pp.v | 2,156 | module MODULE1 (
VAR5 ,
VAR13 ,
VAR18 ,
VAR16 ,
VAR19 ,
VAR6,
VAR3,
VAR1 ,
VAR10
);
output VAR5 ;
input VAR13 ;
input VAR18 ;
input VAR16 ;
input VAR19 ;
input VAR6;
input VAR3;
input VAR1 ;
input VAR10 ;
wire VAR12 ;
wire VAR7 ;
wire VAR2 ;
wire VAR11;
or VAR17 (VAR12 , VAR18, VAR13 );
or VAR8 (VAR7 , VAR19, VAR16 );
... | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/ip/SOC/submodules/SoC_NIOS_jtag_debug_module_wrapper.v | 9,714 | module MODULE1 (
VAR2,
VAR28,
clk,
VAR12,
VAR6,
VAR48,
VAR16,
VAR47,
VAR8,
VAR58,
VAR45,
VAR51,
VAR30,
VAR5,
VAR35,
VAR19,
VAR1,
VAR14,
VAR33,
VAR4,
VAR34,
VAR54,
VAR18,
VAR60,
VAR57,
VAR26,
VAR22,
VAR9,
VAR13,
VAR20,
VAR11,
VAR53,
VAR38,
VAR31,
VAR32,
VAR55
)
;
output [ 37: 0] VAR34;
output VAR54;
output VAR18;
output... | gpl-2.0 |
titorgalaxy/Titor | rtl/verilog/core/Register.v | 1,519 | module MODULE1 (
VAR3,
memory,
VAR2,
VAR5,
VAR1,
clk,
reset
);
output reg [VAR4-1:0] VAR3;
input [VAR4-1:0] memory;
input [VAR4-1:0] VAR2;
input VAR5;
input VAR1;
input clk;
input reset;
always @(posedge clk) begin
if(reset) begin VAR3 <= 0; end
else if(VAR5) begin VAR3 <= memory; end
else if(VAR1) begin VAR3 <= VAR2; ... | gpl-3.0 |
oere/progressive-learning-platform | reference/hw/verilog/cpu_wb.v | 1,300 | module MODULE1(VAR9, VAR5, VAR4, VAR7, VAR2,
VAR6, VAR8, VAR1, VAR3);
input VAR9;
input [1:0] VAR5;
input [31:0] VAR4;
input [31:0] VAR7;
input [4:0] VAR2;
input [31:0] VAR6;
output VAR8;
output [31:0] VAR1;
output [4:0] VAR3;
assign VAR8 = VAR9;
assign VAR1 =
(VAR5 == 2'b00) ? VAR4 :
(VAR5 == 2'b01) ? VAR7 :
(VAR5 == ... | gpl-3.0 |
secworks/aes | src/rtl/aes_inv_sbox.v | 11,471 | module MODULE1(
input wire [31 : 0] VAR2,
output wire [31 : 0] VAR1
);
wire [7 : 0] VAR3 [0 : 255];
assign VAR1[31 : 24] = VAR3[VAR2[31 : 24]];
assign VAR1[23 : 16] = VAR3[VAR2[23 : 16]];
assign VAR1[15 : 08] = VAR3[VAR2[15 : 08]];
assign VAR1[07 : 00] = VAR3[VAR2[07 : 00]];
assign VAR3[8'h00] = 8'h52;
assign VAR3[8'h0... | bsd-2-clause |
petrmikheev/miksys | verilog/CHARMAP.v | 6,459 | module MODULE1 (
address,
VAR41,
VAR34);
input [8:0] address;
input VAR41;
output [17:0] VAR34;
tri1 VAR41;
wire [17:0] VAR40;
wire [17:0] VAR34 = VAR40[17:0];
VAR49 VAR8 (
.VAR16 (address),
.VAR30 (VAR41),
.VAR43 (VAR40),
.VAR53 (1'b0),
.VAR33 (1'b0),
.VAR9 (1'b1),
.VAR5 (1'b0),
.VAR35 (1'b0),
.VAR48 (1'b1),
.VAR32 (1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s.behavioral.pp.v | 1,868 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR2,
VAR3,
VAR10 ,
VAR5
);
output VAR9 ;
input VAR6 ;
input VAR2;
input VAR3;
input VAR10 ;
input VAR5 ;
wire VAR8 ;
wire VAR7;
buf VAR1 (VAR8 , VAR6 );
VAR12 VAR11 (VAR7, VAR8, VAR2, VAR3);
buf VAR4 (VAR9 , VAR7 );
endmodule | apache-2.0 |
LSaldyt/qnp | output/vs/opt_var10_multi.v | 9,262 | module MODULE1(VAR7, VAR2, VAR6, VAR1, VAR10, VAR3, VAR5, VAR4, VAR11, VAR8, valid);
wire 000;
wire 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
wire 020;
wire 021;
wire 022;
wire ... | mit |
wangdongCCNU/HPDAQ2 | DDR3_code/ddr3.v | 8,267 | module MODULE1
(
inout [63:0] VAR51,
inout [7:0] VAR43,
inout [7:0] VAR40,
output [13:0] VAR5,
output [2:0] VAR23,
output VAR9,
output VAR4,
output VAR36,
output VAR1,
output VAR45,
output VAR6,
output VAR34,
output VAR18,
output [7:0] VAR31,
output VAR30,
input VAR16,
input VAR15,
input VAR21
);
wire VAR33;
wire VAR26... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111a/sky130_fd_sc_lp__o2111a_4.v | 2,448 | module MODULE1 (
VAR2 ,
VAR10 ,
VAR1 ,
VAR12 ,
VAR7 ,
VAR11 ,
VAR9,
VAR6,
VAR8 ,
VAR5
);
output VAR2 ;
input VAR10 ;
input VAR1 ;
input VAR12 ;
input VAR7 ;
input VAR11 ;
input VAR9;
input VAR6;
input VAR8 ;
input VAR5 ;
VAR3 VAR4 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR11(VAR11),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311oi/sky130_fd_sc_hd__a311oi.pp.blackbox.v | 1,429 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR6 ,
VAR7 ,
VAR10 ,
VAR5 ,
VAR8,
VAR1,
VAR4 ,
VAR9
);
output VAR3 ;
input VAR2 ;
input VAR6 ;
input VAR7 ;
input VAR10 ;
input VAR5 ;
input VAR8;
input VAR1;
input VAR4 ;
input VAR9 ;
endmodule | apache-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/db/ip/ik_swift/submodules/ik_swift_master_0_b2p_adapter.v | 1,492 | module MODULE1 (
input clk,
input VAR12,
output reg VAR1,
input VAR10,
input [ 7: 0] VAR6,
input [ 7: 0] VAR2,
input VAR11,
input VAR13,
input VAR8,
output reg VAR4,
output reg [ 7: 0] VAR7,
output reg VAR3,
output reg VAR5
);
reg VAR9;
always @* begin
VAR1 = VAR8;
VAR4 = VAR10;
VAR7 = VAR6;
VAR3 = VAR11;
VAR5 = VAR13;... | mit |
olofk/oh | xilibs/hdl/fifo_async_104x32.v | 2,217 | module MODULE1
(
VAR2, VAR14, VAR3, dout, VAR11, valid,
VAR7, VAR13, VAR10, VAR12, VAR6, din, VAR5
);
parameter VAR9 = 104; parameter VAR1 = 16;
input VAR7; input VAR13; input VAR10; input VAR12;
input VAR6;
input [VAR9-1:0] din;
output VAR2;
output VAR14;
output VAR3;
input VAR5;
output [VAR9-1:0] dout;
output VAR11;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21o/sky130_fd_sc_ls__a21o.pp.symbol.v | 1,344 | module MODULE1 (
input VAR6 ,
input VAR8 ,
input VAR4 ,
output VAR3 ,
input VAR5 ,
input VAR1,
input VAR7,
input VAR2
);
endmodule | apache-2.0 |
hj3938/FPGA-Imaging-Library | Connector/ColorBin2Channels/srcs/ColorBin2Channels.v | 1,590 | module MODULE1(
VAR1,
VAR3
);
parameter VAR4 = 8;
parameter VAR7 = 3;
input VAR1;
output[VAR7 * VAR4 - 1 : 0] VAR3;
genvar VAR6;
generate
for (VAR6 = 0; VAR6 < VAR7; VAR6 = VAR6 + 1) begin: VAR5
assign VAR3[VAR2 : VAR8] = VAR1 ? {VAR4{1'b1}} : {VAR4{1'b0}};
end
endgenerate
endmodule | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3.symbol.v | 1,322 | module MODULE1 (
input VAR3,
output VAR5
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busreceiver/sky130_fd_sc_lp__busreceiver.behavioral.pp.v | 1,799 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR10,
VAR8,
VAR4 ,
VAR6
);
output VAR5 ;
input VAR7 ;
input VAR10;
input VAR8;
input VAR4 ;
input VAR6 ;
wire VAR11 ;
wire VAR3;
buf VAR1 (VAR11 , VAR7 );
VAR9 VAR12 (VAR3, VAR11, VAR10, VAR8);
buf VAR2 (VAR5 , VAR3 );
endmodule | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_mini/main.v | 10,255 | module MODULE1(
output [22:0] VAR113,
output VAR64,
input VAR108,
output VAR57,
input VAR69,
output [21:0] VAR113,
output VAR19,
output VAR105,
output VAR118,
output VAR62,
output VAR141,
input VAR87,
input VAR72,
input [23:0] VAR148,
input VAR132,
input VAR49,
input VAR117,
inout [7:0] VAR90,
input VAR106,
input VAR12... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ssi/rtl/jbi_ssi_ucbif.v | 20,069 | module MODULE1(
VAR104, VAR148, VAR99,
VAR2, VAR86,
VAR28, VAR92, VAR96,
VAR75, VAR5, VAR138,
VAR130, VAR42, VAR76, VAR3,
VAR87, VAR26, VAR53,
VAR123, VAR117,
clk, VAR23, VAR32, VAR56,
VAR17, VAR18, VAR19,
VAR88, VAR8, VAR9,
VAR111, VAR12, VAR144,
VAR72, VAR14, VAR140,
VAR21, VAR69, VAR39
);
input clk;
input VAR23;
inp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor2/sky130_fd_sc_hdll__xnor2_2.v | 2,148 | module MODULE2 (
VAR3 ,
VAR7 ,
VAR9 ,
VAR1,
VAR2,
VAR5 ,
VAR8
);
output VAR3 ;
input VAR7 ;
input VAR9 ;
input VAR1;
input VAR2;
input VAR5 ;
input VAR8 ;
VAR4 VAR6 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR3,
VAR7,
VAR9
);
output VAR3;
... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/buf_ram_dp_128x512.v | 4,280 | module MODULE1 (
clk ,
VAR38 ,
VAR13 ,
VAR28 ,
VAR8 ,
VAR11 ,
VAR5 ,
VAR45 ,
VAR2 ,
VAR15 ,
VAR36
);
input clk ;
input VAR38 ;
input [1:0] VAR13 ;
input [8:0] VAR28 ;
input [VAR25*8-1:0] VAR8 ;
output [VAR25*8-1:0] VAR11 ;
input VAR5 ;
input [1:0] VAR45 ;
input [8:0] VAR2 ;
input [VAR25*8-1:0] VAR15 ;
output [VAR25*8-1... | gpl-3.0 |
eecsninja/duinocube-core | common/palette.v | 2,406 | module MODULE1(
VAR27, VAR19, VAR32, VAR13, VAR18, VAR22, VAR11,
VAR30, VAR21, VAR31, VAR2, VAR9, VAR20);
parameter VAR12 = 3;
localparam VAR14 = 8;
localparam VAR23 = VAR12 * VAR14;
localparam VAR24 = 10;
input VAR27;
input VAR19;
input VAR32;
input [VAR12-1:0] VAR11;
input [VAR24-1:0] VAR13;
input [VAR23-1:0] VAR18;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrtp/sky130_fd_sc_hvl__dfrtp.behavioral.v | 2,054 | module MODULE1 (
VAR11 ,
VAR10 ,
VAR17 ,
VAR15
);
output VAR11 ;
input VAR10 ;
input VAR17 ;
input VAR15;
supply1 VAR19;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR4 ;
wire VAR16 ;
wire VAR5 ;
reg VAR8 ;
wire VAR9 ;
wire VAR18 ;
wire VAR14;
wire VAR12 ;
not VAR2 (VAR5 , VAR14 );
VAR1 VAR6 (VAR16 , VAR18, VAR12, VAR5, VAR8... | apache-2.0 |
bigeagle/riffa | fpga/altera/de5/DE5Gen2x8If128/hdl/DE5Gen2x8If128.v | 24,095 | module MODULE1
parameter VAR23 = 8,
parameter VAR206 = 128,
parameter VAR124 = 256,
parameter VAR122 = 5
)
(
output [7:0] VAR94,
input VAR3,
input VAR54,
input [VAR23-1:0] VAR51,
output [VAR23-1:0] VAR10,
input VAR11
);
wire VAR8;
wire VAR43;
wire [11:0] VAR179;
wire [31:0] VAR127;
wire VAR174;
wire VAR136;
wire VAR121... | bsd-3-clause |
andrewandrepowell/zybo_petalinux | zybo_petalinux_gpio_sysfs/zybo_petalinux_1.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v | 3,789 | module MODULE1(
VAR2,
VAR14,
VAR12,
VAR26,
VAR3,
VAR10,
VAR23,
VAR11,
VAR21,
VAR27,
VAR24,
VAR5,
VAR25,
VAR13,
VAR18,
VAR6,
VAR16,
VAR28,
VAR4,
VAR15
);
input VAR2, VAR14;
input [VAR20-1:0] VAR12,VAR26;
input VAR3, VAR10;
input [VAR7-1:0] VAR21, VAR27;
input [VAR8:0] VAR23, VAR11;
output reg VAR25, VAR13;
output reg [V... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_clk_synth/pix_pll.v | 12,362 | module MODULE1
(
input VAR58,
input VAR36,
input [2:0] VAR43,
input [1:0] VAR65,
input VAR33,
input [7:0] VAR2,
input [7:0] VAR68,
input [7:0] VAR79,
input [7:0] VAR16,
input [7:0] VAR28,
input [7:0] VAR54,
input [7:0] VAR90,
input [7:0] VAR78,
input VAR74,
output reg [6:0] VAR37,
output reg [5:0] VAR23,
output reg [2:... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/ad9467_fmc/common/ad9467_spi.v | 3,593 | module MODULE1 (
VAR16,
VAR7,
VAR14,
VAR6,
VAR3);
input [ 1:0] VAR16;
input VAR7;
input VAR14;
output VAR6;
inout VAR3;
reg [ 5:0] VAR10 = 'd0;
reg VAR13 = 'd0;
reg VAR1 = 'd0;
wire VAR2;
wire VAR4;
assign VAR2 = & VAR16;
assign VAR4 = VAR1 & ~VAR2;
always @(posedge VAR7 or posedge VAR2) begin
if (VAR2 == 1'b1) begin
V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2_1.v | 2,037 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR3,
VAR4
);
output VAR1 ;
input VAR5 ;
input VAR3;
input VAR4;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
supply1 VAR3;
supply0 VAR4;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule | apache-2.0 |
unihd-cag/openhmc | rtl/building_blocks/counter/openhmc_counter48.v | 3,229 | module MODULE1 #(
parameter VAR3 = 16 ) (
input wire clk,
input wire VAR4,
input wire VAR2,
input wire VAR7,
output wire [VAR3-1:0] VAR1
);
reg [VAR3-1:0] VAR5;
reg VAR8;
assign VAR1 = VAR5;
always @(posedge clk or negedge VAR4) else
always @(posedge clk) VAR6
begin
if(!VAR4) begin
VAR5 <= {VAR3{1'b0}};
VAR8 <= 1'b0;
e... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or2/sky130_fd_sc_hvl__or2.pp.blackbox.v | 1,258 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR7 ,
VAR4,
VAR6,
VAR5 ,
VAR1
);
output VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR4;
input VAR6;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_p_pp_sn/sky130_fd_sc_hs__udp_dlatch_p_pp_sn.blackbox.v | 1,377 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR4 ,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR2 ;
input VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkbuf/sky130_fd_sc_ls__clkbuf_4.v | 2,034 | module MODULE2 (
VAR3 ,
VAR2 ,
VAR7,
VAR5,
VAR6 ,
VAR4
);
output VAR3 ;
input VAR2 ;
input VAR7;
input VAR5;
input VAR6 ;
input VAR4 ;
VAR1 VAR8 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR3,
VAR2
);
output VAR3;
input VAR2;
supply1 VAR7;
supply0 VAR5;... | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/wb/rtl/wb_mux_2.v | 5,435 | module MODULE1 #
(
parameter VAR8 = 32, parameter VAR26 = 32, parameter VAR36 = (VAR8/8) )
(
input wire clk,
input wire rst,
input wire [VAR26-1:0] VAR16, input wire [VAR8-1:0] VAR28, output wire [VAR8-1:0] VAR4, input wire VAR22, input wire [VAR36-1:0] VAR33, input wire VAR17, output wire VAR23, output wire VAR6, outp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21boi/sky130_fd_sc_hs__a21boi_2.v | 2,205 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR5 ,
VAR1,
VAR4,
VAR8
);
output VAR3 ;
input VAR2 ;
input VAR5 ;
input VAR1;
input VAR4;
input VAR8;
VAR6 VAR7 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR3 ,
VAR2 ,
VAR5 ,
VAR1
);
output VAR3 ;
input VAR2 ;
input VAR5 ... | apache-2.0 |
vad-rulezz/megabot | minsoc/utils/contributions/minsoc_tc_top_B3.v | 44,006 | module MODULE2 (
VAR165,
VAR33,
VAR241,
VAR195,
VAR71,
VAR12,
VAR203,
VAR229,
VAR104,
VAR295,
VAR10,
VAR76,
VAR109,
VAR210,
VAR31,
VAR75,
VAR67,
VAR91,
VAR307,
VAR252,
VAR6,
VAR222,
VAR308,
VAR305,
VAR262,
VAR242,
VAR116,
VAR187,
VAR237,
VAR179,
VAR275,
VAR26,
VAR164,
VAR152,
VAR204,
VAR177,
VAR254,
VAR17,
VAR145,
VAR2... | gpl-2.0 |
solowandererY2K/FPGA-Quantum-Compiler | src/squarer.v | 4,036 | module MODULE1 (
VAR1,
VAR10);
input [39:0] VAR1;
output [79:0] VAR10;
wire [79:0] VAR4;
wire [79:0] VAR10 = VAR4[79:0];
VAR5 VAR14 (
.VAR12 (VAR1),
.VAR10 (VAR4),
.VAR3 (1'b0),
.VAR11 (1'b1),
.VAR13 (1'b1));
VAR14.VAR6 = 40,
VAR14.VAR9 = "VAR16",
VAR14.VAR8 = 0,
VAR14.VAR2 = "VAR7",
VAR14.VAR15 = 80;
endmodule | mit |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/opencores/ge_1000baseX/decoder_8b10b.v | 14,931 | module MODULE1 (
input reset,
input VAR60,
input [9:0] VAR25,
output reg VAR54,
output reg [7:0] VAR20,
output reg VAR33,
output reg VAR27,
output VAR72
);
wire [4:0] VAR65; wire [2:0] VAR46;
assign VAR65 = VAR20[4:0];
assign VAR46 = VAR20[7:5];
wire VAR55,VAR43,VAR17,VAR98,VAR28,VAR70,VAR62,VAR48,VAR96,VAR8;
assign {V... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_dq_pad.v | 7,431 | module MODULE1(
VAR1, VAR9, VAR30, VAR36,
VAR32, VAR42,
VAR39,
VAR34, VAR5, VAR25, VAR4, VAR10, VAR16,
VAR40, VAR2, VAR46, VAR13, VAR19, VAR21, VAR23,
VAR22, VAR31, VAR43, VAR14,
VAR7, VAR37, VAR41, VAR11,
VAR38, VAR18, VAR24, clk, VAR20, VAR47, VAR28,
VAR29, VAR6, VAR26, VAR44
);
input VAR44; input VAR26; input VAR6; ... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/flow_classification.v | 4,116 | module MODULE1
( output [63:0] VAR42,
output [15:0] VAR7,
output VAR39,
output reg VAR43,
input VAR27,
output [63:0] VAR23,
output [15:0] VAR21,
output VAR34,
output reg VAR26,
input VAR31,
input [63:0] VAR10,
input [7:0] VAR28,
input VAR8,
output VAR37,
input VAR9,
input VAR3,
input VAR45,
input [VAR18-1:0] VAR13,
inp... | mit |
Digilent/vivado-library | ip/Pmods/PmodACL2_v1_0/src/PmodACL2.v | 13,887 | module MODULE1
(VAR76,
VAR34,
VAR142,
VAR120,
VAR173,
VAR80,
VAR175,
VAR112,
VAR77,
VAR75,
VAR113,
VAR123,
VAR212,
VAR83,
VAR101,
VAR82,
VAR204,
VAR97,
VAR165,
VAR188,
VAR195,
VAR22,
VAR48,
VAR29,
VAR6,
VAR168,
VAR88,
VAR78,
VAR52,
VAR205,
VAR99,
VAR209,
VAR56,
VAR185,
VAR96,
VAR122,
VAR90,
VAR117,
VAR16,
VAR79,
VAR38,... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/phase_align.v | 3,419 | module MODULE1
(
VAR4,
VAR1,
VAR5
);
input VAR4;
input VAR1;
output VAR5;
reg [0:1] VAR2;
always @(posedge VAR1)
begin
VAR2[0] <= VAR3 VAR4;
VAR2[1] <= VAR3 VAR2[0];
end
assign VAR5 = VAR2[1];
endmodule | bsd-2-clause |
ptracton/wb_soc_template | tasks/uart_tasks.v | 2,793 | module MODULE1;
task VAR5;
begin
@(posedge VAR6);
@(posedge VAR6);
@(posedge VAR6);
@(posedge VAR6);
@(posedge VAR6);
@(posedge VAR6);
end
endtask
task VAR2;
input [7:0] VAR4;
begin
@(posedge VAR6);
end
endtask
task VAR1;
input [7:0] VAR3;
begin
begin
end
end
endtask
endmodule | mit |
mrehkopf/sd2snes | verilog/sd2snes_sgb/vram.v | 10,612 | module MODULE1 (
VAR37,
VAR40,
VAR8,
VAR28,
VAR16,
VAR10,
VAR29,
VAR56,
VAR35);
input [12:0] VAR37;
input [12:0] VAR40;
input VAR8;
input [7:0] VAR28;
input [7:0] VAR16;
input VAR10;
input VAR29;
output [7:0] VAR56;
output [7:0] VAR35;
tri1 VAR8;
tri0 VAR10;
tri0 VAR29;
wire [7:0] VAR18;
wire [7:0] VAR61;
wire [7:0] VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21o/sky130_fd_sc_lp__a21o.functional.v | 1,406 | module MODULE1 (
VAR9 ,
VAR8,
VAR1,
VAR2
);
output VAR9 ;
input VAR8;
input VAR1;
input VAR2;
wire VAR3 ;
wire VAR5;
and VAR7 (VAR3 , VAR8, VAR1 );
or VAR4 (VAR5, VAR3, VAR2 );
buf VAR6 (VAR9 , VAR5 );
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_iwb_biu.v | 15,610 | module MODULE1(
clk, rst, VAR13,
VAR35, VAR5, VAR45, VAR44, VAR3, VAR15,
VAR30, VAR18, VAR46, VAR23, VAR20, VAR7,
VAR34,
VAR26, VAR16,
VAR42, VAR22, VAR28, VAR17, VAR1, VAR36, VAR41,
VAR25, VAR2, VAR39
);
parameter VAR37 = VAR31;
parameter VAR9 = VAR31;
input clk; input rst; input [1:0] VAR13;
input VAR35; input VAR5; ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22o/sky130_fd_sc_lp__a22o_lp.v | 2,347 | module MODULE2 (
VAR1 ,
VAR8 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR11,
VAR2,
VAR3 ,
VAR7
);
output VAR1 ;
input VAR8 ;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR11;
input VAR2;
input VAR3 ;
input VAR7 ;
VAR10 VAR9 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR... | apache-2.0 |
AngelTerrones/ADA | rtl/ada_reg_file.v | 2,196 | module MODULE1(
input clk, input [4:0] VAR8, input [4:0] VAR5, input [4:0] VAR2, input [31:0] VAR3, input VAR7, output [31:0] VAR6, output [31:0] VAR1 );
reg [31:0] VAR4 [1:31];
always @(posedge clk) begin
if (VAR2 != 0)
VAR4[VAR2] <= (VAR7) ? VAR3 : VAR4[VAR2];
end
assign VAR6 = (VAR8 == 5'b0) ? 32'h00000000 : VAR4[VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlclkp/sky130_fd_sc_hd__dlclkp_1.v | 2,154 | module MODULE1 (
VAR4,
VAR7,
VAR5 ,
VAR2,
VAR8,
VAR3 ,
VAR9
);
output VAR4;
input VAR7;
input VAR5 ;
input VAR2;
input VAR8;
input VAR3 ;
input VAR9 ;
VAR1 VAR6 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR4,
VAR7,
VAR5
);
output VAR4;
inpu... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/round.v | 2,129 | module MODULE1
parameter VAR10=0,
parameter VAR3=0, parameter VAR1=1, parameter VAR11=0) (input [VAR6-1:0] in,
output [VAR10-1:0] out,
output [VAR6-VAR10:0] VAR9);
wire VAR7,VAR8,VAR5,VAR2,VAR4;
assign VAR8 = 0;
assign VAR5 = (in[VAR6-1] & |in[VAR6-VAR10-1:0]);
assign VAR2 = in[VAR6-VAR10-1];
generate
if(VAR6-VAR10 > 1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dlatch_p/sky130_fd_sc_hvl__udp_dlatch_p.symbol.v | 1,298 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR1
);
endmodule | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/rx_engine.v | 10,673 | module MODULE1 #(
parameter VAR40 = 64, parameter VAR38 = 'h400
) (
input VAR6, input VAR26, input [VAR40-1:0] VAR18,
input VAR11,
input VAR50,
output reg VAR14,
input VAR37, output reg VAR30, output reg [31:0] VAR35, output reg [2:0] VAR20, output reg VAR47, output reg VAR33, output reg [1:0] VAR27, output reg [9:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111a/sky130_fd_sc_hd__o2111a_4.v | 2,448 | module MODULE1 (
VAR3 ,
VAR12 ,
VAR6 ,
VAR9 ,
VAR7 ,
VAR4 ,
VAR8,
VAR11,
VAR1 ,
VAR2
);
output VAR3 ;
input VAR12 ;
input VAR6 ;
input VAR9 ;
input VAR7 ;
input VAR4 ;
input VAR8;
input VAR11;
input VAR1 ;
input VAR2 ;
VAR10 VAR5 (
.VAR3(VAR3),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VA... | apache-2.0 |
roberth188/EMU-Hearing-Assistance-Device | EMU_Basic_Project/src/mojo_top.v | 2,041 | module MODULE1(
input clk,
input VAR22,
output VAR28,
output VAR4,
output [11:0] VAR2,
output VAR18,
output VAR12,
output VAR23,
output VAR3,
input VAR20,
input VAR8,
input VAR15,
input VAR26,
output VAR21,
input [13:0] VAR13 );
wire rst = VAR22;
assign VAR9 = clk;
wire VAR29;
wire [9:0] VAR27;
wire [8:0] VAR24;
wire [... | mit |
walkthetalk/fsref | ip/axis_scaler/src/include/scaler_1d.v | 6,896 | module MODULE1 # (
parameter integer VAR15 = 12,
parameter integer VAR5 = 12,
parameter integer VAR35 = 4 ,
parameter integer VAR58 = 2 ,
parameter integer VAR18 = 0 , parameter integer VAR83 = 2
) (
input wire clk,
input wire VAR53,
input [VAR15-1:0] VAR46,
input [VAR5-1:0] VAR14,
output wire VAR16 ,
input wire VAR76 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22ai/sky130_fd_sc_hs__o22ai.pp.symbol.v | 1,343 | module MODULE1 (
input VAR6 ,
input VAR4 ,
input VAR7 ,
input VAR1 ,
output VAR3 ,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfsbp/sky130_fd_sc_hd__dfsbp.blackbox.v | 1,356 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR5 ,
VAR4 ,
VAR6
);
output VAR1 ;
output VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR6;
supply1 VAR8;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxbp/sky130_fd_sc_hvl__dfxbp.functional.pp.v | 2,171 | module MODULE1 (
VAR13 ,
VAR17 ,
VAR6 ,
VAR10 ,
VAR19,
VAR5,
VAR12 ,
VAR11
);
output VAR13 ;
output VAR17 ;
input VAR6 ;
input VAR10 ;
input VAR19;
input VAR5;
input VAR12 ;
input VAR11 ;
wire VAR16 ;
wire VAR14 ;
wire VAR1;
VAR9 VAR7 VAR15 (VAR16 , VAR10, VAR6, , VAR19, VAR5 );
buf VAR8 (VAR14 , VAR16 );
VAR18 VAR4 (V... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_cmd_gen.v | 118,926 | module MODULE1
VAR97 = 33,
VAR314 = 3,
VAR363 = 8,
VAR75 = 4,
VAR11 = 4,
VAR281 = 5,
VAR178 = 2,
VAR143 = 2,
VAR280 = 5,
VAR366 = 2,
VAR293 = 2, VAR255 = 8,
VAR332 = 1, VAR249 = 1, VAR161 = 3,
VAR247 = 13,
VAR239 = 10,
VAR168 = 10,
VAR335 = 1,
VAR144 = 1,
VAR180 = 0,
VAR370 = 4,
VAR315 = 4,
VAR83 = 8,
VAR369 = 12,
VAR2... | gpl-3.0 |
alexforencich/hdg2000 | fpga/lib/wb/rtl/wb_mux_3.v | 6,922 | module MODULE1 #
(
parameter VAR36 = 32, parameter VAR15 = 32, parameter VAR44 = (VAR36/8) )
(
input wire clk,
input wire rst,
input wire [VAR15-1:0] VAR55, input wire [VAR36-1:0] VAR32, output wire [VAR36-1:0] VAR40, input wire VAR57, input wire [VAR44-1:0] VAR4, input wire VAR49, output wire VAR14, output wire VAR29,... | mit |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ipshared/xilinx.com/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_fmsw_gp.v | 6,459 | module MODULE1(
VAR72,
VAR99,
VAR93,
VAR8,
VAR63,
VAR50,
VAR70,
VAR78,
VAR65,
VAR31,
VAR13,
VAR75,
VAR69,
VAR23,
VAR37,
VAR45,
VAR32,
VAR57,
VAR19,
VAR100,
VAR51,
VAR59,
VAR68,
VAR43,
VAR17,
VAR73,
VAR74,
VAR39,
VAR83,
VAR15,
VAR86,
VAR36,
VAR48,
VAR77,
VAR90,
VAR29,
VAR35,
VAR4,
VAR55,
VAR79,
VAR80,
VAR33,
VAR92,
VAR6... | gpl-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_128bits.v | 1,917 | module MODULE2 (
clk,
VAR29, VAR21, VAR5, VAR8, VAR23, VAR10, VAR15, VAR4,
sum,
);
input clk;
input [VAR30+0-1:0] VAR29, VAR21, VAR5, VAR8, VAR23, VAR10, VAR15, VAR4;
output [VAR30 :0] sum;
reg [VAR30 :0] sum;
wire [VAR30+3-1:0] VAR3;
wire [VAR30+2-1:0] VAR22, VAR13;
wire [VAR30+1-1:0] VAR32, VAR24, VAR12, VAR11;
reg [... | mit |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_0_poc_pd.v | 4,588 | module MODULE1 #
(parameter VAR12 = "VAR17",
parameter VAR1 = "VAR23",
parameter VAR33 = 100)
(
VAR21,
VAR10, clk, VAR2, VAR4
);
input VAR10;
input clk;
input VAR2;
input VAR4;
wire VAR8;
VAR28 #
(.VAR7 ("VAR13"),
.VAR15 (1'b0),
.VAR31 (1'b0),
.VAR14 ("VAR32"))
VAR29
(.VAR24 (VAR8),
.VAR6 (),
.VAR5 (VAR4),
.VAR3 (1'b1)... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_077.v | 1,546 | module MODULE2 (
VAR5,
VAR8
);
input [31:0] VAR5;
output [31:0]
VAR8;
wire [31:0]
VAR13,
VAR4,
VAR1,
VAR3,
VAR7,
VAR11,
VAR2,
VAR14,
VAR9;
assign VAR13 = VAR5;
assign VAR1 = VAR4 - VAR13;
assign VAR4 = VAR13 << 10;
assign VAR7 = VAR3 - VAR1;
assign VAR2 = VAR7 + VAR11;
assign VAR3 = VAR13 << 14;
assign VAR9 = VAR2 + VA... | mit |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/cpu_0_jtag_debug_module.v | 12,372 | module MODULE1 (
VAR16,
VAR28,
clk,
VAR45,
VAR33,
VAR34,
VAR41,
VAR23,
VAR29,
VAR27,
VAR38,
VAR10,
VAR54,
VAR2,
VAR55,
VAR46,
VAR50,
VAR42,
VAR26,
VAR49,
VAR13,
VAR9,
VAR7,
VAR24,
VAR52,
VAR37,
VAR21,
VAR31,
VAR43,
VAR57,
VAR22,
irq,
VAR48,
VAR39,
VAR20,
VAR17,
VAR32,
VAR15,
VAR12,
VAR4,
VAR56,
VAR3,
VAR19,
VAR25,
VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/decap/sky130_fd_sc_hdll__decap.blackbox.v | 1,199 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_pwrgood_pp_pg_s/sky130_fd_sc_lp__udp_pwrgood_pp_pg_s.symbol.v | 1,360 | module MODULE1 (
input VAR3 ,
output VAR1,
input VAR5 ,
input VAR4 ,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxtp/sky130_fd_sc_ls__sedfxtp.behavioral.pp.v | 2,629 | module MODULE1 (
VAR21 ,
VAR20 ,
VAR12 ,
VAR9 ,
VAR1 ,
VAR26 ,
VAR22,
VAR15,
VAR17 ,
VAR18
);
output VAR21 ;
input VAR20 ;
input VAR12 ;
input VAR9 ;
input VAR1 ;
input VAR26 ;
input VAR22;
input VAR15;
input VAR17 ;
input VAR18 ;
wire VAR13 ;
reg VAR29 ;
wire VAR10 ;
wire VAR19 ;
wire VAR28;
wire VAR16;
wire VAR5;
wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2i/sky130_fd_sc_hdll__mux2i.behavioral.pp.v | 1,954 | module MODULE1 (
VAR11 ,
VAR7 ,
VAR13 ,
VAR14 ,
VAR1,
VAR5,
VAR10 ,
VAR4
);
output VAR11 ;
input VAR7 ;
input VAR13 ;
input VAR14 ;
input VAR1;
input VAR5;
input VAR10 ;
input VAR4 ;
wire VAR9;
wire VAR15;
VAR12 VAR2 (VAR9, VAR7, VAR13, VAR14 );
VAR6 VAR8 (VAR15, VAR9, VAR1, VAR5);
buf VAR3 (VAR11 , VAR15 );
endmodule | apache-2.0 |
olofk/oh | edma/hdl/edma.v | 7,587 | module MODULE1 (
VAR5, VAR2, VAR1,
reset, clk, VAR9, VAR12, VAR6, VAR4, VAR3
);
parameter VAR7 = 6;
parameter VAR11 = 32;
parameter VAR8 = 32;
parameter VAR10 = 104;
input reset; input clk;
input VAR9;
input VAR12;
input [VAR7+1:0] VAR6;
input [63:0] VAR4;
output [31:0] VAR5;
output VAR2;
output [VAR10-1:0] VAR1;
input... | gpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/xilinx_v5_pcie_wrapper.v | 11,105 | module MODULE1
(
VAR94, VAR84, VAR61, VAR62,
VAR33, VAR60, VAR73, VAR10,
VAR9, VAR15, VAR19, VAR82,
VAR7, VAR41, VAR23,
VAR45, VAR110, VAR83,
VAR97, VAR67, VAR36, VAR47, VAR86,
VAR102, VAR107, VAR24, VAR96,
VAR32, VAR98, VAR29, VAR1,
VAR103, VAR25, VAR37, VAR52,
VAR63, VAR21, VAR74,
VAR14, VAR13,
VAR4, VAR91, VAR42,
VA... | lgpl-3.0 |
cynngah/virtualsynthesizer | sound_files/clock_generator.v | 9,808 | module MODULE1 (
VAR19,
reset,
VAR92
);
parameter VAR72 = 14;
parameter VAR74 = 31;
input VAR19;
input reset;
output VAR92;
wire VAR68;
VAR84 VAR95 (
.VAR10 ({1'b0, VAR19}),
.clk (VAR92),
.VAR9 (VAR68),
.VAR53 (),
.VAR69 (reset),
.VAR59 (),
.VAR35 ({6{1'b1}}),
.VAR64 (),
.VAR61 (1'b0),
.VAR62 (),
.VAR88 (),
.VAR22 (),
... | mit |
AmeerAbdelhadi/Dynamic-Frequency-Phase-Sweeping | keyfilter.v | 3,454 | module MODULE1 (
input VAR6 , input VAR8 , output reg VAR10 );
wire [18:0] VAR9;
VAR5 #( .VAR3(19 ), .VAR7(0 )) VAR1 ( .clk(VAR6 ), .VAR4(1'b1 ), .rst(1'b0 ), .VAR2(VAR9));
reg VAR11;
always @(posedge VAR6)
VAR11 <= (VAR9==19'd0);
always @(posedge VAR11)
VAR10 <= !VAR8;
endmodule | bsd-3-clause |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_csr.v | 51,657 | module MODULE1 #
( parameter
VAR92 = 2,
VAR22 = 1,
VAR176 = 1,
VAR69 = 0,
VAR192 = 0,
VAR82 = 8,
VAR13 = 32,
VAR34 = 1,
VAR114 = 72,
VAR72 = 1, VAR6 = 13, VAR162 = 10, VAR173 = 3,
VAR26 = 1,
VAR172 = 1,
VAR2 = 0,
VAR76 = 4, VAR101 = 4, VAR15 = 4, VAR8 = 5, VAR137 = 4, VAR122 = 6, VAR135 = 8, VAR40 = 13, VAR171 = 4, VAR... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/sctag_scbuf_rptr3.v | 7,720 | module MODULE1 (
VAR6, VAR18,
VAR50, VAR15,
VAR32, VAR33,
VAR27, VAR8,
VAR25, VAR3,
VAR34, VAR42,
VAR45, VAR4,
VAR17, VAR14,
VAR26, VAR37,
VAR16, VAR10,
VAR20, VAR47,
VAR9, VAR19,
VAR43,
VAR2, VAR31,
VAR22, VAR23,
VAR46, VAR44,
VAR30, VAR24,
VAR11, VAR29,
VAR49, VAR38,
VAR48, VAR41,
VAR12, VAR21,
VAR13, VAR7,
VAR35, VA... | gpl-2.0 |
DSDL2016/project2 | source/lcd_controller.v | 1,808 | module MODULE1 (
input VAR5,
input reset,
input [7:0] VAR15,
input VAR14,
input VAR6,
output reg VAR16,
output [7:0] VAR4,
output [4:0] VAR2
);
parameter VAR10 = 16;
reg [4:0] VAR13;
reg [1:0] state;
reg VAR1, VAR12;
reg VAR9;
assign VAR4 = VAR15;
assign VAR2 = {1'b0, VAR9, VAR14, 1'b1, 1'b1};
parameter [1:0] VAR3 = 2'... | mit |
ptracton/wb_soc_template | rtl/LM32/rtl/BSCAN_SPARTAN6.v | 3,640 | module MODULE1 (VAR9, VAR4, VAR3, VAR11, VAR1, VAR13, VAR8, VAR5, VAR6, VAR7, VAR2);
output VAR9, VAR4, VAR3, VAR11, VAR1, VAR13, VAR8, VAR5, VAR6, VAR7;
input VAR2;
reg VAR12;
parameter integer VAR10 = 1;
pulldown (VAR4);
pulldown (VAR3);
pulldown (VAR1);
pulldown (VAR13);
pulldown (VAR5);
pulldown (VAR7); | mit |
vipinkmenon/scas | hw/fpga/source/memory_if/mig_7series_v1_8_ddr_phy_wrcal.v | 74,375 | module MODULE1 #
(
parameter VAR289 = 100, parameter VAR8 = 2, parameter VAR253 = 2500,
parameter VAR265 = 64, parameter VAR264 = 3, parameter VAR223 = 8, parameter VAR99 = 8, parameter VAR43 = "VAR38", parameter VAR283 = "VAR22", parameter VAR28 = 2 )
(
input clk,
input rst,
input VAR92,
input VAR88,
input VAR36,
inpu... | mit |
cospan/prometheus_fpga | rtl/slave_fifo/prometheus_fx3_stream_in.v | 2,200 | module MODULE1(
input VAR1,
input VAR2,
input VAR10,
input VAR11,
input VAR7,
output VAR5,
output [31:0] VAR14
);
reg [2:0]VAR9;
reg [2:0]VAR4;
reg [31:0]VAR6;
parameter [2:0] VAR3 = 3'd0;
parameter [2:0] VAR8 = 3'd1;
parameter [2:0] VAR12 = 3'd2;
parameter [2:0] VAR13 = 3'd3;
assign VAR5 = ((VAR9 == VAR12) && (VAR7 ==... | gpl-3.0 |
hydai/Verilog-Practice | DigitalDesign/hw3/hw3_t.v | 2,282 | module MODULE1 ;
reg [57:0] VAR1 [VAR5-1:0];
reg [291:0] VAR3 [VAR5-1:0];
reg [25:0] VAR4;
reg [15:0] VAR18;
reg [15:0] VAR26;
reg clk, VAR25;
reg VAR14, VAR9, VAR29, VAR15;
reg [15:0] VAR6;
reg [15:0] VAR22;
reg [15:0] VAR34;
reg [15:0] VAR36;
reg [15:0] VAR20;
reg [15:0] VAR8;
reg [15:0] VAR30;
reg [15:0] VAR12;
reg ... | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_AO_RVT_TT_210930.v | 231,279 | module MODULE1 (VAR8, VAR7, VAR6, VAR11, VAR9);
output VAR8;
input VAR7, VAR6, VAR11, VAR9;
wire VAR2, VAR1, VAR4;
wire VAR10, VAR3, VAR5;
not (VAR10, VAR9);
not (VAR4, VAR11);
not (VAR1, VAR6);
and (VAR3, VAR1, VAR4);
not (VAR2, VAR7);
and (VAR5, VAR2, VAR4);
or (VAR8, VAR5, VAR3, VAR10); | bsd-3-clause |
sabertazimi/hust-lab | verilog/labs/lab2/src/bcd_to_7segment_decoder.v | 1,082 | module MODULE1(input [3:0] VAR2, output [3:0] VAR3, output [6:0] VAR1);
assign VAR3 = 4'b0001;
assign VAR1[0] = (~VAR2[0] & ~VAR2[1] & VAR2[2]) | (VAR2[0] & ~VAR2[1] & ~VAR2[2] & ~VAR2[3]); assign VAR1[1] = (VAR2[0] ^ VAR2[1]) & VAR2[2]; assign VAR1[2] = ~VAR2[0] & VAR2[1] & ~VAR2[2]; assign VAR1[3] = (~VAR2[0] & ~VAR2... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_4.behavioral.v | 1,250 | module MODULE1( VAR2, VAR6, VAR5, VAR3 );
input VAR5, VAR6, VAR2;
output VAR3;
VAR7 VAR4(.VAR2(VAR2),.VAR6(VAR6),.VAR5(VAR5),.VAR3(VAR3));
VAR7 VAR1(.VAR2(VAR2),.VAR6(VAR6),.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
rkrajnc/minimig-de1 | rtl/minimig/Amber.v | 12,379 | module MODULE1
(
input wire clk, input wire VAR40, input wire [ 2-1:0] VAR10, input wire [ 2-1:0] VAR11, input wire [ 2-1:0] VAR50, input wire [ 9-1:1] VAR4, input wire VAR56, input wire VAR57, input wire VAR9, input wire [ 4-1:0] VAR33, input wire [ 4-1:0] VAR24, input wire [ 4-1:0] VAR49, input wire VAR53, input wire... | gpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_top.v | 24,587 | module MODULE1(
VAR183, VAR208, VAR88, VAR351,
VAR368, VAR427, VAR99, VAR292, VAR89, VAR71,
VAR425, VAR412, VAR216, VAR240, VAR181, VAR148,
VAR301,
VAR254, VAR10,
VAR242, VAR350, VAR268, VAR81, VAR54, VAR293,
VAR53, VAR291, VAR91, VAR50, VAR159, VAR49,
VAR381,
VAR225, VAR147,
VAR218, VAR342, VAR253, VAR379, VAR408, VAR... | mit |
scalable-networks/ext | uhd/fpga/usrp1/sdr_lib/cic_decim.v | 2,709 | module MODULE1
( VAR7,reset,enable,VAR20,VAR11,VAR3,VAR5,VAR13);
parameter VAR21 = 16;
parameter VAR18 = 4;
parameter VAR10 = 7;
parameter VAR6 = VAR18 * VAR10;
input VAR7;
input reset;
input enable;
input [7:0] VAR20;
input VAR11,VAR3;
input [VAR21-1:0] VAR5;
output [VAR21-1:0] VAR13;
reg [VAR21-1:0] VAR13;
wire [VAR2... | gpl-2.0 |
theapi/de0-nano | vga/vga_800x480_buffered/ip_ram/ip_ram_bb.v | 5,727 | module MODULE1 (
address,
VAR2,
VAR1,
VAR4,
VAR3);
input [14:0] address;
input VAR2;
input [15:0] VAR1;
input VAR4;
output [15:0] VAR3;
tri1 VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlxtp/sky130_fd_sc_lp__srdlxtp.functional.pp.v | 1,850 | module MODULE1 (
VAR16 ,
VAR7 ,
VAR13 ,
VAR3,
VAR9 ,
VAR10 ,
VAR12 ,
VAR11 ,
VAR4
);
output VAR16 ;
input VAR7 ;
input VAR13 ;
input VAR3;
input VAR9 ;
input VAR10 ;
input VAR12 ;
input VAR11 ;
input VAR4 ;
wire VAR8 ;
wire VAR2;
wire VAR14 ;
VAR5 VAR1 VAR6 (VAR8 , VAR7, VAR13, VAR3, VAR9, VAR12, VAR10);
bufif1 VAR15 (... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_dtl_vref.v | 1,313 | module MODULE1 (
VAR1, VAR2
);
output VAR1;
input VAR2; assign VAR1 = 1'b1;
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_1.behavioral.pp.v | 1,383 | module MODULE1( VAR3, VAR7, VAR9, VAR5, VAR10, VAR4, VAR2 );
input VAR3, VAR7, VAR9, VAR5;
inout VAR4, VAR2;
output VAR10;
VAR1 VAR6(.VAR3(VAR3),.VAR7(VAR7),.VAR9(VAR9),.VAR5(VAR5),.VAR10(VAR10),.VAR4(VAR4),.VAR2(VAR2));
VAR1 VAR8(.VAR3(VAR3),.VAR7(VAR7),.VAR9(VAR9),.VAR5(VAR5),.VAR10(VAR10),.VAR4(VAR4),.VAR2(VAR2)); | apache-2.0 |
gnucap/gnucap-geda | include/analog.v | 2,152 | MODULE1 VAR16=VAR22
module MODULE6(1 2);
parameter VAR21=1;
VAR38 #(.VAR7(VAR21)) VAR7(1,2);
endmodule
VAR42 MODULE6
module MODULE9(VAR28 VAR51);
endmodule
VAR42 MODULE9
module MODULE10(1 2);
parameter VAR21=1;
VAR27 #(.VAR53(VAR21)) VAR53(1,2);
endmodule
VAR42 MODULE10
module MODULE3(VAR51 VAR28);
parameter VAR21=1;
V... | gpl-3.0 |
orbancedric/DeepGate | other/Mojo Projects/Mojo-SDRAM/src/serial_rx.v | 1,686 | module MODULE1 #(
parameter VAR11 = 50,
parameter VAR6 = 6
)(
input clk,
input rst,
input VAR15,
output [7:0] VAR1,
output VAR9
);
localparam VAR10 = 2;
localparam VAR5 = 2'd0,
VAR14 = 2'd1,
VAR17 = 2'd2,
VAR7 = 2'd3;
reg [VAR6-1:0] VAR21, VAR2;
reg [2:0] VAR22, VAR8;
reg [7:0] VAR18, VAR4;
reg VAR16, VAR12;
reg [VAR10... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221oi/sky130_fd_sc_hs__a221oi_4.v | 2,330 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR9 ,
VAR1 ,
VAR6 ,
VAR5 ,
VAR3,
VAR10
);
output VAR4 ;
input VAR2 ;
input VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR5 ;
input VAR3;
input VAR10;
VAR8 VAR7 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR10(VAR10)
);
endmodule
module MODUL... | apache-2.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/soc_system_dipsw_pio.v | 3,950 | module MODULE1 (
address,
VAR10,
clk,
VAR6,
VAR4,
VAR3,
VAR14,
VAR8
)
;
output [ 31: 0] VAR8;
input [ 1: 0] address;
input VAR10;
input clk;
input [ 3: 0] VAR6;
input VAR4;
input VAR3;
input [ 31: 0] VAR14;
wire VAR9;
reg [ 3: 0] VAR1;
reg [ 3: 0] VAR11;
wire [ 3: 0] VAR5;
reg [ 3: 0] VAR13;
wire VAR7;
wire [ 3: 0] VAR... | gpl-3.0 |
HarmonInstruments/verilog | fir/mac_24x18.v | 1,354 | module MODULE1
(
input VAR17,
input VAR21, input signed [23:0] VAR7,
input signed [17:0] VAR14,
output signed [23:0] VAR18);
VAR9 #(.VAR24(24), .VAR4(18), .VAR23(24), .VAR11(18), .VAR20(1), .VAR10(1)) VAR13
(
.VAR15(VAR17),
.VAR22(1'b1),
.VAR6(1'b1),
.VAR3(1'b1),
.VAR5(1'b1),
.VAR7(VAR7),
.VAR14(VAR14),
.VAR17(24'd1310... | gpl-3.0 |
siamumar/TinyGarbled | circuit_synthesis/knns_td/knns_seq_td.v | 2,894 | module MODULE1
(
parameter VAR29 = 32,
parameter VAR30 = 10
)
(
clk,
rst,
VAR16,
VAR42,
VAR35
);
function integer VAR28;
input [31:0] VAR3;
reg [31:0] VAR33;
begin
VAR33 = VAR3;
for (VAR28=0; VAR33>0; VAR28=VAR28+1)
VAR33 = VAR33>>1;
end
endfunction
localparam VAR17 = VAR28(VAR29);
input clk;
input rst;
input [2*VAR29-... | gpl-3.0 |
sarchar/uart_de0_nano | uart.v | 8,059 | module MODULE1
VAR21 = 5,
VAR10 = 1,
VAR29 = 0,
VAR14 = 8)
(input reset,
input VAR16,
input [7:0] VAR2,
input VAR19,
output reg VAR35,
output wire VAR40,
output reg VAR17,
input VAR13,
input VAR31,
output wire VAR3,
output reg [7:0] VAR11,
output reg VAR30);
localparam VAR25 = VAR4(VAR20);
reg [VAR25-1:0] VAR8;
localpa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.v | 2,160 | module MODULE2 (
VAR5 ,
VAR6 ,
VAR8,
VAR1,
VAR4 ,
VAR2
);
output VAR5 ;
input VAR6 ;
input VAR8;
input VAR1;
input VAR4 ;
input VAR2 ;
VAR3 VAR7 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR5,
VAR6
);
output VAR5;
input VAR6;
supply1 VAR8;
supply0 VAR1;... | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/adapter_ppfifo_2_ppfifo.v | 3,583 | module MODULE1#(
parameter VAR9 = 32
)(
input clk,
input rst,
input VAR7,
output reg VAR4,
input [23:0] VAR1,
input [VAR9 - 1:0] VAR3,
output reg VAR5,
input [1:0] VAR12,
output reg [1:0] VAR10,
input [23:0] VAR11,
output reg VAR13,
output [VAR9 - 1:0] VAR2
);
reg [23:0] VAR8;
reg [23:0] VAR6;
assign VAR2 = VAR3;
alway... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/small_async_fifo.v | 6,640 | module MODULE4
parameter VAR31 = 8,
parameter VAR9 = 3,
parameter VAR2 = 5,
parameter VAR35 = 3
)
(
output VAR11,
output VAR28,
input [VAR31-1:0] VAR17,
input VAR23, VAR3, VAR42,
output [VAR31-1:0] VAR5,
output VAR38,
output VAR12,
input VAR27, VAR8, VAR22
);
wire [VAR9-1:0] VAR1, VAR20;
wire [VAR9:0] VAR29, VAR40, VAR... | apache-2.0 |
lvd2/ngs | cpld/cpld3_onlyclock/GS_3032.v | 2,251 | module MODULE1(
VAR45, VAR38, VAR22, VAR28, VAR47,
VAR54, VAR33, VAR40, VAR14, VAR34,
VAR18,VAR13,VAR11,VAR41, VAR8,VAR42, VAR49,VAR50, VAR4,VAR1,
VAR52,VAR29, VAR46,VAR31,
VAR20,VAR27,
VAR19,
VAR16,
VAR44 );
output VAR45; reg VAR45;
input VAR38;
input VAR22;
output VAR28; reg VAR28;
input VAR47;
input VAR54;
input VAR... | gpl-3.0 |
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