repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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Pylonight/Washing-Machine | washing_machine/counter.v | 1,193 | module MODULE1(
input VAR3,
input VAR6,
input VAR1,
input [7:0] VAR4,
input VAR2,
output reg [7:0] VAR5,
output VAR8
);
reg VAR7;
begin
begin
begin
begin
end
begin
begin
begin | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_burst_tracking.v | 4,593 | module MODULE1
parameter
VAR9 = 7,
VAR6 = 6,
VAR8 = 4
)
(
VAR10,
VAR3,
VAR5,
VAR7,
VAR13,
VAR11,
VAR1,
VAR2
);
input VAR10;
input VAR3;
input VAR5;
input VAR7;
output [VAR9-1:0] VAR13;
output [VAR9-1:0] VAR11;
input VAR1;
input [VAR8-1:0] VAR2;
wire VAR10;
wire VAR3;
wire VAR5;
wire VAR7;
wire [VAR9-1:0] VAR13;
wire [V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2/sky130_fd_sc_ms__nor2.behavioral.pp.v | 1,783 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR9 ,
VAR13,
VAR7,
VAR11 ,
VAR8
);
output VAR3 ;
input VAR6 ;
input VAR9 ;
input VAR13;
input VAR7;
input VAR11 ;
input VAR8 ;
wire VAR1 ;
wire VAR4;
nor VAR12 (VAR1 , VAR6, VAR9 );
VAR5 VAR10 (VAR4, VAR1, VAR13, VAR7);
buf VAR2 (VAR3 , VAR4 );
endmodule | apache-2.0 |
redfern314/RFIDuino | verilog/mchester_decode.v | 1,499 | module MODULE1(
input VAR6,
input VAR7,
input VAR4,
input VAR2,
output reg [44:0] VAR8,
output reg VAR11
);
reg VAR10;
integer VAR3;
integer VAR1;
reg VAR9, VAR5; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgndnovpb/sky130_fd_sc_ls__tapvgndnovpb.symbol.v | 1,240 | module MODULE1 ();
supply1 VAR3;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
alan4186/ParCNN | Hardware/v/nh_shift_reg.v | 3,072 | module MODULE2(
input VAR9,
input reset,
input VAR1,
input [VAR15:0] VAR2,
output VAR7,
output [VAR15:0] VAR26
);
wire [(VAR12*2)-2:0] VAR6;
wire [VAR15:0] VAR5 [VAR23-1:0];
wire [VAR15+1:0] VAR8 [VAR16-1:0];
reg [VAR15+1:0] VAR19 [VAR23-1:0][VAR23-1:0];
assign VAR7 = VAR6[0];
always@(posedge VAR9 or negedge reset) beg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31a/sky130_fd_sc_hs__o31a.behavioral.pp.v | 1,916 | module MODULE1 (
VAR10,
VAR12,
VAR14 ,
VAR3 ,
VAR8 ,
VAR6 ,
VAR11
);
input VAR10;
input VAR12;
output VAR14 ;
input VAR3 ;
input VAR8 ;
input VAR6 ;
input VAR11 ;
wire VAR11 VAR9 ;
wire VAR5 ;
wire VAR1;
or VAR15 (VAR9 , VAR8, VAR3, VAR6 );
and VAR7 (VAR5 , VAR9, VAR11 );
VAR2 VAR4 (VAR1, VAR5, VAR10, VAR12);
buf VAR13... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_16/bsg_misc/bsg_mux.v | 1,149 | module MODULE1 #(
parameter VAR9(VAR21 ),
parameter VAR9(VAR24 ),
parameter VAR16 = 1,
parameter VAR26 = 0,
parameter VAR17 = VAR13(VAR24)
) (
input [VAR24-1:0][VAR21-1:0] VAR27,
input [VAR17-1:0] VAR23,
output [VAR21-1:0] VAR25
);
if (VAR16 && VAR26 && (VAR24==2) && (VAR21==1))
begin: VAR30
logic VAR29;
VAR4 VAR31 (
.... | bsd-3-clause |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_JTAG_UART.v | 17,138 | module MODULE3 (
clk,
VAR46,
VAR42,
VAR1,
VAR29,
VAR27,
VAR55
)
;
output VAR1;
output [ 7: 0] VAR29;
output VAR27;
output [ 5: 0] VAR55;
input clk;
input [ 7: 0] VAR46;
input VAR42;
wire VAR1;
wire [ 7: 0] VAR29;
wire VAR27;
wire [ 5: 0] VAR55;
always @(posedge clk)
begin
if (VAR42)
("%VAR2", VAR46);
end
assign VAR55 =... | gpl-2.0 |
colinww/spi-core-generator | source/spi_core.v | 5,859 | module MODULE1 (
VAR5, VAR22, VAR11, VAR20, VAR24, VAR12,
VAR15, VAR8, VAR13, VAR3, VAR9, VAR16, VAR1, VAR2
);
parameter VAR18 = 8;
parameter VAR21 = 3;
parameter VAR17 = 3;
input VAR15;
input VAR8; input VAR13; input VAR3; output VAR5; output VAR22; input VAR9; input VAR16; input VAR1;
output VAR11; output VAR20; outp... | gpl-3.0 |
twlostow/dsi-shield | hdl/rtl/pll_drp/pll_drp.v | 4,824 | module MODULE2
(
input VAR37,
input [4:0] VAR40,
input [39:0] VAR7,
input VAR34,
input VAR20,
input [4:0] VAR45,
output reg [39:0] VAR8
);
reg [39:0] VAR5 [0:31];
always@(posedge VAR37)
if(VAR34)
VAR5[VAR40] <= VAR7;
always@(posedge VAR20)
VAR8 <= VAR5[VAR45];
endmodule
module MODULE1
(
input VAR33,
input VAR22,
input ... | lgpl-3.0 |
devinacker/sd2snes | verilog/sd2snes/main.v | 22,860 | module MODULE1(
input VAR323,
input [23:0] VAR249,
input VAR166,
input VAR170,
input VAR58,
inout [7:0] VAR131,
input VAR248,
input VAR92,
output VAR241,
output VAR11,
output VAR155,
input VAR107,
input [7:0] VAR269,
input VAR352,
input VAR37,
inout [15:0] VAR224,
output [22:0] VAR48,
output VAR371,
output VAR184,
outp... | gpl-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/serialInterfaceEngine/lineControlUpdate.v | 3,376 | module MODULE1(VAR2, VAR5, VAR1, VAR4);
input VAR2;
input VAR5;
output [1:0] VAR1;
output [1:0] VAR4;
wire VAR2;
wire VAR5;
reg [1:0] VAR1;
reg [1:0] VAR4;
always @(VAR2)
begin
if (VAR2 == 1'b1)
begin
VAR1 = VAR6;
VAR4 = VAR3;
end
else
begin
VAR1 = VAR3;
VAR4 = VAR6;
end
end
endmodule | gpl-3.0 |
mgohde/MiniMicroII | pipeBreakU.v | 1,076 | module MODULE1(
VAR19,
VAR14,
VAR5,
VAR17,
VAR1,
VAR7,
VAR2,
VAR3,
VAR18,
VAR15,
VAR9,
VAR10,
VAR16,
VAR20,
VAR6,
VAR12,
VAR11,
VAR4,
VAR8,
VAR13
);
input [15:0] VAR19;
input [15:0] VAR14;
input [15:0] VAR5;
input [15:0] VAR17;
input [15:0] VAR1;
output [6:0] VAR7;
output [6:0] VAR2;
output [6:0] VAR3;
output [6:0] VAR... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fa/sky130_fd_sc_hs__fa.blackbox.v | 1,257 | module MODULE1 (
VAR7,
VAR2 ,
VAR3 ,
VAR6 ,
VAR4
);
output VAR7;
output VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR4 ;
supply1 VAR5;
supply0 VAR1;
endmodule | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v | 1,044 | module MODULE1 (
input VAR10,
input VAR12,
input VAR8,
input VAR15,
input VAR18,
input [31:0]VAR19,
output [31:0]VAR3,
output VAR11,
output VAR21,
output VAR6,
output [31:0]VAR17,
output VAR13,
output VAR20,
output [3:0]VAR5
);
wire VAR7;
assign VAR5[3] = VAR21;
assign VAR5[2] = VAR21;
assign VAR5[1] = VAR21;
assign VA... | lgpl-3.0 |
combinatorylogic/soc | backends/small1/hw/rtl/3rdparty/vgafifo.v | 14,719 | module MODULE2 (VAR30, VAR27, VAR47, VAR17, VAR49, VAR24, VAR43, VAR22, VAR14, VAR40);
parameter VAR52 = 7; parameter VAR39 = 16;
input VAR30; input VAR27; input VAR47; input VAR17; input VAR49; input [VAR39 -1:0] VAR24; input VAR43; output [VAR39 -1:0] VAR22;
output VAR14; reg VAR14;
output VAR40; reg VAR40;
reg VAR29... | mit |
chahuja/hilbert-fpga | RAM1.v | 1,410 | module MODULE1(VAR6,VAR7,VAR2,VAR8,VAR4,VAR9,VAR11,VAR1,VAR13);
parameter VAR3 = 32;
input VAR6;
input VAR7;
input VAR2;
input VAR8;
input [VAR3-1:0] VAR4;
input [VAR3-1:0] VAR9;
output reg VAR11;
output [VAR3-1:0] VAR1;
output [VAR3-1:0] VAR13;
reg [VAR3-1:0] VAR12 [0:31];
reg [VAR3-1:0] VAR10 [0:31];
reg [5:0] addr;
... | gpl-2.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/syn/verilog/ANN_ST_WandB.v | 1,417 | module MODULE1 (VAR2, VAR9, VAR7, VAR4, VAR3, clk);
parameter VAR5 = 32;
parameter VAR1 = 13;
parameter VAR8 = 6560;
input[VAR1-1:0] VAR2;
input VAR9;
input[VAR5-1:0] VAR7;
input VAR4;
output reg[VAR5-1:0] VAR3;
input clk;
reg [VAR5-1:0] VAR6[VAR8-1:0];
begin
begin
begin
end | gpl-3.0 |
timofonic/fpga_nes | hw/src/cmn/fifo/fifo.v | 4,188 | module MODULE1
parameter VAR8 = 8,
parameter VAR7 = 3
)
(
input wire clk, input wire reset, input wire VAR6, input wire VAR15, input wire [VAR8-1:0] VAR20, output wire [VAR8-1:0] VAR14, output wire VAR19, output wire VAR16 );
reg [VAR7-1:0] VAR21;
wire [VAR7-1:0] VAR18;
reg [VAR7-1:0] VAR17;
wire [VAR7-1:0] VAR5;
reg V... | bsd-2-clause |
alexforencich/verilog-lfsr | rtl/lfsr_prbs_gen.v | 6,790 | module MODULE1 #
(
parameter VAR3 = 31,
parameter VAR16 = 31'h10000001,
parameter VAR21 = {VAR3{1'b1}},
parameter VAR8 = "VAR2",
parameter VAR11 = 0,
parameter VAR13 = 1,
parameter VAR18 = 8,
parameter VAR4 = "VAR1"
)
(
input wire clk,
input wire rst,
input wire enable,
output wire [VAR18-1:0] VAR10
);
reg [VAR3-1:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221ai/sky130_fd_sc_ms__o221ai_2.v | 2,457 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR12 ,
VAR1 ,
VAR3 ,
VAR4 ,
VAR7,
VAR2,
VAR10 ,
VAR6
);
output VAR9 ;
input VAR5 ;
input VAR12 ;
input VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR7;
input VAR2;
input VAR10 ;
input VAR6 ;
VAR8 VAR11 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_1.behavioral.v | 1,116 | module MODULE1( VAR1, VAR3 );
input VAR1;
output VAR3;
VAR4 VAR5(.VAR1(VAR1),.VAR3(VAR3));
VAR4 VAR2(.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Lab1/sietesegmentos/pruebas.v | 1,321 | module MODULE1;
reg VAR6;
reg VAR3;
reg VAR13;
reg VAR11;
wire VAR10;
wire VAR4;
wire VAR12;
wire VAR5;
wire VAR7;
wire VAR9;
wire VAR8;
VAR1 VAR2 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR13(VAR13),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8)
); | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_4.behavioral.v | 1,317 | module MODULE1( VAR7, VAR6, VAR1, VAR5, VAR2 );
input VAR5, VAR1, VAR6, VAR7;
output VAR2;
VAR4 VAR3(.VAR7(VAR7),.VAR6(VAR6),.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2));
VAR4 VAR8(.VAR7(VAR7),.VAR6(VAR6),.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32oi/sky130_fd_sc_ls__a32oi.functional.v | 1,615 | module MODULE1 (
VAR11 ,
VAR3,
VAR8,
VAR2,
VAR13,
VAR10
);
output VAR11 ;
input VAR3;
input VAR8;
input VAR2;
input VAR13;
input VAR10;
wire VAR7 ;
wire VAR4 ;
wire VAR6;
nand VAR9 (VAR7 , VAR8, VAR3, VAR2 );
nand VAR12 (VAR4 , VAR10, VAR13 );
and VAR5 (VAR6, VAR7, VAR4);
buf VAR1 (VAR11 , VAR6 );
endmodule | apache-2.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001.v | 6,176 | module MODULE1 #(
parameter VAR20 = 34,
parameter VAR5 = 0,
parameter VAR7 = 34,
parameter VAR16 = 0,
parameter VAR4 = 0,
parameter VAR6 = 0,
parameter VAR15 = 1,
parameter VAR12 = 1,
parameter VAR18 = 0,
parameter VAR13 = 34,
parameter VAR8 = 0,
parameter VAR24 = 1,
parameter VAR10 = 0,
parameter VAR25 = 1,
parameter ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor3/sky130_fd_sc_hdll__xor3_1.v | 2,215 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR2 ,
VAR4 ,
VAR1,
VAR9,
VAR10 ,
VAR5
);
output VAR8 ;
input VAR6 ;
input VAR2 ;
input VAR4 ;
input VAR1;
input VAR9;
input VAR10 ;
input VAR5 ;
VAR3 VAR7 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221oi/sky130_fd_sc_lp__a221oi_4.v | 2,457 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR6 ,
VAR1 ,
VAR9 ,
VAR12 ,
VAR3,
VAR4,
VAR8 ,
VAR7
);
output VAR11 ;
input VAR2 ;
input VAR6 ;
input VAR1 ;
input VAR9 ;
input VAR12 ;
input VAR3;
input VAR4;
input VAR8 ;
input VAR7 ;
VAR5 VAR10 (
.VAR11(VAR11),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR3(... | apache-2.0 |
ptracton/wb_soc_template | rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v | 31,968 | module MODULE1 (
VAR66,
VAR63,
VAR18,
VAR31,
VAR33,
VAR39,
VAR75, VAR6,
VAR117,
VAR115,
VAR116,
VAR25, VAR43, VAR82, VAR17, VAR51, VAR76,
VAR77, VAR93, VAR92, VAR44, VAR38, VAR14
);
input VAR66;
output VAR63;
input VAR18;
input VAR31;
input VAR33;
input VAR39;
input [52:0] VAR75;
input VAR6;
output VAR117;
input VAR115... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/bd_0/hdl/bd_c3fe_wrapper.v | 2,892 | module MODULE1
(VAR6,
VAR3,
VAR17,
VAR7,
VAR15,
VAR1,
VAR13,
VAR20,
VAR8,
VAR5,
VAR11,
VAR2,
VAR16,
VAR9,
VAR12,
VAR14,
VAR10,
clk,
VAR19);
input [8:0]VAR6;
input VAR3;
input VAR17;
input [8:0]VAR7;
input VAR15;
input VAR1;
input VAR13;
input [1:0]VAR20;
input VAR8;
input [31:0]VAR5;
input VAR11;
input [1:0]VAR2;
input... | mit |
VectorBlox/PYNQ | Pynq-Z1/vivado/ip/audio_direct_1.0/src/PdmSer.v | 1,801 | module MODULE1(
input clk,
input en,
input [15:0] din,
output VAR7,
output VAR4
);
reg VAR9=0;
reg VAR2=0;
reg VAR8=0;
reg VAR3;
reg [15:0] VAR6, dout;
integer VAR5=0;
integer VAR1=0;
assign VAR7 = VAR2;
assign VAR4 = VAR6[15];
always @(posedge clk)
VAR9 <= en;
always @(posedge clk)
begin
if (VAR9==0)
VAR5 <=0;
end
els... | bsd-3-clause |
eda-globetrotter/PicenoDecoders | extra_credit/decoder4to16.v | 1,421 | module MODULE1 (in,out);
output reg [15:1] out;
input [3:0] in;
reg [3:0] VAR1;
always @(*)
begin
VAR1=~in;
out[1]=in[0] & VAR1[1] & VAR1[2] & VAR1[3];
out[2]=VAR1[0] & in[1] & VAR1[2] & VAR1[3];
out[3]=in[0] & in[1] & VAR1[2] & VAR1[3];
out[4]=VAR1[0] & VAR1[1] & in[2] & VAR1[3];
out[5]=in[0] & VAR1[1] & in[2] & VAR1[... | mit |
monotone-RK/FACE | IEICE-Trans/data_compression/16-way_2-tree/src/ip_dram/clocking/mig_7series_v2_3_iodelay_ctrl.v | 13,630 | module MODULE1 #
(
parameter VAR114 = 100,
parameter VAR93 = "VAR40",
parameter VAR56 = "VAR58",
parameter VAR69 = "VAR48",
parameter VAR50 = "VAR48",
parameter VAR1 = "VAR6",
parameter VAR27 = 1,
parameter VAR102 = "VAR28",
parameter VAR92 = 1,
parameter VAR81 = "VAR6"
)
(
input VAR36,
input VAR42,
input VAR57,
input ... | mit |
DreamSourceLab/DSLogic-hdl | src/ipcore_dir/rfifo.v | 14,008 | module MODULE1(
VAR337,
VAR200,
VAR116,
VAR182,
din,
VAR140,
VAR402,
dout,
VAR168,
VAR404,
VAR152,
VAR127
);
input VAR337;
input VAR200;
input VAR116;
input VAR182;
input [15 : 0] din;
input VAR140;
input VAR402;
output [15 : 0] dout;
output VAR168;
output VAR404;
output [9 : 0] VAR152;
output [9 : 0] VAR127;
VAR108 #(... | gpl-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_47.v | 32,906 | module MODULE2 (
clk,
reset,
VAR212,
VAR234,
VAR105,
VAR140,
VAR79
);
parameter VAR127 = 18;
parameter VAR243 = 47;
parameter VAR32 = 24;
localparam VAR203 = 54;
input clk;
input reset;
input VAR212;
input VAR234;
input [VAR127-1:0] VAR105; output VAR140;
output [VAR127-1:0] VAR79;
localparam VAR160 = 18; localparam VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2b/sky130_fd_sc_lp__nor2b.functional.pp.v | 1,969 | module MODULE1 (
VAR15 ,
VAR10 ,
VAR8 ,
VAR5,
VAR4,
VAR9 ,
VAR1
);
output VAR15 ;
input VAR10 ;
input VAR8 ;
input VAR5;
input VAR4;
input VAR9 ;
input VAR1 ;
wire VAR13 ;
wire VAR2 ;
wire VAR6;
not VAR3 (VAR13 , VAR10 );
and VAR14 (VAR2 , VAR13, VAR8 );
VAR11 VAR7 (VAR6, VAR2, VAR5, VAR4);
buf VAR12 (VAR15 , VAR6 );
e... | apache-2.0 |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_to_uint_0_0/affine_block_ieee754_fp_to_uint_0_0_stub.v | 1,290 | module MODULE1(VAR2, VAR1)
;
input [31:0]VAR2;
output [9:0]VAR1;
endmodule | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/asmi/synthesis/submodules/asmi_asmi_parallel_0.v | 38,504 | module MODULE1
(
addr,
VAR71,
VAR16,
VAR36,
VAR63,
VAR2,
read,
reset) ;
input [23:0] addr;
output VAR71;
input VAR16;
output VAR36;
output [7:0] VAR63;
input VAR2;
input read;
input reset;
tri0 read;
tri0 reset;
wire [2:0] VAR18;
wire [2:0] VAR8;
wire [1:0] VAR177;
wire VAR133;
reg VAR9;
wire VAR179;
wire [23:0] VAR97;... | gpl-3.0 |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/basic_fifo.v | 2,809 | module MODULE1(
VAR17,
VAR7,
VAR3,
VAR13,
VAR1,
VAR9,
VAR10,
VAR2,
VAR6
);
parameter VAR12 = 32;
parameter VAR5 = 6;
input VAR17, VAR7;
input [VAR12-1:0] VAR3;
input VAR13;
output VAR1;
output reg [VAR5:0] VAR9;
output reg [VAR12-1:0] VAR10;
output reg VAR2;
input VAR6;
reg [VAR12-1:0] VAR4 [2**(VAR5)-1:0];
reg [VAR5:0... | gpl-3.0 |
mfkiwl/parallella-platform | hdl/ewrapper_link_txo.v | 10,565 | module MODULE1(
VAR23, VAR3,
reset, VAR18, VAR59, VAR10,
VAR62, VAR65, VAR60,
VAR37, VAR22, VAR42
);
input reset; input VAR18;
input VAR59;
input VAR10;
input [1:0] VAR62;
input [3:0] VAR65;
input [31:0] VAR60;
input [31:0] VAR37;
input [31:0] VAR22;
input VAR42;
output VAR23;
output [71:0] VAR3;
reg VAR52;
reg VAR47;
... | gpl-3.0 |
jotego/jt12 | hdl/adpcm/jt10_adpcm_drvB.v | 3,894 | module MODULE1(
input VAR38,
input clk,
input VAR4, input VAR32, input VAR11, input VAR6, input VAR36, input VAR1, input [ 1:0] VAR12, input [15:0] VAR8, input [15:0] VAR41, input [15:0] VAR17, input [ 7:0] VAR35, output flag,
input VAR34,
output [23:0] addr,
input [ 7:0] VAR9,
output reg VAR14,
output reg signed [15:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4b/sky130_fd_sc_lp__nand4b.pp.blackbox.v | 1,347 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR4 ,
VAR3 ,
VAR7 ,
VAR1,
VAR6,
VAR2 ,
VAR8
);
output VAR9 ;
input VAR5 ;
input VAR4 ;
input VAR3 ;
input VAR7 ;
input VAR1;
input VAR6;
input VAR2 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill_diode/sky130_fd_sc_hs__fill_diode_4.v | 1,901 | module MODULE2 (
VAR2,
VAR5,
VAR3 ,
VAR4
);
input VAR2;
input VAR5;
input VAR3 ;
input VAR4 ;
VAR1 VAR6 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR4 ;
VAR1 VAR6 ();
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1/db/ip/niosII_system/submodules/niosII_system_sysid_qsys_0.v | 1,415 | module MODULE1 (
address,
VAR1,
VAR3,
VAR2
)
;
output [ 31: 0] VAR2;
input address;
input VAR1;
input VAR3;
wire [ 31: 0] VAR2;
assign VAR2 = address ? 1422916944 : 0;
endmodule | gpl-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_p_dst_data_stream_0_V.v | 3,017 | module MODULE1 (
clk,
VAR22,
VAR23,
VAR2,
VAR26);
parameter VAR27 = 32'd8;
parameter VAR3 = 32'd1;
parameter VAR8 = 32'd2;
input clk;
input [VAR27-1:0] VAR22;
input VAR23;
input [VAR3-1:0] VAR2;
output [VAR27-1:0] VAR26;
reg[VAR27-1:0] VAR21 [0:VAR8-1];
integer VAR5;
always @ (posedge clk)
begin
if (VAR23)
begin
for (V... | gpl-3.0 |
545/Atari7800 | core/ag_6502/trunk/juke-box/ag_video.v | 4,566 | module MODULE1(input[10:0] VAR2, input VAR1, output[7:0] VAR4);
reg[7:0] VAR5[0:2047];
assign VAR4 = VAR1?VAR5[VAR2]:8'VAR3; | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2/sky130_fd_sc_hd__mux2.blackbox.v | 1,269 | module MODULE1 (
VAR7 ,
VAR1,
VAR2,
VAR4
);
output VAR7 ;
input VAR1;
input VAR2;
input VAR4 ;
supply1 VAR8;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_cpu_s1_mult_cell.v | 6,320 | module MODULE1 (
VAR43,
VAR3,
clk,
VAR11,
VAR14
)
;
output [ 31: 0] VAR14;
input [ 31: 0] VAR43;
input [ 31: 0] VAR3;
input clk;
input VAR11;
wire [ 31: 0] VAR14;
wire [ 31: 0] VAR16;
wire [ 15: 0] VAR46;
wire VAR55;
assign VAR55 = ~VAR11;
VAR29 VAR45
(
.VAR28 (VAR55),
.VAR38 (clk),
.VAR15 (VAR43[15 : 0]),
.VAR4 (VAR3[... | gpl-2.0 |
fbalakirev/red-pitaya-notes | cores/axis_decimator_v1_0/axis_decimator.v | 2,150 | module MODULE1 #
(
parameter integer VAR15 = 32,
parameter integer VAR20 = 32
)
(
input wire VAR16,
input wire VAR4,
input wire [VAR20-1:0] VAR9,
output wire VAR12,
input wire [VAR15-1:0] VAR8,
input wire VAR14,
input wire VAR17,
output wire [VAR15-1:0] VAR5,
output wire VAR10
);
reg [VAR15-1:0] VAR2, VAR21;
reg [VAR20... | mit |
martinmiranda14/Digitales | Lab_6/new/teclado.v | 5,479 | module MODULE1(
input [7:0] VAR22,
output reg [4:0] VAR25,
output reg [2:0] VAR9,
output [7:0] VAR1
);
localparam VAR3 = 3'd1;
localparam VAR30 = 3'd2;
localparam VAR17 = 3'd3;
localparam VAR23 = 3'd4;
localparam VAR28 = 8'h45;
localparam VAR13 = 8'h16;
localparam VAR2 = 8'h1E;
localparam VAR19 = 8'h26;
localparam VAR2... | apache-2.0 |
ProjectVault/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/ftl_top.v | 7,084 | module MODULE1 (
input wire VAR17,
input wire VAR57,
output wire [9:0] VAR33,
output wire VAR19,
output wire VAR12,
output wire VAR16,
input wire VAR69,
input wire [31:0] VAR3,
output wire [31:0] VAR24,
input wire [31:0] VAR61,
input wire [3:0] VAR2,
input wire VAR43,
input wire VAR45,
input wire VAR39,
output wire VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o31ai/sky130_fd_sc_hdll__o31ai.behavioral.pp.v | 2,047 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR9 ,
VAR5 ,
VAR6 ,
VAR11,
VAR12,
VAR4 ,
VAR13
);
output VAR10 ;
input VAR1 ;
input VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR11;
input VAR12;
input VAR4 ;
input VAR13 ;
wire VAR15 ;
wire VAR8 ;
wire VAR7;
or VAR16 (VAR15 , VAR9, VAR1, VAR5 );
nand VAR17 (VAR8 , VAR6, VAR15 );
VAR3 VAR2... | apache-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_fifo_tracker.v | 8,020 | module MODULE1
(clk, reset, VAR49, VAR18, VAR24, VAR46, VAR48, VAR1, VAR50,
VAR17, VAR51);
parameter VAR13 = 8;
parameter VAR20 = 0;
parameter VAR19 = 0;
parameter VAR7 = 0;
parameter VAR30 = VAR40;
localparam VAR45 = VAR33(VAR13+1);
input clk;
input reset;
input VAR49;
input VAR18;
input VAR24;
output VAR46;
wire VAR4... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invkapwr/sky130_fd_sc_lp__invkapwr.functional.v | 1,275 | module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
wire VAR2;
not VAR4 (VAR2, VAR3 );
buf VAR5 (VAR1 , VAR2 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mux.v | 3,704 | if (VAR31 && VAR1 == VAR19 && VAR4 == VAR17) \
begin: VAR18 \
wire [VAR1-1:0] VAR5 = VAR1 ' (1'b1 << VAR7); \
\
VAR14 VAR42 \
(.* \
, .VAR32(VAR5) \
); \
end
if (VAR13 && VAR31 && (VAR1==4)) \
begin: VAR18 \
wire [VAR4-1:0] VAR33; \
\
\
VAR24 VAR29 (.VAR11 (VAR34[0]) \
,.VAR21(VAR34[1]) \
,.VAR3(VAR34[2]) \
,.VAR6(VAR3... | bsd-3-clause |
intelligenttoasters/CPC2.0 | FPGA/rtl/cpc/a40010.v | 8,740 | module MODULE1(
input VAR3,
input VAR48,
input [15:0] VAR10,
input [7:0] VAR15,
input [7:0] VAR16,
input VAR43,
input VAR44,
input VAR41,
input VAR21,
input VAR39,
output VAR28,
output VAR4,
output [5:0] VAR40,
output [8:0] VAR29,
input [2:0] VAR38,
input VAR22,
output [23:0] VAR6,
input VAR42,
input VAR20
);
wire VAR1... | gpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_reset.v | 19,952 | module MODULE1 #
(
parameter VAR24 = "VAR45", parameter VAR7 = 1, parameter VAR71 = 6'd63, parameter VAR66 = 1
)
(
input VAR5,
input VAR26,
input VAR22,
input VAR23,
input [VAR7-1:0] VAR72,
input [VAR7-1:0] VAR27,
input VAR2,
input [VAR7-1:0] VAR6,
input [VAR7-1:0] VAR14,
input VAR1,
input [VAR7-1:0] VAR19,
input [VAR7... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311a/sky130_fd_sc_lp__o311a.blackbox.v | 1,373 | module MODULE1 (
VAR6 ,
VAR7,
VAR8,
VAR9,
VAR1,
VAR2
);
output VAR6 ;
input VAR7;
input VAR8;
input VAR9;
input VAR1;
input VAR2;
supply1 VAR10;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_ecc_encoder_32_syn.v | 12,982 | module MODULE2 #
( parameter
VAR15 = 0
)
(
clk,
VAR6,
VAR16,
VAR4
) ;
input clk;
input VAR6;
input [31:0] VAR16;
output [38:0] VAR4;
wire [31:0] VAR13;
wire [17:0] VAR12;
wire [9:0] VAR11;
wire [4:0] VAR14;
wire [1:0] VAR5;
wire [0:0] VAR9;
wire [5:0] VAR7;
wire [37:0] VAR8;
wire [37:0] VAR2;
reg [37:0] VAR10;
wire [37... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxtp/sky130_fd_sc_hd__sdfxtp.pp.blackbox.v | 1,363 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR4 ,
VAR2 ,
VAR7 ,
VAR3,
VAR6,
VAR1 ,
VAR9
);
output VAR8 ;
input VAR5 ;
input VAR4 ;
input VAR2 ;
input VAR7 ;
input VAR3;
input VAR6;
input VAR1 ;
input VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor2/sky130_fd_sc_hdll__xnor2.behavioral.pp.v | 1,845 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR3 ,
VAR8,
VAR13,
VAR10 ,
VAR5
);
output VAR4 ;
input VAR9 ;
input VAR3 ;
input VAR8;
input VAR13;
input VAR10 ;
input VAR5 ;
wire VAR7 ;
wire VAR1;
xnor VAR2 (VAR7 , VAR9, VAR3 );
VAR11 VAR6 (VAR1, VAR7, VAR8, VAR13);
buf VAR12 (VAR4 , VAR1 );
endmodule | apache-2.0 |
devinacker/sd2snes | verilog/sd2snes/address.v | 9,774 | module MODULE1(
input VAR11,
input [7:0] VAR39, input [2:0] VAR20, input [23:0] VAR43, input [7:0] VAR6, input VAR9, output [23:0] VAR10, output VAR28, output VAR17, output VAR22, output VAR23, input [23:0] VAR15,
input [23:0] VAR5,
output VAR30,
output VAR8,
output VAR1,
output VAR4,
input [14:0] VAR44,
output VAR18,
... | gpl-2.0 |
mlab-upenn/pvs | hdl_harness/led_flasher.v | 2,167 | module MODULE1
(
clk,
VAR4,
VAR8
);
input clk;
input VAR4;
output VAR8;
parameter VAR5 = 600; parameter VAR3 = 600;
parameter VAR7 = 2'd0;
parameter VAR1 = 2'd1;
parameter VAR2 = 2'd2;
reg[15:0] VAR6 = 0;
reg [1:0] state = 2'd0;
always @(posedge clk) begin
case(state)
VAR7:
begin
VAR6 <= 16'd0;
state <= (VAR4) ? VAR2 :... | gpl-3.0 |
glennchid/font5-firmware | src/verilog/synthesis/ShiftReg.v | 1,291 | module MODULE1(
input clk,
input VAR11,
input signed [12:0] din,
input [4:0] VAR10,
output reg signed [12:0] dout = 13'VAR2
);
parameter VAR4 = 32;
parameter VAR1 = 13'VAR2;
reg signed [12:0] VAR5 [0:VAR4-3];
reg [4:0] VAR3 = 5'd2;
reg VAR9 = 1'b1;
integer VAR8;
integer VAR6;
VAR7 for (VAR6=0; VAR6 < (VAR4-3); VAR6=VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux4/sky130_fd_sc_hs__mux4.symbol.v | 1,332 | module MODULE1 (
input VAR5,
input VAR6,
input VAR2,
input VAR4,
output VAR8 ,
input VAR3,
input VAR9
);
supply1 VAR7;
supply0 VAR1;
endmodule | apache-2.0 |
merckhung/zet | cores/wb_abrg/wb_abrgr.v | 4,126 | module MODULE1 (
input VAR10,
input VAR8,
input [19:1] VAR36,
input [15:0] VAR5,
output reg [15:0] VAR23,
input [ 1:0] VAR9,
input VAR38,
input VAR20,
input VAR6,
input VAR16,
output VAR3,
input VAR34,
output reg [19:1] VAR28,
output reg [15:0] VAR1,
input [15:0] VAR32,
output reg [ 1:0] VAR22,
output reg VAR39,
output... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/iodelay_ctrl.v | 7,544 | module MODULE1 #
(
parameter VAR32 = 100, parameter VAR1 = "VAR15", parameter VAR38 = "VAR34", parameter VAR20 = 1 )
(
input VAR19,
input VAR25,
input VAR12,
input VAR37,
output VAR5
);
localparam VAR29 = 15;
wire VAR16;
wire VAR18;
wire VAR30;
reg [VAR29-1:0] VAR14 ;
wire VAR21;
wire VAR28;
assign VAR28 = VAR20 ? ~VAR... | lgpl-3.0 |
ujamjar/hardcaml-riscv | altera/de0_nano_sdram/hardcaml_lib.v | 2,462 | module MODULE9 #(parameter VAR10=1)
(
input [VAR10-1:0] VAR6,
input [VAR10-1:0] VAR1,
output [VAR10-1:0] VAR3
);
assign VAR3 = VAR6 + VAR1;
endmodule
module MODULE5 #(parameter VAR10=1)
(
input [VAR10-1:0] VAR6,
input [VAR10-1:0] VAR1,
output [VAR10-1:0] VAR3
);
assign VAR3 = VAR6 - VAR1;
endmodule
module MODULE1
param... | mit |
P3Stor/P3Stor | pcie/app/BMD_128_RX_ENGINE.v | 48,486 | module MODULE1 (
clk,
VAR71,
VAR33,
VAR40,
VAR27,
VAR43,
VAR68,
VAR28,
VAR7,
VAR74,
VAR48,
VAR26,
VAR14,
VAR61,
VAR69, VAR36, VAR42, VAR32, VAR8, VAR34, VAR76, VAR51,
VAR67, VAR18, VAR75, VAR54,
VAR35,
VAR47,
VAR57,
VAR59,
VAR6,
VAR49,
VAR11,
VAR41,
VAR25,
VAR65,
VAR66
);
input clk;
input VAR71;
input VAR33;
input [127... | gpl-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_receiveFIFODataOut.v | 1,913 | module MODULE1 (
address,
clk,
VAR5,
VAR3,
VAR6
)
;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input clk;
input [ 8: 0] VAR5;
input VAR3;
wire VAR2;
wire [ 8: 0] VAR1;
wire [ 8: 0] VAR4;
reg [ 31: 0] VAR6;
assign VAR2 = 1;
assign VAR4 = {9 {(address == 0)}} & VAR1;
always @(posedge clk or negedge VAR3)
begin
if (VAR3... | gpl-3.0 |
saiedhk/WhirlpoolHashEngine | whirlpool_wcipher_gamma.v | 6,345 | module MODULE1 (
output [7:0] VAR108, VAR134, VAR109, VAR140, VAR60, VAR29, VAR150, VAR27,
VAR88, VAR48, VAR183, VAR101, VAR73, VAR156, VAR43, VAR76,
VAR53, VAR75, VAR127, VAR136, VAR35, VAR85, VAR142, VAR175,
VAR51, VAR41, VAR146, VAR191, VAR152, VAR124, VAR49, VAR55,
VAR45, VAR23, VAR6, VAR95, VAR179, VAR61, VAR42, V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4bb/sky130_fd_sc_lp__and4bb_lp.v | 2,331 | module MODULE2 (
VAR2 ,
VAR6 ,
VAR11 ,
VAR10 ,
VAR8 ,
VAR7,
VAR5,
VAR9 ,
VAR1
);
output VAR2 ;
input VAR6 ;
input VAR11 ;
input VAR10 ;
input VAR8 ;
input VAR7;
input VAR5;
input VAR9 ;
input VAR1 ;
VAR3 VAR4 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9),
.... | apache-2.0 |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v | 7,627 | module MODULE1 (
VAR22,
VAR1, VAR24, VAR12, VAR44, VAR15, VAR16 );
output [15:0] VAR22;
input VAR1; input [13:0] VAR24; input [15:0] VAR12; input VAR44; input [1:0] VAR15; input VAR16;
parameter [14:0] VAR33 = 15'h0090;
parameter VAR43 = 2;
parameter [VAR43-1:0] VAR4 = 'h0,
VAR41 = 'h1,
VAR6 = 'h2,
VAR26 = 'h3;
paramet... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.v | 2,461 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR2 ,
VAR9 ,
VAR11 ,
VAR4 ,
VAR1,
VAR12,
VAR8 ,
VAR6
);
output VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR9 ;
input VAR11 ;
input VAR4 ;
input VAR1;
input VAR12;
input VAR8 ;
input VAR6 ;
VAR10 VAR3 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR1(VA... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/synthesis/submodules/nios_solo_pio_0.v | 2,443 | module MODULE1 (
address,
VAR4,
clk,
VAR2,
VAR10,
VAR5,
VAR7,
irq,
VAR6
)
;
output irq;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR4;
input clk;
input VAR2;
input VAR10;
input VAR5;
input [ 31: 0] VAR7;
wire VAR8;
wire VAR1;
wire irq;
reg VAR9;
wire VAR3;
reg [ 31: 0] VAR6;
assign VAR8 = 1;
assign VAR3 = ({1... | gpl-3.0 |
YurongYou/MIPS_CPU | MEM_WB.v | 1,372 | module MODULE1 (
input clk,
input rst,
input VAR21,
input[VAR7-1:0] VAR8,
input[VAR28-1:0] VAR5,
input[VAR28-1:0] VAR16,
input VAR25,
input VAR27,
input[VAR28-1:0] VAR17,
input[VAR28-1:0] VAR10,
input VAR26,
input VAR11,
output[VAR7-1:0] VAR19,
output[VAR28-1:0] VAR18,
output[VAR28-1:0] VAR14,
output VAR31,
output VAR2... | mpl-2.0 |
yunqu/PYNQ | boards/ip/io_switch_1.1/hdl/io_switch_v1_1_S_AXI.v | 21,256 | module MODULE1 #
(
parameter VAR56=4, parameter VAR52 = 28,
parameter VAR105 = 6,
parameter VAR77 = 8,
parameter VAR35 = 2,
parameter integer VAR22 = 32,
parameter integer VAR55 = 6
)
(
input [VAR52-1:0] VAR40,
output [VAR52-1:0] VAR39,
output [VAR52-1:0] VAR61,
output [VAR52-1:0] VAR101,
input [VAR52-1:0] VAR103,
inpu... | bsd-3-clause |
richard42/CoCo3FPGA | cocokey.v | 12,865 | module MODULE1(
VAR20,
VAR16, VAR11,
VAR14,
VAR6,
VAR17,
VAR7,
VAR9,
VAR10
);
input VAR20;
input VAR16;
input VAR11;
input VAR14;
input VAR6;
output [55:0] VAR17;
reg [55:0] VAR17;
output VAR7;
reg VAR7;
output VAR9;
reg VAR9;
output VAR10;
reg VAR10;
reg [5:0] VAR8;
wire VAR12;
reg [4:0] VAR5;
wire [7:0] VAR19;
wire V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4/sky130_fd_sc_hdll__nand4.pp.symbol.v | 1,311 | module MODULE1 (
input VAR2 ,
input VAR3 ,
input VAR9 ,
input VAR7 ,
output VAR5 ,
input VAR4 ,
input VAR6,
input VAR1,
input VAR8
);
endmodule | apache-2.0 |
fbalakirev/red-pitaya-notes | cores/axis_oscilloscope_v1_0/axis_oscilloscope.v | 2,940 | module MODULE1 #
(
parameter integer VAR16 = 32,
parameter integer VAR11 = 12
)
(
input wire VAR14,
input wire VAR9,
input wire VAR18,
input wire VAR7,
input wire [VAR11-1:0] VAR13,
input wire [VAR11-1:0] VAR15,
output wire [VAR11:0] VAR10,
output wire VAR19,
input wire [VAR16-1:0] VAR21,
input wire VAR4,
output wire [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s.blackbox.v | 1,321 | module MODULE1 (
VAR4,
VAR5
);
output VAR4;
input VAR5;
supply1 VAR3;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
dvanmali/Superscalar_Pipeline_Processor | globalbranchpredictor.v | 7,187 | module MODULE1(clk,VAR14,VAR4,VAR9,VAR5,VAR12,VAR6,VAR7,VAR15);
input clk;
input [1:0] VAR14,VAR4;
input [63:0] VAR6;
input [31:0] VAR5,VAR12, VAR9;
output reg [31:0] VAR7;
output reg VAR15;
reg [71:0] VAR17[127:0];
reg [31:0] VAR10;
reg [1:0] global;
integer VAR8;
reg VAR3, VAR1; VAR13 begin
global = 2'b00;
for (VAR8=... | apache-2.0 |
parallella/oh | common/hdl/oh_reg0.v | 1,160 | module MODULE1 #(parameter VAR5 = 1 )
( input VAR2, input clk, input [VAR5-1:0] in, output [VAR5-1:0] out );
VAR3 VAR4 [VAR5-1:0] (.VAR2(VAR2),
.clk(clk),
.in(in[VAR5-1:0]),
.out(out[VAR5-1:0]));
reg [VAR5-1:0] VAR1;
always @ (negedge clk or negedge VAR2)
if(~VAR2)
VAR1[VAR5-1:0] <= 'b0;
else
VAR1[VAR5-1:0] <= in[VAR5-... | mit |
sirchuckalot/zet-ng | rtl/v1_3_1/zet_core.v | 6,449 | module MODULE1 (
input clk,
input rst,
input VAR28,
output VAR7,
input VAR81,
output VAR17,
output [19:0] VAR38,
input [15:0] VAR10,
input [15:0] VAR84,
output [15:0] VAR20,
output VAR31,
input VAR78,
output VAR79,
output VAR71,
output VAR45,
output [19:0] VAR22 );
wire [VAR24-1:0] VAR66;
wire [15:0] VAR72;
wire [15:0]... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_addr_cmd_pads.v | 12,938 | module MODULE1(
VAR52,
VAR21,
VAR26,
VAR49,
VAR62,
VAR44,
VAR16,
VAR73,
VAR70,
VAR3,
VAR79,
VAR28,
VAR9,
VAR75,
VAR92,
VAR64,
VAR25,
VAR51,
VAR69,
VAR109,
VAR63,
VAR83,
VAR15,
VAR68,
VAR99,
VAR90,
VAR100
);
parameter VAR85 = "";
parameter VAR7 = "";
parameter VAR23 = "";
parameter VAR17 = "";
parameter VAR11 = "";
para... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32ai/sky130_fd_sc_hs__o32ai.behavioral.pp.v | 2,092 | module MODULE1 (
VAR7,
VAR8,
VAR6 ,
VAR1 ,
VAR9 ,
VAR10 ,
VAR18 ,
VAR13
);
input VAR7;
input VAR8;
output VAR6 ;
input VAR1 ;
input VAR9 ;
input VAR10 ;
input VAR18 ;
input VAR13 ;
wire VAR18 VAR5 ;
wire VAR18 VAR16 ;
wire VAR12 ;
wire VAR15;
nor VAR3 (VAR5 , VAR10, VAR1, VAR9 );
nor VAR14 (VAR16 , VAR18, VAR13 );
or V... | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/altera_up_av_config_auto_init_ob_de2_115.v | 7,268 | module MODULE1 (
VAR16,
VAR12
);
parameter VAR8 = 9'h01A;
parameter VAR1 = 9'h01A;
parameter VAR10 = 9'h07B;
parameter VAR9 = 9'h07B;
parameter VAR13 = 9'h0F8;
parameter VAR11 = 9'h006;
parameter VAR14 = 9'h000;
parameter VAR5 = 9'h001;
parameter VAR2 = 9'h002;
parameter VAR3 = 9'h001;
input [ 5: 0] VAR16;
output [26: ... | gpl-2.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/Verilog_Xilinx_Port/sources/hdl/main_pll_2x.v | 2,645 | module MODULE1(VAR8,
VAR12,
VAR34,
VAR10,
VAR40);
input VAR8;
output VAR12;
output VAR34;
output VAR10;
output VAR40;
wire VAR51;
wire VAR57;
wire VAR19;
wire VAR42;
wire VAR41;
assign VAR41 = 0;
assign VAR12 = VAR57;
assign VAR34 = VAR51;
VAR18 VAR27 (.VAR11(VAR8),
.VAR14(VAR57));
VAR20 VAR3 (.VAR11(VAR19),
.VAR14(VAR... | gpl-3.0 |
ychaim/FPGA-Litecoin-Miner | source/altera_virtual_wire.v | 1,865 | module MODULE1 (VAR7, VAR22);
parameter VAR15 = 1;
parameter VAR9 = 1;
parameter VAR12 = " 0";
parameter VAR5 = "VAR14";
input [0:VAR9-1] VAR7;
output [0:VAR15-1] VAR22;
assign VAR22 = 0;
VAR1 VAR33 (
.VAR7 (VAR7),
.VAR22 (VAR22)
,
.VAR13 (),
.VAR29 (),
.VAR8 (),
.VAR17 (),
.VAR30 (),
.VAR31 (),
.VAR24 (),
.VAR25 (),
.... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_1.behavioral.v | 2,716 | module MODULE1( VAR11, VAR20, VAR6, VAR9 );
input VAR6, VAR20, VAR11;
output VAR9;
reg VAR21;
VAR15 VAR4(.VAR11(VAR11),.VAR20(VAR20),.VAR6(VAR6),.VAR9(VAR9),.VAR21(VAR21));
VAR15 VAR16(.VAR11(VAR11),.VAR20(VAR20),.VAR6(VAR6),.VAR9(VAR9),.VAR21(VAR21));
not VAR7(VAR5,VAR20);
not VAR2(VAR23,VAR11);
and VAR17(VAR8,VAR23,V... | apache-2.0 |
ILoveSpeccy/Aeon-Lite | cores/radio-86rk/src/k580wt57.v | 3,914 | module MODULE1(
input clk,
input VAR3,
input reset,
input[3:0] VAR27,
input[7:0] VAR23,
input[3:0] VAR22,
input VAR6,
input VAR20,
input VAR5,
output VAR8,
output reg[3:0] VAR13,
output[7:0] VAR15,
output[15:0] VAR28,
output VAR1,
output VAR31,
output VAR11,
output VAR33 );
parameter VAR7 = 3'b000;
parameter VAR25 = 3'... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4/sky130_fd_sc_ls__and4.symbol.v | 1,288 | module MODULE1 (
input VAR3,
input VAR6,
input VAR7,
input VAR9,
output VAR2
);
supply1 VAR1;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probe_p/sky130_fd_sc_hd__probe_p.pp.symbol.v | 1,277 | module MODULE1 (
input VAR5 ,
output VAR1 ,
input VAR2 ,
input VAR4,
input VAR6,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3b/sky130_fd_sc_hd__and3b.functional.pp.v | 1,961 | module MODULE1 (
VAR16 ,
VAR13 ,
VAR1 ,
VAR11 ,
VAR6,
VAR5,
VAR7 ,
VAR12
);
output VAR16 ;
input VAR13 ;
input VAR1 ;
input VAR11 ;
input VAR6;
input VAR5;
input VAR7 ;
input VAR12 ;
wire VAR14 ;
wire VAR8 ;
wire VAR9;
not VAR2 (VAR14 , VAR13 );
and VAR10 (VAR8 , VAR11, VAR14, VAR1 );
VAR3 VAR15 (VAR9, VAR8, VAR6, VAR5... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_2.behavioral.v | 1,098 | module MODULE1( VAR5, VAR2 );
input VAR5;
output VAR2;
VAR4 VAR1(.VAR5(VAR5),.VAR2(VAR2));
VAR4 VAR3(.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric.behavioral.pp.v | 1,962 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR8 ,
VAR4 ,
VAR12,
VAR2 ,
VAR7
);
output VAR3 ;
input VAR11 ;
input VAR8 ;
input VAR4 ;
input VAR12;
input VAR2 ;
input VAR7 ;
wire VAR6;
wire VAR5 ;
VAR1 VAR13 (VAR6, VAR11, VAR12, VAR4 );
buf VAR9 (VAR5 , VAR6 );
VAR1 VAR10 (VAR3 , VAR5, VAR8, VAR4);
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9265/axi_ad9265_channel.v | 6,557 | module MODULE1 (
VAR27,
VAR26,
VAR68,
VAR76,
VAR77,
VAR75,
VAR61,
VAR55,
VAR28,
VAR58,
VAR43,
VAR3,
VAR49,
VAR78,
VAR63,
VAR74,
VAR6,
VAR32,
VAR66,
VAR70);
parameter VAR42 = 0;
parameter VAR59 = 0;
input VAR27;
input VAR26;
input [15:0] VAR68;
input VAR76;
output [15:0] VAR77;
output VAR75;
output VAR61;
output VAR55;
... | gpl-3.0 |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axis_dwidth_converter_0_0/axis_dwidth_converter_v1_1/hdl/verilog/axis_dwidth_converter_v1_1_axisc_upsizer.v | 14,818 | module MODULE1 #
(
parameter VAR19 = "VAR52",
parameter integer VAR8 = 32,
parameter integer VAR26 = 96,
parameter integer VAR65 = 1,
parameter integer VAR16 = 1,
parameter integer VAR18 = 1,
parameter integer VAR58 = 3,
parameter [31:0] VAR42 = 32'hFF ,
parameter integer VAR3 = 3 )
(
input wire VAR59,
input wire VAR24... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_hvc_wpad/sky130_fd_io__top_power_hvc_wpad.pp.blackbox.v | 1,893 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR9 ,
VAR12 ,
VAR1 ,
VAR3,
VAR10 ,
VAR8 ,
VAR5 ,
VAR14 ,
VAR13 ,
VAR17 ,
VAR11 ,
VAR15 ,
VAR7 ,
VAR16 ,
VAR4
);
inout VAR2 ;
inout VAR6 ;
inout VAR9 ;
inout VAR12 ;
inout VAR1 ;
inout VAR3;
inout VAR10 ;
inout VAR8 ;
inout VAR5 ;
inout VAR14 ;
inout VAR13 ;
inout VAR17 ;
inout VAR11 ;
in... | apache-2.0 |
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