repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/altera_primitives.v | 35,174 | module MODULE5 (in, out);
input in;
output out;
assign out = in;
endmodule
module MODULE1 (in, out);
input in;
output out;
assign out = in;
endmodule
module MODULE8 (in, out);
input in;
output out;
assign out = in;
endmodule
module MODULE11 (VAR9, VAR5, VAR19, VAR8);
input VAR9;
input VAR5;
output VAR19;
output VAR8;
a... | gpl-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/2-instruction_decode/control_unit.v | 6,026 | module MODULE1
parameter VAR2=32 )
(
input wire [5:0] VAR7,
input wire [5:0] VAR16,
output wire VAR13,
output wire VAR14,
output wire VAR5,
output wire VAR15,
output wire VAR10,
output wire VAR4,
output wire VAR12,
output wire [5:0] VAR9,
output wire VAR17,
output wire VAR1
);
wire [7:0] VAR8; wire [4:0] VAR3; wire [1:... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/dram_ddr_rptr_south.v | 4,423 | module MODULE1 (
VAR16, VAR24, VAR13,
VAR19, VAR5, VAR23,
VAR8, VAR6,
VAR10, VAR15,
VAR18, VAR9, VAR1,
VAR29, VAR25, VAR32,
VAR35, VAR2,
VAR31, VAR33, VAR17,
VAR14, VAR21, VAR28,
VAR34, VAR4, VAR12,
VAR11, VAR30, VAR27,
VAR26, VAR36, VAR7, VAR20,
VAR3, VAR22
);
output VAR16;
output [31:0] VAR24;
output [255:0] VAR13;
o... | gpl-2.0 |
olajep/oh | src/common/hdl/oh_7seg_decode.v | 1,335 | module MODULE1 ( input [3:0] VAR8, output VAR3, output VAR4, output VAR7, output VAR5, output VAR2, output VAR1, output VAR6 );
reg VAR3,VAR4,VAR7,VAR5,VAR2,VAR1,VAR6;
always @ (*)
case(VAR8[3:0])
4'h0 : {VAR3,VAR4,VAR7,VAR5,VAR2,VAR1,VAR6} = 7'b0000001;
4'h1 : {VAR3,VAR4,VAR7,VAR5,VAR2,VAR1,VAR6} = 7'b1001111;
4'h2 : ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4bb/sky130_fd_sc_hs__nand4bb_4.v | 2,207 | module MODULE2 (
VAR3 ,
VAR1 ,
VAR6 ,
VAR8 ,
VAR2 ,
VAR9,
VAR5
);
output VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR9;
input VAR5;
VAR7 VAR4 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR3 ,
VAR1,
VAR6,
VAR8 ,
VAR2
)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_hl_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.pp.symbol.v | 1,581 | module MODULE1 (
input VAR5 ,
output VAR2 ,
input VAR1 ,
input VAR3 ,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_3/ff169405/src/AXI4DataDriver.v | 4,384 | module MODULE1
(
parameter VAR7 = 32 ,
parameter VAR16 = 32 ,
parameter VAR12 = 8
)
(
VAR14 ,
VAR2 ,
VAR5 ,
VAR3 ,
VAR13 ,
VAR6 ,
VAR10 ,
VAR19 ,
VAR15 ,
VAR18 ,
VAR1 ,
VAR21
);
input VAR14 ;
input VAR2 ;
input [VAR12 - 1:0] VAR5 ;
input VAR3 ;
output VAR13 ;
input [VAR16 - 1:0] VAR6 ;
input VAR10 ;
output VAR19 ;
outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/buf/sky130_fd_sc_ms__buf.functional.pp.v | 1,746 | module MODULE1 (
VAR12 ,
VAR4 ,
VAR6,
VAR2,
VAR9 ,
VAR1
);
output VAR12 ;
input VAR4 ;
input VAR6;
input VAR2;
input VAR9 ;
input VAR1 ;
wire VAR11 ;
wire VAR3;
buf VAR7 (VAR11 , VAR4 );
VAR5 VAR10 (VAR3, VAR11, VAR6, VAR2);
buf VAR8 (VAR12 , VAR3 );
endmodule | apache-2.0 |
hoglet67/opc | system/src/system.v | 5,367 | module MODULE1 ( input clk, input[7:0] VAR9, output[7:0] VAR63, input VAR50, output VAR32,
output [6:0] VAR48, output [3:0] VAR28, input select);
parameter VAR30 = 32000000;
parameter VAR62 = 2;
parameter VAR47 = 2;
parameter VAR1 = 115200;
parameter VAR7 = 0;
parameter VAR34 = 32;
parameter VAR59 = 20;
parameter VAR16... | gpl-3.0 |
ShepardSiegel/ocpi | rtl/mkPWrk_n210.v | 58,189 | module MODULE1(VAR343,
VAR252,
VAR211,
VAR119,
VAR318,
VAR296,
VAR81,
VAR342,
VAR138,
VAR68,
VAR41,
VAR169,
VAR310,
VAR171,
VAR188,
VAR175,
VAR166,
VAR60,
VAR241,
VAR20,
VAR28);
input VAR343;
input VAR252;
input VAR211;
inout VAR119;
inout VAR318;
output [47 : 0] VAR296;
output VAR81;
input [2 : 0] VAR342;
input VAR138... | lgpl-3.0 |
merckhung/zet | cores/zet/rtl/zet_othop.v | 2,372 | module MODULE1 (VAR20, VAR19, VAR18, VAR13, VAR7, VAR5, VAR12, out, VAR6);
input [15:0] VAR20, VAR19, VAR13, VAR18, VAR7;
input [2:0] VAR5;
input VAR12;
output [19:0] out;
output [8:0] VAR6;
wire [15:0] VAR11, VAR17, VAR9, VAR4, VAR16, VAR8, VAR1;
wire [19:0] VAR3, VAR15;
wire VAR2;
VAR10 VAR14 (VAR5, VAR3[15:0], VAR15... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpio_ovtv2/sky130_fd_io__top_gpio_ovtv2.functional.v | 33,275 | module MODULE1 ( VAR150, VAR70, VAR93, VAR157, VAR33,
VAR134, VAR149, VAR152, VAR87, VAR20,
VAR68, VAR144, VAR85, VAR56, VAR26, VAR129, VAR122, VAR22, VAR34, VAR154,
VAR29, VAR35, VAR78, VAR138, VAR16, VAR145, VAR71, VAR83, VAR104, VAR38 );
input VAR16;
input VAR138;
input VAR154;
input VAR26;
input VAR129;
input VAR12... | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/dc_req_upload.v | 2,678 | module MODULE1( clk,
rst,
VAR2,
VAR14,
VAR5,
VAR13,
VAR4,
VAR6,
VAR3
);
input clk;
input rst;
input [47:0] VAR2;
input VAR14;
input VAR5;
output [15:0] VAR13;
output VAR4;
output [1:0] VAR6;
output VAR3;
parameter VAR1=1'b0;
parameter VAR9=1'b1;
reg VAR8;
reg [47:0] VAR10;
reg [1:0] VAR11;
reg VAR4;
reg VAR15;
reg VAR1... | apache-2.0 |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/rom.v | 3,620 | module MODULE1(
input wire[15:0] VAR1,
output reg[31:0] VAR2
);
always @(*) begin
case (VAR1)
0: VAR2 = 32'h00000000;
4: VAR2 = 32'h10000001;
8: VAR2 = 32'h00000000;
12: VAR2 = 32'h3c08beff;
16: VAR2 = 32'h3508fff8;
20: VAR2 = 32'h240900ff;
24: VAR2 = 32'had090000;
28: VAR2 = 32'h3c10be00;
32: VAR2 = 32'h240f0000;
36: ... | unlicense |
Elphel/x353 | sensor/sensortrig.v | 12,318 | module MODULE1 (VAR68,
VAR7, VAR4, VAR29, VAR17, VAR49, VAR52, VAR64, VAR70, VAR1, VAR80, VAR23, VAR69, VAR32, VAR65, VAR19, VAR6, VAR43, VAR58, VAR83,
VAR76, VAR71, VAR25
);
input VAR68;
input VAR7;
input VAR4;
input VAR29;
input [15:0] VAR49;
input [ 7:0] VAR52; input [ 2:0] VAR64;
input VAR17; input VAR70;
input VAR... | gpl-3.0 |
lbl-cal/StanfordNoC | router/src/clib/c_rotate.v | 2,671 | module MODULE1
(VAR5, VAR4, VAR9);
parameter VAR3 = 8;
parameter VAR10 = VAR6;
localparam VAR8 = VAR7(VAR3);
input [0:VAR3-1] VAR4;
input [0:VAR8-1] VAR5;
output [0:VAR3-1] VAR9;
wire [0:VAR3-1] VAR9;
wire [0:(2*VAR3-1)-1] VAR2;
wire [0:(2*VAR3-1)-1] VAR1;
generate
case (VAR10)
begin
assign VAR2 = {VAR4, VAR4[0:(VAR3-1... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311a/sky130_fd_sc_lp__o311a_lp.v | 2,430 | module MODULE2 (
VAR1 ,
VAR8 ,
VAR10 ,
VAR7 ,
VAR12 ,
VAR4 ,
VAR2,
VAR6,
VAR11 ,
VAR5
);
output VAR1 ;
input VAR8 ;
input VAR10 ;
input VAR7 ;
input VAR12 ;
input VAR4 ;
input VAR2;
input VAR6;
input VAR11 ;
input VAR5 ;
VAR3 VAR9 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR2... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/generic/adapter_axi_stream_2_ppfifo.v | 4,318 | module MODULE1 #(
parameter VAR10 = 32,
parameter VAR17 = VAR10 / 8,
parameter VAR14 = 0
)(
input rst,
input VAR19,
output VAR4,
input [VAR10 - 1:0] VAR1,
input [VAR17 - 1:0] VAR13,
input VAR3,
input VAR12,
output VAR6,
input [1:0] VAR5,
output reg [1:0] VAR7,
input [23:0] VAR2,
output reg VAR18,
output reg [VAR10 - 1:... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/erase_ram.v | 7,458 | module MODULE1 (
address,
VAR9,
VAR61,
VAR10,
VAR28
);
parameter VAR40 = "VAR1 VAR32";
parameter VAR55 = 8;
parameter VAR41 = 416;
localparam VAR42 = VAR22(VAR41); localparam VAR47 = 2**VAR42;
input [VAR42-1:0] address;
input VAR9;
input [VAR55-1:0] VAR61;
input VAR10;
output [VAR55-1:0] VAR28;
tri1 VAR9;
wire [VAR55-1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3b/sky130_fd_sc_hd__nand3b.pp.symbol.v | 1,313 | module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR5 ,
output VAR8 ,
input VAR1 ,
input VAR2,
input VAR3,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22o/sky130_fd_sc_hvl__a22o.blackbox.v | 1,360 | module MODULE1 (
VAR1 ,
VAR3,
VAR7,
VAR5,
VAR9
);
output VAR1 ;
input VAR3;
input VAR7;
input VAR5;
input VAR9;
supply1 VAR8;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/video/video_sync_v.v | 2,374 | module MODULE1(
input wire clk,
input wire VAR2, input wire VAR13,
input wire VAR8,
input wire VAR17,
output reg VAR14,
output reg VAR5,
output reg VAR3,
output reg VAR18 );
localparam VAR12 = 9'd00;
localparam VAR6 = 9'd08;
localparam VAR9 = 9'd11;
localparam VAR4 = 9'd32;
localparam VAR16 = 9'd0;
localparam VAR7 = 9'... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_base/address.v | 10,453 | module MODULE1(
input VAR2,
input [15:0] VAR1, input [2:0] VAR23, input [23:0] VAR26, input VAR17,
input [7:0] VAR54, input VAR61, output [23:0] VAR3, output VAR45, output VAR41, output VAR40, output VAR13, output VAR38, input [7:0] VAR39,
input [23:0] VAR22,
input [23:0] VAR53,
input VAR7,
input VAR10,
input VAR34,
in... | gpl-2.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/ip/clk_bluetooth/clk_bluetooth.v | 4,106 | module MODULE1
(
output VAR3,
output VAR6,
input VAR4,
output VAR1,
input VAR5
);
VAR2 VAR7
(
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule | gpl-3.0 |
brabect1/risc8 | verif/hdl/verilog/exp.v | 4,856 | module MODULE1 (
clk,
reset,
VAR11,
VAR7,
VAR3,
VAR8,
VAR9,
VAR2
);
input clk;
input reset;
output [7:0] VAR11;
output [7:0] VAR7; input [7:0] VAR3; input [6:0] VAR8; input VAR9; input VAR2;
reg [7:0] VAR7;
reg [7:0] VAR11;
reg [7:0] VAR5;
reg [0:0] VAR6;
reg [9:0] VAR10;
reg [7:0] VAR4;
reg [7:0] VAR1 [0:1023]; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp.behavioral.pp.v | 2,984 | module MODULE1 (
VAR4 ,
VAR27 ,
VAR20 ,
VAR10 ,
VAR17 ,
VAR8,
VAR9 ,
VAR1 ,
VAR31 ,
VAR23
);
output VAR4 ;
input VAR27 ;
input VAR20 ;
input VAR10 ;
input VAR17 ;
input VAR8;
input VAR9 ;
input VAR1 ;
input VAR31 ;
input VAR23 ;
wire VAR11 ;
wire VAR13 ;
wire VAR6 ;
reg VAR29 ;
wire VAR26 ;
wire VAR14 ;
wire VAR2 ;
wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfsbp/sky130_fd_sc_ls__dfsbp.functional.pp.v | 1,956 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR1 ,
VAR13 ,
VAR3,
VAR11 ,
VAR16 ,
VAR5 ,
VAR4
);
output VAR8 ;
output VAR7 ;
input VAR1 ;
input VAR13 ;
input VAR3;
input VAR11 ;
input VAR16 ;
input VAR5 ;
input VAR4 ;
wire VAR2;
wire VAR15 ;
not VAR9 (VAR15 , VAR3 );
VAR10 VAR12 VAR14 (VAR2 , VAR13, VAR1, VAR15, , VAR11, VAR16);
buf... | apache-2.0 |
alexforencich/verilog-ethernet | example/DE2-115/fpga/rtl/fpga.v | 6,454 | module MODULE1 (
input wire VAR6,
input wire [3:0] VAR36,
input wire [17:0] VAR48,
output wire [8:0] VAR168,
output wire [17:0] VAR145,
output wire [6:0] VAR19,
output wire [6:0] VAR118,
output wire [6:0] VAR1,
output wire [6:0] VAR96,
output wire [6:0] VAR18,
output wire [6:0] VAR72,
output wire [6:0] VAR80,
output wi... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_2.behavioral.pp.v | 1,476 | module MODULE1( VAR8, VAR4, VAR7, VAR6, VAR3 );
input VAR4, VAR8;
inout VAR6, VAR3;
output VAR7;
VAR1 VAR5(.VAR8(VAR8),.VAR4(VAR4),.VAR7(VAR7),.VAR6(VAR6),.VAR3(VAR3));
VAR1 VAR2(.VAR8(VAR8),.VAR4(VAR4),.VAR7(VAR7),.VAR6(VAR6),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31ai/sky130_fd_sc_hs__o31ai_1.v | 2,208 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR5 ,
VAR2 ,
VAR1 ,
VAR8,
VAR7
);
output VAR6 ;
input VAR3 ;
input VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR8;
input VAR7;
VAR4 VAR9 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR6 ,
VAR3,
VAR5,
VAR2,
VAR1
);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3.pp.symbol.v | 1,324 | module MODULE1 (
input VAR4 ,
output VAR1 ,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
kulp/tenyr | hw/verilog/top.v | 5,450 | module MODULE1(
input clk, reset, inout VAR121,
output[7:0] VAR101, output[3:0] VAR145, inout[23:0] VAR26,
output[2:0] VAR42, VAR64, output[2:1] VAR99, output VAR155, VAR89, VAR17
);
parameter VAR8 = 13;
wire VAR149, VAR72, VAR102, VAR52;
wire VAR90, VAR14, VAR150, VAR88;
wire[3:0] VAR123, VAR115;
wire VAR9, VAR20, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221o/sky130_fd_sc_ms__a221o.pp.symbol.v | 1,401 | module MODULE1 (
input VAR4 ,
input VAR3 ,
input VAR6 ,
input VAR9 ,
input VAR1 ,
output VAR5 ,
input VAR10 ,
input VAR2,
input VAR8,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311a/sky130_fd_sc_hs__o311a.functional.pp.v | 1,954 | module MODULE1 (
VAR13,
VAR15,
VAR16 ,
VAR4 ,
VAR5 ,
VAR10 ,
VAR1 ,
VAR11
);
input VAR13;
input VAR15;
output VAR16 ;
input VAR4 ;
input VAR5 ;
input VAR10 ;
input VAR1 ;
input VAR11 ;
wire VAR1 VAR12 ;
wire VAR14 ;
wire VAR3;
or VAR7 (VAR12 , VAR5, VAR4, VAR10 );
and VAR2 (VAR14 , VAR12, VAR1, VAR11 );
VAR6 VAR8 (VAR3... | apache-2.0 |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/fmlbrg.v | 11,103 | module MODULE1 #(
parameter VAR12 = 23,
parameter VAR15 = 9 )
(
input VAR14,
input VAR3,
input [VAR12-1:1] VAR19,
input [15:0] VAR11,
output [15:0] VAR13,
input [ 1:0] VAR22,
input VAR16,
input VAR6,
input VAR18,
input VAR23,
output reg VAR17,
output reg [VAR12-1:0] VAR25,
output reg VAR5,
output reg VAR27,
input VAR2,... | gpl-3.0 |
brianbennett/fpga_nes | hw/src/nes_top.v | 8,308 | module MODULE1
(
input wire VAR103, input wire VAR121, input wire VAR93, input wire VAR35, input wire [3:0] VAR75, input wire VAR30, input wire VAR5, output wire VAR65, output wire VAR96, output wire VAR32, output wire [2:0] VAR79, output wire [2:0] VAR127, output wire [1:0] VAR15, output wire VAR17, output wire VAR108... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32ai/sky130_fd_sc_ms__o32ai.pp.blackbox.v | 1,425 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR9 ,
VAR5 ,
VAR1 ,
VAR2 ,
VAR4,
VAR7,
VAR3 ,
VAR10
);
output VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR5 ;
input VAR1 ;
input VAR2 ;
input VAR4;
input VAR7;
input VAR3 ;
input VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111ai/sky130_fd_sc_ms__o2111ai.symbol.v | 1,401 | module MODULE1 (
input VAR2,
input VAR4,
input VAR1,
input VAR10,
input VAR6,
output VAR7
);
supply1 VAR8;
supply0 VAR5;
supply1 VAR9 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvp/sky130_fd_sc_hd__einvp.pp.symbol.v | 1,329 | module MODULE1 (
input VAR1 ,
output VAR5 ,
input VAR6 ,
input VAR3 ,
input VAR7,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufinv/sky130_fd_sc_lp__bufinv.pp.symbol.v | 1,272 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR2 ,
input VAR3,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_phy_init.v | 198,065 | module MODULE1 #
(
parameter VAR131 = 1500, parameter VAR66 = 100,
parameter VAR123 = 4, parameter VAR325 = 3000, parameter VAR16 = 0, parameter VAR140 = "150", parameter VAR386 = "VAR144", parameter VAR47 = 8, parameter VAR361 = 2,
parameter VAR73 = "VAR206", parameter VAR36 = 10,
parameter VAR380 = 1, parameter VAR22... | bsd-2-clause |
drom/quark | src/tail_length.v | 1,924 | <%
var = VAR1();
var VAR2 = .logic(4);
var VAR4 = .logic(3);
var VAR4 = {
'??00': '0001',
'1?0?': '0001',
'0001': '0010',
'0010': '0100',
'0011': '1000'
};
%>
module MODULE1 (VAR2, VAR4);
input [3:0] VAR2;
output [3:0] VAR4;
reg [3:0] VAR4;
reg VAR3;
always @ (VAR2)
begin
VAR4 = {
(VAR2 == 4'b0011),
(VAR2 == 4'b0010),... | mit |
omicronns/studies-sys-rek | de1-soc-template/v/I2C_Controller.v | 4,278 | module MODULE1 (
VAR4,
VAR3, VAR5, VAR15, VAR16, VAR10, VAR18, VAR7, VAR8
);
input VAR4;
input [31:0]VAR15;
input VAR16;
input VAR8;
input VAR18;
inout VAR5;
output VAR3;
output VAR10;
output VAR7;
reg VAR13;
reg VAR6;
reg VAR10;
reg [31:0]VAR1;
reg [6:0]VAR12;
wire VAR3=VAR6 | ( ((VAR12 >= 4) & (VAR12 <=39))? ~VAR4 :0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41oi/sky130_fd_sc_hs__a41oi.blackbox.v | 1,354 | module MODULE1 (
VAR1 ,
VAR5,
VAR4,
VAR8,
VAR3,
VAR2
);
output VAR1 ;
input VAR5;
input VAR4;
input VAR8;
input VAR3;
input VAR2;
supply1 VAR6;
supply0 VAR7;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2a/sky130_fd_sc_hd__o2bb2a.pp.blackbox.v | 1,400 | module MODULE1 (
VAR6 ,
VAR1,
VAR5,
VAR7 ,
VAR2 ,
VAR3,
VAR8,
VAR9 ,
VAR4
);
output VAR6 ;
input VAR1;
input VAR5;
input VAR7 ;
input VAR2 ;
input VAR3;
input VAR8;
input VAR9 ;
input VAR4 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_40.v | 26,401 | module MODULE1 (
clk,
reset,
VAR74,
VAR70,
VAR217,
VAR145,
VAR76
);
parameter VAR154 = 18;
parameter VAR126 = 40;
parameter VAR202 = 20;
localparam VAR178 = 41;
input clk;
input reset;
input VAR74;
input VAR70;
input [VAR154-1:0] VAR217; output VAR145;
output [VAR154-1:0] VAR76;
localparam VAR85 = 18; localparam VAR196... | mit |
skatpgusskat/KoreaUnivHomework_2015_1 | Computer Architecture/Homework/Lab10/control_units.v | 1,873 | module MODULE1(clk, VAR8, VAR11, VAR2, VAR4, VAR7, VAR3, VAR1, VAR5, VAR9, VAR6, VAR10);
input clk, VAR8;
input [5:0] VAR11;
output VAR2, VAR4, VAR7, VAR1, VAR5, VAR9, VAR6, VAR10;
reg VAR2, VAR4, VAR7, VAR1, VAR5, VAR9, VAR6, VAR10;
output [1:0] VAR3;
reg [1:0] VAR3;
always @(VAR11)
begin
case (VAR11)
6'b100011: begin... | mit |
sehugg/8bitworkshop | presets/verilog/ram.v | 1,896 | module MODULE1(clk, addr, din, dout, VAR4);
parameter VAR1 = 10; parameter VAR2 = 8;
input clk; input [VAR1-1:0] addr; input [VAR2-1:0] din; input VAR4;
output reg [VAR2-1:0] dout;
reg [VAR2-1:0] VAR5 [0:(1<<VAR1)-1];
always @(posedge clk) begin
if (VAR4) VAR5[addr] <= din; dout <= VAR5[addr]; end
endmodule
module MODU... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22a/sky130_fd_sc_hd__o22a.functional.pp.v | 2,156 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR19 ,
VAR2 ,
VAR8 ,
VAR10,
VAR3,
VAR14 ,
VAR11
);
output VAR5 ;
input VAR1 ;
input VAR19 ;
input VAR2 ;
input VAR8 ;
input VAR10;
input VAR3;
input VAR14 ;
input VAR11 ;
wire VAR9 ;
wire VAR7 ;
wire VAR18 ;
wire VAR13;
or VAR16 (VAR9 , VAR19, VAR1 );
or VAR4 (VAR7 , VAR8, VAR2 );
and VA... | apache-2.0 |
lbl-cal/StanfordNoC | router/src/router_wrap.v | 9,721 | module MODULE1
(clk, reset, VAR19, VAR34, VAR10, VAR52,
VAR42, VAR1);
localparam VAR11 = VAR70 * VAR48;
localparam VAR74 = VAR11 * VAR40;
localparam VAR27 = VAR71(VAR74);
localparam VAR16
= (VAR14 + VAR64 - 1) / VAR64;
localparam VAR36 = VAR54(VAR16, VAR76);
localparam VAR47 = VAR71(VAR36);
localparam VAR4 = VAR76 * VA... | bsd-2-clause |
wyvernSemi/lm32fpga | HDL/rtl/I2C_Controller.v | 4,793 | module MODULE1 (
clk,
VAR4,
VAR20, VAR18, VAR15,
VAR3,
VAR13, VAR10, VAR1, VAR7, VAR12
);
parameter VAR14 = 50000; parameter VAR19 = 20;
parameter VAR9 = (VAR14 / VAR19)-1;
input clk;
input VAR4;
input [23:0] VAR3;
input VAR13;
input VAR1;
output VAR10;
output VAR7;
output VAR12;
output VAR18;
input VAR15;
output VAR20... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/buf/sky130_fd_sc_hs__buf.pp.symbol.v | 1,203 | module MODULE1 (
input VAR4 ,
output VAR3 ,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_reset_controller.v | 12,017 | module MODULE1
parameter VAR67 = 6,
parameter VAR68 = 0,
parameter VAR41 = 0,
parameter VAR19 = 0,
parameter VAR42 = 0,
parameter VAR34 = 0,
parameter VAR74 = 0,
parameter VAR32 = 0,
parameter VAR1 = 0,
parameter VAR2 = 0,
parameter VAR7 = 0,
parameter VAR13 = 0,
parameter VAR79 = 0,
parameter VAR6 = 0,
parameter VAR60... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_1.behavioral.pp.v | 1,164 | module MODULE1( VAR6, VAR7, VAR3, VAR1 );
input VAR6;
inout VAR3, VAR1;
output VAR7;
VAR4 VAR2(.VAR6(VAR6),.VAR7(VAR7),.VAR3(VAR3),.VAR1(VAR1));
VAR4 VAR5(.VAR6(VAR6),.VAR7(VAR7),.VAR3(VAR3),.VAR1(VAR1)); | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/MULT_PEAK/MULT_PEAK.v | 4,395 | module MODULE1 (
VAR4,
VAR6,
VAR3);
input [59:0] VAR4;
input [49:0] VAR6;
output [109:0] VAR3;
wire [109:0] VAR19;
wire [109:0] VAR3 = VAR19[109:0];
VAR17 VAR15 (
.VAR4 (VAR4),
.VAR6 (VAR6),
.VAR3 (VAR19),
.VAR9 (1'b0),
.VAR18 (1'b1),
.VAR12 (1'b0),
.sum (1'b0));
VAR15.VAR10 = "VAR1=VAR2,VAR11=1",
VAR15.VAR14 = "VAR16... | gpl-2.0 |
ZipCPU/wbuart32 | rtl/rxuartlite.v | 21,442 | module MODULE1 #(
parameter VAR52 = 10,
parameter [(VAR52-1):0] VAR7 = 16, else
parameter [(VAR52-1):0] VAR7 = 868, VAR16
localparam VAR26 = VAR52,
localparam [3:0] VAR1 = 4'h0,
localparam [3:0] VAR20 = 4'h1,
localparam [3:0] VAR53 = 4'h2,
localparam [3:0] VAR35 = 4'h3,
localparam [3:0] VAR27 = 4'h4,
localparam [3:0] V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbp/sky130_fd_sc_ms__dfbbp.pp.symbol.v | 1,474 | module MODULE1 (
input VAR10 ,
output VAR3 ,
output VAR2 ,
input VAR7,
input VAR1 ,
input VAR4 ,
input VAR8 ,
input VAR6 ,
input VAR9 ,
input VAR5
);
endmodule | apache-2.0 |
m-labs/milkymist | cores/vgafb/rtl/vgafb_ctlif.v | 3,361 | module MODULE1 #(
parameter VAR25 = 4'h0,
parameter VAR20 = 26
) (
input VAR6,
input VAR12,
input [13:0] VAR19,
input VAR26,
input [31:0] VAR5,
output reg [31:0] VAR13,
output reg VAR21,
output reg [10:0] VAR23,
output reg [10:0] VAR4,
output reg [10:0] VAR16,
output reg [10:0] VAR22,
output reg [10:0] VAR24,
output re... | lgpl-3.0 |
alan4186/Hardware-CNN | Hardware/v/fm_coord_sr.v | 1,237 | module MODULE1 (
input VAR7,
input reset,
input [VAR10:0] VAR6, input [VAR5:0] VAR9, output [VAR10:0] VAR12, output [VAR5:0] VAR14 );
reg [VAR10:0] VAR1 [VAR4-1:0];
reg [VAR5:0] VAR8 [VAR4-1:0];
assign VAR12 = VAR1[VAR4-1];
assign VAR14 = VAR8[VAR4-1];
always@(posedge VAR7 or negedge reset) begin
if(reset == 1'b0) begi... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dmac_v1_00_a/hdl/verilog/src_axi_stream.v | 4,026 | module MODULE1 (
input VAR4,
input VAR6,
input enable,
output VAR31,
input VAR36,
output VAR12,
input [VAR23-1:0] VAR7,
output [VAR23-1:0] VAR14,
input VAR16,
output VAR15,
input VAR34,
input [VAR20-1:0] VAR1,
input [0:0] VAR22,
input VAR27,
output VAR17,
output [VAR20-1:0] VAR26,
input VAR10,
output VAR13,
input [3:0]... | mit |
csturton/wirepatch | system/hardware/cores/or1200/or1200_top.v | 24,618 | module MODULE1(
VAR118, VAR162, VAR174, VAR147,
VAR125, VAR199, VAR39, VAR100, VAR336, VAR36,
VAR139, VAR419, VAR95, VAR65, VAR19, VAR299,
VAR145,
VAR283, VAR222,
VAR301, VAR146, VAR282, VAR264, VAR221, VAR355,
VAR373, VAR158, VAR71, VAR390, VAR318, VAR379,
VAR34,
VAR151, VAR136,
VAR354, VAR28, VAR79, VAR353, VAR397, V... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_modeling.v | 67,608 | module MODULE1(
clk ,
VAR72 ,
VAR118 ,
VAR60 ,
VAR189 ,
VAR52 ,
VAR54 ,
VAR115 ,
VAR170 ,
VAR9 ,
VAR151 ,
VAR136 ,
VAR128 ,
VAR30 ,
VAR196 ,
VAR25 ,
VAR70 ,
VAR100 ,
VAR194 ,
VAR204 ,
VAR21 ,
VAR156 ,
VAR96 ,
VAR63 ,
VAR133 ,
VAR147 ,
VAR111 ,
VAR174 ,
VAR103 ,
VAR38 ,
VAR2
);
input clk ; input VAR72 ;
input [10:0] VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbp/sky130_fd_sc_hd__dlrbp.pp.blackbox.v | 1,440 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR4,
VAR1 ,
VAR9 ,
VAR7 ,
VAR8 ,
VAR3 ,
VAR6
);
output VAR2 ;
output VAR5 ;
input VAR4;
input VAR1 ;
input VAR9 ;
input VAR7 ;
input VAR8 ;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_dbg/rtl/jbi_dbg_ctl.v | 15,341 | module MODULE1(
VAR53, VAR54, VAR24, VAR27,
VAR31, VAR71, VAR88, VAR86,
VAR50, VAR60, VAR36, VAR79,
VAR93, VAR61,
clk, VAR26, VAR96, VAR23, VAR76,
VAR10, VAR22, VAR67,
VAR87, VAR34,
VAR65, VAR113,
VAR57, VAR48,
VAR98, VAR107, VAR63
); input clk;
input VAR26;
input VAR96;
input VAR23;
input [47:0] VAR76;
input VAR10;
in... | gpl-2.0 |
gtaylormb/opl3_fpga | fpga/bd/opl3_cpu/ipshared/xilinx.com/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v | 3,389 | module MODULE1(
VAR57,
VAR49,
VAR15,
VAR23,
VAR55,
VAR47,
VAR39,
VAR66,
VAR61,
VAR60,
VAR44,
VAR51,
VAR9,
VAR4,
VAR14,
VAR26,
VAR30,
VAR28,
VAR2,
VAR16,
VAR43,
VAR33,
VAR38,
VAR31,
VAR56,
VAR29,
VAR5,
VAR65,
VAR54,
VAR45,
VAR36,
VAR37,
VAR41,
VAR7,
VAR27,
VAR18,
VAR42,
VAR8
);
input VAR57;
input VAR49;
input [VAR20-1:0... | lgpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x1_125/example_design/PIO.v | 7,293 | module MODULE1 (
VAR25,
VAR4,
VAR18,
VAR21,
VAR14,
VAR23,
VAR20,
VAR26,
VAR30,
VAR13,
VAR11,
VAR34,
VAR6,
VAR12,
VAR5,
VAR19,
VAR33,
VAR24,
VAR27,
VAR10,
VAR2,
VAR15,
VAR31
);
input VAR25;
input VAR4;
input VAR18;
output [63:0] VAR21;
output [7:0] VAR14;
output VAR23;
output VAR20;
output VAR26;
output VAR30;
input VAR... | lgpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v | 11,711 | module MODULE1 #(
parameter VAR43 = 28,
parameter VAR71 = 1
)
(
output [1:0] VAR13,
output [15:0] VAR6,
output VAR29,
output VAR74,
output [ 2:0] VAR48,
output VAR55,
input [1:0] VAR20,
input [15:0] VAR39,
input VAR7,
input VAR63,
input [ 2:0] VAR2,
input VAR51,
input VAR41,
input VAR53,
input VAR57,
input VAR50
);
loc... | lgpl-3.0 |
hcabrera-/lancetfish | RTL/shared/verif/sink.v | 6,116 | module MODULE1 #(
parameter VAR7 = 5,
parameter VAR21 = VAR15,
parameter VAR12 = 0
)
(
input wire clk,
input wire [VAR5-1:0] VAR1,
output reg VAR2
);
localparam VAR11 = 65;
reg [12*8:0] VAR6;
reg [4*8:0] VAR16;
reg VAR10 VAR20;
reg [17:0] VAR3;
reg [11:0] VAR9;
reg [31:0] VAR22;
reg [31:0] VAR8;
reg [31:0] VAR18;
reg [... | gpl-3.0 |
slongfield/StereoCensus | verilog/lib/dff.v | 1,121 | module MODULE1#(
parameter VAR3 = 1
) (
input wire clk,
input wire rst,
input wire [VAR3-1:0] VAR2,
output reg [VAR3-1:0] VAR1
);
always @(posedge clk) begin
VAR1 <= rst ? 0 : VAR2;
end
endmodule | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_clk_gen/bsg_rp_clk_gen_coarse_delay_tuner.v | 2,184 | module MODULE1
(input VAR22
, input [1:0] VAR26
, input VAR17
, input VAR6
, output VAR5
);
wire [1:0] VAR11;
wire [8:0] VAR33;
assign VAR33[0] = VAR22;
VAR35 VAR8 (.VAR36(VAR33[0]), .VAR9(VAR33[1]) );
VAR35 VAR16 (.VAR36(VAR33[1]), .VAR9(VAR33[2]) );
VAR18 VAR12 (.VAR36(VAR33[1]), .VAR9() );
VAR35 VAR32 (.VAR36(VAR33[... | bsd-3-clause |
olajep/oh | src/adi/hdl/library/axi_dmac/axi_dmac.v | 22,016 | module MODULE1 #(
parameter VAR62 = 0,
parameter VAR230 = 64,
parameter VAR189 = 64,
parameter VAR67 = 24,
parameter VAR49 = 0,
parameter VAR217 = 1,
parameter VAR43 = 1,
parameter VAR11 = 1,
parameter VAR169 = 0,
parameter VAR168 = 0,
parameter VAR129 = 0,
parameter VAR233 = 1,
parameter VAR219 = 0,
parameter VAR269 =... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvn/sky130_fd_sc_hdll__einvn.pp.symbol.v | 1,337 | module MODULE1 (
input VAR5 ,
output VAR4 ,
input VAR6,
input VAR7 ,
input VAR1,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/phy_rddata_sync.v | 23,751 | module MODULE1 #
(
parameter VAR9 = 100, parameter VAR50 = 64, parameter VAR37 = 8, parameter VAR34 = 8, parameter VAR32 = 4, parameter VAR43 = 4, parameter VAR70 = 4, parameter VAR4 = 4, parameter VAR54 = 32'h03020100, parameter VAR68 = 32'h07060504, parameter VAR36 = 0, parameter VAR55 = 0 )
(
input clk,
input [3:0] ... | mit |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/hls_contrast_stretch.v | 40,496 | module MODULE1 (
VAR365,
VAR270,
VAR253,
VAR324,
VAR370,
VAR352,
VAR82,
VAR465,
VAR264,
VAR320,
VAR88,
VAR183,
VAR205,
VAR126,
VAR51,
VAR37,
VAR114,
VAR239,
VAR398,
VAR426,
VAR99,
VAR211,
VAR47,
VAR323,
VAR383,
VAR428,
VAR392,
VAR362,
VAR263,
VAR199,
VAR458,
VAR356,
VAR70,
VAR9,
VAR414,
VAR441,
VAR202
);
parameter VAR3... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_delay_cntrl.v | 6,713 | module MODULE1 (
VAR1,
VAR11,
VAR4,
VAR18,
VAR15,
VAR16,
VAR23,
VAR8,
VAR32,
VAR6,
VAR19,
VAR2,
VAR30,
VAR12,
VAR5,
VAR31);
parameter VAR28 = 8;
parameter VAR25 = 6'h02;
input VAR1;
output VAR11;
input VAR4;
output [(VAR28-1):0] VAR18;
output [((VAR28*5)-1):0] VAR15;
input [((VAR28*5)-1):0] VAR16;
input VAR23;
input VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221a/sky130_fd_sc_ls__o221a_1.v | 2,444 | module MODULE2 (
VAR11 ,
VAR10 ,
VAR2 ,
VAR12 ,
VAR4 ,
VAR1 ,
VAR8,
VAR3,
VAR5 ,
VAR7
);
output VAR11 ;
input VAR10 ;
input VAR2 ;
input VAR12 ;
input VAR4 ;
input VAR1 ;
input VAR8;
input VAR3;
input VAR5 ;
input VAR7 ;
VAR6 VAR9 (
.VAR11(VAR11),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR1(VAR1),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/diode/sky130_fd_sc_ls__diode_2.v | 1,978 | module MODULE1 (
VAR1,
VAR3 ,
VAR2 ,
VAR6 ,
VAR5
);
input VAR1;
input VAR3 ;
input VAR2 ;
input VAR6 ;
input VAR5 ;
VAR7 VAR4 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR1
);
input VAR1;
supply1 VAR3;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR5 ;
VAR7 VAR4 (
.VAR1(VA... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v | 9,218 | module MODULE1(
VAR80,
VAR57,
VAR72,
VAR40,
VAR59,
VAR50,
VAR95,
VAR55,
VAR62,
VAR85,
VAR19,
VAR89,
VAR30,
VAR82,
VAR21,
VAR56,
VAR26,
VAR73,
VAR33,
VAR122,
VAR52,
VAR91,
VAR67,
VAR29,
VAR12,
VAR103,
VAR115,
VAR51,
VAR108
);
parameter VAR60 = "";
parameter VAR7 = "";
parameter VAR93 = "";
parameter VAR70 = "";
paramete... | gpl-3.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_serdes_clk.v | 4,908 | module MODULE1 (
VAR2,
VAR4,
VAR6,
clk,
VAR9,
VAR3,
VAR38,
VAR13,
VAR31,
VAR39,
VAR7,
VAR5,
VAR28,
VAR33);
parameter VAR22 = 1;
parameter VAR27 = 1;
parameter VAR16 = 0;
parameter VAR25 = 1.667;
parameter VAR35 = 6;
parameter VAR21 = 12.000;
parameter VAR11 = 2.000;
parameter VAR17 = 6;
input VAR2;
input VAR4;
input VA... | lgpl-3.0 |
rkrajnc/minimig-mist | rtl/minimig/userio_osd_spi.v | 3,471 | module MODULE1
(
input clk, input VAR4,
input VAR6,
input VAR2, input VAR13, output VAR10, input VAR3, input [7:0] in, output reg [7:0] out, output reg VAR1, output reg VAR11, output VAR7 );
reg [2:0] VAR16; reg [7:0] VAR9; reg [7:0] VAR8;
reg VAR14; reg VAR15; reg VAR12;
reg VAR17=0, VAR5=0;
always @ (posedge clk) beg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/decap/sky130_fd_sc_hs__decap.pp.blackbox.v | 1,147 | module MODULE1 (
VAR1,
VAR2
);
input VAR1;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s.pp.symbol.v | 1,358 | module MODULE1 (
input VAR1 ,
output VAR5 ,
input VAR6 ,
input VAR3,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
chinnytp/proxmark3 | fpga/hi_iso14443a.v | 19,155 | module MODULE1(
VAR54, VAR56, VAR47,
VAR8, VAR30, VAR50, VAR24, VAR62, VAR13,
VAR14, VAR59,
VAR28, VAR29, VAR67, VAR34,
VAR41, VAR25,
VAR9,
VAR23
);
input VAR54, VAR56, VAR47;
output VAR8, VAR30, VAR50, VAR24, VAR62, VAR13;
input [7:0] VAR14;
output VAR59;
input VAR67;
output VAR28, VAR29, VAR34;
input VAR41, VAR25;
ou... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2/sky130_fd_sc_hdll__nand2.blackbox.v | 1,247 | module MODULE1 (
VAR4,
VAR7,
VAR1
);
output VAR4;
input VAR7;
input VAR1;
supply1 VAR2;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22a/sky130_fd_sc_hs__o22a.functional.pp.v | 2,057 | module MODULE1 (
VAR3,
VAR16,
VAR4 ,
VAR12 ,
VAR11 ,
VAR14 ,
VAR10
);
input VAR3;
input VAR16;
output VAR4 ;
input VAR12 ;
input VAR11 ;
input VAR14 ;
input VAR10 ;
wire VAR10 VAR5 ;
wire VAR10 VAR9 ;
wire VAR7 ;
wire VAR6;
or VAR15 (VAR5 , VAR11, VAR12 );
or VAR1 (VAR9 , VAR10, VAR14 );
and VAR2 (VAR7 , VAR5, VAR9 );
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ai/sky130_fd_sc_hdll__o21ai.blackbox.v | 1,342 | module MODULE1 (
VAR3 ,
VAR1,
VAR5,
VAR7
);
output VAR3 ;
input VAR1;
input VAR5;
input VAR7;
supply1 VAR2;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
MeshSr/onetswitch20 | ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/core/tx_queue.v | 11,988 | module MODULE1
parameter VAR23 = 64,
parameter VAR54 = VAR23/8,
parameter VAR52 = 1,
parameter VAR43 = 'hff,
parameter VAR21 = 32,
parameter VAR46 = VAR21/8
)
(input [VAR23-1:0] VAR37,
input [VAR54-1:0] VAR29,
input VAR33,
output VAR22,
input VAR32,
output reg VAR55,
output [VAR21 - 1 : 0] VAR25,
output reg VAR15,
outp... | lgpl-2.1 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_pcie_brams_7x.v | 9,076 | module MODULE1
parameter [3:0] VAR25 = 4'h1, parameter [5:0] VAR6 = 6'h08, parameter VAR1 = "VAR9",
parameter VAR2 = 0,
parameter VAR26 = 1,
parameter VAR8 = 1,
parameter VAR16 = 1
)
(
input VAR11,
input VAR17,
input VAR22,
input [12:0] VAR20,
input [71:0] VAR4,
input VAR19,
input VAR15,
input [12:0] VAR13,
output [71:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor2/sky130_fd_sc_hdll__xnor2.behavioral.v | 1,409 | module MODULE1 (
VAR3,
VAR4,
VAR9
);
output VAR3;
input VAR4;
input VAR9;
supply1 VAR8;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR10 ;
wire VAR7;
xnor VAR1 (VAR7, VAR4, VAR9 );
buf VAR6 (VAR3 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tap/sky130_fd_sc_hs__tap.behavioral.pp.v | 1,138 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
jotego/jt51 | hdl/jt51_pg.v | 9,207 | module MODULE1(
input rst,
input clk,
input VAR6 ,
input VAR36,
input [6:0] VAR7,
input [5:0] VAR4,
input [3:0] VAR17,
input [2:0] VAR70,
input [1:0] VAR20,
input [7:0] VAR44,
input [2:0] VAR69,
input VAR25,
output reg [ 4:0] VAR9,
output [ 9:0] VAR37
,output [19:0] VAR15
,output [12:0] VAR22
);
wire [19:0] VAR21;
reg ... | gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_streaming_top.v | 37,806 | module MODULE1
parameter VAR246 = "VAR215",
parameter VAR243 = 1,
parameter VAR237 = 32,
parameter VAR174 = 1 ,
parameter VAR219 = 1 ,
parameter VAR60 = 1 ,
parameter VAR89 = 1 ,
parameter VAR72 = 32,
parameter VAR139 = 8,
parameter VAR71 = 1,
parameter VAR43 = 1,
parameter VAR103 = 1,
parameter VAR93 = 1,
parameter VA... | gpl-3.0 |
theapi/nand2tetris_fpga | hack/ip/pll/pll/pll_0002.v | 2,136 | module MODULE1(
input wire VAR40,
input wire rst,
output wire VAR35,
output wire VAR44,
output wire VAR20
);
VAR23 #(
.VAR12("false"),
.VAR19("50.0 VAR14"),
.VAR3("VAR10"),
.VAR58(2),
.VAR43("25.000000 VAR14"),
.VAR48("0 VAR60"),
.VAR15(50),
.VAR42("100.000000 VAR14"),
.VAR38("0 VAR60"),
.VAR69(50),
.VAR29("0 VAR14"),
... | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_cpu_s0_jtag_debug_module_wrapper.v | 10,200 | module MODULE1 (
VAR39,
VAR8,
clk,
VAR14,
VAR55,
VAR38,
VAR7,
VAR32,
VAR16,
VAR52,
VAR26,
VAR44,
VAR60,
VAR45,
VAR6,
VAR27,
VAR1,
VAR20,
VAR10,
VAR21,
VAR5,
VAR29,
VAR41,
VAR47,
VAR31,
VAR15,
VAR17,
VAR23,
VAR34,
VAR2,
VAR25,
VAR53,
VAR24,
VAR54,
VAR4,
VAR3
)
;
output [ 37: 0] VAR5;
output VAR29;
output VAR41;
output V... | gpl-2.0 |
bargei/NoC264 | NoC264_3x3/mkInputArbiter.v | 8,265 | module MODULE1(VAR46,
VAR36,
VAR21,
select,
VAR43);
input VAR46;
input VAR36;
input [4 : 0] VAR21;
output [4 : 0] select;
input VAR43;
wire [4 : 0] select;
reg [4 : 0] VAR35;
wire [4 : 0] VAR32;
wire VAR17;
wire [1 : 0] VAR44,
VAR30,
VAR8,
VAR29,
VAR33,
VAR13,
VAR47,
VAR20,
VAR15,
VAR3;
wire VAR28,
VAR38,
VAR50,
VAR7,
... | mit |
Triple-Z/COExperiment_Repo | Project_Assignment_OnBoard/regfile.v | 4,878 | module MODULE1(
input clk,
input VAR5,
input [4 :0] VAR2,
input [4 :0] VAR9,
input [4 :0] VAR1,
input [31:0] VAR3,
output reg [31:0] VAR8,
output reg [31:0] VAR6,
input [4 :0] VAR7,
output reg [31:0] VAR10
);
reg [31:0] VAR4[31:0];
always @(posedge clk)
begin
if (VAR5)
begin
VAR4[VAR1] <= VAR3;
end
end
always @
begin
c... | mit |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_misc.v | 8,385 | module MODULE1 #
(
parameter VAR20 = 0 )
(
input wire VAR9 , input wire VAR2 , input wire VAR29 , input wire VAR28 , input wire [2:0] VAR10 , input wire VAR5 ,
output wire VAR11 , output wire VAR26 , output wire VAR13 , output wire VAR6 , output wire [2:0] VAR27 , output wire VAR4 ,
input wire VAR16 , input wire VAR24 ... | lgpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/spw_babasu_TIME_IN.v | 2,181 | module MODULE1 (
address,
VAR7,
clk,
VAR4,
VAR2,
VAR6,
VAR3,
VAR9
)
;
output [ 7: 0] VAR3;
output [ 31: 0] VAR9;
input [ 1: 0] address;
input VAR7;
input clk;
input VAR4;
input VAR2;
input [ 31: 0] VAR6;
wire VAR1;
reg [ 7: 0] VAR5;
wire [ 7: 0] VAR3;
wire [ 7: 0] VAR8;
wire [ 31: 0] VAR9;
assign VAR1 = 1;
assign VAR8 ... | gpl-3.0 |
zKarp/Karpentium-Processor | src/verilog/random_access_memory.v | 1,241 | module MODULE1#(parameter VAR5=1, parameter VAR4=1)(clk,address,VAR8,enable,VAR2,VAR3);
parameter VAR6 = (2**VAR5);
integer VAR1;
input clk, enable,VAR2,VAR3;
input [VAR5-1:0]address; inout [VAR4-1:0]VAR8; reg [VAR4-1:0]VAR7 [VAR6-1:0];
begin | gpl-2.0 |
lokisz/openzcore | pippo-0.9/rtl/verilog/reg_gpr.v | 4,850 | module MODULE1(
clk, rst,
VAR23, VAR18, VAR38, VAR4,
VAR35, VAR26, VAR46, VAR29, VAR37, VAR31,
VAR17, VAR39, VAR51, VAR14, VAR10, VAR50, VAR3, VAR40, VAR9
);
parameter VAR47 = VAR5;
parameter VAR27 = VAR45;
input clk;
input rst;
input VAR23;
input VAR18;
input [VAR27-1:0] VAR17;
input [VAR27-1:0] VAR39;
input [VAR27-1:... | gpl-2.0 |
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