repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3.pp.blackbox.v | 1,309 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR6,
VAR5,
VAR2 ,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR6;
input VAR5;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_8.behavioral.pp.v | 1,246 | module MODULE1( VAR7, VAR6, VAR4, VAR5, VAR2 );
input VAR7, VAR6;
inout VAR5, VAR2;
output VAR4;
VAR1 VAR3(.VAR7(VAR7),.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2));
VAR1 VAR8(.VAR7(VAR7),.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.behavioral.pp.v | 3,847 | module MODULE1( VAR5, VAR26, VAR11, VAR13, VAR27, VAR9 );
input VAR5, VAR26, VAR11;
inout VAR27, VAR9;
output VAR13;
reg VAR24;
VAR1 VAR16(.VAR5(VAR5),.VAR26(VAR26),.VAR11(VAR11),.VAR13(VAR13),.VAR27(VAR27),.VAR9(VAR9),.VAR24(VAR24));
VAR1 VAR10(.VAR5(VAR5),.VAR26(VAR26),.VAR11(VAR11),.VAR13(VAR13),.VAR27(VAR27),.VAR9(... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_arb_select.v | 26,794 | module MODULE1 #
(
parameter VAR16 = 100,
parameter VAR99 = "VAR135",
parameter VAR86 = "1T",
parameter VAR44 = 11,
parameter VAR89 = 3,
parameter VAR30 = "8",
parameter VAR57 = 4,
parameter VAR154 = 5,
parameter VAR32 = 5,
parameter VAR12 = 31,
parameter VAR85 = 8,
parameter VAR159 = "VAR93",
parameter VAR33 = "VAR135... | mit |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/tag/crc16.v | 2,274 | module MODULE1(reset, VAR6, VAR4, VAR1, VAR3, VAR2);
input reset, VAR6, VAR4, VAR1;
output VAR3, VAR2;
reg [15:0] VAR7;
reg [3:0] VAR5;
wire VAR2;
assign VAR3 = VAR7[~VAR5];
assign VAR2 = (VAR5 == 15);
always @ (posedge VAR1 or posedge reset) begin
if (reset) begin
VAR5 <= 0;
end else if (!VAR2) begin
VAR5 <= VAR5 + 4'... | gpl-3.0 |
sehugg/8bitworkshop | presets/verilog-vga/ball_paddle.v | 7,627 | module MODULE1(clk, reset, VAR13, VAR47, VAR44, VAR17);
input clk;
input reset;
input VAR13;
output VAR47, VAR44;
output [2:0] VAR17;
wire VAR35;
wire [9:0] VAR22;
wire [9:0] VAR27;
reg [9:0] VAR5;
reg [9:0] VAR51; reg [9:0] VAR32; reg VAR41; reg VAR8; reg VAR40;
reg VAR55 [0:VAR36*VAR21-1];
wire [3:0] VAR18; wire [3:0... | gpl-3.0 |
nickdesaulniers/Omicron | clk_blk/clk_blk.v | 2,443 | module MODULE1(VAR35,
VAR25,
VAR16,
VAR37,
VAR31);
input VAR35;
input VAR25;
output VAR16;
output VAR37;
output VAR31;
wire VAR42;
wire VAR9;
wire VAR36;
wire VAR23;
assign VAR23 = 0;
assign VAR16 = VAR42;
VAR18 VAR32 (.VAR15(VAR9),
.VAR13(VAR42));
VAR18 VAR48 (.VAR15(VAR36),
.VAR13(VAR37));
VAR3 #( .VAR20("1X"), .VAR5... | gpl-3.0 |
hydai/Verilog-Practice | DigitalDesign/SYN/hw5/fifo_t.v | 3,376 | module MODULE1;
parameter period = 20;
parameter delay = 2;
reg clk, VAR9, VAR6, VAR12;
reg [7:0] VAR4;
wire VAR1, VAR11, VAR8, VAR7, VAR2;
wire [7:0] VAR10;
VAR3 VAR5 (
clk,
VAR9,
VAR6,
VAR12,
VAR4,
VAR1,
VAR11,
VAR8,
VAR7,
VAR2,
VAR10
);
always #(period/2) clk = ~clk;
begin
begin
begin
begin | mit |
CospanDesign/vivado-ip-cores | ip/axi_on_screen_display/character_buffer.v | 21,113 | module MODULE1 #(
parameter VAR27 = 12,
parameter VAR55 = 5,
parameter VAR49 = 8,
parameter VAR86 = 80,
parameter VAR23 = 34,
parameter VAR4 = VAR86 * VAR23
)(
input clk,
input rst,
input VAR1,
input VAR45,
input [2:0] VAR50,
input VAR57,
input [7:0] VAR18,
output VAR58,
input VAR17,
input VAR14,
output reg VAR65,
outp... | mit |
nyaxt/dmix | uart_t.v | 1,974 | module MODULE1;
reg clk;
parameter VAR9 = 20;
VAR5 clk = 0;
always #(VAR9/2) clk = ~clk;
parameter VAR2 = 104167;
reg VAR10;
reg [7:0] VAR1;
reg VAR8;
VAR4 VAR6(
.clk(clk),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR8(VAR8));
task VAR3;
input [7:0] VAR7;
begin
VAR10 = 0; #(VAR2);
VAR10 = VAR7[0];
VAR10 = VAR7[1];
VAR10 = VAR7[2];... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrbp/sky130_fd_sc_hvl__dfrbp.pp.blackbox.v | 1,412 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR7 ,
VAR5 ,
VAR2,
VAR6 ,
VAR3 ,
VAR4 ,
VAR1
);
output VAR9 ;
output VAR8 ;
input VAR7 ;
input VAR5 ;
input VAR2;
input VAR6 ;
input VAR3 ;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_serdes_out.v | 6,633 | module MODULE1 (
rst,
clk,
VAR6,
VAR14,
VAR28,
VAR16,
VAR51,
VAR54,
VAR86,
VAR76,
VAR64,
VAR55,
VAR29);
parameter VAR57 = 0;
parameter VAR18 = 1;
parameter VAR50 = 16;
localparam VAR25 = 1;
localparam VAR72 = 0;
localparam VAR40 = VAR50 - 1;
input rst;
input clk;
input VAR6;
input [VAR40:0] VAR14;
input [VAR40:0] VAR28... | lgpl-3.0 |
yugr/primogen | src/primogen.v | 7,809 | module MODULE1 #(
parameter VAR15 = 4
) (clk, VAR31, rst, ready, VAR46, VAR36);
localparam VAR43 = 1 << VAR15;
localparam VAR42 = VAR43 - 1;
input clk;
input VAR31;
input rst;
output reg ready;
output reg VAR46;
output reg [VAR42:0] VAR36;
localparam VAR19 = {VAR43{1'b1}};
localparam VAR7 = 8;
localparam VAR44 = VAR7 -... | mit |
SiLab-Bonn/pyBAR | firmware/mio/src/clk_gen_12mhz.v | 6,162 | module MODULE1 (
VAR111,
VAR25,
VAR19,
VAR56,
VAR65,
VAR95,
VAR86,
VAR101,
VAR60,
VAR67,
VAR81
);
input wire VAR111;
input wire VAR25;
output wire VAR95;
output wire VAR19;
output wire VAR56;
output wire [7:0] VAR65;
output wire VAR86;
output wire VAR101;
output wire VAR60;
output wire VAR67;
output wire [7:0] VAR81;
w... | bsd-3-clause |
pavel-demin/red-pitaya-notes | projects/red_pitaya_0_92/red_pitaya_hk.v | 7,357 | module MODULE1
(
input VAR31 , input VAR27 ,
output [ 8-1: 0] VAR37 , input [ 8-1: 0] VAR38 , output reg [ 8-1: 0] VAR18 , output reg [ 8-1: 0] VAR2 , input [ 8-1: 0] VAR10 , output reg [ 8-1: 0] VAR25 , output reg [ 8-1: 0] VAR12 ,
input VAR23 , input VAR30 , input [ 32-1: 0] VAR19 , input [ 32-1: 0] VAR36 , input [ 4... | mit |
kylemsguy/FPGA-Litecoin-Miner | experimental/LX150-SIXTYFOUR-A/xilinx_dyn_pll.v | 3,210 | module MODULE1 # (parameter VAR47 = 25 )
(VAR14,
VAR73,
VAR53,
VAR63,
VAR76,
VAR37,
VAR31,
VAR23,
VAR35,
VAR43,
VAR75,
VAR51);
input VAR14;
wire VAR54;
wire VAR34;
output VAR73;
output VAR53;
output VAR63;
output VAR76;
input VAR37;
input VAR31;
input VAR23;
input VAR35;
output VAR43;
output VAR75;
output [2:1] VAR51;
... | gpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v | 50,176 | module MODULE1 #
(
parameter VAR40 = 100,
parameter VAR143 = 2500,
parameter VAR120 = 4,
parameter VAR61 = "VAR65",
parameter VAR77 = 8,
parameter VAR149 = 3,
parameter VAR71 = 8,
parameter VAR79 = 64,
parameter VAR91 = "VAR43",
parameter VAR56 = "VAR111"
)
(
input clk,
input rst,
input VAR107,
input VAR48,
input [5:0]... | lgpl-3.0 |
terkaa/linuxcnc | src/hal/drivers/pluto_servo_firmware/servo.v | 6,410 | module MODULE1(clk, VAR60, VAR38, VAR19, VAR11, VAR28, VAR29, VAR49,
VAR31, dout, din, VAR2, VAR32, VAR16, VAR15, VAR36);
parameter VAR25=14;
input clk;
output VAR60, VAR38;
inout [7:0] VAR11;
input VAR28;
output VAR29;
input VAR49, VAR31, VAR19;
wire VAR68;
reg[9:0] VAR57; output [9:0] dout = VAR68 ? 10'VAR45 : VAR57;... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_p0_flop_mem.v | 2,939 | module MODULE1(
VAR4,
VAR21,
VAR8,
VAR25,
VAR1,
VAR33,
VAR28,
VAR18,
VAR24,
VAR17
);
parameter VAR12 = "";
parameter VAR19 = "";
parameter VAR5 = "";
parameter VAR29 = "";
parameter VAR26 = "";
parameter VAR31 = "";
input VAR4;
input VAR21;
input VAR8;
input [VAR19-1:0] VAR25;
input [VAR5-1:0] VAR1;
input VAR33;
input ... | gpl-3.0 |
quartushaters/project | M1/Part 1/raminout2_bb.v | 8,413 | module MODULE1 (
VAR8,
VAR5,
VAR2,
VAR7,
VAR1,
VAR6,
VAR4,
VAR9,
VAR3);
input [9:0] VAR8;
input [9:0] VAR5;
input VAR2;
input [31:0] VAR7;
input [31:0] VAR1;
input VAR6;
input VAR4;
output [31:0] VAR9;
output [31:0] VAR3;
tri1 VAR2;
tri0 VAR6;
tri0 VAR4;
endmodule | gpl-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/usb_ctrl.v | 4,811 | module MODULE1 (input VAR58, input rst,
output VAR10,
output VAR53,
input VAR33,
input [ 6:0] addr,
input [63:0] VAR56,
output [18:0] VAR7,
output [7:0] VAR2,
output VAR15,
input [7:0] VAR6,
input VAR32,
input VAR49,
output VAR26);
localparam VAR18 = 4'h0;
localparam VAR42 = 4'h1;
localparam VAR12 = 4'h2;
localparam VA... | apache-2.0 |
swallat/yosys | techlibs/intel/cyclone10/cells_map.v | 4,675 | module \VAR17 (input VAR15, VAR2, output VAR5);
parameter VAR43="VAR14";
VAR48 #(.VAR25(VAR43)) VAR11 (.VAR42(VAR15), .VAR35(VAR5), .clk(VAR2), .VAR37(1'b1), .VAR45(1'b1), .VAR40(1'b1), .VAR32(1'b0), .VAR1(1'b0), .VAR27(1'b0), .VAR36(1'b0));
endmodule
module \VAR22 (input VAR15, VAR2, output VAR5);
parameter VAR43="VAR... | isc |
grvmind/amber-cycloneiii | trunk/hw/vlog/amber23/a23_execute.v | 30,620 | module MODULE1 (
input VAR129,
input [31:0] VAR64,
input [4:0] VAR27, input [31:0] VAR164, input VAR137,
output reg [31:0] VAR57 = 'd0,
output reg [31:0] VAR125 = 'd0,
output reg [31:0] VAR169 = 32'hdeaddead,
output reg VAR78 = 'd0, output reg VAR20 = 'd0, output [31:0] VAR130, output reg VAR53 = 'd0, output reg VAR56 ... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_1.behavioral.v | 2,309 | module MODULE1( VAR5, VAR2, VAR7, VAR3, VAR1 );
input VAR3, VAR1, VAR2, VAR5;
output VAR7;
VAR8 VAR6(.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3),.VAR1(VAR1));
VAR8 VAR4(.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3),.VAR1(VAR1)); | apache-2.0 |
manu3193/TextEditor | pong_graph.v | 7,815 | module MODULE1
(
input wire clk, reset,
input wire [2:0] VAR18,
input wire [9:0] VAR35, VAR2,
output wire VAR6,
output reg [2:0] VAR12
);
localparam VAR13 = 640;
localparam VAR1 = 480;
localparam VAR9 = 4'd1;
localparam VAR25 = 4'd2;
localparam VAR27 = 4'd3;
localparam VAR5 = 4'd4;
localparam VAR30 = 4'd5;
localparam V... | mit |
nyaxt/dmix | ise/tepla/ipcore_dir/nkmd_ddr3/example_design/par/ipcore_dir/dcm/example_design/dcm_exdes.v | 4,963 | module MODULE1
parameter VAR12 = 100
)
( input VAR25,
input VAR20,
output [1:1] VAR3,
output VAR10,
input VAR24,
output VAR26
);
localparam VAR23 = 16;
wire VAR16 = !VAR26 || VAR24 || VAR20;
reg VAR18;
reg VAR17;
reg VAR7;
reg VAR5;
wire VAR2;
wire VAR14;
wire clk;
reg [VAR23-1:0] counter;
VAR21 VAR15
( .VAR25 (VAR25),... | mit |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_streaming_top.v | 37,452 | module MODULE1
parameter VAR79 = "VAR148",
parameter VAR97 = 1,
parameter VAR190 = 32,
parameter VAR188 = 1 ,
parameter VAR117 = 1 ,
parameter VAR131 = 1 ,
parameter VAR38 = 1 ,
parameter VAR242 = 32,
parameter VAR206 = 8,
parameter VAR57 = 1,
parameter VAR87 = 1,
parameter VAR177 = 1,
parameter VAR154 = 1,
parameter V... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/micron/ddr_sdram/mobile_ddr_fe.v | 99,206 | module MODULE1 (VAR43, VAR172, VAR107, VAR8, VAR128, VAR186, VAR185, VAR87, VAR165, VAR139, VAR131, VAR143,
VAR193, VAR20, VAR40, VAR109, VAR162, VAR19, VAR153, VAR187);
parameter VAR37 = 1.0; parameter VAR90 = 2.0; parameter VAR57 = 97.5; parameter VAR149 = 1.0; parameter VAR21 = 2.0; parameter VAR47 = 14.99;
paramete... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxbp/sky130_fd_sc_ls__sdfxbp.behavioral.pp.v | 2,509 | module MODULE1 (
VAR11 ,
VAR9 ,
VAR1 ,
VAR26 ,
VAR25 ,
VAR5 ,
VAR20,
VAR7,
VAR22 ,
VAR12
);
output VAR11 ;
output VAR9 ;
input VAR1 ;
input VAR26 ;
input VAR25 ;
input VAR5 ;
input VAR20;
input VAR7;
input VAR22 ;
input VAR12 ;
wire VAR24 ;
wire VAR14 ;
reg VAR2 ;
wire VAR13 ;
wire VAR16;
wire VAR17;
wire VAR4;
wire VA... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/V2NFC100DDR/src/NPM_Toggle_TIMER.v | 11,924 | module MODULE1
(
parameter VAR13 = 4
)
(
VAR24 ,
VAR14 ,
VAR37 ,
VAR28 ,
VAR3 ,
VAR11 ,
VAR17 ,
VAR22 ,
VAR12 ,
VAR18 ,
VAR9 ,
VAR30 ,
VAR26 ,
VAR21 ,
VAR15 ,
VAR38 ,
VAR35 ,
VAR39 ,
VAR40 ,
VAR6
);
input VAR24 ;
input VAR14 ;
output VAR37 ;
output VAR28 ;
input VAR3 ;
input [2:0] VAR11 ;
input [VAR13 - 1:0] VAR17 ;
in... | gpl-3.0 |
omicronns/studies-sys-rek | de1-soc-template/v/RAW2RGB.v | 4,054 | module MODULE1( VAR18,
VAR19,
VAR5,
VAR8,
VAR11,
VAR22,
VAR17,
VAR7,
VAR13,
VAR23
);
input [10:0] VAR11;
input [10:0] VAR22;
input [11:0] VAR17;
input VAR7;
input VAR13;
input VAR23;
output [11:0] VAR18;
output [11:0] VAR19;
output [11:0] VAR5;
output VAR8;
wire [11:0] VAR3;
wire [11:0] VAR6;
reg [11:0] VAR10;
reg [11:... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fanout_splitter.v | 2,062 | module MODULE1(VAR23, VAR16, VAR18, VAR22, VAR7, VAR13, VAR19, VAR1);
parameter VAR2 = 32;
parameter VAR6 = 2;
input VAR23, VAR16;
input [VAR2-1:0] VAR18;
input VAR22;
output VAR7;
output reg [VAR2-1:0] VAR13;
input [VAR6-1:0] VAR19;
output [VAR6-1:0] VAR1;
wire [VAR2-1:0] VAR4;
wire VAR9;
wire VAR12;
VAR20 VAR24 (.clk... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_1.behavioral.v | 1,964 | module MODULE1( VAR2, VAR4, VAR7, VAR8, VAR3 );
input VAR4, VAR8, VAR3, VAR2;
output VAR7;
VAR6 VAR1(.VAR2(VAR2),.VAR4(VAR4),.VAR7(VAR7),.VAR8(VAR8),.VAR3(VAR3));
VAR6 VAR5(.VAR2(VAR2),.VAR4(VAR4),.VAR7(VAR7),.VAR8(VAR8),.VAR3(VAR3)); | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2.1/22465fc93bb76d40/zqynq_lab_1_design_xbar_0_stub.v | 5,981 | module MODULE1(VAR23, VAR19, VAR71, VAR57,
VAR39, VAR9, VAR22, VAR37, VAR52, VAR70,
VAR1, VAR25, VAR63, VAR27, VAR43, VAR51,
VAR15, VAR38, VAR41, VAR67, VAR24, VAR31, VAR4,
VAR28, VAR64, VAR29, VAR78, VAR12, VAR17,
VAR10, VAR16, VAR20, VAR11, VAR33, VAR8, VAR14,
VAR66, VAR42, VAR40, VAR61, VAR18, VAR7, VAR49,
VAR48, VA... | mit |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk01/src/cpu/k580wm80a.v | 11,264 | module MODULE1(
input clk,
input VAR36,
input reset,
input VAR16,
input [7:0] VAR39,
output reg [15:0] addr,
output reg sync,
output rd,
output reg VAR21,
output VAR8,
output reg [7:0] VAR20,
output VAR44);
reg VAR80,VAR17,VAR63,VAR9,VAR75,VAR6,VAR87,VAR30,VAR41,VAR73,VAR59,VAR60,VAR34,VAR51,VAR32,VAR14,VAR82,VAR10;
re... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22a/sky130_fd_sc_hdll__o22a.blackbox.v | 1,364 | module MODULE1 (
VAR8 ,
VAR2,
VAR9,
VAR4,
VAR5
);
output VAR8 ;
input VAR2;
input VAR9;
input VAR4;
input VAR5;
supply1 VAR6;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/mc_phy.v | 82,759 | module MODULE1
parameter VAR74 = 4'b1111,
parameter VAR410 = 4'b0000,
parameter VAR229 = 4'b0000,
parameter VAR198 = 4'b0000,
parameter VAR382 = 4'b0000,
parameter VAR131 = 4'hc,
parameter VAR275 = 4'hf,
parameter VAR426 = 4'hf,
parameter VAR51 = 4'hf,
parameter VAR296 = 4'hf,
parameter VAR315 = 48'hdffdfffedfff,
param... | lgpl-3.0 |
parallella/oh | gpio/hdl/parallella_gpio.v | 7,166 | module MODULE1(
VAR33, VAR41, VAR35, VAR45, VAR42,
VAR44, VAR52, VAR53, VAR31, VAR47,
VAR36, VAR38,
VAR39, VAR49,
VAR32, VAR51, VAR5, VAR48, VAR61,
VAR34, VAR1, VAR22, VAR16,
VAR37, VAR64, VAR11, VAR63, VAR59,
VAR2, VAR40, VAR46, VAR57,
VAR43, VAR18, VAR60, VAR25, VAR56,
VAR15, VAR27, VAR50, VAR58,
VAR55, VAR19, VAR9, ... | mit |
hightoon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_trn_data_fsm.v | 16,101 | module MODULE1(
input wire clk,
input wire rst,
input wire [63:0] VAR81,
input wire [7:0] VAR80,
input wire VAR77,
input wire VAR38,
input wire VAR75,
input wire VAR6,
output reg VAR85,
input wire VAR4,
output wire VAR36,
input wire [6:0] VAR73,
input wire [11:0] VAR19,
input wire [7:0] VAR70,
input wire [11:0] VAR40,
... | bsd-2-clause |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Ultrasonico/ultrasonic.v | 1,897 | module MODULE1 #( parameter VAR10 = 16 , VAR2 = 20'd588 ) (
input clk,
input VAR7,
input VAR4,
output reg [VAR10-1:0] VAR6 ,
output reg VAR5
);
reg [1:0] state ;
reg [VAR10-1:0] VAR1 ;
parameter VAR3 = 2'b00 ;
parameter VAR9 = 2'b01 ;
parameter VAR8 = 2'b10 ;
always @ ( negedge clk )
if ( ~VAR4 )
state <= VAR3 ;
else
c... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_2/synth/design_1_xbar_2.v | 20,753 | module MODULE1 (
VAR99,
VAR92,
VAR30,
VAR77,
VAR89,
VAR70,
VAR42,
VAR68,
VAR83,
VAR33,
VAR17,
VAR25,
VAR82,
VAR105,
VAR11,
VAR60,
VAR123,
VAR16,
VAR58,
VAR13,
VAR118,
VAR72,
VAR78,
VAR121,
VAR127,
VAR5,
VAR75,
VAR50,
VAR66,
VAR109,
VAR32,
VAR9,
VAR122,
VAR126,
VAR116,
VAR88,
VAR4,
VAR48,
VAR94,
VAR96,
VAR18,
VAR91,
VAR... | mit |
petrmikheev/miksys | verilog/SHIFT.v | 3,927 | module MODULE1 (
VAR5,
VAR15,
VAR18,
VAR6);
input [15:0] VAR5;
input VAR15;
input [3:0] VAR18;
output [15:0] VAR6;
wire [15:0] VAR1;
wire [15:0] VAR6 = VAR1[15:0];
VAR10 VAR13 (
.VAR5 (VAR5),
.VAR15 (VAR15),
.VAR18 (VAR18),
.VAR6 (VAR1)
,
.VAR12 (),
.VAR9 (),
.VAR16 (),
.VAR14 (),
.VAR17 ()
);
VAR13.VAR7 = "VAR11",
VA... | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/altera_jtag_avalon_master_171/synth/ghrd_10as066n2_hps_m_altera_jtag_avalon_master_171_wqhllki.v | 25,714 | module MODULE1 #(
parameter VAR18 = 0,
parameter VAR3 = 50000,
parameter VAR28 = 2
) (
input wire VAR16, input wire VAR15, output wire [31:0] VAR9, input wire [31:0] VAR19, output wire VAR7, output wire VAR35, output wire [31:0] VAR22, input wire VAR43, input wire VAR4, output wire [3:0] VAR17, output wire VAR2 );
wire... | mit |
TheMadSocrates/vercpu-project | rtl/core/datapath.v | 5,768 | module MODULE1(
input wire [ 7 : 0] VAR38,
input wire [ 7 : 0] VAR43,
input wire clk,
input wire VAR53,
input wire [ 1 : 0] VAR13,
input wire VAR35,
input wire VAR41,
input wire VAR34,
input wire [ 1 : 0] VAR22,
input wire VAR55,
input wire VAR9,
input wire [ 1 : 0] VAR36,
input wire VAR16,
input wire [ 2 : 0] VAR4,
in... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/DOUBLE/Tenth_Phase_syn.v | 10,317 | module MODULE5 ( VAR2, VAR95, VAR59, VAR45, VAR128 );
input [1:0] VAR2;
input [0:0] VAR95;
input [0:0] VAR59;
input [0:0] VAR45;
output [0:0] VAR128;
wire VAR29, VAR113, VAR140, VAR141;
VAR13 VAR90 ( .VAR60(VAR95[0]), .VAR132(VAR113), .VAR119(VAR2[0]), .VAR146(VAR59[0]), .VAR105(VAR140) );
VAR42 VAR22 ( .VAR60(VAR2[1])... | gpl-3.0 |
jrward/qdbreakout | rtl/block_positions.v | 7,414 | module MODULE1 (
address,
VAR10,
VAR16,
VAR32,
VAR39,
VAR20);
input [9:0] address;
input VAR10;
input VAR16;
input [3:0] VAR32;
input VAR39;
output [3:0] VAR20;
tri0 VAR10;
tri1 VAR16;
wire [3:0] VAR55;
wire [3:0] VAR20 = VAR55[3:0];
VAR13 VAR8 (
.VAR15 (address),
.VAR10 (VAR10),
.VAR24 (VAR16),
.VAR23 (VAR32),
.VAR3 (... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2b/sky130_fd_sc_ms__or2b.behavioral.pp.v | 1,924 | module MODULE1 (
VAR9 ,
VAR13 ,
VAR2 ,
VAR5,
VAR12,
VAR15 ,
VAR7
);
output VAR9 ;
input VAR13 ;
input VAR2 ;
input VAR5;
input VAR12;
input VAR15 ;
input VAR7 ;
wire VAR6 ;
wire VAR1 ;
wire VAR3;
not VAR14 (VAR6 , VAR2 );
or VAR8 (VAR1 , VAR6, VAR13 );
VAR4 VAR10 (VAR3, VAR1, VAR5, VAR12);
buf VAR11 (VAR9 , VAR3 );
end... | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_example_top_34.v | 7,281 | module MODULE1 (
VAR46,
VAR11,
VAR12,
VAR63,
VAR58,
VAR65,
VAR45,
VAR62,
VAR35,
VAR1,
VAR52,
VAR34,
VAR13,
VAR53,
VAR6,
VAR49,
VAR14,
VAR22,
VAR26,
VAR30,
VAR38
)
;
output [ 12: 0] VAR12;
output [ 2: 0] VAR63;
output VAR58;
output [ 0: 0] VAR65;
inout [ 0: 0] VAR45;
inout [ 0: 0] VAR62;
output [ 0: 0] VAR35;
output [ 7... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221oi/sky130_fd_sc_ms__a221oi.behavioral.v | 1,678 | module MODULE1 (
VAR6 ,
VAR5,
VAR10,
VAR1,
VAR16,
VAR12
);
output VAR6 ;
input VAR5;
input VAR10;
input VAR1;
input VAR16;
input VAR12;
supply1 VAR11;
supply0 VAR14;
supply1 VAR7 ;
supply0 VAR4 ;
wire VAR13 ;
wire VAR8 ;
wire VAR17;
and VAR2 (VAR13 , VAR1, VAR16 );
and VAR9 (VAR8 , VAR5, VAR10 );
nor VAR3 (VAR17, VAR13... | apache-2.0 |
sh-chris110/chris | FPGA/chris.bak/Qsys/soc_design/synthesis/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR2,
VAR3,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR2;
input VAR3;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1500008019 : 255;
endmodule | gpl-2.0 |
daveshah1/openMixR | fpga/vivado/openmixr_base/openmixr_base.cache/ip/b018d6374f05f04f/init_config_rom_stub.v | 1,305 | module MODULE1(VAR3, VAR1, VAR2)
;
input VAR3;
input [9:0]VAR1;
output [31:0]VAR2;
endmodule | mit |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/verilog/axi_vdma_v6_2_axis_infrastructure_v1_0_util_vector2axis.v | 7,415 | module MODULE1 #
(
parameter integer VAR26 = 32,
parameter integer VAR41 = 1,
parameter integer VAR27 = 1,
parameter integer VAR25 = 1,
parameter integer VAR8 = 44,
parameter [31:0] VAR12 = 32'hFF
)
(
input wire [VAR8-1:0] VAR42,
output wire [VAR26-1:0] VAR34,
output wire [VAR26/8-1:0] VAR14,
output wire [VAR26/8-1:0] ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xor2/sky130_fd_sc_hvl__xor2.functional.pp.v | 1,823 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR11 ,
VAR12,
VAR2,
VAR7 ,
VAR1
);
output VAR9 ;
input VAR10 ;
input VAR11 ;
input VAR12;
input VAR2;
input VAR7 ;
input VAR1 ;
wire VAR5 ;
wire VAR4;
xor VAR3 (VAR5 , VAR11, VAR10 );
VAR13 VAR8 (VAR4, VAR5, VAR12, VAR2);
buf VAR6 (VAR9 , VAR4 );
endmodule | apache-2.0 |
fpgasystems/caribou | hw/src/nukv/nukv_value_set.v | 8,393 | module MODULE1 #(
parameter VAR24 = 128,
parameter VAR33 = 42, parameter VAR45 = 96,
parameter VAR9 = 512,
parameter VAR38 = 21,
parameter VAR36 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR24+VAR33+VAR45-1:0] VAR37,
input wire VAR1,
output reg VAR2,
input wire [VAR9-1:0] VAR28,
input wire VAR49,
output reg V... | gpl-3.0 |
davidlee80/miaow | src/verilog/rtl/alu/src_mux.v | 1,457 | module MODULE1 (
VAR4,
VAR2,
VAR7,
VAR11,
VAR9,
VAR8,
VAR6,
VAR3,
VAR10,
VAR1
);
input [9:0] VAR4;
input [31:0] VAR2;
input [2047:0] VAR7;
input [63:0] VAR11;
input [63:0] VAR9;
input [31:0] VAR8;
input VAR6;
input [3:0] VAR10;
input [31:0] VAR3;
output [2047:0] VAR1;
reg [2047:0] VAR1;
always @ (VAR4 or VAR2 or
VAR7 o... | bsd-3-clause |
CospanDesign/nysa-artemis-usb2-platform | artemis_usb2/slave/wb_artemis_pcie_platform/rtl/c/axi_basic_rx_pipeline.v | 26,830 | module MODULE1 #(
parameter VAR70 = 128, parameter VAR80 = "VAR86", parameter VAR39 = 1,
parameter VAR21 = (VAR70 == 128) ? 2 : 1, parameter VAR66 = VAR70 / 8 ) (
output reg [VAR70-1:0] VAR26, output reg VAR87, input VAR11, output [VAR66-1:0] VAR53, output VAR79, output reg [21:0] VAR16,
input [VAR70-1:0] VAR6, input V... | gpl-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeZynq/build/AXI4LiteToRFBridgeVerilog.v | 16,860 | module MODULE1 #
(
parameter integer VAR16 = 32,
parameter integer VAR31 = 32
)
(
output wire [VAR16-1 : 0] VAR32,
output wire [VAR16-1 : 0] VAR6,
output wire VAR29,
output wire [VAR31-1 : 0] VAR3,
input wire [VAR31-1 : 0] VAR9,
input wire VAR36,
input wire VAR27,
input wire [VAR16-1 : 0] VAR20,
input wire [2 : 0] VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4bb/sky130_fd_sc_hd__and4bb.pp.blackbox.v | 1,351 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR8 ,
VAR9 ,
VAR4 ,
VAR7,
VAR2,
VAR1 ,
VAR6
);
output VAR3 ;
input VAR5 ;
input VAR8 ;
input VAR9 ;
input VAR4 ;
input VAR7;
input VAR2;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1.pp.symbol.v | 1,330 | module MODULE1 (
input VAR4 ,
output VAR5 ,
input VAR6 ,
input VAR2,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/db/ip/niosII_system/submodules/niosII_system_sysid_qsys_0.v | 1,415 | module MODULE1 (
address,
VAR1,
VAR2,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR1;
input VAR2;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1459999942 : 0;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbn/sky130_fd_sc_hd__dlrbn.behavioral.v | 2,566 | module MODULE1 (
VAR22 ,
VAR1 ,
VAR14,
VAR7 ,
VAR24
);
output VAR22 ;
output VAR1 ;
input VAR14;
input VAR7 ;
input VAR24 ;
supply1 VAR10;
supply0 VAR9;
supply1 VAR17 ;
supply0 VAR8 ;
wire VAR23 ;
wire VAR25 ;
reg VAR11 ;
wire VAR13 ;
wire VAR19 ;
wire VAR6 ;
wire VAR4;
wire VAR18 ;
wire VAR2 ;
wire VAR26 ;
wire VAR21 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor3/sky130_fd_sc_hs__xnor3.functional.v | 1,716 | module MODULE1 (
VAR12 ,
VAR3 ,
VAR2 ,
VAR4 ,
VAR9,
VAR8
);
output VAR12 ;
input VAR3 ;
input VAR2 ;
input VAR4 ;
input VAR9;
input VAR8;
wire VAR10 ;
wire VAR6;
xnor VAR7 (VAR10 , VAR3, VAR2, VAR4 );
VAR5 VAR11 (VAR6, VAR10, VAR9, VAR8);
buf VAR1 (VAR12 , VAR6 );
endmodule | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/pll_reconfig/altera_pll_reconfig_top.v | 7,541 | module MODULE1
parameter VAR5 = 64,
parameter VAR4 = "VAR42 VAR48",
parameter VAR17 = 6,
parameter VAR37 = 32,
parameter VAR33 = 9,
parameter VAR44 = 32,
parameter VAR39 = 512,
parameter VAR53 = 0,
parameter VAR19 = ""
) (
input wire VAR43,
input wire VAR24,
output wire [VAR5-1:0] VAR45,
input wire [VAR5-1:0] VAR47,
ou... | mit |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp_synth.v | 4,397 | module MODULE1 (
VAR2,
VAR7,
VAR10,
VAR8,
VAR11,
VAR9,
VAR6,
VAR1,
VAR12,
VAR3,
VAR5,
VAR4
);
input VAR2;
input VAR7;
input [1 : 0] VAR10;
input [9 : 0] VAR8;
input [15 : 0] VAR11;
output [15 : 0] VAR9;
input VAR6;
input VAR1;
input [1 : 0] VAR12;
input [9 : 0] VAR3;
input [15 : 0] VAR5;
output [15 : 0] VAR4;
endmodule | bsd-3-clause |
SiLab-Bonn/basil | basil/firmware/modules/seq_rec/seq_rec.v | 1,594 | module MODULE1 #(
parameter VAR17 = 0,
parameter VAR6 = 0,
parameter VAR22 = 16,
parameter VAR5 = 2*1024,
parameter VAR10 = 8
) (
input wire VAR4,
input wire VAR18,
input wire [VAR22-1:0] VAR8,
inout wire [7:0] VAR16,
input wire VAR19,
input wire VAR11,
input wire VAR9,
input wire [VAR10-1:0] VAR21,
input wire VAR12
);... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtn/sky130_fd_sc_ls__sdfrtn_1.v | 2,587 | module MODULE2 (
VAR1 ,
VAR11 ,
VAR6 ,
VAR12 ,
VAR7 ,
VAR8,
VAR10 ,
VAR4 ,
VAR3 ,
VAR2
);
output VAR1 ;
input VAR11 ;
input VAR6 ;
input VAR12 ;
input VAR7 ;
input VAR8;
input VAR10 ;
input VAR4 ;
input VAR3 ;
input VAR2 ;
VAR5 VAR9 (
.VAR1(VAR1),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR8(VAR8),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv.functional.pp.v | 1,792 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR8,
VAR5,
VAR2 ,
VAR9
);
output VAR7 ;
input VAR3 ;
input VAR8;
input VAR5;
input VAR2 ;
input VAR9 ;
wire VAR1 ;
wire VAR12;
not VAR11 (VAR1 , VAR3 );
VAR6 VAR10 (VAR12, VAR1, VAR8, VAR5);
buf VAR4 (VAR7 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtp/sky130_fd_sc_ls__dlxtp.blackbox.v | 1,292 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR5
);
output VAR4 ;
input VAR2 ;
input VAR5;
supply1 VAR3;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_117.v | 1,527 | module MODULE2 (
VAR5,
VAR8
);
input [31:0] VAR5;
output [31:0]
VAR8;
wire [31:0]
VAR2,
VAR6,
VAR14,
VAR13,
VAR3,
VAR10,
VAR4,
VAR1,
VAR12;
assign VAR2 = VAR5;
assign VAR4 = VAR3 - VAR10;
assign VAR3 = VAR14 - VAR13;
assign VAR14 = VAR6 - VAR2;
assign VAR6 = VAR2 << 11;
assign VAR12 = VAR1 - VAR4;
assign VAR10 = VAR2 <... | mit |
ashikpoojari/NIDS-Wu-Manber | Wu_Manber_shiftPE.v | 31,764 | module MODULE1 #(parameter VAR40=128, VAR6=4, VAR32=3, VAR50=20, VAR38=1024,
VAR47=VAR41(VAR50-VAR32+1),VAR53=VAR6*VAR40,
VAR57=2*VAR40, VAR27=VAR41(VAR57), VAR11=4, VAR12=VAR38/VAR11,VAR8=VAR41(VAR38/VAR11),VAR60=VAR41(VAR8+VAR11+2),VAR48=78)
( input clk,
input reset,
input VAR54,
input [VAR53-1:0] VAR58,
output VAR34... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_pwrgood_pp_g/sky130_fd_sc_ls__udp_pwrgood_pp_g.blackbox.v | 1,251 | module MODULE1 (
VAR2,
VAR3 ,
VAR1
);
output VAR2;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxtp/sky130_fd_sc_hs__edfxtp_1.v | 2,150 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR3 ,
VAR1 ,
VAR2,
VAR5
);
output VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR1 ;
input VAR2;
input VAR5;
VAR4 VAR8 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR6 ,
VAR7,
VAR3 ,
VAR1
);
output VAR6 ;
input VAR7;
input VAR3 ... | apache-2.0 |
fbelavenuto/msx1fpga | src/hdmi/hdmidataencoder.v | 7,951 | module MODULE1
(
input VAR36,
input VAR34,
input VAR33,
input VAR8,
input [15:0] VAR5,
input [15:0] VAR25,
output [3:0] VAR21,
output [3:0] VAR6,
output [3:0] VAR22,
output VAR11
);
localparam [191:0] VAR28 = (VAR14 == 48000)?192'hc202004004:(VAR14 == 44100)?192'hc200004004:192'hc203004004;
localparam [55:0] VAR17 = {V... | gpl-3.0 |
fzyz999/5-stage-MIPS | datapath/ext.v | 1,689 | module MODULE1 (VAR7,din,dout);
input [1:0] VAR7;
input [15:0] din;
output [31:0] dout;
assign dout=(VAR7==2'b00)?{16'h0,din}:
(VAR7==2'b01&&din[15]==1'b1)?{16'hffff,din}:
(VAR7==2'b01&&din[15]==1'b0)?{16'h0000,din}:
{din,16'h0};
endmodule
module MODULE4 (VAR2,VAR7,VAR8);
input [1:0] VAR2;
input [1:0] VAR7;
output [3:0... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_misc_chunk5.v | 4,987 | module MODULE1(clk ,VAR34 ,VAR19 ,
VAR18 ,VAR25 ,VAR40 ,VAR1 ,VAR4 ,VAR48 ,VAR47 ,
VAR35 ,VAR31 ,VAR27 ,VAR50 ,VAR17 ,VAR44 ,VAR21 ,
VAR26 ,VAR12 ,VAR2 ,VAR33 ,VAR24 ,VAR38 ,VAR20 ,VAR49 ,
VAR53 ,VAR45 ,VAR14 ,VAR56 ,VAR30 ,VAR29 ,VAR52 ,VAR22 ,
VAR9 );
output [2:1] VAR9 ;
input [2:1] VAR18 ;
input [5:4] VAR25 ;
input ... | gpl-2.0 |
borti4938/sd2snes | verilog/sd2snes_sa1/sa1_div.v | 4,466 | module MODULE1 (
VAR3,
VAR9,
VAR12,
VAR18,
VAR15);
input VAR3;
input [15:0] VAR9;
input [15:0] VAR12;
output [15:0] VAR18;
output [15:0] VAR15;
wire [15:0] VAR1;
wire [15:0] VAR5;
wire [15:0] VAR18 = VAR1[15:0];
wire [15:0] VAR15 = VAR5[15:0];
VAR11 VAR7 (
.VAR3 (VAR3),
.VAR9 (VAR9),
.VAR12 (VAR12),
.VAR18 (VAR1),
.VAR... | gpl-2.0 |
marmolejo/zet | cores/vga/rtl/vga_c4_iface.v | 2,377 | module MODULE1 (
input VAR15,
input VAR17,
input [16:1] VAR9,
input [ 1:0] VAR16,
input VAR14,
input [15:0] VAR4,
output [15:0] VAR8,
input VAR13,
output VAR10,
output [17:1] VAR12,
output [ 1:0] VAR7,
output VAR5,
output [15:0] VAR19,
input [15:0] VAR11,
output reg VAR3,
input VAR1
);
reg VAR18;
reg [7:0] VAR2;
wire V... | gpl-3.0 |
Cognoscan/BoostDSP | verilog/src/sigmaDelta/sdDualMagnitude.v | 1,208 | module MODULE1 #(
parameter VAR11 = 16,
parameter VAR4 = 6
)
(
input clk, input rst, input en, input VAR1, input VAR8, output wire [VAR11-1:0] out );
localparam VAR7 = 16;
reg [VAR11+VAR4-1:0] VAR10;
reg [2:0] VAR3;
reg [2:0] VAR5;
reg [3:0] VAR9;
reg VAR2;
reg VAR6;
always @(posedge clk) begin
if (rst) begin
VAR10 <= ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decap/sky130_fd_sc_lp__decap.pp.blackbox.v | 1,198 | module MODULE1 (
VAR4,
VAR2,
VAR1 ,
VAR3
);
input VAR4;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22oi/sky130_fd_sc_ls__a22oi.behavioral.pp.v | 2,164 | module MODULE1 (
VAR6 ,
VAR18 ,
VAR2 ,
VAR5 ,
VAR14 ,
VAR17,
VAR9,
VAR1 ,
VAR7
);
output VAR6 ;
input VAR18 ;
input VAR2 ;
input VAR5 ;
input VAR14 ;
input VAR17;
input VAR9;
input VAR1 ;
input VAR7 ;
wire VAR11 ;
wire VAR3 ;
wire VAR16 ;
wire VAR13;
nand VAR4 (VAR11 , VAR2, VAR18 );
nand VAR8 (VAR3 , VAR14, VAR5 );
an... | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/HLS_accel_v1_0/dbdcd11c/hdl/verilog/HLS_accel_fptrunc_64ns_32_1.v | 1,159 | module MODULE1
VAR4 = 5,
VAR3 = 1,
VAR13 = 64,
VAR9 = 32
)(
input wire [VAR13-1:0] VAR10,
output wire [VAR9-1:0] dout
);
wire VAR7;
wire [63:0] VAR14;
wire VAR6;
wire [31:0] VAR11;
VAR5 VAR8 (
.VAR1 ( VAR7 ),
.VAR15 ( VAR14 ),
.VAR12 ( VAR6 ),
.VAR16 ( VAR11 )
);
assign VAR7 = 1'b1;
assign VAR14 = VAR10==='VAR2 ? 'b0 :... | mit |
miyukki/spartan-3an-vga | program.v | 7,484 | module MODULE1 # (
parameter VAR36 = 1'b1,
parameter VAR26 = 1'b0,
parameter VAR5 = 640,
parameter VAR39 = 16,
parameter VAR33 = 96,
parameter VAR9 = 48,
parameter VAR30 = VAR5 + VAR39 + VAR33 + VAR9,
parameter VAR24 = 480,
parameter VAR4 = 10,
parameter VAR25 = 2,
parameter VAR38 = 33,
parameter VAR12 = VAR24 + VAR4 +... | mit |
finnball/igloo | infra/hdl/infra.v | 1,401 | module MODULE1(
input VAR17,
output VAR23,
output VAR5,
input VAR29,
output [7:0] VAR22,
input VAR14,
output [VAR16 - 1 : 0] VAR8,
output VAR6,
input [VAR16 - 1 : 0] VAR18,
input VAR27,
output VAR20,
output VAR12
);
wire VAR15;
wire VAR26, VAR30;
assign VAR23 = VAR26;
assign VAR5 = VAR30;
VAR9 #(
.VAR1(0),
.VAR4(1),
.V... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_mm_interconnect_0_avalon_st_adapter_004.v | 6,161 | module MODULE1 #(
parameter VAR18 = 10,
parameter VAR5 = 0,
parameter VAR7 = 10,
parameter VAR20 = 0,
parameter VAR1 = 0,
parameter VAR24 = 0,
parameter VAR14 = 1,
parameter VAR3 = 1,
parameter VAR19 = 0,
parameter VAR12 = 10,
parameter VAR2 = 0,
parameter VAR13 = 1,
parameter VAR11 = 0,
parameter VAR6 = 1,
parameter V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbp/sky130_fd_sc_hs__dfbbp.behavioral.pp.v | 2,761 | module MODULE1 (
VAR15 ,
VAR23 ,
VAR2 ,
VAR21 ,
VAR24 ,
VAR6,
VAR19 ,
VAR8
);
output VAR15 ;
output VAR23 ;
input VAR2 ;
input VAR21 ;
input VAR24 ;
input VAR6;
input VAR19 ;
input VAR8 ;
wire VAR17 ;
wire VAR7 ;
wire VAR12 ;
wire VAR11 ;
wire VAR26;
wire VAR16 ;
reg VAR13 ;
wire VAR14 ;
wire VAR4 ;
wire VAR25 ;
wire V... | apache-2.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/opengfx430/ogfx_backend_lut_fifo.v | 21,636 | module MODULE1 (
VAR14,
VAR23, VAR50,
VAR47, VAR20, VAR8
VAR72, VAR27,
VAR7, VAR66,
VAR53,
VAR58, VAR38, VAR8
VAR52, VAR18,
VAR55, VAR67, VAR34, VAR63, VAR36 );
output VAR14;
output [15:0] VAR23; output VAR50;
output [VAR16:0] VAR47; output VAR20; VAR8
input VAR72; input VAR27;
input [15:0] VAR7; input VAR66;
input [2:... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor2/sky130_fd_sc_hd__xnor2.pp.blackbox.v | 1,301 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR6 ,
VAR1,
VAR7,
VAR5 ,
VAR2
);
output VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR1;
input VAR7;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/MuxModule_old (2).v | 1,965 | module MODULE1(
input signed [20:0] VAR9,
input signed [14:0] VAR12,
input VAR8,
input clk,
input VAR5,
output reg signed [12:0] VAR10,
input VAR2,
input signed [12:0] VAR1,
output reg VAR14
);
reg [7:0] VAR6;
reg signed [36:0] VAR7;
reg signed [12:0] VAR4;
reg signed [12:0] VAR13 =0;
reg signed [36:0] VAR11;
always @ ... | gpl-3.0 |
e33b1711/rfnoc_pp_channelizer | sysgen_models/channelizer/checkpoint/sysgen/channelizer.v | 36,847 | module MODULE13 (
input [32-1:0] VAR99,
output [16-1:0] VAR139,
output [16-1:0] VAR276
);
wire [16-1:0] VAR219;
wire [16-1:0] VAR56;
wire [32-1:0] VAR3;
wire [16-1:0] VAR156;
wire [16-1:0] VAR249;
assign VAR139 = VAR219;
assign VAR276 = VAR56;
assign VAR3 = VAR99;
VAR231 VAR100 (
.clk(1'b0),
.VAR145(1'b0),
.VAR204(1'b0... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/8-way/src/riffa/register.v | 2,681 | module MODULE1
parameter VAR1 = 0
)
(input VAR4,
input VAR3,
output [VAR8-1:0] VAR6,
input [VAR8-1:0] VAR5,
input VAR2
);
reg [VAR8-1:0] VAR7;
assign VAR6 = VAR7;
always @(posedge VAR4) begin
if(VAR3) begin
VAR7 <= VAR1;
end else if(VAR2) begin
VAR7 <= VAR5;
end
end
endmodule | mit |
bluespec/Flute | builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkNear_Mem.v | 50,950 | module MODULE1(VAR131,
VAR42,
VAR355,
VAR75,
VAR294,
VAR352,
VAR148,
VAR408,
VAR156,
VAR109,
VAR228,
VAR292,
VAR305,
VAR402,
VAR331,
VAR235,
VAR204,
VAR137,
VAR242,
VAR33,
VAR377,
VAR254,
VAR412,
VAR231,
VAR324,
VAR298,
VAR163,
VAR225,
VAR329,
VAR256,
VAR403,
VAR285,
VAR80,
VAR18,
VAR74,
VAR26,
VAR99,
VAR153,
VAR189,
V... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/c2i/rtl/c2i_sctrl.v | 16,216 | module MODULE1 (
VAR78, VAR70, VAR38, VAR29,
VAR89, VAR61, VAR26, VAR28,
VAR2, VAR24, VAR30,
VAR9, VAR5, VAR101, VAR31,
VAR85, VAR108, VAR25, VAR23,
VAR60, VAR105, VAR34,
VAR68, clk, VAR90, VAR53, VAR113,
VAR111, VAR73, VAR3, VAR69,
VAR55, VAR67, VAR13,
VAR47, VAR36, VAR49,
VAR12, VAR80
);
input VAR68;
input clk;
input... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_legacy/bsg_murn_converter.v | 2,584 | module MODULE1
, parameter VAR22(VAR6)
)
(
input VAR13
, input [VAR31-1:0] VAR1
, input [VAR31-1:0] VAR17
, output [VAR31-1:0] VAR20
, input [VAR6-1:0] VAR8 [VAR31-1:0]
, output [VAR31-1:0] VAR19
, input [VAR31-1:0] VAR21
, output [VAR6-1:0] VAR9 [VAR31-1:0]
, input [VAR31-1:0] VAR24
, output [VAR31-1:0] VAR23
, input ... | bsd-3-clause |
aselectroworks/HDL | rtl/verilog/i2s_to_tdm_converter.v | 4,815 | module MODULE1(
VAR17,
VAR19,
VAR13,
VAR4,
VAR16,
VAR6,
VAR22,
VAR20
);
input VAR17; input VAR19; input VAR13; input VAR4; input [3:0] VAR16;
output VAR6; output VAR22; output reg VAR20;
reg VAR10;
wire rst = VAR17 | VAR10;
reg [8:0] VAR12; wire VAR9 = VAR12[8];
wire VAR7 = VAR19; assign VAR6 = VAR7;
wire [5:0] VAR14 =... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4/sky130_fd_sc_ms__nand4_4.v | 2,253 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR4 ,
VAR5 ,
VAR8 ,
VAR1,
VAR11,
VAR9 ,
VAR3
);
output VAR7 ;
input VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR8 ;
input VAR1;
input VAR11;
input VAR9 ;
input VAR3 ;
VAR6 VAR10 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR... | apache-2.0 |
cynngah/virtualsynthesizer | sound_files/audio_codec.v | 10,062 | module MODULE1 (
clk,
reset,
read, write,
VAR27, VAR53,
VAR38,
VAR14,
VAR23,
VAR5,
VAR11, VAR28,
VAR41, VAR49,
VAR8
);
parameter VAR46 = 24;
parameter VAR42 = 5'd23;
input clk;
input reset;
input read;
input write;
input [VAR46-1:0] VAR27;
input [VAR46-1:0] VAR53;
input VAR38;
input VAR14;
input VAR23;
input VAR5;
outp... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_1.behavioral.v | 1,495 | module MODULE1( VAR6, VAR4, VAR7, VAR2 );
input VAR7, VAR6, VAR2;
output VAR4;
VAR1 VAR5(.VAR6(VAR6),.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2));
VAR1 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2)); | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/acl_ic_mem_router.v | 5,697 | module MODULE1 #(
parameter integer VAR34 = 256,
parameter integer VAR16 = 6,
parameter integer VAR14 = 32,
parameter integer VAR37 = VAR34 / 8,
parameter integer VAR44 = 2
)
(
input logic VAR3,
input logic VAR46,
input logic [VAR44-1:0] VAR45,
input logic VAR12,
input logic VAR35,
input logic VAR28,
input logic [VAR34... | mit |
hsnuonly/PikachuVolleyFPGA | VGA.ip_user_files/ip/ball_pixel/ball_pixel_stub.v | 1,299 | module MODULE1(VAR5, VAR2, VAR3, VAR4, VAR1)
;
input VAR5;
input [0:0]VAR2;
input [11:0]VAR3;
input [11:0]VAR4;
output [11:0]VAR1;
endmodule | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/syn/src/spare/build1/prog_counter2.v | 1,201 | module MODULE1 (VAR1,rst,clk);
output [0:31] VAR1;
input clk;
input rst;
reg [0:31] VAR1;
always @(posedge clk)
begin
if(rst)
begin
VAR1<=32'd0;
end
else
begin
VAR1<=VAR1+32'd4;
end
end
endmodule | mit |
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