repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_large.v | 11,214 | module MODULE1 #(parameter VAR32(VAR8)
, parameter VAR32(VAR34)
)
(input VAR71
, input VAR5
, input [VAR8-1:0] VAR45
, input VAR58
, output VAR10
, output VAR23
, output [VAR8-1:0] VAR47
, input VAR20
);
VAR56 assert ((VAR34 & 1) == 0) else
("VAR46 VAR48 VAR67 VAR31 for VAR59 VAR1 VAR51 not VAR60.");
wire [VAR8*2-1:0] ... | bsd-3-clause |
everskar2013/PentiumX | Hardware/Code/seven_seg_Dev_IO.v | 1,653 | module MODULE1(
clk,
rst,
VAR6,
VAR1,
VAR2,
VAR7,
VAR9,
VAR10,
VAR8,
VAR4,
VAR11,
VAR3,
VAR5
);
input clk, rst, VAR6;
input [ 2: 0] VAR1;
input [31: 0] VAR2, VAR7, VAR9, VAR10, VAR8, VAR4, VAR11, VAR3;
output reg [31: 0] VAR5 = 32'h0;
always @(negedge clk or posedge rst) begin
if ( rst ) VAR5 <= 32'hAA5555AA;
end
else ... | mit |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/SGMII_TX1.v | 16,710 | module MODULE1(
clk,
reset,
VAR12,
VAR30,VAR50,
VAR24,
VAR52,
VAR1,
VAR9,VAR41,
VAR4,VAR6,
VAR23,
VAR25,
VAR20,
VAR51,
VAR42,
VAR29,
VAR40,
VAR31 );
input clk;
input reset;
input VAR12;
output [7:0] VAR30;
output VAR50;
output VAR24;
output VAR52;
output VAR1;
output VAR9;
input VAR41;
input VAR4;
input VAR6;
input VAR... | apache-2.0 |
ptracton/wb_dsp | behavioral/adc/adc.v | 2,548 | module MODULE1 (
VAR11, VAR6,
VAR10, VAR3, VAR2, enable
) ;
parameter VAR7 = 8;
parameter VAR5 = "";
input VAR10;
input VAR3;
input VAR2;
input enable;
output reg [VAR7-1:0] VAR11;
output wire VAR6;
reg [2:0] VAR1;
reg VAR9;
reg [VAR7-1:0] memory [1023:0];
reg [31:0] VAR8;
reg [31:0] VAR4; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3/sky130_fd_sc_hd__or3.behavioral.pp.v | 1,801 | module MODULE1 (
VAR6 ,
VAR14 ,
VAR7 ,
VAR4 ,
VAR2,
VAR8,
VAR3 ,
VAR12
);
output VAR6 ;
input VAR14 ;
input VAR7 ;
input VAR4 ;
input VAR2;
input VAR8;
input VAR3 ;
input VAR12 ;
wire VAR13 ;
wire VAR10;
or VAR1 (VAR13 , VAR7, VAR14, VAR4 );
VAR11 VAR5 (VAR10, VAR13, VAR2, VAR8);
buf VAR9 (VAR6 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2b/sky130_fd_sc_hs__and2b.behavioral.v | 1,825 | module MODULE1 (
VAR10 ,
VAR4 ,
VAR7 ,
VAR6,
VAR9
);
output VAR10 ;
input VAR4 ;
input VAR7 ;
input VAR6;
input VAR9;
wire VAR10 VAR13 ;
wire VAR11 ;
wire VAR8;
not VAR1 (VAR13 , VAR4 );
and VAR5 (VAR11 , VAR13, VAR7 );
VAR12 VAR2 (VAR8, VAR11, VAR6, VAR9);
buf VAR3 (VAR10 , VAR8 );
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way_2-tree/src/riffa/tx_multiplexer_32.v | 18,416 | module MODULE1
parameter VAR104 = 9'd32,
parameter VAR18 = 4'd12,
parameter VAR29 = 5, parameter VAR3 = "VAR56"
)
(
input VAR66,
input VAR27,
input [VAR18-1:0] VAR10, input [(VAR18*VAR23)-1:0] VAR52, input [(VAR18*VAR49)-1:0] VAR105, input [(VAR18*VAR104)-1:0] VAR74, output [VAR18-1:0] VAR109, output [VAR18-1:0] VAR12,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1n/sky130_fd_sc_hdll__inputiso1n.blackbox.v | 1,363 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR5
);
output VAR4 ;
input VAR1 ;
input VAR5;
supply1 VAR2;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xnor2/sky130_fd_sc_hvl__xnor2.behavioral.pp.v | 1,836 | module MODULE1 (
VAR10 ,
VAR5 ,
VAR9 ,
VAR13,
VAR6,
VAR8 ,
VAR3
);
output VAR10 ;
input VAR5 ;
input VAR9 ;
input VAR13;
input VAR6;
input VAR8 ;
input VAR3 ;
wire VAR12 ;
wire VAR7;
xnor VAR4 (VAR12 , VAR5, VAR9 );
VAR1 VAR11 (VAR7, VAR12, VAR13, VAR6);
buf VAR2 (VAR10 , VAR7 );
endmodule | apache-2.0 |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/AXIvideo2Mat.v | 42,480 | module MODULE1 (
VAR57,
VAR22,
VAR25,
VAR65,
VAR127,
VAR107,
VAR63,
VAR98,
VAR32,
VAR26,
VAR78,
VAR33,
VAR13,
VAR40,
VAR42,
VAR19,
VAR139,
VAR92,
VAR10,
VAR131,
VAR94,
VAR134,
VAR34,
VAR69,
VAR154,
VAR152,
VAR160,
VAR113,
VAR41,
VAR47,
VAR59,
VAR91,
VAR36,
VAR77,
VAR48,
VAR97,
VAR21
);
parameter VAR68 = 8'd1;
parameter... | mit |
rkrajnc/minimig-de1 | rtl/or1200/or1200_mult_mac.v | 10,340 | module MODULE1(
clk, rst,
VAR60, VAR50, VAR20, VAR21, VAR57, VAR58, VAR51, VAR38, VAR13,
VAR59, VAR8, VAR6, VAR33, VAR19
);
parameter VAR16 = VAR3;
input clk;
input rst;
input VAR60;
input VAR50;
input VAR20;
input [VAR16-1:0] VAR21;
input [VAR16-1:0] VAR57;
input [VAR41-1:0] VAR58;
input [VAR7-1:0] VAR51;
output [VAR1... | gpl-3.0 |
which0326/ca_project2 | code/dcache_top.v | 5,307 | module MODULE1
(
VAR2,
VAR49,
VAR10,
VAR26,
VAR31,
VAR11,
VAR35,
VAR40,
VAR38,
VAR9,
VAR4,
VAR19,
VAR44,
VAR48
);
input VAR2;
input VAR49;
input [256-1:0] VAR10;
input VAR26;
output [256-1:0] VAR31;
output [32-1:0] VAR11;
output VAR35;
output VAR40;
input [32-1:0] VAR38;
input [32-1:0] VAR9;
input VAR4;
input VAR19;
ou... | cc0-1.0 |
alexforencich/verilog-ethernet | example/DE5-Net/fpga/rtl/si570_i2c_init.v | 15,865 | module MODULE1 (
input wire clk,
input wire rst,
output wire [6:0] VAR12,
output wire VAR9,
output wire VAR2,
output wire VAR4,
output wire VAR7,
output wire VAR14,
output wire VAR10,
input wire VAR16,
output wire [7:0] VAR13,
output wire VAR1,
input wire VAR8,
output wire VAR6,
output wire VAR5,
input wire VAR11
);
lo... | mit |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/decoder_ip_export/src/stego_decode.v | 3,286 | module MODULE1(clk, rst, VAR21, VAR2, VAR7, VAR25);
output VAR25, VAR7;
input clk, rst, VAR21;
input [7:0] VAR2;
wire VAR25;
wire VAR7;
wire [11:0] VAR6;
wire VAR29;
reg VAR9;
reg VAR20;
reg VAR14;
reg signed [8:0] VAR3 = {9'd228};
reg signed [11:0] VAR23;
reg signed [20:0] VAR1;
reg signed [20:0] VAR22;
reg signed [8:... | gpl-3.0 |
parallella/oh | padring/hdl/oh_pads_domain.v | 4,370 | module MODULE1
( inout [VAR10-1:0] VAR13, inout VAR14, inout VAR7, inout VAR8, inout VAR26, inout VAR23, input [VAR10-1:0] dout, output [VAR10-1:0] din, input [VAR10-1:0] VAR4, input [VAR10-1:0] VAR33, input [VAR10*8-1:0] VAR17 );
generate
genvar VAR12;
for(VAR12=0;VAR12<VAR10;VAR12=VAR12+1)
begin : VAR3
VAR18 #(.VAR11... | mit |
sehugg/8bitworkshop | presets/verilog-vga/chardisplay.v | 1,853 | module MODULE1(clk, reset, VAR21, VAR11, VAR27);
input clk, reset;
output VAR21, VAR11;
output [2:0] VAR27;
wire VAR23;
wire [9:0] VAR6;
wire [9:0] VAR10;
wire [9:0] VAR28;
wire [7:0] VAR4;
reg [7:0] VAR15;
reg VAR26 = 0;
VAR18 VAR3(
.clk(clk),
.dout(VAR4),
.din(VAR15),
.addr(VAR28),
.VAR1(VAR26)
);
VAR17 VAR5(
.clk(cl... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_3.behavioral.pp.v | 1,159 | module MODULE1( VAR6, VAR3, VAR4, VAR5 );
input VAR6;
inout VAR4, VAR5;
output VAR3;
VAR7 VAR1(.VAR6(VAR6),.VAR3(VAR3),.VAR4(VAR4),.VAR5(VAR5));
VAR7 VAR2(.VAR6(VAR6),.VAR3(VAR3),.VAR4(VAR4),.VAR5(VAR5)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/temac_v6_v1_5/example_design/client/fifo/eth_fifo_8.v | 7,982 | module MODULE1 (
VAR1, VAR13, VAR17, VAR10, VAR29, VAR7, VAR22, VAR19, VAR50,
VAR49, VAR41, VAR33, VAR4, VAR34, VAR39, VAR57, VAR38, VAR42,
VAR16, VAR51, VAR48, VAR44, VAR32, VAR37, VAR6, VAR24,
VAR55, VAR54, VAR23, VAR26, VAR15, VAR2, VAR43, VAR46 );
parameter VAR53 = 0;
input VAR1;
input VAR13;
input VAR17;
output [7... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbn/sky130_fd_sc_lp__dlxbn.behavioral.pp.v | 2,056 | module MODULE1 (
VAR18 ,
VAR5 ,
VAR12 ,
VAR1,
VAR13 ,
VAR10 ,
VAR17 ,
VAR16
);
output VAR18 ;
output VAR5 ;
input VAR12 ;
input VAR1;
input VAR13 ;
input VAR10 ;
input VAR17 ;
input VAR16 ;
wire VAR8 ;
wire VAR11 ;
wire VAR7;
wire VAR2 ;
reg VAR6 ;
VAR15 VAR3 (VAR11 , VAR2, VAR8, VAR6, VAR13, VAR10);
not VAR9 (VAR8 , V... | apache-2.0 |
sehugg/8bitworkshop | presets/verilog/music.v | 6,108 | module MODULE2(clk, reset, out, VAR23, VAR6, VAR24);
input clk, reset;
input [3:0] VAR23; input [7:0] VAR6; input VAR24; output [7:0] out;
parameter VAR28 = 4;
reg VAR26[0:VAR28-1];
reg [11:0] VAR8[0:VAR28-1];
reg [7:0] register[0:15];
reg [5:0] VAR21;
integer VAR20;
always @(posedge clk) begin
if (VAR21 == 0) begin
ou... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4b/sky130_fd_sc_ls__nor4b_2.v | 2,302 | module MODULE2 (
VAR7 ,
VAR10 ,
VAR11 ,
VAR4 ,
VAR9 ,
VAR3,
VAR2,
VAR6 ,
VAR8
);
output VAR7 ;
input VAR10 ;
input VAR11 ;
input VAR4 ;
input VAR9 ;
input VAR3;
input VAR2;
input VAR6 ;
input VAR8 ;
VAR1 VAR5 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.... | apache-2.0 |
sam-falvo/kestrel | cores/KCP53K/cpu2/rtl/verilog/lsu.v | 7,547 | module MODULE1(
input VAR46,
input VAR49,
input [63:0] VAR44,
input VAR25,
input VAR55,
input VAR57,
input [2:0] VAR61,
input [63:0] VAR13,
input [4:0] VAR8,
output VAR54,
output [2:0] VAR47,
output [63:0] VAR36,
output [4:0] VAR51,
output [63:0] VAR2,
output [15:0] VAR32,
output VAR6,
output VAR34,
output VAR35,
outpu... | mpl-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/hps_sdram_p0_generic_ddio.v | 2,314 | module MODULE1(
VAR25,
VAR8,
VAR2,
VAR24,
VAR11
);
parameter VAR16 = 1;
localparam VAR14 = 4 * VAR16;
localparam VAR3 = VAR16;
input [VAR14-1:0] VAR25;
input VAR8;
input [VAR16-1:0] VAR24;
input [VAR16-1:0] VAR11;
output [VAR3-1:0] VAR2;
generate
genvar VAR5;
for (VAR5 = 0; VAR5 < VAR16; VAR5 = VAR5 + 1)
begin:VAR17
wi... | mit |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v | 53,459 | module MODULE1 (
VAR173,
VAR100,
VAR134,
VAR95,
VAR59,
VAR170,
VAR169,
VAR133,
VAR132,
VAR174,
VAR116,
VAR77,
VAR34,
VAR17,
VAR165,
VAR88,
VAR117,
VAR12,
VAR13,
VAR106,
VAR175,
VAR26,
VAR83,
VAR67,
VAR24,
VAR46,
VAR127
);
parameter VAR171 = 0;
parameter VAR53 = 0;
parameter VAR92 = 32;
parameter VAR91 = 20;
parameter V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp.functional.v | 1,772 | module MODULE1 (
VAR8 ,
VAR4,
VAR9 ,
VAR12,
VAR11
);
output VAR8 ;
input VAR4;
input VAR9 ;
input VAR12;
input VAR11;
wire VAR10 ;
wire VAR2;
VAR5 VAR3 (VAR2, VAR9, VAR12, VAR11 );
VAR6 VAR13 VAR7 (VAR10 , VAR2, VAR4 );
buf VAR1 (VAR8 , VAR10 );
endmodule | apache-2.0 |
danbone/core | instr_decoder.v | 13,372 | module MODULE1 (
input [31:0] VAR7,
input [31:0] VAR19 ,
output VAR140 ,
output VAR45 ,
output VAR99 ,
output [1:0] VAR76 ,
output [VAR29-1:0] VAR142 ,
output VAR97 ,
output VAR104 ,
output [31:0] VAR130 ,
output [31:0] VAR24 ,
output [VAR137-1:0] VAR103 ,
output VAR11 ,
output [31:0] VAR109 ,
output [31:0] VAR123 ,
ou... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_1.behavioral.pp.v | 1,069 | module MODULE1( VAR4, VAR3 );
inout VAR4, VAR3;
VAR1 VAR2(.VAR4(VAR4),.VAR3(VAR3));
VAR1 VAR5(.VAR4(VAR4),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxtp/sky130_fd_sc_hd__sedfxtp_1.v | 2,466 | module MODULE1 (
VAR11 ,
VAR4 ,
VAR3 ,
VAR12 ,
VAR9 ,
VAR6 ,
VAR10,
VAR8,
VAR1 ,
VAR7
);
output VAR11 ;
input VAR4 ;
input VAR3 ;
input VAR12 ;
input VAR9 ;
input VAR6 ;
input VAR10;
input VAR8;
input VAR1 ;
input VAR7 ;
VAR2 VAR5 (
.VAR11(VAR11),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1... | apache-2.0 |
lsnow/mips32 | mul.v | 7,089 | module MODULE1(
VAR40,
VAR35, VAR15, VAR17
);
input [31:0] VAR35, VAR15;
input VAR17;
output [63:0] VAR40;
wire [63:0] VAR25, VAR14, VAR24;
reg [31:0] VAR26;
reg [4:0] VAR1;
wire [31:0] VAR39 = VAR15[0] ? VAR35 : 32'b0;
wire [31:0] VAR5 = VAR15[1] ? VAR35 : 32'b0;
wire [31:0] VAR12 = VAR15[2] ? VAR35 : 32'b0;
wire [31:... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_4.behavioral.v | 3,096 | module MODULE1( VAR1, VAR3, VAR5, VAR4, VAR8 );
input VAR3, VAR4, VAR5;
output VAR8, VAR1;
VAR6 VAR7(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4),.VAR8(VAR8));
VAR6 VAR2(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4),.VAR8(VAR8)); | apache-2.0 |
asicguy/gplgpu | hdl/de_temp/ded_funshf.v | 6,836 | module MODULE1
(
input VAR3,
output reg [(VAR23<<3)-1:0] VAR20, output [VAR23-1:0] VAR16 );
reg [(VAR23<<4)-1:0] VAR1; reg [31:0] VAR13;
reg [4:0] VAR14;
wire [1:0] VAR24;
wire [1:0] VAR17;
wire [3:0] VAR10;
wire [127:0] VAR19;
wire [135:0] VAR22;
wire [151:0] VAR25;
wire [183:0] VAR26;
wire [VAR23-1:0] VAR6;
wire [VAR... | gpl-3.0 |
romovs/xula-lib-verilog | camera/SCCBCtrl.v | 8,442 | module MODULE1 (VAR11, VAR7, VAR16, VAR17, VAR1, VAR12, VAR4, VAR3, VAR18, VAR14,
VAR15, VAR20, VAR9);
input VAR11; input VAR7; input VAR16; input VAR17; input [7:0] VAR1; input [15:0] VAR12; output reg [7:0] VAR4; input VAR3; input VAR18; output VAR14; output reg VAR15; output VAR20; inout VAR9;
reg VAR8 = 1;
reg [6:0... | gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/controller_command_fifo.v | 13,456 | module MODULE1(
clk,
rst,
din,
VAR350,
VAR41,
dout,
VAR47,
VAR55,
VAR225
);
input clk;
input rst;
input [127 : 0] din;
input VAR350;
input VAR41;
output [127 : 0] dout;
output VAR47;
output VAR55;
output [4 : 0] VAR225;
VAR81 #(
.VAR102(0),
.VAR190(0),
.VAR310(0),
.VAR70(0),
.VAR201(0),
.VAR7(0),
.VAR236(0),
.VAR127(32... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tap/sky130_fd_sc_hdll__tap.symbol.v | 1,236 | module MODULE1 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_mm_interconnect_0_avalon_st_adapter_003.v | 6,161 | module MODULE1 #(
parameter VAR1 = 10,
parameter VAR15 = 0,
parameter VAR19 = 10,
parameter VAR24 = 0,
parameter VAR25 = 0,
parameter VAR21 = 0,
parameter VAR20 = 1,
parameter VAR8 = 1,
parameter VAR5 = 0,
parameter VAR16 = 10,
parameter VAR7 = 0,
parameter VAR18 = 1,
parameter VAR12 = 0,
parameter VAR9 = 1,
parameter ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21a/sky130_fd_sc_lp__o21a_m.v | 2,245 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR9 ,
VAR4 ,
VAR6,
VAR2,
VAR3 ,
VAR5
);
output VAR7 ;
input VAR1 ;
input VAR9 ;
input VAR4 ;
input VAR6;
input VAR2;
input VAR3 ;
input VAR5 ;
VAR10 VAR8 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE1 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2_lp.v | 2,105 | module MODULE2 (
VAR4 ,
VAR8 ,
VAR5 ,
VAR1,
VAR9,
VAR3 ,
VAR7
);
output VAR4 ;
input VAR8 ;
input VAR5 ;
input VAR1;
input VAR9;
input VAR3 ;
input VAR7 ;
VAR2 VAR6 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR4,
VAR8,
VAR5
);
output VAR4;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21a/sky130_fd_sc_lp__o21a.behavioral.pp.v | 1,998 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR12 ,
VAR8 ,
VAR1,
VAR9,
VAR6 ,
VAR3
);
output VAR11 ;
input VAR2 ;
input VAR12 ;
input VAR8 ;
input VAR1;
input VAR9;
input VAR6 ;
input VAR3 ;
wire VAR16 ;
wire VAR4 ;
wire VAR13;
or VAR5 (VAR16 , VAR12, VAR2 );
and VAR10 (VAR4 , VAR16, VAR8 );
VAR7 VAR14 (VAR13, VAR4, VAR1, VAR9);
b... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_non_blocking_dma.v | 8,879 | module MODULE1
import VAR96::*;
, parameter VAR70(VAR91)
, parameter VAR70(VAR42)
, parameter VAR70(VAR7)
, parameter VAR70(VAR13)
, parameter VAR95=VAR56(VAR7)
, parameter VAR110=VAR56(VAR13)
, parameter VAR40=VAR56(VAR42)
, parameter VAR62=VAR56(VAR91>>3)
, parameter VAR87=(VAR2-VAR95-VAR40-VAR62)
, parameter VAR58=V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4bb/sky130_fd_sc_hs__nand4bb.pp.blackbox.v | 1,304 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR5 ,
VAR1 ,
VAR6 ,
VAR7,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR5 ;
input VAR1 ;
input VAR6 ;
input VAR7;
input VAR3;
endmodule | apache-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_outputcontrol.v | 6,347 | module MODULE1(VAR10, VAR1, VAR4, VAR13, VAR14, VAR5, VAR6, VAR16, VAR8, VAR7);
parameter VAR2 = 1;
input VAR10; input VAR1; input VAR5; input VAR6; input VAR4; input VAR13; input [6:0] VAR14; input VAR16;
output VAR8; output VAR7;
wire VAR15;
reg VAR12;
reg VAR11;
reg VAR7;
reg VAR9;
reg VAR3;
reg VAR8;
assign VAR15 =... | gpl-2.0 |
mshr-h/verilog_building_block | rtl/uart_rx.v | 1,509 | module MODULE1
(
input wire clk, input wire VAR13,
input wire VAR14,
output reg [7:0] VAR5,
output reg VAR8
);
localparam VAR12 = 0;
localparam VAR4 = 1;
localparam VAR1 = 2;
localparam VAR11 = 3;
localparam VAR6 = 4;
localparam VAR10 = 5;
localparam VAR7 = 6;
localparam VAR9 = 7;
localparam VAR3 = 8;
localparam VAR2 =... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/ddr_ctrl_ip_controller_phy.v | 14,790 | module MODULE1 (
VAR113,
VAR51,
VAR164,
VAR33,
VAR94,
VAR3,
VAR172,
VAR29,
VAR48,
VAR127,
VAR17,
VAR162,
VAR37,
VAR145,
VAR108,
VAR126,
VAR143,
VAR155,
VAR18,
VAR58,
VAR116,
VAR13,
VAR16,
VAR39,
VAR1,
VAR144,
VAR156,
VAR93,
VAR167,
VAR73,
VAR125,
VAR77,
VAR66,
VAR7,
VAR78,
VAR133,
VAR64,
VAR97,
VAR30,
VAR11,
VAR119,
VA... | gpl-2.0 |
richard42/CoCo3FPGA | 6850RX.v | 5,108 | module MODULE1(
VAR7,
VAR14,
VAR5,
VAR13,
VAR3,
VAR12,
VAR6,
VAR9,
VAR8,
VAR4
);
input VAR7;
input VAR14;
input VAR5;
output [7:0] VAR13;
reg [7:0] VAR13;
input VAR3;
input VAR12;
input VAR6;
output VAR9;
reg VAR9;
output VAR8;
reg VAR8;
output VAR4;
reg VAR4;
reg [5:0] VAR2;
reg [2:0] VAR1;
reg VAR10;
reg VAR11;
alway... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2/sky130_fd_sc_ls__nor2_2.v | 2,086 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR9 ,
VAR1,
VAR2,
VAR3 ,
VAR8
);
output VAR6 ;
input VAR4 ;
input VAR9 ;
input VAR1;
input VAR2;
input VAR3 ;
input VAR8 ;
VAR5 VAR7 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR6,
VAR4,
VAR9
);
output VAR6;
... | apache-2.0 |
Jside/pdp1 | pdp1_opr_decoder.v | 2,547 | module MODULE1(VAR18, VAR4, VAR5, VAR12,
VAR6, VAR9, VAR3, VAR14, VAR15);
parameter VAR10 = "VAR11-1";
input VAR18;
input [0:11] VAR4;
input [0:17] VAR5;
input [0:17] VAR12;
input [0:5] VAR6;
input [0:17] VAR9;
output [0:17] VAR3;
output [0:17] VAR14;
output [0:5] VAR15;
wire [0:18] VAR17;
wire [0:18] VAR2;
wire [0:18]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4bb/sky130_fd_sc_hs__nor4bb_2.v | 2,198 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR2 ,
VAR7 ,
VAR9 ,
VAR3,
VAR4
);
output VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR7 ;
input VAR9 ;
input VAR3;
input VAR4;
VAR8 VAR1 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR6 ,
VAR5 ,
VAR2 ,
VAR7,
VAR9
... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/ten_100_1g_eth_fifo.v | 6,882 | module MODULE1 #
(
parameter VAR25 = 0
)
(
input VAR12, input VAR17, input [7:0] VAR15,
input VAR24,
input VAR32,
output VAR34,
input VAR20, input VAR39, output [7:0] VAR30,
output VAR10,
output VAR5,
input VAR28,
output VAR11,
output VAR8,
output [3:0] VAR3,
input VAR33,
input VAR13,
input VAR38, input VAR18, output [... | mit |
skarpenko/ultiparc | rtl/src/fabric_port_demux.v | 3,461 | module MODULE1(
VAR7,
VAR1,
VAR25,
VAR21,
VAR18,
VAR23,
VAR24,
VAR6,
VAR8,
VAR4,
VAR17,
VAR20,
VAR5,
VAR16,
VAR15,
VAR19,
VAR9,
VAR11,
VAR14,
VAR10,
VAR3,
VAR12
);
input wire VAR7;
input wire [VAR2-1:0] VAR1;
input wire [2:0] VAR25;
input wire [VAR22-1:0] VAR21;
input wire [VAR13-1:0] VAR18;
output reg VAR23;
output re... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregsbp/sky130_fd_sc_lp__sregsbp.pp.blackbox.v | 1,397 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR3 ,
VAR10 ,
VAR1 ,
VAR4 ,
VAR6,
VAR8 ,
VAR5 ,
VAR2 ,
VAR11
);
output VAR9 ;
output VAR7 ;
input VAR3 ;
input VAR10 ;
input VAR1 ;
input VAR4 ;
input VAR6;
input VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR11 ;
endmodule | apache-2.0 |
AndreaCorallo/KPU | rtl/kpu/int_ctrl.v | 2,817 | module MODULE1(
input wire VAR5,
input wire VAR3,
input wire [VAR6-1:0] VAR7, output reg VAR4, output reg [VAR2-1:0] VAR1 ); | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221o/sky130_fd_sc_hd__a221o.pp.symbol.v | 1,401 | module MODULE1 (
input VAR4 ,
input VAR1 ,
input VAR10 ,
input VAR8 ,
input VAR6 ,
output VAR5 ,
input VAR9 ,
input VAR7,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4/sky130_fd_sc_hd__nor4.symbol.v | 1,321 | module MODULE1 (
input VAR5,
input VAR3,
input VAR6,
input VAR4,
output VAR8
);
supply1 VAR9;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
eckucukoglu/basic-vending-machine | src/lab3_2.v | 2,386 | module MODULE1(
input [2:0] VAR2,
input [1:0] VAR3,
input VAR5,
input VAR6,
output reg [7:0] VAR4,
output reg [5:0] VAR1);
begin
begin
end
begin
begin
begin
begin
begin
end
begin
end
begin
begin
begin
begin | gpl-2.0 |
MarcoVogt/basil | firmware/modules/utils/rbcp_to_bus.v | 1,448 | module MODULE1 (
input wire VAR12,
input wire VAR3,
input wire VAR14,
input wire [31:0] VAR11,
input wire [7:0] VAR4,
input wire VAR8,
input wire VAR9,
output reg VAR13,
output wire [7:0] VAR1,
output wire VAR10,
output wire VAR2,
output wire [31:0] VAR5,
inout wire [7:0] VAR7
);
always@(posedge VAR3) begin
if(VAR12)
V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp.functional.v | 1,732 | module MODULE1 (
VAR13 ,
VAR1 ,
VAR12 ,
VAR2 ,
VAR10
);
output VAR13 ;
input VAR1 ;
input VAR12 ;
input VAR2 ;
input VAR10;
wire VAR3;
wire VAR6 ;
VAR11 VAR8 (VAR3, VAR1, VAR12, VAR2 );
VAR5 VAR7 VAR9 (VAR6 , VAR3, VAR10 );
buf VAR4 (VAR13 , VAR6 );
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_axi_gpio_1_0/ip_design_axi_gpio_1_0_stub.v | 2,350 | module MODULE1(VAR8, VAR10, VAR9,
VAR5, VAR20, VAR13, VAR4, VAR11, VAR3,
VAR21, VAR6, VAR14, VAR17, VAR7, VAR19,
VAR16, VAR18, VAR12, VAR1, VAR15, VAR2)
;
input VAR8;
input VAR10;
input [8:0]VAR9;
input VAR5;
output VAR20;
input [31:0]VAR13;
input [3:0]VAR4;
input VAR11;
output VAR3;
output [1:0]VAR21;
output VAR6;
inp... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_048.v | 1,521 | module MODULE2 (
VAR14,
VAR8
);
input [31:0] VAR14;
output [31:0]
VAR8;
wire [31:0]
VAR9,
VAR5,
VAR12,
VAR6,
VAR2,
VAR1,
VAR4,
VAR11,
VAR10;
assign VAR9 = VAR14;
assign VAR11 = VAR4 << 7;
assign VAR10 = VAR2 - VAR11;
assign VAR2 = VAR12 - VAR6;
assign VAR12 = VAR5 - VAR9;
assign VAR5 = VAR9 << 14;
assign VAR6 = VAR9 <<... | mit |
donnaware/AGC | rtl/de0/modules/ng_CLG.v | 11,906 | module MODULE1(
input VAR34, input VAR37, input VAR58, input VAR40, input VAR51, input VAR43, input VAR47, input VAR63, input VAR44, input VAR62, input VAR33, input VAR49, input VAR67, output VAR25, output VAR70, output reg [3:0] VAR27, output VAR12, output VAR10, output VAR61, output VAR55, output VAR24, output VAR38 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211ai/sky130_fd_sc_hs__o211ai.behavioral.v | 1,942 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR8 ,
VAR11 ,
VAR2 ,
VAR5,
VAR12
);
output VAR4 ;
input VAR7 ;
input VAR8 ;
input VAR11 ;
input VAR2 ;
input VAR5;
input VAR12;
wire VAR2 VAR13 ;
wire VAR3 ;
wire VAR14;
or VAR15 (VAR13 , VAR8, VAR7 );
nand VAR6 (VAR3 , VAR2, VAR13, VAR11 );
VAR9 VAR1 (VAR14, VAR3, VAR5, VAR12);
buf VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtp/sky130_fd_sc_hd__dlrtp.symbol.v | 1,428 | module MODULE1 (
input VAR2 ,
output VAR3 ,
input VAR7,
input VAR5
);
supply1 VAR1;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/minsoc_startup/spi_shift.v | 6,588 | module MODULE1
(
clk, rst, VAR22, VAR23, VAR3, VAR21,
posedge, negedge,
VAR5, VAR19, VAR10,
VAR11, VAR12,
VAR15, VAR16, VAR7, VAR8, VAR2);
parameter VAR18 = 1;
input clk; input rst; input VAR22; input [3:0] VAR23; input [VAR14-1:0] VAR3; input VAR5; input VAR10;
input VAR19;
input VAR21; input posedge; input negedge; o... | gpl-2.0 |
campsandrew/ECE-474A-Program-1 | Modules/CIRCUIT6.v | 1,102 | module MODULE1(VAR24, VAR4, VAR6, VAR35, VAR19, VAR34, VAR21, VAR29, VAR11, VAR23, VAR12, VAR15);
input VAR23, VAR12;
input [15:0] VAR24, VAR4, VAR6, VAR35, VAR19, VAR34, VAR21, VAR29, VAR11;
output [15:0] VAR15;
reg [15:0] VAR30, VAR5, VAR38, VAR20, VAR7, VAR33, VAR36;
wire [15:0] VAR3;
wire [31:0] VAR25, VAR27, VAR10... | gpl-3.0 |
fpgasystems/Centaur | rtl/fthread/fthread_controller.v | 35,124 | module MODULE1 #(parameter VAR20 = 2,
parameter VAR139 = 2,
parameter VAR70 = 9) (
input wire clk,
input wire VAR47,
input wire VAR191,
input wire [VAR200-1:0] VAR102,
output reg VAR86,
output wire VAR185,
output wire VAR158,
output wire [67:0] VAR108,
input wire VAR15,
input wire VAR174,
input wire [VAR65-1:0] VAR198,... | apache-2.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/EmbededSystem/controlunit6.v | 7,368 | module MODULE1 (output reg VAR8, VAR16, VAR1, VAR6, VAR19, VAR18, VAR7, VAR17,VAR4,VAR9,VAR15,VAR11,VAR14,output reg[4:0] VAR12, output reg[3:0] VAR22, input VAR20, VAR13,VAR2, input [31:0] VAR3,input [3:0] VAR10);
reg [4:0] VAR21, VAR5;
always @ (negedge VAR2, posedge VAR13)
if (VAR13) begin
VAR21 <= 5'b00001;VAR18 = ... | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_gtp_pipe_drp.v | 11,710 | module MODULE1 #
(
parameter VAR9 = 2'd1, parameter VAR18 = 1'd0
)
(
input VAR24,
input VAR22,
input VAR11,
input VAR3,
input [15:0] VAR1,
input VAR6,
output [ 8:0] VAR10,
output VAR17,
output [15:0] VAR12,
output VAR35,
output VAR34,
output [ 2:0] VAR27
);
reg VAR20;
reg VAR7;
reg [15:0] VAR25;
reg VAR2;
reg VAR14;
re... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/lsu/rtl/lsu_tlbdp.v | 11,274 | module MODULE1(
VAR56, VAR43, VAR59, VAR4,
VAR46, VAR25, VAR84,
VAR44, VAR83, VAR85,
VAR87,
VAR26, VAR79, VAR86, VAR73, VAR49,
VAR30, VAR13, VAR24, VAR41,
VAR61, VAR37, VAR48,
VAR77, VAR55, VAR17
);
input VAR26;
input VAR79;
input VAR86;
output VAR56;
input [58:0] VAR73 ; input [42:0] VAR49 ; input VAR30 ;
input [39:10... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_sync_unmanaged.v | 2,060 | module MODULE1
, parameter VAR6(VAR17)
, parameter VAR6(VAR2)
, parameter VAR19 = VAR9(VAR5,1)
)
(input VAR11
, input VAR24
, input [VAR19-1:0] VAR4
, input VAR21
, input [VAR17-1:0] VAR20
, input [VAR2-1:0] VAR3
, output [VAR19-1:0] VAR13
, input VAR23
, input [VAR17-1:0] VAR14
, output logic [VAR2-1:0] VAR16
, output... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp.functional.pp.v | 2,169 | module MODULE1 (
VAR12 ,
VAR19 ,
VAR16 ,
VAR18 ,
VAR11,
VAR3,
VAR14,
VAR13 ,
VAR10
);
output VAR12 ;
input VAR19 ;
input VAR16 ;
input VAR18 ;
input VAR11;
input VAR3;
input VAR14;
input VAR13 ;
input VAR10 ;
wire VAR1 ;
wire VAR6 ;
wire VAR20;
VAR9 VAR7 (VAR1 , VAR19, VAR16, VAR18 );
VAR17 VAR4 VAR2 (VAR6 , VAR1, VAR1... | apache-2.0 |
dtysky/FPGA-Imaging-Library | LocalFilter/RankFilter/HDL/RankFilter.srcs/sources_1/new/Encoder.v | 2,255 | module MODULE1(VAR4, VAR1);
parameter VAR2 = 3;
parameter VAR3 = 4;
input[VAR2 * VAR2 - 1 : 0] VAR4;
output[VAR3 - 1 : 0] VAR1;
reg[VAR3 - 1 : 0] VAR5;
assign VAR1 = VAR5;
generate
case(VAR2)
2 :
always@ begin
case(VAR4)
1 : VAR5 <= 0;
2 : VAR5 <= 1;
4 : VAR5 <= 2;
8 : VAR5 <= 3;
16 : VAR5 <= 4;
32 : VAR5 <= 5;
64 : VA... | lgpl-2.1 |
klaNath/synth1 | synth_arb.v | 3,557 | module MODULE1 (
clk,
VAR15,
VAR7,
VAR5,
VAR18,
VAR13,
VAR11,
VAR12);
input wire clk, VAR15, VAR18, VAR12;
input wire [7:0] VAR7, VAR5;
output reg [7:0] VAR13, VAR11;
reg [7:0] VAR1;
reg [3:0] VAR22;
reg VAR23, VAR6;
always @(posedge VAR18, posedge VAR6, negedge VAR15)
begin
if(VAR15 == 0) VAR23 <= 0;
end
else if(VAR6 ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd.behavioral.pp.v | 1,200 | module MODULE1 (
VAR1,
VAR4,
VAR3 ,
VAR2
);
input VAR1;
input VAR4;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
jameshegarty/rigel | platform/camera1x/vsrc/cfifo32x16.v | 13,694 | module MODULE1(
rst,
VAR163,
VAR231,
din,
VAR128,
VAR388,
dout,
VAR363,
VAR246
);
input rst;
input VAR163;
input VAR231;
input [31 : 0] din;
input VAR128;
input VAR388;
output [31 : 0] dout;
output VAR363;
output VAR246;
VAR284 #(
.VAR102(0),
.VAR188(0),
.VAR59(0),
.VAR213(0),
.VAR269(0),
.VAR381(0),
.VAR326(0),
.VAR16... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxtp/sky130_fd_sc_ls__dfxtp.pp.symbol.v | 1,311 | module MODULE1 (
input VAR5 ,
output VAR1 ,
input VAR7 ,
input VAR3 ,
input VAR6,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
olofk/wb_intercon | rtl/verilog/wb_cdc.v | 2,586 | module MODULE1
(input VAR32,
input VAR20,
input [VAR24-1:0] VAR18,
input [31:0] VAR30,
input [3:0] VAR12,
input VAR8,
input VAR2,
input VAR5,
output [31:0] VAR4,
output VAR21,
input VAR27,
input VAR1,
output [VAR24-1:0] VAR26,
output [31:0] VAR33,
output [3:0] VAR28,
output VAR34,
output VAR7,
output VAR15,
input [31:0... | lgpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/bram_patch/BRAM1BE_cur.v | 4,016 | module MODULE1(VAR16,
VAR8,
VAR15,
VAR6,
VAR9,
VAR10
);
parameter VAR3 = 0;
parameter VAR17 = 1;
parameter VAR12 = 1;
parameter VAR5 = 1;
parameter VAR2 = 1;
parameter VAR7 = 1;
input VAR16;
input VAR8;
input [VAR2-1:0] VAR15;
input [VAR17-1:0] VAR6;
input [VAR12-1:0] VAR9;
output [VAR12-1:0] VAR10;
reg [VAR12-1:0] VAR... | lgpl-3.0 |
glennchid/font5-firmware | src/verilog/synthesis/align_monitor.v | 14,651 | module MODULE1(
input VAR5,
input VAR1,
input rst,
input VAR2,
input VAR25,
input VAR23,
output reg [6:0] VAR12,
output reg VAR15,
output reg [6:0] VAR31, output reg [6:0] VAR6, output reg [6:0] VAR14, output reg VAR16
);
reg VAR33;
reg VAR22;
reg VAR21;
reg [1:0] VAR27 = 2'b00;
reg VAR32;
reg VAR13;
reg VAR17;
reg VAR... | gpl-3.0 |
Microsoft/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_trn_monitor.v | 23,586 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR11, input wire [31:0] VAR61, input wire [31:0] VAR54, output reg VAR16, input wire VAR18,
input wire VAR2,
input wire VAR75, output reg [4:0] VAR105,
output reg [31:0] VAR108,
output reg VAR96,
output wire [4:0] VAR71,
input [31:0] VAR86,
output reg VAR19,
i... | bsd-2-clause |
benreynwar/fpga-sdrlib | verilog/fft/buffer_BB_to_stage.v | 3,133 | module MODULE1
parameter VAR12 = 8,
parameter VAR10 = 3,
parameter VAR1 = 32,
parameter VAR18 = 1
)
(
input wire clk,
input wire VAR14,
input wire VAR2,
input wire VAR15,
input wire [VAR1+VAR18-1: 0] VAR13,
output reg VAR19,
output wire [VAR10-1:0] VAR9,
output wire [VAR10-1:0] VAR20,
output reg VAR4,
output reg [VAR1-... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2/sky130_fd_sc_hd__and2.behavioral.pp.v | 1,783 | module MODULE1 (
VAR3 ,
VAR13 ,
VAR5 ,
VAR11,
VAR6,
VAR2 ,
VAR7
);
output VAR3 ;
input VAR13 ;
input VAR5 ;
input VAR11;
input VAR6;
input VAR2 ;
input VAR7 ;
wire VAR8 ;
wire VAR10;
and VAR9 (VAR8 , VAR13, VAR5 );
VAR1 VAR4 (VAR10, VAR8, VAR11, VAR6);
buf VAR12 (VAR3 , VAR10 );
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/ac97/rtl/ac97_dma.v | 3,753 | module MODULE1(
input VAR17,
input VAR12,
output reg [31:0] VAR8,
output [2:0] VAR2,
output reg VAR42,
output VAR28,
output VAR6,
input VAR31,
input [31:0] VAR41,
output [31:0] VAR25,
output reg VAR1,
input VAR14,
output reg VAR21,
output reg [19:0] VAR18,
output reg VAR37,
output reg [19:0] VAR16,
output reg VAR27,
in... | lgpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_48.v | 30,659 | module MODULE4 (
clk,
reset,
VAR79,
VAR87,
VAR137,
VAR10,
VAR232
);
parameter VAR213 = 18;
parameter VAR147 = 48;
parameter VAR201 = 24;
localparam VAR93 = 49;
input clk;
input reset;
input VAR79;
input VAR87;
input [VAR213-1:0] VAR137; output VAR10;
output [VAR213-1:0] VAR232;
localparam VAR84 = 18; localparam VAR274 ... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/mgt/rocketio_wrapper_tile_gt_usrclk_source.v | 11,408 | module MODULE1
(
input wire VAR94,
input wire VAR97,
output wire VAR43,
input wire VAR86,
input wire VAR11,
output wire VAR29,
input wire VAR96,
input wire VAR91,
output wire VAR72,
input wire VAR62,
input wire VAR48,
output wire VAR31,
output VAR49,
output VAR98,
input VAR28,
output VAR20,
output VAR95,
input VAR16,
o... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufkapwr/sky130_fd_sc_lp__bufkapwr.symbol.v | 1,309 | module MODULE1 (
input VAR2,
output VAR1
);
supply1 VAR7 ;
supply0 VAR4 ;
supply1 VAR5;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_dsp/spi.v | 3,187 | module MODULE1(
input clk,
input VAR23,
input VAR3,
inout VAR27,
input VAR24,
output VAR34,
output VAR8,
output [7:0] VAR20,
output [7:0] VAR15,
output VAR16,
output VAR10,
input [7:0] VAR12,
output [31:0] VAR29,
output [2:0] VAR5
);
reg [7:0] VAR4;
reg [7:0] VAR33;
reg [2:0] VAR11;
reg [2:0] VAR14;
always @(posedge cl... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_rf16x32.v | 15,268 | module MODULE1 (
dout, VAR39,
VAR32, VAR24, VAR19, VAR21, VAR1, VAR35, VAR14, VAR16,
VAR11, VAR20, VAR2, VAR27, VAR15, din
);
input VAR32;
input VAR24;
input VAR19;
input VAR21;
input VAR1; input VAR35;
input [6:0] VAR14 ; input [6:0] VAR16 ;
input VAR11 ; input VAR20 ;
input [6:2] VAR2 ;
input VAR27 ; input [15:0] VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busreceiver/sky130_fd_sc_lp__busreceiver.pp.symbol.v | 1,289 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR3 ,
input VAR1,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai.behavioral.pp.v | 2,206 | module MODULE1 (
VAR3 ,
VAR2,
VAR10,
VAR14 ,
VAR12 ,
VAR19,
VAR16,
VAR17 ,
VAR7
);
output VAR3 ;
input VAR2;
input VAR10;
input VAR14 ;
input VAR12 ;
input VAR19;
input VAR16;
input VAR17 ;
input VAR7 ;
wire VAR5 ;
wire VAR18 ;
wire VAR11 ;
wire VAR4;
nand VAR13 (VAR5 , VAR10, VAR2 );
or VAR8 (VAR18 , VAR12, VAR14 );
n... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxbp/sky130_fd_sc_ls__dfxbp.functional.v | 1,578 | module MODULE1 (
VAR7 ,
VAR4,
VAR9,
VAR10
);
output VAR7 ;
output VAR4;
input VAR9;
input VAR10 ;
wire VAR1;
VAR8 VAR2 VAR5 (VAR1 , VAR10, VAR9 );
buf VAR6 (VAR7 , VAR1 );
not VAR3 (VAR4 , VAR1 );
endmodule | apache-2.0 |
freecores/gost28147-89 | rtl/gost89_ecb.v | 7,969 | module MODULE2(
input clk,
input reset,
input VAR5,
input VAR7,
input [511:0] VAR2,
input [255:0] VAR6,
input [63:0] in,
output reg [63:0] out,
output reg VAR4
);
reg [5:0] VAR9;
reg [31:0] VAR1, VAR11, VAR8;
wire [31:0] VAR3, VAR12;
VAR10
rnd(clk, VAR2, VAR8, VAR1, VAR11, VAR3, VAR12);
always @(posedge clk) begin
if (... | bsd-3-clause |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cpu/apu/apu_frame_counter.v | 4,004 | module MODULE1
(
input VAR10, input VAR2, input VAR1, input VAR5, input [1:0] VAR8, input VAR6, output reg VAR15, output reg VAR11, output reg VAR13 );
reg [14:0] VAR9, VAR12;
reg VAR3, VAR7;
reg VAR4, VAR14;
always @(posedge VAR10)
begin
if (VAR2)
begin
VAR9 <= 15'h0000;
VAR3 <= 1'b0;
VAR4 <= 1'b0;
end
else
begin
VAR9... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211oi/sky130_fd_sc_hdll__a211oi.pp.symbol.v | 1,388 | module MODULE1 (
input VAR7 ,
input VAR9 ,
input VAR8 ,
input VAR1 ,
output VAR2 ,
input VAR5 ,
input VAR6,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_jtag_id.v | 2,322 | module MODULE1 (
VAR2
);
output [3:0] VAR2;
parameter [9:1] VAR3 = 9'b0;
parameter [9:1] VAR4 = 9'b0;
parameter [9:1] VAR1 = 9'b0;
parameter [9:1] VAR5 = 9'b0;
assign VAR2[0] = VAR5[1] ^ VAR5[2] ^ VAR5[3] ^ VAR5[4] ^ VAR5[5] ^ VAR5[6] ^ VAR5[7] ^ VAR5[8] ^ VAR5[9];
assign VAR2[1] = VAR1[1] ^ VAR1[2] ^ VAR1[3] ^ VAR1[4]... | gpl-2.0 |
SymbiFlow/fpga-tool-perf | third_party/picorv32_wrappers/picorv32_def.v | 4,312 | module MODULE1 #(
parameter [ 0:0] VAR39 = 1,
parameter [ 0:0] VAR62 = 1,
parameter [ 0:0] VAR56 = 1,
parameter [ 0:0] VAR10 = 1,
parameter [ 0:0] VAR23 = 0,
parameter [ 0:0] VAR4 = 1,
parameter [ 0:0] VAR52 = 0,
parameter [ 0:0] VAR54 = 0,
parameter [ 0:0] VAR53 = 0,
parameter [ 0:0] VAR32 = 0,
parameter [ 0:0] VAR9 =... | isc |
zhaishaomin/ring_network-based-multicore- | core/core.v | 16,212 | module MODULE1( clk,
rst,
VAR96,
VAR119,
VAR172,
VAR116,
VAR129,
VAR103,
VAR158,
VAR44,
VAR55,
VAR102
);
parameter VAR175=2'b10;
parameter VAR72=2'b11;
input clk;
input rst;
input VAR96;
input [31:0] VAR119;
input VAR172;
input [31:0] VAR116;
output [31:0] VAR129;
output VAR103;
output VAR158;
output [3:0] VAR44;
outpu... | apache-2.0 |
bzisjo/iq_compensation | src/iq_comp.v | 4,362 | module MODULE1 (
input clk, VAR1,
input VAR8, input [1:0] VAR29,
input [3:0] VAR10, VAR22,
input signed [12:0] VAR24, VAR2, output reg signed [3:0] VAR7, VAR21,
output wire VAR16, output reg signed [12:0] VAR13, VAR12
);
localparam VAR3 = 2'b00;
localparam VAR19 = 2'b01;
localparam VAR17 = 2'b10;
localparam VAR4 = 2'b1... | mit |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/v_axi4s_vid_out_v3_0/49ac95ae/hdl/verilog/v_axi4s_vid_out_v3_0_out_coupler.v | 7,084 | module MODULE1
parameter VAR21 = 24,
parameter VAR16 = 10, parameter VAR25 = 2
)
(
input wire VAR36, input wire rst , input wire VAR24, input wire VAR12, input VAR8, input VAR1, input VAR15, input wire [VAR21 +2:0] VAR22 , input valid , output reg ready, output wire [VAR21 -1:0] VAR10, output wire VAR27, output wire VA... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_dff_reset_en.v | 2,546 | if (VAR10 && VAR14==VAR7) \
begin: VAR6 \
VAR3 VAR13(.VAR15 \
,.VAR12 \
,.VAR5 \
,.VAR2(~VAR4) \
,.VAR8); \
end
module MODULE1 #(VAR14=-1, VAR10=1)
(input VAR16
,input VAR4
,input [VAR14-1:0] VAR12
,input VAR5
,output [VAR14-1:0] VAR8
);
else VAR1(32)
else VAR1(31)
else VAR1(30)
else VAR1(29)
else VAR1(28)
else VAR1(27... | bsd-3-clause |
zhaishaomin/ring_network-based-multicore- | core/core_pc.v | 1,864 | module MODULE1( clk,
rst,
VAR1,
VAR12,
VAR9,
VAR6,
VAR7, VAR14, VAR10,
VAR19,
VAR20,
VAR4,
VAR13
);
parameter VAR16=32'h00040000;
parameter VAR15=2'b00;
parameter VAR11=2'b01;
parameter VAR5=2'b10;
parameter VAR18=2'b11;
input clk;
input rst;
input [31:0] VAR1;
input [31:0] VAR12;
input VAR14;
input VAR6;
input VAR9;
i... | apache-2.0 |
Tsung-Wei/OpenTimer | example/optimizer/optimizer.v | 2,044 | module MODULE1 (
VAR77,
VAR28,
VAR6,
VAR7,
VAR1,
VAR45,
VAR34);
input VAR77;
input VAR28;
input VAR6;
input VAR7;
input VAR1;
input VAR45;
output VAR34;
wire VAR77;
wire VAR35;
wire VAR74;
wire VAR56;
wire VAR34;
wire VAR7;
wire VAR27;
wire VAR1;
wire VAR47;
wire VAR6;
wire VAR18;
wire VAR28;
wire VAR50;
wire VAR12;
wi... | gpl-3.0 |
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