repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311a/sky130_fd_sc_ls__o311a.functional.pp.v | 2,053 | module MODULE1 (
VAR17 ,
VAR3 ,
VAR13 ,
VAR10 ,
VAR4 ,
VAR16 ,
VAR2,
VAR6,
VAR15 ,
VAR12
);
output VAR17 ;
input VAR3 ;
input VAR13 ;
input VAR10 ;
input VAR4 ;
input VAR16 ;
input VAR2;
input VAR6;
input VAR15 ;
input VAR12 ;
wire VAR1 ;
wire VAR9 ;
wire VAR18;
or VAR14 (VAR1 , VAR13, VAR3, VAR10 );
and VAR5 (VAR9 , V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfsbp/sky130_fd_sc_ms__dfsbp.functional.pp.v | 1,956 | module MODULE1 (
VAR15 ,
VAR4 ,
VAR8 ,
VAR11 ,
VAR17,
VAR12 ,
VAR13 ,
VAR1 ,
VAR7
);
output VAR15 ;
output VAR4 ;
input VAR8 ;
input VAR11 ;
input VAR17;
input VAR12 ;
input VAR13 ;
input VAR1 ;
input VAR7 ;
wire VAR14;
wire VAR3 ;
not VAR5 (VAR3 , VAR17 );
VAR16 VAR9 VAR10 (VAR14 , VAR11, VAR8, VAR3, , VAR12, VAR13);
... | apache-2.0 |
asicguy/gplgpu | hdl/vga/crt_clk_gen.v | 13,914 | module MODULE1
(
input VAR19,
input VAR70,
input VAR60,
input VAR41,
input VAR14, input VAR96, input [15:0] VAR4, input [7:0] VAR106, input VAR81, input VAR45, input VAR29,
input VAR43, input VAR22, input VAR59, input VAR110,
input VAR61,
input VAR92,
input VAR104, input VAR56, input VAR99, input VAR62, input VAR25, in... | gpl-3.0 |
hcabrera-/lancetfish | RTL/processing_element/des_engine/rtl/des_sbox5.v | 3,336 | module MODULE1
(
input wire [0:5] VAR1,
output reg [0:3] VAR2
);
always @(*)
case ({VAR1[0], VAR1[5]})
2'b00:
case (VAR1[1:4])
4'd0: VAR2 = 4'd2;
4'd1: VAR2 = 4'd12;
4'd2: VAR2 = 4'd4;
4'd3: VAR2 = 4'd1;
4'd4: VAR2 = 4'd7;
4'd5: VAR2 = 4'd10;
4'd6: VAR2 = 4'd11;
4'd7: VAR2 = 4'd6;
4'd8: VAR2 = 4'd8;
4'd9: VAR2 = 4'd5;
... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/extramfifo/nobl_fifo.v | 3,850 | module MODULE1
(
input clk,
input rst,
input [VAR5-1:0] VAR8,
output [VAR5-1:0] VAR9,
output VAR12,
output [VAR21-1:0] VAR18,
output VAR1,
output VAR26,
output VAR11,
output VAR10,
output VAR14,
input [VAR5-1:0] VAR27,
input VAR16,
output reg VAR2,
output [VAR5-1:0] VAR15,
input VAR7, output VAR3, output reg [VAR17-1:0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2.behavioral.v | 1,208 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/rtl/verilog/ddr_ctrl_wrapper.v | 4,467 | module MODULE1 #(
parameter VAR12 = 25 )
(
output VAR2,
output VAR39,
input [31:0] VAR20,
output [31:0] VAR7,
input [31:0] VAR37,
output [31:0] VAR14,
input [3:0] VAR17,
input VAR10,
output VAR15,
input VAR16,
input [3:0] VAR19,
output [VAR12-3:0] VAR36,
output VAR25,
output VAR38,
output VAR6,
output [31:0] VAR29,
out... | gpl-2.0 |
secworks/cmac | src/rtl/cmac_core.v | 11,842 | module MODULE1(
input wire clk,
input wire VAR51,
input wire [255 : 0] VAR40,
input wire VAR37,
input wire [7 : 0] VAR48,
input wire VAR55,
input wire VAR13,
input wire VAR22,
input wire [127 : 0] VAR57,
output wire [127 : 0] VAR47,
output wire ready,
output wire valid
);
localparam VAR46 = 0;
localparam VAR42 = 1;
loc... | bsd-2-clause |
glennchid/font5-firmware | src/verilog/synthesis/antiDroopIIR.v | 2,157 | module MODULE1 (
input clk,
input VAR4,
input signed [12:0] din,
input signed [6:0] VAR2,
input VAR7,
output reg VAR9 = 1'd0,
output reg signed [15:0] dout = 16'VAR3);
parameter VAR12 = 15;
reg signed [12:0] VAR11 = 13'VAR3;
reg signed [47:0] VAR14 = 48'VAR3;
reg signed [19:0] VAR5 = 20'VAR3;
reg VAR1 = 1'b0, VAR13 = 1... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/up_hdmi_tx.v | 17,112 | module MODULE1 (
VAR6,
VAR95,
VAR34,
VAR53,
VAR55,
VAR42,
VAR20,
VAR3,
VAR54,
VAR64,
VAR89,
VAR63,
VAR100,
VAR49,
VAR80,
VAR22,
VAR44,
VAR88,
VAR92,
VAR16,
VAR13,
VAR31,
VAR33,
VAR37,
VAR94,
VAR72,
VAR35,
VAR18,
VAR51,
VAR73,
VAR87,
VAR7);
parameter VAR17 = 32'h00040062;
parameter VAR93 = 0;
input VAR6;
output VAR95;
o... | mit |
rossmacarthur/verilog-utilities | vga/VGA_Control.v | 1,117 | module MODULE1 (
input clk, input rst,
output reg VAR1, output reg VAR3, output reg [10:0] VAR2, output reg [9:0] VAR4 );
always @(posedge clk) begin
if(rst) begin
VAR2 <= 0;
VAR4 <= 0;
VAR1 <= 1;
VAR3 <= 1;
end else begin
if (VAR2 == 1343) begin
VAR2 <= 0;
if (VAR4 == 805) VAR4 <= 0;
end
else VAR4 <= VAR4 + 1'b1;
end ... | mit |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_0_stub.v | 2,281 | module MODULE1(VAR13, VAR15, VAR8, VAR2, VAR4, VAR14, VAR3, VAR9, VAR12, VAR7, VAR5, VAR1, VAR10, VAR6, VAR11)
;
input VAR13;
input VAR15;
output [31:0]VAR8;
output [2:0]VAR2;
output VAR4;
input VAR14;
output [31:0]VAR3;
output [3:0]VAR9;
output VAR12;
input VAR7;
input [1:0]VAR5;
input VAR1;
output VAR10;
output VAR6;... | mit |
airabinovich/finalArquitectura | CONTROL_UNIT/controlUnit/ControlUnit.v | 3,469 | module MODULE1(
input [5:0] VAR7,
output reg VAR8,
output reg VAR2,
output reg VAR4,
output reg VAR9,
output reg [1:0] VAR3,
output reg VAR6,
output reg VAR5,
output reg VAR1
);
always @* begin
case (VAR7)
'b100000:begin VAR8<=0;
VAR2<=0;
VAR4<=1;
VAR9<=1;
VAR6<=0;
VAR5<=1;
VAR1<=1;
VAR3<=2'b0;
end
'b100001:begin VAR8<... | lgpl-2.1 |
AmeerAbdelhadi/Multiported-RAM | dpram.v | 5,360 | module MODULE1
wire [VAR18-1:0] VAR6; VAR15 #( .VAR2 (VAR2 ), .VAR18 (VAR18 ), .VAR12(1 ), .VAR17(1 ), .VAR13 (VAR13 ), .VAR5 (VAR5 )) VAR16 ( .clk (clk ), .VAR14 (VAR14 ), .VAR10 (VAR10 ), .VAR8 (VAR8 ), .VAR3 (VAR3 ), .VAR1 (VAR6));
reg VAR19;
reg [VAR20(VAR2)-1:0] VAR22;
reg [VAR20(VAR2)-1:0] VAR21;
reg [VAR18-1:0] ... | bsd-3-clause |
skarpenko/ultiparc | rtl/src/sys_top.v | 6,717 | module MODULE1 (
clk,
VAR61
);
input wire clk;
input wire VAR61;
wire [VAR110-1:0] VAR65;
wire VAR95;
wire [VAR142-1:0] VAR37;
wire VAR106;
wire VAR122;
wire [VAR110-1:0] VAR46;
wire VAR34;
wire VAR63;
wire [VAR54-1:0] VAR117;
wire [VAR142-1:0] VAR79;
wire [VAR142-1:0] VAR51;
wire VAR86;
wire VAR25;
wire [VAR110-1:0] V... | bsd-2-clause |
eda-globetrotter/PicenoDecoders | andy/design/z.v | 2,083 | module MODULE1();
integer VAR1;
reg clk;
reg VAR2[0:13];
always begin
clk = 0;
clk = 1; end
begin
begin | mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_decerr_slave.v | 9,274 | module MODULE1 #
(
parameter integer VAR35 = 1,
parameter integer VAR32 = 32,
parameter integer VAR6 = 1,
parameter integer VAR16 = 1,
parameter integer VAR47 = 0,
parameter integer VAR24 = 2'b11
)
(
input wire VAR25,
input wire VAR13,
input wire [(VAR35-1):0] VAR20,
input wire VAR11,
output wire VAR34,
input wire VAR2... | mit |
chebykinn/university | circuitry/lab4/src/hdl/ex_stage.v | 4,452 | module MODULE1( input clk,
input rst,
input VAR4,
input VAR1,
input VAR34,
input VAR46,
input VAR38,
input VAR8,
input VAR30, input [1:0] VAR19,
input [1:0] VAR16,
input VAR10,
input [31:0] VAR15,
input [31:0] VAR6,
input [31:0] VAR9,
input [31:0] VAR31, input [4:0] VAR42, input [4:0] rd, input [5:0] VAR23,
input [1:0]... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/altera_jtag_dc_streaming/altera_avalon_st_idle_remover.v | 1,891 | module MODULE1 (
input clk,
input VAR9,
output reg VAR5,
input VAR10,
input [7: 0] VAR7,
input VAR6,
output reg VAR3,
output reg [7: 0] VAR1
);
reg VAR8;
wire VAR4, VAR2;
assign VAR2 = (VAR7 == 8'h4a);
assign VAR4 = (VAR7 == 8'h4d);
always @(posedge clk or negedge VAR9) begin
if (!VAR9) begin
VAR8 <= 0;
end else begin
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/decap/sky130_fd_sc_hvl__decap.pp.blackbox.v | 1,202 | module MODULE1 (
VAR3,
VAR1,
VAR2 ,
VAR4
);
input VAR3;
input VAR1;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3/sky130_fd_sc_ls__nand3_1.v | 2,175 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR10 ,
VAR2 ,
VAR8,
VAR1,
VAR6 ,
VAR7
);
output VAR9 ;
input VAR3 ;
input VAR10 ;
input VAR2 ;
input VAR8;
input VAR1;
input VAR6 ;
input VAR7 ;
VAR4 VAR5 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Position/I2C_Top.v | 10,431 | module MODULE1(
input clk,
input VAR27,
input rst,
input en,
input VAR22,
input VAR12,
input VAR24,
input VAR6,
input [7:0] VAR9,
output reg VAR34,
output reg VAR14,
output reg [7:0] VAR31,
output VAR4,
input VAR35,
output VAR13,
output VAR18
);
reg VAR8, VAR23, VAR2, VAR10, VAR16; wire VAR20, VAR33; VAR1 VAR7 ( .clk(c... | mit |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/async_dpram_32W_256D.v | 9,304 | module MODULE1 (
VAR52,
VAR5,
VAR1,
VAR47,
VAR43,
VAR45,
VAR8);
input [31:0] VAR52;
input [7:0] VAR5;
input VAR1;
input [7:0] VAR47;
input VAR43;
input VAR45;
output [31:0] VAR8;
tri1 VAR43;
tri0 VAR45;
wire [31:0] VAR54;
wire [31:0] VAR8 = VAR54[31:0];
VAR50 VAR17 (
.VAR39 (VAR47),
.VAR29 (VAR43),
.VAR48 (VAR52),
.VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211ai/sky130_fd_sc_hs__o211ai.symbol.v | 1,339 | module MODULE1 (
input VAR2,
input VAR7,
input VAR1,
input VAR3,
output VAR5
);
supply1 VAR4;
supply0 VAR6;
endmodule | apache-2.0 |
ayaovi/yoda | UART/UART_Rx.v | 3,353 | module MODULE1 #(
parameter VAR14 = 5,
parameter VAR10 = 5'd29 )(
input VAR19,
input VAR4,
output reg [7:0]VAR12,
output reg VAR3,
input VAR8,
input VAR2
);
reg VAR9;
reg VAR6;
reg [ 7:0]VAR11;
reg [VAR14-1:0]VAR5;
reg [ 2:0]VAR17;
reg VAR15;
reg [1:0]VAR16;
localparam VAR13 = 2'b00;
localparam VAR7 = 2'b01;
localparam... | gpl-3.0 |
LSaldyt/qnp | output/vs/opt_var6_multi.v | 2,573 | module MODULE1(VAR5, VAR3, VAR1, VAR4, VAR2, VAR6, valid);
wire 00;
wire 01;
wire 02;
wire 03;
wire 04;
wire 05;
wire 06;
wire 07;
wire 08;
wire 09;
wire 10;
wire 11;
wire 12;
wire 13;
wire 14;
wire 15;
wire 16;
wire 17;
wire 18;
wire 19;
wire 20;
wire 21;
wire 22;
wire 23;
wire 24;
wire 25;
wire 26;
wire 27;
wire 28;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41o/sky130_fd_sc_hd__a41o_2.v | 2,426 | module MODULE2 (
VAR5 ,
VAR10 ,
VAR6 ,
VAR11 ,
VAR1 ,
VAR4 ,
VAR8,
VAR9,
VAR3 ,
VAR7
);
output VAR5 ;
input VAR10 ;
input VAR6 ;
input VAR11 ;
input VAR1 ;
input VAR4 ;
input VAR8;
input VAR9;
input VAR3 ;
input VAR7 ;
VAR12 VAR2 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2.functional.v | 1,724 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR6,
VAR2
);
output VAR7 ;
input VAR10 ;
input VAR6;
input VAR2;
wire VAR5 ;
wire VAR3;
buf VAR8 (VAR5 , VAR10 );
VAR1 VAR4 (VAR3, VAR5, VAR6, VAR2);
buf VAR9 (VAR7 , VAR3 );
endmodule | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/soc/spi_dma_ext.v | 5,832 | module MODULE1
(
VAR33,
VAR36,
VAR25,
VAR13,
VAR32,
VAR21,
VAR41,
VAR16,
VAR18,
VAR27,
VAR19,
VAR35,
VAR30,
VAR23,
VAR3,
VAR14,
VAR1
);
parameter VAR38 = 18;
parameter VAR34 = 32;
parameter VAR20 = 4;
parameter VAR7 = 8;
input VAR33 ;
input VAR36 ;
output VAR25 ;
output VAR13 ;
output VAR32 ;
input VAR21 ;
output[VAR38... | mit |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_pcie_bram_7x.v | 8,934 | module MODULE1
parameter [3:0] VAR9 = 4'h1, parameter [5:0] VAR29 = 6'h08, parameter VAR12 = "VAR15", parameter VAR13 = 0, parameter VAR18 = 0 )
(
input VAR20, input VAR8,
input VAR23, input [12:0] VAR21, input [VAR18 - 1:0] VAR28,
input VAR3, input VAR5, input [12:0] VAR25,
output [VAR18 - 1:0] VAR4 );
localparam VAR1... | mit |
hewittc/proxmark3lcd | fpga/hi_read_rx_xcorr.v | 5,494 | module MODULE1(
VAR8, VAR9, VAR31,
VAR2, VAR6, VAR30, VAR27, VAR21, VAR12,
VAR28, VAR1,
VAR18, VAR19, VAR17, VAR15,
VAR13, VAR14,
VAR16,
VAR4, VAR20, VAR22
);
input VAR8, VAR9, VAR31;
output VAR2, VAR6, VAR30, VAR27, VAR21, VAR12;
input [7:0] VAR28;
output VAR1;
input VAR17;
output VAR18, VAR19, VAR15;
input VAR13, VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxbp/sky130_fd_sc_hs__edfxbp.functional.v | 1,757 | module MODULE1 (
VAR12 ,
VAR3 ,
VAR9 ,
VAR13 ,
VAR10 ,
VAR2,
VAR8
);
output VAR12 ;
output VAR3 ;
input VAR9 ;
input VAR13 ;
input VAR10 ;
input VAR2;
input VAR8;
wire VAR6;
VAR7 VAR1 VAR5 (VAR6 , VAR13, VAR9, VAR10, VAR2, VAR8);
buf VAR4 (VAR12 , VAR6 );
not VAR11 (VAR3 , VAR6 );
endmodule | apache-2.0 |
sundw2014/carADS | fpga_firmware/sr04_dis.v | 1,171 | module MODULE1(VAR4,clk,VAR2,VAR9);
input VAR4,clk,VAR2;
output VAR9;
reg[9:0]VAR9,VAR10;
wire VAR6,VAR8;
reg VAR7,VAR3;
parameter VAR11=2'b00;
parameter VAR1=2'b01;
parameter VAR5=2'b10;
reg [1:0]state;
assign VAR6=VAR7&~VAR3; assign VAR8=~VAR7&VAR3; always @(posedge clk or negedge VAR2)
begin
if(!VAR2)begin VAR7<=0;V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4b/sky130_fd_sc_hs__nor4b.pp.blackbox.v | 1,288 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR6 ,
VAR4 ,
VAR5 ,
VAR1,
VAR3
);
output VAR7 ;
input VAR2 ;
input VAR6 ;
input VAR4 ;
input VAR5 ;
input VAR1;
input VAR3;
endmodule | apache-2.0 |
pavel-demin/red-pitaya-notes | cores/axis_variant_v1_0/axis_variant.v | 1,312 | module MODULE1 #
(
parameter integer VAR1 = 32
)
(
input wire VAR2,
input wire VAR5,
input wire VAR3,
input wire [VAR1-1:0] VAR8,
input wire [VAR1-1:0] VAR13,
input wire VAR11,
output wire [VAR1-1:0] VAR10,
output wire VAR7
);
reg [VAR1-1:0] VAR4;
reg VAR6, VAR12;
wire [VAR1-1:0] VAR9;
assign VAR9 = VAR3 ? VAR13 : VAR8... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxtp/sky130_fd_sc_ms__sedfxtp.behavioral.pp.v | 2,629 | module MODULE1 (
VAR16 ,
VAR21 ,
VAR4 ,
VAR2 ,
VAR26 ,
VAR24 ,
VAR6,
VAR11,
VAR23 ,
VAR18
);
output VAR16 ;
input VAR21 ;
input VAR4 ;
input VAR2 ;
input VAR26 ;
input VAR24 ;
input VAR6;
input VAR11;
input VAR23 ;
input VAR18 ;
wire VAR20 ;
reg VAR28 ;
wire VAR10 ;
wire VAR15 ;
wire VAR27;
wire VAR13;
wire VAR8;
wire ... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/KOA_1c_approx.v | 6,511 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR20,
input wire [VAR32-1:0] VAR37,
input wire [VAR32-1:0] VAR18,
output wire [2*VAR32-1:0] VAR2
);
wire [1:0] VAR9;
wire [3:0] VAR14;
assign VAR9 = 2'b00;
assign VAR14 = 4'b0000;
wire [VAR32/2-1:0] VAR36;
wire [VAR32/2:0] VAR6;
wire [VAR32/2-3:0] VAR25;
wire... | gpl-3.0 |
manu3193/TextEditor | font_rom.v | 101,783 | module MODULE1
(
input wire clk,
input wire [10:0] addr,
output reg [7:0] VAR1
);
reg [10:0] VAR2;
always @(posedge clk)
VAR2 <= addr;
always @*
case (VAR2)
11'h000: VAR1 = 8'b00000000; 11'h001: VAR1 = 8'b00000000; 11'h002: VAR1 = 8'b00000000; 11'h003: VAR1 = 8'b00000000; 11'h004: VAR1 = 8'b00000000; 11'h005: VAR1 = 8'... | mit |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/controller_iobs.v | 6,876 | module MODULE1 (
VAR10,
VAR50,
VAR27,
VAR15,
VAR59,
VAR30,
VAR45,
VAR56,
VAR23,
VAR37,
VAR12,
VAR36,
VAR3,
VAR39,
VAR14,
VAR1,
VAR2,
VAR31,
VAR20,
VAR46,
VAR13,
VAR24,
VAR63
);
input VAR10;
input VAR50;
input VAR27;
input VAR15;
input VAR59;
input VAR30;
input [12:0]VAR45;
input [1:0]VAR56;
input VAR23;
input VAR37;
ou... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrbp/sky130_fd_sc_ms__dfrbp.functional.pp.v | 2,000 | module MODULE1 (
VAR10 ,
VAR14 ,
VAR13 ,
VAR8 ,
VAR11,
VAR1 ,
VAR4 ,
VAR6 ,
VAR3
);
output VAR10 ;
output VAR14 ;
input VAR13 ;
input VAR8 ;
input VAR11;
input VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR3 ;
wire VAR15;
wire VAR16;
not VAR12 (VAR16 , VAR11 );
VAR17 VAR7 VAR5 (VAR15 , VAR8, VAR13, VAR16, , VAR1, VAR4);
bu... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab3/db/ip/nios_system/submodules/nios_system_sram_data.v | 3,747 | module MODULE1 (
address,
VAR12,
clk,
VAR11,
VAR8,
VAR3,
VAR10,
VAR2
)
;
inout [ 15: 0] VAR10;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input VAR12;
input clk;
input VAR11;
input VAR8;
input [ 31: 0] VAR3;
wire [ 15: 0] VAR10;
wire VAR6;
reg [ 15: 0] VAR9;
wire [ 15: 0] VAR5;
reg [ 15: 0] VAR7;
wire [ 15: 0] VAR4;
... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController/src/m_axi_dma.v | 10,109 | module MODULE1 # (
parameter VAR14 = 32,
parameter VAR101 = 64,
parameter VAR46 = 1,
parameter VAR18 = 1,
parameter VAR92 = 1,
parameter VAR89 = 1,
parameter VAR87 = 1,
parameter VAR99 = 1
)
(
input VAR15,
input VAR72,
output [VAR46-1:0] VAR49,
output [VAR14-1:0] VAR22,
output [7:0] VAR40,
output [2:0] VAR13,
output [1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31a/sky130_fd_sc_lp__o31a_2.v | 2,322 | module MODULE2 (
VAR2 ,
VAR3 ,
VAR5 ,
VAR8 ,
VAR1 ,
VAR11,
VAR6,
VAR7 ,
VAR10
);
output VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR8 ;
input VAR1 ;
input VAR11;
input VAR6;
input VAR7 ;
input VAR10 ;
VAR4 VAR9 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR7(VAR7),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill/sky130_fd_sc_ls__fill.pp.symbol.v | 1,175 | module MODULE1 (
input VAR4 ,
input VAR3,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111a/sky130_fd_sc_lp__o2111a.blackbox.v | 1,394 | module MODULE1 (
VAR6 ,
VAR2,
VAR8,
VAR9,
VAR10,
VAR5
);
output VAR6 ;
input VAR2;
input VAR8;
input VAR9;
input VAR10;
input VAR5;
supply1 VAR7;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/example/S10DX_DK/fpga_10g/rtl/axis2avst.v | 3,094 | module MODULE1 #(
parameter VAR4 = 8,
parameter VAR1 = (VAR4/8),
parameter VAR8 = (VAR4>8),
parameter VAR25 = VAR14(VAR1),
parameter VAR5 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR4-1:0] VAR20,
input wire [VAR1-1:0] VAR13,
input wire VAR21,
output wire VAR3,
input wire VAR9,
input wire VAR10,
input wire VA... | mit |
alexforencich/xfcp | lib/eth/rtl/axis_eth_fcs_insert_64.v | 22,478 | module MODULE1 #
(
parameter VAR55 = 0,
parameter VAR91 = 64
)
(
input wire clk,
input wire rst,
input wire [63:0] VAR35,
input wire [7:0] VAR38,
input wire VAR90,
output wire VAR86,
input wire VAR5,
input wire VAR22,
output wire [63:0] VAR33,
output wire [7:0] VAR81,
output wire VAR32,
input wire VAR37,
output wire VA... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_port_lookup/cam_router/src/unencoded_cam_lut_sm_lpm.v | 8,263 | module MODULE1
parameter VAR35 = 3,
parameter VAR8 = 16,
parameter VAR50 = VAR43(VAR8),
parameter VAR22 = 0, parameter VAR13 = {VAR35{1'b0}}, parameter VAR44 = {VAR5{1'b0}}, parameter VAR49 = {VAR5{1'b0}} )
( input VAR51,
input [VAR5-1:0] VAR26,
input [VAR5-1:0] VAR39,
output reg VAR10,
output reg VAR16,
output [VAR35-... | mit |
azonenberg/antikernel-ipcores | noc/rpcv3/RPCv3RouterTransmitter_buffering.v | 8,569 | module MODULE1
parameter VAR5 = 32,
parameter VAR8 = 32
)
(
input wire clk,
output reg VAR1 = 0,
output reg[VAR5-1:0] VAR6 = 0,
input wire VAR9,
output wire[5:0] VAR7,
input wire VAR11,
input wire VAR2,
input wire[VAR8-1:0] VAR4,
output reg VAR3 = 0
, output VAR10
); | bsd-3-clause |
promach/cordic | rtl/cordic_pipelined.v | 2,548 | module MODULE1(clk, VAR8, VAR9, VAR19);
parameter VAR18 = 12;
parameter VAR15 = 17;
input clk;
input signed [VAR18:0] VAR8;
output reg signed [VAR15:0] VAR9, VAR19;
parameter VAR20 = 10;
reg [(VAR20-1):0] VAR12;
wire signed [VAR15:0] VAR17 [VAR20:0];
wire signed [VAR15:0] VAR13 [VAR20:0];
wire signed [VAR18:0] VAR3 [VA... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_arbdecdp.v | 21,621 | module MODULE1(
VAR143, VAR73, VAR121, VAR43,
VAR99, VAR36, VAR145,
VAR8, VAR37, VAR65,
VAR71, VAR115, VAR4,
VAR90, VAR130, VAR154,
VAR12, VAR112, VAR41,
VAR109, VAR63, VAR45,
VAR139, VAR89, VAR76,
VAR61, VAR40, VAR118,
VAR95, VAR103, VAR93,
VAR105, VAR84, VAR88,
VAR3, VAR53, VAR21,
VAR133, VAR135, VAR54,
VAR25, VAR13,... | gpl-2.0 |
chriz2600/DreamcastHDMI | Core/source/i2c_slave/registerInterface.v | 12,975 | module MODULE1 (
input clk,
input[7:0] addr,
input[7:0] VAR77,
input VAR71,
output[7:0] VAR34,
output[7:0] VAR54,
output[9:0] VAR74,
output VAR13,
output VAR21,
output[7:0] VAR61,
output[7:0] VAR56,
output[7:0] VAR42,
output VAR37 VAR3,
output [23:0] VAR5,
output VAR47,
output VAR43,
output[7:0] VAR2,
output VAR1,
outp... | mit |
tmolteno/TART | hardware/FPGA/ddrmem/iobs_clock.v | 2,448 | module MODULE1 (
VAR8,
VAR1,
VAR2,
VAR3,
VAR24,
VAR14
);
input VAR8;
input VAR1;
input VAR2;
output VAR3;
output VAR24;
output VAR14;
wire VAR12;
wire VAR16;
reg VAR3 = 0;
always @(posedge VAR8)
VAR3 <= VAR2;
VAR19 VAR22 (
.VAR23 (VAR12),
.VAR13 (VAR8),
.VAR7 (~VAR8),
.VAR21 (1'b1),
.VAR17 (0),
.VAR20 (1),
.VAR5 (!VAR1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2/sky130_fd_sc_ls__mux2_4.v | 2,187 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR4 ,
VAR3 ,
VAR1,
VAR10,
VAR9 ,
VAR6
);
output VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR3 ;
input VAR1;
input VAR10;
input VAR9 ;
input VAR6 ;
VAR2 VAR5 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbn/sky130_fd_sc_hs__sdfbbn.pp.symbol.v | 1,536 | module MODULE1 (
input VAR8 ,
output VAR6 ,
output VAR5 ,
input VAR9,
input VAR10 ,
input VAR3 ,
input VAR2 ,
input VAR1 ,
input VAR7 ,
input VAR4
);
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/four_port_ddr_ctrl.v | 10,120 | module MODULE1(
input VAR63,
input VAR23,
output reg VAR16,
output reg [255:0]VAR69,
output reg [31:0] VAR48,
output reg VAR35,
output reg [31:0] VAR43,
output reg [2:0] VAR18,
output reg VAR82,
input VAR11,
input VAR12,
input [255:0] VAR52,
input VAR70,
input VAR66,
input [255:0] VAR4,
input [31:0] VAR53,
input VAR55,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/diode/sky130_fd_sc_lp__diode.functional.v | 1,081 | module MODULE1 (
VAR1
);
input VAR1;
endmodule | apache-2.0 |
ElegantLin/My-CPU | Snake/Snake.srcs/sources_1/new/Game_Ctrl_Unit.v | 1,213 | module MODULE1
(
input clk,
input rst,
input VAR1,
input VAR6,
input VAR11,
input VAR4,
output reg [1:0]VAR13,
input VAR7,
input VAR2,
output reg VAR5,
output reg VAR10
);
localparam VAR14 = 2'b00;
localparam VAR9 = 2'b01;
localparam VAR12 = 2'b10;
localparam VAR3 = 2'b11;
reg[31:0]VAR8;
always@(posedge clk or negedge ... | gpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_fp_mul_ll_s5_double.v | 30,746 | module MODULE1
(
VAR10,
VAR18,
VAR11,
VAR62,
VAR56) ;
input VAR10;
input VAR18;
input [63:0] VAR11;
input [63:0] VAR62;
output [63:0] VAR56;
tri1 VAR10;
reg VAR48;
reg VAR65;
reg VAR67;
reg VAR12;
reg VAR38;
reg VAR53;
reg VAR8;
reg VAR17;
reg [12:0] VAR16;
reg [12:0] VAR5;
reg [12:0] VAR43;
reg VAR15;
reg VAR25;
reg [... | mit |
elegabriel/myzju | junior1/CA/LAB/lab5/code/alu.v | 2,096 | module MODULE1(VAR2,VAR4,VAR3,VAR1
);
input wire [31:0] VAR2,VAR4;
input wire [4:0] VAR3;
output reg [31:0] VAR1;
always @*
begin
case(VAR3)
5'd0: VAR1=VAR2+VAR4;
5'd1: VAR1=VAR2+VAR4;
5'd2: VAR1=VAR2-VAR4;
5'd3: VAR1=VAR2-VAR4;
5'd4: VAR1=VAR2&VAR4;
5'd5: VAR1=VAR2|VAR4;
5'd6: VAR1=VAR2^VAR4;
5'd7: VAR1=~(VAR2|VAR4);
... | gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/RD_DATA_FIFO.v | 13,455 | module MODULE1(
rst,
VAR114,
VAR308,
din,
VAR372,
VAR23,
dout,
VAR205,
VAR300,
VAR108
);
input rst;
input VAR114;
input VAR308;
input [255 : 0] din;
input VAR372;
input VAR23;
output [255 : 0] dout;
output VAR205;
output VAR300;
output VAR108;
VAR94 #(
.VAR239(0),
.VAR407(0),
.VAR124(0),
.VAR118(0),
.VAR30(0),
.VAR350(... | gpl-2.0 |
erdmannp/de2 | rtl/verilog/orpsoc_top.v | 20,223 | module MODULE1 #(
parameter VAR121 = 6,
parameter VAR415 = 3
)
(
input VAR395,
input VAR102,
output [17:0] VAR373,
output [8:0] VAR307,
input [17:0] VAR213,
input [3:0] VAR250,
inout [7:0] VAR435,
output VAR472,
input VAR453,
input VAR340,
input VAR331,
output [1:0] VAR216,
output [11:0] VAR276,
output VAR457,
output V... | gpl-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/NIOS_Sys_nios2_qsys_0_mult_cell.v | 6,492 | module MODULE1 (
VAR48,
VAR12,
clk,
VAR50,
VAR9
)
;
output [ 31: 0] VAR9;
input [ 31: 0] VAR48;
input [ 31: 0] VAR12;
input clk;
input VAR50;
wire [ 31: 0] VAR9;
wire [ 31: 0] VAR54;
wire [ 15: 0] VAR40;
wire VAR38;
assign VAR38 = ~VAR50;
VAR20 VAR47
(
.VAR29 (VAR38),
.VAR31 (clk),
.VAR25 (VAR48[15 : 0]),
.VAR7 (VAR12[... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2b/sky130_fd_sc_lp__nor2b_m.v | 2,170 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR1 ,
VAR3,
VAR7,
VAR6 ,
VAR8
);
output VAR5 ;
input VAR4 ;
input VAR1 ;
input VAR3;
input VAR7;
input VAR6 ;
input VAR8 ;
VAR2 VAR9 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR5 ,
VAR4 ,
VAR1
);
output VAR5... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/synth/zynq_design_1_system_ila_0.v | 87,800 | module MODULE1 (
clk,
VAR26,
VAR4,
VAR40,
VAR54,
VAR1,
VAR44,
VAR50,
VAR24,
VAR42,
VAR59,
VAR31,
VAR23,
VAR49,
VAR58,
VAR13,
VAR15,
VAR46,
VAR38,
VAR12,
VAR6,
VAR55,
VAR45,
VAR48,
VAR57,
VAR17,
VAR8,
VAR29,
VAR7,
VAR43,
VAR41,
VAR2,
VAR52,
VAR28,
VAR19,
VAR30,
VAR14,
VAR62,
VAR53,
VAR36,
VAR21,
VAR3,
VAR10,
VAR11,
VAR5... | mit |
skarpenko/ultiparc | rtl/src/cpu/uparc_long_imul.v | 3,071 | module MODULE1(
clk,
VAR3,
VAR4,
VAR9,
VAR2,
VAR8,
ready,
VAR6
);
input wire clk;
input wire VAR3;
input wire [VAR11-1:0] VAR4;
input wire [VAR11-1:0] VAR9;
input wire VAR2;
input wire VAR8;
output wire ready;
output wire [2*VAR11-1:0] VAR6;
reg [5:0] VAR5;
reg [2*VAR11-1:0] VAR1;
reg [VAR11-1:0] VAR7;
assign ready = !... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31o/sky130_fd_sc_hs__a31o_1.v | 2,210 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR1 ,
VAR8 ,
VAR6 ,
VAR9,
VAR7
);
output VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR9;
input VAR7;
VAR4 VAR2 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR5 ,
VAR3,
VAR1,
VAR8,
VAR6
);... | apache-2.0 |
ultraembedded/riscv | core/riscv/riscv_xilinx_2r1w.v | 5,808 | module MODULE2
(
input VAR18
,input VAR40
,input [ 4:0] VAR25
,input [ 31:0] VAR15
,input [ 4:0] VAR2
,input [ 4:0] VAR9
,output [ 31:0] VAR29
,output [ 31:0] VAR33
);
wire [31:0] VAR12;
wire [31:0] VAR20;
wire [31:0] VAR3;
wire [31:0] VAR32;
wire [31:0] VAR10;
wire [31:0] VAR16;
wire VAR5;
wire VAR39;
wire VAR27;
genv... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222o/sky130_fd_sc_ms__a222o.blackbox.v | 1,419 | module MODULE1 (
VAR3 ,
VAR7,
VAR5,
VAR2,
VAR9,
VAR10,
VAR8
);
output VAR3 ;
input VAR7;
input VAR5;
input VAR2;
input VAR9;
input VAR10;
input VAR8;
supply1 VAR11;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_alu.v | 14,079 | module MODULE1(
VAR3, VAR1, VAR5, VAR15,
VAR12, VAR26, VAR49,
VAR42, VAR46,
VAR20, VAR32, VAR14,
VAR31, VAR29,
VAR28, VAR16, VAR6, flag
);
parameter VAR47 = VAR13;
input [VAR47-1:0] VAR3;
input [VAR47-1:0] VAR1;
input [VAR47-1:0] VAR5;
input VAR15;
input [VAR7-1:0] VAR12;
input [VAR35-1:0] VAR26;
input [VAR9-1:0] VAR49... | mit |
defano/digital-design | seven-segment-counter/rtl/sevensegment.v | 3,317 | module MODULE1 (
clk,
reset,
VAR11,
VAR22
);
input clk; input reset; output [6:0] VAR11; output [3:0] VAR22;
reg [19:0] VAR27;
reg [3:0] VAR3;
reg [3:0] VAR8;
reg [3:0] VAR24;
reg [3:0] VAR15;
wire [6:0] VAR21;
wire [6:0] VAR6;
wire [6:0] VAR18;
wire [6:0] VAR5;
VAR7 VAR16 (
.clk(clk),
.reset(reset),
.VAR26(VAR21),
.VA... | mit |
asicguy/gplgpu | hdl/de/der_smdisp.v | 8,278 | module MODULE1
(
input VAR50,
input VAR10,
input VAR28,
input VAR33,
input VAR16,
input VAR51,
input VAR34,
input [3:0] VAR8,
input [3:0] VAR35,
input [3:0] VAR55,
input VAR49, input VAR30,
output reg VAR56,
output reg VAR21, output reg VAR18, output reg VAR44, output reg VAR23,
output reg VAR17,
output reg VAR6,
outpu... | gpl-3.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/synth/design_1_auto_pc_0.v | 13,144 | module MODULE1 (
VAR104,
VAR2,
VAR76,
VAR81,
VAR24,
VAR94,
VAR102,
VAR23,
VAR29,
VAR78,
VAR40,
VAR1,
VAR46,
VAR21,
VAR14,
VAR80,
VAR106,
VAR111,
VAR49,
VAR36,
VAR67,
VAR52,
VAR42,
VAR9,
VAR17,
VAR107,
VAR56,
VAR8,
VAR59,
VAR32,
VAR3,
VAR79,
VAR48,
VAR10,
VAR99,
VAR13,
VAR50,
VAR57,
VAR7,
VAR47,
VAR22,
VAR39,
VAR108,
VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.v | 2,471 | module MODULE1 (
VAR3 ,
VAR4,
VAR10,
VAR6 ,
VAR8 ,
VAR9,
VAR1,
VAR7 ,
VAR11
);
output VAR3 ;
input VAR4;
input VAR10;
input VAR6 ;
input VAR8 ;
input VAR9;
input VAR1;
input VAR7 ;
input VAR11 ;
VAR5 VAR2 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR11(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21boi/sky130_fd_sc_hd__a21boi.behavioral.pp.v | 2,172 | module MODULE1 (
VAR7 ,
VAR15 ,
VAR10 ,
VAR16,
VAR12,
VAR5,
VAR9 ,
VAR3
);
output VAR7 ;
input VAR15 ;
input VAR10 ;
input VAR16;
input VAR12;
input VAR5;
input VAR9 ;
input VAR3 ;
wire VAR1 ;
wire VAR6 ;
wire VAR18 ;
wire VAR13;
not VAR17 (VAR1 , VAR16 );
and VAR2 (VAR6 , VAR15, VAR10 );
nor VAR11 (VAR18 , VAR1, VAR6 ... | apache-2.0 |
chipsalliance/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/sram1024x18.v | 4,549 | module MODULE1 (
VAR19,
VAR25,
VAR15,
VAR5,
VAR24,
VAR12,
VAR13,
VAR2,
VAR21,
VAR8,
VAR20,
VAR17,
VAR14,
VAR4
);
input wire VAR19;
input wire VAR25;
input wire VAR15;
input wire [9:0] VAR5;
input wire [17:0] VAR24;
input wire [17:0] VAR12;
output reg [17:0] VAR13;
input wire VAR2;
input wire VAR21;
input wire VAR8;
inp... | apache-2.0 |
alexforencich/verilog-ethernet | rtl/eth_mac_10g_fifo.v | 14,656 | module MODULE1 #
(
parameter VAR120 = 64,
parameter VAR169 = (VAR120/8),
parameter VAR178 = VAR120,
parameter VAR40 = (VAR178>8),
parameter VAR37 = (VAR178/8),
parameter VAR152 = 1,
parameter VAR132 = 1,
parameter VAR1 = 64,
parameter VAR115 = 4096,
parameter VAR125 = 1,
parameter VAR47 = 1,
parameter VAR5 = VAR47,
par... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22o/sky130_fd_sc_ls__a22o.pp.blackbox.v | 1,385 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR7 ,
VAR5 ,
VAR6 ,
VAR8,
VAR9,
VAR1 ,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR7 ;
input VAR5 ;
input VAR6 ;
input VAR8;
input VAR9;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/controller/col_mach.v | 18,435 | module MODULE1 #
(
parameter VAR11 = 100,
parameter VAR35 = 3,
parameter VAR67 = "8",
parameter VAR58 = 12,
parameter VAR28 = 4,
parameter VAR130 = 8,
parameter VAR77 = 1,
parameter VAR85 = 0,
parameter VAR45 = 8,
parameter VAR105 = "VAR36",
parameter VAR55 = "VAR75",
parameter VAR62 = "VAR75",
parameter VAR70 = 31,
pa... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3/sky130_fd_sc_ls__and3.blackbox.v | 1,254 | module MODULE1 (
VAR1,
VAR2,
VAR5,
VAR8
);
output VAR1;
input VAR2;
input VAR5;
input VAR8;
supply1 VAR3;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
keith-epidev/VHDL-lib | top/lab_2/part_5/ip/dds/dds_stub.v | 1,188 | module MODULE1(VAR1, VAR2, VAR3)
;
input VAR1;
output VAR2;
output [15:0]VAR3;
endmodule | gpl-2.0 |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v | 28,421 | module MODULE1 (
VAR142,
VAR34,
VAR88,
VAR188,
VAR152,
VAR130,
VAR93,
VAR66,
VAR78,
VAR59,
VAR150,
VAR217,
VAR166,
VAR120,
VAR250,
VAR123,
VAR83,
VAR102,
VAR40,
VAR35,
VAR205,
VAR24,
VAR202,
VAR197,
VAR175,
VAR17,
VAR114,
VAR227,
VAR177,
VAR1,
VAR94,
VAR67,
VAR133,
VAR14,
VAR233,
VAR105,
VAR71,
VAR245,
VAR211,
VAR181,
... | apache-2.0 |
ad510/ee201l_cpu | Operate.v | 5,855 | module MODULE1
(clk, reset, VAR23, ack, VAR13, VAR5,
VAR41, VAR4, addr, VAR2, VAR35, VAR31);
localparam VAR24 = 32, VAR26 = 8, VAR28 = 8,
VAR25 = 8'h0, VAR11 = 8'h1, VAR21 = 8'h2, VAR1 = 8'h3,
VAR18 = 8'h4, VAR38 = 8'h5, VAR14 = 8'h6, VAR37 = 8'h7,
VAR15 = 8'h8, VAR9 = 8'h9, VAR40 = 8'hA, VAR6 = 8'hB,
VAR30 = 8'hC, VAR... | mit |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/rtr_crossbar_mac.v | 3,255 | module MODULE1
(VAR10, VAR4, VAR6);
parameter VAR8 = 5;
parameter VAR7 = 32;
parameter VAR3 = VAR9;
input [0:VAR8*VAR8-1] VAR10;
input [0:VAR8*VAR7-1] VAR4;
output [0:VAR8*VAR7-1] VAR6;
wire [0:VAR8*VAR7-1] VAR6;
wire [0:VAR8*VAR8-1] VAR15;
VAR1
.VAR11(VAR8))
VAR16
(.VAR2(VAR10),
.VAR12(VAR15));
VAR14
.VAR17(VAR8),
.VA... | gpl-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/synth/pr_region_default_mm_bridge_1.v | 4,529 | module MODULE1 #(
parameter VAR16 = 512,
parameter VAR9 = 8,
parameter VAR7 = 32,
parameter VAR24 = 5,
parameter VAR23 = 1,
parameter VAR25 = 1
) (
input wire clk, input wire VAR13, input wire [VAR16-1:0] VAR18, input wire VAR8, output wire [VAR24-1:0] VAR29, output wire [VAR16-1:0] VAR14, output wire [VAR7-1:0] VAR17,... | mit |
ShirmanXia/EE469SPRING16 | lab3/db/ip/nios_system/submodules/nios_system_regfile_r1sel.v | 2,340 | module MODULE1 (
address,
VAR3,
clk,
VAR2,
VAR6,
VAR4,
VAR7,
VAR1
)
;
output [ 5: 0] VAR7;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR3;
input clk;
input VAR2;
input VAR6;
input [ 31: 0] VAR4;
wire VAR5;
reg [ 5: 0] VAR9;
wire [ 5: 0] VAR7;
wire [ 5: 0] VAR8;
wire [ 31: 0] VAR1;
assign VAR5 = 1;
assign VAR8 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xnor2/sky130_fd_sc_hvl__xnor2.pp.symbol.v | 1,308 | module MODULE1 (
input VAR7 ,
input VAR2 ,
output VAR4 ,
input VAR3 ,
input VAR6,
input VAR5,
input VAR1
);
endmodule | apache-2.0 |
alexforencich/xfcp | rtl/wb_drp.v | 2,471 | module MODULE1 #
(
parameter VAR9 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR9-1:0] VAR1, input wire [15:0] VAR10, output wire [15:0] VAR4, input wire VAR5, input wire VAR13, output wire VAR6, input wire VAR12,
output wire [VAR9-1:0] VAR2,
output wire [15:0] VAR14,
input wire [15:0] VAR8,
output wire VAR3,... | mit |
olajep/oh | src/adi/hdl/library/axi_dmac/axi_dmac_reset_manager.v | 8,863 | module MODULE1 #(
parameter VAR23 = 1,
parameter VAR5 = 1,
parameter VAR2 = 1
) (
input clk,
input VAR40,
input VAR46,
input VAR32,
output VAR20,
output VAR36,
input VAR35,
input VAR22,
input VAR45,
output VAR13,
output VAR50,
input VAR25,
input VAR21,
input VAR8,
output VAR51,
output VAR1,
input VAR42,
output [11:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor3/sky130_fd_sc_lp__xor3.symbol.v | 1,309 | module MODULE1 (
input VAR5,
input VAR8,
input VAR4,
output VAR7
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/vcr_alloc_mac.v | 15,223 | module MODULE1
(clk, reset, VAR84, VAR44, VAR96,
VAR17, VAR34, VAR53, VAR67,
VAR55, VAR13, VAR90, VAR100,
VAR70, VAR52, VAR86, VAR39,
VAR4, VAR110, VAR82, VAR25, VAR33,
VAR92, VAR102, VAR99);
parameter VAR38 = 2;
parameter VAR41 = 2;
localparam VAR35 = VAR38 * VAR41;
parameter VAR83 = 1;
localparam VAR75 = VAR35 * VAR8... | gpl-2.0 |
yaqwsx/MandelbrotFPGA | MandelbrotFPGA.v | 1,614 | module MODULE1(VAR24, VAR8, VAR45, VAR9, VAR6,
VAR11, VAR28, VAR19, VAR47,
VAR23, VAR31, VAR15, VAR35, VAR44);
input VAR24; input VAR8;
input [3:0] VAR45; input [17:0] VAR9; output [8:0] VAR35; output [17:0] VAR44; output VAR6; output VAR11; output VAR28; output VAR19;output VAR47; output [9:0] VAR23; output [9:0] VAR3... | mit |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_misc_v6.v | 7,525 | module MODULE1 #
(
parameter VAR28 = 0 )
(
input wire VAR7 ,
input wire VAR1 ,
input wire VAR22 ,
input wire VAR23 ,
input wire [2:0] VAR20 ,
input wire VAR17 ,
output wire VAR13 ,
output wire VAR6 ,
output wire VAR18 ,
output wire VAR2 ,
output wire [2:0] VAR24 ,
output wire VAR9 ,
input wire VAR14 ,
input wire VAR19
... | lgpl-3.0 |
aap/pdp6 | verilog/tty.v | 6,771 | module MODULE2(
input wire clk,
input wire reset,
input wire VAR45,
input wire VAR29,
input wire VAR26,
input wire VAR42,
input wire VAR33,
input wire VAR18,
input wire VAR20,
input wire VAR25,
input wire VAR64, input wire [3:9] VAR16,
input wire [0:35] VAR24,
output wire [1:7] VAR54,
output wire [0:35] VAR39,
output w... | mit |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_encoder.v | 2,479 | module MODULE1
(VAR2, VAR3);
parameter VAR8 = 8;
localparam VAR4 = VAR6(VAR8);
input [0:VAR8-1] VAR2;
output [0:VAR4-1] VAR3;
wire [0:VAR4-1] VAR3;
generate
genvar VAR7;
for(VAR7 = 0; VAR7 < VAR4; VAR7 = VAR7 + 1)
begin:VAR5
wire [0:VAR8-1] VAR1;
genvar VAR10;
for(VAR10 = 0; VAR10 < VAR8; VAR10 = VAR10 + 1)
begin:VAR9
... | mit |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/ddr2/altera_avalon_half_rate_bridge.v | 12,818 | module MODULE1 (
VAR45,
VAR3,
VAR44,
VAR18,
VAR38,
VAR47,
VAR39,
VAR54,
VAR21,
VAR14,
VAR22,
VAR23,
VAR20,
VAR41,
VAR61,
VAR57,
VAR24,
VAR40,
VAR19,
VAR56,
VAR58,
VAR43
);
localparam VAR12 = 1;
parameter VAR36 = 32;
parameter VAR60 = 28;
parameter VAR31 = 4;
parameter VAR27 = 64;
parameter VAR33 = 25;
parameter VAR62 =... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.functional.pp.v | 2,158 | module MODULE1 (
VAR17 ,
VAR15 ,
VAR4 ,
VAR13 ,
VAR6 ,
VAR10,
VAR20 ,
VAR1 ,
VAR11 ,
VAR9
);
output VAR17 ;
input VAR15 ;
input VAR4 ;
input VAR13 ;
input VAR6 ;
input VAR10;
input VAR20 ;
input VAR1 ;
input VAR11 ;
input VAR9 ;
wire VAR14 ;
wire VAR12 ;
wire VAR18;
not VAR8 (VAR12 , VAR10 );
VAR5 VAR7 (VAR18, VAR4, VA... | apache-2.0 |
jotego/jt12 | hdl/jt12_eg_ctrl.v | 3,036 | module MODULE1(
input VAR16,
input VAR17,
input [2:0] VAR25,
input [9:0] VAR26,
input [4:0] VAR10, input [4:0] VAR20, input [4:0] VAR8, input [3:0] VAR12,
input [3:0] VAR13, input VAR23,
input [2:0] VAR15,
input VAR5,
output reg VAR6,
output reg [4:0] VAR11,
output reg [2:0] VAR14,
output reg VAR4
);
localparam VAR1 = ... | gpl-3.0 |
jhol/butterflylogic | rtl/Logic_Sniffer.v | 10,175 | module MODULE1 #(
parameter [31:0] VAR19=6,
parameter [31:0] VAR35=50,
parameter [1:0] VAR46=2'b00
parameter VAR50 = 100000000, parameter VAR133 = 28, parameter VAR65 = 115200 VAR81
)(
input wire VAR135,
input wire VAR28,
output wire VAR127,
input wire VAR31,
output wire VAR122,
inout wire [31:0] VAR97,
output wire VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor3/sky130_fd_sc_hd__xnor3_2.v | 2,184 | module MODULE2 (
VAR5 ,
VAR4 ,
VAR6 ,
VAR8 ,
VAR10,
VAR1,
VAR3 ,
VAR2
);
output VAR5 ;
input VAR4 ;
input VAR6 ;
input VAR8 ;
input VAR10;
input VAR1;
input VAR3 ;
input VAR2 ;
VAR9 VAR7 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.