repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_1.behavioral.pp.v | 2,576 | module MODULE1( VAR9, VAR8, VAR2, VAR1, VAR7, VAR6 );
input VAR8, VAR9, VAR2;
inout VAR7, VAR6;
output VAR1;
VAR3 VAR4(.VAR9(VAR9),.VAR8(VAR8),.VAR2(VAR2),.VAR1(VAR1),.VAR7(VAR7),.VAR6(VAR6));
VAR3 VAR5(.VAR9(VAR9),.VAR8(VAR8),.VAR2(VAR2),.VAR1(VAR1),.VAR7(VAR7),.VAR6(VAR6)); | apache-2.0 |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_wdata_mux.v | 6,771 | module MODULE1 #
(
parameter VAR47 = "none", parameter integer VAR4 = 1, parameter integer VAR36 = 1, parameter integer VAR39 = 1, parameter integer VAR21 = 0 )
(
input wire VAR1,
input wire VAR29,
input wire [VAR36*VAR4-1:0] VAR30,
input wire [VAR36-1:0] VAR35,
input wire [VAR36-1:0] VAR46,
output wire [VAR36-1:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2o/sky130_fd_sc_hs__a2bb2o.behavioral.v | 2,125 | module MODULE1 (
VAR1 ,
VAR14,
VAR9,
VAR17 ,
VAR4 ,
VAR16,
VAR11
);
output VAR1 ;
input VAR14;
input VAR9;
input VAR17 ;
input VAR4 ;
input VAR16;
input VAR11;
wire VAR4 VAR7 ;
wire VAR4 VAR2 ;
wire VAR6 ;
wire VAR15;
and VAR3 (VAR7 , VAR17, VAR4 );
nor VAR8 (VAR2 , VAR14, VAR9 );
or VAR5 (VAR6 , VAR2, VAR7 );
VAR12 VA... | apache-2.0 |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/niosII_system_curr_gear_out.v | 2,298 | module MODULE1 (
address,
VAR5,
clk,
VAR1,
VAR2,
VAR4,
VAR6,
VAR9
)
;
output [ 1: 0] VAR6;
output [ 31: 0] VAR9;
input [ 1: 0] address;
input VAR5;
input clk;
input VAR1;
input VAR2;
input [ 31: 0] VAR4;
wire VAR8;
reg [ 1: 0] VAR3;
wire [ 1: 0] VAR6;
wire [ 1: 0] VAR7;
wire [ 31: 0] VAR9;
assign VAR8 = 1;
assign VAR7 ... | apache-2.0 |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/db/dac_pll_altpll.v | 3,965 | module MODULE1
(
clk,
VAR15) ;
output [4:0] clk;
input [1:0] VAR15;
tri0 [1:0] VAR15;
wire [4:0] VAR3;
wire VAR10;
VAR23 VAR25
(
.VAR31(),
.clk(VAR3),
.VAR30(),
.VAR24(VAR10),
.VAR36(VAR10),
.VAR15(VAR15),
.VAR17(),
.VAR7(),
.VAR11(),
.VAR38(),
.VAR8(),
.VAR32()
,
.VAR4(1'b0),
.VAR27(1'b0),
.VAR35(1'b0),
.VAR13(1'b1),
... | gpl-3.0 |
fabianz66/cursos-tec | taller-digital/Lab4/lab_pong/mod_fsm_bola.v | 2,143 | module MODULE1(clk,VAR1, VAR14, VAR5, VAR11, VAR12, VAR9, VAR10);
input clk, VAR1;
input [4:0] VAR9;
output VAR14, VAR5;
output [10:0] VAR11;
output [9:0] VAR12, VAR10;
reg VAR6;
reg [2:0] state, VAR8, VAR7;;
parameter VAR3 = 0;
parameter VAR2 = 1;
parameter VAR4 = 2;
parameter VAR13 = 3;
begin
begin
begin
begin
begin
... | mit |
kielfriedt/ece472 | lab4/alu.v | 1,533 | module MODULE1(VAR6, VAR2, VAR3, VAR1, VAR5);
input [2:0] VAR6;
input [31:0] VAR2, VAR3;
output [31:0] VAR1;
output VAR5;
reg [31:0] VAR1;
reg VAR5;
always @(VAR2 or VAR3 or VAR6)
begin
case (VAR6)
3'b000 : VAR1 = VAR2 & VAR3; 3'b001 : VAR1 = VAR2 | VAR3; 3'b010 : VAR1 = VAR2 + VAR3; 3'b110 : VAR1 = VAR2 - VAR3; 3'b111... | gpl-3.0 |
jotego/jt51 | hdl/filter/jt51_fir_ram.v | 1,194 | module MODULE1
(
input [(VAR4-1):0] VAR5,
input [(VAR6-1):0] addr,
input VAR2, clk,
output [(VAR4-1):0] VAR1
);
reg [VAR4-1:0] VAR3[2**VAR6-1:0];
reg [VAR6-1:0] VAR7;
always @ (posedge clk) begin
if (VAR2)
VAR3[addr] <= VAR5;
VAR7 <= addr;
end
assign VAR1 = VAR3[VAR7];
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor2/sky130_fd_sc_ls__xnor2.behavioral.pp.v | 1,827 | module MODULE1 (
VAR10 ,
VAR3 ,
VAR2 ,
VAR6,
VAR4,
VAR13 ,
VAR1
);
output VAR10 ;
input VAR3 ;
input VAR2 ;
input VAR6;
input VAR4;
input VAR13 ;
input VAR1 ;
wire VAR9 ;
wire VAR8;
xnor VAR12 (VAR9 , VAR3, VAR2 );
VAR7 VAR11 (VAR8, VAR9, VAR6, VAR4);
buf VAR5 (VAR10 , VAR8 );
endmodule | apache-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir/qmfir_uart/qmfir_240MHz/ISE_project/QMFIR_uart_top.v | 7,380 | module MODULE1(
VAR79,
VAR22, clk, VAR62
);
output VAR79;
input VAR22;
input clk;
input VAR62;
wire VAR62;
wire [15:0] VAR2;
wire VAR10;
wire VAR56;
reg VAR34;
reg delay;
wire VAR83; wire [13:0] VAR45; wire [31:0] VAR61; wire VAR49; wire VAR28;
wire [23:0] VAR35;
reg [23:0] VAR15;
wire [15:0] VAR50;
wire [15:0] VAR78;
... | gpl-2.0 |
ehliar/schematic_gui | mux3.v | 1,079 | module MODULE1 #(parameter VAR2 = 1) (input wire [1:0] VAR4,
input wire [VAR2:0] VAR1, VAR5, VAR6,
output reg [VAR2:0] VAR3); | gpl-3.0 |
AngelTerrones/MUSB | Hardware/musb/musb_reg_file.v | 2,173 | module MODULE1(
input clk, input [4:0] VAR7, input [4:0] VAR1, input [4:0] VAR5, input [31:0] VAR2, input VAR3, output [31:0] VAR8, output [31:0] VAR4 );
reg [31:0] VAR6 [1:31];
always @(posedge clk) begin
if (VAR5 != 0)
VAR6[VAR5] <= (VAR3) ? VAR2 : VAR6[VAR5];
end
assign VAR8 = (VAR7 == 5'b0) ? 32'h00000000 : VAR6[VA... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xbar_1/zqynq_lab_1_design_xbar_1_stub.v | 5,769 | module MODULE1(VAR16, VAR14, VAR42, VAR74,
VAR5, VAR50, VAR70, VAR62, VAR11, VAR71,
VAR58, VAR8, VAR73, VAR63, VAR67, VAR32,
VAR20, VAR49, VAR65, VAR18, VAR21, VAR29, VAR36,
VAR72, VAR44, VAR56, VAR23, VAR61, VAR19,
VAR57, VAR4, VAR7, VAR55, VAR30, VAR33, VAR6,
VAR1, VAR34, VAR43, VAR53, VAR10, VAR39,
VAR25, VAR68, VAR... | mit |
P3Stor/P3Stor | pcie/IP core/pcie_data_send_fifo.v | 13,698 | module MODULE1(
rst,
VAR215,
VAR55,
din,
VAR268,
VAR92,
dout,
VAR409,
VAR176,
VAR350,
VAR377,
VAR17,
VAR2,
VAR201
);
input rst;
input VAR215;
input VAR55;
input [255 : 0] din;
input VAR268;
input VAR92;
output [127 : 0] dout;
output VAR409;
output VAR176;
output VAR350;
output VAR377;
output [10 : 0] VAR17;
output [9 :... | gpl-2.0 |
ffu/DSA-3.2.2 | usrp/fpga/sdr_lib/atr_delay.v | 2,004 | module MODULE1(VAR10,VAR2,VAR5,VAR11,VAR6,VAR3,VAR8);
input VAR10;
input VAR2;
input VAR5;
input VAR11;
input [11:0] VAR6;
input [11:0] VAR3;
output VAR8;
reg [3:0] state;
reg [11:0] VAR7;
always @(posedge VAR10)
if (VAR2 | ~VAR5)
begin
state <= VAR9;
VAR7 <= 12'b0;
end
else
case (state)
if (!VAR11)
begin
state <= VAR1... | gpl-3.0 |
spesialstyrker/boula | src/ocp_master_fsm.v | 26,052 | module MODULE1(
input wire [VAR81 - 1:0] address,
input wire enable,
input wire [2:0] VAR98,
input wire VAR29, input wire [VAR48 - 1:0] VAR90,
input wire VAR38,
input wire VAR19,
input wire reset,
input wire VAR39,
input wire [VAR100 - 1:0] VAR40,
input wire [VAR100 - 1:0] VAR25, input wire VAR96,
input wire VAR16, out... | gpl-2.0 |
anderson1008/NOCulator | hring/hw/buffered/src/vcr_vc_alloc_sep_of.v | 22,826 | module MODULE1
(clk, reset, VAR63, VAR69, VAR45, VAR19,
VAR25, VAR82, VAR32, VAR35, VAR46);
parameter VAR54 = 2;
parameter VAR4 = 2;
localparam VAR71 = VAR54 * VAR4;
parameter VAR76 = 1;
localparam VAR11 = VAR71 * VAR76;
parameter VAR28 = 5;
localparam VAR87 = VAR79(VAR28);
parameter VAR103 = VAR10;
parameter VAR12 = V... | mit |
hewittc/proxmark3lcd | fpga/fpga_lf.v | 4,611 | module MODULE1(
input VAR84, output VAR3, input VAR63, input VAR13,
input VAR12, input VAR18, input VAR70,
output VAR68, output VAR82,
output VAR71, output VAR75, output VAR16, output VAR15,
input [7:0] VAR17, output VAR21, output VAR79,
output VAR4, output VAR22, input VAR43, output VAR30,
input VAR52, input VAR14,
ou... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/conb/sky130_fd_sc_ls__conb.pp.blackbox.v | 1,255 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR6,
VAR3,
VAR4 ,
VAR5
);
output VAR2 ;
output VAR1 ;
input VAR6;
input VAR3;
input VAR4 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isolatch/sky130_fd_sc_lp__isolatch.blackbox.v | 1,305 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR3
);
output VAR2 ;
input VAR6 ;
input VAR3;
supply1 VAR4;
supply1 VAR8 ;
supply0 VAR1 ;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/RAMB16_S9_altera.v | 7,812 | module MODULE1 (
address,
VAR53,
VAR51,
VAR21,
VAR8,
VAR36);
input [10:0] address;
input VAR53;
input [7:0] VAR51;
input VAR21;
input VAR8;
output [7:0] VAR36;
tri1 VAR53;
tri1 VAR21;
parameter VAR40 = "";
wire [7:0] VAR55;
wire [7:0] VAR36 = VAR55[7:0];
VAR54 VAR35 (
.VAR24 (address),
.VAR49 (VAR53),
.VAR15 (VAR51),
.... | mit |
lvd2/zxevo | unsupported/flasher/fpga/main.v | 8,847 | module MODULE1(
input VAR90,
output VAR41,
input VAR134,
input VAR4,
input VAR145,
input VAR131,
input VAR103,
input VAR112,
input VAR136,
input VAR13,
input VAR48,
input VAR138,
output VAR83,
inout [7:0] VAR64,
output [15:0] VAR6,
output VAR100,
output VAR63,
output VAR2,
output VAR143,
output VAR28, output VAR18,
out... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai.pp.blackbox.v | 1,355 | module MODULE1 (
VAR5 ,
VAR7,
VAR3,
VAR1 ,
VAR2 ,
VAR4,
VAR6
);
output VAR5 ;
input VAR7;
input VAR3;
input VAR1 ;
input VAR2 ;
input VAR4;
input VAR6;
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdaptevaLib/src/ecfg/hdl/axi_ecfg.v | 9,017 | module MODULE1 (
VAR36, VAR75, VAR48, VAR17,
VAR18, VAR27, VAR62, VAR23,
VAR12, VAR39, VAR14,
VAR64, VAR10, VAR25,
VAR4, VAR55, VAR11,
VAR6, VAR63, VAR67, VAR35,
VAR37,
VAR43, VAR31, VAR5, VAR32,
VAR40, VAR46, VAR42, VAR47,
VAR7, VAR3, VAR66, VAR69,
VAR56, VAR8, VAR16, VAR33,
VAR72, VAR34, VAR44,
VAR26, VAR15, VAR58,
V... | lgpl-3.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/soc_system_hps_0_hps_io.v | 11,724 | module MODULE1 (
output wire [14:0] VAR46, output wire [2:0] VAR13, output wire VAR72, output wire VAR10, output wire VAR31, output wire VAR69, output wire VAR43, output wire VAR68, output wire VAR3, output wire VAR37, inout wire [31:0] VAR21, inout wire [3:0] VAR57, inout wire [3:0] VAR67, output wire VAR64, output wi... | epl-1.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dff_pr/sky130_fd_sc_hdll__udp_dff_pr.symbol.v | 1,325 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
codustry/cuckoo | FPGA - Verilog HDL/display.v | 2,405 | module MODULE1(
output [6:0] VAR54,
output [3:0] VAR44, VAR39,
output [7:0] VAR31,
output VAR57,VAR11,
input [7:0] VAR56, input VAR41, VAR53, VAR2, VAR33, VAR51, VAR9,
input [1:0] VAR21
);
parameter VAR47 = 1'b1;
wire VAR6,VAR3,VAR35;
wire [1:0] VAR29;
wire [3:0] VAR24,out;
wire VAR61, VAR32, VAR59, VAR40;
wire [3:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2/sky130_fd_sc_lp__nor2_4.v | 2,086 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR7 ,
VAR2,
VAR3,
VAR8 ,
VAR4
);
output VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR2;
input VAR3;
input VAR8 ;
input VAR4 ;
VAR6 VAR5 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR9,
VAR1,
VAR7
);
output VAR9;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp.functional.pp.v | 2,249 | module MODULE1 (
VAR19,
VAR16 ,
VAR8,
VAR6 ,
VAR3,
VAR10,
VAR1 ,
VAR13
);
output VAR19;
input VAR16 ;
input VAR8;
input VAR6 ;
input VAR3;
input VAR10;
input VAR1 ;
input VAR13 ;
wire VAR9 ;
wire VAR14 ;
wire VAR11 ;
wire VAR20;
wire VAR17 ;
not VAR4 (VAR14 , VAR9 );
not VAR12 (VAR11 , VAR6 );
nor VAR21 (VAR20, VAR8, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41oi/sky130_fd_sc_lp__a41oi_0.v | 2,439 | module MODULE1 (
VAR12 ,
VAR2 ,
VAR1 ,
VAR8 ,
VAR5 ,
VAR4 ,
VAR9,
VAR3,
VAR6 ,
VAR10
);
output VAR12 ;
input VAR2 ;
input VAR1 ;
input VAR8 ;
input VAR5 ;
input VAR4 ;
input VAR9;
input VAR3;
input VAR6 ;
input VAR10 ;
VAR7 VAR11 (
.VAR12(VAR12),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VA... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way/src/riffa/tx_port_monitor_64.v | 8,363 | module MODULE1 #(
parameter VAR8 = 9'd64,
parameter VAR18 = 512,
parameter VAR42 = (VAR18 - 4),
parameter VAR43 = VAR15((2**VAR15(VAR18))+1),
parameter VAR44 = 1
)
(
input VAR41,
input VAR36,
input [VAR8:0] VAR7, input VAR28, output VAR12,
output [VAR8-1:0] VAR29, output VAR2, input [VAR43-1:0] VAR39,
output VAR27, inp... | mit |
sh-chris110/chris | FPGA/chris.convolution.ok/Qsys/chris_slave.ok.v | 2,537 | module MODULE1 (
input wire [3:0] VAR8, input wire VAR9, output wire [31:0] VAR7, input wire VAR14, input wire [31:0] VAR10, output wire VAR2, input wire VAR5, input wire VAR12, output wire VAR1 );
reg [31:0] VAR4;
assign VAR7 = VAR4;
reg VAR3;
reg VAR11;
reg [31:0] VAR6;
reg VAR15;
reg [31:0] VAR13[8:0];
assign VAR2 =... | gpl-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/utils/generic_fifo.v | 2,245 | module MODULE1 (
clk,
reset,
write,
read,
VAR6,
VAR10,
VAR11,
VAR12,
VAR13
);
parameter VAR5 = 32;
parameter VAR8 = 8;
input wire clk, reset, write, read;
input wire [VAR5-1:0] VAR6;
output wire VAR10;
output reg VAR11;
output reg [VAR5-1:0] VAR12;
reg [VAR5:0] VAR14 [VAR8-1:0];
parameter VAR3 = VAR2(VAR8);
reg [VAR3-1... | bsd-3-clause |
mlarouche/sd2snes | verilog/sd2snes_obc1/cheat.v | 6,568 | module MODULE1(
input clk,
input [23:0] VAR18,
input [7:0] VAR17,
input VAR26,
input VAR19,
input VAR8,
input [2:0] VAR35,
input VAR24,
input [31:0] VAR13,
output [7:0] VAR11,
output VAR36,
output VAR21
);
reg VAR1 = 0;
reg VAR29 = 0;
reg VAR37 = 0;
reg VAR5 = 0;
reg VAR12 = 1;
reg VAR4 = 0;
reg VAR20 = 0;
reg VAR16 = ... | gpl-2.0 |
trander1/Queues-and-Adders | Verilog Files/lifo_top.v | 4,887 | (VAR6<=4)?2:\
(VAR6<=8)?3:\
(VAR6<=16)?4:\
(VAR6<=32)?5:\
(VAR6<=64)?6:\
(VAR6<=128)?7:\
(VAR6<=256)?8:\
-1
module MODULE1(
VAR2, VAR18, VAR22,
VAR4, reset,
clk
);
parameter VAR12 = 4;
parameter VAR3 = 8;
parameter VAR9 = 2;
parameter VAR23 = VAR12+VAR9; parameter VAR19 = 'b0;
parameter VAR24 = VAR1(VAR3);
output reg [... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21bai/sky130_fd_sc_hs__o21bai.functional.pp.v | 2,065 | module MODULE1 (
VAR1,
VAR16,
VAR2 ,
VAR13 ,
VAR8 ,
VAR7
);
input VAR1;
input VAR16;
output VAR2 ;
input VAR13 ;
input VAR8 ;
input VAR7;
wire VAR4 ;
wire VAR12 ;
wire VAR3 ;
wire VAR15;
not VAR11 (VAR4 , VAR7 );
or VAR5 (VAR12 , VAR8, VAR13 );
nand VAR10 (VAR3 , VAR4, VAR12 );
VAR6 VAR14 (VAR15, VAR3, VAR1, VAR16);
bu... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v | 15,778 | module MODULE1
(output VAR66,
input VAR29,
input VAR63,
input VAR4,
inout VAR82,
input VAR220,
input VAR99,
output VAR52,
output VAR211,
input wire [11:0] VAR25,
input wire [11:0] VAR40,
input wire [11:0] VAR93,
input wire [11:0] VAR44,
output wire [13:0] VAR87,
output wire [13:0] VAR120,
output wire VAR218,
output wir... | gpl-2.0 |
theapi/de0-nano | keyboard/ps2controller.v | 1,402 | module MODULE1 (
input reset,
input VAR3,
input VAR5,
output VAR1,
output [7:0] VAR4
);
reg [7:0] VAR2;
reg [3:0] counter;
reg ready;
assign VAR4 = VAR2;
assign VAR1 = ready;
always @(negedge VAR3 or posedge reset) begin
if (reset) begin
VAR2 = 8'b0;
counter = 4'd0;
end else begin
if (counter == 4'd0) begin
ready = 1'b... | mit |
davidkoltak/tawas-core | ip/rcn/rtl/rcn_master_slave.v | 2,352 | module MODULE1
(
input rst,
input clk,
input [68:0] VAR17,
output [68:0] VAR15,
input VAR5,
input [1:0] VAR7,
output VAR13,
input wr,
input [3:0] VAR1,
input [23:0] addr,
input [31:0] VAR31,
output VAR10,
output VAR27,
output [1:0] VAR19,
output [3:0] VAR21,
output [23:0] VAR18,
output [31:0] VAR9,
output VAR32,
output... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_2.functional.v | 1,360 | module MODULE1( VAR8, VAR9, VAR6, VAR13 );
input VAR13, VAR6, VAR8;
output VAR9;
wire VAR15;
not VAR11( VAR15, VAR13 );
wire VAR7;
not VAR2( VAR7, VAR8 );
wire VAR10;
and VAR5( VAR10, VAR15, VAR7 );
wire VAR1;
not VAR12( VAR1, VAR6 );
wire VAR14;
and VAR4( VAR14, VAR1, VAR7 );
or VAR3( VAR9, VAR10, VAR14 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211o/sky130_fd_sc_ms__a211o_1.v | 2,348 | module MODULE2 (
VAR2 ,
VAR6 ,
VAR4 ,
VAR3 ,
VAR7 ,
VAR11,
VAR9,
VAR1 ,
VAR5
);
output VAR2 ;
input VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR7 ;
input VAR11;
input VAR9;
input VAR1 ;
input VAR5 ;
VAR8 VAR10 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/bd_0/ip/ip_4/synth/bd_350b_slot_0_b_0.v | 4,558 | module MODULE1 (
VAR64,
VAR36,
dout
);
input wire [0 : 0] VAR64;
input wire [0 : 0] VAR36;
output wire [1 : 0] dout;
VAR2 #(
.VAR5(1),
.VAR23(1),
.VAR57(1),
.VAR6(1),
.VAR16(1),
.VAR55(1),
.VAR61(1),
.VAR46(1),
.VAR54(1),
.VAR40(1),
.VAR8(1),
.VAR66(1),
.VAR10(1),
.VAR31(1),
.VAR38(1),
.VAR45(1),
.VAR65(1),
.VAR69(1),
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31ai/sky130_fd_sc_hs__o31ai.behavioral.v | 1,921 | module MODULE1 (
VAR6 ,
VAR15 ,
VAR1 ,
VAR11 ,
VAR10 ,
VAR9,
VAR2
);
output VAR6 ;
input VAR15 ;
input VAR1 ;
input VAR11 ;
input VAR10 ;
input VAR9;
input VAR2;
wire VAR10 VAR13 ;
wire VAR12 ;
wire VAR8;
or VAR4 (VAR13 , VAR1, VAR15, VAR11 );
nand VAR14 (VAR12 , VAR10, VAR13 );
VAR7 VAR5 (VAR8, VAR12, VAR9, VAR2);
buf... | apache-2.0 |
zKarp/Karpentium-Processor | src/verilog/program_memory.v | 1,239 | module MODULE1 #(parameter VAR2=1, parameter VAR6=1)(clk,address,VAR7,enable);
parameter VAR3 = (2**VAR2); parameter VAR4 = (5*2*20); integer VAR5;
input clk, enable;
input [VAR2-1:0]address; output reg [VAR3-1:0]VAR7; reg ready;
reg [VAR6-1:0]VAR1 [VAR3-1:0];
begin | gpl-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_prbs_gen.v | 7,727 | module MODULE1 #
(
parameter VAR14 = 100, parameter VAR10 = 64 )
(
input VAR5, input VAR9, input VAR6, input [VAR10-1:0] VAR12, input VAR13, input VAR17, output [VAR10-1:0] VAR16 );
function integer VAR18 (input integer VAR2);
begin
VAR2 = VAR2 - 1;
for (VAR18=1; VAR2>1; VAR18=VAR18+1)
VAR2 = VAR2 >> 1;
end
endfunction... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111oi/sky130_fd_sc_hs__a2111oi_4.v | 2,334 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR10 ,
VAR4 ,
VAR9 ,
VAR2 ,
VAR6,
VAR5
);
output VAR1 ;
input VAR7 ;
input VAR10 ;
input VAR4 ;
input VAR9 ;
input VAR2 ;
input VAR6;
input VAR5;
VAR8 VAR3 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODUL... | apache-2.0 |
secworks/salsa20 | src/rtl/salsa20.v | 25,929 | module MODULE1(
input wire clk,
input wire VAR126,
input wire VAR22,
input wire VAR81,
input wire [7 : 0] address,
input wire [31 : 0] VAR129,
output wire [31 : 0] VAR88,
output wire VAR31
);
parameter VAR56 = 8'h00;
parameter VAR10 = 0;
parameter VAR87 = 1;
parameter VAR114 = 8'h01;
parameter VAR154 = 0;
parameter VAR... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_4.behavioral.pp.v | 1,069 | module MODULE1( VAR1, VAR2 );
inout VAR1, VAR2;
VAR4 VAR3(.VAR1(VAR1),.VAR2(VAR2));
VAR4 VAR5(.VAR1(VAR1),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor2/sky130_fd_sc_ms__xnor2.behavioral.v | 1,401 | module MODULE1 (
VAR3,
VAR9,
VAR1
);
output VAR3;
input VAR9;
input VAR1;
supply1 VAR4;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR6 ;
wire VAR7;
xnor VAR5 (VAR7, VAR9, VAR1 );
buf VAR10 (VAR3 , VAR7 );
endmodule | apache-2.0 |
cynngah/virtualsynthesizer | vga_controller.v | 7,625 | module MODULE1( VAR40, VAR17, VAR15, VAR16,
VAR34, VAR29, VAR13,
VAR6, VAR37, VAR27,
VAR14, VAR7);
parameter VAR35 = 1;
parameter VAR18 = "VAR24";
parameter VAR5 = "320x240";
parameter VAR22 = 10'd480;
parameter VAR30 = 10'd493;
parameter VAR23 = 10'd494; parameter VAR28 = 10'd525;
parameter VAR12 = 10'd640;
parameter ... | mit |
balanx/laotzu | RTL/stream_asyn_fifo_write.v | 6,618 | module MODULE1 #(
parameter VAR20 = 6,
parameter [VAR20:0] VAR30 = 44,
parameter [VAR20:0] VAR4 = 0,
parameter [VAR20:0] VAR35 = 0,
parameter [VAR20:0] VAR1 = 7
) (
input wire VAR33 ,
input wire VAR21 ,
input wire [2:0] VAR2 , input wire [VAR20:0] VAR39 ,
output reg [VAR20-1:0] VAR17 ,
output [VAR20:0] VAR10 ,
output V... | apache-2.0 |
azonenberg/yosys | passes/techmap/tff_untechmap.v | 5,080 | module MODULE16 (VAR39, VAR13);
input VAR39;
output wire VAR13;
wire VAR27;
VAR17 VAR31 (
.VAR33(VAR13),
.VAR18(VAR27),
);
VAR22 VAR1 (
.VAR39(VAR39),
.VAR6(VAR27),
.VAR13(VAR13),
);
endmodule
module MODULE20 (VAR39, VAR13);
input VAR39;
output wire VAR13;
wire VAR27;
VAR17 VAR31 (
.VAR33(VAR13),
.VAR18(VAR27),
);
VAR3... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41a/sky130_fd_sc_hs__o41a_4.v | 2,284 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR5 ,
VAR4 ,
VAR9 ,
VAR10 ,
VAR8,
VAR3
);
output VAR6 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR10 ;
input VAR8;
input VAR3;
VAR2 VAR7 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcin/sky130_fd_sc_lp__fahcin.behavioral.pp.v | 2,782 | module MODULE1 (
VAR23,
VAR26 ,
VAR7 ,
VAR16 ,
VAR10 ,
VAR3,
VAR18,
VAR25 ,
VAR27
);
output VAR23;
output VAR26 ;
input VAR7 ;
input VAR16 ;
input VAR10 ;
input VAR3;
input VAR18;
input VAR25 ;
input VAR27 ;
wire VAR4 ;
wire VAR20 ;
wire VAR13 ;
wire VAR12 ;
wire VAR24 ;
wire VAR6 ;
wire VAR2 ;
wire VAR28;
not VAR15 (V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4/sky130_fd_sc_hd__nor4.pp.symbol.v | 1,330 | module MODULE1 (
input VAR5 ,
input VAR1 ,
input VAR7 ,
input VAR4 ,
output VAR2 ,
input VAR6 ,
input VAR3,
input VAR8,
input VAR9
);
endmodule | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_fpu_post_norm_mul.v | 15,704 | module MODULE1(
VAR25,
VAR52,
VAR17,
VAR10,
VAR50,
VAR35,
VAR47,
VAR16,
VAR19
);
parameter VAR8 = 32;
parameter VAR34 = 0; parameter VAR33 = 11; parameter VAR45 = 23;
parameter VAR30 = 8;
parameter VAR28 = 31'd0;
parameter VAR32 = 31'b1111111100000000000000000000000;
parameter VAR18 = 31'b111111111000000000000000000000... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/cnet_reg_iface.v | 15,798 | module MODULE1 (
input [VAR43-1:0] VAR46, input [VAR41-1:0] VAR45, input VAR76, input VAR31,
output VAR26, output VAR37,
output reg [VAR43-1:0] VAR20, output reg VAR59,
input VAR82, input VAR53,
input [31:0] VAR54, output VAR27,
output reg VAR7, output reg VAR49, output reg [VAR41-1:0] VAR98, output reg [VAR43-1:0] VAR... | mit |
marcuseng/synchronousRead | Image_viewer_top.v | 6,134 | module MODULE1(VAR78,
VAR44, VAR58, VAR25, VAR53, VAR59,
VAR7, VAR11, VAR50, VAR32, VAR24, VAR63, VAR77, VAR30,
VAR1, VAR54,
VAR15, VAR47, VAR56, VAR57, VAR73, VAR69, VAR72, VAR65, VAR18, VAR29, VAR27, VAR34, VAR8,
VAR13, VAR66, VAR4, VAR23, VAR49
);
input VAR78;
output VAR7, VAR11, VAR50, VAR32, VAR24, VAR63, VAR77, V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3b/sky130_fd_sc_ls__or3b.behavioral.v | 1,467 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR7 ,
VAR3
);
output VAR1 ;
input VAR11 ;
input VAR7 ;
input VAR3;
supply1 VAR4;
supply0 VAR10;
supply1 VAR9 ;
supply0 VAR13 ;
wire VAR8 ;
wire VAR6;
not VAR12 (VAR8 , VAR3 );
or VAR5 (VAR6, VAR7, VAR11, VAR8 );
buf VAR2 (VAR1 , VAR6 );
endmodule | apache-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/mig_wrap_mig_7series_0_0_mig.v | 67,199 | module MODULE1 #
(
parameter VAR83 = 1,
parameter VAR355 = 3,
parameter VAR109 = 1,
parameter VAR22 = 10,
parameter VAR72 = 1,
parameter VAR339 = 1,
parameter VAR419 = 1,
parameter VAR367 = 4,
parameter VAR375 = 4,
parameter VAR49 = 8,
parameter VAR286 = 2,
parameter VAR185 = 16,
parameter VAR68 = 2,
parameter VAR87 = ... | mit |
TokiSeven/schoolMIPS | src/sm_cpu.v | 6,162 | module MODULE3
(
input clk, input VAR14, input [ 4:0] VAR5, output [31:0] VAR16, output [31:0] VAR37, input [31:0] VAR22, input [7:0] VAR30 );
wire VAR1;
wire VAR36;
wire VAR10;
wire VAR39;
wire VAR9;
wire [ 3:0] VAR17;
wire VAR4;
wire [31:0] VAR27;
wire [31:0] VAR41;
wire [31:0] VAR19 = VAR27 + 1;
wire [31:0] VAR7 = ~... | mit |
bigeagle/riffa | fpga/riffa_hdl/sg_list_reader_128.v | 4,700 | module MODULE1 #(
parameter VAR6 = 9'd128
)
(
input VAR20,
input VAR12,
input [VAR6-1:0] VAR11, input VAR16, output VAR15,
output VAR3, output VAR10, input VAR17, output [63:0] VAR8, output [31:0] VAR14 );
reg VAR5=VAR1, VAR5=VAR1;
reg VAR2=VAR13, VAR2=VAR13;
reg [VAR6-1:0] VAR7={VAR6{1'd0}}, VAR7={VAR6{1'd0}};
reg [63... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr.behavioral.pp.v | 1,882 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR12,
VAR11 ,
VAR5 ,
VAR3 ,
VAR2
);
output VAR1 ;
input VAR8 ;
input VAR12;
input VAR11 ;
input VAR5 ;
input VAR3 ;
input VAR2 ;
wire VAR7 ;
wire VAR6;
buf VAR4 (VAR7 , VAR8 );
VAR9 VAR10 (VAR6, VAR7, VAR12, VAR5);
buf VAR13 (VAR1 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/inv/sky130_fd_sc_hd__inv_8.v | 1,995 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR1,
VAR4,
VAR5 ,
VAR8
);
output VAR3 ;
input VAR6 ;
input VAR1;
input VAR4;
input VAR5 ;
input VAR8 ;
VAR2 VAR7 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR3,
VAR6
);
output VAR3;
input VAR6;
supply1 VAR1;
supply0 VAR4;... | apache-2.0 |
valptek/v586 | board_specific_files/nexys4/TOP_SYS_arty.v | 9,440 | module MODULE1(
VAR209,
VAR153,VAR87,VAR157,VAR55,
VAR101,VAR100,VAR181,VAR30,VAR201,VAR202,VAR26,
VAR191,VAR84,VAR193,VAR60,
VAR97,VAR16,VAR35,VAR235,VAR230,
VAR9,VAR94
);
input VAR209;
input VAR87;
output VAR153;
input [6:0] VAR157;
output VAR84,VAR60;
output VAR193,VAR30,VAR201,VAR181,VAR202,VAR191;
input VAR55;
out... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22oi/sky130_fd_sc_ms__a22oi.behavioral.v | 1,641 | module MODULE1 (
VAR15 ,
VAR10,
VAR2,
VAR9,
VAR3
);
output VAR15 ;
input VAR10;
input VAR2;
input VAR9;
input VAR3;
supply1 VAR12;
supply0 VAR7;
supply1 VAR13 ;
supply0 VAR1 ;
wire VAR11 ;
wire VAR4 ;
wire VAR5;
nand VAR14 (VAR11 , VAR2, VAR10 );
nand VAR16 (VAR4 , VAR3, VAR9 );
and VAR8 (VAR5, VAR11, VAR4);
buf VAR6 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdlclkp/sky130_fd_sc_hs__sdlclkp.functional.v | 1,991 | module MODULE1 (
VAR2,
VAR12,
VAR13,
VAR6 ,
VAR19,
VAR9
);
input VAR2;
input VAR12;
output VAR13;
input VAR6 ;
input VAR19;
input VAR9 ;
wire VAR5 ;
wire VAR18 ;
wire VAR16 ;
wire VAR4 ;
wire VAR7 ;
wire VAR15 ;
wire VAR17;
wire VAR11 ;
not VAR1 (VAR18 , VAR5 );
not VAR10 (VAR16 , VAR9 );
nor VAR20 (VAR11, VAR19, VAR6 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbp/sky130_fd_sc_ms__sdfbbp.functional.v | 2,286 | module MODULE1 (
VAR3 ,
VAR14 ,
VAR13 ,
VAR11 ,
VAR16 ,
VAR17 ,
VAR7 ,
VAR8
);
output VAR3 ;
output VAR14 ;
input VAR13 ;
input VAR11 ;
input VAR16 ;
input VAR17 ;
input VAR7 ;
input VAR8;
wire VAR4 ;
wire VAR12 ;
wire VAR9 ;
wire VAR1;
not VAR2 (VAR4 , VAR8 );
not VAR20 (VAR12 , VAR7 );
VAR18 VAR5 (VAR1, VAR13, VAR11,... | apache-2.0 |
thinkoco/de1_soc_opencl | de10_standard_sharedonly_vga/iface/acl_iface_system/acl_iface_system_bb.v | 4,393 | module MODULE1 (
VAR19,
VAR38,
VAR8,
VAR4,
VAR32,
VAR25,
VAR15,
VAR14,
VAR43,
VAR68,
VAR3,
VAR37,
VAR33,
VAR58,
VAR18,
VAR1,
VAR55,
VAR45,
VAR64,
VAR27,
VAR35,
VAR26,
VAR29,
VAR57,
VAR46,
VAR7,
VAR50,
VAR67,
VAR24,
VAR16,
VAR48,
VAR28,
VAR30,
VAR39,
VAR51,
VAR12,
VAR6,
VAR11,
VAR21,
VAR41,
VAR63,
VAR10,
VAR47,
VAR66,
V... | apache-2.0 |
Jam-G/MIPS | PC.v | 7,811 | module MODULE2(
input clk,
input [1:0] VAR5,
input [31:0] VAR10,VAR4,VAR12,VAR9,
output reg [31:0] VAR14,
output [31:0] VAR16
);
wire [31:0] VAR13;
wire [31:0] VAR7;
VAR11 VAR15(VAR10,VAR4,VAR12,VAR9,VAR5,VAR13);
VAR1 VAR1(VAR13,clk,VAR7);
MODULE1 MODULE1(clk,VAR7,VAR16);
always @(VAR7)
VAR14=VAR7+32'h4;
endmodule
modu... | lgpl-3.0 |
Yarr/Yarr-fw | rtl/kintex7/rx-core/descrambler.v | 2,412 | module MODULE1 #
(
parameter VAR4 = 64
)
(
VAR9,
VAR5,
enable,
VAR2,
clk,
rst
);
input [0:(VAR4+1)] VAR9; input enable;
output [(VAR4-1):0] VAR5;
output [1:0] VAR2;
input clk;
input rst;
reg [57:0] MODULE1;
integer VAR6;
reg [((VAR4*2)-7):0] VAR8;
reg [0:(VAR4-1)] VAR10;
reg [(VAR4-1):0] VAR3;
reg VAR7;
wire [0:63] VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s.behavioral.pp.v | 1,868 | module MODULE1 (
VAR11 ,
VAR10 ,
VAR2,
VAR8,
VAR9 ,
VAR4
);
output VAR11 ;
input VAR10 ;
input VAR2;
input VAR8;
input VAR9 ;
input VAR4 ;
wire VAR12 ;
wire VAR5;
buf VAR6 (VAR12 , VAR10 );
VAR7 VAR3 (VAR5, VAR12, VAR2, VAR8);
buf VAR1 (VAR11 , VAR5 );
endmodule | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/NormaliseAdder.v | 5,201 | module MODULE1(
input VAR9,
input [31:0] VAR10,
input [27:0] VAR3,
input VAR4,
output reg VAR8,
output reg [31:0] VAR1,
output reg [27:0] VAR2
);
parameter VAR5 = 1'b0,
VAR6 = 1'b1;
wire [7:0] VAR7;
assign VAR7 = VAR10[30:23];
always @ (posedge VAR4)
begin
VAR8 <= VAR9;
if (VAR9 != VAR6) begin
VAR1[31] <= VAR10[31];
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1.behavioral.v | 1,440 | module MODULE1 (
VAR2,
VAR6
);
output VAR2;
input VAR6;
supply1 VAR8;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR5 ;
wire VAR1;
not VAR9 (VAR1, VAR6 );
buf VAR7 (VAR2 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0n/sky130_fd_sc_lp__iso0n.pp.symbol.v | 1,279 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR6,
input VAR1 ,
input VAR7 ,
input VAR2 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfstp/sky130_fd_sc_hd__sdfstp.behavioral.v | 2,775 | module MODULE1 (
VAR30 ,
VAR26 ,
VAR2 ,
VAR16 ,
VAR15 ,
VAR23
);
output VAR30 ;
input VAR26 ;
input VAR2 ;
input VAR16 ;
input VAR15 ;
input VAR23;
supply1 VAR18;
supply0 VAR29;
supply1 VAR31 ;
supply0 VAR24 ;
wire VAR5 ;
wire VAR10 ;
wire VAR4 ;
reg VAR22 ;
wire VAR17 ;
wire VAR1 ;
wire VAR19 ;
wire VAR11;
wire VAR12 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.v | 2,511 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR1 ,
VAR3 ,
VAR12 ,
VAR4,
VAR9 ,
VAR8 ,
VAR11 ,
VAR10
);
output VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR12 ;
input VAR4;
input VAR9 ;
input VAR8 ;
input VAR11 ;
input VAR10 ;
VAR2 VAR6 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR9... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/user_logic.v | 8,625 | module MODULE2 #(parameter VAR16 = 4, parameter VAR9 = 64) (input wire VAR24,
input wire VAR25,
input wire VAR14,
input wire VAR35,
input wire [VAR9-1:0] din,
output wire [VAR9-1:0] VAR17,
output wire VAR20,
output wire VAR30,
output reg [VAR16:0] VAR27);
reg [VAR16-1:0] head;
reg [VAR9-1:0] VAR12 [(1<<VAR16)-1:0];
ass... | mit |
SI-RISCV/e200_opensource | rtl/e203/core/e203_irq_sync.v | 3,376 | module MODULE1 #(
parameter VAR21 = 1
) (
input clk,
input VAR14,
input VAR4,
input VAR20,
input VAR2,
input VAR13,
output VAR9,
output VAR10,
output VAR5,
output VAR3
);
generate
if(VAR21 == 1) begin:VAR1
.VAR18(VAR8),
.VAR6(1)
) VAR11(
.VAR16 (VAR13),
.dout (VAR3),
.clk (clk ),
.VAR14 (VAR14)
);
VAR19 # (
.VAR18(VAR8... | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/bench/verilog/wb_slave_behavioral.v | 12,219 | module MODULE1
(
VAR38,
VAR20,
VAR16,
VAR36,
VAR46,
VAR2,
VAR30,
VAR42,
VAR33,
VAR34,
VAR24,
VAR8,
VAR32
);
input VAR38;
input VAR20;
output VAR16;
input VAR29 VAR36;
input VAR46;
output VAR31 VAR2;
input VAR31 VAR30;
output VAR42;
output VAR33;
input VAR10 VAR34;
input VAR24;
input VAR8;
input VAR32;
reg VAR31 VAR2;
r... | gpl-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/fp_mult_v1.v | 39,786 | module MODULE1
(
VAR20,
VAR40,
VAR89,
VAR18) ;
input VAR20;
input [63:0] VAR40;
input [63:0] VAR89;
output [63:0] VAR18;
reg VAR94;
reg VAR68;
reg VAR69;
reg VAR44;
reg VAR83;
reg VAR9;
reg VAR17;
reg VAR29;
reg [12:0] VAR42;
reg [12:0] VAR46;
reg [12:0] VAR52;
reg VAR65;
reg VAR37;
reg VAR39;
reg VAR87;
reg [52:0] VAR... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_1.behavioral.pp.v | 1,159 | module MODULE1( VAR5, VAR2, VAR6, VAR4 );
input VAR5;
inout VAR6, VAR4;
output VAR2;
VAR1 VAR3(.VAR5(VAR5),.VAR2(VAR2),.VAR6(VAR6),.VAR4(VAR4));
VAR1 VAR7(.VAR5(VAR5),.VAR2(VAR2),.VAR6(VAR6),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai.symbol.v | 1,380 | module MODULE1 (
input VAR6,
input VAR7,
input VAR10,
input VAR1,
input VAR5,
output VAR9
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
brysonli12/CS152A-Lab4-TicTacToe | Score/binary_to_bcd.v | 1,756 | module MODULE2(VAR18,VAR17,VAR20,VAR14);
input [7:0] VAR18;
output [3:0] VAR17, VAR20;
output [3:0] VAR14;
wire [3:0] VAR16,VAR4,VAR12,VAR11,VAR19,VAR21,VAR1;
wire [3:0] VAR2,VAR6,VAR10,VAR22,VAR3,VAR23,VAR13;
assign VAR2 = {1'b0,VAR18[7:5]};
assign VAR6 = {VAR16[2:0],VAR18[4]};
assign VAR10 = {VAR4[2:0],VAR18[3]};
ass... | mit |
keith-epidev/VHDL-lib | top/stereo_radio/ip/fir_bp_lr/fir_bp_lr_stub.v | 1,483 | module MODULE1(VAR6, VAR5, VAR2, VAR3, VAR4, VAR1)
;
input VAR6;
input VAR5;
output VAR2;
input [15:0]VAR3;
output VAR4;
output [39:0]VAR1;
endmodule | gpl-2.0 |
asicguy/gplgpu | hdl/altera_plls/sys_pll_rb_bb.v | 12,245 | module MODULE1 (
VAR3,
VAR5,
VAR1,
VAR4,
VAR2);
input VAR3;
input VAR5;
output VAR1;
output VAR4;
output VAR2;
tri0 VAR3;
endmodule | gpl-3.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_data.v | 9,167 | module MODULE1 #
(parameter VAR36 = 100,
parameter VAR17 = 4,
parameter VAR3 = 3,
parameter VAR8 = 64)
(
VAR18,
clk, rst, VAR20, VAR10, VAR30,
VAR13, VAR19, VAR11,
VAR25
);
localparam [7:0] VAR16 = 8'b00000000;
input clk;
input rst;
input VAR20;
input [2*VAR17*VAR8-1:0] VAR10;
input [2*VAR17*VAR8-1:0] VAR30;
input [VAR... | mit |
ashikpoojari/NIDS-Wu-Manber | Wu_Manber_sft_FSM.v | 3,916 | module MODULE1 #(parameter VAR2=5, VAR10=2,VAR18=4,VAR4=4)
( input clk,
input reset,
input VAR16,
output reg VAR15, output reg VAR9,
output VAR21, output VAR17, output reg VAR14,
output reg VAR7, output reg VAR5,
output reg VAR13);
localparam VAR1=3'h0, VAR20=3'h1, VAR11=3'h2, VAR6=3'h3, VAR12=3'h4, VAR3=3'h5;
reg [2:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211ai/sky130_fd_sc_ms__o211ai.functional.pp.v | 2,048 | module MODULE1 (
VAR10 ,
VAR4 ,
VAR17 ,
VAR13 ,
VAR5 ,
VAR2,
VAR14,
VAR3 ,
VAR6
);
output VAR10 ;
input VAR4 ;
input VAR17 ;
input VAR13 ;
input VAR5 ;
input VAR2;
input VAR14;
input VAR3 ;
input VAR6 ;
wire VAR9 ;
wire VAR1 ;
wire VAR16;
or VAR12 (VAR9 , VAR17, VAR4 );
nand VAR11 (VAR1 , VAR5, VAR9, VAR13 );
VAR7 VAR8... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxbp/sky130_fd_sc_hd__sedfxbp.behavioral.pp.v | 2,768 | module MODULE1 (
VAR13 ,
VAR18 ,
VAR9 ,
VAR5 ,
VAR25 ,
VAR24 ,
VAR8 ,
VAR12,
VAR31,
VAR11 ,
VAR7
);
output VAR13 ;
output VAR18 ;
input VAR9 ;
input VAR5 ;
input VAR25 ;
input VAR24 ;
input VAR8 ;
input VAR12;
input VAR31;
input VAR11 ;
input VAR7 ;
wire VAR17 ;
reg VAR29 ;
wire VAR3 ;
wire VAR10 ;
wire VAR16;
wire VAR... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/ecc_gen.v | 7,893 | module MODULE1
parameter VAR11 = 72,
parameter VAR12 = 8,
parameter VAR6 = 64
)
(
VAR17
);
function integer VAR18 (input integer VAR15);
integer VAR4;
if (VAR15 == 1) VAR18 = 1;
else begin
VAR18 = 1;
for (VAR4=2; VAR4<=VAR15; VAR4=VAR4+1)
VAR18 = VAR18 * VAR4;
end
endfunction
function integer VAR7 (input integer VAR19,... | mit |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii.v | 18,035 | module MODULE1 (
input wire clk, input wire reset, output wire [31:0] VAR47, input wire VAR46, input wire [31:0] VAR2, input wire VAR35, output wire VAR36, input wire [7:0] VAR24, input wire VAR10, input wire VAR20, output wire [31:0] VAR7, output wire VAR1, output wire [5:0] VAR9, output wire [1:0] VAR21, input wire V... | apache-2.0 |
kevintownsend/bi-directional_XOR_memory | bidirectional_xor_memory.v | 1,573 | module MODULE1(clk, wr, addr, VAR10, VAR9);
parameter VAR12 = 4;
parameter VAR8 = 512;
parameter VAR17 = 64;
parameter VAR18 = VAR2(VAR8 - 1);
input clk;
input [0:VAR12 - 1] wr;
input [VAR12 * VAR18 - 1:0] addr;
input [VAR12 * VAR17 - 1:0] VAR10;
output [VAR12 * VAR17 - 1:0] VAR9;
reg [0:VAR12 - 1] VAR13;
reg [VAR18 - ... | apache-2.0 |
juan199/Lab_Digitales | exp2/Module_ROM.v | 1,032 | module MODULE1
(
input wire[15:0] VAR8,
output reg [27:0] VAR13
);
always @ ( VAR8 )
begin
case (VAR8)
0: VAR13 = { VAR6 ,24'd4000 };
1: VAR13 = { VAR2 , VAR7,16'b0001 };
2: VAR13 = { VAR2 ,VAR16,16'h1 };
3: VAR13 = { VAR2, VAR12,16'd1 };
4: VAR13 = { VAR2, VAR9,16'd0 }; 5: VAR13 = { VAR14 ,8'b0,VAR7,8'b0 };
6: VAR13 =... | lgpl-3.0 |
trander1/Queues-and-Adders | Verilog Files/synthesis_fifo_top.v | 4,619 | (VAR26<=4)?2:\
(VAR26<=8)?3:\
(VAR26<=16)?4:\
(VAR26<=32)?5:\
(VAR26<=64)?6:\
(VAR26<=128)?7:\
(VAR26<=256)?8:\
-1
module MODULE1(
VAR25, VAR11, VAR6,
VAR24, reset,
clk
);
parameter VAR21 = 4;
parameter VAR10 = 4;
parameter VAR19 = 2;
parameter VAR22 = VAR21+VAR19; parameter VAR16 = 'b0;
parameter VAR14 = VAR15(VAR10);... | gpl-2.0 |
jcowgill/BfProcessor | stack.v | 2,454 | module MODULE1(VAR6, clk, VAR10, VAR5, VAR9);
parameter VAR4 = 8;
parameter VAR2 = 5;
output [VAR4 - 1:0] VAR6;
input clk;
input [VAR4 - 1:0] VAR10; input VAR5; input VAR9;
reg [VAR4 - 1:0] VAR7[0:(1 << VAR2) - 1];
reg [VAR2 - 1:0] VAR8;
reg [VAR4 - 1:0] VAR3;
assign VAR6 = VAR3;
integer VAR1;
begin
begin
begin
end
beg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/fill/sky130_fd_sc_hdll__fill_2.v | 1,856 | module MODULE2 (
VAR3,
VAR5,
VAR1 ,
VAR2
);
input VAR3;
input VAR5;
input VAR1 ;
input VAR2 ;
VAR4 VAR6 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 ();
supply1 VAR3;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR2 ;
VAR4 VAR6 ();
endmodule | apache-2.0 |
trander1/Dual-Core-Processor | FinalProjectV3/Modules/dualcore.v | 4,390 | (VAR32<=4)?2:\
(VAR32<=8)?3:\
(VAR32<=16)?4:\
(VAR32<=32)?5:\
(VAR32<=64)?6:\
(VAR32<=128)?7:\
(VAR32<=256)?8:\
-1
module MODULE1(
VAR47, VAR46, VAR17, VAR25, VAR12, VAR50, VAR7, VAR4,
VAR28, VAR10, VAR44, VAR15, reset, clk
);
parameter VAR35 = 4; parameter VAR21 = 8; parameter VAR8 = 16; parameter VAR9 = 2; parameter ... | gpl-2.0 |
elegabriel/myzju | junior1/CA/LAB/lab6/lab6_gxl_3120102146/code/ID_EX.v | 1,672 | module MODULE1(
clk,rst,VAR2,
VAR18, VAR5, VAR6, VAR7, VAR14, VAR4, VAR21, VAR15,VAR3,VAR12,
VAR19, VAR1, VAR9, VAR16, VAR17, VAR20, VAR13, VAR10,VAR8,VAR11
);
input clk,rst,VAR2;
input wire [31:0] VAR18,VAR5,VAR7,VAR3,VAR12;
input wire [4:0] VAR6,VAR14;
input wire VAR4,VAR21,VAR15;
output reg [31:0] VAR19,VAR1,VAR16,V... | gpl-2.0 |
calee0219/Course | DLAB/Lab03/01_RTL/IMPOR.v | 4,956 | module MODULE1(
output reg [2:0] out,
output reg VAR20,
output reg ready,
input [2:0] in,
input [2:0] VAR1,
input VAR7,
input clk,
input VAR10
);
reg VAR12;
reg [2:0] VAR17, VAR2, VAR9, VAR18, VAR15, VAR19, VAR13, VAR3, VAR24;
wire [2:0] VAR25, VAR22, VAR4, VAR23, VAR14, VAR8, VAR6, VAR11, VAR21;
reg [20:0] VAR5, VAR16... | mit |
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