repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/fill/sky130_fd_sc_hdll__fill.symbol.v | 1,194 | module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv.behavioral.pp.v | 1,748 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR11,
VAR10,
VAR3 ,
VAR1
);
output VAR8 ;
input VAR7 ;
input VAR11;
input VAR10;
input VAR3 ;
input VAR1 ;
wire VAR12 ;
wire VAR2;
not VAR4 (VAR12 , VAR7 );
VAR9 VAR5 (VAR2, VAR12, VAR11, VAR10);
buf VAR6 (VAR8 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor2/sky130_fd_sc_lp__xnor2_0.v | 2,132 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR6 ,
VAR1,
VAR3,
VAR7 ,
VAR5
);
output VAR4 ;
input VAR9 ;
input VAR6 ;
input VAR1;
input VAR3;
input VAR7 ;
input VAR5 ;
VAR8 VAR2 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR4,
VAR9,
VAR6
);
output VAR4;
... | apache-2.0 |
rkrajnc/minimig-mist | rtl/or1200/or1200_wbmux.v | 4,875 | module MODULE1(
clk, rst,
VAR13, VAR12,
VAR6, VAR4, VAR1, VAR5,
VAR2, VAR11, VAR7
);
parameter VAR10 = VAR8;
input clk;
input rst;
input VAR13;
input [VAR9-1:0] VAR12;
input [VAR10-1:0] VAR6;
input [VAR10-1:0] VAR4;
input [VAR10-1:0] VAR1;
input [VAR10-1:0] VAR5;
output [VAR10-1:0] VAR2;
output [VAR10-1:0] VAR11;
outpu... | gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_axis_data_fifo_3_0/synth/design_SWandHW_standalone_axis_data_fifo_3_0.v | 5,897 | module MODULE1 (
VAR28,
VAR14,
VAR25,
VAR22,
VAR6,
VAR45,
VAR33,
VAR16,
VAR41,
VAR12,
VAR37,
VAR15,
VAR43,
VAR11,
VAR13
);
input wire VAR28;
input wire VAR14;
input wire VAR25;
output wire VAR22;
input wire [31 : 0] VAR6;
input wire [3 : 0] VAR45;
input wire VAR33;
output wire VAR16;
input wire VAR41;
output wire [31 :... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_rptr_vddcom.v | 1,096 | module MODULE1(VAR1,VAR2);
input VAR1;
output VAR2;
endmodule | gpl-2.0 |
omicronns/studies-sys-rek | de1-soc-template/v/VGAController.v | 3,987 | module MODULE1(
input VAR12,
input VAR21,
input [7:0] VAR28,
input [7:0] VAR16,
input [7:0] VAR24,
output [7:0] VAR11,
output [7:0] VAR23,
output [7:0] VAR30,
output VAR8,
output VAR22,
output VAR14,
output VAR9
);
parameter VAR29 = 96;
parameter VAR20 = 48;
parameter VAR5 = 640;
parameter VAR25 = 16;
parameter VAR2 = ... | mit |
tdene/synth_opt_adders | src/pptrees/mappings/sky130_fd_sc_hd_map.v | 4,263 | module MODULE23
(
VAR10, VAR4
);
output VAR10;
input VAR4;
VAR25 MODULE23(.VAR10(VAR10), .VAR4(VAR4));
endmodule
module MODULE6
(
VAR10, VAR4
);
output VAR10;
input VAR4;
VAR20 MODULE6(.VAR19(VAR10), .VAR4(VAR4));
endmodule
module MODULE20
(
VAR10, VAR4, VAR15
);
output VAR10;
input VAR4, VAR15;
VAR35 MODULE20(.VAR10(V... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_mul_add_unsigned.v | 1,544 | module MODULE1 #(
parameter VAR5(VAR2)
,parameter VAR5(VAR10)
,parameter VAR16 = VAR2 + VAR10
,parameter VAR12 = VAR18( ((1 << VAR2) - 1) * ((1 << VAR10) - 1) +
((1 << VAR16)-1) + 1 )
,parameter VAR11 = 0
) (
input VAR1
,input [VAR2-1 : 0] VAR22
,input [VAR10-1 : 0] VAR14
,input [VAR16-1 : 0] VAR20
,output [VAR12-1 : 0... | bsd-3-clause |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_StackPointer_0_0/RAT_StackPointer_0_0_stub.v | 1,381 | module MODULE1(VAR2, VAR7, VAR4, VAR1, VAR6, VAR5, VAR3)
;
input [7:0]VAR2;
input VAR7;
input VAR4;
input VAR1;
input VAR6;
input VAR5;
output [7:0]VAR3;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3/sky130_fd_sc_hdll__and3_4.v | 2,180 | module MODULE2 (
VAR3 ,
VAR1 ,
VAR5 ,
VAR2 ,
VAR4,
VAR10,
VAR6 ,
VAR7
);
output VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR4;
input VAR10;
input VAR6 ;
input VAR7 ;
VAR8 VAR9 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4.v | 2,464 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR7,
VAR1 ,
VAR3 ,
VAR6
);
output VAR8 ;
input VAR5 ;
input VAR7;
input VAR1 ;
input VAR3 ;
input VAR6 ;
VAR4 VAR2 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR8,
VAR5
);
output VAR8;
input VAR5;
wire VAR7;
supply1 VAR1 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_nsr_pp_pg/sky130_fd_sc_hs__udp_dff_nsr_pp_pg.symbol.v | 1,583 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR1,
input VAR7 ,
input VAR3,
input VAR6 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311oi/sky130_fd_sc_hs__a311oi.pp.blackbox.v | 1,376 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR6 ,
VAR2 ,
VAR3 ,
VAR4 ,
VAR5,
VAR8
);
output VAR1 ;
input VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR4 ;
input VAR5;
input VAR8;
endmodule | apache-2.0 |
aabdelfattah/alhaitham-hardware | center_pos.v | 1,279 | module MODULE1(VAR8 , VAR12 ,reset , clk ,VAR14,VAR5,valid);
input [15:0] VAR8;
input [15:0] VAR12 ;
input reset;
input clk ;
input [15:0] valid ;
output [15:0] VAR14;
output [15:0] VAR5;
reg [15:0] VAR14;
reg [15:0] VAR5;
reg [31:0] VAR11;
reg [31:0] VAR9;
reg [31:0]VAR15 ;
reg [31 : 0 ] VAR7 ;
always @ (posedge clk)
... | gpl-3.0 |
toyoshim/tvcl | sample/LED_spartan-3-starterkit.v | 3,345 | module MODULE1(
VAR32,
VAR27,
VAR4,
VAR12,
VAR5,
VAR39,
VAR52,
VAR43,
VAR24,
VAR42,
VAR29,
VAR18,
VAR11,
VAR9,
VAR37,
VAR21,
VAR30,
VAR25,
VAR41,
VAR7,
VAR49,
VAR15,
VAR50,
VAR34,
VAR14,
VAR45,
VAR3,
VAR2,
VAR20,
VAR10,
VAR17,
VAR26,
VAR13,
VAR8,
VAR16,
VAR1,
VAR51,
VAR28,
VAR19);
input VAR32;
input VAR27;
output [17:0... | bsd-3-clause |
danidim13/labo-digitales | Experimento2/MultLUT.v | 1,953 | module MODULE3 # (parameter VAR21=8)
(
input wire [VAR21-1:0] VAR17,
input wire [1:0] VAR9,
output reg [VAR21+1:0] VAR18
);
wire [VAR21+1:0] VAR22, VAR3, VAR13, VAR8;
assign VAR3 = {2'b0, VAR17};
assign VAR22 = VAR3 ^ VAR3; assign VAR13 = {1'b0, VAR17, 1'b0};
assign VAR8 = VAR13 + VAR3;
always @ (VAR17, VAR9)
begin
cas... | gpl-3.0 |
fpgasystems/caribou | hw/src/nukv/nukv_feedback.v | 1,569 | module MODULE1 #(
parameter VAR14 = 128,
parameter VAR2 = 96
)
(
input wire clk,
input wire rst,
input wire [VAR14+VAR2-1:0] VAR12,
input wire VAR4,
output wire VAR10,
output wire [VAR14+VAR2-1:0] VAR9,
output wire VAR13,
input wire VAR3,
input wire [VAR14+VAR2-1:0] VAR8,
input wire VAR11,
output wire VAR7,
output wire... | gpl-3.0 |
uzlonewolf/proxmark3 | fpga/hi_iso14443a.v | 19,749 | module MODULE1(
VAR14,
VAR46, VAR35, VAR33, VAR19, VAR31, VAR26,
VAR21, VAR40,
VAR49, VAR22, VAR16, VAR10,
VAR34,
VAR57
);
input VAR14;
output VAR46, VAR35, VAR33, VAR19, VAR31, VAR26;
input [7:0] VAR21;
output VAR40;
input VAR16;
output VAR49, VAR22, VAR10;
output VAR34;
input [3:0] VAR57;
wire VAR40 = VAR14;
reg VAR4... | gpl-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_OA_SRAM_TT_210930.v | 242,336 | module MODULE1 (VAR1, VAR7, VAR13, VAR3, VAR8, VAR6);
output VAR1;
input VAR7, VAR13, VAR3, VAR8, VAR6;
wire VAR2, VAR9, VAR4;
wire VAR10, VAR11, VAR5;
wire VAR12;
not (VAR11, VAR6);
not (VAR10, VAR8);
not (VAR4, VAR3);
and (VAR5, VAR4, VAR10);
not (VAR9, VAR13);
not (VAR2, VAR7);
and (VAR12, VAR2, VAR9, VAR10);
or (VA... | bsd-3-clause |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_tpram_32x32.v | 11,508 | module MODULE1(
VAR122, VAR2, VAR63, VAR59, VAR132, VAR64, VAR94, VAR101,
VAR89, VAR75, VAR45, VAR1, VAR3, VAR67, VAR56, VAR72
);
parameter VAR11 = 5;
parameter VAR48 = 32;
input VAR122; input VAR2; input VAR63; input VAR59; input VAR132; input [VAR11-1:0] VAR64; input [VAR48-1:0] VAR94; output [VAR48-1:0] VAR101; inpu... | gpl-3.0 |
jotego/jt12 | hdl/dac/jt12_dac.v | 1,369 | module MODULE1 #(parameter VAR1=12)
(
input clk,
input rst,
input signed [VAR1-1:0] din,
output dout
);
localparam VAR3 = VAR1+1;
reg [VAR1-1:0] VAR2;
reg [VAR3-1:0] VAR5;
wire [VAR3-2:0] VAR4 = VAR5[VAR3-2:0];
assign dout = VAR5[VAR3-1];
always @(posedge clk)
if( rst ) begin
VAR5 <= {(VAR3){1'b0}};
VAR2 <= {VAR1{1'b0}... | gpl-3.0 |
wgml/sysrek | arithm/arithm.v | 1,203 | module MODULE1(
input clk,
input VAR13,
input [13:0] VAR11,
input [13:0] VAR3,
input [13:0] VAR1,
output [28:0] VAR20
);
wire signed [14:0] VAR17;
wire signed [13:0] VAR9;
wire signed [28:0] VAR16;
VAR14 VAR12 (
.VAR18(VAR11), .VAR2(VAR3), .clk(clk), .VAR13(VAR13), .VAR5(VAR17) );
delay # (
.VAR6(2),
.VAR10(14))
VAR15
... | gpl-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_fp_atan2_s5.v | 1,229 | module MODULE1 (
enable,
VAR4,
VAR1,
VAR2,
VAR8);
input enable;
input VAR4;
input [31:0] VAR1;
input [31:0] VAR2;
output [31:0] VAR8;
wire [31:0] VAR6;
wire [31:0] VAR8 = VAR6[31:0];
VAR5 VAR9 (
.en (enable),
.VAR3(1'b0),
.clk(VAR4),
.VAR11(VAR1),
.VAR7(VAR2),
.VAR10(VAR6));
endmodule | mit |
alexforencich/xfcp | lib/eth/lib/axis/rtl/sync_reset.v | 1,654 | module MODULE1 #
(
parameter VAR1 = 2
)
(
input wire clk,
input wire rst,
output wire out
);
reg [VAR1-1:0] VAR2 = {VAR1{1'b1}};
assign out = VAR2[VAR1-1];
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR2 <= {VAR1{1'b1}};
end else begin
VAR2 <= {VAR2[VAR1-2:0], 1'b0};
end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.v | 2,154 | module MODULE2 (
VAR6,
VAR3,
VAR8 ,
VAR9,
VAR5,
VAR4 ,
VAR1
);
output VAR6;
input VAR3;
input VAR8 ;
input VAR9;
input VAR5;
input VAR4 ;
input VAR1 ;
VAR2 VAR7 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR6,
VAR3,
VAR8
);
output VAR6;
inpu... | apache-2.0 |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/start_for_Resize_U0.v | 3,010 | module MODULE2 (
clk,
VAR17,
VAR25,
VAR18,
VAR19);
parameter VAR14 = 32'd1;
parameter VAR24 = 32'd2;
parameter VAR16 = 3'd3;
input clk;
input [VAR14-1:0] VAR17;
input VAR25;
input [VAR24-1:0] VAR18;
output [VAR14-1:0] VAR19;
reg[VAR14-1:0] VAR9 [0:VAR16-1];
integer VAR3;
always @ (posedge clk)
begin
if (VAR25)
begin
fo... | mit |
titorgalaxy/Titor | rtl/verilog/util/Debounce.v | 1,630 | module MODULE1(
VAR2,
VAR3,
reset,
clk
);
parameter VAR4 = 0;
output reg VAR2;
input VAR3;
input clk;
input reset;
reg [VAR8-1:0] VAR5;
reg VAR6;
reg VAR7;
wire VAR1;
assign VAR1 = VAR6 ^^ VAR7;
always @(posedge clk) begin
if(reset) VAR5 <= 0;
end
else if(!VAR1)
if(VAR5!=VAR4) VAR5 <= VAR5+1;
else VAR5 <= VAR5;
else VA... | gpl-3.0 |
NickShaffner/rhea | rhea/cores/usbext/fpgalink/comm_fpga_fx2_v2.v | 6,213 | module MODULE1 (
VAR19,
VAR35,
VAR34,
VAR25,
VAR12,
VAR20,
VAR33,
VAR1,
VAR18,
VAR27,
VAR17,
VAR32,
VAR14,
VAR31,
VAR9,
VAR8,
VAR22,
VAR30
);
input VAR19;
input VAR35;
output VAR34;
reg VAR34;
input [7:0] VAR25;
output [7:0] VAR12;
reg [7:0] VAR12;
output VAR20;
reg VAR20;
input VAR33;
input VAR1;
input VAR18;
input VA... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/clk_gen/clk_gen_clk_wiz.v | 6,434 | module MODULE1
( input VAR46,
output VAR68,
input reset
);
VAR47 VAR74
(.VAR23 (VAR30),
.VAR37 (VAR46));
wire [15:0] VAR44;
wire VAR56;
wire VAR28;
wire VAR78;
wire VAR35;
wire VAR57;
wire VAR39;
wire VAR41;
wire VAR9;
wire VAR15;
wire VAR14;
wire VAR80;
wire VAR70;
wire VAR19;
wire VAR45;
wire VAR32;
wire VAR62;
wire ... | gpl-3.0 |
lvd2/ngs | fpga/obsolete/fpgaD_release/zxbus/zxbus.v | 8,930 | module MODULE1(
VAR19, VAR5, VAR51,VAR29, VAR1,VAR20, VAR14,VAR15, VAR50, VAR11, VAR32, VAR2, VAR45, VAR53,
VAR42,
VAR17, VAR21,
VAR35, VAR55,
VAR27, VAR4,
VAR30, VAR18,
VAR31, VAR37,
VAR48,
VAR43,
VAR54
);
parameter VAR39 = 2;
localparam VAR25 = 8'hBB;
localparam VAR38 = VAR25;
localparam VAR7 = 8'hB3;
localparam VAR2... | gpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/vfabric_pla.v | 4,720 | module MODULE1(VAR53, VAR31,
VAR43, VAR16, VAR47, VAR51, VAR25, VAR18,
VAR24, VAR7, VAR12, VAR19, VAR10, VAR37,
VAR52, VAR29, VAR6, VAR34, VAR50);
parameter VAR4 = 1;
parameter VAR49 = 20;
parameter VAR15 = 64;
input VAR53, VAR31;
input [VAR4-1:0] VAR43;
input [VAR4-1:0] VAR51;
input [VAR4-1:0] VAR24;
input [VAR4-1:0] ... | mit |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/sasc_fifo4.v | 4,674 | module MODULE1(
dout, VAR3, VAR4,
clk, VAR7, VAR5, din, VAR1, VAR6
);
input clk, VAR7;
input VAR5;
input [7:0] din;
input VAR1;
output [7:0] dout;
input VAR6;
output VAR3, VAR4;
reg [7:0] VAR2[0:3];
reg [1:0] VAR11;
reg [1:0] VAR10;
wire [1:0] VAR8;
wire [1:0] VAR12;
wire VAR3, VAR4;
reg VAR9;
always @(posedge clk or n... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp.functional.pp.v | 2,469 | module MODULE1 (
VAR21 ,
VAR16 ,
VAR7 ,
VAR5 ,
VAR13 ,
VAR15 ,
VAR17,
VAR11,
VAR24 ,
VAR1
);
output VAR21 ;
output VAR16 ;
input VAR7 ;
input VAR5 ;
input VAR13 ;
input VAR15 ;
input VAR17;
input VAR11;
input VAR24 ;
input VAR1 ;
wire VAR4 ;
wire VAR19 ;
wire VAR20 ;
wire VAR14;
VAR12 VAR18 (VAR19 , VAR5, VAR13, VAR15 ... | apache-2.0 |
sam-falvo/remex | rtl/rx_DS_char.v | 2,723 | module MODULE1(
input VAR14,
input VAR3,
input [1:0] VAR8,
input VAR19,
output [7:0] VAR30,
output VAR6,
output VAR22,
output VAR4
);
reg VAR6, VAR25;
reg VAR22, VAR24;
reg VAR4;
always @(posedge VAR14) begin
if(VAR3) begin
VAR6 <= 0;
VAR22 <= 0;
end
else begin
VAR6 <= VAR25;
VAR22 <= VAR24;
end
end
reg [5:0] state;
re... | mpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_2.functional.v | 1,838 | module MODULE1( VAR20, VAR19, VAR12, VAR10, VAR13, VAR6, VAR2 );
input VAR2, VAR6, VAR13, VAR10, VAR19, VAR20;
output VAR12;
wire VAR1;
not VAR16( VAR1, VAR2 );
wire VAR9;
not VAR8( VAR9, VAR6 );
wire VAR4;
not VAR17( VAR4, VAR13 );
wire VAR22;
and VAR5( VAR22, VAR1, VAR9, VAR4 );
wire VAR3;
not VAR11( VAR3, VAR10 );
w... | apache-2.0 |
cagiurumescu/pmod_oled_s3e | src/oled_cls.v | 4,213 | module MODULE1 (
input clk,
input reset,
input VAR4,
output reg VAR2,
output VAR16,
output VAR17,
output VAR15,
output reg VAR20 );
localparam VAR9 = VAR14'h0;
localparam VAR8 = VAR14'h1;
localparam VAR23 = VAR14'h2;
localparam VAR19 = VAR14'h3;
localparam VAR5 = VAR14'h4;
localparam VAR6 = VAR14'h5;
localparam VAR10 =... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_2.behavioral.v | 1,502 | module MODULE1( VAR6, VAR4, VAR1, VAR7 );
input VAR4, VAR1;
output VAR6, VAR7;
VAR5 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7));
VAR5 VAR2(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ha/sky130_fd_sc_ls__ha.behavioral.pp.v | 2,194 | module MODULE1 (
VAR16,
VAR11 ,
VAR10 ,
VAR12 ,
VAR5,
VAR3,
VAR13 ,
VAR4
);
output VAR16;
output VAR11 ;
input VAR10 ;
input VAR12 ;
input VAR5;
input VAR3;
input VAR13 ;
input VAR4 ;
wire VAR14 ;
wire VAR19;
wire VAR9 ;
wire VAR7 ;
and VAR2 (VAR14 , VAR10, VAR12 );
VAR6 VAR18 (VAR19, VAR14, VAR5, VAR3);
buf VAR8 (VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtp/sky130_fd_sc_hd__dfrtp_4.v | 2,329 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR9 ,
VAR6,
VAR7 ,
VAR5 ,
VAR1 ,
VAR2
);
output VAR4 ;
input VAR8 ;
input VAR9 ;
input VAR6;
input VAR7 ;
input VAR5 ;
input VAR1 ;
input VAR2 ;
VAR3 VAR10 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1.pp.symbol.v | 1,322 | module MODULE1 (
input VAR4 ,
output VAR5 ,
input VAR6 ,
input VAR3,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
praveendath92/securePUF | source/ipcore_dependencies/tx_client_fifo_8.v | 43,716 | module MODULE1
(
VAR105,
VAR147,
VAR53,
VAR39,
VAR81,
VAR152,
VAR114,
VAR126,
VAR96,
VAR47,
VAR34,
VAR25,
VAR74,
VAR151,
VAR30,
VAR59,
VAR78
);
input VAR105;
input VAR147;
input VAR53;
output [7:0] VAR39;
output VAR81;
input VAR152;
input VAR114;
input VAR126;
output VAR96;
input VAR47;
input VAR34;
input [7:0] VAR25;
... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_4.behavioral.v | 1,336 | module MODULE1( VAR5, VAR7, VAR4, VAR8, VAR1 );
input VAR1, VAR8, VAR5, VAR4;
output VAR7;
VAR3 VAR2(.VAR5(VAR5),.VAR7(VAR7),.VAR4(VAR4),.VAR8(VAR8),.VAR1(VAR1));
VAR3 VAR6(.VAR5(VAR5),.VAR7(VAR7),.VAR4(VAR4),.VAR8(VAR8),.VAR1(VAR1)); | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/reorder_queue_output.v | 10,581 | module MODULE1 #(
parameter VAR32 = 9'd128,
parameter VAR30 = 4'd12,
parameter VAR35 = 5, parameter VAR50 = 8, parameter VAR33 = 5, parameter VAR43 = 10, parameter VAR28 = VAR32/32,
parameter VAR8 = VAR22(VAR28),
parameter VAR24 = VAR22(VAR28+1),
parameter VAR47 = 2**VAR35
)
(
input VAR17, input VAR6, output [VAR43-1:0... | gpl-3.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkPTW.v | 35,350 | module MODULE1(VAR109,
VAR110,
VAR151,
VAR73,
VAR12,
VAR190,
VAR125,
VAR91,
VAR147,
VAR68,
VAR143,
VAR77,
VAR100,
VAR35,
VAR189,
VAR130,
VAR159,
VAR113,
VAR131,
VAR83);
parameter [2 : 0] VAR45 = 3'b0;
input VAR109;
input VAR110;
input [127 : 0] VAR151;
input VAR73;
output VAR12;
input VAR190;
output [131 : 0] VAR125;
o... | apache-2.0 |
cpulabs/mist1032isa | src/core/execute/execute_flag_register.v | 1,538 | module MODULE1(
input wire VAR7,
input wire VAR13,
input wire VAR6,
input wire VAR19,
input wire VAR3,
input wire [4:0] VAR12,
input wire VAR9,
input wire VAR18,
input wire VAR4,
input wire VAR16,
input wire [4:0] VAR8,
input wire VAR2,
input wire [4:0] VAR14,
input wire VAR10,
input wire [4:0] VAR5,
input wire VAR1,
i... | bsd-2-clause |
asicguy/gplgpu | hdl/altera_project/hb_pll/hb_pll.v | 12,091 | module MODULE1 (
VAR24,
VAR40,
VAR55,
VAR60,
VAR18,
VAR14,
VAR64);
input VAR24;
input VAR40;
input VAR55;
output VAR60;
output VAR18;
output VAR14;
output VAR64;
wire [5:0] VAR6;
wire VAR15;
wire [0:0] VAR16 = 1'h0;
wire [2:2] VAR27 = VAR6[2:2];
wire [1:1] VAR52 = VAR6[1:1];
wire [0:0] VAR47 = VAR6[0:0];
wire VAR60 = V... | gpl-3.0 |
luccas641/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE115/SeletorClock.v | 2,932 | module MODULE1(
input wire VAR4,
input wire reset,
input wire VAR3,
input wire VAR16,
input wire VAR15,
input wire VAR19,
input wire VAR10,
input wire VAR8,
input wire VAR13,
input wire VAR11,
input wire VAR18,
input wire VAR7,
input wire VAR14,
input wire VAR2,
input wire VAR6,
input wire VAR1,
input wire VAR17,
input... | gpl-3.0 |
AmeerAbdelhadi/Dynamic-Frequency-Phase-Sweeping | rstgen.v | 3,795 | module MODULE1
reg [VAR7-1:0] VAR10;
wire VAR5;
VAR4 #( .VAR7(VAR7) ) VAR3 ( .VAR10(VAR10) , .VAR5 (VAR5 ) );
localparam VAR2 = {1'b1,{(VAR7-1){1'b0}}}; wire VAR9 = (VAR10 == VAR2) ;
always @(posedge clk or posedge VAR1)
if (VAR1 ) VAR10 <= {VAR7{1'b0}} ;
else if (VAR9) VAR10 <= VAR2 ;
else VAR10 <= {VAR10[VAR7-2:0],VA... | bsd-3-clause |
rfotino/consolite-hardware | src/consolite.v | 22,104 | module MODULE1
(
input clk,
output [7:0] VAR74,
output [7:0] VAR150,
output [2:0] VAR21,
output VAR75,
output VAR105,
output [7:0] VAR202,
input [5:0] VAR185,
input [7:0] VAR67,
inout [7:0] VAR156,
inout [7:0] VAR164,
inout [7:0] VAR23,
inout [7:0] VAR20,
output VAR125,
output VAR111,
output VAR81,
input VAR206,
input ... | mit |
sam-falvo/remex | example/rtl/BROM.v | 3,684 | module MODULE1(
input [7:1] VAR3,
input VAR1,
output VAR2,
output [15:0] VAR4
);
reg [15:0] VAR4;
assign VAR2 = VAR1;
always @(*) begin
case(VAR3)
7'd0: VAR4 = 16'h0113;
7'd1: VAR4 = 16'h0000;
7'd2: VAR4 = 16'h01B7;
7'd3: VAR4 = 16'h0010;
7'd4: VAR4 = 16'h0113;
7'd5: VAR4 = 16'h0011;
7'd6: VAR4 = 16'h5213;
7'd7: VAR4 =... | mpl-2.0 |
Sajid3/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/ftl_brams.v | 1,400 | module MODULE1 #(
parameter VAR4 = 32,
parameter VAR6 = 7
) (
input wire VAR3,
input wire VAR13,
input wire [VAR6-1:0] VAR7,
input wire [VAR4-1:0] VAR10,
output reg [VAR4-1:0] VAR5,
input wire VAR2,
input wire VAR11,
input wire [VAR6-1:0] VAR9,
input wire [VAR4-1:0] VAR1,
output reg [VAR4-1:0] VAR8
);
reg [VAR4-1:0] VA... | apache-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/MUL_FPU_FUNCIONAL_v1/MUL_FPU_FUNCIONAL_v1.srcs/sources_1/imports/Proyecto_De_Graduacion/FPU_FLM/RTL/Mult/Sgf_Multiplication.v | 10,589 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR10,
input wire [VAR17-1:0] VAR20,
input wire [VAR17-1:0] VAR3,
output wire [2*VAR17-1:0] VAR23
);
wire [VAR17/2+1:0] VAR28;
wire [VAR17/2+1:0] VAR18;
wire [2*(VAR17/2)-1:0] VAR7;
wire [2*(VAR17/2+1)-1:0] VAR12;
wire [2*(VAR17/2+2)-1:0] VAR8;
wire [2*(VAR17/... | gpl-3.0 |
praveendath92/DDR2_Interface_Xilinx_XUPV5 | source/ddr2_mem_if_top.v | 16,001 | module MODULE1 #
(
parameter VAR17 = 2,
parameter VAR114 = 1,
parameter VAR106 = 1,
parameter VAR115 = 10,
parameter VAR90 = 0,
parameter VAR24 = 1,
parameter VAR110 = 1,
parameter VAR92 = 1,
parameter VAR56 = 9,
parameter VAR67 = 72,
parameter VAR109 = 7,
parameter VAR93 = 8,
parameter VAR39 = 4,
parameter VAR45 = 9,
... | mit |
bigeagle/riffa | fpga/xilinx/vc707/VC707_Gen2x8If128/hdl/VC707Gen2x8If128.v | 20,944 | module MODULE1
parameter VAR13 = 8,
parameter VAR151 = 128,
parameter VAR90 = 256,
parameter VAR184 = 6
)
(output [(VAR13 - 1) : 0] VAR31,
output [(VAR13 - 1) : 0] VAR30,
input [(VAR13 - 1) : 0] VAR32,
input [(VAR13 - 1) : 0] VAR134,
output [3:0] VAR19,
input VAR11,
input VAR41,
input VAR5
);
wire VAR27;
wire VAR178;
w... | bsd-3-clause |
adamkaplan/linguist | samples/Verilog/vga.v | 8,347 | module MODULE1 (
input VAR91, input VAR62,
input [15:0] VAR63,
output [15:0] VAR76,
input [16:1] VAR45,
input VAR37,
input VAR9,
input [ 1:0] VAR22,
input VAR1,
input VAR32,
output VAR10,
output [ 3:0] VAR36,
output [ 3:0] VAR27,
output [ 3:0] VAR78,
output VAR16,
output VAR15,
output [17:1] VAR83,
output [ 1:0] VAR90,... | mit |
rurume/openrisc_vision_hardware | ISE/uart_sync_flops.v | 5,668 | module MODULE1
(
VAR9,
VAR5,
VAR10,
VAR4,
VAR3,
VAR1
);
parameter VAR2 = 1;
parameter VAR7 = 1;
parameter VAR6 = 1'b0;
input VAR9; input VAR5; input VAR10; input VAR4; input [VAR7-1:0] VAR3; output [VAR7-1:0] VAR1;
reg [VAR7-1:0] VAR1;
reg [VAR7-1:0] VAR8;
always @ (posedge VAR5 or posedge VAR9)
begin
if (VAR9)
VAR8 <=... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/megafunctions/syncfifo_512x32_bb.v | 5,607 | module MODULE1 (
VAR2,
VAR1,
VAR7,
VAR3,
VAR6,
VAR4,
VAR5,
VAR8);
input VAR2;
input [31:0] VAR1;
input VAR7;
input VAR3;
input VAR6;
output VAR4;
output VAR5;
output [31:0] VAR8;
endmodule | mit |
zhangly/azpr_cpu | rtl/cpu/rtl/spm.v | 2,412 | module MODULE1 (
input wire clk,
input wire [VAR4] VAR17, input wire VAR20, input wire VAR27, input wire [VAR2] VAR29, output wire [VAR2] VAR28,
input wire [VAR4] VAR12, input wire VAR22, input wire VAR16, input wire [VAR2] VAR6, output wire [VAR2] VAR14 );
reg VAR11; reg VAR5;
always @(*) begin
if ((VAR20 == VAR1) && ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_1.behavioral.v | 3,306 | module MODULE1( VAR3, VAR6, VAR9, VAR1, VAR5, VAR2 );
input VAR2, VAR5, VAR6, VAR3, VAR9;
output VAR1;
VAR4 VAR7(.VAR3(VAR3),.VAR6(VAR6),.VAR9(VAR9),.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2));
VAR4 VAR8(.VAR3(VAR3),.VAR6(VAR6),.VAR9(VAR9),.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_1.behavioral.v | 1,322 | module MODULE1( VAR5, VAR8, VAR1, VAR6, VAR7 );
input VAR5, VAR8, VAR1, VAR6;
output VAR7;
VAR4 VAR2(.VAR5(VAR5),.VAR8(VAR8),.VAR1(VAR1),.VAR6(VAR6),.VAR7(VAR7));
VAR4 VAR3(.VAR5(VAR5),.VAR8(VAR8),.VAR1(VAR1),.VAR6(VAR6),.VAR7(VAR7)); | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/usbf/usbf_crc16.v | 7,188 | module MODULE1(VAR2, din, VAR1);
input [15:0] VAR2;
input [7:0] din;
output [15:0] VAR1;
assign VAR1[0] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^
din[2] ^ din[1] ^ din[0] ^ VAR2[8] ^ VAR2[9] ^
VAR2[10] ^ VAR2[11] ^ VAR2[12] ^ VAR2[13] ^
VAR2[14] ^ VAR2[15];
assign VAR1[1] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ai/sky130_fd_sc_lp__o21ai_0.v | 2,261 | module MODULE2 (
VAR4 ,
VAR3 ,
VAR2 ,
VAR10 ,
VAR9,
VAR1,
VAR7 ,
VAR6
);
output VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR10 ;
input VAR9;
input VAR1;
input VAR7 ;
input VAR6 ;
VAR8 VAR5 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/conb/sky130_fd_sc_ls__conb.pp.symbol.v | 1,268 | module MODULE1 (
output VAR1 ,
output VAR3 ,
input VAR6 ,
input VAR2,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
brysonli12/CS152A-Lab4-TicTacToe | Game/Game.v | 3,846 | module MODULE1(
input wire clk, input wire VAR62, input wire [4:0] VAR47, input wire VAR18, input wire VAR44, output wire [2:0] VAR27, output wire [2:0] VAR63, output wire [1:0] VAR34, output wire VAR8, output wire VAR36, output wire [7:0] VAR54,
output wire [3:0] VAR53
);
wire VAR31;
wire VAR39;wire VAR6;wire VAR48;
r... | mit |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_pfd_block.v | 2,756 | module MODULE1
parameter VAR5 = 0
)
( input VAR6,
input VAR8,
input VAR11, input VAR9,
output [14-1:0] VAR7
);
reg VAR10; reg VAR4;
wire VAR3;
wire VAR1;
reg [14+VAR5-1:0] VAR2;
assign VAR3 = ( {VAR11,VAR10} == 2'b10 ) ? 1'b1 : 1'b0;
assign VAR1 = ( {VAR9,VAR4} == 2'b10 ) ? 1'b1 : 1'b0;
assign VAR7 = VAR2[14+VAR5-1:VAR... | mit |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/soc_system_dipsw_pio.v | 6,161 | module MODULE1 (
address,
VAR2,
clk,
VAR12,
VAR5,
VAR15,
VAR14,
irq,
VAR10
)
;
output irq;
output [ 31: 0] VAR10;
input [ 1: 0] address;
input VAR2;
input clk;
input [ 9: 0] VAR12;
input VAR5;
input VAR15;
input [ 31: 0] VAR14;
wire VAR13;
reg [ 9: 0] VAR7;
reg [ 9: 0] VAR4;
wire [ 9: 0] VAR3;
reg [ 9: 0] VAR11;
wire V... | epl-1.0 |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_read.v | 6,159 | module MODULE1 #
(
parameter integer VAR1 = 32,
parameter integer VAR10 = 32,
parameter integer VAR18 = 5,
parameter integer VAR16 = 3,
parameter VAR7 = 160'h0000f00C0000f0080000f0040000f000FFFFFFFF,
parameter VAR13 = 5'b11111
)
(
input wire clk ,
input wire reset ,
input wire [VAR1-1:0] VAR12 ,
output wire VAR17 ,
inp... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/translation_xilinx.v | 10,732 | module MODULE1
parameter VAR15 = 256
)
(
input VAR61,
input VAR71,
input [VAR15-1:0] VAR45,
input [(VAR15/8)-1:0] VAR5,
input VAR1,
input VAR27,
output VAR70,
input [VAR41-1:0] VAR66,
output VAR3,
output VAR4,
output [VAR15-1:0] VAR75,
output [(VAR15/8)-1:0] VAR76,
output VAR83,
output VAR81,
input VAR47,
output [VAR14... | gpl-3.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_video_clipper_0.v | 9,904 | module MODULE1 (
clk,
reset,
VAR10,
VAR31,
VAR23,
VAR2,
VAR11,
VAR1,
VAR17,
VAR45,
VAR38,
VAR37,
VAR9,
VAR33
);
parameter VAR40 = 29; parameter VAR5 = 1;
parameter VAR24 = 640; parameter VAR15 = 480; parameter VAR19 = 9; parameter VAR14 = 8;
parameter VAR22 = 192;
parameter VAR12 = 192;
parameter VAR7 = 120;
parameter ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3b/sky130_fd_sc_hs__or3b.symbol.v | 1,265 | module MODULE1 (
input VAR3 ,
input VAR2 ,
input VAR1,
output VAR5
);
supply1 VAR6;
supply0 VAR4;
endmodule | apache-2.0 |
MeshSr/onetswitch20 | ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/wildcard_tcam.v | 7,498 | module MODULE1
parameter VAR28 = 32,
parameter VAR14 = 32,
parameter VAR25 = 5,
parameter VAR16 = 0,
parameter VAR29 = 0
)(
input clk,
input reset,
input [VAR28 - 1 : 0] VAR5,
output VAR8,
output VAR21,
output reg [VAR25 - 1 : 0] VAR13,
input VAR12,
input VAR11,
input [VAR31 -1:0] VAR22,
output reg [VAR28-1:0]VAR9,
out... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probec_p/sky130_fd_sc_hvl__probec_p.blackbox.v | 1,252 | module MODULE1 (
VAR6,
VAR2
);
output VAR6;
input VAR2;
supply1 VAR1;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1n/sky130_fd_sc_lp__iso1n.behavioral.pp.v | 2,048 | module MODULE1 (
VAR13 ,
VAR7 ,
VAR3,
VAR1 ,
VAR8 ,
VAR14 ,
VAR9
);
output VAR13 ;
input VAR7 ;
input VAR3;
input VAR1 ;
input VAR8 ;
input VAR14 ;
input VAR9 ;
wire VAR2 ;
wire VAR10 ;
wire VAR6;
not VAR4 (VAR2 , VAR3 );
VAR12 VAR11 (VAR10 , VAR7, VAR1, VAR8 );
VAR12 VAR15 (VAR6, VAR2, VAR1, VAR8 );
or VAR5 (VAR13 , V... | apache-2.0 |
Jawanga/ece385final | usb_system/synthesis/submodules/usb_system_onchip_memory2_0.v | 3,104 | module MODULE1 (
address,
VAR31,
VAR17,
clk,
VAR3,
reset,
VAR1,
write,
VAR6,
VAR2
)
;
parameter VAR7 = "MODULE1.VAR26";
output [ 31: 0] VAR2;
input [ 12: 0] address;
input [ 3: 0] VAR31;
input VAR17;
input clk;
input VAR3;
input reset;
input VAR1;
input write;
input [ 31: 0] VAR6;
wire VAR18;
wire [ 31: 0] VAR2;
wire V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_2.behavioral.v | 2,148 | module MODULE1( VAR1, VAR3, VAR5 );
input VAR1, VAR3;
output VAR5;
reg VAR6;
VAR8 VAR11(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR6(VAR6));
VAR8 VAR2(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR6(VAR6));
not VAR7(VAR9,VAR3);
buf VAR10(VAR4,VAR3); | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/09J1EJEMPLO/hdl/j1soc.v | 2,727 | module MODULE1#(
parameter VAR2 = "../VAR16/VAR9/VAR7.VAR4" )(
VAR25, VAR19,
VAR5, VAR6
);
input VAR5, VAR6;
output VAR25;
output VAR19;
wire VAR17; wire VAR14; wire [15:0] VAR20; reg [15:0] VAR24; wire [15:0] VAR21;
reg [1:4]VAR12;
wire [15:0] VAR28;
wire [15:0] VAR10;
wire VAR11; wire [15:0] VAR27;
VAR7 #(VAR2) VAR18... | gpl-3.0 |
shangdawei/proxmark3-lcd | fpga/fpga.v | 7,996 | module MODULE1(
VAR2, VAR63, VAR111, VAR115,
VAR10, VAR42, VAR49,
VAR16, VAR78, VAR123, VAR51, VAR33, VAR102,
VAR112, VAR71, VAR44,
VAR26, VAR126, VAR48, VAR105,
VAR107, VAR8,
VAR45, VAR129,
VAR82
);
input VAR2, VAR111, VAR115;
output VAR63;
input VAR10, VAR42, VAR49;
output VAR16, VAR78, VAR123, VAR51, VAR33, VAR102;
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand3/sky130_fd_sc_hvl__nand3.symbol.v | 1,284 | module MODULE1 (
input VAR4,
input VAR6,
input VAR1,
output VAR5
);
supply1 VAR7;
supply0 VAR3;
supply1 VAR8 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/ecc_merge_enc.v | 5,628 | module MODULE1
parameter VAR2 = 100,
parameter VAR12 = 64,
parameter VAR21 = 72,
parameter VAR26 = 4,
parameter VAR25 = 1,
parameter VAR23 = 64,
parameter VAR22 = 72,
parameter VAR13 = 8
)
(
VAR1, VAR5,
clk, rst, VAR8, VAR18, VAR6, VAR16, VAR9
);
input clk;
input rst;
input [4*VAR12-1:0] VAR8;
input [4*VAR23/8-1:0] VAR... | mit |
borti4938/sd2snes | verilog/sd2snes_cx4/cx4_pgmrom.v | 9,160 | module MODULE1 (
VAR19,
VAR40,
VAR17,
VAR47,
VAR56,
VAR12);
input VAR19;
input [7:0] VAR40;
input [8:0] VAR17;
input [9:0] VAR47;
input VAR56;
output [15:0] VAR12;
tri1 VAR19;
tri0 VAR56;
wire [15:0] VAR14;
wire [15:0] VAR12 = VAR14[15:0];
VAR42 VAR10 (
.VAR58 (VAR47),
.VAR4 (VAR17),
.VAR28 (VAR19),
.VAR36 (VAR40),
.VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s.pp.blackbox.v | 1,292 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR4,
VAR3
);
output VAR2 ;
input VAR1 ;
input VAR4;
input VAR3;
endmodule | apache-2.0 |
mikecat/verilog_serial2spi | serial2spi.v | 4,292 | module MODULE1 (reset, clk, VAR17, VAR11, VAR3, VAR2, VAR15, VAR16, VAR1);
input reset;
input clk;
input VAR17;
output VAR11;
input VAR3;
output VAR2;
output VAR15;
output VAR16;
input VAR1;
reg VAR11;
wire VAR2;
reg VAR15;
reg VAR16;
reg [7:0] VAR9;
reg [3:0] VAR12;
reg [2:0] VAR4;
reg VAR5;
reg VAR14;
reg VAR10;
reg ... | mit |
mamijaz/RISC-V | src/riscv_pipeline/decode/IMM_EXTENDER.v | 3,135 | module MODULE1 #(
parameter VAR3 = 25 ,
parameter VAR9 = 32 ,
parameter VAR10 = 3 ,
parameter VAR4 = 3'b000 ,
parameter VAR8 = 3'b001 ,
parameter VAR12 = 3'b010 ,
parameter VAR11 = 3'b011 ,
parameter VAR6 = 3'b100 ,
parameter VAR5 = 3'b101
) (
input [VAR3 - 1 : 0] VAR7 ,
input [VAR10 - 1 : 0] VAR13 ,
output [VAR9 - 1 :... | bsd-2-clause |
juan199/Lab_Digitales | exp3/Module_ROM.v | 6,779 | module MODULE1
(
input wire[15:0] VAR38,
output reg [27:0] VAR28
);
always @ ( VAR38 )
begin
case (VAR38)
0: VAR28 = { VAR34 ,24'd4000 };
1: VAR28 = { VAR22 , VAR6,16'd72 }; 2: VAR28 = { VAR42 , 8'd0, VAR6 , 8'd0 };
3: VAR28 = { VAR5 , VAR23 ,16'd0 };
4: VAR28 = { VAR32 , VAR24 ,16'd0 };
5: VAR28 = { VAR16 , 8'd0, VAR6... | lgpl-3.0 |
James534/SubZero | SubZero/fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/altera_avalon_dc_fifo.v | 25,360 | module MODULE1(
VAR45,
VAR18,
VAR22,
VAR74,
VAR35,
VAR56,
VAR19,
VAR103,
VAR87,
VAR98,
VAR93,
VAR107,
VAR100,
VAR77,
VAR11,
VAR13,
VAR47,
VAR2,
VAR101,
VAR97,
VAR50,
VAR12,
VAR75,
VAR55,
VAR25,
VAR54,
VAR34,
VAR8,
VAR28,
VAR49,
VAR29,
VAR85,
VAR91,
VAR26,
VAR44
);
parameter VAR67 = 1;
parameter VAR89 = 8;
parameter VAR... | mit |
ychaim/FPGA-Litecoin-Miner | experimental/LX150-SLOWEIGHT-A/ltcminer_icarus.v | 12,192 | module MODULE1 (VAR42, VAR55, VAR41, VAR31, VAR108, VAR106, VAR2, VAR33, VAR110, VAR13);
function integer VAR63; input integer VAR88;
begin
VAR88 = VAR88-1;
for (VAR63=0; VAR88>0; VAR63=VAR63+1)
VAR88 = VAR88>>1;
end
endfunction
parameter VAR75 = VAR75;
parameter VAR75 = 25; VAR74
parameter VAR16 = VAR16; else
paramete... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtn/sky130_fd_sc_hs__dlrtn.behavioral.v | 2,339 | module MODULE1 (
VAR8,
VAR22 ,
VAR21 ,
VAR19 ,
VAR16 ,
VAR2
);
input VAR8;
input VAR22 ;
input VAR21 ;
output VAR19 ;
input VAR16 ;
input VAR2 ;
wire VAR3 ;
wire VAR1 ;
reg VAR13 ;
wire VAR18 ;
wire VAR15 ;
wire VAR5 ;
wire VAR7;
wire VAR12 ;
wire VAR14 ;
wire VAR20 ;
wire VAR10 ;
not VAR9 (VAR3 , VAR7 );
not VAR4 (VAR... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/bitc_capture_control.v | 1,980 | module MODULE1(
input VAR2,
input VAR3,
input VAR6,
input VAR7,
output reg VAR5,
output reg VAR8,
output reg VAR4,
output reg VAR1
);
always@(posedge VAR3 or negedge VAR6)
begin
if(!VAR6)
begin
VAR8 <= 1'b0;
VAR1 <= 1'b0;
end
else
begin
VAR8 <= VAR7;
VAR1 <= VAR8;
end
end
always@(posedge VAR2 or negedge VAR6)
begin
if(... | gpl-3.0 |
elegabriel/myzju | junior1/CA/LAB/lab6/lab6_gxl_3120102146/code/EX_ME.v | 1,564 | module MODULE1(
clk,rst,VAR4,
VAR6, VAR15, VAR10, VAR5, VAR17, VAR1,VAR3,VAR14,
VAR12, VAR8, VAR13, VAR9, VAR7, VAR11,VAR2,VAR16
);
input clk,rst,VAR4;
input wire [31:0] VAR6,VAR10,VAR3,VAR14;
input wire [4:0] VAR15;
input wire VAR5,VAR17,VAR1;
output reg [31:0] VAR12,VAR13,VAR2,VAR16;
output reg [4:0] VAR8;
output reg... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/controller/arb_select.v | 19,073 | module MODULE1 #
(
parameter VAR77 = 100,
parameter VAR58 = "VAR66",
parameter VAR109 = 11,
parameter VAR91 = 3,
parameter VAR78 = "8",
parameter VAR62 = 4,
parameter VAR57 = 31,
parameter VAR107 = 8,
parameter VAR11 = "VAR103",
parameter VAR113 = "VAR89",
parameter VAR34 = "VAR89",
parameter VAR83 = 4,
parameter VAR33... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/source/GDA_St_N8_M4_P4.v | 1,844 | module MODULE1(
input [7:0] VAR23,
input [7:0] VAR22,
output [8:0] VAR43
);
wire [2:0] VAR46, VAR15, VAR2, VAR44;
wire VAR32,VAR4;
wire VAR51,VAR21,VAR12,VAR10;
wire VAR36;
wire VAR3;
and VAR42(VAR51,VAR23[0],VAR22[0]);
and VAR19(VAR21,VAR23[1],VAR22[1]);
xor VAR38(VAR12,VAR23[0],VAR22[0]);
xor VAR13(VAR10,VAR23[1],VAR... | gpl-3.0 |
asicguy/gplgpu | hdl/de3d/de3d_tfog.v | 5,445 | module MODULE1
(
input VAR23, input VAR29, input VAR10, input VAR19, input [6:2] VAR15, input [7:0] VAR22, input [31:0] VAR8, input [13:0] VAR1, input VAR2,
output [31:0] VAR17, output [7:0] VAR14 );
reg [8:0] VAR26;
reg [7:0] VAR7, VAR30;
reg [7:0] VAR14;
reg [7:0] VAR25;
reg [8:0] VAR28;
wire [5:0] VAR31, VAR18;
wire... | gpl-3.0 |
8l/kestrel | 2/nexys2/steamer16-4/steamer16x4.v | 6,243 | module MODULE1(
input VAR28,
input VAR31,
output [15:1] VAR9,
output VAR34,
output VAR24,
output VAR39,
output [1:0] VAR21,
output VAR10,
output VAR32,
output [15:0] VAR43,
input VAR25,
input [15:0] VAR29
);
reg [15:1] VAR27;
reg VAR16;
reg VAR26;
reg [1:0] sel;
reg VAR12;
reg VAR23;
reg [15:0] VAR1;
assign VAR9 = VAR2... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/Multipliers/26bit/RKOA/RKOA.v | 8,693 | module MODULE1
(
input wire [VAR10-1:0] VAR31,
input wire [VAR10-1:0] VAR14,
output wire [2*VAR10-1:0] VAR29
);
wire [VAR10/2+1:0] VAR28;
wire [VAR10/2+1:0] VAR15;
wire [2*(VAR10/2)-1:0] VAR16;
wire [2*(VAR10/2+1)-1:0] VAR3;
wire [2*(VAR10/2+2)-1:0] VAR11;
wire [2*(VAR10/2+2)-1:0] VAR6;
wire [2*(VAR10/2+2)-1:0] VAR27;
... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_4.behavioral.v | 1,170 | module MODULE1( VAR3, VAR5, VAR1 );
input VAR3, VAR5;
output VAR1;
VAR2 VAR4(.VAR3(VAR3),.VAR5(VAR5),.VAR1(VAR1));
VAR2 VAR6(.VAR3(VAR3),.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
rohit21122012/CPU | ALU/Logic/ASHIFTER/ASHIFTER_32bit.v | 2,818 | module MODULE1(VAR60, VAR95, VAR72);
input [31:0] VAR95;
input VAR72;
output [31:0] VAR60;
wire VAR14;
wire [61:0]VAR68;
wire VAR26;
not VAR21(VAR14,VAR72);
and VAR24 (VAR68[0], VAR95[0],VAR72);
and VAR88 (VAR60[0], VAR95[1],VAR14);
and VAR87 (VAR68[2], VAR95[1],VAR72);
and VAR17 (VAR68[3], VAR95[2],VAR14);
and VAR47 (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrckapwr/sky130_fd_sc_hd__lpflow_isobufsrckapwr_16.v | 2,506 | module MODULE1 (
VAR2 ,
VAR9,
VAR7 ,
VAR10,
VAR5 ,
VAR3 ,
VAR4 ,
VAR1
);
output VAR2 ;
input VAR9;
input VAR7 ;
input VAR10;
input VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR1 ;
VAR6 VAR8 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
mistryalok/Zedboard | learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_1/synth/design_1_auto_pc_1.v | 15,739 | module MODULE1 (
VAR24,
VAR102,
VAR57,
VAR19,
VAR82,
VAR35,
VAR16,
VAR73,
VAR65,
VAR13,
VAR81,
VAR10,
VAR39,
VAR25,
VAR71,
VAR95,
VAR74,
VAR58,
VAR15,
VAR105,
VAR18,
VAR107,
VAR53,
VAR26,
VAR37,
VAR104,
VAR97,
VAR56,
VAR22,
VAR85,
VAR90,
VAR3,
VAR1,
VAR55,
VAR30,
VAR32,
VAR108,
VAR8,
VAR86,
VAR14,
VAR48,
VAR88,
VAR70,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/maj3/sky130_fd_sc_ms__maj3_2.v | 2,174 | module MODULE1 (
VAR10 ,
VAR4 ,
VAR2 ,
VAR7 ,
VAR9,
VAR6,
VAR5 ,
VAR8
);
output VAR10 ;
input VAR4 ;
input VAR2 ;
input VAR7 ;
input VAR9;
input VAR6;
input VAR5 ;
input VAR8 ;
VAR1 VAR3 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
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