repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2_lp.v | 2,094 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR2 ,
VAR5,
VAR8,
VAR9 ,
VAR3
);
output VAR4 ;
input VAR7 ;
input VAR2 ;
input VAR5;
input VAR8;
input VAR9 ;
input VAR3 ;
VAR6 VAR1 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR4,
VAR7,
VAR2
);
output VAR4;
... | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/fifo.v | 3,996 | module MODULE1(VAR4, VAR2, VAR5, VAR3, VAR11, VAR6, reset, clk);
parameter VAR10 = 8; parameter VAR7 = 8;
output [VAR7-1:0] VAR4;
output VAR2;
output VAR5;
input [VAR7-1:0] VAR3;
input VAR11;
input VAR6;
input reset;
input clk;
reg [VAR7-1:0] VAR4; reg VAR2,VAR5; reg [VAR10-1:0] VAR12, VAR8;
reg [VAR10-1:0] VAR9 [VAR7-... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41o/sky130_fd_sc_lp__a41o_1.v | 2,426 | module MODULE1 (
VAR10 ,
VAR12 ,
VAR11 ,
VAR7 ,
VAR6 ,
VAR1 ,
VAR3,
VAR5,
VAR9 ,
VAR8
);
output VAR10 ;
input VAR12 ;
input VAR11 ;
input VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR3;
input VAR5;
input VAR9 ;
input VAR8 ;
VAR4 VAR2 (
.VAR10(VAR10),
.VAR12(VAR12),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VA... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_085.v | 1,544 | module MODULE1 (
VAR2,
VAR12
);
input [31:0] VAR2;
output [31:0]
VAR12;
wire [31:0]
VAR7,
VAR1,
VAR15,
VAR13,
VAR3,
VAR6,
VAR14,
VAR11,
VAR8,
VAR10;
assign VAR7 = VAR2;
assign VAR6 = VAR3 << 1;
assign VAR10 = VAR8 << 3;
assign VAR8 = VAR11 - VAR15;
assign VAR11 = VAR14 << 2;
assign VAR13 = VAR7 << 2;
assign VAR3 = VAR7... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor3/sky130_fd_sc_ls__xnor3.pp.blackbox.v | 1,302 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR3 ,
VAR5 ,
VAR6,
VAR2,
VAR8 ,
VAR4
);
output VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR5 ;
input VAR6;
input VAR2;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_058.v | 1,508 | module MODULE1 (
VAR12,
VAR11
);
input [31:0] VAR12;
output [31:0]
VAR11;
wire [31:0]
VAR8,
VAR5,
VAR4,
VAR7,
VAR10,
VAR6,
VAR13,
VAR3,
VAR1;
assign VAR8 = VAR12;
assign VAR7 = VAR4 << 2;
assign VAR6 = VAR8 << 8;
assign VAR13 = VAR8 + VAR6;
assign VAR10 = VAR4 + VAR7;
assign VAR3 = VAR13 << 4;
assign VAR1 = VAR10 + VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxtp/sky130_fd_sc_hs__dfxtp.pp.symbol.v | 1,278 | module MODULE1 (
input VAR2 ,
output VAR4 ,
input VAR1 ,
input VAR5,
input VAR3
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_2.behavioral.v | 1,250 | module MODULE1( VAR7, VAR5, VAR3, VAR6 );
input VAR7, VAR5, VAR3;
output VAR6;
VAR1 VAR2(.VAR7(VAR7),.VAR5(VAR5),.VAR3(VAR3),.VAR6(VAR6));
VAR1 VAR4(.VAR7(VAR7),.VAR5(VAR5),.VAR3(VAR3),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_lvc_wpad/sky130_fd_io__top_power_lvc_wpad.pp.blackbox.v | 2,060 | module MODULE1 (
VAR19 ,
VAR5 ,
VAR3 ,
VAR20,
VAR1,
VAR8 ,
VAR15 ,
VAR18 ,
VAR17 ,
VAR14 ,
VAR12 ,
VAR4 ,
VAR7 ,
VAR9 ,
VAR6 ,
VAR10 ,
VAR16 ,
VAR2 ,
VAR13 ,
VAR11
);
inout VAR19 ;
inout VAR5 ;
inout VAR3 ;
inout VAR20;
inout VAR1;
inout VAR8 ;
inout VAR15 ;
inout VAR18 ;
inout VAR17 ;
inout VAR14 ;
inout VAR12 ;
inout... | apache-2.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_Clock_Signals.v | 10,590 | module MODULE1 (
VAR37,
reset,
VAR95,
VAR60,
VAR38,
VAR1
);
input VAR37;
input reset;
output VAR95;
output VAR60;
output VAR38;
output VAR1;
localparam VAR41 = 1;
localparam VAR89 = 1;
wire [ 2: 0] VAR54;
wire VAR50;
wire VAR19;
assign VAR1 = VAR50;
assign VAR38 = VAR54[0];
assign VAR95 = VAR54[1];
assign VAR60 = VAR54... | mit |
eda-globetrotter/MarcheProcessor | processor/spare/build2/piso.v | 7,360 | module MODULE1(VAR12, VAR15, VAR18, VAR4, VAR2, clk);
output VAR12;
output VAR15;
input [7:0] VAR18;
input clk;
input VAR2;
input VAR4;
reg VAR15; reg VAR12; reg VAR10; reg VAR20; reg VAR11; reg VAR3; reg VAR17; reg VAR9; reg VAR1;
reg VAR19; reg VAR14; reg VAR16; reg VAR5; reg VAR8; reg VAR6;
always @(~VAR2)
begin
VAR... | mit |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_CPU_jtag_debug_module_wrapper.v | 10,092 | module MODULE1 (
VAR42,
VAR20,
clk,
VAR23,
VAR39,
VAR15,
VAR4,
VAR31,
VAR35,
VAR46,
VAR5,
VAR7,
VAR25,
VAR19,
VAR60,
VAR55,
VAR45,
VAR34,
VAR11,
VAR30,
VAR10,
VAR18,
VAR6,
VAR2,
VAR51,
VAR50,
VAR8,
VAR40,
VAR49,
VAR57,
VAR17,
VAR56,
VAR33,
VAR14,
VAR48,
VAR28
)
;
output [ 37: 0] VAR10;
output VAR18;
output VAR6;
output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.v | 2,480 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR7,
VAR8 ,
VAR6 ,
VAR4 ,
VAR3 ,
VAR10 ,
VAR9
);
output VAR5 ;
output VAR1 ;
input VAR7;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR10 ;
input VAR9 ;
VAR2 VAR11 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR10(VAR10),
.... | apache-2.0 |
azonenberg/antikernel-ipcores | graphics/gpu/Minimal2DGPU.v | 18,829 | module MODULE1(
clk,
VAR19,
VAR30,
VAR17,
VAR6,
VAR4,
VAR14,
VAR25,
VAR27,
VAR9,
VAR29,
VAR11,
VAR24,
VAR12,
VAR32,
VAR31,
VAR1,
VAR26,
VAR18
);
parameter VAR10 = 128; parameter VAR7 = 32; parameter VAR5 = 1;
localparam VAR16 = VAR10 * VAR7;
localparam VAR33 = VAR16 * VAR5;
localparam VAR20 = VAR33 / 8;
localparam VAR3... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2/sky130_fd_sc_lp__nor2_8.v | 2,086 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR1 ,
VAR3,
VAR7,
VAR4 ,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR1 ;
input VAR3;
input VAR7;
input VAR4 ;
input VAR2 ;
VAR8 VAR9 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR6,
VAR5,
VAR1
);
output VAR6;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invlp/sky130_fd_sc_lp__invlp.blackbox.v | 1,224 | module MODULE1 (
VAR4,
VAR1
);
output VAR4;
input VAR1;
supply1 VAR5;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2.behavioral.v | 1,177 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
zhelnio/ahb_lite_eic | src/mfp_eic_core.v | 15,342 | module MODULE1
(
input VAR60,
input VAR38,
input [ VAR15 - 1 : 0 ] VAR65,
input [ VAR16 - 1 : 0 ] VAR8,
output reg [ 31 : 0 ] VAR4,
input [ VAR16 - 1 : 0 ] VAR37,
input [ 31 : 0 ] VAR67,
input VAR61,
output [ 17 : 1 ] VAR48,
output [ 3 : 0 ] VAR46,
output [ 7 : 0 ] VAR25,
output [ 5 : 0 ] VAR11,
output VAR1,
input VAR8... | mit |
valptek/v586 | core_rtl/synthetic_op.v | 1,712 | module MODULE1 ( clk , sel, VAR13, VAR5 , VAR10 );
input clk;
input [2:0] sel;
input [31:0] VAR13,VAR5;
output [63:0] VAR10;
wire signed [31:0] VAR2,VAR7;
wire [31:0] VAR4,VAR6;
wire [31:0] VAR12,VAR14;
wire [63:0] VAR8;
reg [47:0] VAR16, VAR3;
reg [ 2:0] VAR11,VAR15;
reg [31:0] VAR9,VAR1;
assign VAR2 = (sel[1:0] == 2'... | apache-2.0 |
siamumar/TinyGarbled | circuit_synthesis/knns/first_nns_seq.v | 1,222 | module MODULE1
(
parameter VAR2 = 15
)
(
clk,
rst,
VAR1,
VAR20,
VAR15
);
function integer VAR13;
input [31:0] VAR16;
reg [31:0] VAR22;
begin
VAR22 = VAR16;
for (VAR13=0; VAR22>0; VAR13=VAR13+1)
VAR22 = VAR22>>1;
end
endfunction
localparam VAR11 = VAR13(VAR2);
input clk;
input rst;
input [VAR2-1:0] VAR1;
input [VAR2-1:0... | gpl-3.0 |
Triple-Z/COExperiment_Repo | Project_1/control/ctrl.v | 1,992 | module MODULE1 (VAR1, VAR24, VAR14, VAR18, VAR10, VAR11, VAR6, VAR8, VAR3, VAR25);
input [31:0] VAR1;
output reg [3:0] VAR11;
output reg VAR24;
output reg VAR14;
output reg VAR18;
output reg VAR10;
output reg VAR6;
output reg VAR8;
output reg VAR3;
output reg VAR25;
wire [5:0] VAR22;
wire [5:0] VAR9;
assign VAR22 = VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_pwrgood_pp_p/sky130_fd_sc_hd__udp_pwrgood_pp_p.blackbox.v | 1,251 | module MODULE1 (
VAR2,
VAR1 ,
VAR3
);
output VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21oi/sky130_fd_sc_ms__a21oi.functional.pp.v | 2,006 | module MODULE1 (
VAR15 ,
VAR11 ,
VAR2 ,
VAR10 ,
VAR14,
VAR1,
VAR5 ,
VAR16
);
output VAR15 ;
input VAR11 ;
input VAR2 ;
input VAR10 ;
input VAR14;
input VAR1;
input VAR5 ;
input VAR16 ;
wire VAR13 ;
wire VAR8 ;
wire VAR12;
and VAR3 (VAR13 , VAR11, VAR2 );
nor VAR6 (VAR8 , VAR10, VAR13 );
VAR4 VAR9 (VAR12, VAR8, VAR14, V... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_gsu/main.v | 34,163 | module MODULE1(
output [22:0] VAR172,
output VAR295,
input VAR200,
output VAR309,
input VAR72,
output [21:0] VAR172,
output VAR66,
output VAR330,
output VAR100,
output VAR73,
output VAR259,
input VAR311,
input VAR213,
input [23:0] VAR95,
input VAR141,
input VAR178,
input VAR452,
inout [7:0] VAR382,
input VAR462,
input ... | gpl-2.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_add_nto1.v | 2,269 | module MODULE1
(VAR7, VAR5);
parameter VAR4 = 1;
parameter VAR2 = 2;
localparam VAR3 = VAR1(VAR2 * (1 << VAR4 - 1) + 1);
input [0:VAR4*VAR2-1] VAR7;
output [0:VAR3-1] VAR5;
reg [0:VAR3-1] VAR5;
integer VAR6;
always @(VAR7)
begin
VAR5 = {VAR3{1'b0}};
for(VAR6 = 0; VAR6 < VAR2; VAR6 = VAR6 + 1)
begin
VAR5 = VAR5 + VAR7[V... | mit |
lvd2/zxevo | fpga/baseconf/trunk/sound/sound.v | 2,337 | module MODULE1(
input wire clk,
input wire [7:0] din,
input wire VAR1,
input wire VAR10,
input wire VAR13,
output wire VAR4
);
reg [6:0] VAR8;
reg [7:0] VAR11;
reg VAR12;
reg VAR5;
reg VAR3;
wire VAR14;
always @(posedge clk)
begin
if( VAR1 && (VAR5!=VAR3) )
VAR12 <= 1'b1;
end
else if( VAR10 )
VAR12 <= 1'b0;
end
always ... | gpl-3.0 |
hakehuang/pycpld | ips/ip/uart8bit/my_uart_tx8to8.v | 2,509 | module MODULE1(
clk,
VAR3,
VAR9,
VAR10,
VAR1,
VAR2,
VAR16
);
input clk;
input VAR3;
input [2:0] VAR9;
input [7:0] VAR10;
input VAR1;
output VAR2;
output VAR16;
parameter VAR11 = 13'd5208, VAR15 = 13'd2603, VAR4 = 13'd1301, VAR13 = 13'd867, VAR12 = 13'd434, VAR8 = 13'd195;
reg [12:0] VAR14;
reg VAR6;
reg [3:0] VAR5;
reg... | mit |
glennchid/font5-firmware | src/verilog/synthesis/chanOffsetMUX.v | 4,345 | module MODULE1 (
input clk,
input signed [12:0] VAR6,
input [3:0] VAR15,
output reg signed [12:0] VAR16 = 13'VAR10, output reg signed [12:0] VAR7 = 13'VAR10,
output reg signed [12:0] VAR11 = 13'VAR10,
output reg signed [12:0] VAR1 = 13'VAR10,
output reg signed [12:0] VAR12 = 13'VAR10,
output reg signed [12:0] VAR14 = 1... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_dff_en.v | 4,902 | if (VAR4 && VAR2==VAR6 && (VAR15==VAR11)) \
begin: VAR13 \
VAR17 VAR19(.VAR10(VAR3) \
,.VAR1({ VAR2 { VAR5 } }) \
,.VAR18({ VAR2 {VAR9} }) \
,.VAR12(VAR16) \
); \
end
module MODULE1 #(VAR2="VAR14"
, VAR4=1
, VAR15=1
)
(input VAR9
,input [VAR2-1:0] VAR3
,input VAR5
,output [VAR2-1:0] VAR16
);
begin : VAR7
reg [VAR2-1:0]... | bsd-3-clause |
ffu/DSA-3.2.2 | usrp/fpga/toplevel/mrfm/shifter.v | 3,753 | module MODULE1(input wire [33:0] in, output wire [15:0] out, input wire [7:0] VAR6);
reg [15:0] VAR5, VAR1;
wire [15:0] VAR2;
reg [18:0] VAR4;
wire VAR3;
always @*
case(VAR6)
0 : VAR5 = in[15:0];
1 : VAR5 = in[16:1];
2 : VAR5 = in[17:2];
3 : VAR5 = in[18:3];
4 : VAR5 = in[19:4];
5 : VAR5 = in[20:5];
6 : VAR5 = in[21:6]... | gpl-3.0 |
YosysHQ/yosys | techlibs/nexus/lrams_map.v | 8,557 | module MODULE1 (...);
parameter VAR35 = 0;
parameter VAR71 = "VAR37";
input VAR70;
input VAR46;
input VAR50;
input VAR122;
input VAR45;
input VAR170;
input [13:0] VAR61;
input [3:0] VAR144;
input [31:0] VAR104;
output [31:0] VAR125;
input VAR173;
input VAR28;
input VAR7;
input VAR180;
input VAR29;
input [13:0] VAR126;
... | isc |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/altera_avalon_st_pipeline_base.v | 4,993 | module MODULE1 (
clk,
reset,
VAR10,
VAR4,
VAR3,
VAR14,
VAR9,
VAR12
);
parameter VAR1 = 1;
parameter VAR13 = 8;
parameter VAR11 = 1;
localparam VAR2 = VAR1 * VAR13;
input clk;
input reset;
output VAR10;
input VAR4;
input [VAR2-1:0] VAR3;
input VAR14;
output VAR9;
output [VAR2-1:0] VAR12;
reg VAR5;
reg VAR15;
reg [VAR2-1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2i/sky130_fd_sc_hd__mux2i.functional.v | 1,558 | module MODULE1 (
VAR5 ,
VAR3,
VAR7,
VAR8
);
output VAR5 ;
input VAR3;
input VAR7;
input VAR8 ;
wire VAR6;
VAR1 VAR2 (VAR6, VAR3, VAR7, VAR8 );
buf VAR4 (VAR5 , VAR6);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s.pp.symbol.v | 1,355 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR3 ,
input VAR1,
input VAR6,
input VAR4
);
endmodule | apache-2.0 |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/num_6.v | 1,027 | module MODULE1(
input [2:0] VAR3,
output reg [4:0] VAR4
);
parameter [4:0] VAR6 = 5'b01110; parameter [4:0] VAR1 = 5'b00001; parameter [4:0] VAR5 = 5'b01111; parameter [4:0] VAR2 = 5'b10001;
always @ *
begin
case (VAR3)
3'b000:
VAR4 = VAR6;
3'b001:
VAR4 = VAR1;
3'b010:
VAR4 = VAR5;
3'b011:
VAR4 = VAR2;
3'b100:
VAR4 = V... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_led_pio/synth/ghrd_10as066n2_led_pio.v | 1,518 | module MODULE1 (
input wire clk, input wire [3:0] VAR2, output wire [3:0] VAR1, input wire VAR4, input wire [1:0] address, input wire VAR6, input wire [31:0] VAR8, input wire VAR9, output wire [31:0] VAR5 );
VAR3 VAR7 (
.clk (clk), .VAR4 (VAR4), .address (address), .VAR6 (VAR6), .VAR8 (VAR8), .VAR9 (VAR9), .VAR5 (VAR5)... | mit |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/multi_fft/multi_fft_stub.v | 1,206 | module MODULE1(VAR1, VAR3, VAR2, VAR4)
;
input VAR1;
input [28:0]VAR3;
input [28:0]VAR2;
output [57:0]VAR4;
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_4.functional.v | 1,746 | module MODULE1( VAR7, VAR23, VAR14, VAR27, VAR20 );
input VAR23, VAR27, VAR14;
output VAR20, VAR7;
wire VAR22;
and VAR18( VAR22, VAR23, VAR27 );
wire VAR1;
and VAR5( VAR1, VAR23, VAR14 );
wire VAR12;
and VAR2( VAR12, VAR27, VAR14 );
or VAR11( VAR20, VAR22, VAR1, VAR12 );
wire VAR25;
and VAR21( VAR25, VAR23, VAR27, VAR1... | apache-2.0 |
eda-globetrotter/PicenoDecoders | final/src/tosynth Folder/alu_shift.v | 95,822 | module MODULE1 (VAR5,VAR9,VAR2,VAR4,VAR1);
output [0:127] VAR1;
input [0:127] VAR5;
input [0:127] VAR9;
input [0:1] VAR2;
input [0:4] VAR4;
parameter VAR8 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR1;
integer VAR3;
integer VAR6;
integer VAR7;
always @(VAR5 or VAR9 or VAR2 or VAR4)
begin
case(VAR4)
begin
ca... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/HardFloat/source/fNToRecFN.v | 3,945 | module
MODULE1#(parameter VAR14 = 3, parameter VAR8 = 3) (
input [(VAR14 + VAR8 - 1):0] in,
output [(VAR14 + VAR8):0] out
);
localparam VAR2 = VAR16(VAR8);
wire VAR5;
wire [(VAR14 - 1):0] VAR11;
wire [(VAR8 - 2):0] VAR4;
assign {VAR5, VAR11, VAR4} = in;
wire VAR3 = (VAR11 == 0);
wire VAR7 = (VAR4 == 0);
wire [(VAR2 - 1... | bsd-3-clause |
asicguy/gplgpu | hdl/altera_project/dpram_64_32x32_be/dpram_64_32x32_be.v | 9,594 | module MODULE1 (
VAR34,
VAR30,
VAR17,
VAR50,
VAR36,
VAR41,
VAR3,
VAR7);
input [63:0] VAR34;
input VAR30;
input [4:0] VAR17;
input [5:0] VAR50;
input [7:0] VAR36;
input VAR41;
input VAR3;
output [31:0] VAR7;
wire [31:0] VAR25;
wire [31:0] VAR7 = VAR25[31:0];
VAR15 VAR22 (
.VAR43 (VAR30),
.VAR1 (VAR41),
.VAR5 (VAR3),
.VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4/sky130_fd_sc_ls__or4.blackbox.v | 1,269 | module MODULE1 (
VAR8,
VAR7,
VAR3,
VAR9,
VAR2
);
output VAR8;
input VAR7;
input VAR3;
input VAR9;
input VAR2;
supply1 VAR1;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.v | 2,398 | module MODULE1 (
VAR2 ,
VAR6,
VAR11,
VAR7 ,
VAR5 ,
VAR1,
VAR8,
VAR4 ,
VAR10
);
output VAR2 ;
input VAR6;
input VAR11;
input VAR7 ;
input VAR5 ;
input VAR1;
input VAR8;
input VAR4 ;
input VAR10 ;
VAR3 VAR9 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR10(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai.functional.pp.v | 2,184 | module MODULE1 (
VAR9 ,
VAR13,
VAR14,
VAR11 ,
VAR6 ,
VAR5,
VAR19,
VAR18 ,
VAR7
);
output VAR9 ;
input VAR13;
input VAR14;
input VAR11 ;
input VAR6 ;
input VAR5;
input VAR19;
input VAR18 ;
input VAR7 ;
wire VAR12 ;
wire VAR4 ;
wire VAR1 ;
wire VAR8;
nand VAR16 (VAR12 , VAR14, VAR13 );
or VAR2 (VAR4 , VAR6, VAR11 );
nand... | apache-2.0 |
asicguy/gplgpu | hdl/math/flt_recip.v | 11,256 | module MODULE3
(
input clk,
input [31:0] VAR15,
output [31:0] VAR2
);
wire [7:0] VAR13;
MODULE1 MODULE2
(
.clk (clk),
.VAR6 (VAR15[22:16]),
.VAR19 (VAR13)
);
MODULE2 MODULE1
(
.clk (clk),
.VAR30 (VAR13),
.VAR15 (VAR15),
.VAR2 (VAR2)
);
endmodule
module MODULE1
(
input clk,
input [6:0] VAR6,
output reg [7:0] VAR19
);
al... | gpl-3.0 |
Obijuan/ACC | hw/roadmap/04-debouncer/debouncer.v | 2,739 | module MODULE3 (input wire clk,
input wire VAR14,
output wire VAR13);
wire VAR9, VAR7;
VAR23 #(
.VAR20(6'VAR19 101001),
.VAR15(1'VAR19 1)
) VAR18 (
.VAR21(VAR14),
.VAR10(VAR9)
);
assign VAR7 = ~VAR9;
MODULE2 MODULE1 (
.clk(clk),
.VAR14(VAR7),
.VAR13(VAR13)
);
endmodule
module MODULE2(input wire clk,
input wire VAR14,
o... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_4.behavioral.v | 1,317 | module MODULE1( VAR7, VAR1, VAR2, VAR8, VAR5 );
input VAR8, VAR2, VAR1, VAR7;
output VAR5;
VAR3 VAR6(.VAR7(VAR7),.VAR1(VAR1),.VAR2(VAR2),.VAR8(VAR8),.VAR5(VAR5));
VAR3 VAR4(.VAR7(VAR7),.VAR1(VAR1),.VAR2(VAR2),.VAR8(VAR8),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor3/sky130_fd_sc_ms__xnor3.blackbox.v | 1,269 | module MODULE1 (
VAR4,
VAR3,
VAR5,
VAR7
);
output VAR4;
input VAR3;
input VAR5;
input VAR7;
supply1 VAR2;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_prng.v | 4,471 | module MODULE1 #(
parameter VAR9 = 48271, parameter VAR13 = 323485697,
parameter VAR12 = 901448241,
parameter VAR16 = 31,
parameter VAR4 = 14
)
(
input VAR21,
input VAR3 ,
output signed [VAR4-1:0] VAR19
);
reg [VAR16-1:0] VAR11;
wire [VAR16-1:0] VAR15;
reg [VAR16-1:0] VAR5;
reg [16-1:0] VAR1;
always @(posedge VAR21)
if... | mit |
danbone/core | riscv/src/lib/sync_fifo.v | 3,090 | (VAR1 <= 2) ? 1 : \
(VAR1 <= 4) ? 2 : \
(VAR1 <= 8) ? 3 : \
(VAR1 <= 16) ? 4 : \
(VAR1 <= 32) ? 5 : \
(VAR1 <= 64) ? 6 : \
(VAR1 <= 128) ? 7 : \
(VAR1 <= 256) ? 8 : \
-1
module MODULE1 #(
parameter VAR18 = 3,
parameter VAR19 = 32,
parameter VAR7 = 1,
parameter VAR8 = 1,
parameter VAR13 = 0
)
(
input clk,
input VAR4,
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2.functional.v | 1,112 | module MODULE1 ();
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_p0_iss_probe.v | 1,754 | module MODULE1 (
VAR32
);
parameter VAR6 = 1;
parameter VAR31 = "VAR21";
input [VAR6-1:0] VAR32;
VAR25 VAR12 (
.VAR19 (VAR32),
.VAR24 ()
,
.VAR30 (),
.VAR18 (),
.VAR7 (),
.VAR26 (),
.VAR20 (),
.VAR8 (),
.VAR10 (),
.VAR28 (),
.VAR34 (),
.VAR11 (),
.VAR1 (),
.VAR14 (),
.VAR33 (),
.VAR4 (),
.VAR2 (),
.VAR29 (),
.VAR5 ()
)... | gpl-3.0 |
airabinovich/finalArquitectura | UART/rx.v | 2,147 | module MODULE1(
input VAR11, input VAR14, input reset,
input VAR15, output reg VAR9, output reg [7:0] dout );
localparam [1:0] VAR12 = 0,
VAR1 = 1,
VAR3 = 2,
VAR8 = 3;
localparam VAR10 = 8,
VAR13= 0,
VAR6= 1;
reg [1:0] VAR7, VAR2;
reg [3:0] VAR4;
reg [3:0] VAR5;
always @(posedge VAR15, posedge reset) begin
if(reset)
VA... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32ai/sky130_fd_sc_ms__o32ai.behavioral.v | 1,643 | module MODULE1 (
VAR10 ,
VAR4,
VAR2,
VAR16,
VAR11,
VAR15
);
output VAR10 ;
input VAR4;
input VAR2;
input VAR16;
input VAR11;
input VAR15;
supply1 VAR5;
supply0 VAR13;
supply1 VAR9 ;
supply0 VAR8 ;
wire VAR12 ;
wire VAR17 ;
wire VAR1;
nor VAR6 (VAR12 , VAR16, VAR4, VAR2 );
nor VAR14 (VAR17 , VAR11, VAR15 );
or VAR7 (VAR... | apache-2.0 |
miyukki/spartan-3an-vga | serial.v | 2,681 | module MODULE1 # (
parameter VAR16 = 1'b1,
parameter VAR21 = 1'b0,
parameter VAR8 = 5208,
parameter VAR7 = 8,
parameter VAR14 = 9,
parameter VAR4 = 10
)(
input VAR22,
output VAR15,
input [63:0] VAR17,
input [2:0] VAR20,
output [2:0] VAR18,
output VAR3,
output VAR11
);
reg [63:0] VAR13;
reg [2:0] VAR1;
assign VAR5 = VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4bb/sky130_fd_sc_ms__nand4bb.pp.symbol.v | 1,340 | module MODULE1 (
input VAR8 ,
input VAR2 ,
input VAR3 ,
input VAR5 ,
output VAR9 ,
input VAR4 ,
input VAR7,
input VAR6,
input VAR1
);
endmodule | apache-2.0 |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/hls_gamma_correction.v | 26,862 | module MODULE1 (
VAR145,
VAR162,
VAR117,
VAR153,
VAR83,
VAR54,
VAR79,
VAR99,
VAR170,
VAR45,
VAR52,
VAR174,
VAR44,
VAR150,
VAR41,
VAR56,
VAR160,
VAR29,
VAR129,
VAR173,
VAR103,
VAR146,
VAR90,
VAR36,
VAR98,
VAR74,
VAR67,
VAR37,
VAR46,
VAR66,
VAR55,
VAR136,
VAR78,
VAR130,
VAR122,
VAR123,
VAR100
);
parameter VAR11 = 32;
par... | mit |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_byte_lane.v | 27,862 | module MODULE1 #(
parameter VAR256 = "VAR121", parameter VAR111 = "VAR204",
parameter VAR220 = 12'b111111111111,
parameter VAR227 = 12'b111111111111,
parameter VAR10 = 24'b001000100010001000100010,
parameter VAR306 = "VAR333",
parameter VAR117 = 4,
parameter VAR168 = "VAR204",
parameter VAR92 = 1,
parameter VAR170 = 1,... | bsd-2-clause |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/reader/rfid_reader.v | 6,936 | module MODULE1 (
reset, clk, VAR33, VAR7
);
input reset, clk, VAR33;
output VAR7;
parameter VAR15 = 0;
parameter VAR57 = 1;
parameter VAR44 = 2;
parameter VAR43 = 3;
parameter VAR18 = 4;
parameter VAR53 = 5;
parameter VAR10 = 6;
parameter VAR30 = 7;
parameter VAR34 = 8;
parameter VAR32 = 9;
parameter VAR13 = 10;
parame... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2_1.v | 1,966 | module MODULE2 (
VAR5,
VAR4,
VAR3 ,
VAR6
);
input VAR5;
input VAR4;
input VAR3 ;
input VAR6 ;
VAR2 VAR1 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE2 ();
supply1 VAR5;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR6 ;
VAR2 VAR1 ();
endmodule | apache-2.0 |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/syn/src/bmu.v | 2,410 | module MODULE1 (VAR5, VAR10, VAR3, VAR8, VAR2, VAR9, VAR6, VAR1, VAR7, VAR4);
output [1:0] VAR3, VAR8, VAR2, VAR9, VAR6, VAR1, VAR7, VAR4;
input VAR5, VAR10;
reg [1:0] VAR3, VAR8, VAR2, VAR9, VAR6, VAR1, VAR7, VAR4;
always@ (VAR5 or VAR10)
begin
if (VAR5==0 && VAR10==0)
begin
VAR3 <= 2'd0; VAR8 <= 2'd2; VAR2 <= 2'd2; V... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/mul_u16.v | 9,438 | module MODULE1 (
clk,
VAR15,
VAR34,
VAR29,
VAR27,
VAR12);
parameter VAR4 = 16;
localparam VAR18 = VAR4 - 1;
input clk;
input [15:0] VAR15;
input [15:0] VAR34;
output [31:0] VAR29;
input [VAR18:0] VAR27;
output [VAR18:0] VAR12;
reg [VAR18:0] VAR40 = 'd0;
reg [16:0] VAR23 = 'd0;
reg [16:0] VAR28 = 'd0;
reg [15:0] VAR10 =... | mit |
HSID/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/TX_controller_noloss.v | 10,049 | module MODULE1(
input clk,
input rst,
input [4:0] VAR11,
input VAR23,
input [31:0] VAR25,
input [31:0] VAR2,
output reg VAR9,
input VAR21,
output reg [27:6] VAR13,
output reg [2:0] VAR14
);
localparam VAR12 = 3'b000;
localparam VAR20 = 3'b001;
localparam VAR28 = 3'b010;
localparam VAR18 = 3'b011;
localparam VAR16 = 3'b... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtn/sky130_fd_sc_ls__dfrtn.functional.v | 1,775 | module MODULE1 (
VAR13 ,
VAR2 ,
VAR7 ,
VAR12
);
output VAR13 ;
input VAR2 ;
input VAR7 ;
input VAR12;
wire VAR3 ;
wire VAR10 ;
wire VAR8;
not VAR5 (VAR10 , VAR12 );
not VAR6 (VAR8, VAR2 );
VAR4 VAR1 VAR11 (VAR3 , VAR7, VAR8, VAR10);
buf VAR9 (VAR13 , VAR3 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_4.behavioral.pp.v | 2,990 | module MODULE1( VAR14, VAR2, VAR24, VAR13, VAR19, VAR21 );
input VAR2, VAR14, VAR24;
inout VAR19, VAR21;
output VAR13;
reg VAR20;
VAR11 VAR28(.VAR14(VAR14),.VAR2(VAR2),.VAR24(VAR24),.VAR13(VAR13),.VAR19(VAR19),.VAR21(VAR21),.VAR20(VAR20));
VAR11 VAR8(.VAR14(VAR14),.VAR2(VAR2),.VAR24(VAR24),.VAR13(VAR13),.VAR19(VAR19),.... | apache-2.0 |
jotego/jt51 | hdl/jt51_noise_lfsr.v | 1,258 | module MODULE1 #(parameter VAR1=14220 )(
input rst,
input clk,
input VAR3,
input VAR4,
output out
);
reg [16:0] VAR2;
assign out = VAR2[16];
always @(posedge clk, posedge rst) begin : VAR5
if( rst ) begin
VAR2 <= VAR1[16:0];
end
else if(VAR3) begin
if( VAR4 ) begin
VAR2[16:1] <= VAR2[15:0];
VAR2[0] <= ~(VAR2[16]^VAR2[1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr.blackbox.v | 1,376 | module MODULE1 (
VAR4,
VAR5
);
output VAR4;
input VAR5;
supply1 VAR3 ;
supply0 VAR1 ;
supply1 VAR6;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_sysid_qsys.v | 1,419 | module MODULE1 (
address,
VAR1,
VAR3,
VAR2
)
;
output [ 31: 0] VAR2;
input address;
input VAR1;
input VAR3;
wire [ 31: 0] VAR2;
assign VAR2 = address ? 1419000801 : 2899645186;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2i/sky130_fd_sc_hs__mux2i.behavioral.pp.v | 1,857 | module MODULE1 (
VAR10,
VAR2,
VAR6 ,
VAR13 ,
VAR7 ,
VAR4
);
input VAR10;
input VAR2;
output VAR6 ;
input VAR13 ;
input VAR7 ;
input VAR4 ;
wire VAR9;
wire VAR1 ;
VAR3 VAR8 (VAR9, VAR13, VAR7, VAR4 );
VAR11 VAR12 (VAR1 , VAR9, VAR10, VAR2);
buf VAR5 (VAR6 , VAR1 );
endmodule | apache-2.0 |
anderson1008/NOCulator | hring/hw/bless_mc/seqPortAlloc.v | 5,417 | module MODULE2(
VAR10,
VAR7,
VAR15,
VAR11,
VAR1,
VAR14
);
input [VAR9-1:0] VAR10;
input [VAR17-2:0] VAR7, VAR15;
output [VAR17-2:0] VAR11, VAR1;
output [VAR9-1:0] VAR14;
wire [VAR9-1:0] VAR12 [VAR17-1:0];
wire [VAR17-2:0] VAR5, VAR16;
wire [VAR17-2:0] VAR13, VAR3;
assign VAR12[0] = VAR10;
genvar VAR4;
generate
for (VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i_m.v | 2,211 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR7 ,
VAR1 ,
VAR10,
VAR5,
VAR3 ,
VAR2
);
output VAR8 ;
input VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR10;
input VAR5;
input VAR3 ;
input VAR2 ;
VAR9 VAR4 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_ethmac/eth_clockgen.v | 5,374 | module MODULE1(VAR4, VAR7, VAR8, VAR5, VAR11, VAR2);
parameter VAR6=1;
input VAR4; input VAR7; input [7:0] VAR8;
output VAR2; output VAR5; output VAR11;
reg VAR2;
reg [7:0] VAR1;
wire VAR10;
wire [7:0] VAR3;
wire [7:0] VAR9;
assign VAR9[7:0] = (VAR8[7:0]<2)? 8'h02 : VAR8[7:0]; assign VAR3[7:0] = (VAR9[7:0]>>1) - 8'b1;
... | lgpl-3.0 |
fabianz66/cursos-tec | taller-digital/Lab2/laboratorio2/time_parameters.v | 1,397 | module MODULE1(clk, rst, VAR1, VAR5, VAR4, VAR6, VAR8);
input clk;
input rst;
input VAR1;
input [1:0] VAR5;
input [3:0] VAR4;
input [1:0] VAR6;
output [3:0] VAR8;
reg [3:0] VAR2, VAR3, VAR7;
begin
begin
begin
end
begin | mit |
titorgalaxy/Titor | rtl/verilog/chardev/FSM_VGA.v | 4,341 | module MODULE1(
VAR31,
VAR34,
VAR26,
VAR15, VAR4,
reset,
clk
);
output VAR31;
output VAR34;
output VAR26;
input clk;
input reset;
reg [VAR18-1:0] VAR19;
reg [VAR18-1:0] VAR1;
output wire [VAR18-1:0] VAR15;
output wire [VAR18-1:0] VAR4;
reg [VAR18-1:0] VAR25;
reg [VAR18-1:0] VAR42;
wire VAR11;
wire VAR21;
wire [VAR18-1:... | gpl-3.0 |
mamijaz/RISC-V | src/riscv_pipeline/forwarding_unit/FORWARDING_UNIT.v | 9,580 | module MODULE1 #(
parameter VAR64 = 32 ,
parameter VAR29 = 5 ,
parameter VAR54 = 2 ,
parameter VAR8 = 3 ,
parameter VAR24 = 3'b000 ,
parameter VAR9 = 1'b0 ,
parameter VAR3 = 1'b1 ,
parameter VAR25 = 1'b0 ,
parameter VAR63 = 1'b1 ,
parameter VAR52 = 2'b00 ,
parameter VAR53 = 2'b01 ,
parameter VAR5 = 2'b10 ,
parameter VA... | bsd-2-clause |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_ethmac/eth_top.v | 36,680 | module MODULE1
(
VAR10, VAR2, VAR175, VAR97,
VAR180, VAR121, VAR214, VAR291, VAR75, VAR58, VAR171,
VAR153, VAR74, VAR229,
VAR8, VAR167, VAR282,
VAR254, VAR276, VAR104,
VAR17, VAR194,
VAR118, VAR144, VAR100, VAR217,
VAR90, VAR41, VAR262, VAR230, VAR234, VAR42,
VAR256, VAR132, VAR129, VAR246,
VAR284
,
VAR88, VAR169, VAR1... | lgpl-3.0 |
sundw2014/carADS | fpga_firmware/top.v | 3,425 | module MODULE1(
clk,
VAR49,
VAR29,
VAR1,
VAR28,
VAR8,
VAR26,
VAR13,
VAR46,
VAR37,
VAR52,
VAR42,
VAR2,
VAR51,
VAR6,
VAR53,
VAR40,
VAR5
);
input clk, VAR49, VAR37;
inout VAR29;
input[15:0]VAR1;
output VAR28, VAR8, VAR26, VAR13, VAR46, VAR52;
input VAR2;
output VAR42;
output reg [7:0] VAR51;
output wire VAR6,VAR5;
output ... | lgpl-3.0 |
rurume/openrisc_vision_hardware | ISE/or1200_dmmu_top.v | 10,102 | module MODULE1(
clk, rst,
VAR3, VAR43, VAR50, VAR4, VAR27, VAR2,
VAR38, VAR1,
VAR17, VAR11, VAR7, VAR36, VAR39,
VAR25, VAR10, VAR30,
VAR48, VAR45, VAR53, VAR24, VAR18
);
parameter VAR19 = VAR41;
parameter VAR9 = VAR41;
input clk;
input rst;
input VAR3;
input VAR43;
input VAR50;
input [VAR9-1:0] VAR4;
input VAR27;
input... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31oi/sky130_fd_sc_ms__a31oi.symbol.v | 1,369 | module MODULE1 (
input VAR6,
input VAR4,
input VAR3,
input VAR5,
output VAR8
);
supply1 VAR7;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_PPS_OPENFLOW/INGRESS/INGRESS_OFFSET.v | 7,805 | module MODULE1(
input clk,
input reset,
input VAR5,
input [133:0] VAR25,
input VAR7,
input VAR45,
output VAR32,
input VAR50,
input [133:0] VAR19,
input VAR16,
input VAR51,
output VAR24,
output reg VAR15,
output reg [133:0] VAR18,
output reg VAR38,
output reg VAR43,
input VAR20
);
wire VAR48;
wire VAR21;
reg VAR23;
wire... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/adv7511/vc707/system_top.v | 6,821 | module MODULE1 (
VAR15,
VAR53,
VAR14,
VAR45,
VAR78,
VAR51,
VAR23,
VAR19,
VAR33,
VAR31,
VAR6,
VAR38,
VAR35,
VAR11,
VAR62,
VAR67,
VAR81,
VAR64,
VAR37,
VAR72,
VAR46,
VAR52,
VAR16,
VAR59,
VAR73,
VAR77,
VAR3,
VAR42,
VAR56,
VAR47,
VAR57,
VAR12,
VAR36,
VAR68,
VAR29,
VAR69,
VAR71,
VAR34,
VAR28,
VAR5,
VAR9,
VAR76,
VAR70,
VAR55,... | gpl-3.0 |
DreamIP/GPStudio | support/io/arm/hdl/arm.v | 12,529 | module MODULE1
(
input wire VAR4,
input wire VAR64,
output wire [14:0] VAR30,
output wire [2:0] VAR107,
output wire VAR106,
output wire VAR55,
output wire VAR3,
output wire VAR83,
output wire VAR52,
output wire VAR67,
output wire VAR65,
output wire VAR23,
inout wire [31:0] VAR45,
inout wire [3:0] VAR40,
inout wire [3:0... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_35.v | 24,092 | module MODULE1 (
clk,
reset,
VAR149,
VAR165,
VAR54,
VAR29,
VAR79
);
parameter VAR10 = 18;
parameter VAR61 = 35;
parameter VAR56 = 18;
localparam VAR77 = 36;
input clk;
input reset;
input VAR149;
input VAR165;
input [VAR10-1:0] VAR54; output VAR29;
output [VAR10-1:0] VAR79;
localparam VAR188 = 18; localparam VAR132 = 36... | mit |
ridecore/ridecore | src/fpga/top.v | 2,984 | module MODULE1
(
input VAR20,
input VAR8,
input VAR16,
output VAR6,
input VAR25,
output reg [7:0] VAR46
);
wire clk;
wire VAR55;
wire [VAR37-1:0] VAR39;
wire [4*VAR24-1:0] VAR3;
wire [8:0] VAR26;
wire [VAR30-1:0] VAR45;
wire [VAR30-1:0] VAR31;
wire [VAR37-1:0] VAR35;
wire VAR5;
wire [VAR30-1:0] VAR28;
wire [VAR37-1:0] ... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/rtl/cpx_spc_rpt.v | 5,990 | module MODULE1 (
VAR23, VAR26, VAR22,
VAR13, VAR17,
VAR38, VAR31, VAR10,
VAR27, VAR35, VAR7,
VAR15, VAR20, VAR28,
VAR34, VAR41, VAR21,
VAR2, VAR39, VAR37,
VAR16, VAR4, VAR25,
VAR44, VAR8, VAR29,
VAR24, VAR14, VAR6,
VAR43, VAR1, VAR3,
VAR42, VAR18,
VAR19, VAR32,
VAR11,
VAR9, VAR40, VAR36, VAR45, VAR12
);
input VAR9;
inp... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp1/megacells/fifo_4k_bb.v | 5,956 | module MODULE1 (
VAR1,
VAR9,
VAR5,
VAR3,
VAR2,
VAR8,
VAR6,
VAR10,
VAR7,
VAR4,
VAR11);
input [15:0] VAR1;
input VAR9;
input VAR5;
input VAR3;
input VAR2;
input VAR8;
output [15:0] VAR6;
output VAR10;
output [11:0] VAR7;
output VAR4;
output [11:0] VAR11;
endmodule | gpl-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/ddr2_phy_bb.v | 4,211 | module MODULE1 (
VAR56,
VAR29,
VAR33,
VAR58,
VAR48,
VAR6,
VAR55,
VAR50,
VAR11,
VAR15,
VAR62,
VAR21,
VAR8,
VAR4,
VAR44,
VAR61,
VAR16,
VAR36,
VAR42,
VAR28,
VAR32,
VAR22,
VAR30,
VAR57,
VAR9,
VAR10,
VAR3,
VAR47,
VAR41,
VAR27,
VAR34,
VAR52,
VAR23,
VAR60,
VAR24,
VAR46,
VAR49,
VAR40,
VAR19,
VAR45,
VAR18,
VAR2,
VAR12,
VAR43,
V... | apache-2.0 |
KiwiOnChip/Projet_VHDL_-_Paint | 04_IP_Xillinx/Clk_Wizard/Clk_Wizard.v | 4,118 | module MODULE1
(
output VAR3,
output VAR4,
input VAR6,
output VAR1,
input VAR7
);
VAR2 VAR5
(
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule | gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_example_driver.v | 44,023 | module MODULE1 (
clk,
VAR64,
VAR80,
VAR90,
VAR56,
VAR109,
VAR16,
VAR96,
VAR6,
VAR74,
VAR44,
VAR86,
VAR12,
VAR1,
VAR48,
VAR41,
VAR113,
VAR105,
VAR9
)
;
output [ 2: 0] VAR109;
output [ 31: 0] VAR16;
output VAR96;
output [ 9: 0] VAR6;
output VAR74;
output VAR44;
output [ 12: 0] VAR86;
output [ 4: 0] VAR12;
output [255: 0]... | gpl-3.0 |
ayaovi/yoda | nexys4_DDR_projects/Keyboard/src/hdl/debouncer.v | 1,036 | module MODULE1(
input clk,
input VAR3,
input VAR5,
output reg VAR8,
output reg VAR4
);
reg [4:0]VAR9, VAR10;
reg VAR7=0,VAR1=0;
reg VAR2, VAR6;
always@(posedge(clk))begin
if (VAR3==VAR7)begin
if (VAR9==19)VAR8<=VAR3;
end
else VAR9<=VAR9+1;
end
else begin
VAR9<="00000";
VAR7<=VAR3;
end
if (VAR5==VAR1)begin
if (VAR10==19... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/or1200/or1200_rf.v | 8,463 | module MODULE1(
clk, rst,
VAR43, VAR17, VAR33, VAR48, VAR42, VAR34,
VAR11, VAR51, VAR6, VAR3, VAR27, VAR14, VAR47,
VAR53, VAR57, VAR25, VAR15, VAR26
);
parameter VAR30 = VAR10;
parameter VAR12 = VAR1;
input clk;
input rst;
input VAR43;
input VAR17;
input [VAR12-1:0] VAR33;
input [VAR30-1:0] VAR48;
input VAR42;
input VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tap/sky130_fd_sc_lp__tap.pp.blackbox.v | 1,215 | module MODULE1 (
VAR4,
VAR1,
VAR2 ,
VAR3
);
input VAR4;
input VAR1;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
lab1-ufba/Genius | infrared_control.v | 8,974 | module MODULE1(
input VAR10, input clk, input reset, output reg VAR5, output reg VAR7, output reg VAR11, output reg VAR14, output reg VAR9 );
integer VAR1;
reg VAR16;
reg VAR6;
parameter VAR3 = 0; parameter VAR13 = 1; parameter VAR15 = 2; parameter VAR17 = 3; parameter VAR12 = 4; parameter VAR4 = 5; parameter VAR8 = 6;... | gpl-3.0 |
olajep/oh | src/adi/hdl/library/util_cdc/sync_bits.v | 2,979 | module MODULE1 #(
parameter VAR3 = 1,
parameter VAR6 = 1)(
input [VAR3-1:0] in,
input VAR5,
input VAR4,
output [VAR3-1:0] out);
generate if (VAR6 == 1) begin
reg [VAR3-1:0] VAR1 = 'h0;
reg [VAR3-1:0] VAR2 = 'h0;
always @(posedge VAR4)
begin
if (VAR5 == 1'b0) begin
VAR1 <= 'b0;
VAR2 <= 'b0;
end else begin
VAR1 <= in;
VA... | mit |
scalable-networks/ext | uhd/fpga/usrp2/vrt/gen_context_pkt.v | 3,275 | module MODULE1
parameter VAR6=0)
(input clk, input reset, input VAR13,
input VAR10, output VAR30,
input [31:0] VAR35,
input [63:0] VAR11,
input [31:0] VAR9,
input [31:0] VAR20,
output [35:0] VAR22, output VAR26, input VAR32);
localparam VAR34 = 0;
localparam VAR27 = 1;
localparam VAR25 = 2;
localparam VAR33 = 3;
localp... | gpl-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/system_mm_interconnect_1.v | 16,432 | module MODULE1 (
input wire VAR17, input wire VAR22, input wire [29:0] VAR85, output wire VAR46, input wire [0:0] VAR8, input wire [7:0] VAR11, input wire VAR91, output wire [63:0] VAR67, output wire VAR86, input wire VAR93, input wire [63:0] VAR37, input wire VAR13, output wire [3:0] VAR31, output wire VAR64, output w... | mit |
jayrandez/Processor | memory.v | 1,570 | module MODULE1(
input wire VAR12,
input wire VAR2,
input wire VAR5,
input wire VAR10,
output wire VAR4,
inout wire[7:0] VAR14,
output reg VAR15 = 0,
input wire read,
input wire write,
input wire[31:0] address,
input wire[31:0] din,
output reg[31:0] dout = 0
);
parameter VAR3 = 2'b00;
parameter VAR9 = 2'b01;
parameter V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4b/sky130_fd_sc_hd__nand4b.functional.pp.v | 1,998 | module MODULE1 (
VAR12 ,
VAR9 ,
VAR2 ,
VAR3 ,
VAR5 ,
VAR15,
VAR1,
VAR10 ,
VAR13
);
output VAR12 ;
input VAR9 ;
input VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR15;
input VAR1;
input VAR10 ;
input VAR13 ;
wire VAR4 ;
wire VAR7 ;
wire VAR11;
not VAR16 (VAR4 , VAR9 );
nand VAR14 (VAR7 , VAR5, VAR3, VAR2, VAR4 );
VAR17 VAR8... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ai/sky130_fd_sc_hdll__o21ai.behavioral.v | 1,538 | module MODULE1 (
VAR12 ,
VAR3,
VAR5,
VAR6
);
output VAR12 ;
input VAR3;
input VAR5;
input VAR6;
supply1 VAR10;
supply0 VAR11;
supply1 VAR2 ;
supply0 VAR7 ;
wire VAR4 ;
wire VAR8;
or VAR1 (VAR4 , VAR5, VAR3 );
nand VAR9 (VAR8, VAR6, VAR4 );
buf VAR13 (VAR12 , VAR8 );
endmodule | apache-2.0 |
fbalakirev/red-pitaya-notes | cores/axis_pulse_height_analyzer_v1_0/axis_pulse_height_analyzer.v | 4,331 | module MODULE1 #
(
parameter integer VAR4 = 16,
parameter VAR14 = "VAR24",
parameter integer VAR40 = 16
)
(
input wire VAR7,
input wire VAR25,
input wire VAR6,
input wire [VAR4-1:0] VAR37,
input wire [VAR40-1:0] VAR39,
input wire [VAR4-1:0] VAR8,
input wire [VAR4-1:0] VAR31,
output wire VAR32,
input wire [VAR4-1:0] VAR... | mit |
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