repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
eda-globetrotter/PicenoDecoders | extra_credit/ee577bHw2q2.v | 1,124 | module MODULE1 (input VAR3[10:0],output VAR2[14:0]);
output reg [14:0] VAR2;
input [10:0] VAR1;
reg [3:0] VAR4;
VAR4[0]=((VAR3[0]^VAR3[1])^(VAR3[3]^VAR3[4]))^((VAR3[6]^VAR3[8])^VAR3[10]);
VAR4[1]=((VAR3[0]^VAR3[2])^(VAR3[3]^VAR3[5]))^((VAR3[6]^VAR3[9])^VAR3[10]);
VAR4[2]=((VAR3[1]^VAR3[2])^(VAR3[3]^VAR3[7]))^((VAR3[8]^... | mit |
Willster419/ELEC3725_vivado_projects | assignment_6/cpu3.v | 12,933 | module MODULE4(VAR9,clk,VAR1,VAR36,VAR30);
input clk;
wire [5:0] VAR50;
wire [5:0] VAR17;
input [31:0] VAR9; wire [31:0] VAR40; wire [31:0] VAR16; wire [5:0] VAR24; wire [31:0] VAR37; wire [5:0] VAR32; reg VAR20; wire VAR4; wire [31:0] VAR2; wire [5:0] rd; wire [31:0] VAR25; wire [31:0] VAR7; output [31:0] VAR1; wire [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2b/sky130_fd_sc_hd__or2b.pp.blackbox.v | 1,281 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR3 ,
VAR4,
VAR1,
VAR7 ,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR1;
input VAR7 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv_16.v | 2,058 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR7,
VAR4,
VAR3 ,
VAR1
);
output VAR8 ;
input VAR2 ;
input VAR7;
input VAR4;
input VAR3 ;
input VAR1 ;
VAR5 VAR6 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR8,
VAR2
);
output VAR8;
input VAR2;
supply1 VAR7;
supply0 VAR4;... | apache-2.0 |
alexforencich/verilog-ethernet | rtl/ssio_sdr_in_diff.v | 2,986 | module MODULE1 #
(
parameter VAR12 = "VAR31",
parameter VAR1 = "VAR20",
parameter VAR16 = 1
)
(
input wire VAR7,
input wire VAR6,
input wire [VAR16-1:0] VAR23,
input wire [VAR16-1:0] VAR28,
output wire VAR29,
output wire [VAR16-1:0] VAR19
);
wire VAR10;
wire [VAR16-1:0] VAR8;
genvar VAR11;
generate
if (VAR12 == "VAR22"... | mit |
blackmesalabs/sump2 | sump2.v | 31,688 | module MODULE1 #
(
parameter VAR92 = 1024,
parameter VAR137 = 10,
parameter VAR149 = 4,
parameter VAR46 = 16,
parameter VAR51 = 1,
parameter VAR151 = 1,
parameter VAR4 = 1,
parameter VAR63 = 1,
parameter VAR130 = 1,
parameter VAR21 = 1,
parameter VAR145 = 1,
parameter VAR1 = 0,
parameter VAR48 = 16'd80,
parameter VAR15... | gpl-3.0 |
GuzTech/swapforth | j1a/icestorm/j1a.v | 7,108 | module MODULE1(
output [1:0] VAR61,
input VAR21, VAR33, VAR68,
input [10:0] VAR75,
input VAR26, VAR67, VAR1,
input [10:0] VAR99,
input [1:0] VAR29, VAR22
);
parameter VAR30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR4 = 256'h0000000000000000000000000000000000000000000000000000... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrc/sky130_fd_sc_hd__lpflow_isobufsrc.functional.pp.v | 2,061 | module MODULE1 (
VAR2 ,
VAR4,
VAR13 ,
VAR3 ,
VAR1 ,
VAR9 ,
VAR5
);
output VAR2 ;
input VAR4;
input VAR13 ;
input VAR3 ;
input VAR1 ;
input VAR9 ;
input VAR5 ;
wire VAR12 ;
wire VAR15 ;
wire VAR8;
not VAR7 (VAR12 , VAR4 );
and VAR11 (VAR15 , VAR12, VAR13 );
VAR10 VAR14 (VAR8, VAR15, VAR3, VAR1, VAR4);
buf VAR6 (VAR2 , V... | apache-2.0 |
Siliciumer/DOS-Mario-FPGA | sources/first_stage.v | 5,536 | module MODULE1
(
input wire [7:0] VAR43,
input wire [3:0] VAR14,
input wire [5:0] VAR25,
input wire [5:0] VAR13,
input wire [5:0] VAR46,
input wire VAR38,
input wire VAR35,
input wire clk,
input wire rst,
output reg [11:0] VAR34,
output reg [11:0] VAR3,
output reg [5:0] VAR32,
output reg VAR4,
output reg VAR54,
output ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_4.behavioral.v | 2,848 | module MODULE1( VAR26, VAR20, VAR14, VAR8 );
input VAR14, VAR26, VAR20;
output VAR8;
reg VAR24;
VAR16 VAR13(.VAR26(VAR26),.VAR20(VAR20),.VAR14(VAR14),.VAR8(VAR8),.VAR24(VAR24));
VAR16 VAR18(.VAR26(VAR26),.VAR20(VAR20),.VAR14(VAR14),.VAR8(VAR8),.VAR24(VAR24));
buf VAR10(VAR2,VAR20);
not VAR4(VAR1,VAR14);
and VAR25(VAR22... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o.pp.symbol.v | 1,448 | module MODULE1 (
input VAR2,
input VAR1,
input VAR9 ,
input VAR3 ,
output VAR7 ,
input VAR6 ,
input VAR8,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0n/sky130_fd_sc_lp__inputiso0n.functional.pp.v | 1,760 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR6,
VAR10 ,
VAR11 ,
VAR9 ,
VAR8
);
output VAR1 ;
input VAR4 ;
input VAR6;
input VAR10 ;
input VAR11 ;
input VAR9 ;
input VAR8 ;
wire VAR3;
and VAR5 (VAR3, VAR4, VAR6 );
VAR7 VAR2 (VAR1 , VAR3, VAR10, VAR11);
endmodule | apache-2.0 |
rcls/discus | verilog/discus.v | 10,772 | module MODULE1(input wire clk,
input wire reset,
output wire VAR37,
output wire VAR56,
output wire [7:0] VAR15,
output wire [7:0] VAR48,
input wire [7:0] VAR42,
output bit [7:0] VAR46,
output bit VAR43,
input wire [7:0] VAR33);
bit VAR2 = 1;
always@(posedge clk) begin : VAR21
bit VAR23;
VAR23 <= reset;
VAR2 <= VAR23;
e... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v | 3,004 | module MODULE1
(input clk, input reset, input VAR14,
input [35:0] VAR8,
input VAR3,
output VAR1,
output [18:0] VAR24,
output VAR11,
input VAR20 );
wire [18:0] VAR30;
wire VAR6, VAR29;
wire [35:0] VAR2;
wire VAR32, VAR13;
VAR9 #(.VAR33(36)) VAR18
(.clk(clk),.reset(reset),.VAR14(VAR14),
.VAR21(VAR8), .VAR19(VAR3), .VAR23... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbp/sky130_fd_sc_hd__dlxbp.behavioral.pp.v | 1,983 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR13 ,
VAR7,
VAR5,
VAR8,
VAR6 ,
VAR12
);
output VAR11 ;
output VAR3 ;
input VAR13 ;
input VAR7;
input VAR5;
input VAR8;
input VAR6 ;
input VAR12 ;
wire VAR10 ;
wire VAR1;
wire VAR15 ;
reg VAR17 ;
wire VAR4 ;
VAR2 VAR9 (VAR10 , VAR15, VAR1, VAR17, VAR5, VAR8);
buf VAR16 (VAR11 , VAR10 );... | apache-2.0 |
marcuseng/synchronousRead | MemoryCtrl.v | 3,519 | module MODULE1(VAR25, VAR16, VAR7, VAR11, VAR8,
VAR22, VAR23, VAR4, VAR19, VAR5, VAR21, VAR15,
VAR18, VAR2
);
input VAR25, VAR16, VAR18, VAR2;
input [22:0] VAR15;
output VAR11, VAR8, VAR22, VAR23, VAR4, VAR19, VAR5;
output [26:1] VAR7;
output VAR21;
reg VAR11, VAR8, VAR22, VAR23, VAR4, VAR19, VAR5;
reg [22:0] address =... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/slaveController/slaveDirectcontrol.v | 7,237 | module MODULE1 (VAR26, VAR9, VAR6, VAR8, VAR21, VAR5, clk, VAR1, VAR27, rst);
input VAR6;
input VAR8;
input clk;
input VAR1;
input [1:0] VAR27;
input rst;
output [7:0] VAR26;
output [7:0] VAR9;
output VAR21;
output VAR5;
reg [7:0] VAR26, VAR4;
reg [7:0] VAR9, VAR23;
wire VAR6;
wire VAR8;
reg VAR21, VAR25;
reg VAR5, VAR... | gpl-3.0 |
AngelTerrones/MUSB | Hardware/mux_switch/mux_switch.v | 5,871 | module MODULE1 #(
parameter VAR7 = 2,
parameter [VAR7*32-1:0] VAR3 = 0,
parameter [VAR7*32-1:0] VAR17 = 0
)(
input clk,
input [31:0] VAR25, input [31:0] VAR15, input [3:0] VAR12, input VAR8, output [31:0] VAR16, output VAR10, output reg VAR23, input [VAR7*32-1:0] VAR18, input [VAR7-1:0] VAR5, output [31:0] VAR21, outpu... | mit |
ultraembedded/altor32 | rtl/cpu/altor32_regfile_xil.v | 5,327 | module MODULE1
(
input VAR22 ,
input VAR6 ,
input VAR19 ,
input [4:0] VAR18 ,
input [4:0] VAR15 ,
input [4:0] VAR24 ,
output reg [31:0] VAR28 ,
output reg [31:0] VAR25 ,
input [31:0] VAR9
);
parameter VAR3 = "VAR11";
wire [31:0] VAR32;
wire [31:0] VAR39;
wire [31:0] VAR27;
wire [31:0] VAR31;
wire [31:0] VAR2;
wire [31:... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/Multipliers/Karatsubas/Karatsubas.srcs/sources_1/imports/sine_cosine_CORDIC/CORDIC_FSM_v2.v | 8,973 | module MODULE1
(
input wire clk, input wire reset, input wire VAR26, input wire VAR29, input wire VAR8, input wire VAR49,
input wire [1:0] VAR17, input wire [1:0] VAR34, input wire VAR25, input wire VAR11, VAR47, input wire VAR18, VAR43,
output reg VAR6,
output reg VAR48, output reg VAR36, output reg VAR35, output reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxbp/sky130_fd_sc_ms__edfxbp.behavioral.v | 2,290 | module MODULE1 (
VAR3 ,
VAR12,
VAR13,
VAR7 ,
VAR23
);
output VAR3 ;
output VAR12;
input VAR13;
input VAR7 ;
input VAR23 ;
supply1 VAR16;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR17 ;
wire VAR9 ;
reg VAR18 ;
wire VAR8 ;
wire VAR14 ;
wire VAR4;
wire VAR6 ;
wire VAR15 ;
wire VAR22 ;
VAR20 VAR10 (VAR6, VAR9, VAR8, VAR14 );
... | apache-2.0 |
lbl-cal/StanfordNoC | router/src/clib/c_lod.v | 2,865 | module MODULE1
(VAR13, VAR1);
parameter VAR10 = 32;
localparam VAR4 = VAR8(VAR10);
input [0:VAR10-1] VAR13;
output [0:VAR10-1] VAR1;
wire [0:VAR10-1] VAR1;
genvar VAR9;
wire [0:(VAR4+1)*VAR10-1] VAR5;
wire [0:(VAR4+1)*VAR10-1] VAR14;
assign VAR5[0:VAR10-1] = VAR13;
assign VAR14[0:VAR10-1] = VAR13;
generate
for(VAR9 = 0... | bsd-2-clause |
cpulabs/gci-std-display | rtl/display_controller/gci_std_display_sequencer.v | 2,616 | module MODULE1 #(
parameter VAR21 = 640,
parameter VAR2 = 480,
parameter VAR19 = 19,
parameter VAR17 = 23
)(
input wire VAR18,
input wire VAR13,
input wire VAR15,
input wire VAR22,
output wire VAR6,
input wire [31:0] VAR14,
output wire VAR20,
output wire VAR23,
input wire VAR3,
output wire [VAR17-1:0] VAR5,
output wire... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp.functional.v | 1,983 | module MODULE1 (
VAR15 ,
VAR5 ,
VAR9 ,
VAR1 ,
VAR11 ,
VAR16
);
output VAR15 ;
input VAR5 ;
input VAR9 ;
input VAR1 ;
input VAR11 ;
input VAR16;
wire VAR12 ;
wire VAR14 ;
wire VAR7;
not VAR2 (VAR14 , VAR16 );
VAR10 VAR4 (VAR7, VAR9, VAR1, VAR11 );
VAR8 VAR13 VAR3 (VAR12 , VAR7, VAR5, VAR14);
buf VAR6 (VAR15 , VAR12 );
e... | apache-2.0 |
alexforencich/verilog-ethernet | rtl/ip_eth_tx_64.v | 26,896 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR71,
output wire VAR77,
input wire [47:0] VAR82,
input wire [47:0] VAR59,
input wire [15:0] VAR33,
input wire [5:0] VAR19,
input wire [1:0] VAR84,
input wire [15:0] VAR16,
input wire [15:0] VAR52,
input wire [2:0] VAR103,
input wire [12:0] VAR87,
input wire ... | mit |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/riffa/tx_port_channel_gate_32.v | 7,035 | module MODULE1 #(
parameter VAR42 = 9'd32,
parameter VAR19 = 8,
parameter VAR12 = VAR42+1
)
(
input VAR30,
input VAR40, output [VAR12-1:0] VAR23, output VAR16, input VAR14,
input VAR25, input VAR6, output VAR11, input VAR21, input [31:0] VAR5, input [30:0] VAR24, input [VAR42-1:0] VAR18, input VAR8, output VAR20 );
reg... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_mul.v | 1,389 | module MODULE1(
input logic VAR4,
input logic VAR7,
input logic enable,
input logic [31:0] VAR1,
input logic [31:0] VAR5,
output logic [31:0] VAR6
);
VAR8 #(
.VAR2(0)
)
VAR3(
.VAR4(VAR4),
.VAR7(VAR7),
.enable(enable),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ai/sky130_fd_sc_hd__o21ai.symbol.v | 1,349 | module MODULE1 (
input VAR2,
input VAR5,
input VAR7,
output VAR3
);
supply1 VAR4;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/spu/rtl/spu_ctl.v | 34,170 | module MODULE1 (
VAR196,VAR179,VAR265,VAR24,
VAR35, VAR137,
VAR31,VAR150,VAR49,
VAR56,
VAR84,
VAR8,
VAR192,
VAR207,
VAR218,
VAR52,
VAR139,
VAR230,
VAR201,
VAR157,
VAR262,
VAR154,
VAR180,
VAR163,
VAR190, VAR257, VAR97,
VAR85, VAR12,
VAR7, VAR195,
VAR156,VAR170, VAR69,
VAR43, VAR25,
VAR39, VAR93, VAR34,
VAR205, VAR107,
V... | gpl-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_026.v | 1,525 | module MODULE1 (
VAR2,
VAR9
);
input [31:0] VAR2;
output [31:0]
VAR9;
wire [31:0]
VAR7,
VAR14,
VAR1,
VAR6,
VAR10,
VAR12,
VAR4,
VAR8,
VAR11;
assign VAR7 = VAR2;
assign VAR8 = VAR7 << 10;
assign VAR12 = VAR1 << 5;
assign VAR11 = VAR4 - VAR8;
assign VAR6 = VAR7 << 15;
assign VAR10 = VAR1 + VAR6;
assign VAR4 = VAR10 + VAR1... | mit |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T27-rom-param/romnotes.v | 1,946 | module MODULE1(input wire clk,
output wire [4:0] VAR3,
output wire VAR5);
parameter VAR9 = VAR14;
parameter VAR23 = "VAR10.VAR6";
parameter VAR11 = 6;
parameter VAR17 = 16;
wire VAR19, VAR18, VAR12;
reg [VAR11-1: 0] addr = 0;
wire VAR8;
reg VAR22 = 0;
wire [VAR17-1: 0] VAR1;
VAR2
.VAR11(VAR11),
.VAR17(VAR17))
VAR21 (
.... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221ai/sky130_fd_sc_hs__o221ai.pp.symbol.v | 1,376 | module MODULE1 (
input VAR4 ,
input VAR2 ,
input VAR8 ,
input VAR1 ,
input VAR7 ,
output VAR6 ,
input VAR5,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp.blackbox.v | 1,385 | module MODULE1 (
VAR9 ,
VAR7,
VAR8,
VAR1 ,
VAR4,
VAR6
);
output VAR9 ;
output VAR7;
input VAR8;
input VAR1 ;
input VAR4;
input VAR6;
supply1 VAR2;
supply0 VAR10;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
P3Stor/P3Stor | pcie/IP core/write_data_fifo.v | 13,589 | module MODULE1(
rst,
VAR71,
VAR347,
din,
VAR28,
VAR217,
dout,
VAR137,
VAR134,
VAR262,
VAR394,
VAR31
);
input rst;
input VAR71;
input VAR347;
input [255 : 0] din;
input VAR28;
input VAR217;
output [31 : 0] dout;
output VAR137;
output VAR134;
output [12 : 0] VAR262;
output [9 : 0] VAR394;
output VAR31;
VAR227 #(
.VAR351(... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111ai/sky130_fd_sc_ms__o2111ai.functional.v | 1,514 | module MODULE1 (
VAR3 ,
VAR7,
VAR4,
VAR1,
VAR2,
VAR9
);
output VAR3 ;
input VAR7;
input VAR4;
input VAR1;
input VAR2;
input VAR9;
wire VAR6 ;
wire VAR8;
or VAR11 (VAR6 , VAR4, VAR7 );
nand VAR10 (VAR8, VAR2, VAR1, VAR9, VAR6);
buf VAR5 (VAR3 , VAR8 );
endmodule | apache-2.0 |
CospanDesign/python | game/panda/panda_path/example_project/rtl/dependencies/ft_master_interface.v | 17,938 | module MODULE1 (
input rst,
input clk,
input VAR63,
output VAR54,
output reg VAR41,
output reg [31:0] VAR48,
output reg [31:0] VAR57,
output reg [31:0] VAR10,
output reg [27:0] VAR61,
output reg VAR56,
input VAR36,
input [31:0] VAR90,
input [31:0] VAR83,
input [31:0] VAR3,
input [27:0] VAR11,
input VAR22,
inout [7:0] V... | mit |
Digilent/vivado-library | ip/Pmods/PmodBT2_v1_0/src/PmodBT2.v | 12,447 | module MODULE1
(VAR117,
VAR22,
VAR97,
VAR79,
VAR68,
VAR132,
VAR127,
VAR171,
VAR40,
VAR151,
VAR136,
VAR36,
VAR121,
VAR99,
VAR32,
VAR179,
VAR90,
VAR175,
VAR23,
VAR152,
VAR137,
VAR57,
VAR116,
VAR119,
VAR173,
VAR112,
VAR109,
VAR92,
VAR186,
VAR88,
VAR123,
VAR111,
VAR60,
VAR183,
VAR167,
VAR135,
VAR166,
VAR64,
VAR61,
VAR11,
V... | mit |
nishtahir/arty-blaze | src/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_0_ecc_gen.v | 7,899 | module MODULE1
parameter VAR17 = 72,
parameter VAR15 = 8,
parameter VAR5 = 64
)
(
VAR14
);
function integer VAR19 (input integer VAR21);
integer VAR18;
if (VAR21 == 1) VAR19 = 1;
else begin
VAR19 = 1;
for (VAR18=2; VAR18<=VAR21; VAR18=VAR18+1)
VAR19 = VAR19 * VAR18;
end
endfunction
function integer VAR1 (input integer ... | apache-2.0 |
sabertazimi/hust-lab | verilog/labs/lab2/src/carry_look_ahead_adder.v | 1,195 | module MODULE1(
input [3:0] VAR4,
input [3:0] VAR5,
input VAR1,
output VAR7,
output [3:0] VAR3,
output VAR2,
output VAR8,
output VAR6
);
wire [3:0] VAR2;
wire [3:0] VAR8;
wire [3:0] VAR6;
assign VAR2 = VAR4 ^ VAR5;
assign VAR8 = VAR4 & VAR5;
assign VAR6[0] = VAR2[0] & VAR1 | VAR8[0];
assign VAR6[1] = VAR2[1] & (VAR2[0]... | mit |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/capture/signal_phase_DDR.v | 11,465 | module MODULE1
parameter VAR4 = 2, parameter VAR52 = VAR4-1, parameter VAR38 = VAR52-1, parameter VAR22 = 0,
parameter VAR23 = 2, parameter VAR43 = 7, parameter VAR28 = 3, parameter VAR26 = VAR28-1, parameter VAR16 = 0,
parameter VAR41 = 0,
parameter VAR15 = 0, parameter VAR17 = 3) (
input VAR56, input VAR35, input VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlxtn/sky130_fd_sc_hdll__dlxtn.behavioral.pp.v | 1,999 | module MODULE1 (
VAR4 ,
VAR15 ,
VAR16,
VAR6 ,
VAR2 ,
VAR7 ,
VAR13
);
output VAR4 ;
input VAR15 ;
input VAR16;
input VAR6 ;
input VAR2 ;
input VAR7 ;
input VAR13 ;
wire VAR14 ;
wire VAR8 ;
wire VAR10;
wire VAR1 ;
reg VAR3 ;
wire VAR12 ;
not VAR17 (VAR14 , VAR10 );
VAR11 VAR9 (VAR8 , VAR1, VAR14, VAR3, VAR6, VAR2);
buf V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/decap/sky130_fd_sc_hd__decap_4.v | 1,870 | module MODULE1 (
VAR3,
VAR1,
VAR6 ,
VAR5
);
input VAR3;
input VAR1;
input VAR6 ;
input VAR5 ;
VAR2 VAR4 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR5 ;
VAR2 VAR4 ();
endmodule | apache-2.0 |
kwantam/multiexp-a5gx | verilog/xillybus.v | 5,231 | module MODULE1(VAR138, VAR93, VAR102, VAR139, VAR125, VAR97,
VAR38, VAR126, VAR127, VAR105, VAR33,
VAR19, VAR121, VAR90, VAR120, VAR11);
input VAR138;
input VAR93;
input [3:0] VAR102;
input [31:0] VAR127;
input VAR105;
input VAR33;
input VAR120;
output [3:0] VAR139;
output VAR125;
output VAR97;
output [3:0] VAR38;
outp... | gpl-3.0 |
timothympace/SHA1-Verilog | sha1_update.v | 2,191 | module MODULE1(
input clk,
input VAR6,
input [511:0] VAR15,
input [159:0] VAR13,
output VAR7,
output reg [159:0] VAR12
);
localparam VAR2 = 2'd0;
localparam VAR11 = 2'd1;
localparam VAR10 = 2'd2;
reg [1:0] VAR14;
reg [1:0] VAR16;
reg [511:0] VAR8;
wire [159:0] VAR1;
reg [ 31:0] VAR5;
reg [ 6:0] VAR4;
reg VAR9;
wire [ 3... | mit |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ip/fmrv32im_artya7_fmrv32im_axis_uart_0_1/synth/fmrv32im_artya7_fmrv32im_axis_uart_0_1.v | 6,654 | module MODULE1 (
VAR3,
VAR8,
VAR13,
VAR14,
VAR18,
VAR10,
VAR31,
VAR4,
VAR22,
VAR26,
VAR17,
VAR25,
VAR7,
VAR30,
VAR5,
VAR9,
VAR2,
VAR28,
VAR12,
VAR6,
VAR1,
VAR21,
VAR15,
VAR19,
VAR20,
VAR24,
VAR16,
VAR23,
VAR29
);
input wire VAR3;
input wire VAR8;
input wire [15 : 0] VAR13;
input wire [3 : 0] VAR14;
input wire [2 : 0] V... | mit |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodTC1_v1_0/src/PmodTC1.v | 10,158 | module MODULE1
(VAR108,
VAR168,
VAR54,
VAR142,
VAR34,
VAR140,
VAR13,
VAR150,
VAR93,
VAR132,
VAR99,
VAR139,
VAR38,
VAR121,
VAR167,
VAR146,
VAR72,
VAR83,
VAR102,
VAR90,
VAR73,
VAR84,
VAR137,
VAR36,
VAR147,
VAR134,
VAR135,
VAR164,
VAR40,
VAR88,
VAR91,
VAR114,
VAR111,
VAR95,
VAR97,
VAR57,
VAR106,
VAR149,
VAR60,
VAR41,
VAR2... | bsd-3-clause |
manasks/ece_510_pre_si_val | Final Project/hdl/top_decode.v | 1,490 | import VAR19::*;
module MODULE1 ();
wire clk;
wire VAR18;
wire VAR5;
wire [VAR13-1:0] VAR25;
wire VAR16;
wire [VAR13-1:0] VAR12;
wire [VAR9-1:0] VAR6;
wire VAR23;
wire [VAR13-1:0] VAR14;
wire [VAR9-1:0] VAR4;
wire VAR10;
wire [VAR13-1:0] VAR22;
wire [VAR9-1:0] VAR7;
wire [VAR13-1:0] VAR3;
VAR17 VAR11;
VAR8 VAR1;
VAR20 ... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_hdiv.v | 2,559 | module MODULE1(
input VAR2,
input VAR27,
output VAR36,
input VAR13,
output reg VAR22,
input signed [11:0] VAR15,
input signed [11:0] VAR28,
input signed [17:0] VAR29,
input signed [17:0] VAR33,
input VAR6,
input [16:0] VAR9,
input VAR8,
input [16:0] VAR24,
input [10:0] VAR32,
output reg VAR20,
input VAR4,
output reg si... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.blackbox.v | 1,437 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR5 ,
VAR7 ,
VAR1,
VAR4 ,
VAR3
);
output VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR1;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v | 10,379 | module MODULE1 #(parameter VAR6(VAR12 )
, parameter VAR6(VAR22 )
, parameter VAR2 = 1
, parameter VAR29 = 0
)
(input VAR7
, input VAR35
, input [VAR12-1:0] VAR17
, input VAR33
, output VAR16
, output VAR14
, output [VAR12-1:0] VAR25
, input VAR19
);
wire VAR5, VAR3;
wire [VAR12-1:0] VAR1;
logic VAR15, VAR24, VAR32;
wir... | bsd-3-clause |
lab11/M-ulator | platforms/HT_m3/hardware/ICE/hdl/basics_int.v | 8,652 | module MODULE1(
input clk,
input rst,
input VAR59,
input [7:0] VAR55,
input VAR80,
input VAR21,
inout VAR50,
inout [7:0] VAR24,
output VAR45,
input VAR47,
input VAR14,
output reg [7:0] VAR43,
output reg [15:0] VAR36,
output [7:0] VAR39
);
parameter VAR52 = 8'h00;
parameter VAR58 = 8'h01;
reg [7:0] VAR19;
wire [7:0] VAR... | apache-2.0 |
8l/kestrel | 2/nexys2/uxa/ps2io/T_uxa_ps2_wrtlgc.v | 2,419 | module MODULE1;
reg VAR1;
reg VAR6;
reg VAR3;
wire VAR8;
wire VAR4;
wire VAR2;
VAR7 VAR5 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3)
);
always begin
VAR6 <= ~VAR6;
end | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_2.behavioral.v | 1,495 | module MODULE1( VAR5, VAR2, VAR4, VAR1 );
input VAR1, VAR4, VAR5;
output VAR2;
VAR6 VAR3(.VAR5(VAR5),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1));
VAR6 VAR7(.VAR5(VAR5),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
anderson1008/NOCulator | hring/hw/RCnode/nodeRouter.v | 2,027 | module MODULE1
(
input VAR25 VAR23,
input VAR25 VAR8,
input VAR25 VAR17,
input VAR25 VAR47,
output VAR46,
output VAR26,
input clk,
input rst,
output VAR25 VAR16,
output VAR25 VAR20,
output VAR25 VAR45,
output VAR25 VAR39
);
wire VAR18 VAR6, VAR28;
wire VAR21 VAR27, VAR5;
assign VAR6 = addr[VAR3]; assign VAR27 = addr[VA... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/processing_system7_bfm_v2_0_ocm_mem.v | 6,600 | module MODULE1();
parameter VAR15 = 32'h40000; parameter VAR12 = VAR3(VAR15/VAR10);
reg [VAR37-1:0] VAR18 [0:(VAR15/VAR10)-1];
task automatic VAR39;
input [(VAR26*8)-1:0] VAR40;
input [VAR36-1:0] VAR4;
input [VAR24-1:0] VAR44;
endtask
task automatic VAR31;
input [1:0] VAR5;
input [VAR36-1:0] VAR4;
input [VAR24-1:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxbp/sky130_fd_sc_hd__edfxbp.behavioral.pp.v | 2,321 | module MODULE1 (
VAR21 ,
VAR8 ,
VAR18 ,
VAR12 ,
VAR2 ,
VAR9,
VAR15,
VAR5 ,
VAR22
);
output VAR21 ;
output VAR8 ;
input VAR18 ;
input VAR12 ;
input VAR2 ;
input VAR9;
input VAR15;
input VAR5 ;
input VAR22 ;
wire VAR11 ;
reg VAR1 ;
wire VAR16 ;
wire VAR17 ;
wire VAR4;
wire VAR14 ;
wire VAR6 ;
wire VAR7 ;
VAR10 VAR20 (VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221a/sky130_fd_sc_lp__o221a.symbol.v | 1,394 | module MODULE1 (
input VAR4,
input VAR5,
input VAR3,
input VAR8,
input VAR9,
output VAR1
);
supply1 VAR6;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
skatpgusskat/KoreaUnivHomework_2015_1 | Computer Architecture/Homework/Lab09/mux2to1_beh.v | 1,327 | module MODULE2(VAR1,VAR2, VAR3, select);
input [4:0] VAR1, VAR2;
input select;
output [4:0] VAR3;
reg [4:0] VAR3;
always @(VAR1 or VAR2 or select)
begin
if (select == 0)
VAR3 = VAR1;
end
else
VAR3 = VAR2;
end
endmodule
module MODULE1(VAR1,VAR2, VAR3, select);
input [31:0] VAR1, VAR2;
input select;
output [31:0] VAR3;
r... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_4.behavioral.pp.v | 1,402 | module MODULE1( VAR6, VAR2, VAR7, VAR5, VAR9, VAR1, VAR10 );
input VAR9, VAR5, VAR2, VAR6;
inout VAR1, VAR10;
output VAR7;
VAR8 VAR4(.VAR6(VAR6),.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5),.VAR9(VAR9),.VAR1(VAR1),.VAR10(VAR10));
VAR8 VAR3(.VAR6(VAR6),.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5),.VAR9(VAR9),.VAR1(VAR1),.VAR10(VAR10)); | apache-2.0 |
cpulabs/mist1032isa | src/core/pipeline_control/pipeline_control_spr_exchange.v | 5,136 | module MODULE1(
input wire VAR3,
input wire VAR7,
input wire VAR30,
input wire [31:0] VAR15,
input wire [31:0] VAR19,
input wire [31:0] VAR26,
input wire VAR31,
input wire VAR4, output wire VAR17,
output wire [31:0] VAR34,
output wire VAR14,
output wire VAR5,
input wire VAR37,
output wire [1:0] VAR2, output wire VAR18,... | bsd-2-clause |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Lundgren FPU/trunk/fpu_add.v | 5,295 | module MODULE1( clk, rst, enable, VAR15, VAR11, VAR4, VAR30, VAR16);
input clk;
input rst;
input enable;
input [63:0] VAR15, VAR11;
output VAR4;
output [55:0] VAR30;
output [10:0] VAR16;
reg VAR4;
reg [10:0] VAR14;
reg [10:0] VAR21;
reg [51:0] VAR3;
reg [51:0] VAR12;
reg VAR5;
reg [10:0] VAR10;
reg [10:0] VAR13;
reg [5... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_hl_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.v | 1,462 | module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
buf VAR2 (VAR1 , VAR3 );
endmodule | apache-2.0 |
jairov4/accel-oil | solution_kintex7/impl/verilog/nfa_accept_samples_generic_hw_add_16ns_16ns_16_4.v | 5,914 | module MODULE3(clk, reset, VAR48, VAR22, VAR16, VAR28);
input clk;
input reset;
input VAR48;
input [16 - 1 : 0] VAR22;
input [16 - 1 : 0] VAR16;
output [16 - 1 : 0] VAR28;
wire [16 - 1 : 0] VAR11;
wire [16 - 1 : 0] VAR40;
wire [4 - 1 : 0] VAR17;
wire [4 - 1 : 0] VAR6;
wire [8 - 1 : 4] VAR47;
wire [8 - 1 : 4] VAR44;
wir... | lgpl-3.0 |
Elphel/x393_sata | ahci/ahci_ctrl_stat.v | 37,216 | module MODULE1 #(
parameter VAR124 = 10 )(
input VAR89, input VAR146, input VAR52, input VAR209,
input [VAR124-1:0] VAR182, input [31:0] VAR17, input VAR11, output reg [VAR124-1:0] VAR44,
output reg VAR204,
output reg [31:0] VAR71,
output VAR116,
input VAR92,
output VAR185,
input VAR81, input VAR88,
input VAR217,
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2b/sky130_fd_sc_ms__and2b.behavioral.pp.v | 1,934 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR4 ,
VAR6,
VAR3,
VAR12 ,
VAR7
);
output VAR8 ;
input VAR9 ;
input VAR4 ;
input VAR6;
input VAR3;
input VAR12 ;
input VAR7 ;
wire VAR14 ;
wire VAR2 ;
wire VAR15;
not VAR1 (VAR14 , VAR9 );
and VAR5 (VAR2 , VAR14, VAR4 );
VAR10 VAR13 (VAR15, VAR2, VAR6, VAR3);
buf VAR11 (VAR8 , VAR15 );
en... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv.pp.blackbox.v | 1,291 | module MODULE1 (
VAR2,
VAR5 ,
VAR4 ,
VAR1 ,
VAR3
);
output VAR2;
input VAR5 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1.blackbox.v | 1,296 | module MODULE1 (
VAR2,
VAR3,
VAR4
);
output VAR2;
input [3:0] VAR3;
input [3:0] VAR4;
supply1 VAR5;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
firemark/katp91 | src/LedCounter.v | 1,991 | module MODULE1(clk, VAR4, enable, write, VAR3, VAR2);
inout [15:0] VAR4;
output [7:0] VAR3;
output reg [3:0] VAR2;
reg [3:0] VAR1 [3:0];
reg [6:0] counter;
input clk, enable, write; | mit |
fbalakirev/red-pitaya-notes | cores/axis_phase_generator_v1_0/axis_phase_generator.v | 1,232 | module MODULE1 #
(
parameter integer VAR1 = 32,
parameter integer VAR7 = 30
)
(
input wire VAR2,
input wire VAR11,
input wire [VAR7-1:0] VAR9,
input wire VAR12,
output wire [VAR1-1:0] VAR6,
output wire VAR5
);
reg [VAR7-1:0] VAR4, VAR8;
reg VAR10, VAR3;
always @(posedge VAR2)
begin
if(~VAR11)
begin
VAR4 <= {(VAR7){1'b0... | mit |
saisrivathsa/Image-Watermarking | ipcore_dir/adder8.v | 7,506 | module MODULE1 (
VAR49, VAR13, VAR70, VAR38
);
input VAR49;
output [8 : 0] VAR13;
input [7 : 0] VAR70;
input [7 : 0] VAR38;
wire \VAR80/VAR69 ;
wire \VAR80/VAR45 ;
wire \VAR80/VAR43 ;
wire \VAR80/VAR62 ;
wire \VAR80/VAR53 ;
wire \VAR80/VAR86 ;
wire \VAR80/VAR24 ;
wire \VAR80/VAR34 ;
wire \VAR80/VAR10 ;
wire \VAR80/VAR3... | mit |
asicguy/gplgpu | hdl/altera_project/spll_pll/spll_pll_bb.v | 12,178 | module MODULE1 (
VAR3,
VAR6,
VAR2,
VAR1,
VAR4,
VAR5);
input VAR3;
input VAR6;
input VAR2;
output VAR1;
output VAR4;
output VAR5;
endmodule | gpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/buffer/buf/buf_manage.v | 4,201 | module MODULE1(
input clk,
input reset,
input VAR32,
input [359:0] VAR38,
input [138:0] VAR17,
input VAR37,
output [7:0] VAR27,
input [10:0] VAR23,
input VAR12,
output [138:0] VAR40,
input [3:0] VAR10,
input VAR33,
input VAR9,
input [359:0] VAR43,
input [138:0] VAR13,
input VAR14,
output [7:0] VAR11,
input [10:0] VAR5,... | apache-2.0 |
AmeerAbdelhadi/Multiported-RAM | mpram_lvt_bin.v | 7,559 | module MODULE1
localparam VAR24 = VAR12(VAR32 ); localparam VAR33 = VAR12(VAR1);
reg [VAR24 -1:0] VAR6 [VAR1-1:0] ; reg [VAR9 -1:0] VAR19 [VAR1-1:0] ; wire [VAR9*VAR21-1:0] VAR20 [VAR1-1:0] ; reg [VAR9 -1:0] VAR16 [VAR1-1:0][VAR21-1:0]; reg [VAR9 -1:0] VAR29 [VAR21-1:0] ; wire [VAR33 *VAR21-1:0] VAR2 ; reg [VAR33 -1:0]... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4/sky130_fd_sc_ms__nor4.behavioral.v | 1,425 | module MODULE1 (
VAR5,
VAR6,
VAR12,
VAR11,
VAR7
);
output VAR5;
input VAR6;
input VAR12;
input VAR11;
input VAR7;
supply1 VAR10;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
wire VAR8;
nor VAR9 (VAR8, VAR6, VAR12, VAR11, VAR7 );
buf VAR1 (VAR5 , VAR8 );
endmodule | apache-2.0 |
jameshegarty/rigel | platform/camera2.0/vsrc/DramWriterBuf.v | 4,752 | module MODULE1(
input VAR33,
input VAR48,
output VAR39,
output reg [31:0] VAR30,
input VAR46,
output reg VAR47,
output [63:0] VAR49,
output [7:0] VAR28,
input VAR44,
output VAR12,
output VAR32,
input [1:0] VAR51,
input VAR17,
output VAR43,
output [3:0] VAR52,
output [1:0] VAR35,
output [1:0] VAR14,
input VAR15,
output ... | mit |
ridecore/ridecore | src/fpga/ram_sync_nolatch.v | 5,925 | module MODULE3 #(
parameter VAR4 = VAR5,
parameter VAR8 = VAR9,
parameter VAR21 = 32
)
(
input wire clk,
input wire [VAR4-1:0] VAR10,
input wire [VAR4-1:0] VAR3,
output wire [VAR8-1:0] VAR7,
output wire [VAR8-1:0] VAR1,
input wire [VAR4-1:0] VAR12,
input wire [VAR8-1:0] VAR17,
input wire VAR15
);
reg [VAR8-1:0] VAR24 [... | bsd-3-clause |
megari/sd2snes | verilog/sd2snes_obc1/address.v | 4,057 | module MODULE1(
input VAR10,
input [7:0] VAR17, input [2:0] VAR6, input [23:0] VAR18, input [7:0] VAR1, input VAR23, output [23:0] VAR12, output VAR16, output VAR2, output VAR7, output VAR20, input [23:0] VAR19,
input [23:0] VAR5,
output VAR24,
output VAR15,
output VAR8,
output VAR9,
output VAR11,
output VAR13,
output ... | gpl-2.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/soc_system_jtag_uart.v | 16,904 | module MODULE3 (
clk,
VAR21,
VAR18,
VAR5,
VAR22,
VAR13,
VAR16
)
;
output VAR5;
output [ 7: 0] VAR22;
output VAR13;
output [ 5: 0] VAR16;
input clk;
input [ 7: 0] VAR21;
input VAR18;
wire VAR5;
wire [ 7: 0] VAR22;
wire VAR13;
wire [ 5: 0] VAR16;
always @(posedge clk)
begin
if (VAR18)
("%VAR17", VAR21);
end
assign VAR16 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.v | 2,825 | module MODULE1 (
VAR11 ,
VAR13 ,
VAR14 ,
VAR5 ,
VAR9 ,
VAR1 ,
VAR2 ,
VAR10,
VAR7 ,
VAR6 ,
VAR8 ,
VAR12
);
output VAR11 ;
output VAR13 ;
input VAR14 ;
input VAR5 ;
input VAR9 ;
input VAR1 ;
input VAR2 ;
input VAR10;
input VAR7 ;
input VAR6 ;
input VAR8 ;
input VAR12 ;
VAR4 VAR3 (
.VAR11(VAR11),
.VAR13(VAR13),
.VAR14(VAR... | apache-2.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_697_bits/rtl/rom.v | 15,193 | module MODULE1 (clk, addr, out);
input clk;
input [8:0] addr;
output reg [27:0] out;
always @(posedge clk)
case (addr)
0: out <= 28'hc30042;
1: out <= 28'h1450045;
2: out <= 28'h1868041;
3: out <= 28'h1c78041;
4: out <= 28'h30046;
5: out <= 28'h580ea00;
6: out <= 28'h5c08041;
7: out <= 28'h5c5ea17;
8: out <= 28'h605ea0... | apache-2.0 |
antmicro/yosys | techlibs/ecp5/arith_map.v | 2,591 | module MODULE1(
module 80ecp5alu (VAR40, VAR25, VAR27, VAR22, VAR21, VAR46, VAR37);
parameter VAR2 = 0;
parameter VAR34 = 0;
parameter VAR44 = 1;
parameter VAR36 = 1;
parameter VAR26 = 1;
input [VAR44-1:0] VAR40;
input [VAR36-1:0] VAR25;
output [VAR26-1:0] VAR21, VAR46;
input VAR27, VAR22;
output [VAR26-1:0] VAR37;
wir... | isc |
igalanommatis/zdma | hw/oled/src/Delay.v | 3,079 | module MODULE1(
VAR7,
VAR10,
VAR3,
VAR6,
VAR9
);
input VAR7;
input VAR10;
input [11:0] VAR3;
input VAR6;
output VAR9;
wire VAR9;
reg [31:0] VAR4 = "VAR1"; reg [16:0] VAR8 = 17'b00000000000000000; reg [11:0] VAR5 = 12'h000;
assign VAR9 = (VAR4 == "VAR11" && VAR6 == 1'b1) ? 1'b1 : 1'b0;
always @(posedge VAR7) begin
if(VA... | gpl-3.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_07_a/hdl/verilog/spi_clgen.v | 5,111 | module MODULE1 (VAR9, rst, VAR10, enable, VAR3, VAR1, VAR6, posedge, negedge);
parameter VAR8 = 1;
input VAR9; input rst; input enable; input VAR10; input VAR3; input [VAR5-1:0] VAR1; output VAR6; output posedge; output negedge;
reg VAR6;
reg posedge;
reg negedge;
reg [VAR5-1:0] VAR4; wire VAR2; wire VAR7;
assign VAR2 ... | bsd-2-clause |
alr46664/lab4 | verilog_source/mem_dport_sclk.v | 1,062 | module MODULE1(
clk, VAR9, VAR2, VAR3, VAR6, VAR10, VAR8, VAR1, VAR5 );
input clk, VAR9, VAR2;
input signed [VAR11-1:0] VAR3, VAR6;
input [VAR7-1:0] VAR10, VAR8;
output reg [VAR11-1:0] VAR1, VAR5;
reg [VAR11-1:0] VAR4 [0:(1<<VAR7)-1];
always @ (posedge clk) begin
if (VAR9) begin
VAR4[VAR10] <= VAR3;
VAR1 <= VAR3;
end e... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_4.functional.pp.v | 1,520 | module MODULE1( VAR12, VAR15, VAR20, VAR2, VAR4, VAR13, VAR6 );
input VAR4, VAR2, VAR15, VAR12;
inout VAR13, VAR6;
output VAR20;
wire VAR3;
not VAR5( VAR3, VAR4 );
wire VAR7;
not VAR10( VAR7, VAR2 );
wire VAR18;
and VAR1( VAR18, VAR3, VAR7 );
wire VAR8;
not VAR11( VAR8, VAR15 );
wire VAR9;
not VAR14( VAR9, VAR12 );
wir... | apache-2.0 |
nyaxt/dmix | async_fifo.v | 2,540 | module MODULE1
parameter VAR20 = 8
)(
input wire VAR6,
input wire VAR13,
input wire [(VAR20-1):0] VAR11,
input wire VAR7,
output wire VAR24,
input wire VAR10,
input wire VAR14,
output wire [(VAR20-1):0] VAR3,
input wire VAR18,
output wire VAR2);
reg [(VAR20-1):0] VAR8 [3:0];
reg [2:0] VAR5;
wire [2:0] VAR4 = VAR5 + (VA... | mit |
mamijaz/RISC-V | src/riscv_pipeline/program_counter/PROGRAME_COUNTER_STAGE.v | 5,424 | module MODULE1 #(
parameter VAR10 = 32 ,
parameter VAR14 = 32 ,
parameter VAR19 = 5 ,
parameter VAR5 = 32'b0 ,
parameter VAR26 = 5'b01110 ,
parameter VAR12 = 5'b01111 ,
parameter VAR27 = 1'b1 ,
parameter VAR11 = 1'b0
) (
input VAR22 ,
input VAR7 ,
input [VAR19 - 1 : 0] VAR3 ,
input VAR21 ,
input [VAR10 - 1 : 0] VAR25 ,... | bsd-2-clause |
everskar2013/PentiumX | Hardware/Code/uart_new.v | 4,942 | module MODULE1 #(
parameter VAR30 = 100000000,
parameter VAR22 = 115200
) (
input [31:0] VAR8,
input [31:0] VAR11,
input VAR6,
input VAR44,
output reg [31:0] VAR29,
output VAR36,
input VAR20,
input VAR21,
output VAR41,
output VAR33,
input VAR40,
output VAR31,
input VAR32
);
reg [15:0] VAR5;
wire [7:0] VAR35;
wire [7:0]... | mit |
jamesbowman/swapforth | j1a/nandland-go/j1a.v | 8,478 | module MODULE2(
output [1:0] VAR105,
input VAR8, VAR46, VAR7,
input [10:0] VAR11,
input VAR30, VAR88, VAR72,
input [10:0] VAR121,
input [1:0] VAR52, VAR65
);
parameter VAR75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR118 = 256'h0000000000000000000000000000000000000000000000000... | bsd-3-clause |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_clk_wiz.v | 6,549 | module MODULE1
( input VAR51,
output VAR36,
input reset,
output VAR73
);
VAR16 VAR21
(.VAR61 (VAR47),
.VAR53 (VAR51));
wire [15:0] VAR13;
wire VAR43;
wire VAR46;
wire VAR82;
wire VAR75;
wire VAR11;
wire VAR44;
wire VAR4;
wire VAR32;
wire VAR48;
wire VAR68;
wire VAR12;
wire VAR67;
wire VAR10;
wire VAR65;
wire VAR64;
wir... | mit |
scalable-networks/ext | uhd/fpga/usrp1/sdr_lib/tx_chain.v | 2,038 | module MODULE1
(input VAR10,
input reset,
input enable,
input wire [7:0] VAR25,
input VAR9,
input VAR8,
input wire [31:0] VAR28,
input wire [15:0] VAR23,
input wire [15:0] VAR6,
output wire [15:0] VAR22,
output wire [15:0] VAR7
);
wire [15:0] VAR2, VAR26;
VAR5 VAR17
( .VAR10(VAR10),.reset(reset),.enable(enable),
.VAR4(... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/tse_mac2_loopback.v | 3,192 | module MODULE1 (
VAR2,
VAR1,
VAR3
);
output VAR2;
input VAR1;
output VAR3;
reg VAR4; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211oi/sky130_fd_sc_ms__a211oi.pp.symbol.v | 1,380 | module MODULE1 (
input VAR2 ,
input VAR1 ,
input VAR8 ,
input VAR3 ,
output VAR5 ,
input VAR7 ,
input VAR6,
input VAR9,
input VAR4
);
endmodule | apache-2.0 |
bgamari/timetag-fpga | timetag_bench.v | 1,436 | module MODULE1();
reg clk;
reg VAR8;
reg VAR14;
reg [7:0] VAR11;
wire [15:0] VAR6;
reg VAR12;
wire [7:0] VAR13;
wire VAR3;
reg VAR7;
reg [3:0] VAR4;
wire [3:0] VAR1;
wire VAR5;
VAR2 VAR9(
.VAR8(VAR8),
.VAR14(VAR14),
.VAR11(VAR11),
.clk(clk),
.VAR10(VAR4),
.VAR3(VAR3),
.VAR13(VAR13),
.VAR7(VAR7)
);
begin | gpl-3.0 |
GLADICOS/CRCAHB | rtl/crc_datapath.v | 8,648 | module MODULE1
(
output [31:0] VAR12,
output [ 1:0] VAR35,
output [ 7:0] VAR69,
output [31:0] VAR26,
output [31:0] VAR77,
input [31:0] VAR42, input [ 1:0] VAR34, input VAR32,
input VAR61,
input VAR8,
input VAR3,
input VAR9,
input VAR29,
input VAR17,
input VAR70,
input VAR23,
input VAR67,
input [1:0] VAR46,
input [1:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor3/sky130_fd_sc_lp__xor3.functional.pp.v | 1,845 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR9 ,
VAR10 ,
VAR8,
VAR6,
VAR4 ,
VAR5
);
output VAR2 ;
input VAR7 ;
input VAR9 ;
input VAR10 ;
input VAR8;
input VAR6;
input VAR4 ;
input VAR5 ;
wire VAR3 ;
wire VAR13;
xor VAR11 (VAR3 , VAR7, VAR9, VAR10 );
VAR12 VAR14 (VAR13, VAR3, VAR8, VAR6);
buf VAR1 (VAR2 , VAR13 );
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/LX9Co_CoPro80186.v | 13,536 | module MODULE1 (
input VAR145,
input [3:0] VAR104,
input VAR9,
input [2:0] VAR156,
inout [7:0] VAR150,
input VAR257,
input VAR125,
input VAR132,
output VAR58,
output VAR7,
output VAR208,
output VAR249,
output VAR17,
output VAR154,
output [18:0] VAR54,
inout [15:0] VAR61
);
wire clk;
wire VAR138;
wire [15:0] VAR41;
wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3/sky130_fd_sc_ms__and3.functional.v | 1,275 | module MODULE1 (
VAR4,
VAR7,
VAR5,
VAR6
);
output VAR4;
input VAR7;
input VAR5;
input VAR6;
wire VAR1;
and VAR2 (VAR1, VAR6, VAR7, VAR5 );
buf VAR3 (VAR4 , VAR1 );
endmodule | apache-2.0 |
migajv/mips_pipeline | verilog/dm.v | 1,229 | module MODULE1(
input wire clk,
input wire rst,
input wire [6:0] VAR2,
input wire [6:0] VAR5,
input wire wr,
input wire [31:0] VAR1,
output wire [31:0] VAR6);
reg [31:0] VAR3 [0:127]; integer VAR4;
always @(posedge clk, negedge rst) begin
if (!rst) begin
for (VAR4 = 0; VAR4 < 128; VAR4=VAR4+1) begin
VAR3[VAR4] <= 32'h0... | gpl-3.0 |
cpulabs/mist1032sa | src/core/scheduler2/priority_encoder_16.v | 26,825 | module MODULE1(
input wire VAR18,
input wire VAR42,
input wire VAR2,
input wire VAR25,
input wire VAR14,
input wire VAR29,
input wire VAR32,
input wire VAR36,
input wire VAR24,
input wire VAR39,
input wire VAR20,
input wire VAR21,
input wire VAR33,
input wire VAR13,
input wire VAR5,
input wire VAR34,
input wire VAR28,
... | bsd-2-clause |
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