repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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fominok/spilol | verilog/discrete.v | 1,202 | module MODULE1(
input clk,
input rst,
input VAR9,
input [31:0] VAR3,
input [31:0] VAR5,
input VAR2,
output reg[31:0] VAR8,
output[127:0] VAR6,
input [127:0] VAR11
);
reg[15:0] VAR7[7:0];
assign VAR6 = {VAR7[7], VAR7[6], VAR7[5], VAR7[4],
VAR7[3], VAR7[2], VAR7[1], VAR7[0]};
wire[15:0] VAR4[7:0];
assign {VAR4[7], VAR4[6... | gpl-2.0 |
sehugg/8bitworkshop | presets/verilog/racing_game_cpu.v | 7,330 | module MODULE1(clk, reset, VAR50, VAR41, VAR46, VAR19, VAR45);
input clk, reset;
input VAR46, VAR19;
output VAR50, VAR41;
wire VAR60;
wire [8:0] VAR23;
wire [8:0] VAR43;
output [3:0] VAR45;
parameter VAR1 = 0; parameter VAR7 = 1; parameter VAR26 = 2; parameter VAR10 = 3; parameter VAR22 = 4; parameter VAR56 = 5; parame... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2/sky130_fd_sc_hdll__or2.pp.blackbox.v | 1,262 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR3 ,
VAR1,
VAR6,
VAR2 ,
VAR5
);
output VAR4 ;
input VAR7 ;
input VAR3 ;
input VAR1;
input VAR6;
input VAR2 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.v | 2,466 | module MODULE1 (
VAR11 ,
VAR9 ,
VAR10 ,
VAR6 ,
VAR12 ,
VAR2 ,
VAR3,
VAR1,
VAR7 ,
VAR4
);
output VAR11 ;
input VAR9 ;
input VAR10 ;
input VAR6 ;
input VAR12 ;
input VAR2 ;
input VAR3;
input VAR1;
input VAR7 ;
input VAR4 ;
VAR8 VAR5 (
.VAR11(VAR11),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR2(VAR2),
.VA... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_impctl_upclk.v | 10,273 | module MODULE1(VAR116 ,VAR59 ,VAR5 ,VAR40 ,
VAR97 ,VAR92 ,VAR110 ,VAR45 ,VAR78 ,VAR31 ,VAR85 ,VAR25
,VAR82 );
output VAR40 ;
output VAR92 ;
output VAR110 ;
output VAR45 ;
output VAR78 ;
output VAR82 ;
input VAR116 ;
input VAR59 ;
input VAR5 ;
input VAR97 ;
input VAR31 ;
input VAR85 ;
input VAR25 ;
wire [9:0] VAR64 ;
wi... | gpl-2.0 |
bit0fun/Fusion-Core | Fusion-Core-Base/not_32.v | 1,028 | module MODULE1(
input [31:0] VAR1, output [31:0] out );
assign out[0] = !VAR1[0];
assign out[1] = !VAR1[1];
assign out[2] = !VAR1[2];
assign out[3] = !VAR1[3];
assign out[4] = !VAR1[4];
assign out[5] = !VAR1[5];
assign out[6] = !VAR1[6];
assign out[7] = !VAR1[7];
assign out[8] = !VAR1[8];
assign out[9] = !VAR1[9];
assi... | gpl-3.0 |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_15/synth/zynq_1_auto_pc_15.v | 13,119 | module MODULE1 (
VAR1,
VAR62,
VAR92,
VAR65,
VAR33,
VAR103,
VAR48,
VAR75,
VAR3,
VAR41,
VAR78,
VAR22,
VAR59,
VAR85,
VAR89,
VAR79,
VAR17,
VAR19,
VAR7,
VAR4,
VAR106,
VAR21,
VAR66,
VAR110,
VAR20,
VAR49,
VAR11,
VAR72,
VAR81,
VAR105,
VAR63,
VAR23,
VAR104,
VAR97,
VAR36,
VAR108,
VAR5,
VAR45,
VAR6,
VAR26,
VAR53,
VAR50,
VAR58,
VA... | mit |
DSDL2016/project2 | source/synthesizer/DE2_synthesizer.v | 6,019 | module MODULE1 (
VAR16, VAR24, VAR13,
VAR41,
VAR28,
VAR31, VAR29, VAR51, VAR25, VAR5, VAR43, VAR1, VAR15, VAR47, );
input VAR16; input VAR24; input VAR13;
input VAR41;
input VAR28;
inout VAR31; output VAR29;
inout VAR51; inout VAR5; input VAR25; output VAR43; inout VAR1; output VAR15;
output VAR47;
assign VAR47 = 1;
wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dff_p/sky130_fd_sc_ms__udp_dff_p.symbol.v | 1,252 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR1
);
endmodule | apache-2.0 |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_tck.v | 8,183 | module MODULE1 (
VAR19,
VAR16,
VAR23,
VAR1,
VAR38,
VAR25,
VAR24,
VAR20,
VAR12,
VAR39,
VAR5,
VAR28,
VAR15,
VAR22,
VAR32,
VAR7,
VAR10,
VAR21,
VAR34,
VAR26,
VAR3,
VAR18,
VAR30,
VAR8,
VAR6,
VAR37,
VAR31,
VAR36,
VAR27,
VAR29,
VAR2
)
;
output [ 1: 0] VAR31;
output VAR36;
output [ 37: 0] VAR27;
output VAR29;
output VAR2;
inpu... | gpl-2.0 |
hmdgharb/5-Staged-MIPS-Pipeline | CONTROLLER.v | 2,406 | module MODULE1(
input VAR11,
input [15:0] VAR6,
input VAR13,
output reg [3:0] VAR9,
output reg VAR10,
output reg VAR2,
output reg VAR7,
output reg VAR14,
output reg VAR1,
output reg VAR3,
output reg VAR12,
output reg VAR4,
output reg VAR8
);
wire [3:0] VAR5;
assign VAR5 = VAR6[15:12];
always@(posedge VAR11) begin
VAR9 ... | gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/video_sys/submodules/video_sys_Pixel_Buffer.v | 7,225 | module MODULE1 (
clk,
reset,
address,
VAR3,
read,
write,
VAR4,
VAR5,
VAR9,
VAR14,
VAR15,
VAR2,
VAR13,
VAR8,
VAR1,
VAR12
);
input clk;
input reset;
input [17: 0] address;
input [ 1: 0] VAR3;
input read;
input write;
input [15: 0] VAR4;
inout [15: 0] VAR5;
output reg [15: 0] VAR9;
output reg VAR14;
output reg [17: 0] VAR... | gpl-2.0 |
esonghori/TinyGarble | circuit_synthesis/a23/a23_alu.v | 7,235 | module MODULE1 (
input [31:0] VAR13,
input [31:0] VAR2,
input VAR20,
input VAR15,
input [8:0] VAR26,
output [31:0] VAR6,
output [3:0] VAR23 );
wire [31:0] VAR5, VAR3, VAR17;
wire [31:0] VAR28, VAR25, VAR27;
wire [31:0] VAR19, VAR4;
wire [31:0] VAR1, VAR7;
wire [32:0] VAR21;
wire VAR12;
wire VAR24;
wire [1:0] VAR9;
wire... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/hrfp_1.0/mult.v | 18,431 | module MODULE1(input wire clk,
input wire [VAR18:0] VAR23, VAR19,
output wire [VAR18:0] VAR1);
parameter VAR2 = 6;
parameter VAR3 = 1;
parameter VAR9 = 0;
parameter VAR22 = 0;
parameter VAR12 = 0;
wire VAR7; wire [53:0] VAR20;
wire [VAR18:0] VAR16, VAR21;
generate
genvar VAR17;
for(VAR17=0; VAR17 <= VAR18; VAR17 = VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111a/sky130_fd_sc_ms__o2111a_2.v | 2,448 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR2 ,
VAR12 ,
VAR4 ,
VAR6 ,
VAR3,
VAR8,
VAR11 ,
VAR9
);
output VAR10 ;
input VAR7 ;
input VAR2 ;
input VAR12 ;
input VAR4 ;
input VAR6 ;
input VAR3;
input VAR8;
input VAR11 ;
input VAR9 ;
VAR5 VAR1 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3... | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_Video_In_video_rgb_resampler_0.v | 5,750 | module MODULE1 (
clk,
reset,
VAR19,
VAR5,
VAR2,
VAR23,
VAR16,
VAR7,
VAR13,
VAR12,
VAR4,
VAR1,
VAR6,
VAR22
);
parameter VAR14 = 23;
parameter VAR15 = 7;
parameter VAR18 = 1;
parameter VAR17 = 0;
parameter VAR3 = 10'h3FF;
input clk;
input reset;
input [VAR14:0] VAR19;
input VAR5;
input VAR2;
input [VAR18:0] VAR23;
input ... | gpl-3.0 |
dailypips/miaow | src/verilog/rtl/alu/dest_shift_reg.v | 1,372 | module MODULE1 (
VAR17,
VAR10,
VAR3,
VAR5,
VAR13,
VAR12,
VAR16,
VAR2,
VAR14,
VAR6,
clk,
rst
);
input [511:0] VAR17;
input [15:0] VAR10;
input [15:0] VAR3;
input [15:0] VAR5;
input VAR13;
input VAR12;
output [2047:0] VAR16;
output [63:0] VAR2;
output [63:0] VAR14;
output [63:0] VAR6;
input clk;
input rst;
VAR1 #(32) VAR... | bsd-3-clause |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/division_factor.v | 1,876 | module MODULE1(VAR1, VAR3, VAR2);
input [7:0] VAR1;
output [15:0] VAR3;
output [8:0] VAR2;
reg [15:0] VAR3;
reg [8:0] VAR2;
always @(VAR1)
begin
case(VAR1)
8'd1: begin VAR3 = 16'd1; VAR2 = 8'd0; end
8'd2: begin VAR3 = 16'd1; VAR2 = 8'd1; end
8'd3: begin VAR3 = 16'd21845; VAR2 = 8'd16; end
8'd4: begin VAR3 = 16'd1; VAR2... | gpl-3.0 |
niamster/hdl | pulse/pulse.v | 2,913 | module MODULE1
parameter VAR24=2)
(input VAR18,
input clk,
output reg MODULE1);
localparam VAR1 = VAR13(VAR16+VAR24)+1;
reg [VAR1-1:0] VAR35;
always @(posedge clk or negedge VAR18) begin
if (~VAR18)
VAR35 <= 1'b0;
end
else if (VAR35 != VAR16+VAR24)
VAR35 <= VAR35 + 1'b1;
end
always @(posedge clk or negedge VAR18) begin... | mit |
fisherdj/avgai | quartus/avgai/vgaControl.v | 3,083 | module MODULE3(clk, VAR12, VAR29, VAR13);
parameter VAR23 = 10, VAR11 = 1;
input clk;
input [VAR23-1:0] VAR12;
output reg [VAR23-1:0] VAR29 = 0;
output VAR13;
assign VAR13 = VAR29+1 == VAR12 ? 1 :
VAR29+1 < VAR12 ? 0 :
VAR11 ? 1 : 1'VAR18;
always @(posedge clk)
if (!VAR13)
VAR29 <= VAR29 + 1;
else
VAR29 <= 0;
endmodule... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/cm_rom_shared.v | 10,151 | module MODULE1 (
VAR52,
VAR32,
VAR38,
VAR58,
VAR19);
input [8:0] VAR52;
input [8:0] VAR32;
input VAR38;
output [3:0] VAR58;
output [3:0] VAR19;
tri1 VAR38;
wire [3:0] VAR21;
wire [3:0] VAR54;
wire VAR42 = 1'h0;
wire [3:0] VAR27 = 4'h0;
wire [3:0] VAR19 = VAR21[3:0];
wire [3:0] VAR58 = VAR54[3:0];
VAR24 VAR49 (
.VAR45 (... | mit |
codustry/cuckoo | FPGA - Verilog HDL/I2Cslave.v | 3,273 | module MODULE1(VAR27, VAR23, VAR8);
inout VAR27;
input VAR23;
output [7:0] VAR8;
parameter VAR28 = 7'h27;
wire VAR18;
wire VAR6;
VAR1 VAR21(.VAR25(VAR6), .VAR11((~VAR23 | VAR18) ? VAR27 : VAR6));
VAR1 VAR24(.VAR25(VAR18), .VAR11(~VAR23 ? 1'b0 : (VAR27 ^ VAR6)));
assign VAR18 = ~VAR23 ? 1'b0 : (VAR27 ^ VAR6) ;
assign VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_1.behavioral.v | 1,098 | module MODULE1( VAR5, VAR3 );
input VAR5;
output VAR3;
VAR2 VAR1(.VAR5(VAR5),.VAR3(VAR3));
VAR2 VAR4(.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
efabless/openlane | designs/blabla/src/blabla.v | 23,078 | module MODULE2(
input wire clk,
input wire VAR21,
input wire VAR69,
input wire VAR23,
input wire [255 : 0] VAR13,
input wire VAR59,
input wire [63 : 0] VAR118,
input wire [63 : 0] VAR34,
input wire [4 : 0] VAR37,
input wire [511 : 0] VAR24,
output wire ready,
output wire [511 : 0] VAR110,
output wire VAR66
);
localpara... | apache-2.0 |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/fifo_w8_d2_A.v | 2,982 | module MODULE1 (
clk,
VAR4,
VAR22,
VAR17,
VAR13);
parameter VAR3 = 32'd8;
parameter VAR15 = 32'd1;
parameter VAR27 = 2'd2;
input clk;
input [VAR3-1:0] VAR4;
input VAR22;
input [VAR15-1:0] VAR17;
output [VAR3-1:0] VAR13;
reg[VAR3-1:0] VAR2 [0:VAR27-1];
integer VAR6;
always @ (posedge clk)
begin
if (VAR22)
begin
for (VAR... | mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/vfabric_zextend.v | 1,490 | module MODULE1(VAR6, reset,
VAR9, VAR4, VAR8,
VAR5, VAR1, VAR7);
parameter VAR3 = 32;
parameter VAR2 = 64;
input VAR6, reset;
input [VAR3-1:0] VAR9;
input VAR4;
output VAR8;
output [VAR2-1:0] VAR5;
input VAR1;
output VAR7;
assign VAR5 = {{VAR2{1'b0}}, VAR9[VAR3-1:0]};
assign VAR8 = VAR1;
assign VAR7 = VAR4;
endmodule | mit |
lbl-cal/StanfordNoC | router/src/clib/c_matrix_arbiter.v | 4,845 | module MODULE1
(clk, reset, VAR24, VAR14, VAR36, VAR35, VAR12);
parameter VAR17 = 32;
parameter VAR21 = 1;
parameter VAR4 = VAR23;
input clk;
input reset;
input VAR24;
input [0:VAR21*VAR17-1] VAR14;
output [0:VAR21*VAR17-1] VAR36;
wire [0:VAR21*VAR17-1] VAR36;
output [0:VAR17-1] VAR35;
wire [0:VAR17-1] VAR35;
input VAR... | bsd-2-clause |
ffu/DSA-3.2.2 | usrp/fpga/sdr_lib/io_pins.v | 2,246 | module MODULE1
( inout wire [15:0] VAR20, inout wire [15:0] VAR5, inout wire [15:0] VAR14, inout wire [15:0] VAR1,
input wire [15:0] VAR2, input wire [15:0] VAR17, input wire [15:0] VAR4, input wire [15:0] VAR7,
input VAR19, input VAR8, input VAR21,
input [6:0] VAR9, input [31:0] VAR26, input VAR3);
reg [15:0] VAR15,VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4/sky130_fd_sc_hdll__or4.pp.blackbox.v | 1,316 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR3 ,
VAR9 ,
VAR4 ,
VAR6,
VAR8,
VAR2 ,
VAR7
);
output VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR4 ;
input VAR6;
input VAR8;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
q3k/q3kmips | rtl/verilog/qm_icache.v | 6,215 | module MODULE1(
input wire [31:0] address,
input wire reset,
input wire clk,
output reg VAR22,
output reg VAR23,
output reg [31:0] VAR19,
input wire enable,
output wire VAR17, output reg VAR15,
output reg [2:0] VAR20,
output reg [5:0] VAR14,
output reg [29:0] VAR16,
input wire VAR26,
input wire VAR11,
output wire VAR4,... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a_4.v | 2,348 | module MODULE2 (
VAR4 ,
VAR10 ,
VAR6 ,
VAR3 ,
VAR8 ,
VAR9,
VAR2,
VAR1 ,
VAR7
);
output VAR4 ;
input VAR10 ;
input VAR6 ;
input VAR3 ;
input VAR8 ;
input VAR9;
input VAR2;
input VAR1 ;
input VAR7 ;
VAR5 VAR11 (
.VAR4(VAR4),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9434_v1_00_a/hdl/verilog/axi_ad9434_channel.v | 5,593 | module MODULE1 (
VAR58,
VAR42,
VAR53,
VAR10,
VAR22,
VAR17,
VAR30,
VAR19,
VAR29,
VAR31,
VAR43,
VAR55,
VAR1,
VAR16,
VAR41,
VAR2);
input VAR58;
input VAR42;
input [47:0] VAR53;
input VAR10;
output [63:0] VAR22;
output VAR17;
output VAR30;
output VAR19;
input VAR29;
input VAR31;
input VAR43;
input VAR55;
input [13:0] VAR1;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3/sky130_fd_sc_ls__nor3.symbol.v | 1,308 | module MODULE1 (
input VAR7,
input VAR3,
input VAR2,
output VAR1
);
supply1 VAR8;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/byte_enable_generator.v | 30,223 | module MODULE2 (
clk,
reset,
VAR33,
VAR19,
VAR2,
VAR7,
VAR35
);
parameter VAR23 = 4;
input clk;
input reset;
input VAR33; input [VAR23-1:0] VAR19; output wire VAR2;
output wire [VAR23-1:0] VAR7; input VAR35;
generate
if (VAR23 == 1) begin
assign VAR7 = VAR19;
assign VAR2 = VAR35;
end
else if (VAR23 == 2)
begin
MODULE4 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4b/sky130_fd_sc_ls__and4b.pp.symbol.v | 1,324 | module MODULE1 (
input VAR2 ,
input VAR7 ,
input VAR9 ,
input VAR4 ,
output VAR3 ,
input VAR5 ,
input VAR6,
input VAR8,
input VAR1
);
endmodule | apache-2.0 |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/b2b/src/aur1_sym_dec.v | 19,061 | module MODULE1
(
VAR57,
VAR9,
VAR54,
VAR52,
VAR15,
VAR3,
VAR32,
VAR28,
VAR10,
VAR53,
VAR36,
VAR19,
VAR7,
VAR27,
VAR5,
VAR40
);
parameter VAR41 = 4'hb;
parameter VAR6 = 4'hc;
parameter VAR8 = 4'h4;
parameter VAR64 = 4'ha;
parameter VAR61 = 4'h2;
parameter VAR31 = 4'hc;
parameter VAR34 = 4'hb;
parameter VAR24 = 4'h5;
par... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/top/mem_bipo_2p.v | 14,588 | module MODULE1 (
clk ,
VAR32 ,
VAR52 ,
VAR56 ,
VAR23 ,
VAR76 ,
VAR64 ,
VAR5 ,
VAR27 ,
VAR18 ,
VAR14 ,
VAR48 ,
VAR63
);
localparam VAR65 = 2'b00,
VAR55 = 2'b01,
VAR38 = 2'b10,
VAR68 = 2'b11;
input clk ; input VAR32 ; input VAR52 ; input [1:0] VAR56 ; input [3:0] VAR23 ; input [3:0] VAR76 ; input [VAR73*16-1:0] VAR64 ; i... | gpl-3.0 |
zhangly/azpr_cpu | rtl/cpu/rtl/cpu.v | 16,261 | module MODULE1 (
input wire clk, input wire clk, input wire reset,
input wire [VAR75] VAR7, input wire VAR61, input wire VAR37, output wire VAR19, output wire [VAR26] VAR47, output wire VAR34, output wire VAR93, output wire [VAR75] VAR88, input wire [VAR75] VAR21, input wire VAR112, input wire VAR118, output wire VAR66... | mit |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/clk_gen_83M/example_design/clk_gen_83M_exdes.v | 5,556 | module MODULE1
parameter VAR2 = 100
)
( input VAR4,
input VAR7,
output [3:1] VAR15,
input VAR11,
output VAR19
);
localparam VAR21 = 16;
localparam VAR9 = 3;
genvar VAR13;
wire VAR18 = !VAR19 || VAR11 || VAR7;
reg [VAR9:1] VAR6;
reg [VAR9:1] VAR16;
reg [VAR9:1] VAR20;
reg [VAR9:1] VAR1;
wire [VAR9:1] VAR22;
wire [VAR9:1... | gpl-2.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v | 2,635 | module MODULE1;
parameter VAR20 = 750*2;
reg [31:0] VAR4;
reg [19:0] VAR21;
reg VAR15, VAR9, VAR17, VAR18,VAR3;
wire [31:0] VAR14,VAR16,VAR13,VAR22,in;
VAR1 VAR11(in,VAR4,VAR21,VAR15, VAR9, VAR17, VAR18,VAR3, VAR14,VAR16,VAR13,VAR22);
reg [4:0] VAR8;
reg [3:0] VAR7;
reg VAR19,VAR10;
wire [31:0] VAR23;
wire [3:0] VAR6;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp.behavioral.pp.v | 2,513 | module MODULE1 (
VAR5 ,
VAR25 ,
VAR7 ,
VAR13 ,
VAR18 ,
VAR12,
VAR17,
VAR20 ,
VAR2
);
output VAR5 ;
input VAR25 ;
input VAR7 ;
input VAR13 ;
input VAR18 ;
input VAR12;
input VAR17;
input VAR20 ;
input VAR2 ;
wire VAR24 ;
wire VAR16 ;
reg VAR26 ;
wire VAR4 ;
wire VAR14 ;
wire VAR10 ;
wire VAR9 ;
wire VAR6;
wire VAR11;
wi... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_mux_4to2/sky130_fd_sc_lp__udp_mux_4to2.symbol.v | 1,327 | module MODULE1 (
input VAR1,
input VAR4,
input VAR7,
input VAR3,
output VAR5 ,
input VAR6,
input VAR2
);
endmodule | apache-2.0 |
eda-globetrotter/PicenoDecoders | viterbi/syn/src/decoder.v | 22,008 | module MODULE3 (VAR115, VAR73, VAR85, VAR50, VAR106, VAR87);
output [3:0] VAR115;
output VAR73;
input [3:0] VAR85;
input [1:0] VAR50;
input [3:0] VAR106;
input [1:0] VAR87;
reg [3:0] VAR115;
reg VAR73;
reg [3:0] VAR47;
reg [3:0] VAR11;
reg [4:0] VAR121;
reg [4:0] VAR116;
parameter VAR51 = 4'd15;
always @ (VAR85 or VAR5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbp/sky130_fd_sc_ls__sdfbbp.functional.pp.v | 2,572 | module MODULE1 (
VAR22 ,
VAR10 ,
VAR24 ,
VAR11 ,
VAR14 ,
VAR2 ,
VAR12 ,
VAR25,
VAR21 ,
VAR13 ,
VAR1 ,
VAR19
);
output VAR22 ;
output VAR10 ;
input VAR24 ;
input VAR11 ;
input VAR14 ;
input VAR2 ;
input VAR12 ;
input VAR25;
input VAR21 ;
input VAR13 ;
input VAR1 ;
input VAR19 ;
wire VAR8 ;
wire VAR20 ;
wire VAR16 ;
wire... | apache-2.0 |
bunnie/novena-sd-fpga | novena-sd.srcs/sources_1/imports/dbuf_ddr3_reader.v | 1,977 | module MODULE1 (
input wire [15:0] din,
output wire [15:0] dout,
input wire clk,
input wire reset,
input wire VAR5,
input wire [1:0] VAR17,
input wire [18:16] VAR16,
input wire VAR9,
input wire VAR2,
input wire VAR15,
output wire VAR1,
);
reg VAR13;
reg VAR14;
reg VAR12;
reg [18:0] VAR8;
reg [15:0] VAR11;
reg [15:0] VA... | apache-2.0 |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0.v | 5,661 | module MODULE1 (
input wire clk, input wire VAR14, output wire [26:0] VAR6, output wire [3:0] VAR13, output wire VAR10, input wire [31:0] VAR7, input wire VAR26, output wire VAR9, output wire [31:0] VAR23, output wire VAR25, output wire [19:0] VAR12, output wire VAR17, input wire [31:0] VAR15, input wire VAR20, input w... | gpl-2.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_s_r_channel.v | 25,610 | module MODULE1
parameter VAR149 = 32'hffffffff,
parameter VAR160 = 32'h00000000,
parameter VAR173 = 1 ,
parameter VAR26 = 0 ,
parameter VAR93 = 1 ,
parameter VAR9 = 8 ,
parameter VAR76 = 32 ,
parameter VAR145 = 1 ,
parameter VAR114 = 0
) (
input VAR151 ,
input VAR121 ,
input [VAR93-1:0] VAR74 ,
input [31:0] VAR118 ,
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fa/sky130_fd_sc_hd__fa.behavioral.pp.v | 3,007 | module MODULE1 (
VAR23,
VAR17 ,
VAR22 ,
VAR1 ,
VAR19 ,
VAR28,
VAR15,
VAR6 ,
VAR25
);
output VAR23;
output VAR17 ;
input VAR22 ;
input VAR1 ;
input VAR19 ;
input VAR28;
input VAR15;
input VAR6 ;
input VAR25 ;
wire VAR7 ;
wire VAR31 ;
wire VAR11 ;
wire VAR24 ;
wire VAR3 ;
wire VAR8 ;
wire VAR2 ;
wire VAR4;
wire VAR26 ;
w... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111o/sky130_fd_sc_hs__a2111o.functional.v | 1,962 | module MODULE1 (
VAR9,
VAR4,
VAR16 ,
VAR15 ,
VAR6 ,
VAR5 ,
VAR12 ,
VAR11
);
input VAR9;
input VAR4;
output VAR16 ;
input VAR15 ;
input VAR6 ;
input VAR5 ;
input VAR12 ;
input VAR11 ;
wire VAR12 VAR8 ;
wire VAR13 ;
wire VAR14;
and VAR10 (VAR8 , VAR15, VAR6 );
or VAR2 (VAR13 , VAR12, VAR5, VAR8, VAR11 );
VAR3 VAR7 (VAR14... | apache-2.0 |
DSDL2016/project2 | main_module.v | 1,465 | module MODULE1
(
VAR1, output
);
input VAR1;
output output;
endmodule | mit |
amontefusco/gnuradio-amontefusco | gr-sounder/src/fpga/lib/lfsr.v | 1,313 | module MODULE1(VAR7,VAR2,VAR3,VAR5,VAR1,VAR6);
parameter VAR9 = 16;
input VAR7;
input VAR2;
input VAR3;
input VAR5;
input [VAR9-1:0] VAR1;
output VAR6;
reg [VAR9-1:0] VAR8;
wire VAR4 = ^(VAR8 & VAR1);
always @(posedge VAR7)
if (VAR2 | ~VAR3)
VAR8 <= 1;
else
if (VAR5)
VAR8 <= {VAR8[VAR9-2:0],VAR4};
assign VAR6 = VAR8[0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2i/sky130_fd_sc_hd__mux2i.blackbox.v | 1,291 | module MODULE1 (
VAR7 ,
VAR4,
VAR5,
VAR3
);
output VAR7 ;
input VAR4;
input VAR5;
input VAR3 ;
supply1 VAR2;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii/altera_tse_xcvr_resync.v | 3,489 | module MODULE1 #(
parameter VAR1 = 2, parameter VAR2 = 1, parameter VAR9 = 0 ) (
input wire clk,
input wire [VAR2-1:0] VAR13,
output wire [VAR2-1:0] VAR7
);
localparam VAR8 = (VAR1 > 0) ? VAR1 : 1;
genvar VAR12;
generate begin
for(VAR12=0;VAR12<VAR2;VAR12=VAR12+1) begin : VAR11
wire din; reg [VAR8-1:0] VAR5 = {VAR8{1'b... | apache-2.0 |
nczempin/NICNAC16 | src/mojo_top.v | 1,132 | module MODULE1(
input clk,
input VAR7,
input VAR10,
output[7:0]VAR2,
output[7:0]VAR5
);
wire rst = ~VAR7;
wire VAR6;
wire VAR4;
wire VAR13;
wire VAR8;
wire [15:0] VAR15;
wire [15:0] VAR14;
wire [15:0] VAR11;
assign VAR5 = VAR11[7:0];
VAR3 VAR1 (
.VAR9(clk),
.VAR12(VAR10),
.VAR6( VAR6 ),
.VAR4( VAR4 ),
.VAR13( VAR13 ),
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_2.v | 2,463 | module MODULE2 (
VAR5 ,
VAR11,
VAR2,
VAR9 ,
VAR8 ,
VAR10,
VAR3,
VAR4 ,
VAR1
);
output VAR5 ;
input VAR11;
input VAR2;
input VAR9 ;
input VAR8 ;
input VAR10;
input VAR3;
input VAR4 ;
input VAR1 ;
VAR6 VAR7 (
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfsbp/sky130_fd_sc_ms__dfsbp.functional.v | 1,737 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR13 ,
VAR10 ,
VAR1
);
output VAR7 ;
output VAR5 ;
input VAR13 ;
input VAR10 ;
input VAR1;
wire VAR11;
wire VAR12 ;
not VAR9 (VAR12 , VAR1 );
VAR6 VAR8 VAR3 (VAR11 , VAR10, VAR13, VAR12 );
buf VAR2 (VAR7 , VAR11 );
not VAR4 (VAR5 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21oi/sky130_fd_sc_hd__a21oi_1.v | 2,261 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR8 ,
VAR6 ,
VAR10,
VAR7,
VAR2 ,
VAR9
);
output VAR1 ;
input VAR4 ;
input VAR8 ;
input VAR6 ;
input VAR10;
input VAR7;
input VAR2 ;
input VAR9 ;
VAR3 VAR5 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32ai/sky130_fd_sc_ls__o32ai.pp.blackbox.v | 1,425 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR5 ,
VAR2 ,
VAR4 ,
VAR10 ,
VAR1,
VAR3,
VAR7 ,
VAR9
);
output VAR6 ;
input VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR10 ;
input VAR1;
input VAR3;
input VAR7 ;
input VAR9 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_4.functional.pp.v | 1,416 | module MODULE1( VAR2, VAR10, VAR7, VAR4, VAR12, VAR11, VAR16 );
input VAR4, VAR12, VAR2, VAR7;
inout VAR11, VAR16;
output VAR10;
wire VAR13;
not VAR5( VAR13, VAR4 );
wire VAR9;
not VAR3( VAR9, VAR12 );
wire VAR6;
not VAR15( VAR6, VAR2 );
wire VAR14;
not VAR8( VAR14, VAR7 );
or VAR1( VAR10, VAR13, VAR9, VAR6, VAR14 );
e... | apache-2.0 |
manu3193/TextEditor | SVN/Altera_UP_PS2_Data_In.v | 5,136 | module MODULE1 (
clk,
reset,
VAR8,
VAR12,
VAR1,
VAR7,
VAR16,
VAR6,
VAR2 );
input clk;
input reset;
input VAR8;
input VAR12;
input VAR1;
input VAR7;
input VAR16;
output reg [7:0] VAR6;
output reg VAR2;
localparam VAR14 = 3'h0,
VAR15 = 3'h1,
VAR11 = 3'h2,
VAR9 = 3'h3,
VAR3 = 3'h4;
reg [3:0] VAR5;
reg [7:0] VAR13;
reg [2:... | mit |
wyvernSemi/lm32fpga | HDL/rtl/address_decode.v | 4,300 | module MODULE1 (
VAR20,
VAR10,
VAR6,
VAR11,
VAR17,
VAR19,
VAR4,
VAR2,
VAR5,
VAR21,
VAR8,
VAR23,
VAR13,
VAR15,
VAR7,
VAR12
);
input VAR20;
input VAR10;
input [31:0] VAR6;
input VAR11;
input VAR17;
input VAR19;
input VAR4;
input [7:0] VAR2;
input [31:0] VAR5;
input [31:0] VAR21;
output VAR8;
output VAR23;
output VAR13;
o... | gpl-3.0 |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/painter_chooser.v | 1,381 | module MODULE1(
input [9:0] hc,
input [9:0] VAR7,
input [9:0] VAR12,
input [8:0] VAR5,
input [7:0] VAR2,
input [7:0] VAR10,
output reg [9:0] VAR8,
output reg [8:0] VAR6,
output reg [4:0] VAR1,
output reg [7:0] VAR11
);
parameter [7:0]VAR13 = 144; parameter [4:0]VAR9 = 31; parameter [7:0]VAR3 = 8'b00000000;
parameter [7... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22ai/sky130_fd_sc_ms__o22ai_2.v | 2,352 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR5 ,
VAR1 ,
VAR8 ,
VAR11,
VAR2,
VAR3 ,
VAR10
);
output VAR9 ;
input VAR7 ;
input VAR5 ;
input VAR1 ;
input VAR8 ;
input VAR11;
input VAR2;
input VAR3 ;
input VAR10 ;
VAR4 VAR6 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR3(VAR3),
.VA... | apache-2.0 |
mosukiton/mipsprocessor | Mips_single_cycle.srcs/sources_1/new/instructionfetch.v | 4,270 | module MODULE1(
output [31:0] VAR9,
output [31:0] VAR14,
input [31:0] VAR6,
input [27:0] VAR4,
input clk, reset, VAR13, VAR11
);
wire [31:0] VAR12;
wire [1:0] VAR7;
reg [31:0] VAR1, VAR10;
VAR3 VAR5(
.VAR2( VAR1 ),
.VAR8( VAR14 )
);
assign VAR7 = {VAR13, VAR11};
always @ (VAR7 or posedge reset or posedge clk) begin
if(... | gpl-3.0 |
osrf/wandrr | firmware/motor_controller/fpga/fake_eth_phy.v | 19,432 | module MODULE1
(
input VAR8,
input VAR22,
input VAR38,
input [7:0] VAR4,
input VAR18,
input VAR25,
input VAR3,
input VAR26,
output VAR34,
output VAR33,
output reg [7:0] VAR29,
output VAR24,
output reg VAR23,
input VAR19,
input VAR37,
inout VAR36,
input VAR9, output reg VAR21 );
parameter VAR11="VAR30.VAR5";
parameter V... | apache-2.0 |
drichmond/riffa | fpga/xilinx/vc709/VC709_Gen2x8If128/hdl/VC709_Gen2x8If128.v | 26,211 | module MODULE1
parameter VAR98 = 8,
parameter VAR58 = 128,
parameter VAR128 = 256,
parameter VAR29 = 6
)
(output [(VAR98 - 1) : 0] VAR64,
output [(VAR98 - 1) : 0] VAR2,
input [(VAR98 - 1) : 0] VAR144,
input [(VAR98 - 1) : 0] VAR52,
output [7:0] VAR34,
input VAR18,
input VAR134,
input VAR190
);
wire VAR5;
wire VAR137;
w... | bsd-3-clause |
olajep/oh | src/adi/hdl/library/common/ad_perfect_shuffle.v | 2,655 | module MODULE1 #(
parameter VAR8 = 2,
parameter VAR10 = 2,
parameter VAR6 = 8
) (
input [VAR8*VAR10*VAR6-1:0] VAR2,
output [VAR8*VAR10*VAR6-1:0] VAR11
);
generate
genvar VAR9;
genvar VAR5;
for (VAR9 = 0; VAR9 < VAR8; VAR9 = VAR9 + 1) begin: VAR1
for (VAR5 = 0; VAR5 < VAR10; VAR5 = VAR5 + 1) begin: VAR4
localparam VAR7 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211ai/sky130_fd_sc_hd__o211ai.pp.symbol.v | 1,380 | module MODULE1 (
input VAR2 ,
input VAR1 ,
input VAR6 ,
input VAR8 ,
output VAR3 ,
input VAR4 ,
input VAR7,
input VAR9,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor3/sky130_fd_sc_hd__xor3.blackbox.v | 1,289 | module MODULE1 (
VAR4,
VAR6,
VAR5,
VAR2
);
output VAR4;
input VAR6;
input VAR5;
input VAR2;
supply1 VAR7;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_ddr_command_fifo.v | 16,174 | module MODULE1 #
(
parameter VAR13 = "VAR101",
parameter integer VAR51 = 0,
parameter integer VAR9 = 0,
parameter integer VAR34 = 5, parameter integer VAR6 = 64 )
(
input wire VAR2, input wire VAR10, output wire VAR68, input wire [VAR6-1:0] VAR22, input wire VAR86, output wire VAR38, output wire [VAR6-1:0] VAR78, outpu... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.behavioral.v | 1,108 | module MODULE1( VAR4, VAR1 );
input VAR4;
output VAR1;
VAR2 VAR3(.VAR4(VAR4),.VAR1(VAR1));
VAR2 VAR5(.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/datapath.v | 3,773 | module MODULE1 (
VAR1,
VAR15,
VAR18,
VAR14,
VAR3,
VAR10,
VAR6,
VAR7,
VAR22,
VAR19,
VAR2,
VAR27,
VAR25,
VAR13,
VAR8,
VAR23,
VAR4,
VAR16
);
parameter VAR28 = 32;
parameter VAR20 = VAR28 / 8;
parameter VAR5 = 2;
input VAR1;
input VAR15;
input [VAR28-1:0] VAR18;
input [VAR20-1:0] VAR14;
input [VAR5-1:0] VAR3;
output [VAR28... | lgpl-3.0 |
rqou/openfpga | hdl/xc2c-model/XC2CDevice.v | 12,782 | module MODULE1(
VAR2, VAR20, VAR11, VAR1,
VAR17, VAR13, VAR18, VAR7,
VAR3, VAR9
);
parameter VAR15 = 32;
parameter VAR4 = "VAR6";
function integer VAR16;
input[15:0] VAR8;
begin
case(VAR8)
32: VAR16 = 260;
64: VAR16 = 274;
128: VAR16 = 752;
256: VAR16 = 1364;
384: VAR16 = 1868;
512: VAR16 = 1980;
default: VAR16 = 0;
en... | lgpl-2.1 |
asicguy/gplgpu | hdl/altera_project/fifo_32x512a/fifo_32x512a_bb.v | 5,683 | module MODULE1 (
VAR10,
VAR3,
VAR1,
VAR7,
VAR4,
VAR5,
VAR9,
VAR2,
VAR8,
VAR6);
input VAR10;
input [31:0] VAR3;
input VAR1;
input VAR7;
input VAR4;
input VAR5;
output [31:0] VAR9;
output VAR2;
output VAR8;
output [9:0] VAR6;
endmodule | gpl-3.0 |
bnossum/uart_ice40 | src/uartICE40hl.v | 6,698 | module MODULE4
wire VAR10; wire VAR7; MODULE3 MODULE2 (
.VAR14 (VAR14),
.VAR21 (VAR21),
.clk (clk),
.VAR12 (VAR12),
.VAR10 (VAR10),
.VAR8 (VAR8[7:0]));
MODULE1 MODULE3 (
.VAR26 (VAR26),
.VAR9 (VAR9[1:0]),
.VAR19 (VAR19[7:0]),
.clk (clk),
.VAR7 (VAR7),
.VAR11 (VAR11));
MODULE5 #( .VAR29(VAR29),
.VAR17(VAR17))
VAR22
(
.V... | mit |
vvk/sysrek | skin_color_segm/sobel.v | 3,567 | module MODULE1 #(
parameter [9:0] VAR5 = 83 )(
input clk,
input VAR31,
input rst,
input [7:0] VAR14,
input VAR17,
input VAR11,
input VAR4,
output [7:0] VAR21,
output VAR12,
output VAR6,
output VAR22
);
wire [10:0] VAR24;
reg [10:0] VAR25 [2:0];
wire [10:0] VAR9;
reg [10:0] VAR7 [2:0];
wire [10:0] VAR16;
reg [10:0] VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai_m.v | 2,349 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR8 ,
VAR7,
VAR11,
VAR10 ,
VAR2
);
output VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR7;
input VAR11;
input VAR10 ;
input VAR2 ;
VAR1 VAR9 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR10(VAR10),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbp/sky130_fd_sc_ls__sdfbbp.behavioral.pp.v | 3,364 | module MODULE1 (
VAR36 ,
VAR8 ,
VAR35 ,
VAR26 ,
VAR29 ,
VAR33 ,
VAR3 ,
VAR16,
VAR22 ,
VAR11 ,
VAR32 ,
VAR38
);
output VAR36 ;
output VAR8 ;
input VAR35 ;
input VAR26 ;
input VAR29 ;
input VAR33 ;
input VAR3 ;
input VAR16;
input VAR22 ;
input VAR11 ;
input VAR32 ;
input VAR38 ;
wire VAR25 ;
wire VAR30 ;
wire VAR4 ;
reg ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221oi/sky130_fd_sc_lp__a221oi_1.v | 2,457 | module MODULE2 (
VAR12 ,
VAR5 ,
VAR3 ,
VAR6 ,
VAR8 ,
VAR9 ,
VAR2,
VAR10,
VAR11 ,
VAR4
);
output VAR12 ;
input VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR2;
input VAR10;
input VAR11 ;
input VAR4 ;
VAR7 VAR1 (
.VAR12(VAR12),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(V... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pipe_clock.v | 24,527 | module MODULE1 #
(
parameter VAR55 = "VAR42", parameter VAR143 = "VAR42", parameter VAR84= "VAR42", parameter VAR97 = 1, parameter VAR109 = 3, parameter VAR133 = 0, parameter VAR46 = 2, parameter VAR60 = 2, parameter VAR48 = 1, parameter VAR161 = 0
)
(
input VAR145,
input VAR13,
input [VAR97-1:0] VAR12,
input VAR130,
i... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_2.behavioral.v | 1,245 | module MODULE1( VAR5, VAR6, VAR4, VAR7 );
input VAR5, VAR6, VAR4;
output VAR7;
VAR3 VAR1(.VAR5(VAR5),.VAR6(VAR6),.VAR4(VAR4),.VAR7(VAR7));
VAR3 VAR2(.VAR5(VAR5),.VAR6(VAR6),.VAR4(VAR4),.VAR7(VAR7)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3b/sky130_fd_sc_hdll__nand3b.symbol.v | 1,321 | module MODULE1 (
input VAR6,
input VAR7 ,
input VAR3 ,
output VAR4
);
supply1 VAR5;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
Siliciumer/DOS-Mario-FPGA | sources/draw_background.v | 3,105 | module MODULE1 (
input wire [9:0] VAR26,
input wire VAR16,
input wire [9:0] VAR8,
input wire VAR14,
input wire VAR7,
input wire [9:0] VAR24,
input wire clk,
input wire rst,
output reg [9:0] VAR13,
output reg VAR5,
output reg [9:0] VAR29,
output reg VAR1,
output reg [23:0] VAR4,
output reg VAR22
);
localparam VAR18 = 24... | mit |
andykarpov/radio-86rk-wxeda | src/keyboard/rk_kbd.v | 6,097 | module MODULE1(
input clk,
input reset,
inout VAR11,
inout VAR16,
input[7:0] addr,
output reg[7:0] VAR2,
output[2:0] VAR3);
reg VAR14;
reg[9:0] VAR18;
reg[2:0] VAR17;
assign VAR3 = VAR17[2:0];
VAR10 VAR6(
.VAR13(reset), .VAR7(clk),
.VAR8(VAR11), .VAR1(VAR16),
.VAR4(VAR14), .VAR12(VAR18)
);
reg[7:0] VAR9[7:0];
always @(... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/edfxtp/sky130_fd_sc_ls__edfxtp.pp.blackbox.v | 1,363 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR7 ,
VAR5 ,
VAR3,
VAR1,
VAR8 ,
VAR4
);
output VAR6 ;
input VAR2 ;
input VAR7 ;
input VAR5 ;
input VAR3;
input VAR1;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr.behavioral.v | 1,493 | module MODULE1 (
VAR8,
VAR4
);
output VAR8;
input VAR4;
supply1 VAR9 ;
supply0 VAR1 ;
supply1 VAR5;
supply1 VAR7 ;
supply0 VAR6 ;
wire VAR2;
buf VAR3 (VAR2, VAR4 );
buf VAR10 (VAR8 , VAR2 );
endmodule | apache-2.0 |
joaocarlos/udlx-verilog | rtl/execute/execute_address_calculate.v | 6,287 | module MODULE1
parameter VAR51 = 32,
parameter VAR53 = 32,
parameter VAR10 = 32,
parameter VAR62 = 6,
parameter VAR31 = 6,
parameter VAR30 = 5,
parameter VAR65 = 26
)
(
input clk,
input VAR54,
input en,
input [VAR62-1:0] VAR36,
input [VAR31-1:0] VAR64,
input [VAR51-1:0] VAR26,
input [VAR51-1:0] VAR7,
input [VAR30-1:0] ... | lgpl-3.0 |
glennchid/font5-firmware | src/verilog/synthesis/MuxModule_old (4).v | 2,006 | module MODULE1(
output reg VAR13,
input VAR17,
input clk,
input [7:0] VAR16,
input [7:0] VAR9,
input [1:0] VAR6,
input [3:0] VAR1,
input [7:0] VAR12,
output reg VAR10
);
reg [4:0] VAR11=0;
VAR5 VAR13=0;
reg [7:0] VAR15;
reg [7:0] VAR4=0;
reg [7:0] VAR14=0;
always @ (posedge clk) begin
VAR10<=VAR15==VAR9+1|| VAR15== VAR... | gpl-3.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_or.v | 4,319 | module MODULE1 #
(
parameter VAR8 = "VAR9"
)
(
input wire VAR3,
input wire VAR2,
output wire VAR5
);
generate
if ( VAR8 == "VAR12" ) begin : VAR13
assign VAR5 = VAR3 | VAR2;
end else begin : VAR4
wire VAR11;
assign VAR11 = ~VAR2;
VAR10 VAR7
(
.VAR14 (VAR5),
.VAR1 (VAR3),
.VAR6 (1'b1),
.VAR2 (VAR11)
);
end
endgenerate
e... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_2.behavioral.pp.v | 2,990 | module MODULE1( VAR8, VAR7, VAR18, VAR11, VAR13, VAR6 );
input VAR7, VAR8, VAR18;
inout VAR13, VAR6;
output VAR11;
reg VAR12;
VAR25 VAR10(.VAR8(VAR8),.VAR7(VAR7),.VAR18(VAR18),.VAR11(VAR11),.VAR13(VAR13),.VAR6(VAR6),.VAR12(VAR12));
VAR25 VAR4(.VAR8(VAR8),.VAR7(VAR7),.VAR18(VAR18),.VAR11(VAR11),.VAR13(VAR13),.VAR6(VAR6)... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_sctrdq_fifo.v | 6,122 | module MODULE1 (
VAR16, dout, VAR57,
VAR18, din, VAR55, VAR21, VAR47, VAR15, clk, VAR60, VAR10,
VAR28, VAR46, VAR7
);
input VAR18;
input [137:0] din;
output VAR16;
input VAR55;
input VAR21;
input VAR47;
input VAR15;
output [137:0] dout;
output VAR57;
input clk;
input VAR60;
input VAR10;
input VAR28; input VAR46;
input ... | gpl-2.0 |
omicronns/studies-sys-rek | lab4/zlozony/ipcore_dir/sum_18_13/sum_18_13.v | 34,334 | module MODULE1 (
clk, VAR283, VAR45, VAR87, VAR152
);
input clk;
input VAR283;
input [17 : 0] VAR45;
input [12 : 0] VAR87;
output [18 : 0] VAR152;
wire \VAR20/VAR176 ;
wire \VAR20/VAR61 ;
wire \VAR20/VAR248 ;
wire \VAR20/VAR245 ;
wire \VAR20/VAR224 ;
wire \VAR20/VAR361 ;
wire \VAR20/VAR261 ;
wire \VAR20/VAR317 ;
wire \... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkinvkapwr/sky130_fd_sc_hd__lpflow_clkinvkapwr_4.v | 2,261 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR4,
VAR7 ,
VAR2 ,
VAR6 ,
VAR5
);
output VAR8 ;
input VAR9 ;
input VAR4;
input VAR7 ;
input VAR2 ;
input VAR6 ;
input VAR5 ;
VAR3 VAR1 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR8,
VAR9
);
output VAR8;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31a/sky130_fd_sc_ms__o31a_4.v | 2,322 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR7 ,
VAR1 ,
VAR3 ,
VAR9,
VAR2,
VAR8 ,
VAR11
);
output VAR10 ;
input VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR9;
input VAR2;
input VAR8 ;
input VAR11 ;
VAR4 VAR5 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR8(VAR8),
.VA... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type1_block.v | 1,139 | module MODULE1
(
VAR3,
VAR2
);
input signed [35:0] VAR3; output signed [35:0] VAR2;
wire signed [35:0] VAR1;
assign VAR1 = {VAR3[35], VAR3[35:1]};
assign VAR2 = VAR1;
endmodule | gpl-3.0 |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/usart.v | 22,767 | module MODULE1(
VAR80,
clk,
VAR72,
VAR108,
VAR38,
VAR83,
VAR49,
VAR59,
VAR5,
VAR93
);
input VAR80;
input clk;
input VAR72;
output VAR38;
output VAR108;
input VAR83;
wire [VAR71-1:0] VAR20;
reg VAR89;
reg [VAR71-1:0] VAR29;
reg VAR90;
output [VAR71-1:0] VAR93;
output reg [111:0] VAR49; output reg VAR59;
input [335:0] VA... | gpl-2.0 |
theapi/nand2tetris_fpga | hack/ip/qsys/qsys/synthesis/submodules/qsys_mm_interconnect_0_avalon_st_adapter.v | 6,146 | module MODULE1 #(
parameter VAR1 = 18,
parameter VAR6 = 0,
parameter VAR25 = 18,
parameter VAR3 = 0,
parameter VAR22 = 0,
parameter VAR15 = 0,
parameter VAR16 = 1,
parameter VAR13 = 1,
parameter VAR24 = 0,
parameter VAR17 = 18,
parameter VAR10 = 0,
parameter VAR9 = 1,
parameter VAR5 = 0,
parameter VAR20 = 1,
parameter ... | mit |
osrf/wandrr | firmware/motor_controller/fpga/foc.v | 10,462 | module MODULE1
(input VAR115,
input [47:0] VAR4,
input VAR163,
output [15:0] VAR67,
output [15:0] VAR148,
input [10:0] VAR140,
input [10:0] VAR127,
input [15:0] VAR57,
input signed [31:0] VAR70,
input [15:0] VAR36,
input [15:0] VAR162,
input [15:0] VAR120,
output signed [15:0] VAR150,
output signed [15:0] VAR25,
output... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcadc5/vc707/system_top.v | 13,728 | module MODULE1 (
VAR14,
VAR143,
VAR34,
VAR26,
VAR135,
VAR8,
VAR32,
VAR6,
VAR62,
VAR120,
VAR71,
VAR39,
VAR40,
VAR9,
VAR92,
VAR41,
VAR50,
VAR146,
VAR70,
VAR147,
VAR121,
VAR5,
VAR105,
VAR90,
VAR155,
VAR66,
VAR96,
VAR73,
VAR44,
VAR61,
VAR151,
VAR55,
VAR148,
VAR138,
VAR149,
VAR101,
VAR119,
VAR65,
VAR21,
VAR59,
VAR112,
VAR10... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s.functional.pp.v | 1,868 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR6,
VAR1,
VAR7 ,
VAR5
);
output VAR3 ;
input VAR8 ;
input VAR6;
input VAR1;
input VAR7 ;
input VAR5 ;
wire VAR11 ;
wire VAR4;
buf VAR9 (VAR11 , VAR8 );
VAR2 VAR10 (VAR4, VAR11, VAR6, VAR1);
buf VAR12 (VAR3 , VAR4 );
endmodule | apache-2.0 |
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