repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
tmatsuya/milkymist-ml401 | cores/minimac/rtl/minimac_rxfifo.v | 2,726 | module MODULE1(
input VAR22,
input VAR23,
input VAR24,
input [3:0] VAR33,
input VAR28,
input VAR15,
output VAR36,
input ack,
output VAR31,
output [7:0] VAR1,
output reg VAR6
);
wire [8:0] VAR20;
assign VAR31 = VAR20[8];
assign VAR1 = VAR20[7:0];
reg VAR11;
reg [3:0] VAR12;
reg [3:0] VAR32;
wire [8:0] VAR8 = {VAR11, VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufinv/sky130_fd_sc_hs__bufinv_16.v | 1,923 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR5,
VAR3
);
output VAR6 ;
input VAR1 ;
input VAR5;
input VAR3;
VAR2 VAR4 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR5;
supply0 VAR3;
VAR2 VAR4 (
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/iface/ip/mem_splitter/acl_iface_address_to_bankaddress.v | 1,906 | module MODULE1 #(
parameter integer VAR3 = 32, parameter integer VAR7 = 2, parameter integer VAR9 = VAR3-VAR1(VAR7)
)
(
input logic [VAR3-1:0] address,
output logic [VAR7-1:0] VAR8, output logic [VAR1(VAR7)-1:0] VAR2, output logic [VAR3-VAR1(VAR7)-1:0] VAR5
);
integer VAR4;
logic [VAR3:0] VAR6;
assign VAR6 = {1'b0,addr... | mit |
jotego/jt12 | hdl/jt12_single_acc.v | 1,990 | module MODULE1 #(parameter
VAR2=14, VAR9=16 )(
input clk,
input VAR7 ,
input [VAR2-1:0] VAR6,
input VAR5,
input VAR8,
output reg [VAR9-1:0] VAR12
);
reg signed [VAR9-1:0] VAR1, VAR4, VAR13;
reg VAR11;
wire [VAR9-1:0] VAR10 = { 1'b0, {(VAR9-1){1'b1}} }; wire [VAR9-1:0] VAR3 = { 1'b1, {(VAR9-1){1'b0}} };
always @(*) begi... | gpl-3.0 |
jhoward321/pacman | usb_system/synthesis/submodules/usb_system_cpu_mult_cell.v | 6,297 | module MODULE1 (
VAR41,
VAR37,
clk,
VAR36,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 31: 0] VAR41;
input [ 31: 0] VAR37;
input clk;
input VAR36;
wire [ 31: 0] VAR3;
wire [ 31: 0] VAR28;
wire [ 15: 0] VAR46;
wire VAR26;
assign VAR26 = ~VAR36;
VAR19 VAR8
(
.VAR35 (VAR26),
.VAR22 (clk),
.VAR10 (VAR41[15 : 0]),
.VAR18 (VAR37[... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probec_p/sky130_fd_sc_hd__probec_p.pp.blackbox.v | 1,270 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR4,
VAR5 ,
VAR1 ,
VAR2
);
output VAR3 ;
input VAR6 ;
input VAR4;
input VAR5 ;
input VAR1 ;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22o/sky130_fd_sc_hd__a22o.behavioral.v | 1,607 | module MODULE1 (
VAR5 ,
VAR14,
VAR10,
VAR6,
VAR12
);
output VAR5 ;
input VAR14;
input VAR10;
input VAR6;
input VAR12;
supply1 VAR9;
supply0 VAR11;
supply1 VAR16 ;
supply0 VAR15 ;
wire VAR4 ;
wire VAR8 ;
wire VAR1;
and VAR2 (VAR4 , VAR6, VAR12 );
and VAR13 (VAR8 , VAR14, VAR10 );
or VAR3 (VAR1, VAR8, VAR4);
buf VAR7 (VA... | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/iobs.v | 12,258 | module MODULE1 (
VAR31,
VAR26,
clk,
VAR49,
VAR47,
VAR53,
VAR1,
VAR44,
VAR25,
VAR39,
VAR23,
VAR17,
VAR56,
VAR48,
VAR43,
VAR6,
VAR38,
VAR42,
VAR57,
VAR74,
VAR5,
VAR76,
VAR73,
VAR24,
VAR7,
VAR70,
VAR32,
VAR33,
VAR11,
VAR14,
VAR29,
VAR67,
VAR51,
VAR27,
VAR22,
VAR21,
VAR46,
VAR2,
VAR18,
VAR13,
VAR9,
VAR10,
VAR72,
VAR30,
VAR... | lgpl-3.0 |
hongyunnchen/miaow | src/verilog/rtl/decode/PS_flops_wavepool_decode.v | 1,336 | module MODULE1 (
VAR18,
VAR8,
VAR6,
VAR9,
VAR19,
VAR10,
VAR7,
VAR1,
VAR22,
VAR11,
VAR20,
VAR13,
VAR15,
VAR3,
clk,
rst
);
input clk;
input rst;
input [31:0] VAR18;
input VAR8;
input [31:0] VAR6;
input [5:0] VAR9;
input [9:0] VAR19;
input [8:0] VAR10;
input [15:0] VAR7;
output [31:0] VAR1;
output VAR22;
output [31:0] VAR... | bsd-3-clause |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_static_cmdgen.v | 6,094 | module MODULE1
parameter VAR2 = 32'h12A00000,
parameter VAR19 = 32 ,
parameter VAR23 = 4 , parameter VAR22 = 3,
parameter VAR11 = 0,
parameter VAR8 = 0
) (
input VAR12 ,
input VAR24 ,
input VAR26 ,
input [7:0] VAR13 ,
input [9:0] VAR20,
input [31:0] VAR15 ,
input [31:0] VAR5 ,
output [127:0] VAR7 ,
output [VAR19-1:0] V... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_113.v | 1,427 | module MODULE1 (
VAR7,
VAR6
);
input [31:0] VAR7;
output [31:0]
VAR6;
wire [31:0]
VAR12,
VAR4,
VAR11,
VAR8,
VAR5,
VAR9,
VAR2;
assign VAR12 = VAR7;
assign VAR2 = VAR5 - VAR9;
assign VAR8 = VAR11 << 9;
assign VAR5 = VAR12 + VAR8;
assign VAR11 = VAR4 - VAR12;
assign VAR4 = VAR12 << 2;
assign VAR9 = VAR11 << 4;
assign VAR6... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfstp/sky130_fd_sc_hvl__sdfstp.pp.symbol.v | 1,501 | module MODULE1 (
input VAR4 ,
output VAR7 ,
input VAR1,
input VAR6 ,
input VAR10 ,
input VAR5 ,
input VAR9 ,
input VAR2 ,
input VAR8 ,
input VAR3
);
endmodule | apache-2.0 |
EliasLuiz/TCC | Leon3/lib/opencores/ge_1000baseX/ge_1000baseX_an.v | 17,490 | module MODULE1 #(
parameter VAR49 = 0
) (
input VAR62,
input reset,
input VAR75,
output reg [2:0] VAR64,
output reg [15:0] VAR51,
input [15:0] VAR9,
input VAR58,
input VAR25,
input VAR55,
input VAR20,
input VAR27,
input [2:0] VAR26,
input VAR42,
input VAR60,
input VAR59,
input VAR66,
input VAR67,
output reg VAR72,
inpu... | gpl-3.0 |
MarcoVogt/basil | firmware/modules/utils/bus_to_ip.v | 1,300 | module MODULE1
parameter VAR5 = 0,
parameter VAR12 = 0,
parameter VAR3 = 16,
parameter VAR11 = 8
)
(
input wire VAR16,
input wire VAR8,
input wire [VAR3-1:0] VAR2,
inout wire [VAR11-1:0] VAR7,
output wire VAR9,
output wire VAR6,
output wire [VAR3-1:0] VAR15,
output wire [VAR11-1:0] VAR4,
input wire [VAR11-1:0] VAR10
);... | bsd-3-clause |
ppnipuna/Network_Switch | rtl/switch.v | 27,366 | module MODULE6
(input wire VAR22, input wire clk, input wire VAR69, output reg VAR88);
always@(posedge clk or negedge VAR69)
if (~VAR69) VAR88 <= 1'b0;
else VAR88 <= VAR22;
endmodule
module MODULE5
(input wire VAR39, input wire VAR69, input wire VAR21, output wire VAR85);
wire VAR94;
MODULE6
MODULE1
( .clk (VAR39),
.VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221oi/sky130_fd_sc_hs__a221oi_1.v | 2,330 | module MODULE2 (
VAR6 ,
VAR9 ,
VAR2 ,
VAR1 ,
VAR3 ,
VAR7 ,
VAR10,
VAR4
);
output VAR6 ;
input VAR9 ;
input VAR2 ;
input VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR10;
input VAR4;
VAR5 VAR8 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR4(VAR4)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp.behavioral.pp.v | 2,551 | module MODULE1 (
VAR8,
VAR21 ,
VAR10,
VAR17 ,
VAR9,
VAR4,
VAR7 ,
VAR20
);
output VAR8;
input VAR21 ;
input VAR10;
input VAR17 ;
input VAR9;
input VAR4;
input VAR7 ;
input VAR20 ;
wire VAR24 ;
wire VAR16 ;
wire VAR18 ;
wire VAR25 ;
wire VAR1 ;
wire VAR13 ;
wire VAR19;
reg VAR11 ;
wire VAR2 ;
wire VAR22 ;
wire VAR23 ;
no... | apache-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/dds/dds_stub.v | 1,531 | module MODULE1(VAR1, VAR6, VAR7, VAR4, VAR3, VAR2, VAR5)
;
input VAR1;
input VAR6;
input [39:0]VAR7;
output VAR4;
output [31:0]VAR3;
output VAR2;
output [39:0]VAR5;
endmodule | gpl-2.0 |
monotone-RK/FACE | MCSoC-15/8-way_2-parallel/ise/ipcore_dir/dram/user_design/rtl/clocking/mig_7series_v1_9_tempmon.v | 15,167 | module MODULE1 #
(
parameter VAR38 = 100, parameter VAR14 = "VAR3", parameter VAR80 = 5000, parameter VAR46 = 10000000 )
(
input clk, input VAR19,
input rst, input [11:0] VAR12, output [11:0] VAR48 );
function integer VAR87 (input integer VAR5, input integer VAR89);
begin
VAR87 = (VAR5/VAR89) + (((VAR5%VAR89)>0) ? 1 : ... | mit |
tommythorn/yari | Icarus/rtl/altsyncram.v | 4,511 | module MODULE1(VAR28,
VAR46,
VAR44,
VAR18,
VAR7,
VAR13,
VAR37,
VAR45,
VAR15);
parameter VAR12 = "VAR55";
parameter VAR52 = 32;
parameter VAR50 = 32;
parameter VAR20 = 11;
parameter VAR23 = 11;
parameter VAR47 = 2048;
parameter VAR26 = 2048;
parameter VAR9 = "VAR36";
parameter VAR49 = "VAR30";
parameter VAR16 = "VAR43";... | gpl-2.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/hps_sdram_p0_generic_ddio.v | 2,308 | module MODULE1(
VAR9,
VAR15,
VAR21,
VAR11,
VAR17
);
parameter VAR12 = 1;
localparam VAR3 = 4 * VAR12;
localparam VAR5 = VAR12;
input [VAR3-1:0] VAR9;
input VAR15;
input [VAR12-1:0] VAR11;
input [VAR12-1:0] VAR17;
output [VAR5-1:0] VAR21;
generate
genvar VAR22;
for (VAR22 = 0; VAR22 < VAR12; VAR22 = VAR22 + 1)
begin:VAR... | epl-1.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4/sky130_fd_sc_hdll__or4_2.v | 2,247 | module MODULE2 (
VAR11 ,
VAR6 ,
VAR10 ,
VAR5 ,
VAR4 ,
VAR7,
VAR2,
VAR9 ,
VAR8
);
output VAR11 ;
input VAR6 ;
input VAR10 ;
input VAR5 ;
input VAR4 ;
input VAR7;
input VAR2;
input VAR9 ;
input VAR8 ;
VAR1 VAR3 (
.VAR11(VAR11),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9),
.... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/KOA_2c_approx.v | 6,334 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR5,
input wire [VAR14-1:0] VAR7,
input wire [VAR14-1:0] VAR30,
output wire [2*VAR14-1:0] VAR32
);
wire [1:0] VAR6;
wire [3:0] VAR31;
assign VAR6 = 2'b00;
assign VAR31 = 4'b0000;
wire [VAR14/2-1:0] VAR23;
wire [VAR14/2:0] VAR10;
wire [VAR14/2-3:0] VAR29;
wire... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_s00_regslice_0/synth/OpenSSD2_s00_regslice_0.v | 14,871 | module MODULE1 (
VAR94,
VAR55,
VAR29,
VAR20,
VAR76,
VAR12,
VAR30,
VAR99,
VAR49,
VAR65,
VAR83,
VAR24,
VAR56,
VAR71,
VAR34,
VAR6,
VAR73,
VAR111,
VAR36,
VAR78,
VAR44,
VAR57,
VAR52,
VAR48,
VAR31,
VAR61,
VAR75,
VAR40,
VAR4,
VAR105,
VAR14,
VAR80,
VAR2,
VAR53,
VAR101,
VAR45,
VAR37,
VAR90,
VAR59,
VAR63,
VAR26,
VAR88,
VAR81,
VA... | gpl-3.0 |
KestrelComputer/kestrel | cores/MGIA/rtl/verilog/video_fetcher.v | 1,934 | module MODULE1(
input VAR7,
input VAR21,
input VAR4,
input VAR23,
output [12:0] VAR5,
output VAR19,
output VAR18,
input VAR15,
input [15:0] VAR2,
output [ 5:0] VAR6,
output [15:0] VAR22,
output VAR24
);
reg [12:0] VAR13;
reg VAR8;
reg [12:0] VAR20;
reg VAR16;
reg VAR10;
reg VAR11;
reg [ 5:0] VAR17;
reg [ 5:0] VAR3;
reg... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4bb/sky130_fd_sc_hd__or4bb.behavioral.v | 1,510 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR11 ,
VAR7,
VAR4
);
output VAR8 ;
input VAR10 ;
input VAR11 ;
input VAR7;
input VAR4;
supply1 VAR12;
supply0 VAR6;
supply1 VAR9 ;
supply0 VAR5 ;
wire VAR1;
wire VAR13;
nand VAR14 (VAR1, VAR4, VAR7 );
or VAR2 (VAR13, VAR11, VAR10, VAR1);
buf VAR3 (VAR8 , VAR13 );
endmodule | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/hps_sdram_p0_reset.v | 4,395 | module MODULE1(
VAR4,
VAR11,
VAR22,
VAR23,
VAR39,
VAR8,
VAR17,
VAR30,
VAR7,
VAR38,
VAR28,
VAR10,
VAR33,
VAR1,
VAR3,
VAR35,
VAR15,
VAR37,
VAR26,
VAR40
);
parameter VAR18 = "";
parameter VAR5 = 1;
input VAR4;
input VAR11;
input VAR22;
input VAR23;
input VAR39;
input VAR8;
input VAR17;
output VAR30;
output VAR7;
input [VA... | mit |
azonenberg/openfpga | hdl/xc2c-model/XC2CJTAG.v | 17,568 | module MODULE1(
VAR27, VAR65, VAR60, VAR56,
VAR1,
VAR54, VAR39, VAR2,
VAR53, VAR31, VAR68,
VAR38, VAR4);
parameter VAR22 = 32;
parameter VAR43 = "VAR23";
parameter VAR17 = 1;
parameter VAR36 = 1;
input wire VAR27;
input wire VAR65;
input wire VAR60;
output reg VAR56;
output reg VAR1 = 0;
output reg VAR54 = 0;
output re... | lgpl-2.1 |
alexforencich/xfcp | lib/eth/rtl/ssio_sdr_in.v | 3,905 | module MODULE1 #
(
parameter VAR9 = "VAR8",
parameter VAR18 = "VAR16",
parameter VAR24 = 1
)
(
input wire VAR27,
input wire [VAR24-1:0] VAR1,
output wire VAR13,
output wire [VAR24-1:0] VAR6
);
wire VAR23;
wire VAR11;
generate
if (VAR9 == "VAR33") begin
if (VAR18 == "VAR10") begin
VAR10
VAR2 (
.VAR5(VAR27),
.VAR7(VAR23)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor2/sky130_fd_sc_lp__xor2_1.v | 2,117 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR5 ,
VAR1,
VAR7,
VAR8 ,
VAR3
);
output VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR1;
input VAR7;
input VAR8 ;
input VAR3 ;
VAR6 VAR9 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR2,
VAR4,
VAR5
);
output VAR2;
... | apache-2.0 |
lee-dohm/atom-linguist | samples/Verilog/t_button_debounce.v | 1,920 | module MODULE1();
parameter
VAR1 = 66000000,
VAR5 = 2;
reg clk, VAR4, VAR3;
wire VAR2;
VAR6
.VAR1(VAR1),
.VAR5(VAR5)
)
VAR6
(
.clk(clk),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2)
); | mit |
CospanDesign/nysa-sata | rtl/sata_stack.v | 22,310 | module MODULE1 (
input rst, input clk, input VAR244,
input VAR89,
input VAR67,
input VAR9,
input VAR121, output VAR142, output VAR165,
input VAR43,
input [15:0] VAR209,
output VAR55,
output VAR27,
output VAR215,
input VAR241,
input VAR150,
input [7:0] VAR237,
output VAR71,
input [15:0] VAR86,
input [47:0] VAR223,
outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.symbol.v | 1,332 | module MODULE1 (
input VAR3 ,
output VAR1,
input VAR4 ,
input VAR2
);
endmodule | apache-2.0 |
queq/just-stuff | pov/TopFixed/topTransmitter.v | 1,493 | module MODULE1 ( VAR12, VAR8, clk, VAR3, VAR39);
input [0:76] VAR12;
input VAR8, clk, VAR3;
output VAR39;
wire VAR4;
wire VAR30;
wire VAR16;
wire VAR6;
wire VAR14;
wire VAR9;
wire VAR25;
wire VAR22;
wire [0:76] VAR41;
wire [0:6] VAR15;
wire [0:9] VAR36;
wire VAR1;
wire VAR20;
VAR31 VAR18 (
.VAR8(VAR8),
.VAR34(VAR9),
.V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ba/sky130_fd_sc_hdll__o21ba.pp.symbol.v | 1,391 | module MODULE1 (
input VAR1 ,
input VAR2 ,
input VAR3,
output VAR5 ,
input VAR8 ,
input VAR6,
input VAR7,
input VAR4
);
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_qspi_media_1.v | 20,005 | module MODULE1(
input VAR155,
input reset,
output VAR87,
input VAR144,
output VAR39,
output VAR61,
input VAR108,
output VAR190,
output VAR131,
input VAR16,
output VAR80,
output VAR191,
input VAR47,
output VAR19,
output VAR72,
output VAR68,
output VAR32,
output VAR85,
output VAR218,
input [11:0] VAR195,
input VAR150,
in... | apache-2.0 |
yard2010/Arducar | Car/Modules/Video-and-Image-Processing-Design-Using-FPGAs-master/de1_ov7670/SRC/I2C/CCD_Capture.v | 3,430 | module MODULE1(
VAR12,
VAR1,
VAR4,
VAR3,
VAR7,
VAR24,
VAR16,
VAR14,
VAR6,
VAR19,
VAR8,
VAR25,
VAR26,
VAR22 );
output [15:0] VAR12;
reg [15:0] VAR11;
reg [7:0] VAR17;
reg [7:0] VAR23;
assign VAR12 = VAR11;
input [7:0] VAR14;
input VAR6;
input VAR19;
input VAR8;
input VAR25;
input VAR26;
input VAR22;
output [7:0] VAR1;
o... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/pfpu/rtl/pfpu_seq.v | 2,294 | module MODULE1(
input VAR3,
input VAR7,
output reg VAR15,
input VAR6,
input VAR14,
input VAR18,
output reg VAR17,
output reg VAR4,
input VAR10,
output reg VAR16,
output reg VAR9,
input VAR1,
output reg VAR11
);
reg [1:0] state;
reg [1:0] VAR8;
parameter VAR13 = 2'd0;
parameter VAR5 = 2'd1;
parameter VAR2 = 2'd2;
parame... | lgpl-3.0 |
SymbiFlow/fpga-tool-perf | third_party/daisho-usb3/usb3_ep0.v | 10,394 | module MODULE1 (
input wire VAR30,
input wire VAR22,
input wire VAR66,
input wire [8:0] VAR85,
input wire [31:0] VAR70,
input wire VAR101,
output wire VAR106,
input wire VAR15,
input wire [10:0] VAR92,
output wire VAR79,
input wire [8:0] VAR9,
output wire [31:0] VAR100,
output wire [10:0] VAR26,
output wire VAR34,
inpu... | isc |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_lite_i2c/rtl/axi_lite_i2c.v | 16,036 | module MODULE1 #(
parameter VAR8 = 8,
parameter VAR11 = 32,
parameter VAR110 = (VAR11 / 8),
parameter VAR64 = 1,
parameter VAR109 = 50000000
)(
input clk,
input rst,
input VAR76,
input [VAR8 - 1: 0] VAR97,
output VAR77,
input VAR35,
output VAR48,
input [VAR11 - 1: 0] VAR89,
output VAR66,
input VAR113,
output [1:0] VAR2... | mit |
fbalakirev/red-pitaya-notes | projects/red_pitaya_0_92/red_pitaya_daisy_tx.v | 5,122 | module MODULE1
(
input VAR34 , output VAR8 , output VAR60 ,
input VAR42 , input VAR40 ,
output VAR33 , input VAR46 , input [ 16-1: 0] VAR9 );
VAR36 #(
.VAR50 ( "VAR54" ), .VAR37 ( 1'b1 ), .VAR24 ( "VAR45" ) ) VAR23 (
.VAR21 ( VAR8 ), .VAR12 ( VAR34 ), .VAR58 ( 1'b1 ), .VAR22 ( 1'b1 ), .VAR51 ( 1'b0 ), .VAR52 ( !VAR40 )... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_2.behavioral.pp.v | 2,179 | module MODULE1( VAR12, VAR6, VAR7, VAR13, VAR5 );
input VAR12, VAR6;
inout VAR13, VAR5;
output VAR7;
reg VAR8;
VAR2 VAR10(.VAR12(VAR12),.VAR6(VAR6),.VAR7(VAR7),.VAR13(VAR13),.VAR5(VAR5),.VAR8(VAR8));
VAR2 VAR1(.VAR12(VAR12),.VAR6(VAR6),.VAR7(VAR7),.VAR13(VAR13),.VAR5(VAR5),.VAR8(VAR8));
not VAR4(VAR3,VAR6);
buf VAR9(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtn/sky130_fd_sc_ls__dlrtn.pp.symbol.v | 1,420 | module MODULE1 (
input VAR8 ,
output VAR5 ,
input VAR2,
input VAR7 ,
input VAR4 ,
input VAR6 ,
input VAR1 ,
input VAR3
);
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/mem_arbiter.v | 5,567 | module MODULE1 (
input VAR44,
input VAR3,
output reg [22:0] VAR1,
output [15:0] VAR37,
output [1:0] VAR29,
output reg VAR21,
output reg VAR24,
output reg VAR16,
input VAR33,
input VAR4,
input VAR31,
output reg VAR15,
input [22:0] VAR12,
input [15:0] VAR48,
input [1:0] VAR20,
input VAR23,
input VAR11,
input VAR38,
outpu... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController/src/pcie_rx_cmd_fifo.v | 4,960 | module MODULE1 # (
parameter VAR47 = 34,
parameter VAR5 = 5
)
(
input clk,
input VAR41,
input VAR33,
input [VAR47-1:0] VAR39,
output VAR6,
input VAR36,
output [VAR47-1:0] VAR27,
output VAR45
);
localparam VAR14 = 1;
reg [VAR5:0] VAR19;
reg [VAR5:0] VAR7;
wire [VAR5-1:0] VAR15;
reg [VAR5:0] VAR4;
assign VAR6 = ~((VAR4[V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4b/sky130_fd_sc_hd__and4b.behavioral.v | 1,508 | module MODULE1 (
VAR9 ,
VAR12,
VAR5 ,
VAR11 ,
VAR7
);
output VAR9 ;
input VAR12;
input VAR5 ;
input VAR11 ;
input VAR7 ;
supply1 VAR2;
supply0 VAR13;
supply1 VAR1 ;
supply0 VAR4 ;
wire VAR8 ;
wire VAR6;
not VAR10 (VAR8 , VAR12 );
and VAR14 (VAR6, VAR8, VAR5, VAR11, VAR7);
buf VAR3 (VAR9 , VAR6 );
endmodule | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ddr2/ddr2_mig.v | 26,404 | module MODULE1 #
(
parameter VAR26 = 2,
parameter VAR12 = 1,
parameter VAR62 = 2,
parameter VAR31 = 10,
parameter VAR40 = 1,
parameter VAR30 = 1,
parameter VAR77 = 0,
parameter VAR11 = 8,
parameter VAR78 = 64,
parameter VAR8 = 8,
parameter VAR67 = 8,
parameter VAR69 = 6,
parameter VAR21 = 3,
parameter VAR1 = 1,
paramet... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtp/sky130_fd_sc_hs__dlxtp.symbol.v | 1,303 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR2
);
supply1 VAR4;
supply0 VAR5;
endmodule | apache-2.0 |
cmos3511/cmos_linux | python/pj/proj/rtl/LP/mult3232.v | 3,987 | module MODULE1(VAR20,VAR30,VAR32,VAR25,VAR11,VAR17,VAR27,reset);
output VAR20; output [VAR23-1:0] VAR30; input [VAR23-1:0] VAR32; input [VAR23-1:0] VAR25; input [VAR23-1:0] VAR11; input VAR17;
input VAR27;
input reset;
reg [31:0] VAR29, VAR28;
wire [VAR23:0] VAR19; wire [VAR23:0] VAR26; wire [VAR23:0] VAR16; wire [VAR2... | gpl-3.0 |
liqimai/ZPC | PersonalComputer/ControlUnit.v | 7,459 | module MODULE1(
input clk,
input[5:0] VAR9,
input[5:0] VAR8,
input[4:0] VAR27,
input VAR6,
input[31:0] VAR26,
output VAR30,
output VAR23,
output VAR20,
output VAR5,
output VAR4,
output[2:0] VAR2,
output VAR25,
output[1:0] VAR24,
output VAR29,
output[1:0] VAR13,
output VAR3,
output VAR18,
output[1:0] VAR15,
output[2:0] ... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/lsu/rtl/lsu_excpctl.v | 58,679 | module MODULE1 (
VAR188, VAR88, VAR117,
VAR280, VAR164,
VAR174, VAR141,
VAR45, VAR232, VAR12,
VAR146, VAR365,
VAR96, VAR55, VAR317,
VAR310, VAR269, VAR330,
VAR153, VAR260, VAR224,
VAR49, VAR324,
VAR119, VAR157,
VAR173, VAR279, VAR155,
VAR73, VAR336, VAR229,
VAR135, VAR71, VAR165,
VAR4, VAR57, VAR59,
VAR203, VAR129, VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_refgen/sky130_fd_io__top_refgen.symbol.v | 1,972 | module MODULE1 (
input VAR15 ,
input VAR17 ,
input VAR16 ,
input VAR6 ,
input VAR5 ,
input VAR13 ,
inout VAR10,
output VAR18 ,
input VAR2 ,
output VAR1
);
wire VAR9 ;
wire VAR11 ;
wire VAR12 ;
wire VAR8 ;
wire VAR3;
wire VAR14 ;
wire VAR7 ;
wire VAR4;
endmodule | apache-2.0 |
eda-globetrotter/PicenoDecoders | final/src/tosynth Folder/cpu.v | 4,854 | module MODULE1(
clk,
reset,
VAR48, VAR63, VAR22, VAR19, VAR71, VAR49, VAR57 );
input clk, reset;
input [0:31] VAR48; input [0:127] VAR22;
output [0:31] VAR63; output [0:127] VAR19; output [0:21] VAR71; output VAR49, VAR57;
wire [0:31] VAR63;
wire [0:31] VAR59, VAR45, VAR25;
wire [0:4] VAR37, VAR44;
wire [0:1] VAR40, VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi.functional.v | 2,137 | module MODULE1 (
VAR2,
VAR5,
VAR4 ,
VAR3,
VAR7,
VAR10 ,
VAR1
);
input VAR2;
input VAR5;
output VAR4 ;
input VAR3;
input VAR7;
input VAR10 ;
input VAR1 ;
wire VAR1 VAR11 ;
wire VAR1 VAR6 ;
wire VAR14 ;
wire VAR17;
and VAR16 (VAR11 , VAR10, VAR1 );
nor VAR15 (VAR6 , VAR3, VAR7 );
nor VAR9 (VAR14 , VAR6, VAR11 );
VAR8 VAR... | apache-2.0 |
DougFirErickson/parallella-hw | fpga/old/eproto_rx/hdl/eproto_rx.v | 11,885 | module MODULE1 (
VAR27, VAR38, VAR33, VAR4, VAR29,
VAR5, VAR7, VAR25, VAR1,
reset, VAR28, VAR41, VAR37, VAR45, VAR22
);
input reset;
input VAR28; input [7:0] VAR41;
input [63:0] VAR37;
output VAR27; output VAR38;
output VAR33;
output VAR4;
output [1:0] VAR29;
output [3:0] VAR5;
output [31:0] VAR7;
output [31:0] VAR25;
... | gpl-3.0 |
sh-chris110/chris | FPGA/chris.uart.ok/Qsys/soc_design/synthesis/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1500011221 : 255;
endmodule | gpl-2.0 |
RECS-Tsukuba/fpga-filter-hardware | operation.v | 3,722 | module MODULE1 #(
parameter VAR17 = 2,
parameter VAR6 = 2'd0,
parameter VAR11 = 2'd1,
parameter VAR15 = 2'd2,
parameter VAR3 = 2'd3,
parameter VAR7 = 3,
parameter VAR10 = 8 + VAR17
)(
input [VAR10*VAR7*VAR7-1:0] VAR12,
input clk,
input rst,
input VAR5,
output [VAR10-1:0] out
);
wire [VAR10-1:0] VAR1[VAR7-1:0][VAR7-1:0]... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9152/axi_ad9152.v | 7,459 | module MODULE1 (
VAR13,
VAR38,
VAR62,
VAR70,
VAR39,
VAR75,
VAR55,
VAR76,
VAR48,
VAR8,
VAR33,
VAR59,
VAR73,
VAR5,
VAR34,
VAR65,
VAR26,
VAR28,
VAR50,
VAR44,
VAR15,
VAR81,
VAR14,
VAR7,
VAR12,
VAR52,
VAR67,
VAR64,
VAR9,
VAR32);
parameter VAR25 = 0;
parameter VAR45 = 0;
input VAR13;
output [127:0] VAR38;
output VAR62;
outpu... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_2.behavioral.v | 1,620 | module MODULE1( VAR5, VAR2, VAR3, VAR4 );
input VAR4, VAR2, VAR3;
output VAR5;
VAR1 VAR7(.VAR5(VAR5),.VAR2(VAR2),.VAR3(VAR3),.VAR4(VAR4));
VAR1 VAR6(.VAR5(VAR5),.VAR2(VAR2),.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Booth_64/booth_mult_64.v | 3,005 | module MODULE1(
input clk,
input rst,
input en,
input [31:0] VAR16,
input [31:0] VAR4,
output reg VAR10,
output reg [63:0] VAR21
);
wire [31:0] VAR17;
VAR14 VAR2(.VAR16(VAR4),.VAR20(VAR17));
reg VAR6;
reg VAR7;
reg [64:0] VAR3;
reg [31:0] VAR5;
wire [64:0] VAR1;
wire [64:0] VAR12;
VAR13 VAR9(.clk(clk),.en(VAR7),.VAR8(V... | mit |
DougFirErickson/parallella-hw | fpga/old/emaxi/hdl/emaxi_v1_0.v | 5,712 | module MODULE1 #
(
parameter VAR75 = 32'h40000000,
parameter integer VAR48 = 16,
parameter integer VAR92 = 1,
parameter integer VAR55 = 32,
parameter integer VAR94 = 64,
parameter integer VAR104 = 0,
parameter integer VAR81 = 0,
parameter integer VAR34 = 0,
parameter integer VAR4 = 0,
parameter integer VAR36 = 0
)
(
in... | gpl-3.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/FpuFpD.v | 6,617 | module MODULE1(
VAR47,
VAR54, VAR34,
VAR18, VAR31,
VAR40, VAR95,
VAR68, VAR14,
VAR70, VAR15, VAR61,
VAR69, VAR52,
VAR42, VAR80,
VAR79, VAR53
);
input VAR47;
input[7:0] VAR54;
input[1:0] VAR34;
input[63:0] VAR31;
input[63:0] VAR95;
input[63:0] VAR14;
output[63:0] VAR15;
input[6:0] VAR18;
input[6:0] VAR40;
input[6:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv.pp.symbol.v | 1,238 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR4 ,
input VAR3,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
Gifts/descrypt-ztex-bruteforcer | user_cores/des/src/SP_block.v | 1,161 | module MODULE1(
input [47:0] VAR6,
output [31:0] VAR5
);
wire [31:0] VAR4;
VAR7 VAR3(
VAR6,
VAR4);
VAR1 VAR2(
VAR4,
VAR5
);
endmodule | gpl-3.0 |
stevenokm/mor1kx | rtl/verilog/mor1kx_cfgrs.v | 10,775 | module MODULE1
parameter VAR69 = "VAR48",
parameter VAR27 = "VAR48",
parameter VAR25 = "VAR48",
parameter VAR56 = "VAR8",
parameter VAR88 = 5,
parameter VAR2 = 9,
parameter VAR80 = 2,
parameter VAR36 = "VAR8",
parameter VAR95 = 6,
parameter VAR38 = 1,
parameter VAR108 = "VAR8",
parameter VAR11 = 5,
parameter VAR83 = 9,... | mpl-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_5/ab882192/src/Completion.v | 6,138 | module MODULE1
(
parameter VAR9 = 32 ,
parameter VAR7 = 32 ,
parameter VAR22 = 16 ,
parameter VAR20 = 1
)
(
VAR18 ,
VAR35 ,
VAR6 ,
VAR13 ,
VAR27 ,
VAR34 ,
VAR16 ,
VAR26 ,
VAR14 ,
VAR36 ,
VAR10 ,
VAR11 ,
VAR3 ,
VAR31 ,
VAR30 ,
VAR5 ,
VAR17 ,
VAR29 ,
VAR2 ,
VAR8 ,
VAR4 ,
VAR24 ,
VAR21 ,
VAR25
);
input VAR18 ;
input VAR35... | gpl-3.0 |
defano/digital-design | lsuc/rtl/bus_arb.v | 3,873 | module MODULE1 (
clk,
reset,
VAR13,
VAR2,
VAR12,
VAR14,
VAR18,
VAR8,
VAR19,
addr,
VAR16,
req,
VAR15,
VAR3,
VAR6,
VAR11,
VAR10,
VAR5,
VAR7,
VAR4,
VAR1,
VAR17);
input clk;
input reset;
input [31:0] VAR13; output VAR2; input [31:0] VAR12; input VAR14; output [31:0] VAR18; input VAR8; input [3:0] VAR19;
output [7:0] addr; ... | mit |
grindars/bfcore | IRAM.v | 1,180 | module MODULE1 (
VAR8,
VAR1,
VAR5,
VAR4
);
parameter VAR2 = 11;
parameter VAR7 = (1 << VAR2);
input VAR8;
input [VAR2 - 1:0] VAR1;
output reg [7:0] VAR5;
input VAR4;
reg [7:0] VAR3 [0:VAR7 - 1];
always @ (posedge VAR8)
if(VAR4)
VAR5 <= VAR3[VAR1];
integer VAR6;
begin | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/wishbone/host_interface/ft245_sync_fifo/ft_fifo_interface.v | 13,437 | module MODULE1 (
rst,
clk,
VAR9,
VAR10,
VAR80,
VAR36,
VAR54,
VAR55,
VAR43,
VAR7,
VAR49,
VAR3,
VAR45,
VAR17,
VAR58,
VAR6,
VAR66,
VAR77,
VAR39,
VAR90,
VAR70,
VAR33,
VAR79
);
input rst;
input clk;
input VAR9;
output [23:0] VAR10;
output VAR80;
input VAR36;
output [7:0] VAR54;
output VAR55;
input VAR43;
output [23:0] VAR7;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311oi/sky130_fd_sc_ms__a311oi.functional.v | 1,485 | module MODULE1 (
VAR11 ,
VAR6,
VAR3,
VAR1,
VAR9,
VAR8
);
output VAR11 ;
input VAR6;
input VAR3;
input VAR1;
input VAR9;
input VAR8;
wire VAR5 ;
wire VAR7;
and VAR10 (VAR5 , VAR1, VAR6, VAR3 );
nor VAR2 (VAR7, VAR5, VAR9, VAR8);
buf VAR4 (VAR11 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2b/sky130_fd_sc_ls__nor2b.functional.v | 1,393 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR1 ;
input VAR3;
wire VAR6 ;
wire VAR8;
not VAR2 (VAR6 , VAR1 );
and VAR7 (VAR8, VAR6, VAR3 );
buf VAR4 (VAR5 , VAR8 );
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/atr_controller.v | 2,484 | module MODULE1
(input VAR13, input VAR16,
input [5:0] VAR3, input [3:0] VAR10, input [31:0] VAR8, output reg [31:0] VAR2,
input VAR12, input VAR15, input VAR4, output reg VAR17,
input VAR18, input VAR7,
output [31:0] VAR11);
reg [3:0] state;
reg [31:0] VAR9 [0:15];
always @(posedge VAR13)
if(VAR12 & VAR15 & VAR4)
begin... | gpl-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_OA_SRAM_SS_210930.v | 231,431 | module MODULE1 (VAR1, VAR10, VAR6, VAR11, VAR5);
output VAR1;
input VAR10, VAR6, VAR11, VAR5;
wire VAR7, VAR4, VAR2;
wire VAR9, VAR3, VAR8;
not (VAR9, VAR5);
not (VAR2, VAR11);
not (VAR4, VAR6);
and (VAR3, VAR4, VAR2);
not (VAR7, VAR10);
and (VAR8, VAR7, VAR2);
or (VAR1, VAR8, VAR3, VAR9); | bsd-3-clause |
duttondj/DigitalDesignI-P3 | sevensegdecoder_always.v | 1,346 | module MODULE1(VAR2, VAR1);
input [3:0] VAR2;
output [6:0] VAR1; reg [6:0] VAR1;
always @(VAR2) begin
if(VAR2 == 4'h0)
begin
VAR1 = 7'b0000001;
end
if(VAR2 == 4'h1)
begin
VAR1 = 7'b1001111;
end
if(VAR2 == 4'h2)
begin
VAR1 = 7'b0010010;
end
if(VAR2 == 4'h3)
begin
VAR1 = 7'b0000110;
end
if(VAR2 == 4'h4)
begin
VAR1 = 7'b1... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_1.behavioral.v | 1,178 | module MODULE1( VAR2, VAR5, VAR3 );
input VAR2, VAR5;
output VAR3;
VAR6 VAR1(.VAR2(VAR2),.VAR5(VAR5),.VAR3(VAR3));
VAR6 VAR4(.VAR2(VAR2),.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
jmahler/mips-cpu | im_cached.v | 2,955 | module MODULE1(
input wire clk,
input wire [31:0] addr,
output wire VAR14,
output wire [31:0] VAR2);
parameter VAR1 = 128;
parameter VAR6 = "VAR11.VAR18";
parameter VAR10 = 128;
parameter VAR7 = 3;
wire VAR5;
wire [31:0] VAR8;
VAR9 #(.VAR1(VAR1), .VAR6(VAR6), .VAR7(VAR7))
VAR3(.clk(clk), .addr(addr), .VAR5(VAR5), .VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr.pp.blackbox.v | 1,414 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR3 ,
VAR5 ,
VAR7,
VAR1 ,
VAR4
);
output VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR7;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/acl_fp_custom_add_hc_dbl_pumped.v | 2,596 | module MODULE1
(
input VAR16,
input VAR9,
input VAR14,
input VAR24,
input VAR28,
output VAR11,
output VAR13,
input [VAR5-1:0] VAR3,
input [VAR5-1:0] b1,
input [VAR5-1:0] VAR22,
input [VAR5-1:0] VAR23,
output [VAR5-1:0] VAR2,
output [VAR5-1:0] VAR20
);
wire [VAR5-1:0] VAR12;
wire [VAR5-1:0] VAR26;
wire [VAR5-1:0] VAR29;... | mit |
Digilent/vivado-library | ip/MotorFeedback_1.0/hdl/posManager.v | 4,158 | module MODULE1 (
input wire clk,
output wire [15:0] VAR13,
output wire [15:0] VAR4,
output wire [15:0] VAR6,
output wire [15:0] VAR1,
output wire [15:0] VAR11,
output reg [31:0] VAR12,
input wire VAR2,
input wire VAR10,
input wire [1:0] VAR8
);
reg VAR9, VAR3, VAR7, VAR5; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221a/sky130_fd_sc_hd__o221a_2.v | 2,444 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR7 ,
VAR2 ,
VAR8 ,
VAR12 ,
VAR4,
VAR3,
VAR5 ,
VAR10
);
output VAR9 ;
input VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR12 ;
input VAR4;
input VAR3;
input VAR5 ;
input VAR10 ;
VAR1 VAR11 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR4(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probec_p/sky130_fd_sc_hdll__probec_p.functional.pp.v | 1,810 | module MODULE1 (
VAR9 ,
VAR12 ,
VAR6,
VAR7,
VAR3 ,
VAR11
);
output VAR9 ;
input VAR12 ;
input VAR6;
input VAR7;
input VAR3 ;
input VAR11 ;
wire VAR5 ;
wire VAR10;
buf VAR8 (VAR5 , VAR12 );
VAR1 VAR4 (VAR10, VAR5, VAR6, VAR7);
buf VAR2 (VAR9 , VAR10 );
endmodule | apache-2.0 |
muraj/trv_proc | synth/stdcells.v | 1,686 | module MODULE12(VAR7, VAR9, VAR6);
input VAR7, VAR9;
output VAR6;
and(VAR6, VAR7, VAR9);
endmodule
module MODULE3(VAR7, VAR9, VAR6);
input VAR7, VAR9;
output VAR6;
and(VAR6, VAR7, VAR9);
endmodule
module MODULE14(VAR7, VAR9, VAR1, VAR6);
input VAR7, VAR9, VAR1;
output VAR6;
wire VAR3;
and(VAR3, VAR7, VAR9);
nor(VAR6, V... | mit |
gyurco/ZX_Spectrum-128K_MIST | sys/sd_card.v | 17,540 | module MODULE2 (
input VAR68,
output reg[31:0] VAR40,
output reg VAR76,
output reg VAR58,
input VAR16,
input VAR53,
output VAR59,
output VAR44,
input VAR39,
input [31:0] VAR13,
output reg VAR74 = 0,
input [7:0] VAR14,
input VAR71,
output [7:0] VAR12,
input [8:0] VAR26,
input VAR73,
input VAR37,
input VAR32,
input VAR41... | gpl-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/acl_mem1x.v | 8,405 | module MODULE2
parameter VAR64=1,
parameter VAR5=32,
parameter VAR77=3, parameter VAR60="VAR73",
parameter VAR111 = "VAR109", parameter VAR61 = "VAR25" )
(
input wire clk,
input wire VAR21,
input wire [VAR5-1:0] VAR2,
input wire [VAR5-1:0] VAR44,
input wire [VAR5/8-1:0] VAR24,
input wire [VAR5/8-1:0] VAR34,
input wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxbp/sky130_fd_sc_ms__sdfxbp.pp.blackbox.v | 1,398 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR5 ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR6,
VAR10,
VAR9 ,
VAR1
);
output VAR2 ;
output VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR6;
input VAR10;
input VAR9 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3/sky130_fd_sc_lp__nand3.pp.blackbox.v | 1,293 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR6 ,
VAR2 ,
VAR3,
VAR4,
VAR8 ,
VAR5
);
output VAR1 ;
input VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR3;
input VAR4;
input VAR8 ;
input VAR5 ;
endmodule | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v2_0_bank_cntrl.v | 25,941 | module MODULE1 #
(
parameter VAR11 = 100,
parameter VAR17 = "1T",
parameter VAR67 = 3,
parameter VAR28 = 2,
parameter VAR54 = "8",
parameter VAR48 = 12,
parameter VAR96 = 5,
parameter VAR143 = 8,
parameter VAR144 = "VAR18",
parameter VAR101 = "VAR31",
parameter VAR24 = 4,
parameter VAR85 = 4,
parameter VAR57 = 2,
param... | bsd-2-clause |
impedimentToProgress/ProbableCause | ddr2/cores/arbiter/arbiter_ibus.v | 4,719 | module MODULE1
(
VAR14,
VAR15,
VAR18,
VAR30,
VAR45,
VAR37,
VAR49,
VAR44,
VAR23,
VAR40,
VAR20,
VAR42,
VAR1,
VAR9,
VAR26,
VAR31,
VAR6,
VAR2,
VAR21,
VAR7,
VAR13,
VAR22,
VAR12,
VAR10,
VAR39,
VAR29,
VAR34,
VAR32,
VAR33,
VAR35,
VAR16,
VAR50,
VAR43,
VAR3,
VAR46,
VAR5,
VAR36,
VAR4
);
parameter VAR17 = 32;
parameter VAR41 = 32;... | mit |
alanachtenberg/CSCE-350 | Lab 7/lab7_2.v | 1,257 | module MODULE1 (VAR3,VAR6,VAR1,VAR8);
output VAR3, VAR6;
input VAR1, VAR8;
wire VAR10, VAR2;
wire VAR4;
not (VAR4,VAR8);
nand (VAR10,VAR1, VAR8);
nand (VAR2,VAR1, VAR4);
nand (VAR6,VAR2,VAR3);
nand (VAR3,VAR10,VAR6);
endmodule
module MODULE2(VAR1);
parameter VAR9 = 10, VAR5 = 50, VAR7 = 50;
output VAR1;
reg VAR1; | gpl-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b1/ModTxtMemW.v | 4,041 | module MODULE1(VAR23, reset,
VAR3, VAR12,
VAR8, VAR7,
VAR19, VAR28, VAR31, VAR27, VAR4);
input VAR23;
input reset;
input[13:0] VAR3;
output[127:0] VAR12;
input[15:0] VAR8;
output[63:0] VAR7;
input[31:0] VAR19;
inout[31:0] VAR28;
input VAR31;
input VAR27;
output[1:0] VAR4;
reg[1:0] VAR1; reg[31:0] VAR26; wire VAR24;
ass... | mit |
svenstaro/uni-projekt | verilog/ram.v | 7,388 | module MODULE1 (
address,
VAR36,
VAR46,
VAR27,
VAR5,
VAR28,
VAR20);
input [9:0] address;
input [3:0] VAR36;
input VAR46;
input [31:0] VAR27;
input VAR5;
input VAR28;
output [31:0] VAR20;
tri1 [3:0] VAR36;
tri1 VAR46;
tri1 VAR5;
wire [31:0] VAR23;
wire [31:0] VAR20 = VAR23[31:0];
VAR43 VAR32 (
.VAR3 (address),
.VAR2 (VA... | gpl-3.0 |
krmarien/Proxmark | fpga/relay_decode.v | 1,299 | module MODULE1(
clk,
reset,
VAR2,
VAR7,
VAR3,
VAR4
);
input clk, reset, VAR2, VAR7;
output[3:0] VAR3;
output[0:0] VAR4;
reg [3:0] VAR3 = 4'b0;
reg [0:0] VAR4 = 1'b0;
reg [6:0] VAR1 = 7'b0;
reg [6:0] VAR5 = 7'b0;
reg [0:0] VAR6 = 1'b0;
always @(posedge clk)
begin
VAR6 = VAR6 | VAR7 == 1'b1;
VAR1 = VAR1 + (VAR7 == 1'b1 &... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/iobdg_dbg/rtl/iobdg_dbg.v | 24,365 | module MODULE1 (
VAR25, VAR44, VAR50,
VAR43, VAR31, VAR54,
VAR6, VAR71, VAR12,
VAR103, VAR93, VAR106,
VAR141, VAR5, VAR98,
VAR28, VAR76, VAR40, VAR83,
VAR129, VAR56, VAR22, VAR35, VAR37,
VAR97, VAR107, VAR18, VAR30,
VAR126, VAR41, VAR135, VAR7,
VAR42, VAR123, VAR94,
VAR4, VAR34, VAR108, VAR14,
VAR53, VAR63, VAR85,
VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfstp/sky130_fd_sc_lp__dfstp.blackbox.v | 1,319 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR1 ,
VAR3
);
output VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR3;
supply1 VAR8;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkbuf/sky130_fd_sc_hd__clkbuf_8.v | 2,034 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR1,
VAR4,
VAR3 ,
VAR8
);
output VAR7 ;
input VAR5 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR8 ;
VAR2 VAR6 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR7,
VAR5
);
output VAR7;
input VAR5;
supply1 VAR1;
supply0 VAR4;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill_diode/sky130_fd_sc_ls__fill_diode.functional.v | 1,141 | module MODULE1 ();
supply1 VAR4;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decap/sky130_fd_sc_ls__decap.behavioral.pp.v | 1,172 | module MODULE1 (
VAR4,
VAR1,
VAR2 ,
VAR3
);
input VAR4;
input VAR1;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
freecores/zet86 | soc/vga/rtl/vdu.v | 12,854 | module MODULE1 (
input VAR92, input VAR59,
input [15:0] VAR84,
output reg [15:0] VAR79,
input [11:1] VAR4,
input VAR6,
input VAR77,
input [ 1:0] VAR16,
input VAR30,
input VAR13,
output reg VAR38,
output reg [ 1:0] VAR47,
output reg [ 1:0] VAR94,
output reg [ 1:0] VAR22,
output reg VAR67,
output reg VAR102
);
parameter ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_20.behavioral.v | 1,106 | module MODULE1( VAR4, VAR5 );
input VAR4;
output VAR5;
VAR2 VAR1(.VAR4(VAR4),.VAR5(VAR5));
VAR2 VAR3(.VAR4(VAR4),.VAR5(VAR5)); | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_aluspr.v | 1,933 | module MODULE1(
VAR7,
VAR3, VAR1, VAR6
);
input [63:0] VAR3;
input [63:0] VAR1;
input VAR6;
output [63:0] VAR7;
wire [63:0] VAR4;
wire [62:0] VAR5;
wire [63:0] VAR2;
assign VAR4[63:0] = VAR3[63:0] ^ VAR1[63:0];
assign VAR5[62:0] = VAR3[62:0] | VAR1[62:0];
assign VAR2[63:0] = {VAR5[62:0],VAR6};
assign VAR7[63:0] = VAR4[... | gpl-2.0 |
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