repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/altera_avalon_st_pipeline_base.v | 4,579 | module MODULE1 (
clk,
reset,
VAR16,
VAR9,
VAR12,
VAR5,
VAR4,
VAR15
);
parameter VAR14 = 1;
parameter VAR1 = 8;
parameter VAR10 = 1;
localparam VAR13 = VAR14 * VAR1;
input clk;
input reset;
output VAR16;
input VAR9;
input [VAR13-1:0] VAR12;
input VAR5;
output VAR4;
output [VAR13-1:0] VAR15;
reg VAR6;
reg VAR8;
reg [VAR1... | mit |
alexforencich/verilog-ethernet | example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 9,016 | module MODULE1 #
(
parameter VAR125 = 1,
parameter VAR60 = 64,
parameter VAR34 = (VAR60/8),
parameter VAR15 = 2,
parameter VAR82 = 0,
parameter VAR70 = 0,
parameter VAR128 = 0,
parameter VAR105 = 1,
parameter VAR40 = 8,
parameter VAR117 = 125000/6.4
)
(
input wire VAR115,
input wire VAR104,
output wire VAR102,
input wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2/sky130_fd_sc_hdll__and2_2.v | 2,102 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR8 ,
VAR1,
VAR2,
VAR4 ,
VAR3
);
output VAR9 ;
input VAR5 ;
input VAR8 ;
input VAR1;
input VAR2;
input VAR4 ;
input VAR3 ;
VAR7 VAR6 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR9,
VAR5,
VAR8
);
output VAR9;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.blackbox.v | 1,395 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR5 ,
VAR2,
VAR6 ,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR2;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31a/sky130_fd_sc_ls__o31a_4.v | 2,322 | module MODULE2 (
VAR5 ,
VAR11 ,
VAR3 ,
VAR4 ,
VAR1 ,
VAR10,
VAR7,
VAR9 ,
VAR8
);
output VAR5 ;
input VAR11 ;
input VAR3 ;
input VAR4 ;
input VAR1 ;
input VAR10;
input VAR7;
input VAR9 ;
input VAR8 ;
VAR2 VAR6 (
.VAR5(VAR5),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR9(VAR9),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221ai/sky130_fd_sc_hs__o221ai_2.v | 2,330 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR3 ,
VAR9 ,
VAR1 ,
VAR7 ,
VAR10,
VAR5
);
output VAR4 ;
input VAR6 ;
input VAR3 ;
input VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR10;
input VAR5;
VAR8 VAR2 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5)
);
endmodule
module MODUL... | apache-2.0 |
MarcoVogt/basil | firmware/modules/fast_spi_rx/fast_spi_rx_core.v | 3,721 | module MODULE1
parameter VAR18 = 16,
parameter VAR9 = 4'b0001
)(
input wire VAR1,
input wire VAR13,
input wire VAR43,
input wire VAR54,
output wire VAR30,
output wire [31:0] VAR53,
input wire VAR41,
input wire [VAR18-1:0] VAR47,
input wire [7:0] VAR10,
output reg [7:0] VAR60,
input wire VAR4,
input wire VAR5,
input wir... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_evicttag_dp.v | 8,211 | module MODULE1(
VAR21, VAR12, VAR30, VAR9, VAR22,
VAR76, VAR27, VAR61,
VAR66, VAR70, VAR75, VAR43,
VAR33, VAR72, VAR47,
VAR14, VAR81, VAR13,
VAR42, VAR35, VAR17, VAR50, VAR45, VAR55,
VAR6
);
output [39:0] VAR21;
output VAR12;
output [39:6] VAR30 ; output [39:5] VAR9;
output [39:8] VAR22; output [39:0] VAR76;
output [39... | gpl-2.0 |
peteg944/music-fpga | Experimental/Zedboard UART/ipcore_dir/Clock48MHZ/example_design/Clock48MHZ_exdes.v | 6,073 | module MODULE1
parameter VAR19 = 100
)
( input VAR35,
input VAR9,
output [4:1] VAR2,
output [4:1] VAR34,
output VAR25
);
localparam VAR33 = 16;
localparam VAR32 = 4;
genvar VAR1;
wire VAR15 = !VAR25 || VAR9;
reg [VAR32:1] VAR17;
reg [VAR32:1] VAR13;
reg [VAR32:1] VAR30;
reg [VAR32:1] VAR31;
wire [VAR32:1] VAR7;
wire [V... | mit |
combinatorylogic/soc | backends/c2/hw/rtl/soctop.v | 6,119 | module MODULE5(input VAR14,
output VAR5,
input VAR12);
wire clk;
wire rst;
wire [31:0] VAR6;
wire [31:0] VAR22;
wire [31:0] VAR13;
wire [31:0] VAR7;
wire [31:0] VAR21;
wire VAR30;
VAR4 VAR16(.clk(clk),
.rst(rst),
.VAR6(VAR6),
.VAR22(VAR22),
.VAR13(VAR13),
.VAR7(VAR7),
.VAR21(VAR21),
.VAR30(VAR30),
.VAR3(0)
);
wire [31:... | mit |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/flashcontrol.v | 5,092 | module MODULE1(
input wire VAR6,
input wire rst,
input wire[2:0] VAR4,
input wire[22:0] VAR29,
input wire[15:0] VAR10,
input wire[15:0] VAR34,
output wire VAR33,
output wire VAR1,
output wire VAR7,
output wire VAR30,
output wire[22:0] VAR32,
output reg[15:0] VAR22,
output wire VAR13,
output wire[31:0] VAR9
);
reg[2:0] ... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31oi/sky130_fd_sc_lp__a31oi_m.v | 2,347 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR4 ,
VAR5 ,
VAR8 ,
VAR2,
VAR11,
VAR9 ,
VAR3
);
output VAR7 ;
input VAR1 ;
input VAR4 ;
input VAR5 ;
input VAR8 ;
input VAR2;
input VAR11;
input VAR9 ;
input VAR3 ;
VAR6 VAR10 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/source/axi_basic_rx_null_gen.v | 15,674 | module MODULE1 # (
parameter VAR37 = 128, parameter VAR26 = 1,
parameter VAR28 = VAR37 / 8 ) (
input [VAR37-1:0] VAR38, input VAR13, input VAR30, input VAR11, input [21:0] VAR15,
output VAR4, output VAR31, output [VAR28-1:0] VAR9, output VAR14, output reg [4:0] VAR33,
input VAR19, input VAR23 );
localparam VAR7 = (VAR3... | lgpl-3.0 |
kyzhai/NUNY | src/hardware/audio_buffer.v | 1,607 | module MODULE1 ( VAR11, VAR13, reset,
VAR1,
read, VAR9,
VAR8
);
input VAR11,VAR13,reset,read;
input [15:0] VAR1;
output [15:0] VAR9;
output VAR8;
reg [15:0] VAR7 [0:99];
reg [15:0] VAR6 [0:99];
reg [6:0] VAR2 = 7'd0;
reg [6:0] VAR10 = 7'd0;
reg [6:0] VAR14 = 7'd0;
reg VAR12 = 1'b0;
reg VAR5;
reg irq;
reg VAR4;
wire VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221o/sky130_fd_sc_lp__a221o.symbol.v | 1,394 | module MODULE1 (
input VAR8,
input VAR2,
input VAR6,
input VAR10,
input VAR1,
output VAR5
);
supply1 VAR4;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_5/ab882192/src/BCHEncoderCommandChannel.v | 8,035 | module MODULE1
(
parameter VAR5 = 32 ,
parameter VAR31 = 32 ,
parameter VAR23 = 16 ,
parameter VAR33 = 2
)
(
VAR16 ,
VAR15 ,
VAR14 ,
VAR26 ,
VAR39 ,
VAR35 ,
VAR7 ,
VAR30 ,
VAR32 ,
VAR29 ,
VAR8 ,
VAR17 ,
VAR27 ,
VAR20 ,
VAR38 ,
VAR9 ,
VAR21 ,
VAR37 ,
VAR3
);
input VAR16 ;
input VAR15 ;
input [5:0] VAR14 ;
input [4:0] VA... | gpl-3.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/etc/hardware/nes_snes_controller/nes_controller.v | 6,396 | module MODULE1(
VAR9, VAR26, VAR2, VAR20, VAR12 );
input VAR26;
input VAR20;
output VAR9;
output VAR2;
output [7:0] VAR12;
reg [7:0] VAR23; reg VAR16; reg pulse; reg VAR19; reg [17:0] VAR18;
reg [5:0] VAR25;
parameter VAR10 = 1;
parameter VAR3 = 2;
parameter VAR27 = 3;
parameter VAR5 = 4;
parameter VAR21 = 5;
parameter... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22o/sky130_fd_sc_hvl__a22o.behavioral.pp.v | 2,162 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR2 ,
VAR13 ,
VAR11 ,
VAR19,
VAR15,
VAR16 ,
VAR12
);
output VAR6 ;
input VAR4 ;
input VAR2 ;
input VAR13 ;
input VAR11 ;
input VAR19;
input VAR15;
input VAR16 ;
input VAR12 ;
wire VAR8 ;
wire VAR9 ;
wire VAR14 ;
wire VAR3;
and VAR18 (VAR8 , VAR13, VAR11 );
and VAR10 (VAR9 , VAR4, VAR2 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_mux_4to2/sky130_fd_sc_ms__udp_mux_4to2.blackbox.v | 1,298 | module MODULE1 (
VAR2 ,
VAR4,
VAR1,
VAR6,
VAR5,
VAR3,
VAR7
);
output VAR2 ;
input VAR4;
input VAR1;
input VAR6;
input VAR5;
input VAR3;
input VAR7;
endmodule | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/pcie_command_rec_fifo.v | 13,653 | module MODULE1(
rst,
VAR24,
VAR289,
din,
VAR327,
VAR20,
dout,
VAR103,
VAR310,
VAR285,
VAR220,
VAR32,
VAR184
);
input rst;
input VAR24;
input VAR289;
input [127 : 0] din;
input VAR327;
input VAR20;
output [127 : 0] dout;
output VAR103;
output VAR310;
output VAR285;
output VAR220;
output [3 : 0] VAR32;
output [3 : 0] VAR... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/example_design/rtl/traffic_gen/cmd_prbs_gen.v | 10,574 | module MODULE1 #
(
parameter VAR20 = 100,
parameter VAR16 = "VAR1",
parameter VAR26 = 8,
parameter VAR23 = 29,
parameter VAR4 = 32,
parameter VAR3 = "VAR15", parameter VAR8 = 64, parameter VAR24 = 32,
parameter VAR13 = 32'hFFFFD000,
parameter VAR21 = 32'h00002000,
parameter VAR28 = 32'h00002000,
parameter VAR9 = 32'h00... | lgpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/top/N2x0/u2plus.v | 15,172 | module MODULE1
(
input VAR12, input VAR105,
input VAR169, input VAR11,
input VAR22, input VAR132,
input VAR137, input VAR47,
input VAR120, input VAR90,
input VAR60, input VAR99,
input VAR251, input VAR29,
input VAR140, input VAR18,
input VAR297, input VAR121,
input VAR230, input VAR308,
input VAR33, input VAR170,
input... | gpl-2.0 |
hightoon/Sora | FPGA/MIMO/ip_cores/ddr2_memory_interface/rtl/mem_interface_top.v | 8,011 | module MODULE1 #
(
parameter VAR46 = 3, parameter VAR11 = 1, parameter VAR29 = 1, parameter VAR66 = 10, parameter VAR17 = 1, parameter VAR18 = 1, parameter VAR4 = 0, parameter VAR63 = 9, parameter VAR47 = 72, parameter VAR61 = 8, parameter VAR57 = 9, parameter VAR59 = 7, parameter VAR22 = 4, parameter VAR33 = 1, parame... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_pr/sky130_fd_sc_ls__udp_dff_pr.blackbox.v | 1,249 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR1 ,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR1 ;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221oi/sky130_fd_sc_ms__a221oi.functional.pp.v | 2,207 | module MODULE1 (
VAR17 ,
VAR16 ,
VAR13 ,
VAR15 ,
VAR11 ,
VAR10 ,
VAR1,
VAR5,
VAR14 ,
VAR20
);
output VAR17 ;
input VAR16 ;
input VAR13 ;
input VAR15 ;
input VAR11 ;
input VAR10 ;
input VAR1;
input VAR5;
input VAR14 ;
input VAR20 ;
wire VAR7 ;
wire VAR9 ;
wire VAR6 ;
wire VAR18;
and VAR19 (VAR7 , VAR15, VAR11 );
and VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill/sky130_fd_sc_ms__fill.pp.symbol.v | 1,175 | module MODULE1 (
input VAR1 ,
input VAR2,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
mistryalok/Zedboard | learning/training/MSD/s07/mycore/ip_repo/sample_generator_1.0/hdl/sample_generator_v1_0.v | 2,134 | module MODULE1 #
(
parameter integer VAR23 = 32,
parameter integer VAR20 = 32,
parameter integer VAR2 = 32
)
(
input [7:0] VAR19,
input VAR14,
input VAR29,
input wire VAR6,
input wire VAR7,
output wire VAR30,
input wire [VAR23-1 : 0] VAR16,
input wire [(VAR23/8)-1 : 0] VAR18,
input wire VAR3,
input wire VAR31,
input wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1.functional.v | 1,309 | module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
wire VAR4;
buf VAR1 (VAR4, VAR5 );
buf VAR2 (VAR3 , VAR4 );
endmodule | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_SLAVE/source_code/freedm_bus_slave/fb_slave_mac.v | 14,347 | module MODULE1 (VAR94, VAR33, VAR3, VAR17, VAR55, VAR2, VAR66, VAR16, VAR71,
VAR78, VAR48, VAR74, VAR21, VAR98, VAR6, VAR24,
VAR29, VAR60, VAR22, VAR79,
VAR53, VAR70, VAR51, VAR49, VAR85, VAR30, VAR76, VAR96, VAR47,
VAR91, VAR40, VAR77, VAR36
);
input VAR94;
input VAR33;
input VAR3;
input VAR17; input [3:0] VAR55; inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp.pp.symbol.v | 1,332 | module MODULE1 (
input VAR4 ,
input VAR1 ,
input VAR7,
output VAR6,
input VAR3 ,
input VAR5,
input VAR8,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/diode/sky130_fd_sc_lp__diode_0.v | 1,978 | module MODULE1 (
VAR1,
VAR3 ,
VAR5 ,
VAR7 ,
VAR4
);
input VAR1;
input VAR3 ;
input VAR5 ;
input VAR7 ;
input VAR4 ;
VAR2 VAR6 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR1
);
input VAR1;
supply1 VAR3;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR4 ;
VAR2 VAR6 (
.VAR1(VA... | apache-2.0 |
joaocarlos/udlx-verilog | rtl/pipeline/registers/id_ex_reg.v | 6,543 | module MODULE1
parameter VAR27 = 32,
parameter VAR28 = 20,
parameter VAR43 = 32,
parameter VAR50 = 6,
parameter VAR12 = 5,
parameter VAR26 = 5,
parameter VAR13 = 16,
parameter VAR32 = 26
)
(
input clk,
input VAR11,
input en,
input VAR22,
input [VAR43-1:0] VAR48,
input [VAR43-1:0] VAR54,
input [VAR28-1:0] VAR47,
input [... | lgpl-3.0 |
colinww/spi-core-generator | source/reg_slice.v | 5,790 | module MODULE1 (
VAR4,
VAR19, VAR14,
VAR5, VAR38, VAR32, VAR6, VAR12, VAR30, VAR16
);
parameter VAR11 = 16;
input VAR5; input VAR38; input VAR32; input [VAR11-1:0] VAR6; output [VAR11-1:0] VAR4; input VAR12; input VAR30; input VAR16; inout VAR19; inout [VAR11-1:0] VAR14;
wire VAR34, VAR29, VAR39, VAR23;
VAR31 VAR10(.VA... | gpl-3.0 |
masc-ucsc/cmpe220fall16 | rtl/net_2core2dr.v | 58,018 | module MODULE1(
input clk
,input reset
,input logic VAR212
,output logic VAR42
,input VAR334 VAR48
,output logic VAR368
,input logic VAR165
,output VAR87 VAR270
,input VAR180
,output VAR234
,input VAR273 VAR248
,input logic VAR355
,output logic VAR294
,input VAR322 VAR83
,output logic VAR388
,input logic VAR238
,output... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_3.behavioral.v | 1,108 | module MODULE1( VAR5, VAR2 );
input VAR5;
output VAR2;
VAR4 VAR3(.VAR5(VAR5),.VAR2(VAR2));
VAR4 VAR1(.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
vad-rulezz/megabot | minsoc/prj/src/blackboxes/adbg_top.v | 4,176 | module MODULE1(
VAR50,
VAR11,
VAR24,
VAR13,
VAR36,
VAR31,
VAR37,
VAR14,
VAR26
,
VAR21,
VAR39,
VAR38,
VAR22,
VAR33,
VAR7,
VAR52,
VAR32,
VAR56,
VAR12,
VAR6,
VAR10,
VAR46,
VAR53
,
VAR3,
VAR16,
VAR49,
VAR34,
VAR2,
VAR51,
VAR43,
VAR19,
VAR45,
VAR4
,
VAR8,
VAR30,
VAR29,
VAR17,
VAR41,
VAR1,
VAR27,
VAR42,
VAR25,
VAR23
,
VAR21,... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_1.behavioral.pp.v | 3,372 | module MODULE1( VAR8, VAR1, VAR5, VAR9, VAR10, VAR4, VAR2, VAR6 );
input VAR4, VAR10, VAR1, VAR8, VAR9;
inout VAR2, VAR6;
output VAR5;
VAR11 VAR3(.VAR8(VAR8),.VAR1(VAR1),.VAR5(VAR5),.VAR9(VAR9),.VAR10(VAR10),.VAR4(VAR4),.VAR2(VAR2),.VAR6(VAR6));
VAR11 VAR7(.VAR8(VAR8),.VAR1(VAR1),.VAR5(VAR5),.VAR9(VAR9),.VAR10(VAR10),.... | apache-2.0 |
quartushaters/project | M1/Part 1/rominout2.v | 9,761 | module MODULE1 (
VAR13,
VAR60,
VAR47,
VAR53,
VAR3);
input [8:0] VAR13;
input [8:0] VAR60;
input VAR47;
output [31:0] VAR53;
output [31:0] VAR3;
tri1 VAR47;
wire [31:0] VAR20;
wire [31:0] VAR63;
wire VAR44 = 1'h0;
wire [31:0] VAR6 = 32'h0;
wire [31:0] VAR3 = VAR20[31:0];
wire [31:0] VAR53 = VAR63[31:0];
VAR21 VAR19 (
.V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrtp/sky130_fd_sc_hvl__dfrtp.functional.v | 1,651 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR11 ,
VAR9
);
output VAR5 ;
input VAR6 ;
input VAR11 ;
input VAR9;
wire VAR2;
wire VAR4;
not VAR1 (VAR4 , VAR9 );
VAR10 VAR7 VAR3 (VAR2 , VAR11, VAR6, VAR4 );
buf VAR8 (VAR5 , VAR2 );
endmodule | apache-2.0 |
ptracton/wb_dsp | rtl/fifo.v | 2,667 | module MODULE1 (
VAR1, VAR9, VAR2, VAR13,
VAR8, VAR7, VAR6, VAR14, VAR10
) ;
parameter VAR11 = 32;
parameter VAR5 = 16;
input VAR8;
input VAR7;
input VAR6;
input VAR14;
input [VAR11-1:0] VAR10;
output wire [VAR11-1:0] VAR1;
output wire VAR9;
output wire VAR2;
output reg [7:0] VAR13;
reg [7:0] VAR3;
reg [7:0] VAR4;
reg ... | mit |
zeldin/iceGDROM | fpga/source/avr/avr109rx.v | 1,728 | module MODULE1 (
input rst,
input clk,
output[7:0] VAR7,
output VAR17,
input VAR16,
input VAR12
);
parameter VAR15 = 1000000;
parameter VAR4 = 19200;
function integer VAR1;
input integer VAR10;
begin
VAR10 = VAR10-1;
for (VAR1=0; VAR10>0; VAR1=VAR1+1)
VAR10 = VAR10>>1;
end
endfunction
localparam VAR13 = (VAR15 / VAR4);... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/8-way/src/vivado_ip_dram/phy/mig_7series_v2_3_ddr_phy_wrlvl_off_delay.v | 8,955 | module MODULE1 #
(
parameter VAR46 = 100,
parameter VAR21 = 3636,
parameter VAR32 = 2,
parameter VAR11 = 4,
parameter VAR43= 46,
parameter VAR45 = 3,
parameter VAR30 = 8,
parameter VAR42 = 3
)
(
input clk,
input rst,
input VAR40,
input VAR35,
output reg [VAR45:0] VAR17,
output reg VAR38,
output reg VAR19,
output reg VA... | mit |
fbalakirev/red-pitaya-notes | cores/axis_cdc_variable_v1_0/axis_cdc_variable.v | 1,648 | module MODULE1 #
(
parameter integer VAR9 = 32
)
(
input wire VAR1,
input wire VAR8,
input wire VAR7,
input wire [VAR9-1:0] VAR12,
input wire VAR4,
output wire [VAR9-1:0] VAR2,
output wire VAR11
);
reg [VAR9-1:0] VAR5;
reg VAR6, VAR3;
reg VAR14;
reg [2:0] VAR10;
wire VAR13;
always @(posedge VAR1)
VAR14 <= VAR14 ^ VAR13... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_2.behavioral.v | 1,322 | module MODULE1( VAR2, VAR3, VAR1, VAR4, VAR5 );
input VAR2, VAR3, VAR1, VAR4;
output VAR5;
VAR8 VAR6(.VAR2(VAR2),.VAR3(VAR3),.VAR1(VAR1),.VAR4(VAR4),.VAR5(VAR5));
VAR8 VAR7(.VAR2(VAR2),.VAR3(VAR3),.VAR1(VAR1),.VAR4(VAR4),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1.behavioral.pp.v | 1,768 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR6,
VAR5
);
output VAR8 ;
input VAR7 ;
input VAR6;
input VAR5;
wire VAR10 ;
wire VAR2;
not VAR4 (VAR10 , VAR7 );
VAR1 VAR9 (VAR2, VAR10, VAR6, VAR5);
buf VAR3 (VAR8 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/conb/sky130_fd_sc_lp__conb.blackbox.v | 1,238 | module MODULE1 (
VAR4,
VAR1
);
output VAR4;
output VAR1;
supply1 VAR6;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd2/sky130_fd_sc_ls__tapvgnd2.blackbox.v | 1,256 | module MODULE1 ();
supply1 VAR4;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_2.behavioral.pp.v | 1,868 | module MODULE1( VAR7, VAR6, VAR8, VAR3, VAR1, VAR9, VAR10 );
input VAR8, VAR7, VAR3, VAR1;
inout VAR9, VAR10;
output VAR6;
VAR4 VAR2(.VAR7(VAR7),.VAR6(VAR6),.VAR8(VAR8),.VAR3(VAR3),.VAR1(VAR1),.VAR9(VAR9),.VAR10(VAR10));
VAR4 VAR5(.VAR7(VAR7),.VAR6(VAR6),.VAR8(VAR8),.VAR3(VAR3),.VAR1(VAR1),.VAR9(VAR9),.VAR10(VAR10)); | apache-2.0 |
MarcoVogt/basil | firmware/modules/utils/rgmii_io.v | 11,751 | module MODULE1
(
output wire [3:0] VAR34,
output wire VAR56,
output wire VAR4,
input wire [3:0] VAR66,
input wire VAR35,
input wire [7:0] VAR13, input wire VAR2,
input wire VAR33,
output wire VAR39,
output wire VAR50,
output reg [7:0] VAR69, output reg VAR19, output reg VAR7,
output reg VAR44,
output reg [1:0] VAR14,
o... | bsd-3-clause |
rafalmiel/fpga | tron/pll_bb.v | 12,325 | module MODULE1 (
VAR3,
VAR4,
VAR2,
VAR1,
VAR5);
input VAR3;
input VAR4;
output VAR2;
output VAR1;
output VAR5;
tri0 VAR3;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p.symbol.v | 1,374 | module MODULE1 (
input VAR3 ,
output VAR4 ,
input VAR7
);
supply1 VAR5;
supply1 VAR8 ;
supply0 VAR9 ;
supply1 VAR6;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.cache/ip/2018.2/653f640df9678210/gcd_zynq_snick_processing_system7_0_0_stub.v | 5,426 | module MODULE1(VAR24, VAR16, VAR44, VAR4,
VAR6, VAR70, VAR39, VAR59, VAR2,
VAR7, VAR71, VAR10, VAR36, VAR11,
VAR1, VAR46, VAR48, VAR61,
VAR63, VAR49, VAR23, VAR43, VAR27,
VAR19, VAR50, VAR62, VAR58, VAR34,
VAR25, VAR5, VAR26, VAR41, VAR69,
VAR65, VAR33, VAR35, VAR57, VAR52,
VAR21, VAR47, VAR45, VAR8, VAR56, VAR60,
VAR1... | mit |
qeedquan/fpga | de2-115/nios_lights/lights/synthesis/submodules/lights_nios2_qsys_0_jtag_debug_module_tck.v | 8,269 | module MODULE1 (
VAR35,
VAR20,
VAR11,
VAR39,
VAR13,
VAR19,
VAR21,
VAR9,
VAR28,
VAR30,
VAR2,
VAR38,
VAR33,
VAR8,
VAR4,
VAR7,
VAR17,
VAR12,
VAR15,
VAR10,
VAR40,
VAR25,
VAR24,
VAR34,
VAR22,
VAR36,
VAR29,
VAR18,
VAR14,
VAR16,
VAR27
)
;
output [ 1: 0] VAR29;
output VAR18;
output [ 37: 0] VAR14;
output VAR16;
output VAR27;
i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_pwrgood_pp_g/sky130_fd_sc_hd__udp_pwrgood_pp_g.symbol.v | 1,285 | module MODULE1 (
input VAR1 ,
output VAR3,
input VAR2
);
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | example/S10DX_DK/fpga_10g/rtl/debounce_switch.v | 2,595 | module MODULE1 #(
parameter VAR5=1, parameter VAR6=3, parameter VAR3=125000 )(
input wire clk,
input wire rst,
input wire [VAR5-1:0] in,
output wire [VAR5-1:0] out
);
reg [23:0] VAR2 = 24'd0;
reg [VAR6-1:0] VAR1[VAR5-1:0];
reg [VAR5-1:0] state;
assign out = state;
integer VAR4;
always @(posedge clk or posedge rst) begi... | mit |
wyvernSemi/lm32fpga | HDL/rtl/usb_jtag_cmd.v | 5,160 | module MODULE1 (
VAR44,
VAR39,
VAR11,
VAR15,
VAR10,
VAR23,
VAR28,
VAR5,
VAR9,
VAR22,
VAR18,
VAR29,
VAR45,
VAR36,
VAR27,
VAR46,
VAR21,
VAR37,
VAR34,
VAR17,
VAR6,
VAR41,
VAR13,
VAR2,
VAR43
);
input VAR44;
input VAR39;
input VAR23;
input VAR10;
input VAR15;
output VAR11;
output [9:0] VAR17;
output [7:0] VAR34;
input [15:0... | gpl-3.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/source/rtl/Shift_left_logical.v | 1,107 | module MODULE1
(
input wire [VAR3-1:0] VAR14,
input wire VAR11,
input wire VAR12,
output wire [VAR3-1:0] VAR4
);
genvar VAR1;
generate for (VAR1=VAR7; VAR1<=0 ; VAR1=VAR1-1) begin
case (VAR1==1)
1:begin
VAR2 #(.VAR8(1)) VAR13(
.VAR10(VAR11),
.VAR6 (VAR14[VAR1-1]),
.VAR5 (VAR12),
.VAR9 (VAR4[VAR1])
);
end
default:begin
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31oi/sky130_fd_sc_ls__a31oi.pp.symbol.v | 1,374 | module MODULE1 (
input VAR8 ,
input VAR3 ,
input VAR9 ,
input VAR1 ,
output VAR7 ,
input VAR4 ,
input VAR6,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtp/sky130_fd_sc_ls__dlrtp.symbol.v | 1,428 | module MODULE1 (
input VAR2 ,
output VAR8 ,
input VAR7,
input VAR4
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/up_adc_common.v | 14,403 | module MODULE1 #(
parameter VAR67 = 0,
parameter VAR103 = 0,
parameter VAR70 = 6'h00,
parameter VAR49 = 0,
parameter VAR94 = 0,
parameter VAR51 = 0,
parameter VAR2 = 0) (
output VAR30,
input VAR50,
output VAR73,
output VAR27,
output VAR34,
output VAR44,
input VAR48,
input VAR106,
input VAR100,
input [31:0] VAR105,
outp... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v | 12,129 | module MODULE1(
clk, rst,
VAR33, VAR18, VAR22, VAR5, VAR23,
VAR54, VAR9, VAR48, VAR20,
VAR40, VAR1, VAR17, VAR47, VAR21,
VAR45, VAR26, VAR2,
VAR29, VAR52, VAR24, VAR8, VAR38, VAR39
);
parameter VAR49 = VAR37;
parameter VAR44 = VAR37;
input clk;
input rst;
input VAR33;
input VAR18;
input VAR22;
input [VAR44-1:0] VAR5;
i... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2b/sky130_fd_sc_hdll__or2b.pp.blackbox.v | 1,289 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR3 ,
VAR4,
VAR1,
VAR5 ,
VAR2
);
output VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR4;
input VAR1;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/lsu/rtl/lsu_tagdp.v | 7,914 | module MODULE1(
VAR27, VAR54, VAR17,
VAR26, VAR32, VAR56, VAR47, VAR2, VAR24,
VAR3, VAR48, VAR9,
VAR46, VAR40, VAR55,
VAR15, VAR45, VAR4,
VAR49
);
input VAR26;
input VAR32;
input VAR56;
output VAR27;
input [47:3] VAR47 ;
input VAR2;
input [3:0] VAR24; input [29:0] VAR3; input [29:0] VAR48; input [29:0] VAR9; input [29:... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.behavioral.pp.v | 1,174 | module MODULE1( VAR5, VAR2, VAR6, VAR1 );
input VAR5;
inout VAR6, VAR1;
output VAR2;
VAR7 VAR4(.VAR5(VAR5),.VAR2(VAR2),.VAR6(VAR6),.VAR1(VAR1));
VAR7 VAR3(.VAR5(VAR5),.VAR2(VAR2),.VAR6(VAR6),.VAR1(VAR1)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_1.behavioral.pp.v | 1,784 | module MODULE1( VAR11, VAR6, VAR4, VAR2, VAR7 );
input VAR6, VAR11;
inout VAR2, VAR7;
output VAR4;
reg VAR10;
VAR1 VAR9(.VAR11(VAR11),.VAR6(VAR6),.VAR4(VAR4),.VAR2(VAR2),.VAR7(VAR7),.VAR10(VAR10));
VAR1 VAR8(.VAR11(VAR11),.VAR6(VAR6),.VAR4(VAR4),.VAR2(VAR2),.VAR7(VAR7),.VAR10(VAR10));
not VAR3(VAR12,VAR6);
buf VAR13(VA... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v | 17,487 | module MODULE1(
clk, rst, VAR4,
VAR32, VAR17, VAR46, VAR25, VAR2, VAR9, din, dout,
VAR35, VAR8, VAR31, VAR45, VAR33, VAR43
);
input clk;
input rst;
input VAR4;
input VAR17;
input [15:0] VAR32;
input [3:0] VAR46;
output VAR25; reg VAR25;
output VAR2; reg VAR2;
output VAR9; reg VAR9;
input din;
output dout;
reg dout;
inp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfstp/sky130_fd_sc_hd__sdfstp.pp.symbol.v | 1,497 | module MODULE1 (
input VAR10 ,
output VAR7 ,
input VAR3,
input VAR9 ,
input VAR4 ,
input VAR5 ,
input VAR2 ,
input VAR1 ,
input VAR6 ,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.v | 2,345 | module MODULE2 (
VAR1 ,
VAR6 ,
VAR10 ,
VAR4 ,
VAR11 ,
VAR9,
VAR7,
VAR5 ,
VAR3
);
output VAR1 ;
input VAR6 ;
input VAR10 ;
input VAR4 ;
input VAR11 ;
input VAR9;
input VAR7;
input VAR5 ;
input VAR3 ;
VAR8 VAR2 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR5(VAR5),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o_m.v | 2,466 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR1 ,
VAR9 ,
VAR3 ,
VAR4 ,
VAR2,
VAR8,
VAR11 ,
VAR5
);
output VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR4 ;
input VAR2;
input VAR8;
input VAR11 ;
input VAR5 ;
VAR6 VAR12 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VA... | apache-2.0 |
toyoshim/tvcl | ram/spartan-3-starterkit/RAM_64Kx8.v | 1,403 | module MODULE1(
VAR13,
VAR11,
VAR7,
VAR15,
VAR2,
VAR16,
VAR5,
VAR17,
VAR14,
VAR9,
VAR1,
VAR10,
VAR6,
VAR8,
VAR4,
VAR3);
output [17:0] VAR13;
output VAR11;
output VAR7;
inout [15:0] VAR15;
output VAR2;
output VAR16;
output VAR5;
inout [15:0] VAR17;
output VAR14;
output VAR9;
output VAR1;
input [15:0] VAR10;
input VAR6;
... | bsd-3-clause |
combinatorylogic/soc | backends/c2/hw/nexys4ddr/3rdparty/uart.v | 2,846 | module MODULE1 #
(
parameter VAR14 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR14-1:0] VAR6,
input wire VAR21,
output wire VAR12,
output wire [VAR14-1:0] VAR11,
output wire VAR20,
input wire VAR8,
input wire VAR16,
output wire VAR17,
output wire VAR1,
output wire VAR13,
output wire VAR19,
output wire VAR5,
i... | mit |
joaocarlos/udlx-verilog | rtl/bootloader/mux_sram.v | 1,291 | module MODULE1
parameter VAR13 = 32,
parameter VAR12 = 20
)
(
input VAR9,
input VAR5,
input [VAR12-1:0] VAR15,
input [VAR13-1:0] VAR7,
input VAR3,
input VAR16,
input [VAR13-1:0] VAR1,
output reg [VAR13-1:0] VAR10,
input [VAR12-1:0] VAR8,
output reg VAR6,
output reg VAR2,
output reg [VAR13-1:0] VAR4,
input [VAR13-1:0] V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon.functional.pp.v | 2,415 | module MODULE1 (
VAR16 ,
VAR14 ,
VAR9,
VAR15 ,
VAR8 ,
VAR1 ,
VAR11 ,
VAR6
);
output VAR16 ;
input VAR14 ;
input VAR9;
input VAR15 ;
input VAR8 ;
input VAR1 ;
input VAR11 ;
input VAR6 ;
wire VAR12 ;
wire VAR4 ;
wire VAR3;
not VAR7 (VAR12 , VAR9 );
and VAR5 (VAR4 , VAR9, VAR14 );
VAR13 VAR10 (VAR3, VAR4, VAR15, VAR1, VAR... | apache-2.0 |
lucasrangit/Robertsons_Multiplier | robsparts.v | 2,238 | module MODULE3 # (parameter VAR3 = 8)
(input clk,
input [VAR3-1:0] in,
output reg [VAR3-1:0] out,
input VAR6,
input VAR10
);
always @ (posedge clk or posedge VAR10)
if (VAR10) out <= 0;
else if (VAR6) out <= in;
else out <= in;
endmodule
module MODULE4 # (parameter VAR3 = 16)
(input clk,
input [VAR3/2-1:0] VAR4,
input ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32oi/sky130_fd_sc_lp__a32oi_m.v | 2,480 | module MODULE2 (
VAR4 ,
VAR12 ,
VAR10 ,
VAR6 ,
VAR3 ,
VAR2 ,
VAR1,
VAR7,
VAR9 ,
VAR11
);
output VAR4 ;
input VAR12 ;
input VAR10 ;
input VAR6 ;
input VAR3 ;
input VAR2 ;
input VAR1;
input VAR7;
input VAR9 ;
input VAR11 ;
VAR5 VAR8 (
.VAR4(VAR4),
.VAR12(VAR12),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1... | apache-2.0 |
sehugg/8bitworkshop | presets/verilog/racing_game.v | 4,156 | module MODULE1(clk, VAR35, VAR11, VAR18, VAR3, VAR29);
input clk;
input VAR3, VAR29;
output VAR35, VAR11;
output [2:0] VAR18;
wire VAR55;
wire [8:0] VAR9;
wire [8:0] VAR37;
reg [7:0] VAR52;
reg [7:0] VAR8;
reg [7:0] VAR5;
reg [7:0] VAR25;
reg [7:0] VAR41 = 128;
reg [7:0] VAR38 = 128;
reg VAR2 = 0;
reg [15:0] VAR4 = 0; ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.behavioral.pp.v | 1,561 | module MODULE1( VAR1, VAR3, VAR2, VAR7, VAR5, VAR9 );
input VAR3, VAR1, VAR7;
inout VAR5, VAR9;
output VAR2;
VAR6 VAR4(.VAR1(VAR1),.VAR3(VAR3),.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5),.VAR9(VAR9));
VAR6 VAR8(.VAR1(VAR1),.VAR3(VAR3),.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5),.VAR9(VAR9)); | apache-2.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/altera_reset_synchronizer.v | 3,479 | module MODULE1
parameter VAR4 = 1,
parameter VAR6 = 2
)
(
input VAR3 ,
input clk,
output VAR5
);
reg [VAR6-1:0] VAR2;
reg VAR1;
generate if (VAR4) begin
always @(posedge clk or posedge VAR3) begin
if (VAR3) begin
VAR2 <= {VAR6{1'b1}};
VAR1 <= 1'b1;
end
else begin
VAR2[VAR6-2:0] <= VAR2[VAR6-1:1];
VAR2[VAR6-1] <= 0;
VAR... | mit |
xuefei1/ElectronicEngineControl | niosII_system/synthesis/submodules/altera_up_rs232_out_serializer.v | 8,342 | module MODULE1 (
clk,
reset,
VAR7,
VAR17,
VAR14,
VAR11
);
parameter VAR8 = 9; parameter VAR32 = 433;
parameter VAR1 = 216;
parameter VAR2 = 11; parameter VAR22 = 9;
input clk;
input reset;
input [VAR22: 0] VAR7;
input VAR17;
output reg [ 7: 0] VAR14;
output reg VAR11;
wire VAR29;
wire VAR28;
wire VAR10;
wire VAR16;
wir... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA/integracion_fisica/front_end/source/subRecursiveKOA.v | 5,540 | module MODULE1
(
input wire clk,
input wire [VAR11-1:0] VAR16,
input wire [VAR11-1:0] VAR4,
output wire [2*VAR11-1:0] VAR6
);
generate
if (VAR11 <=VAR5 || VAR11 <=VAR32) begin : VAR8
VAR7 #(.VAR11(VAR11))
VAR29 (
.clk(clk),
.VAR16(VAR16),
.VAR4(VAR4),
.VAR6(VAR6)
);
end else begin : VAR17
reg [2*VAR11-1:0] VAR2;
wire [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311oi/sky130_fd_sc_hd__a311oi.functional.pp.v | 2,076 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR5 ,
VAR13 ,
VAR9 ,
VAR17 ,
VAR2,
VAR14,
VAR4 ,
VAR16
);
output VAR8 ;
input VAR7 ;
input VAR5 ;
input VAR13 ;
input VAR9 ;
input VAR17 ;
input VAR2;
input VAR14;
input VAR4 ;
input VAR16 ;
wire VAR6 ;
wire VAR11 ;
wire VAR10;
and VAR3 (VAR6 , VAR13, VAR7, VAR5 );
nor VAR12 (VAR11 , VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlxtp/sky130_fd_sc_hvl__dlxtp.behavioral.v | 1,768 | module MODULE1 (
VAR11 ,
VAR10 ,
VAR12
);
output VAR11 ;
input VAR10 ;
input VAR12;
supply1 VAR5;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR8 ;
reg VAR1 ;
wire VAR9 ;
wire VAR6;
wire VAR3 ;
VAR14 VAR13 (VAR9 , VAR3, VAR6, VAR1, VAR5, VAR4);
buf VAR2 (VAR11 , VAR9 );
endmodule | apache-2.0 |
peteasa/oh | src/mio/hdl/mrx.v | 4,335 | module MODULE1 (
VAR7, VAR35, VAR29, VAR13, VAR28, VAR9,
clk, VAR34, VAR1, VAR25, VAR36, VAR5, VAR31,
VAR4, VAR12, VAR6
);
parameter VAR26 = 104; parameter VAR14 = 8; parameter VAR20 = 32; parameter VAR11 = "VAR32";
input clk; input VAR34; input [7:0] VAR1; input VAR25;
input VAR36;
input VAR5;
output VAR7; output VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/diode/sky130_fd_sc_lp__diode.functional.pp.v | 1,200 | module MODULE1 (
VAR3,
VAR1 ,
VAR4 ,
VAR2 ,
VAR5
);
input VAR3;
input VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR5 ;
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cpu/apu/apu_mixer.v | 6,669 | module MODULE1
(
input wire VAR1, input wire VAR5, input wire [3:0] VAR8, input wire [3:0] VAR6, input wire [3:0] VAR12, input wire [3:0] VAR15, input wire [3:0] VAR19, output wire VAR2 );
wire [3:0] VAR7;
wire [3:0] VAR11;
wire [3:0] VAR17;
wire [3:0] VAR4;
reg [4:0] VAR14;
reg [5:0] VAR20;
reg [6:0] VAR10;
reg [5:0] ... | mit |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_clkgen.v | 6,955 | module MODULE1 (
VAR2,
VAR25,
VAR10,
VAR13,
VAR11,
VAR27,
VAR8,
VAR17,
VAR6,
VAR33,
VAR7,
VAR3,
VAR29,
VAR4,
VAR18,
VAR32,
VAR26,
VAR14,
VAR15);
localparam VAR24 = 32'h00040063;
parameter VAR22 = 0;
output VAR2;
output VAR25;
output VAR10;
output VAR13;
output [11:0] VAR11;
output [15:0] VAR27;
input [15:0] VAR8;
input... | lgpl-3.0 |
fpgasystems/Centaur | rtl/fthread_shell/csr_file.v | 7,159 | module MODULE1(
input wire clk,
input wire VAR5,
output wire VAR7,
output reg VAR3,
output reg [31:0] VAR22,
input wire VAR25,
output reg VAR12,
output reg [31:0] VAR26,
input wire VAR23,
output reg VAR2,
output reg [31:0] VAR6,
input wire VAR1,
input wire VAR20,
input wire [13:0] VAR14,
input wire [31:0] VAR10
);
loca... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311a/sky130_fd_sc_hs__o311a_2.v | 2,295 | module MODULE2 (
VAR1 ,
VAR6 ,
VAR8 ,
VAR7 ,
VAR3 ,
VAR10 ,
VAR9,
VAR5
);
output VAR1 ;
input VAR6 ;
input VAR8 ;
input VAR7 ;
input VAR3 ;
input VAR10 ;
input VAR9;
input VAR5;
VAR2 VAR4 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxtp/sky130_fd_sc_ls__sdfxtp.pp.blackbox.v | 1,363 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR3 ,
VAR7 ,
VAR8 ,
VAR9,
VAR4,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR6 ;
input VAR3 ;
input VAR7 ;
input VAR8 ;
input VAR9;
input VAR4;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/generic/uart_fifo.v | 4,422 | module MODULE1 (
clk,
rst,
VAR23,
VAR20,
VAR28,
VAR32,
VAR19,
VAR11,
VAR8,
VAR3,
VAR2,
VAR10,
VAR12
);
parameter VAR24 = 10;
input clk;
input rst;
output wire [31:0] VAR23;
input VAR20;
output wire [31:0] VAR28;
input [7:0] VAR32;
input VAR19;
output reg [31:0] VAR11;
output wire [7:0] VAR8;
output reg VAR3;
output reg... | mit |
efabless/openlane | designs/jpeg_encoder/src/jpeg_rle1.v | 8,951 | module MODULE1(clk, rst, VAR5, VAR1, din, VAR17, VAR12, VAR3, VAR11, VAR4);
input clk; input rst; input VAR5; input VAR1;
input [11:0] din;
output [ 3:0] VAR17; output [ 3:0] VAR12; output [11:0] VAR3; output VAR11; output VAR4;
reg [ 3:0] VAR17, VAR12;
reg [11:0] VAR3;
reg VAR11, VAR4;
reg [5:0] VAR15;
reg [3:0] VAR6;... | apache-2.0 |
wyvernSemi/lm32fpga | HDL/rtl/Sdram_Controller/sdr_data_path.v | 1,988 | module MODULE1(
VAR6,
VAR9,
VAR5,
VAR8,
VAR1,
VAR4
);
input VAR6; input VAR9; input [VAR7-1:0] VAR5; input [VAR7/8-1:0] VAR8; output [VAR7-1:0] VAR1;
output [VAR7/8-1:0] VAR4; reg [VAR7/8-1:0] VAR4;
reg [VAR7-1:0] VAR10;
reg [VAR7-1:0] VAR3;
reg [VAR7/8-1:0] VAR2;
always @(posedge VAR6 or negedge VAR9)
begin
if (VAR9 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222o/sky130_fd_sc_ms__a222o.behavioral.v | 1,786 | module MODULE1 (
VAR1 ,
VAR12,
VAR18,
VAR7,
VAR6,
VAR17,
VAR2
);
output VAR1 ;
input VAR12;
input VAR18;
input VAR7;
input VAR6;
input VAR17;
input VAR2;
supply1 VAR10;
supply0 VAR14;
supply1 VAR11 ;
supply0 VAR13 ;
wire VAR5 ;
wire VAR16 ;
wire VAR15 ;
wire VAR8;
and VAR4 (VAR5 , VAR7, VAR6 );
and VAR9 (VAR16 , VAR12,... | apache-2.0 |
AquarHEAD/stopwatch | src/regfile.v | 1,076 | module MODULE1(
input wire VAR14, VAR18,
input wire[3:0] address,
input wire[23:0] VAR41,
output wire[23:0] VAR23);
wire[15:0] VAR6;
wire[15:0] clk;
assign clk[15:0] = {16{VAR14}} & VAR6;
wire[23:0] VAR27, VAR29, VAR40, VAR39, VAR13,
VAR22, VAR3, VAR33, VAR4, VAR2, VAR12,
VAR9, VAR19, VAR36, VAR31, VAR11;
VAR15 VAR21(a... | mit |
ptracton/wb_soc_template | rtl/LM32/rtl/lm32_dp_ram.v | 4,840 | module MODULE1 (
VAR14,
VAR6,
VAR15,
VAR2,
VAR17,
VAR9,
VAR10,
VAR19,
VAR7,
VAR8,
VAR20,
VAR12
);
parameter VAR5 = 1; parameter VAR16 = 1; parameter VAR11 = "VAR4";
input VAR14; input VAR6;
input VAR15; input VAR2; input [VAR16-1:0] VAR17; input [VAR16-1:0] VAR9; input [VAR5-1:0] VAR10; input [VAR5-1:0] VAR19; input VA... | mit |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/bv-288/lookup.v | 2,883 | module MODULE1(
clk,
reset,
VAR2,
VAR13,
VAR29,
VAR23,
VAR5,
VAR14,
VAR1,
VAR16,
VAR27,
VAR21
);
input clk;
input reset;
input VAR2;
input VAR13;
input [31:0] VAR29;
input VAR23;
output wire VAR5;
output wire [31:0] VAR14;
input VAR1;
input [287:0] VAR16;
output wire VAR27;
output wire [5:0] VAR21;
wire VAR28[0:3];
wir... | apache-2.0 |
peteasa/oh | src/gpio/dv/dut_gpio.v | 2,397 | module MODULE1(
VAR7, VAR20, VAR10, VAR22, VAR21,
VAR6, VAR16, VAR13, VAR11, VAR5, VAR2, VAR14, VAR23
);
parameter VAR8 = 32;
parameter VAR26 = 32;
parameter VAR12 = 2;
parameter VAR24 = 12;
parameter VAR18 = 6;
parameter VAR17 = 12;
parameter VAR9 = 104;
parameter VAR3 = 32;
input VAR6;
input VAR16;
input VAR13;
input... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4bb/sky130_fd_sc_hd__and4bb_2.v | 2,323 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR10 ,
VAR2 ,
VAR11 ,
VAR5,
VAR9,
VAR7 ,
VAR8
);
output VAR4 ;
input VAR1 ;
input VAR10 ;
input VAR2 ;
input VAR11 ;
input VAR5;
input VAR9;
input VAR7 ;
input VAR8 ;
VAR6 VAR3 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR7(VAR7),
.... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_rml.v | 36,414 | module MODULE1 (
VAR173, VAR199, VAR161,
VAR117, VAR50, VAR16, VAR121,
VAR262, VAR263, VAR158, VAR112,
VAR219, VAR97, VAR59,
VAR228, VAR146, VAR3,
VAR226, VAR73, VAR191,
VAR229, VAR15, VAR165,
VAR261, VAR245, VAR204,
VAR100, VAR157, VAR238,
VAR147, VAR137, VAR272,
VAR35, VAR223, VAR193,
VAR217, VAR19, VAR11,
VAR208, VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4bb/sky130_fd_sc_ls__or4bb_2.v | 2,314 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR1 ,
VAR2 ,
VAR10 ,
VAR8,
VAR3,
VAR11 ,
VAR5
);
output VAR7 ;
input VAR9 ;
input VAR1 ;
input VAR2 ;
input VAR10 ;
input VAR8;
input VAR3;
input VAR11 ;
input VAR5 ;
VAR4 VAR6 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR11(VAR11),
.... | apache-2.0 |
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