repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/controller/rank_mach.v | 11,023 | module MODULE1 #
(
parameter VAR26 = "8",
parameter VAR39 = 4,
parameter VAR40 = "VAR7",
parameter VAR31 = 40,
parameter VAR53 = 4,
parameter VAR41 = 2,
parameter VAR42 = 5,
parameter VAR15 = 30,
parameter VAR19 = 8,
parameter VAR36 = 4,
parameter VAR3 = 4,
parameter VAR22 = 20,
parameter VAR20 = 16,
parameter VAR18 = ... | lgpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3/alt_ddrx_decoder_40.v | 18,708 | module MODULE1
(
VAR1,
VAR15,
VAR61,
VAR57,
VAR8,
VAR45) ;
input VAR1;
input [38:0] VAR15;
output VAR61;
output VAR57;
output VAR8;
output [31:0] VAR45;
tri0 VAR1;
reg [0:0] VAR47;
reg [0:0] VAR39;
reg [0:0] VAR63;
reg [31:0] VAR7;
wire [63:0] VAR41;
wire VAR18;
wire VAR14;
wire VAR64;
wire VAR10;
wire VAR31;
wire VAR2... | gpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_spram_1024x8.v | 10,444 | module MODULE1(
VAR21, VAR34, VAR16,
clk, rst, VAR14, VAR26, VAR45, addr, VAR46, VAR54
);
parameter VAR9 = 10;
parameter VAR2 = 8;
input VAR21;
input [VAR28 - 1:0] VAR16;
output VAR34;
input clk; input rst; input VAR14; input VAR26; input VAR45; input [VAR9-1:0] addr; input [VAR2-1:0] VAR46; output [VAR2-1:0] VAR54;
as... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp_1.v | 2,451 | module MODULE2 (
VAR7 ,
VAR6 ,
VAR4 ,
VAR9 ,
VAR11 ,
VAR1 ,
VAR12,
VAR3,
VAR10 ,
VAR2
);
output VAR7 ;
output VAR6 ;
input VAR4 ;
input VAR9 ;
input VAR11 ;
input VAR1 ;
input VAR12;
input VAR3;
input VAR10 ;
input VAR2 ;
VAR5 VAR8 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR12... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_2.functional.v | 1,494 | module MODULE1( VAR6, VAR11, VAR3, VAR8, VAR5 );
input VAR5, VAR8, VAR11, VAR6;
output VAR3;
wire VAR18;
not VAR4( VAR18, VAR5 );
wire VAR7;
not VAR9( VAR7, VAR8 );
wire VAR15;
and VAR1( VAR15, VAR18, VAR7 );
wire VAR10;
not VAR12( VAR10, VAR11 );
wire VAR14;
not VAR16( VAR14, VAR6 );
wire VAR2;
and VAR13( VAR2, VAR10,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxbp/sky130_fd_sc_hd__sdfxbp.pp.blackbox.v | 1,398 | module MODULE1 (
VAR10 ,
VAR9 ,
VAR2 ,
VAR4 ,
VAR8 ,
VAR1 ,
VAR5,
VAR6,
VAR7 ,
VAR3
);
output VAR10 ;
output VAR9 ;
input VAR2 ;
input VAR4 ;
input VAR8 ;
input VAR1 ;
input VAR5;
input VAR6;
input VAR7 ;
input VAR3 ;
endmodule | apache-2.0 |
bkboggy/MIPS | D_MEM.v | 1,352 | module MODULE1(input clk, VAR4, VAR6, input [31:0] VAR3, VAR2,
output reg [31:0] VAR5);
reg [31:0] VAR1 [128:0];
begin
begin | mit |
DreamSourceLab/DSLogic-hdl | src/cfg.v | 14,704 | module MODULE1(
input VAR57,
input VAR128,
input VAR45,
input VAR144,
input VAR60,
input VAR113,
input [15:0] VAR21,
input VAR64,
output VAR131,
output VAR78,
output VAR35,
output VAR54,
output VAR58,
output VAR26,
output VAR19,
output VAR88,
output VAR91,
output [23:0] VAR27,
output reg VAR110,
output VAR153,
output [... | gpl-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_fifo.v | 10,267 | module MODULE1 #
(
parameter VAR32 = 4096,
parameter VAR22 = 8,
parameter VAR8 = (VAR22>8),
parameter VAR30 = (VAR22/8),
parameter VAR15 = 1,
parameter VAR18 = 0,
parameter VAR1 = 8,
parameter VAR3 = 0,
parameter VAR7 = 8,
parameter VAR25 = 1,
parameter VAR27 = 1,
parameter VAR14 = 2,
parameter VAR6 = 0,
parameter VAR3... | mit |
audiocircuit/NCSU-Low-Power-RFID | Memory/clock.v | 1,067 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR4,
output reg VAR1,
output reg VAR5
);
reg [8:0] VAR2;
reg [8:0] VAR3;
reg [8:0] VAR6;
always@(posedge clk or negedge reset)
begin
if( ~reset )
begin
VAR1 <= 1;
VAR5 <= 0;
VAR2 <= 0;
VAR3 <= 63;
VAR6 <= 100;
end
else if( VAR4 )
begin
VAR6 <= VAR6;
if( VAR2... | gpl-3.0 |
fredyamalves/Collision-detection-for-a-CPU-FPGA-heterogeneous-System | Verilog design/inputs_mem2.v | 12,766 | module MODULE1 #(VAR46 = 20, VAR21 = 14, VAR56 = 512)
(
input clk,
input VAR40,
output [VAR46-1:0] VAR45,
output [VAR21-1:0] VAR33,
output reg VAR68,
input VAR52,
input VAR28,
input [VAR21-1:0] VAR35,
input [VAR56-1:0] VAR2,
output [VAR56-1:0] VAR61,
input [31:0] VAR6,
output reg VAR18
);
reg VAR37;
reg VAR60;
reg [VAR... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_miss.v | 15,103 | module MODULE1
import VAR68::*;
,parameter VAR16(VAR19)
,parameter VAR16(VAR29)
,parameter VAR16(VAR139)
,parameter VAR16(VAR58)
,parameter VAR59=VAR91(VAR29)
,parameter VAR113=VAR91(VAR139)
,parameter VAR42=VAR91(VAR19>>3)
,parameter VAR36=(VAR29 > 1) ? VAR42+VAR59 : VAR42
,parameter VAR27=(VAR107-VAR113-VAR36)
,param... | bsd-3-clause |
lokisz/openzcore | pippo-0.9/rtl/verilog/lsu_mem2reg.v | 1,774 | module MODULE1(addr, VAR8, VAR7, VAR4);
parameter VAR1 = VAR3;
input [1:0] addr;
input [VAR6-1:0] VAR8;
input [VAR1-1:0] VAR7;
output [VAR1-1:0] VAR4;
reg [VAR1-1:0] VAR4;
reg [VAR1-1:0] VAR5;
always @(addr or VAR7) begin
end
case(addr) else
case(addr) VAR2
2'b00:
VAR5 = VAR7;
2'b01:
VAR5 = {VAR7[23:0], 8'b0};
2'b10:
V... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_1.behavioral.v | 1,267 | module MODULE1( VAR6, VAR5, VAR3, VAR7 );
input VAR7, VAR3, VAR6;
output VAR5;
VAR2 VAR4(.VAR6(VAR6),.VAR5(VAR5),.VAR3(VAR3),.VAR7(VAR7));
VAR2 VAR1(.VAR6(VAR6),.VAR5(VAR5),.VAR3(VAR3),.VAR7(VAR7)); | apache-2.0 |
HeberthVG/papiGB | rtl/dzcpu_ucode_lut.v | 32,294 | module MODULE2
(
input wire[7:0] VAR65,
output reg [9:0] VAR38
);
always @ ( VAR65 )
begin
case ( VAR65 )
default:
VAR38 = 10'd278;
endcase
end
endmodule
module MODULE1
(
input wire[7:0] VAR65,
output reg [8:0] VAR38
);
always @ ( VAR65 )
begin
case ( VAR65 )
8'h7C: VAR38 = 9'd16; 8'h11: VAR38 = 9'd69; 8'h38: VAR38 = 9... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.behavioral.pp.v | 1,084 | module MODULE1( VAR4, VAR3 );
inout VAR4, VAR3;
VAR1 VAR5(.VAR4(VAR4),.VAR3(VAR3));
VAR1 VAR2(.VAR4(VAR4),.VAR3(VAR3)); | apache-2.0 |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T24-uart-tx/uart_tx.v | 5,020 | module MODULE1 (
input wire clk, input wire VAR7, input wire VAR2, input wire [7:0] VAR14, output reg VAR4, output wire ready );
parameter VAR3 = VAR10;
reg VAR13;
wire VAR15;
reg [3:0] VAR9;
reg [7:0] VAR6;
wire VAR8; wire VAR12;
always @(posedge clk)
VAR13 <= VAR2;
always @(posedge clk)
if (VAR2 == 1 && state == VAR1... | gpl-2.0 |
Cognoscan/BoostLogic | verilog/src/receivers/RxUart.v | 3,869 | module MODULE1 #(
parameter VAR18 = 4 )
(
input clk, input rst, input VAR9, input read, input VAR14, output wire [7:0] VAR17, output wire VAR7, output wire VAR4, output wire VAR6 );
reg [7:0] VAR15;
reg [7:0] VAR5; reg [3:0] VAR2;
reg VAR3; reg VAR21;
reg VAR19;
reg VAR8;
reg write;
reg VAR1;
reg VAR10;
reg VAR12;
if (... | apache-2.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_fetchtexel.v | 1,876 | module MODULE1 #(
parameter VAR17 = 2,
parameter VAR12 = 26
) (
input VAR16,
input VAR1,
output VAR3,
input VAR23,
output VAR13,
input [VAR12-5-1:0] VAR4,
output VAR6,
input VAR19,
output [255:0] VAR5,
output reg [VAR12-1:0] VAR11,
output reg VAR2,
input VAR21,
input [63:0] VAR9
);
wire VAR22;
always @(posedge VAR16) b... | lgpl-3.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_pcie_bram_top_7x.v | 8,601 | module MODULE1
parameter VAR16 = "VAR14", parameter VAR23 = 0, parameter [3:0] VAR10 = 4'h1, parameter [5:0] VAR1 = 6'h08,
parameter VAR6 = 31, parameter VAR31 = 24, parameter VAR5 = 1, parameter VAR21 = 2, parameter VAR7 = 1,
parameter VAR32 = 'h1FFF, parameter VAR20 = 1, parameter VAR12 = 2, parameter VAR8 = 1 )
(
in... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N8_R1_P5_syn.v | 2,430 | module MODULE1 ( VAR16, VAR25, VAR19 );
input [7:0] VAR16;
input [7:0] VAR25;
output [8:0] VAR19;
wire VAR11, VAR59, VAR33, VAR58, VAR2,
VAR60, VAR8, VAR65, VAR64, VAR27, VAR44, VAR56, VAR3, VAR6, VAR51, VAR17, VAR7, VAR53, VAR12, VAR30,
VAR62, VAR21;
VAR55 VAR77 ( .VAR4(VAR25[1]), .VAR49(VAR16[1]), .VAR1(VAR11), .VAR7... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2o/sky130_fd_sc_hs__a2bb2o_2.v | 2,336 | module MODULE1 (
VAR5 ,
VAR8,
VAR4,
VAR3 ,
VAR2 ,
VAR9,
VAR7
);
output VAR5 ;
input VAR8;
input VAR4;
input VAR3 ;
input VAR2 ;
input VAR9;
input VAR7;
VAR6 VAR1 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR5 ,
VAR8,
VAR4,
VAR3 ,
VAR2
);
ou... | apache-2.0 |
omicronns/studies-sys-rek | de1-soc-template/v/sdram_pll.v | 17,503 | module MODULE1 (
input wire VAR2, input wire rst, output wire VAR5, output wire VAR3, output wire VAR6, output wire VAR7 );
VAR1 VAR8 (
.VAR2 (VAR2), .rst (rst), .VAR5 (VAR5), .VAR3 (VAR3), .VAR6 (VAR6), .VAR7 (VAR7), .VAR4 () );
endmodule | mit |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_up_video_clipper_drop.v | 8,657 | module MODULE1 (
clk,
reset,
VAR25,
VAR41,
VAR12,
VAR30,
VAR38,
VAR19,
VAR3,
VAR11,
VAR36,
VAR26,
VAR9,
VAR7
);
parameter VAR2 = 15; parameter VAR40 = 0;
parameter VAR35 = 640; parameter VAR43 = 480; parameter VAR33 = 9; parameter VAR24 = 8;
parameter VAR14 = 0;
parameter VAR17 = 0;
parameter VAR5 = 0;
parameter VAR31 ... | gpl-3.0 |
lvd2/zxevo | fpga/sdload/trunk/top.v | 3,797 | module MODULE1(
input VAR48,
output VAR2,
input VAR74,
input VAR44,
input VAR1,
input VAR13,
input VAR56,
input VAR54,
input VAR39,
output VAR50,
output VAR61,
output VAR7,
output VAR4,
inout [7:0] VAR53,
input [15:0] VAR75,
output VAR26,
output VAR29,
output VAR38,
output VAR8,
output VAR49, output VAR71,
output VAR73... | gpl-3.0 |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/03_usb/usb_top.v | 5,048 | module MODULE1(
input VAR22 ,
input VAR12 ,
input VAR11 ,
input VAR17 ,
input VAR16 ,
input VAR8 ,
input [15: 0] VAR9 ,
output VAR10 ,
output [15: 0] VAR31 ,
input VAR19 ,
output [31: 0] VAR37 ,
output VAR38 ,
input VAR21 ,
input [7 : 0] VAR13 ,
output VAR30 ,
input VAR34 ,
output [7 : 0] VAR7 ,
output VAR2 ,
output VA... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_seeed_tft/rtl/seeed_tft_data_writer.v | 11,512 | module MODULE1#(
parameter VAR27 = 12
)(
input rst,
input clk,
output [31:0] VAR45,
input VAR69,
input [7:0] VAR39,
input VAR22,
input [31:0] VAR18,
input [31:0] VAR19,
input [7:0] VAR5,
input VAR51,
input [31:0] VAR80,
input VAR50,
output [1:0] VAR46,
input [1:0] VAR55,
input VAR14,
output [23:0] VAR49,
input [31:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211ai/sky130_fd_sc_lp__o211ai.functional.pp.v | 2,048 | module MODULE1 (
VAR5 ,
VAR11 ,
VAR16 ,
VAR15 ,
VAR8 ,
VAR9,
VAR1,
VAR2 ,
VAR4
);
output VAR5 ;
input VAR11 ;
input VAR16 ;
input VAR15 ;
input VAR8 ;
input VAR9;
input VAR1;
input VAR2 ;
input VAR4 ;
wire VAR12 ;
wire VAR13 ;
wire VAR7;
or VAR3 (VAR12 , VAR16, VAR11 );
nand VAR10 (VAR13 , VAR8, VAR12, VAR15 );
VAR17 V... | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Cache/L1/Data_Ram.v | 2,491 | module MODULE1(
input [6:0] VAR7,
input [3:0] VAR19,
input [31:0] VAR20,
input [4095:0] VAR1,
input VAR14,
input [3:0] VAR26,
output [31:0] VAR5,
output [4095:0] VAR8,
input VAR10
);
wire [127:0] VAR15;
wire [7:0] VAR11 [127:0];
wire [7:0] VAR16 [127:0];
wire [7:0] VAR24 [127:0];
wire [7:0] VAR4 [127:0];
genvar VAR17,V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufinv/sky130_fd_sc_hdll__bufinv.symbol.v | 1,280 | module MODULE1 (
input VAR5,
output VAR2
);
supply1 VAR6;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fme/fme_satd_8x8.v | 19,128 | module MODULE3 (
VAR24,
VAR87
);
parameter VAR53 = VAR185;
input [VAR53-1 : 0] VAR24;
output [VAR53-2 : 0] VAR87;
wire [VAR53-1 : 0] VAR187 ;
assign VAR187 = ({(VAR53-1){VAR24[VAR53-1]}} ^ {VAR24[VAR53-2:0]}) + {{(VAR53-1){1'b0}},VAR24[VAR53-1]};
assign VAR87 = VAR187[VAR53-2:0];
endmodule
module MODULE1 (
VAR210,
VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtn/sky130_fd_sc_hs__dfrtn.blackbox.v | 1,329 | module MODULE1 (
VAR4,
VAR1 ,
VAR2 ,
VAR3
);
input VAR4;
input VAR1 ;
input VAR2 ;
output VAR3 ;
supply1 VAR6;
supply0 VAR5;
endmodule | apache-2.0 |
Triple-Z/COExperiment_Repo | Project_2_OC/SingleCycleCPUOnBoard/regfile.v | 5,746 | module MODULE1(
input clk,
input VAR4,
input [4 :0] VAR6,
input [4 :0] VAR1,
input [4 :0] VAR2,
input [31:0] VAR5,
output reg [31:0] VAR8,
output reg [31:0] VAR7,
input [4 :0] VAR3,
output reg [31:0] VAR11,
input VAR10
);
reg [31:0] VAR9[31:0];
always @(posedge clk)
begin
if (VAR4)
begin
VAR9[VAR2] <= VAR5;
end
if(!VAR... | mit |
sam-falvo/polaris | processor/docs/example/bridge.v | 3,959 | module MODULE1(
input VAR2,
input [1:0] VAR26,
input [2:0] VAR15,
input [63:0] VAR34,
output [63:0] VAR12,
output [7:0] VAR14,
output [63:0] VAR62,
input [63:0] VAR54
);
wire VAR19 = (VAR26 == 2'b00);
wire VAR24 = (VAR26 == 2'b01);
wire VAR55 = (VAR26 == 2'b10);
wire VAR60 = (VAR26 == 2'b11);
wire VAR33 = VAR15[2:0] ==... | mpl-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/DcTile3.v | 13,215 | module MODULE1(
VAR63, reset,
VAR7, VAR43,
VAR39, VAR23,
VAR25, VAR26,
VAR34,
VAR69, VAR18,
VAR48, VAR29,
VAR42, VAR65,
VAR37
);
input VAR63;
input reset;
input[31:0] VAR39; input[63:0] VAR7; input VAR25; input VAR26; input[4:0] VAR34;
output[63:0] VAR43; output[1:0] VAR23;
input[127:0] VAR69; output[127:0] VAR18; outp... | mit |
sh-chris110/chris | FPGA/HPS/db/ip/hps_design/submodules/hps_design_mm_interconnect_0_avalon_st_adapter.v | 6,164 | module MODULE1 #(
parameter VAR10 = 34,
parameter VAR19 = 0,
parameter VAR9 = 34,
parameter VAR14 = 0,
parameter VAR4 = 0,
parameter VAR13 = 0,
parameter VAR17 = 1,
parameter VAR1 = 1,
parameter VAR6 = 0,
parameter VAR20 = 34,
parameter VAR18 = 0,
parameter VAR23 = 1,
parameter VAR24 = 0,
parameter VAR11 = 1,
parameter... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1n/sky130_fd_sc_lp__inputiso1n.symbol.v | 1,389 | module MODULE1 (
input VAR7 ,
output VAR1 ,
input VAR4
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3b/sky130_fd_sc_ls__nand3b.functional.v | 1,401 | module MODULE1 (
VAR6 ,
VAR2,
VAR7 ,
VAR3
);
output VAR6 ;
input VAR2;
input VAR7 ;
input VAR3 ;
wire VAR9 ;
wire VAR1;
not VAR5 (VAR9 , VAR2 );
nand VAR8 (VAR1, VAR7, VAR9, VAR3 );
buf VAR4 (VAR6 , VAR1 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_1.behavioral.v | 8,908 | module MODULE1( VAR44, VAR80, VAR56, VAR82, VAR88 );
input VAR82, VAR56, VAR44, VAR80;
output VAR88;
reg VAR1;
VAR51 VAR27(.VAR44(VAR44),.VAR80(VAR80),.VAR56(VAR56),.VAR82(VAR82),.VAR88(VAR88),.VAR1(VAR1));
VAR51 VAR53(.VAR44(VAR44),.VAR80(VAR80),.VAR56(VAR56),.VAR82(VAR82),.VAR88(VAR88),.VAR1(VAR1));
not VAR57(VAR45,V... | apache-2.0 |
plindstroem/oh | common/hdl/pulse2pulse.v | 1,654 | module MODULE1(
out,
VAR7, VAR2, in, reset
);
input in; input VAR7; output out; input VAR2;
input reset;
wire VAR3;
wire VAR6;
VAR5 VAR5(
.out (VAR3),
.clk (VAR7),
.in (in),
.reset (reset));
VAR4 #(1) VAR4(
.out (VAR6),
.in (VAR3),
.clk (VAR2),
.reset (reset));
VAR1 VAR1(
.out (out),
.clk (VAR2),
.in (VAR6),
.reset (re... | gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab10/lab10/Code/CPU/MCtrl_IO.v | 1,080 | module MODULE1(input clk,
input reset,
input [31:0] VAR7,
input VAR8,
input VAR1,
input VAR16,
output reg VAR20,
output reg VAR15,
output reg[2:0]VAR18,
output [4:0]VAR2,
output reg VAR19,
output reg VAR12,
output reg VAR17,
output reg [1:0]VAR4,
output reg VAR6,
output reg [1:0]VAR14,
output reg VAR9,
output reg [1:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dff_pr/sky130_fd_sc_ms__udp_dff_pr.blackbox.v | 1,249 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR4 ,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR2;
endmodule | apache-2.0 |
vvk/sysrek | martix_multiplier/ipcore_dir/multiply.v | 12,531 | module MODULE1 (
clk, VAR107, VAR22, VAR24
);
input clk;
output [25 : 0] VAR107;
input [12 : 0] VAR22;
input [12 : 0] VAR24;
wire \VAR2/VAR89 ;
wire \VAR2/VAR7 ;
wire \VAR2/VAR110 ;
wire \VAR2/VAR105 ;
wire \VAR2/VAR56 ;
wire \VAR2/VAR10 ;
wire \VAR2/VAR28 ;
wire \VAR2/VAR104 ;
wire \VAR2/VAR33 ;
wire \VAR2/VAR53 ;
wir... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcin/sky130_fd_sc_hs__fahcin_1.v | 2,210 | module MODULE1 (
VAR6,
VAR2 ,
VAR9 ,
VAR8 ,
VAR5 ,
VAR1,
VAR3
);
output VAR6;
output VAR2 ;
input VAR9 ;
input VAR8 ;
input VAR5 ;
input VAR1;
input VAR3;
VAR4 VAR7 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR6,
VAR2 ,
VAR9 ,
VAR8 ,
VAR5
)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbp/sky130_fd_sc_lp__sdfbbp.blackbox.v | 1,532 | module MODULE1 (
VAR1 ,
VAR12 ,
VAR10 ,
VAR6 ,
VAR9 ,
VAR3 ,
VAR4 ,
VAR11
);
output VAR1 ;
output VAR12 ;
input VAR10 ;
input VAR6 ;
input VAR9 ;
input VAR3 ;
input VAR4 ;
input VAR11;
supply1 VAR5;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
Jside/nova1 | nova_io_snooper.v | 1,964 | module MODULE1(VAR12, VAR9, VAR10, VAR14, VAR3, VAR11, VAR6);
input VAR12;
input VAR9;
input VAR10;
input VAR14;
input [0:7] VAR3;
input [0:15] VAR11;
output [0:15] VAR6;
always @(posedge VAR12) begin
if(VAR10) begin
VAR13("%VAR8 VAR7 %VAR2 VAR5! %VAR4 %VAR1 %VAR1",
VAR3[0:5], VAR11, VAR3[6:7], VAR14);
if(VAR14) begin
... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_1.behavioral.pp.v | 6,220 | module MODULE1( VAR58, VAR29, VAR18, VAR44, VAR28, VAR53, VAR20 );
input VAR29, VAR58, VAR18, VAR44;
inout VAR53, VAR20;
output VAR28;
reg VAR21;
VAR36 VAR13(.VAR58(VAR58),.VAR29(VAR29),.VAR18(VAR18),.VAR44(VAR44),.VAR28(VAR28),.VAR53(VAR53),.VAR20(VAR20),.VAR21(VAR21));
VAR36 VAR56(.VAR58(VAR58),.VAR29(VAR29),.VAR18(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3/sky130_fd_sc_hd__nand3.functional.pp.v | 1,819 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR6 ,
VAR12 ,
VAR1,
VAR3,
VAR5 ,
VAR9
);
output VAR7 ;
input VAR11 ;
input VAR6 ;
input VAR12 ;
input VAR1;
input VAR3;
input VAR5 ;
input VAR9 ;
wire VAR14 ;
wire VAR8;
nand VAR2 (VAR14 , VAR6, VAR11, VAR12 );
VAR13 VAR4 (VAR8, VAR14, VAR1, VAR3);
buf VAR10 (VAR7 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311a/sky130_fd_sc_ls__o311a.pp.symbol.v | 1,379 | module MODULE1 (
input VAR4 ,
input VAR3 ,
input VAR1 ,
input VAR8 ,
input VAR9 ,
output VAR5 ,
input VAR7 ,
input VAR2,
input VAR6,
input VAR10
);
endmodule | apache-2.0 |
jmahler/mips-cpu | regr.v | 1,100 | module MODULE1 (
input clk,
input VAR3,
input VAR2,
input wire [VAR1-1:0] in,
output reg [VAR1-1:0] out);
parameter VAR1 = 1;
always @(posedge clk) begin
if (VAR3)
out <= {VAR1{1'b0}};
end
else if (VAR2)
out <= out;
else
out <= in;
end
endmodule | gpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/acl_token_fifo_counter.v | 4,105 | module MODULE1
parameter integer VAR9 = 32, parameter integer VAR13 = 1, parameter integer VAR6 = 0 )
(
VAR5,
VAR11,
VAR20, VAR3,
VAR18,
VAR7,
VAR14,
VAR19,
VAR2
);
localparam VAR10 = (VAR13 == 0) ?
((VAR9 > 1 ? VAR8(VAR9-1) : 0) + 2) :
(VAR8(VAR9) + 1);
input VAR5;
input VAR11;
output [VAR10-1:0] VAR20;
input VAR3;
ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon.behavioral.pp.v | 2,415 | module MODULE1 (
VAR10 ,
VAR14 ,
VAR3,
VAR4 ,
VAR11 ,
VAR8 ,
VAR12 ,
VAR7
);
output VAR10 ;
input VAR14 ;
input VAR3;
input VAR4 ;
input VAR11 ;
input VAR8 ;
input VAR12 ;
input VAR7 ;
wire VAR13 ;
wire VAR5 ;
wire VAR9;
not VAR16 (VAR13 , VAR3 );
and VAR1 (VAR5 , VAR3, VAR14 );
VAR15 VAR2 (VAR9, VAR5, VAR4, VAR8, VAR1... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_NTNU/integracion_fisica/front_end/source/significand_alu.v | 2,861 | module MODULE1(VAR1, VAR10, VAR13, VAR7, VAR9, VAR5);
input [3:0] VAR1;
input [31:0] VAR10, VAR13; output reg VAR7;
output VAR9;
output [31:0] VAR5;
reg signed [31:0] VAR12;
assign VAR5 = VAR12;
assign VAR9 = (VAR12 == 32'b0) ? 1'b1 : 1'b0;
always @(VAR1, VAR10, VAR13) begin
VAR12 = 32'b0;
VAR7 = VAR10[31];
case (VAR1)... | gpl-3.0 |
jkanasu/utl | lab14eve16/asic/j02a_unsignedArrayMultiplier.v | 1,717 | module MODULE1(VAR2, VAR28, VAR29);
output [7:0] VAR2;
input [3:0] VAR28, VAR29;
wire [14:0] VAR10;
wire [10:0] VAR33;
wire [5:0] VAR11;
and VAR25 ( VAR10[0], VAR28[0], VAR29[1] );
and VAR17 ( VAR10[1], VAR28[0], VAR29[2] );
and VAR4 ( VAR10[2], VAR28[0], VAR29[3] );
and VAR20 ( VAR10[3], VAR28[1], VAR29[0] );
and VAR1... | apache-2.0 |
PsiStarPsi/firmware-general | General/rtl/encode.v | 4,104 | module MODULE1 (VAR28, VAR24, VAR40, VAR37) ;
input [8:0] VAR28 ;
input VAR24 ; output [9:0] VAR40 ;
output VAR37 ;
wire VAR2 = VAR28[0] ;
wire VAR13 = VAR28[1] ;
wire VAR20 = VAR28[2] ;
wire VAR39 = VAR28[3] ;
wire VAR31 = VAR28[4] ;
wire VAR23 = VAR28[5] ;
wire VAR42 = VAR28[6] ;
wire VAR10 = VAR28[7] ;
wire VAR34 = ... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai.pp.blackbox.v | 1,414 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR7 ,
VAR5 ,
VAR2 ,
VAR1 ,
VAR10,
VAR8,
VAR6 ,
VAR3
);
output VAR9 ;
input VAR4 ;
input VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR10;
input VAR8;
input VAR6 ;
input VAR3 ;
endmodule | apache-2.0 |
SymbiFlow/fpga-tool-perf | third_party/ibex/ram_1p.v | 1,086 | module MODULE1 (
VAR5,
VAR16,
VAR6,
VAR18,
VAR20,
VAR1,
VAR4,
VAR11,
VAR8
);
parameter signed [31:0] VAR7 = 128;
input VAR5;
input VAR16;
input VAR6;
input VAR18;
input [3:0] VAR20;
input [31:0] VAR1;
input [31:0] VAR4;
output reg VAR11;
output reg [31:0] VAR8;
parameter signed [31:0] VAR14 = VAR17(VAR7);
reg [31:0] VA... | isc |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai.behavioral.v | 1,674 | module MODULE1 (
VAR2 ,
VAR11,
VAR8,
VAR6 ,
VAR3
);
output VAR2 ;
input VAR11;
input VAR8;
input VAR6 ;
input VAR3 ;
supply1 VAR7;
supply0 VAR10;
supply1 VAR12 ;
supply0 VAR16 ;
wire VAR4 ;
wire VAR9 ;
wire VAR5;
nand VAR13 (VAR4 , VAR8, VAR11 );
or VAR1 (VAR9 , VAR3, VAR6 );
nand VAR14 (VAR5, VAR4, VAR9);
buf VAR15 (V... | apache-2.0 |
bunnie/novena-sd-fpga | novena-sd.srcs/sources_1/ip/mig_v3_91_0/ddr3_if/user_design/rtl/mcb_controller/mcb_soft_calibration_top.v | 12,826 | module MODULE1 # (
parameter VAR6 = 10'h512, parameter VAR55 = "VAR76", parameter VAR84 = 1'b0, parameter VAR62 = 1'b0, parameter VAR58 = 1'b0, parameter VAR9 = "VAR11", parameter VAR29 = "VAR102" )
(
input wire VAR54, input wire VAR60, input wire VAR71, output wire VAR82, input wire VAR42, input wire VAR17,
input wire... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufinv/sky130_fd_sc_hdll__bufinv_8.v | 2,060 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR2,
VAR5,
VAR3 ,
VAR1
);
output VAR7 ;
input VAR8 ;
input VAR2;
input VAR5;
input VAR3 ;
input VAR1 ;
VAR6 VAR4 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR7,
VAR8
);
output VAR7;
input VAR8;
supply1 VAR2;
supply0 VAR5;... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/async_fifo_fwft.v | 4,803 | module MODULE1 #(
parameter VAR2 = 32, parameter VAR21 = 1024, parameter VAR16 = 2**VAR18(VAR21),
parameter VAR23 = VAR6(VAR16),
parameter VAR19 = VAR6(VAR16+1)
)
(
input VAR4, input VAR17, input VAR1, input VAR26, input [VAR2-1:0] VAR10, input VAR24, output [VAR2-1:0] VAR11, input VAR25, output VAR22, output VAR14 );
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221o/sky130_fd_sc_lp__a221o_m.v | 2,441 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR12 ,
VAR6 ,
VAR11 ,
VAR1 ,
VAR7,
VAR2,
VAR8 ,
VAR9
);
output VAR3 ;
input VAR5 ;
input VAR12 ;
input VAR6 ;
input VAR11 ;
input VAR1 ;
input VAR7;
input VAR2;
input VAR8 ;
input VAR9 ;
VAR10 VAR4 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR7(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2b/sky130_fd_sc_lp__nor2b.behavioral.pp.v | 1,969 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR8 ,
VAR11,
VAR14,
VAR12 ,
VAR1
);
output VAR7 ;
input VAR6 ;
input VAR8 ;
input VAR11;
input VAR14;
input VAR12 ;
input VAR1 ;
wire VAR3 ;
wire VAR2 ;
wire VAR10;
not VAR5 (VAR3 , VAR6 );
and VAR15 (VAR2 , VAR3, VAR8 );
VAR13 VAR9 (VAR10, VAR2, VAR11, VAR14);
buf VAR4 (VAR7 , VAR10 );
... | apache-2.0 |
Alabamajack/Garfield | FPGA_Design/ip_extern/altsource_probe/hps_reset_bb.v | 3,059 | module MODULE1 (
VAR3,
VAR2,
VAR1);
input VAR3;
input VAR2;
output [2:0] VAR1;
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_2.functional.pp.v | 1,772 | module MODULE1( VAR26, VAR29, VAR22, VAR15, VAR21, VAR20, VAR6 );
input VAR29, VAR15, VAR22;
inout VAR20, VAR6;
output VAR21, VAR26;
wire VAR9;
and VAR10( VAR9, VAR29, VAR15 );
wire VAR8;
and VAR14( VAR8, VAR29, VAR22 );
wire VAR11;
and VAR7( VAR11, VAR15, VAR22 );
or VAR18( VAR21, VAR9, VAR8, VAR11 );
wire VAR16;
and ... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_int_mult108u.v | 1,621 | module MODULE1 (VAR7, enable, VAR18, VAR9, VAR13);
input VAR7, enable;
input [53:0] VAR18;
input [53:0] VAR9;
output [107:0] VAR13;
VAR2 VAR14 (
.VAR7 (VAR7),
.VAR18 (VAR18),
.VAR9 (VAR9),
.VAR5 (enable),
.VAR13 (VAR13),
.VAR11 (1'b0),
.sum (1'b0));
VAR14.VAR8 = "VAR4=9",
VAR14.VAR12 = 3,
VAR14.VAR15 = "VAR16",
VAR14.... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/host_interface/ft245_sync_fifo/ft245_host_interface.v | 9,976 | module MODULE1 (
input clk,
input rst,
input VAR37,
inout [7:0] VAR36,
input VAR22,
output VAR14,
input VAR32,
output VAR35,
output VAR20,
output VAR13,
output VAR24,
input [1:0] VAR34,
output reg [1:0] VAR26,
output reg VAR42,
input [23:0] VAR44,
output reg [VAR17 - 1: 0] VAR23,
output VAR5,
input VAR30,
output reg VA... | mit |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_wf_alloc.v | 3,667 | module MODULE1
(clk, reset, VAR15, req, VAR12);
parameter VAR11 = 8;
parameter VAR8 = VAR6;
parameter VAR9 = 0;
parameter VAR16 = VAR7;
input clk;
input reset;
input VAR15;
input [0:VAR11*VAR11-1] req;
output [0:VAR11*VAR11-1] VAR12;
wire [0:VAR11*VAR11-1] VAR12;
generate
case(VAR8)
begin
VAR13
.VAR9(VAR9),
.VAR16(VAR1... | mit |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/radio_controller_v1_22_a/hdl/verilog/radio_controller_TxTiming.v | 3,639 | module MODULE1
(
clk,
reset,
VAR5,
VAR8,
VAR14,
VAR18,
VAR3,
VAR7,
VAR10,
VAR16,
VAR11,
VAR15,
VAR6,
VAR4
);
input clk;
input reset;
input VAR5;
input [0:5] VAR8;
input [0:3] VAR14;
input [0:3] VAR18;
input [0:7] VAR3;
input [0:11] VAR7;
input [0:7] VAR10;
input [0:7] VAR16;
output VAR11;
output VAR4;
output VAR6;
outp... | bsd-2-clause |
asicguy/gplgpu | hdl/clk_gen/clk_gen.v | 6,097 | module MODULE1
(
input VAR31,
input VAR43,
input VAR4,
input [1:0] VAR28,
input [13:0] VAR14,
input [2:0] VAR19,
input VAR25,
input [1:0] VAR48,
input VAR17,
input VAR37,
output VAR45,
output reg VAR20,
output reg VAR6,
output reg [2:0] VAR11 );
reg [2:0] VAR46;
reg [2:0] VAR27, VAR13; reg VAR38; reg [1:0] VAR15; reg [... | gpl-3.0 |
theapi/de1-soc | ps2/rtl/verilog/ps2_controller.v | 2,133 | module MODULE1 (
input reset,
input clk,
input VAR7,
input VAR6,
output VAR4,
output [7:0] VAR5
);
reg [7:0] VAR3;
reg [3:0] VAR1 = 4'd0;
reg ready;
reg [1:0] VAR2 = 2'b00;
wire VAR8;
assign VAR5 = VAR3;
assign VAR4 = ready;
assign VAR8 = (VAR2 == 2'b10);
always @(posedge clk) begin
VAR2 <= {VAR2[0], VAR7};
end
always ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222o/sky130_fd_sc_hs__a222o.behavioral.v | 2,281 | module MODULE1 (
VAR1 ,
VAR18 ,
VAR10 ,
VAR7 ,
VAR5 ,
VAR13 ,
VAR2 ,
VAR6,
VAR4
);
output VAR1 ;
input VAR18 ;
input VAR10 ;
input VAR7 ;
input VAR5 ;
input VAR13 ;
input VAR2 ;
input VAR6;
input VAR4;
wire VAR5 VAR17 ;
wire VAR5 VAR11 ;
wire VAR5 VAR3 ;
wire VAR19 ;
wire VAR15;
and VAR16 (VAR17 , VAR7, VAR5 );
and VAR... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ddr_byte_group_io.v | 19,285 | module MODULE1 #(
parameter VAR111 = 12'b111111111111,
parameter VAR51 = 12'b000000000000,
parameter VAR62 = "VAR96",
parameter VAR164 = "VAR100",
parameter VAR11 = 4,
parameter VAR14 = "VAR19",
parameter VAR22 = 00,
parameter VAR165 = "VAR46",
parameter VAR93 = 12,
parameter VAR163 = "VAR96"
)
(
input [9:0] VAR166,
ou... | mit |
jairov4/accel-oil | solution_virtex5_plb/syn/verilog/nfa_get_initials_1.v | 11,650 | module MODULE1 (
VAR21,
VAR30,
VAR41,
VAR13,
VAR32,
VAR4,
VAR31,
VAR7,
VAR6,
VAR5,
VAR27,
VAR9,
VAR45,
VAR36,
VAR1,
VAR2,
VAR10,
VAR23,
VAR24,
VAR18,
VAR33
);
parameter VAR43 = 1'b1;
parameter VAR29 = 1'b0;
parameter VAR35 = 1'b0;
parameter VAR34 = 32'b00000000000000000000000000000000;
parameter VAR19 = 32'b1;
paramete... | lgpl-3.0 |
Giako68/SD_RAM_VIDEO | VIDEOGEN.v | 4,849 | module MODULE1
( input VAR11,
input VAR22,
output reg [7:0] VAR27,
output reg [7:0] VAR15,
output reg [7:0] VAR16,
output reg VAR14,
output reg VAR13,
output reg VAR8,
output reg [10:0] VAR1,
output reg VAR20,
input [8:0] VAR19,
input [15:0] VAR23,
input VAR2,
input [7:0] VAR4,
input [31:0] VAR26,
input VAR21,
input [5... | gpl-2.0 |
lloves/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/pcie_dma_engine/tx_engine.v | 11,962 | module MODULE1(
input clk,
input rst,
input VAR39,
input [31:0] VAR6, output [11:0] VAR21,
input [15:0] VAR20,
output [63:0] VAR11,
output [7:0] VAR57,
output VAR10,
output VAR30,
output VAR68,
output VAR48,
input VAR18,
input VAR3,
output VAR8,
input [2:0] VAR67,
input VAR27,
input [63:0] VAR4,
input VAR17,
input [63:... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15.symbol.v | 1,356 | module MODULE1 (
input VAR4,
output VAR6
);
supply1 VAR5;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/Video_System_Video_RGB_Resampler.v | 7,566 | module MODULE1 (
clk,
reset,
VAR6,
VAR15,
VAR7,
VAR19,
VAR4,
VAR5,
VAR3,
VAR11,
VAR21,
VAR14,
VAR12,
VAR1
);
parameter VAR18 = 23;
parameter VAR10 = 15;
parameter VAR20 = 1;
parameter VAR16 = 0;
parameter VAR2 = 10'h3FF;
input clk;
input reset;
input [VAR18:0] VAR6;
input VAR15;
input VAR7;
input [VAR20:0] VAR19;
input... | gpl-2.0 |
jotego/jt12 | hdl/adpcm/jt10_adpcm.v | 3,560 | module MODULE1(
input VAR12,
input clk, input VAR21, input [3:0] VAR9,
input VAR10, input VAR33,
output signed [15:0] VAR34
);
localparam VAR18 = 12;
reg signed [VAR18-1:0] VAR20, VAR26, VAR8, VAR3, VAR29, VAR28;
reg signed [VAR18-1:0] VAR19;
reg [5:0] VAR27, VAR13, VAR4, VAR22, VAR15, VAR7;
reg [5:0] VAR17, VAR14;
reg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n.behavioral.v | 1,389 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR5
);
output VAR6 ;
input VAR1 ;
input VAR5;
supply1 VAR3;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR4 ;
and VAR7 (VAR6 , VAR1, VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1p/sky130_fd_sc_lp__inputiso1p.functional.pp.v | 1,726 | module MODULE1 (
VAR11 ,
VAR4 ,
VAR5,
VAR7 ,
VAR6 ,
VAR10 ,
VAR9
);
output VAR11 ;
input VAR4 ;
input VAR5;
input VAR7 ;
input VAR6 ;
input VAR10 ;
input VAR9 ;
wire VAR8;
or VAR1 (VAR8, VAR4, VAR5 );
VAR2 VAR3 (VAR11 , VAR8, VAR7, VAR6);
endmodule | apache-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/DecOp4_XE.v | 14,385 | module MODULE1(
VAR38,
VAR75,
VAR87,
VAR85,
VAR63,
VAR92
);
input[31:0] VAR38;
output[6:0] VAR75;
output[6:0] VAR87;
output[6:0] VAR85;
output[31:0] VAR63;
output[7:0] VAR92;
reg[6:0] VAR29;
reg[6:0] VAR59;
reg[6:0] VAR64; reg[31:0] VAR93; reg[7:0] VAR81;
assign VAR75 = VAR29;
assign VAR87 = VAR59;
assign VAR85 = VAR64... | mit |
takeshineshiro/fpga_linear_128 | ArrayUltrasound.v | 14,857 | module MODULE1(
input VAR38,
output [15:0] VAR72,
output [15:0] VAR84,
output VAR111,
output VAR168,
output VAR69,
output VAR21,
output VAR177,
output [3:0] VAR70,
output [2:0] VAR180,
output VAR85,
output VAR116,
output VAR164,
output VAR8,
input VAR30,
input VAR33,
input VAR7,
input VAR90,
input VAR37,
input VAR11,
i... | mit |
mcoughli/root_of_trust | experiments/secure_filesystem/secure_filesystem_hls/solution1/syn/verilog/filesystem_encrypt_AXILiteS_s_axi.v | 8,324 | module MODULE1
VAR44 = 6,
VAR6 = 32
)(
input wire VAR37,
input wire VAR25,
input wire VAR10,
input wire [VAR44-1:0] VAR34,
input wire VAR9,
output wire VAR2,
input wire [VAR6-1:0] VAR54,
input wire [VAR6/8-1:0] VAR29,
input wire VAR18,
output wire VAR4,
output wire [1:0] VAR21,
output wire VAR13,
input wire VAR45,
inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtn/sky130_fd_sc_hs__sdfrtn.symbol.v | 1,472 | module MODULE1 (
input VAR6 ,
output VAR7 ,
input VAR1,
input VAR2 ,
input VAR5 ,
input VAR8
);
supply1 VAR3;
supply0 VAR4;
endmodule | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_qpll_reset.v | 14,389 | module MODULE1 #
(
parameter VAR24 = "VAR15", parameter VAR1 = "VAR10", parameter VAR9 = 1, parameter VAR31 = 1
)
(
input VAR4,
input VAR16,
input VAR3,
input [VAR9-1:0] VAR44,
input [(VAR9-1)>>2:0]VAR42,
input [(VAR9-1)>>2:0]VAR46,
input [ 1:0] VAR28,
input [VAR9-1:0] VAR17,
input [VAR9-1:0] VAR49,
output VAR2,
output... | lgpl-3.0 |
hpcn-uam/hardware_packet_train | NetFPGA10G/Verilog/generator.v | 14,035 | module MODULE1
parameter VAR19=256,
parameter VAR7=256,
parameter VAR37=128,
parameter VAR10=128,
parameter VAR27=16,
parameter VAR63=24,
parameter VAR59= 400,
parameter VAR12 = "VAR5",
parameter VAR56 = 32,
parameter VAR55 = 32,
parameter VAR53 = 0,
parameter VAR62 = 0,
parameter VAR29 = 32'hFFFFFFFF,
parameter VAR18 ... | gpl-2.0 |
amerc/phimii | NEXYS3/server.v | 346,824 | module MODULE1(VAR46,VAR52,VAR24,VAR49,VAR48,VAR47,clk,rst,VAR21,VAR37,VAR44,VAR50,VAR30,VAR36);
integer VAR19;
real VAR5;
input [15:0] VAR46;
input [15:0] VAR52;
input VAR24;
input VAR49;
input VAR48;
input VAR47;
input clk;
input rst;
output [15:0] VAR21;
output [15:0] VAR37;
output VAR44;
output VAR50;
output VAR30;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221oi/sky130_fd_sc_hd__a221oi_1.v | 2,457 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR10 ,
VAR12 ,
VAR7 ,
VAR1 ,
VAR6,
VAR3,
VAR8 ,
VAR9
);
output VAR4 ;
input VAR5 ;
input VAR10 ;
input VAR12 ;
input VAR7 ;
input VAR1 ;
input VAR6;
input VAR3;
input VAR8 ;
input VAR9 ;
VAR2 VAR11 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(... | apache-2.0 |
TWW12/lzw | final_project/lzw_compression/lzw_compression.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/synth/design_1_auto_pc_0.v | 13,157 | module MODULE1 (
VAR37,
VAR99,
VAR2,
VAR42,
VAR12,
VAR96,
VAR35,
VAR24,
VAR80,
VAR63,
VAR26,
VAR55,
VAR85,
VAR49,
VAR74,
VAR87,
VAR18,
VAR101,
VAR54,
VAR77,
VAR100,
VAR66,
VAR108,
VAR7,
VAR94,
VAR21,
VAR61,
VAR112,
VAR30,
VAR68,
VAR32,
VAR76,
VAR27,
VAR13,
VAR73,
VAR103,
VAR57,
VAR22,
VAR78,
VAR17,
VAR106,
VAR23,
VAR45... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.v | 2,485 | module MODULE1 (
VAR7 ,
VAR10,
VAR8,
VAR9 ,
VAR3 ,
VAR1,
VAR2,
VAR5 ,
VAR4
);
output VAR7 ;
input VAR10;
input VAR8;
input VAR9 ;
input VAR3 ;
input VAR1;
input VAR2;
input VAR5 ;
input VAR4 ;
VAR6 VAR11 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VA... | apache-2.0 |
phasza/axi_spi_if | fifo1.v | 1,844 | module MODULE1(
input VAR13,
input VAR12,
input [VAR9-1:0] VAR3,
input VAR5,
input VAR4,
output [VAR9-1:0] VAR7,
output VAR1,
output VAR11
);
parameter VAR9 = 32;
reg [VAR9-1:0] VAR8;
reg VAR10;
reg VAR2;
VAR6 VAR8 = 0;
always @(posedge VAR13, negedge VAR12)
if(!VAR12)
begin
VAR2 <= 1;
VAR10 <= 0;
end
else
begin
if(VAR... | gpl-3.0 |
AndreaCorallo/KPU | rtl/kpu/kpu.v | 23,152 | module MODULE1(
input wire VAR174, input VAR98, input VAR55, input wire VAR130, output wire [VAR142-1:0] VAR182, input wire [VAR142-1:0] VAR139, output wire [VAR142-1:0] VAR61, output wire [3:0] VAR8, output wire [VAR142-1:0] VAR75, input wire [VAR142-1:0] VAR38, input wire VAR153 );
wire [VAR142-1:0] VAR190;
reg [VAR1... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/cordic_Arch3/CORDIC_FSM_v3.v | 4,741 | module MODULE1
(
input wire clk, input wire reset, input wire VAR12, input wire VAR14, input wire VAR3,
input wire VAR18, input wire VAR13, input wire VAR17,
output reg VAR6, output reg VAR21, output reg VAR24, output reg VAR2, output reg VAR4, VAR7, VAR5,
output reg VAR20
);
parameter VAR16 = 8'b00000001;
parameter VA... | gpl-3.0 |
kigawas/MipsCPU | CPU/cla32.v | 2,197 | module MODULE6(VAR8, VAR17, VAR3, VAR18, VAR14);
input [31:0] VAR8, VAR17;
input VAR3;
output [31:0] VAR18;
output VAR14;
wire VAR7, VAR11;
MODULE6 MODULE3(VAR8, VAR17, VAR3, VAR7, VAR11, VAR18);
assign VAR14 = VAR7 | VAR11 & VAR3;
endmodule
module MODULE6(VAR8, VAR17, VAR12, VAR7, VAR11, VAR18);
input [31:0] VAR8, VAR... | apache-2.0 |
8l/kestrel | 2/nexys2/j1a/M_j1a.v | 9,773 | module MODULE1(
input VAR20,
input VAR12,
output [13:1] VAR39,
input [15:0] VAR33,
output [15:1] VAR37,
output [15:0] VAR44,
input [15:0] VAR35,
output VAR16,
output VAR22,
output VAR38,
output VAR48,
input VAR1,
output VAR32 );
reg [15:1] VAR9;
reg [15:0] VAR21;
wire VAR5 = (VAR33[15:13] === 3'b011);
wire VAR10 = (VAR... | apache-2.0 |
muraj/trv_proc | rtl/wb_shift_ram.v | 3,387 | module MODULE1
parameter VAR14 = 32,
parameter VAR10 = 8,
parameter VAR29 = 3,
parameter VAR28 = 3,
)
(
input wire VAR21,
input wire VAR27,
input wire [0 +: VAR29] VAR8,
input wire [0 +: VAR14] VAR2,
output wire [0 +: VAR14] VAR22,
output wire [0 +: VAR29] VAR12, input wire VAR3,
input wire VAR9,
input wire VAR30,
inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41oi/sky130_fd_sc_lp__a41oi_2.v | 2,439 | module MODULE2 (
VAR7 ,
VAR10 ,
VAR12 ,
VAR1 ,
VAR2 ,
VAR8 ,
VAR9,
VAR4,
VAR3 ,
VAR6
);
output VAR7 ;
input VAR10 ;
input VAR12 ;
input VAR1 ;
input VAR2 ;
input VAR8 ;
input VAR9;
input VAR4;
input VAR3 ;
input VAR6 ;
VAR5 VAR11 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4bb/sky130_fd_sc_hdll__nor4bb_4.v | 2,341 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR3 ,
VAR11 ,
VAR5 ,
VAR2,
VAR1,
VAR10 ,
VAR8
);
output VAR4 ;
input VAR9 ;
input VAR3 ;
input VAR11 ;
input VAR5 ;
input VAR2;
input VAR1;
input VAR10 ;
input VAR8 ;
VAR6 VAR7 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR10(VAR10),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311a/sky130_fd_sc_hs__o311a.blackbox.v | 1,337 | module MODULE1 (
VAR2 ,
VAR5,
VAR8,
VAR3,
VAR1,
VAR6
);
output VAR2 ;
input VAR5;
input VAR8;
input VAR3;
input VAR1;
input VAR6;
supply1 VAR7;
supply0 VAR4;
endmodule | apache-2.0 |
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