repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxbp/sky130_fd_sc_ms__sdfxbp.pp.symbol.v | 1,434 | module MODULE1 (
input VAR5 ,
output VAR8 ,
output VAR10 ,
input VAR7 ,
input VAR2 ,
input VAR9 ,
input VAR3 ,
input VAR1,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd.pp.symbol.v | 1,228 | module MODULE1 (
input VAR2 ,
input VAR1,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor3/sky130_fd_sc_hdll__xnor3.behavioral.v | 1,404 | module MODULE1 (
VAR3,
VAR6,
VAR9,
VAR8
);
output VAR3;
input VAR6;
input VAR9;
input VAR8;
supply1 VAR1;
supply0 VAR11;
supply1 VAR7 ;
supply0 VAR5 ;
wire VAR4;
xnor VAR10 (VAR4, VAR6, VAR9, VAR8 );
buf VAR2 (VAR3 , VAR4 );
endmodule | apache-2.0 |
alan4186/Hardware-CNN | Hardware/v/mult_adder.v | 3,587 | module MODULE2(
input VAR3,
input reset,
input [VAR8:0] in,
input [VAR8:0] VAR18,
input [VAR29:0] VAR12,
output [VAR29:0] out
);
wire [VAR14:0] VAR9 [VAR17-1:0];
wire [VAR29:0] VAR19 [((VAR17*2)-1)-1:0];
wire [(VAR17*2)-1-1:0]VAR5 ;
assign out = VAR19[0] + VAR12;
assign VAR5 [(VAR17*2)-1-1:VAR17-1] = VAR17'd0;
genvar V... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/ddr_ch.v | 53,415 | module MODULE1(VAR218 ,VAR45 ,VAR12 ,VAR71 ,
VAR223 ,VAR38 ,VAR24 ,VAR44 ,VAR31 ,VAR57 ,VAR3 ,
VAR91 ,VAR35 ,VAR47 ,VAR212 ,VAR228 ,VAR160
,VAR172 ,VAR209 ,VAR11 , VAR149,
VAR110 ,VAR200 ,VAR4 ,VAR117 ,VAR166 ,
VAR93 ,VAR131 ,VAR80 ,VAR27 ,
VAR163 ,VAR101 ,VAR1 ,VAR6 ,VAR120
,VAR114 ,VAR60 ,VAR100 ,VAR103 ,
VAR104 ,VAR... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/iobdg_dbg/rtl/iobdg_dbg_iob.v | 15,841 | module MODULE1 (
VAR19, VAR18, VAR143,
VAR67, clk, VAR10, VAR83, VAR56,
VAR130, VAR58, VAR118, VAR100,
VAR97, VAR55, VAR135,
VAR38, VAR4, VAR73,
VAR134, VAR61, VAR140,
VAR47, VAR52, VAR51, VAR16,
VAR78, VAR93, VAR82, VAR17,
VAR98, VAR121, VAR6, VAR5,
VAR107, VAR43, VAR45,
VAR44, VAR142, VAR2,
VAR136, VAR109, VAR53, VAR... | gpl-2.0 |
Willster419/ELEC3725_vivado_projects | assignment_8_p2_final/ARMS_phase4-9.v | 32,245 | module MODULE2(VAR96,clk,VAR133,VAR3,reset,VAR123);
input clk;
input reset;
output [63:0] VAR123; wire [63:0] VAR67; wire [63:0] VAR70; wire [63:0] VAR97; reg [1:0] VAR24;
wire [1:0] VAR84;
wire [1:0] VAR130;
wire VAR79; wire [63:0] VAR22; wire [63:0] VAR91;
wire [63:0] VAR62;
wire VAR34;
wire VAR129;
reg [2:0] VAR16;
... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_0002.v | 11,728 | module MODULE1 (
input wire VAR35, input wire VAR30, input wire VAR13, output wire VAR22, output wire VAR66, output wire VAR46, output wire [12:0] VAR87, output wire [2:0] VAR14, output wire VAR70, output wire VAR60, output wire VAR62, output wire VAR28, output wire [1:0] VAR40, output wire VAR68, output wire VAR77, ou... | lgpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_csc_1_mul.v | 6,893 | module MODULE1 (
clk,
VAR13,
VAR10,
VAR24,
VAR18,
VAR17);
parameter VAR22 = 16;
localparam VAR26 = VAR22 - 1;
input clk;
input [16:0] VAR13;
input [ 7:0] VAR10;
output [24:0] VAR24;
input [VAR26:0] VAR18;
output [VAR26:0] VAR17;
reg VAR21 = 'd0;
reg [VAR26:0] VAR16 = 'd0;
reg [23:0] VAR20 = 'd0;
reg [23:0] VAR1 = 'd0;
... | mit |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_gpio_led_0/system_axi_gpio_led_0_stub.v | 2,503 | module MODULE1(VAR25, VAR14, VAR4,
VAR17, VAR10, VAR13, VAR22, VAR23, VAR8,
VAR2, VAR16, VAR5, VAR18, VAR6, VAR12,
VAR9, VAR20, VAR24, VAR15, VAR19, VAR7, VAR11,
VAR1, VAR3, VAR21)
;
input VAR25;
input VAR14;
input [8:0]VAR4;
input VAR17;
output VAR10;
input [31:0]VAR13;
input [3:0]VAR22;
input VAR23;
output VAR8;
outp... | apache-2.0 |
Cognoscan/BoostLogic | verilog/src/displays/SevenSegment.v | 1,081 | module MODULE1 (
input wire [3:0] VAR2,
output reg [6:0] VAR1
);
always @(VAR2) begin
case (VAR2)
4'h0 : VAR1 <= 7'b1111110;
4'h1 : VAR1 <= 7'b0110000;
4'h2 : VAR1 <= 7'b1101101;
4'h3 : VAR1 <= 7'b1111001;
4'h4 : VAR1 <= 7'b0110011;
4'h5 : VAR1 <= 7'b1011011;
4'h6 : VAR1 <= 7'b1011111;
4'h7 : VAR1 <= 7'b1110000;
4'h8 :... | apache-2.0 |
olajep/oh | src/elink/hdl/erx_arbiter.v | 3,306 | module MODULE1 (
VAR27, VAR16, VAR23, VAR13, VAR36,
VAR34, VAR12, VAR33, VAR1, VAR18,
VAR4, VAR7, VAR17, VAR35, VAR25,
VAR6, VAR3, VAR16, VAR27, VAR22
);
parameter VAR21 = 32;
parameter VAR9 = 32;
parameter VAR14 = 104;
parameter VAR30 = 12'h800; parameter VAR19 = 6;
input VAR4; input [VAR14-1:0] VAR7;
output VAR27; ou... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/DW_rbsh_inst_syn.v | 3,003 | module MODULE1 ( VAR6, VAR24, VAR13, VAR17 );
input [7:0] VAR6;
input [2:0] VAR24;
output [7:0] VAR17;
input VAR13;
wire VAR47, VAR31, VAR40, VAR34, VAR33, VAR2, VAR49, VAR46, VAR29, VAR58, VAR54, VAR21, VAR48, VAR15,
VAR26, VAR12, VAR18, VAR45, VAR37;
VAR42 VAR3 ( .VAR52(VAR24[1]), .VAR10(VAR6[7]), .VAR53(VAR47), .VAR... | gpl-3.0 |
freecores/eco32 | fpga/src/kbd/kbd.v | 1,376 | module MODULE1(clk, reset,
en, wr, addr,
VAR7, VAR10,
VAR2, irq,
VAR6, VAR5);
input clk;
input reset;
input en;
input wr;
input addr;
input [7:0] VAR7;
output [7:0] VAR10;
output VAR2;
output irq;
input VAR6;
input VAR5;
wire [7:0] VAR4;
wire VAR9;
reg [7:0] VAR8;
reg VAR13;
reg VAR1;
reg [7:2] VAR12;
VAR11 VAR3(
.VAR6... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc.blackbox.v | 1,343 | module MODULE1 (
VAR3 ,
VAR4,
VAR6
);
output VAR3 ;
input VAR4;
input VAR6 ;
supply1 VAR1;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221oi/sky130_fd_sc_ms__a221oi_4.v | 2,457 | module MODULE2 (
VAR12 ,
VAR3 ,
VAR7 ,
VAR4 ,
VAR6 ,
VAR9 ,
VAR5,
VAR1,
VAR2 ,
VAR11
);
output VAR12 ;
input VAR3 ;
input VAR7 ;
input VAR4 ;
input VAR6 ;
input VAR9 ;
input VAR5;
input VAR1;
input VAR2 ;
input VAR11 ;
VAR10 VAR8 (
.VAR12(VAR12),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VA... | apache-2.0 |
ptracton/Picoblaze | library/uart_pb/pb_uart_regs.v | 4,702 | module MODULE1 (
VAR26, interrupt, VAR12, VAR10, VAR1,
enable, VAR7,
clk, reset, VAR13, VAR22, VAR5, VAR14,
VAR2, VAR9, VAR6, VAR29,
VAR19, VAR27, VAR18
) ;
input clk;
input reset;
input [7:0] VAR13;
input [7:0] VAR22;
output [7:0] VAR26;
input VAR5;
input VAR14;
output interrupt;
output VAR12;
output [7:0] VAR10;
outp... | mit |
Elphel/x393_sata | x393/axi/axibram_read.v | 13,213 | module MODULE1 #(
parameter VAR10 = 10 )(
input VAR55, input VAR67, input [31:0] VAR30, input VAR52, output VAR19, input [11:0] VAR15, input [ 3:0] VAR39, input [ 1:0] VAR22, input [ 1:0] VAR48, output [31:0] VAR3, output reg VAR1, input VAR13, output reg [11:0] VAR33, output reg VAR60, output [ 1:0] VAR2,
output [VAR1... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_1.behavioral.v | 1,502 | module MODULE1( VAR4, VAR3, VAR5, VAR2 );
input VAR3, VAR5;
output VAR4, VAR2;
VAR7 VAR6(.VAR4(VAR4),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2));
VAR7 VAR1(.VAR4(VAR4),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4/sky130_fd_sc_ls__or4.behavioral.pp.v | 1,828 | module MODULE1 (
VAR11 ,
VAR6 ,
VAR7 ,
VAR2 ,
VAR9 ,
VAR14,
VAR10,
VAR13 ,
VAR8
);
output VAR11 ;
input VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR9 ;
input VAR14;
input VAR10;
input VAR13 ;
input VAR8 ;
wire VAR5 ;
wire VAR4;
or VAR12 (VAR5 , VAR9, VAR2, VAR7, VAR6 );
VAR1 VAR3 (VAR4, VAR5, VAR14, VAR10);
buf VAR15 (VA... | apache-2.0 |
combinatorylogic/soc | backends/tiny1/hw/ice/top.v | 6,327 | module MODULE1(
input clk,
input rst,
input [7:0] VAR21,
input VAR58,
input VAR44,
output [7:0] VAR51,
output VAR38,
output VAR43,
output reg [7:0] VAR25
);
wire [15:0] VAR6;
wire [15:0] VAR41;
wire [15:0] VAR56;
wire VAR68;
wire VAR7;
VAR4 VAR70(.clk(clk),
.addr(VAR6[14:1]),
.VAR17(VAR41),
.VAR42(VAR56),
.VAR36(VAR68)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311oi/sky130_fd_sc_hd__a311oi_1.v | 2,450 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR3 ,
VAR10 ,
VAR7 ,
VAR8 ,
VAR1,
VAR5,
VAR4 ,
VAR6
);
output VAR2 ;
input VAR9 ;
input VAR3 ;
input VAR10 ;
input VAR7 ;
input VAR8 ;
input VAR1;
input VAR5;
input VAR4 ;
input VAR6 ;
VAR12 VAR11 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR... | apache-2.0 |
cynngah/virtualsynthesizer | sound_files/Altera_UP_Audio_Out_Serializer.v | 9,608 | module MODULE1 (
clk,
reset,
VAR23,
VAR22,
VAR21,
VAR30,
VAR16,
VAR8,
VAR31,
VAR18,
VAR7,
VAR10,
VAR36
);
parameter VAR27 = 16;
input clk;
input reset;
input VAR23;
input VAR22;
input VAR21;
input VAR30;
input [VAR27:1] VAR16;
input VAR8;
input [VAR27:1] VAR31;
input VAR18;
output reg [7:0] VAR7;
output reg [7:0] VAR10... | mit |
YoelRP/PROYECTO | bin/dbcport/DbCPortStateMachine.v | 4,227 | module MODULE1
(
input wire VAR16 ,
input wire VAR14 ,
input wire VAR9 ,
input wire VAR17 ,
input wire VAR10 ,
input wire VAR18 ,
input wire VAR19 ,
input wire VAR3 ,
input wire VAR2,
input wire VAR4,
input wire VAR15,
input wire VAR6
);
reg [4:0] VAR13;
reg [4:0] VAR21;
always @ (posedge VAR16)
begin : VAR11
if (VAR18... | gpl-3.0 |
varunnagpaal/Digital-Hardware-Modelling | systemverilog/Combinational/alu8b.v | 1,032 | module MODULE1 (input wire [7:0] VAR7,
input wire [7:0] VAR3,
input wire VAR9,
input wire [2:0] VAR8,
output wire [7:0] VAR6,
output wire VAR10);
reg [7:0] VAR2;
reg VAR1;
wire [7:0] VAR4;
wire VAR5;
assign VAR6 = VAR2;
assign VAR10 = VAR1;
assign {VAR5, VAR4} = VAR7 + VAR3 + VAR9;
always @ ( * ) begin
VAR1 = 1'b0; cas... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/lsu/rtl/lsu_asi_decode.v | 17,429 | module MODULE1 (
VAR43, VAR33, VAR28, VAR41,
VAR40, VAR2, VAR35, VAR39,
VAR24, VAR15, VAR55,
VAR32, VAR49, VAR22, VAR21,
VAR29, VAR57, VAR68, VAR53,
VAR25, VAR67, VAR12,
VAR54, VAR1, VAR69,
VAR45, VAR63, VAR11,
VAR10, VAR36, VAR72,
VAR58
);
input [7:0] VAR58 ;
output VAR43 ;
output VAR33 ;
output VAR28 ;
output VAR41 ;... | gpl-2.0 |
OpenSoCPlus/hight_crypto_core | rtl/WKG.v | 4,800 | module MODULE1(
VAR1 ,
VAR4 ,
VAR8 ,
VAR2 ,
VAR6 ,
VAR7 ,
VAR9 ,
VAR5
);
input VAR1 ;
input VAR4 ;
input[31:0] VAR8 ;
input[31:0] VAR2 ;
output[7:0] VAR6 ;
output[7:0] VAR7 ;
output[7:0] VAR9 ;
output[7:0] VAR5 ;
wire VAR3;
assign VAR3 = VAR1 ^ VAR4;
assign VAR6 = (~VAR3) ? VAR2[31:24] : VAR8[31:24] ; assign VAR7 = (~V... | lgpl-2.1 |
mrehkopf/sd2snes | verilog/sd2snes_sdd1/address.v | 6,365 | module MODULE1(
input VAR19,
input [15:0] VAR36, input [2:0] VAR13, input [23:0] VAR12, input [7:0] VAR10, input VAR34, output [23:0] VAR31, output VAR3, output VAR7, output VAR5, output VAR15, input [23:0] VAR28,
input [23:0] VAR21,
output VAR11,
output VAR32,
output VAR29,
output VAR26,
input [14:0] VAR27,
output VAR... | gpl-2.0 |
orbancedric/DeepGate | src/interface/mojo/avr_interface.v | 3,920 | module MODULE1 #(
parameter VAR3 = 50000000,
parameter VAR43 = 500000
)(
input clk,
input rst,
input VAR16,
output VAR21,
input VAR26,
input VAR25,
input VAR5,
output [3:0] VAR4,
output VAR32,
input VAR49,
input [3:0] VAR30,
output VAR34,
output [9:0] VAR48,
output [3:0] VAR45,
input [7:0] VAR6,
input VAR23,
output VAR... | gpl-3.0 |
PyLCARS/PythonUberHDL | myHDL_ComputerFundamentals/Memorys/fifoStatus.v | 3,193 | module MODULE1 (
wr,
rd,
VAR18,
VAR4,
VAR5,
VAR12,
VAR13,
VAR15,
VAR22,
VAR19,
VAR14,
clk,
VAR9
);
input wr;
input rd;
input VAR18;
input VAR4;
input [4:0] VAR5;
input [4:0] VAR12;
output VAR13;
wire VAR13;
output VAR15;
wire VAR15;
output VAR22;
wire VAR22;
output VAR19;
wire VAR19;
output VAR14;
wire VAR14;
input clk... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkmux2/sky130_fd_sc_hdll__clkmux2.pp.symbol.v | 1,338 | module MODULE1 (
input VAR2 ,
input VAR6 ,
output VAR8 ,
input VAR4 ,
input VAR7 ,
input VAR3,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18.pp.symbol.v | 1,356 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR6 ,
input VAR4,
input VAR3,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_refgen/sky130_fd_io__top_refgen.blackbox.v | 2,021 | module MODULE1 (
VAR16 ,
VAR10 ,
VAR17,
VAR2 ,
VAR6 ,
VAR12 ,
VAR7 ,
VAR5 ,
VAR13 ,
VAR3
);
output VAR16 ;
output VAR10 ;
inout VAR17;
input VAR2 ;
input VAR6 ;
input VAR12 ;
input VAR7 ;
input VAR5 ;
input VAR13 ;
input VAR3 ;
wire VAR11 ;
wire VAR15 ;
wire VAR1 ;
wire VAR4 ;
wire VAR8;
wire VAR18 ;
wire VAR14 ;
wire ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_2.behavioral.pp.v | 2,375 | module MODULE1( VAR9, VAR1, VAR6, VAR10, VAR5, VAR8, VAR7 );
input VAR5, VAR10, VAR1, VAR9;
inout VAR8, VAR7;
output VAR6;
VAR4 VAR2(.VAR9(VAR9),.VAR1(VAR1),.VAR6(VAR6),.VAR10(VAR10),.VAR5(VAR5),.VAR8(VAR8),.VAR7(VAR7));
VAR4 VAR3(.VAR9(VAR9),.VAR1(VAR1),.VAR6(VAR6),.VAR10(VAR10),.VAR5(VAR5),.VAR8(VAR8),.VAR7(VAR7)); | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sgb/address.v | 3,097 | module MODULE1(
input VAR5,
input [15:0] VAR20, input [23:0] VAR2, input [7:0] VAR9, input VAR16, output [23:0] VAR15, output VAR14, output VAR4, output VAR17, output VAR21, output VAR18,
output VAR12,
output VAR23,
output VAR19,
output VAR24,
output VAR13,
output VAR8
);
parameter [2:0]
VAR3 = 0,
VAR22 = 1,
VAR11 = 2,... | gpl-2.0 |
eda-globetrotter/MarcheProcessor | processor/reading/alu.v | 6,549 | module MODULE1(VAR18,VAR6,VAR14,VAR16,VAR10,VAR28,VAR29,VAR1,VAR21,VAR2);
input VAR18,VAR6;
input [7:0] VAR14;
input [7:0] VAR16;
input [15:0] VAR28;
output [7:0] VAR10;
output VAR29;
output VAR21;
output VAR1;
output VAR2;
reg [7:0] VAR10,VAR7,VAR33;
wire [7:0] VAR30;
reg VAR31;
wire VAR29,VAR21,VAR1,VAR2;
wire VAR4;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or2/sky130_fd_sc_hvl__or2.functional.v | 1,248 | module MODULE1 (
VAR2,
VAR3,
VAR6
);
output VAR2;
input VAR3;
input VAR6;
wire VAR1;
or VAR5 (VAR1, VAR6, VAR3 );
buf VAR4 (VAR2 , VAR1 );
endmodule | apache-2.0 |
alanachtenberg/CSCE-350 | Project 2/InstructionMemory.v | 10,813 | module MODULE1(VAR4, VAR1);
parameter VAR2 = 20;
parameter VAR5 = 40;
output [31:0] VAR4;
input [31:0] VAR1;
reg [31:0] VAR4;
always @ (VAR1) begin
case(VAR1)
32'h00: VAR4 = 32'h34080032;
32'h04: VAR4 = 32'hac080000;
32'h08: VAR4 = 32'h34080028;
32'h0C: VAR4 = 32'hac080004;
32'h10: VAR4 = 32'h3408001e;
32'h14: VAR4 = 3... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/np_core.v | 5,266 | module MODULE1
parameter VAR55=VAR102/8,
parameter VAR36 = 2,
parameter VAR22 = 2,
parameter VAR7 = 255,
parameter VAR44 = 8,
parameter VAR66 = 3,
parameter VAR8 = 4,
parameter VAR13 = 0)
( output [VAR102-1:0] VAR38,
output [VAR55-1:0] VAR109,
output VAR64,
input VAR17,
input [VAR102-1:0] VAR33,
input [VAR55-1:0] VAR11... | mit |
niamster/hdl | fifo/fifoctrl.v | 3,585 | module MODULE3
(input [VAR10:0] VAR6,
input [VAR10:0] VAR23,
input [VAR10:0] VAR4,
input VAR16,
input VAR14,
output VAR30,
output VAR5,
output [VAR10:0] VAR21,
output [VAR10:0] VAR20,
output VAR13,
output VAR7);
wire [VAR10:0] VAR31;
wire [VAR10:0] VAR3;
assign VAR31 = {VAR10+1{1'b0}};
assign VAR3 = {{VAR10{1'b0}}, 1'b... | mit |
borti4938/sd2snes | verilog/sd2snes_cx4/msu.v | 5,555 | module MODULE1(
input VAR26,
input enable,
input [13:0] VAR45,
input [7:0] VAR24,
input VAR41,
input [2:0] VAR16,
input [7:0] VAR31,
output [7:0] VAR29,
input VAR6,
input VAR4,
input VAR30,
output [7:0] VAR44,
output [7:0] VAR35,
output VAR28,
output [31:0] VAR2,
output [15:0] VAR38,
input [5:0] VAR1,
input [5:0] VAR19... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fah/sky130_fd_sc_ms__fah.symbol.v | 1,296 | module MODULE1 (
input VAR4 ,
input VAR2 ,
input VAR6 ,
output VAR8,
output VAR7
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd.pp.blackbox.v | 1,226 | module MODULE1 (
VAR4,
VAR1,
VAR2 ,
VAR3
);
input VAR4;
input VAR1;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/and3/sky130_fd_sc_hvl__and3.blackbox.v | 1,258 | module MODULE1 (
VAR8,
VAR1,
VAR7,
VAR4
);
output VAR8;
input VAR1;
input VAR7;
input VAR4;
supply1 VAR2;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
mgohde/MiniMicroII | cpu.v | 14,247 | module MODULE1(
VAR69,
VAR18,
VAR60,
addr,
VAR31,
VAR59
);
input VAR69;
input [15:0] VAR18;
input VAR60;
output [31:0] addr;
output [15:0] VAR31;
output VAR59;
reg VAR64;
wire clk;
assign clk=VAR69&&~VAR64;
reg [15:0] VAR73;
assign VAR31=VAR73;
reg VAR67;
assign VAR59=VAR67;
reg [15:0] VAR75[4:0]; wire [6:0] VAR55;
wir... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4b/sky130_fd_sc_ms__nand4b.functional.v | 1,432 | module MODULE1 (
VAR1 ,
VAR7,
VAR6 ,
VAR10 ,
VAR3
);
output VAR1 ;
input VAR7;
input VAR6 ;
input VAR10 ;
input VAR3 ;
wire VAR8 ;
wire VAR5;
not VAR9 (VAR8 , VAR7 );
nand VAR4 (VAR5, VAR3, VAR10, VAR6, VAR8);
buf VAR2 (VAR1 , VAR5 );
endmodule | apache-2.0 |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/internal_flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v | 54,854 | module MODULE1 (
VAR112,
VAR141,
VAR117,
VAR139,
VAR137,
VAR37,
VAR44,
VAR159,
VAR120,
VAR90,
VAR151,
VAR127,
VAR30,
VAR57,
VAR1,
VAR16,
VAR47,
VAR147,
VAR48,
VAR145,
VAR116,
VAR46,
VAR142,
VAR10,
VAR45,
VAR173,
VAR181
);
parameter VAR136 = 0;
parameter VAR69 = 0;
parameter VAR68 = 32;
parameter VAR31 = 20;
parameter V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtp/sky130_fd_sc_hs__dfrtp.blackbox.v | 1,295 | module MODULE1 (
VAR3,
VAR5 ,
VAR4 ,
VAR1
);
input VAR3;
input VAR5 ;
input VAR4 ;
output VAR1 ;
supply1 VAR6;
supply0 VAR2;
endmodule | apache-2.0 |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/openMSP430_fpga.v | 30,327 | module MODULE1 (
VAR252,
VAR183,
VAR322,
VAR242,
VAR335,
VAR120,
VAR196,
VAR134,
VAR332,
VAR258,
VAR169,
VAR227,
VAR215,
VAR11,
VAR211,
VAR7,
VAR260,
VAR328,
VAR157,
VAR14,
VAR278,
VAR319,
VAR324,
VAR149,
VAR208,
VAR77,
VAR318,
VAR39,
VAR338,
VAR298,
VAR15,
VAR225,
VAR295,
VAR107,
VAR63,
VAR281,
VAR30,
VAR71,
VAR205,
V... | bsd-3-clause |
kDaniu/miaow | src/verilog/rtl/dispatcher/gpu_interface.v | 16,448 | module MODULE1
(
VAR32, VAR48,
VAR104, VAR37,
VAR80, VAR105,
VAR66, VAR109,
VAR30, VAR86,
VAR78, VAR46,
clk, rst, VAR35,
VAR45, VAR25,
VAR95,
VAR72, VAR41,
VAR108, VAR107, VAR12,
VAR58, VAR24,
VAR31, VAR63,
VAR5, VAR73,
VAR101
) ;
parameter VAR69 = 6;
parameter VAR8 = 4;
parameter VAR85 = 6;
parameter VAR38 = 40;
param... | bsd-3-clause |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_debug.v | 11,912 | module MODULE1 (
VAR23,
VAR45,
VAR60,
VAR19,
VAR3,
VAR54,
VAR9,
VAR15,
VAR39,
VAR7,
VAR26,
VAR35,
VAR34,
VAR2,
VAR41,
VAR28,
VAR31,
VAR12,
VAR5,
VAR17,
VAR30,
VAR38
);
parameter VAR37 = 0; parameter VAR36 = 0;
input VAR23; input VAR45;
input [VAR11] VAR60; input VAR19; input VAR3; input [VAR61] VAR54; input VAR9; input... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphetap/sky130_fd_sc_ls__decaphetap.pp.symbol.v | 1,165 | module MODULE1 (
input VAR2 ,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | network_interface/arbiter_4_enq.v | 4,506 | module MODULE1 ( VAR11,
VAR4,
VAR1,
VAR2,
VAR8, VAR9, VAR7, VAR5, VAR6, VAR14, VAR12, VAR16, VAR3,
VAR15,
VAR13,
VAR10
);
input [15:0] VAR11;
input [1:0] VAR4;
input VAR1; input [1:0] VAR2;
output [15:0] VAR8; output [1:0] VAR9; output [15:0] VAR7; output [1:0] VAR5; output [15:0] VAR6; output [1:0] VAR14; output [15:0... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221oi/sky130_fd_sc_ls__a221oi.behavioral.v | 1,678 | module MODULE1 (
VAR7 ,
VAR14,
VAR16,
VAR6,
VAR4,
VAR5
);
output VAR7 ;
input VAR14;
input VAR16;
input VAR6;
input VAR4;
input VAR5;
supply1 VAR9;
supply0 VAR15;
supply1 VAR2 ;
supply0 VAR11 ;
wire VAR3 ;
wire VAR12 ;
wire VAR17;
and VAR8 (VAR3 , VAR6, VAR4 );
and VAR1 (VAR12 , VAR14, VAR16 );
nor VAR13 (VAR17, VAR3, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtn/sky130_fd_sc_hdll__dlrtn.symbol.v | 1,424 | module MODULE1 (
input VAR8 ,
output VAR1 ,
input VAR4,
input VAR7
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/8-way_2-tree/src/riffa/async_fifo.v | 8,704 | module MODULE1 #(
parameter VAR47 = 32, parameter VAR46 = 1024, parameter VAR61 = 2**VAR2(VAR46),
parameter VAR14 = VAR2(VAR61),
parameter VAR24 = VAR2(VAR61+1)
)
(
input VAR27, input VAR55, input VAR5, input VAR19, input [VAR47-1:0] VAR28, input VAR69, output [VAR47-1:0] VAR45, input VAR58, output VAR15, output VAR32 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2ai/sky130_fd_sc_hd__o2bb2ai.behavioral.v | 1,674 | module MODULE1 (
VAR3 ,
VAR8,
VAR4,
VAR15 ,
VAR1
);
output VAR3 ;
input VAR8;
input VAR4;
input VAR15 ;
input VAR1 ;
supply1 VAR10;
supply0 VAR13;
supply1 VAR9 ;
supply0 VAR16 ;
wire VAR5 ;
wire VAR12 ;
wire VAR7;
nand VAR11 (VAR5 , VAR4, VAR8 );
or VAR6 (VAR12 , VAR1, VAR15 );
nand VAR2 (VAR7, VAR5, VAR12);
buf VAR14 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.v | 2,221 | module MODULE2 (
VAR5 ,
VAR3 ,
VAR9,
VAR4 ,
VAR2 ,
VAR8 ,
VAR1
);
output VAR5 ;
input VAR3 ;
input VAR9;
input VAR4 ;
input VAR2 ;
input VAR8 ;
input VAR1 ;
VAR6 VAR7 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5 ,
VAR3 ,
VAR9
);
output VA... | apache-2.0 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/megacells/clk_doubler_bb.v | 7,864 | module MODULE1 (
VAR1,
VAR2);
input VAR1;
output VAR2;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/maj3/sky130_fd_sc_hd__maj3.blackbox.v | 1,264 | module MODULE1 (
VAR1,
VAR4,
VAR7,
VAR3
);
output VAR1;
input VAR4;
input VAR7;
input VAR3;
supply1 VAR2;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222o/sky130_fd_sc_hs__a222o.symbol.v | 1,374 | module MODULE1 (
input VAR5,
input VAR6,
input VAR4,
input VAR9,
input VAR3,
input VAR7,
output VAR1
);
supply1 VAR8;
supply0 VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4b/sky130_fd_sc_hdll__nor4b.blackbox.v | 1,330 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR6 ,
VAR7 ,
VAR9
);
output VAR1 ;
input VAR5 ;
input VAR6 ;
input VAR7 ;
input VAR9;
supply1 VAR4;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/4-way/ise/ipcore_dir/dram/user_design/rtl/clocking/mig_7series_v1_9_infrastructure.v | 24,158 | module MODULE1 #
(
parameter VAR16 = "VAR41", parameter VAR4 = 100, parameter VAR27 = 3000, parameter VAR46 = 2, parameter VAR54 = "VAR5",
parameter VAR51 = "VAR41",
parameter VAR56 = 4, parameter VAR48 = 1, parameter VAR57 = 45.0, parameter VAR13 = 16, parameter VAR11 = 4, parameter VAR2 = 64, parameter VAR3 = 16, par... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_int_mult64s_s5.v | 6,340 | module MODULE1 (
enable,
VAR20,
VAR13,
VAR17,
VAR21);
parameter VAR19 = 64;
parameter VAR18 = 64;
input enable;
input VAR20;
input [VAR19 - 1 : 0] VAR13;
input [VAR18 - 1 : 0] VAR17;
output reg [63:0] VAR21;
reg [VAR19 - 1 : 0] VAR10;
reg [VAR18 - 1 : 0] VAR2;
reg [VAR19 - 1 : 0] VAR4;
reg [VAR18 - 1 : 0] VAR7;
localpa... | mit |
chriswynnyk/american-put-verilog | american_put_cyclone/src/value_membank.v | 2,875 | module MODULE1(
clk,
VAR27,
VAR11,
VAR16,
VAR21,
VAR30,
VAR24,
VAR15,
VAR29,
VAR12,
VAR10,
VAR34,
VAR14,
VAR4,
VAR8
);
input clk;
input VAR27;
input VAR11;
input VAR30; input [9:0] VAR16;
input [9:0] VAR21;
input [63:0] VAR15;
input [63:0] VAR29;
input [63:0] VAR12;
input [63:0] VAR10;
output [63:0] VAR34;
output [63:0... | apache-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir/qmfir_uart/qmfir_240MHz/ISE_project/QMFIR_uart_if.v | 5,158 | module MODULE1 (
VAR28, VAR24, VAR21, VAR1, VAR16, VAR27,
VAR38, VAR10, clk, VAR11, VAR29
);
output [31:0] VAR28;
output [13:0] VAR24;
output VAR21;
output VAR1;
output VAR16;
output VAR27;
input [23:0] VAR38;
input [23:0] VAR10;
input clk;
input VAR11;
input VAR29;
reg [15:0] VAR8;
reg [31:0] VAR28;
parameter VAR9 = 0... | gpl-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/phyIniCommand1_and.v | 1,177 | module MODULE1
(
input [(VAR1-1):0] VAR7,
input [(VAR3-1):0] addr,
input VAR4, clk,
output [(VAR1-1):0] VAR6
);
reg [VAR1-1:0] VAR2[2**VAR3-1:0];
reg [VAR3-1:0] VAR5;
begin | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/timing/time_receiver.v | 4,037 | module MODULE1
(input clk, input rst,
output reg [63:0] VAR1,
output reg VAR35,
input VAR9);
wire VAR12, VAR33, VAR3, VAR19;
reg VAR27;
reg [9:0] VAR11;
reg [3:0] VAR29;
wire [8:0] VAR23;
reg [8:0] VAR32;
reg VAR5, VAR18;
always @(posedge clk) VAR5 <= VAR9;
always @(posedge clk) VAR18 <= VAR5;
always @(posedge clk)
VAR... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_stub.v | 4,673 | module MODULE1(VAR21, VAR35, VAR27, VAR6,
VAR16, VAR52, VAR56, VAR37, VAR47, VAR36,
VAR44, VAR24, VAR14, VAR11, VAR4, VAR2,
VAR46, VAR30, VAR54, VAR19, VAR7, VAR9, VAR3,
VAR42, VAR18, VAR33, VAR8, VAR39, VAR51,
VAR60, VAR12, VAR53, VAR55, VAR38, VAR25,
VAR50, VAR34, VAR13, VAR43, VAR40, VAR1, VAR32,
VAR10, VAR58, VAR29... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/system_acl_iface_hps.v | 16,175 | module MODULE1 #(
parameter VAR90 = 0,
parameter VAR35 = 0
) (
output wire VAR80, input wire VAR26, output wire [11:0] VAR89, output wire [20:0] VAR59, output wire [3:0] VAR57, output wire [2:0] VAR39, output wire [1:0] VAR87, output wire [1:0] VAR60, output wire [3:0] VAR31, output wire [2:0] VAR44, output wire VAR63,... | mit |
jncronin/jca | cpu/cpuv1.v | 14,651 | module MODULE1(clk, rst, addr, VAR39, VAR23, VAR41, VAR22, VAR35, VAR21, VAR13);
input clk;
input rst;
inout [7:0] VAR39;
output [31:0] addr;
output [31:0] VAR23;
output VAR35;
output VAR41;
output VAR22;
input VAR21;
output VAR13;
parameter VAR3 = 16; parameter VAR29 = 3; parameter VAR18 = 0;
parameter VAR25 = 1;
para... | mit |
theapi/nand2tetris_fpga | hack/ip/pll/pll.v | 17,093 | module MODULE1 (
input wire VAR1, input wire rst, output wire VAR6, output wire VAR3 );
VAR4 VAR2 (
.VAR1 (VAR1), .rst (rst), .VAR6 (VAR6), .VAR3 (VAR3), .VAR5 () );
endmodule | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/ff.v | 2,338 | module MODULE1
(
input VAR2,
input VAR3,
output reg VAR1
);
always @ (posedge VAR2) begin
VAR1 <= VAR3;
end
endmodule | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/cpc_clks.v | 17,447 | module MODULE1 (
input wire VAR8, input wire rst, output wire VAR2, output wire VAR4, output wire VAR7, output wire VAR3 );
VAR5 VAR6 (
.VAR8 (VAR8), .rst (rst), .VAR2 (VAR2), .VAR4 (VAR4), .VAR7 (VAR7), .VAR3 (VAR3), .VAR1 () );
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32o/sky130_fd_sc_ls__a32o.functional.pp.v | 2,224 | module MODULE1 (
VAR3 ,
VAR15 ,
VAR6 ,
VAR11 ,
VAR2 ,
VAR8 ,
VAR9,
VAR16,
VAR13 ,
VAR1
);
output VAR3 ;
input VAR15 ;
input VAR6 ;
input VAR11 ;
input VAR2 ;
input VAR8 ;
input VAR9;
input VAR16;
input VAR13 ;
input VAR1 ;
wire VAR10 ;
wire VAR5 ;
wire VAR14 ;
wire VAR17;
and VAR18 (VAR10 , VAR11, VAR15, VAR6 );
and VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2/sky130_fd_sc_hdll__and2.behavioral.v | 1,358 | module MODULE1 (
VAR2,
VAR4,
VAR3
);
output VAR2;
input VAR4;
input VAR3;
supply1 VAR9;
supply0 VAR8;
supply1 VAR10 ;
supply0 VAR7 ;
wire VAR5;
and VAR6 (VAR5, VAR4, VAR3 );
buf VAR1 (VAR2 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtn/sky130_fd_sc_hd__dlrtn.functional.pp.v | 2,056 | module MODULE1 (
VAR17 ,
VAR6,
VAR11 ,
VAR16 ,
VAR1 ,
VAR8 ,
VAR12 ,
VAR2
);
output VAR17 ;
input VAR6;
input VAR11 ;
input VAR16 ;
input VAR1 ;
input VAR8 ;
input VAR12 ;
input VAR2 ;
wire VAR13 ;
wire VAR14;
wire VAR5 ;
not VAR7 (VAR13 , VAR6 );
not VAR3 (VAR14, VAR16 );
VAR10 VAR15 VAR4 (VAR5 , VAR11, VAR14, VAR13, ... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_010bits.v | 1,917 | module MODULE2 (
clk,
VAR22, VAR27, VAR20, VAR1, VAR5, VAR7, VAR23, VAR17,
sum,
);
input clk;
input [VAR16+0-1:0] VAR22, VAR27, VAR20, VAR1, VAR5, VAR7, VAR23, VAR17;
output [VAR16 :0] sum;
reg [VAR16 :0] sum;
wire [VAR16+3-1:0] VAR25;
wire [VAR16+2-1:0] VAR24, VAR12;
wire [VAR16+1-1:0] VAR15, VAR34, VAR3, VAR26;
reg [... | mit |
FAST-Switch/fast | projects/SDTS/example/hw-src/cdp/rx_tx_1000.v | 4,098 | module MODULE1(
VAR36,
VAR6,
VAR35, VAR34, reset,
VAR22,
VAR29,
VAR32,
VAR45,
VAR38,
VAR13,
VAR7, VAR23,
VAR16,
VAR31,
VAR19,
VAR3, VAR44,
VAR27,
VAR11,
VAR18,
VAR5,
VAR28,
VAR40,
VAR21
);
input VAR36;
input VAR6;
input VAR35;
input VAR34;
input reset;
output [3:0]VAR22;
output VAR29;
output VAR32;
input [3:0]VAR45;
in... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfsbp/sky130_fd_sc_ls__dfsbp.behavioral.pp.v | 2,300 | module MODULE1 (
VAR18 ,
VAR11 ,
VAR5 ,
VAR3 ,
VAR14,
VAR19 ,
VAR15 ,
VAR1 ,
VAR7
);
output VAR18 ;
output VAR11 ;
input VAR5 ;
input VAR3 ;
input VAR14;
input VAR19 ;
input VAR15 ;
input VAR1 ;
input VAR7 ;
wire VAR22 ;
wire VAR8 ;
reg VAR21 ;
wire VAR12 ;
wire VAR4;
wire VAR17 ;
wire VAR2 ;
wire VAR16 ;
wire VAR20 ;
... | apache-2.0 |
chriz2600/DreamcastHDMI | Core/source/adv7513/adv7513_reconfig.v | 3,931 | module MODULE1 (
input VAR3,
input [7:0] VAR10,
input [7:0] VAR7,
input [1:0] VAR16,
output VAR14 VAR9,
output [7:0] VAR8,
output [1:0] VAR15,
output VAR5
);
reg [7:0] VAR6 = 0;
reg [1:0] VAR12 = 0;
reg [7:0] VAR4 = 0;
reg [7:0] VAR2 = 8'b01100000;
reg [1:0] VAR1 = 0;
reg VAR13;
VAR14 VAR11; | mit |
tloinuy/opencpi-opencv | opencpi/components/wbr.hdl/wbr.v | 5,408 | module MODULE1 (
VAR45,
VAR19,
VAR43,
VAR5,
VAR8,
VAR3,
VAR30,
VAR56,
VAR18,
VAR21,
VAR49,
VAR51,
VAR57,
VAR34,
VAR11,
VAR50,
VAR41,
VAR22,
VAR1,
VAR31,
VAR36,
VAR17,
VAR6,
VAR46,
VAR15,
VAR52,
VAR13,
VAR12 );
input VAR45;
input VAR19;
input VAR43;
input VAR5;
input [ 2 : 0 ] VAR28;
input VAR54;
input [ 3 : 0 ] VAR40;
... | gpl-2.0 |
peterfox/proxmark3 | fpga/hi_read_rx_xcorr.v | 5,222 | module MODULE1(
VAR25, VAR3, VAR11,
VAR1, VAR19, VAR8, VAR32, VAR24, VAR2,
VAR20, VAR27,
VAR26, VAR23, VAR7, VAR21,
VAR4, VAR16,
VAR29,
VAR28, VAR9, VAR12
);
input VAR25, VAR3, VAR11;
output VAR1, VAR19, VAR8, VAR32, VAR24, VAR2;
input [7:0] VAR20;
output VAR27;
input VAR7;
output VAR26, VAR23, VAR21;
input VAR4, VAR16... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/vrt/vita_rx_chain.v | 4,761 | module MODULE1
parameter VAR28=0,
parameter VAR10=10,
parameter VAR72=1,
parameter VAR3=0)
(input clk, input reset,
input VAR22, input [7:0] VAR15, input [31:0] VAR53,
input VAR63, input [7:0] VAR36, input [31:0] VAR43,
input [63:0] VAR59,
input [31:0] VAR64, input VAR42,
output [35:0] VAR4, output VAR70, input VAR23,
... | gpl-2.0 |
ZiCog/xoro | rtl/spi.v | 2,112 | module MODULE1 (
input wire clk,
input wire VAR7,
input wire VAR10,
output wire VAR5,
output reg [15:0] VAR6,
input wire [15:0] VAR9,
output reg VAR11,
output reg VAR2,
output reg VAR3,
input wire VAR1
);
reg [3:0] state;
reg [15:0] VAR4;
reg [15:0] VAR8;
always @ (posedge clk) begin
VAR8 = VAR8 + 1;
if (VAR8 == 33) be... | mit |
osrf/wandrr | firmware/motor_controller/fpga/usb_crc16.v | 3,263 | module MODULE1(
input [7:0] VAR3,
input VAR1,
output [15:0] VAR6,
input rst,
input VAR2);
reg [15:0] VAR5, VAR7;
wire [7:0] VAR4 = { VAR3[0], VAR3[1], VAR3[2], VAR3[3], VAR3[4], VAR3[5], VAR3[6], VAR3[7] };
assign VAR6 = { ~VAR5[ 0], ~VAR5[ 1], ~VAR5[ 2], ~VAR5[ 3],
~VAR5[ 4], ~VAR5[ 5], ~VAR5[ 6], ~VAR5[ 7],
~VAR5[ 8]... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.symbol.v | 1,332 | module MODULE1 (
input VAR2 ,
output VAR4,
input VAR3 ,
input VAR1
);
endmodule | apache-2.0 |
manasks/ece_510_pre_si_val | Lab0/alu_datapath.v | 3,185 | module MODULE1(clk, VAR28, VAR36, VAR9, VAR25, VAR23, VAR45, VAR5, VAR50);
parameter VAR20 = 8;
input clk;
input VAR28;
input VAR36;
input VAR9;
input VAR25;
input VAR23;
output VAR45;
output VAR5;
output VAR50;
reg VAR50;
wire clk;
wire [VAR20-1:0] VAR28;
wire [1:0] VAR36;
wire VAR9;
wire VAR25;
wire VAR23;
reg VAR45;... | gpl-3.0 |
ipburbank/Raster-Laser-Projector | src/Video_In/synthesis/submodules/Raster_Laser_Projector_Video_In_video_chroma_resampler_0.v | 7,298 | module MODULE1 (
clk,
reset,
VAR20,
VAR21,
VAR13,
VAR28,
VAR17,
VAR18,
VAR1,
VAR11,
VAR19,
VAR9,
VAR5,
VAR25
);
parameter VAR6 = 15; parameter VAR2 = 23;
parameter VAR3 = 0; parameter VAR16 = 1;
input clk;
input reset;
input [VAR6:0] VAR20;
input VAR21;
input VAR13;
input [VAR3:0] VAR28;
input VAR17;
input VAR18;
outpu... | gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ip/block_design_auto_pc_0/synth/block_design_auto_pc_0.v | 13,163 | module MODULE1 (
VAR12,
VAR61,
VAR79,
VAR74,
VAR85,
VAR75,
VAR99,
VAR95,
VAR33,
VAR25,
VAR77,
VAR96,
VAR110,
VAR1,
VAR56,
VAR47,
VAR57,
VAR28,
VAR106,
VAR6,
VAR18,
VAR69,
VAR22,
VAR35,
VAR39,
VAR3,
VAR67,
VAR103,
VAR102,
VAR86,
VAR107,
VAR10,
VAR27,
VAR37,
VAR23,
VAR81,
VAR36,
VAR44,
VAR70,
VAR91,
VAR52,
VAR97,
VAR11,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfsbp/sky130_fd_sc_hs__sdfsbp.behavioral.pp.v | 2,853 | module MODULE1 (
VAR10 ,
VAR28 ,
VAR5 ,
VAR31 ,
VAR1 ,
VAR14 ,
VAR23 ,
VAR3 ,
VAR18
);
input VAR10 ;
input VAR28 ;
output VAR5 ;
output VAR31 ;
input VAR1 ;
input VAR14 ;
input VAR23 ;
input VAR3 ;
input VAR18;
wire VAR15 ;
wire VAR7 ;
wire VAR17 ;
reg VAR21 ;
wire VAR9 ;
wire VAR16 ;
wire VAR25 ;
wire VAR13;
wire VAR1... | apache-2.0 |
adbrant/zuma-fpga | verilog/platforms/altera/SDPR.v | 9,059 | module MODULE1 (
VAR9,
VAR27,
VAR4,
VAR31,
VAR45,
VAR11);
input VAR9;
input [0:0] VAR27;
input [VAR38-1:0] VAR4;
input [VAR38-1:0] VAR31;
input VAR45;
output [0:0] VAR11;
tri0 VAR45;
wire [0:0] VAR3;
wire [0:0] VAR11 = VAR3[0:0];
VAR14 VAR22 (
.VAR27 (VAR27),
.VAR4 (VAR4),
.VAR45 (VAR45),
.VAR43 (VAR9),
.VAR31 (VAR31),... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31o/sky130_fd_sc_ms__a31o.functional.v | 1,434 | module MODULE1 (
VAR10 ,
VAR8,
VAR1,
VAR3,
VAR7
);
output VAR10 ;
input VAR8;
input VAR1;
input VAR3;
input VAR7;
wire VAR9 ;
wire VAR5;
and VAR2 (VAR9 , VAR3, VAR8, VAR1 );
or VAR4 (VAR5, VAR9, VAR7 );
buf VAR6 (VAR10 , VAR5 );
endmodule | apache-2.0 |
Proxmark/proxmark3 | fpga/fpga_hf.v | 7,670 | module MODULE1(
input VAR46, output VAR26, input VAR2, input VAR55,
input VAR83, input VAR17, input VAR78,
output VAR94, output VAR42,
output VAR20, output VAR54, output VAR92, output VAR11,
input [7:0] VAR75, output VAR13, output VAR67,
output VAR25, output VAR95, input VAR93, output VAR39,
input VAR33, input VAR36,
o... | gpl-2.0 |
theapi/de0-nano | vga/vga_800x480_buffered/frame_buffer.v | 1,727 | module MODULE1(
clk,
VAR3,
VAR6,
VAR5,
VAR2,
VAR8,
VAR9
);
input clk;
input [15:0] VAR3;
input [15:0] VAR6; input VAR5;
input [10:0] VAR2; input [10:0] VAR8;
output VAR9;
wire[15:0] VAR4;
wire[4:0] VAR10;
wire[15:0] VAR13;
assign VAR13 = (VAR2 + (VAR8 * 800) ) >> 4; assign VAR10 = VAR2 + VAR8;
assign VAR9 = VAR4[VAR10[... | mit |
r2apu/Labo_Digitales | L3/SubR/Collaterals.v | 6,531 | module MODULE2 # (parameter VAR5=16)
(
input wire VAR6, VAR22,
input wire [VAR5-1:0] VAR12,
input wire VAR44,
output reg [VAR5-1:0] VAR39
);
always @(posedge VAR6 )
begin
if (VAR22)
VAR39 = VAR12;
end
else
begin
if (VAR44)
VAR39 = VAR39 + 1;
end
end
endmodule
module MODULE1 (VAR41,VAR37,VAR4,VAR26, sel, out);
input wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22oi/sky130_fd_sc_ls__a22oi.symbol.v | 1,371 | module MODULE1 (
input VAR8,
input VAR7,
input VAR6,
input VAR1,
output VAR3
);
supply1 VAR5;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/vcr_sw_alloc_ip.v | 11,485 | module MODULE1
(clk, reset, VAR35, VAR16, VAR17, VAR50, VAR41,
VAR10, VAR31, VAR32);
parameter VAR20 = 2;
parameter VAR15 = 5;
parameter VAR44 = VAR30;
parameter VAR19 = VAR2;
parameter VAR43 = VAR49;
input clk;
input reset;
input [0:VAR20*VAR15-1] VAR35;
input [0:VAR20-1] VAR16;
output [0:VAR15-1] VAR17;
wire [0:VAR15... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfsbp/sky130_fd_sc_ms__dfsbp.pp.blackbox.v | 1,372 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR2 ,
VAR1 ,
VAR9,
VAR3 ,
VAR8 ,
VAR4 ,
VAR6
);
output VAR7 ;
output VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR9;
input VAR3 ;
input VAR8 ;
input VAR4 ;
input VAR6 ;
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/V2NFC100DDR/src/NPM_Toggle_CAL_DDR100.v | 23,885 | module MODULE1
(
parameter VAR3 = 4
)
(
VAR59 ,
VAR65 ,
VAR52 ,
VAR9 ,
VAR34 ,
VAR51 ,
VAR33 ,
VAR14 ,
VAR74 ,
VAR50 ,
VAR28 ,
VAR7 ,
VAR38 ,
VAR47 ,
VAR10 ,
VAR25 ,
VAR1
);
input VAR59 ;
input VAR65 ;
output VAR52 ;
output VAR9 ;
input VAR34 ;
input [VAR3 - 1:0] VAR51 ;
input [3:0] VAR33 ;
input VAR14 ;
input [7:0] VA... | gpl-3.0 |
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