repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp.pp.blackbox.v | 1,479 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR3 ,
VAR10 ,
VAR9 ,
VAR5 ,
VAR11,
VAR8 ,
VAR7 ,
VAR4 ,
VAR1
);
output VAR6 ;
output VAR2 ;
input VAR3 ;
input VAR10 ;
input VAR9 ;
input VAR5 ;
input VAR11;
input VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
eda-globetrotter/PicenoDecoders | final/src/alu_add.v | 31,406 | module MODULE1 (VAR18,VAR10,VAR6,VAR15,VAR28);
output [0:127] VAR28;
input [0:127] VAR18;
input [0:127] VAR10;
input [0:1] VAR6;
input [0:4] VAR15;
parameter VAR30 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR28;
reg [0:127] VAR24;
reg [0:15] VAR12;
reg [0:15] VAR21;
reg [0:15] VAR16;
reg [0:15] VAR17;
reg [... | mit |
Anirudh94/Connect4-FPGA | Connect4/redDiskModule.v | 6,250 | module MODULE1 (
address,
VAR20,
VAR25);
input [7:0] address;
input VAR20;
output [2:0] VAR25;
tri1 VAR20;
wire [2:0] VAR13;
wire [2:0] VAR25 = VAR13[2:0];
VAR8 VAR42 (
.VAR38 (address),
.VAR21 (VAR20),
.VAR26 (VAR13),
.VAR6 (1'b0),
.VAR1 (1'b0),
.VAR39 (1'b1),
.VAR48 (1'b0),
.VAR7 (1'b0),
.VAR35 (1'b1),
.VAR12 (1'b1),... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/phy_top.v | 42,331 | module MODULE1 #
(
parameter VAR234 = 100, parameter VAR53 = "0", parameter VAR62 = 3, parameter VAR308 = "8", parameter VAR122 = "VAR169", parameter VAR56 = 1, parameter VAR246 = 5,
parameter VAR145 = 12, parameter VAR14 = 1, parameter VAR204 = 1, parameter VAR284 = 5,
parameter VAR154 = 8, parameter VAR73 = 64, param... | lgpl-3.0 |
DougFirErickson/parallella-hw | fpga/src/i2c/hdl/parallella_i2c.v | 2,505 | module MODULE1
(
VAR9, VAR1,
VAR20, VAR18,
VAR23, VAR19, VAR17, VAR16
);
input VAR23;
input VAR19;
output VAR9;
input VAR17;
input VAR16;
output VAR1;
inout VAR20;
inout VAR18;
wire VAR20 = VAR19 ? 1'VAR8 : VAR23;
wire VAR9 = VAR20;
wire VAR18 = VAR16 ? 1'VAR8 : VAR17;
wire VAR1 = VAR18;
VAR7 #(
.VAR13(8), .VAR12("VAR5... | gpl-3.0 |
lsnow/mips32 | EX_stage.v | 2,417 | module MODULE1(
clk, rst, VAR14, VAR22, VAR13, VAR10,
VAR20, VAR19, VAR9, VAR11,
VAR12, VAR15, VAR3, VAR21,
VAR18,
VAR1, VAR5, VAR8,
VAR2, VAR6, VAR16,
VAR17, VAR7, VAR4);
input clk;
input rst;
input VAR14;
input VAR22;
input VAR13;
input VAR10;
input VAR20;
input VAR19;
input VAR9;
input [31:0] VAR11;
input [8:0] VAR1... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab0-3/single_register/register.v | 1,079 | module MODULE1(VAR4, VAR7, VAR3, VAR1, clk, reset, VAR2);
input wire [4:0] VAR4; input wire [4:0] VAR7; input wire [31:0] VAR3;input wire VAR1; input wire clk; input wire reset;
output wire [31:0] VAR2;
reg [31:0] VAR6 [31:0]; reg [31:0] VAR8;
task VAR5;
begin
for ( VAR8 = 0; VAR8 < 32; VAR8 = VAR8 + 1) begin
VAR6[VAR8... | mit |
QuantumQuadrate/HamamatsuCameralink | camera_deserializer.v | 7,076 | module MODULE1
(
VAR50,
VAR88,
VAR27,
VAR63,
VAR39,
VAR46,
VAR64,
VAR12,
VAR96,
VAR53,
VAR37,
VAR83,
VAR41,
VAR106,
VAR66,
VAR87,
VAR5,
VAR45,
VAR101,
VAR11,
VAR79,
VAR14,
VAR13,
VAR97,
VAR24,
VAR44,
VAR85,
VAR84,
VAR48,
VAR91,
VAR82,
VAR28,
VAR67,
VAR58,
VAR43,
VAR21,
VAR73,
VAR99,
rst
);
input VAR50;
input VAR88;
inp... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3/sky130_fd_sc_hd__nor3_2.v | 2,198 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR1 ,
VAR7 ,
VAR6,
VAR10,
VAR8 ,
VAR3
);
output VAR2 ;
input VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR6;
input VAR10;
input VAR8 ;
input VAR3 ;
VAR5 VAR4 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211ai/sky130_fd_sc_hs__o211ai.functional.pp.v | 1,949 | module MODULE1 (
VAR9,
VAR2,
VAR12 ,
VAR13 ,
VAR15 ,
VAR11 ,
VAR3
);
input VAR9;
input VAR2;
output VAR12 ;
input VAR13 ;
input VAR15 ;
input VAR11 ;
input VAR3 ;
wire VAR3 VAR7 ;
wire VAR5 ;
wire VAR1;
or VAR8 (VAR7 , VAR15, VAR13 );
nand VAR4 (VAR5 , VAR3, VAR7, VAR11 );
VAR6 VAR10 (VAR1, VAR5, VAR9, VAR2);
buf VAR14... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4b/sky130_fd_sc_ms__nand4b.behavioral.v | 1,528 | module MODULE1 (
VAR4 ,
VAR5,
VAR3 ,
VAR8 ,
VAR6
);
output VAR4 ;
input VAR5;
input VAR3 ;
input VAR8 ;
input VAR6 ;
supply1 VAR12;
supply0 VAR13;
supply1 VAR1 ;
supply0 VAR2 ;
wire VAR9 ;
wire VAR10;
not VAR14 (VAR9 , VAR5 );
nand VAR11 (VAR10, VAR6, VAR8, VAR3, VAR9);
buf VAR7 (VAR4 , VAR10 );
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/buffers/dpMem_dc.v | 3,780 | module MODULE1( VAR2, VAR11, VAR3, VAR10, VAR7, VAR4, VAR8, VAR6);
parameter VAR9 = 8;
parameter VAR1 = 64;
parameter VAR5 = 6;
input VAR3;
input VAR10;
input [VAR9-1:0] VAR7;
output [VAR9-1:0] VAR6;
input VAR4;
input VAR8;
input [VAR5-1:0] VAR2;
input [VAR5-1:0] VAR11;
wire VAR3;
wire VAR10;
wire [VAR9-1:0] VAR7;
reg ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_2.functional.pp.v | 1,069 | module MODULE1( VAR11, VAR14, VAR1, VAR3, VAR10, VAR6 );
input VAR3, VAR14, VAR1;
inout VAR10, VAR6;
output VAR11;
wire VAR9;
and VAR13( VAR9, VAR3, VAR14 );
wire VAR8;
not VAR7( VAR8, VAR1 );
wire VAR15;
and VAR12( VAR15, VAR8, VAR3 );
wire VAR4;
and VAR5( VAR4, VAR14, VAR1 );
or VAR2( VAR11, VAR9, VAR15, VAR4 );
endm... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41a/sky130_fd_sc_hd__o41a_4.v | 2,411 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR8 ,
VAR12 ,
VAR11 ,
VAR6 ,
VAR7,
VAR1,
VAR3 ,
VAR4
);
output VAR5 ;
input VAR2 ;
input VAR8 ;
input VAR12 ;
input VAR11 ;
input VAR6 ;
input VAR7;
input VAR1;
input VAR3 ;
input VAR4 ;
VAR9 VAR10 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR7(... | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_HLS_accel_0_0/hdl/verilog/HLS_accel_dmul_64ns_64ns_64_6_max_dsp.v | 1,991 | module MODULE1
VAR22 = 6,
VAR19 = 6,
VAR16 = 64,
VAR21 = 64,
VAR26 = 64
)(
input wire clk,
input wire reset,
input wire VAR9,
input wire [VAR16-1:0] VAR14,
input wire [VAR21-1:0] VAR24,
output wire [VAR26-1:0] dout
);
wire VAR25;
wire VAR2;
wire VAR27;
wire [63:0] VAR8;
wire VAR3;
wire [63:0] VAR17;
wire VAR7;
wire [63... | mit |
lsnow/mips32 | IF_stage.v | 1,106 | module MODULE1(
clk, rst, VAR6, VAR5, VAR3, VAR1,
VAR8, VAR4,
VAR7,VAR2);
input clk;
input rst;
input VAR6;
input VAR5;
input VAR3;
input [31:0] VAR1;
input [31:0] VAR8;
input [31:0] VAR4;
output reg [31:0] VAR7;
output reg [31:0] VAR2;
always @(posedge clk) begin
VAR7 <= rst ? 32'b0 : (VAR3 ? VAR7 : ((VAR6 | VAR5) ? 3... | gpl-2.0 |
peteasa/oh | src/accelerator/hdl/accelerator.v | 7,324 | module MODULE1 (
VAR11, VAR58, VAR61, VAR26, VAR53,
VAR38, VAR1, VAR35, VAR5,
clk, VAR33, VAR55, VAR42, VAR44, VAR28,
VAR50, VAR2, VAR40, VAR4, VAR6
);
parameter VAR34 = 32; parameter VAR27 = 2 * VAR34 + 40; parameter VAR12 = 12'h810; parameter VAR43 = 6;
input clk; input VAR33;
output VAR11;
output [VAR27-1:0] VAR58;
... | mit |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/mouse_out.v | 1,709 | module MODULE1(
input wire [9:0] VAR3,
input wire [8:0] VAR2,
input VAR4,
output reg [4:0]VAR1
);
reg [1:0] VAR5;
reg [2:0] VAR6;
always @
begin
if(VAR4 && VAR5 < 3 && VAR6 < 6)
begin
VAR1 = {(VAR5 * 6) + VAR6}[4:0];
end
else
begin
VAR1 = 5'b10010;
end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfstp/sky130_fd_sc_ls__dfstp.functional.v | 1,624 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR11 ,
VAR10
);
output VAR1 ;
input VAR6 ;
input VAR11 ;
input VAR10;
wire VAR2;
wire VAR3 ;
not VAR9 (VAR3 , VAR10 );
VAR8 VAR7 VAR5 (VAR2 , VAR11, VAR6, VAR3 );
buf VAR4 (VAR1 , VAR2 );
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_rams/dpram_64x64.v | 9,634 | module MODULE1 (
VAR9,
VAR61,
VAR58,
VAR59,
VAR8,
VAR51,
VAR49);
input [7:0] VAR9;
input VAR61;
input [63:0] VAR58;
input [5:0] VAR59;
input [5:0] VAR8;
input VAR51;
output [63:0] VAR49;
wire [63:0] VAR53;
wire [63:0] VAR49 = VAR53[63:0];
VAR39 VAR60 (
.VAR21 (VAR51),
.VAR29 (VAR61),
.VAR9 (VAR9),
.VAR50 (VAR8),
.VAR42... | gpl-3.0 |
manu3193/ControladorElevadorTDD | Sincronizador.v | 10,481 | module MODULE1( clk, VAR49, VAR19, VAR45, VAR44, VAR9,
VAR29, VAR30, VAR36, VAR20, VAR12,
VAR11, VAR28, VAR42, VAR2, VAR15,
VAR22);
input VAR19, VAR45, clk;
input [2:0] VAR49;
input [1:0] VAR44, VAR9, VAR29, VAR30, VAR36;
output reg VAR12, VAR11;
output reg [2:0] VAR20;
output reg [1:0] VAR28, VAR42, VAR2, VAR15, VAR22... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.behavioral.v | 6,154 | module MODULE1( VAR57, VAR15, VAR56, VAR52, VAR34 );
input VAR56, VAR57, VAR15, VAR52;
output VAR34;
reg VAR19;
VAR6 VAR42(.VAR57(VAR57),.VAR15(VAR15),.VAR56(VAR56),.VAR52(VAR52),.VAR34(VAR34),.VAR19(VAR19));
VAR6 VAR37(.VAR57(VAR57),.VAR15(VAR15),.VAR56(VAR56),.VAR52(VAR52),.VAR34(VAR34),.VAR19(VAR19));
and VAR41(VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.v | 2,583 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR11 ,
VAR12 ,
VAR9 ,
VAR2,
VAR6 ,
VAR3 ,
VAR7 ,
VAR4
);
output VAR8 ;
input VAR5 ;
input VAR11 ;
input VAR12 ;
input VAR9 ;
input VAR2;
input VAR6 ;
input VAR3 ;
input VAR7 ;
input VAR4 ;
VAR1 VAR10 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR12(VAR12),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.v | 2,290 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR4 ,
VAR5 ,
VAR7,
VAR1 ,
VAR9
);
output VAR8 ;
input VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR7;
input VAR1 ;
input VAR9 ;
VAR6 VAR2 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR8,
VAR3
);
output VAR8;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/inv/sky130_fd_sc_hd__inv_1.v | 1,995 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR3,
VAR1,
VAR7 ,
VAR4
);
output VAR5 ;
input VAR2 ;
input VAR3;
input VAR1;
input VAR7 ;
input VAR4 ;
VAR6 VAR8 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR5,
VAR2
);
output VAR5;
input VAR2;
supply1 VAR3;
supply0 VAR1;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_1.functional.pp.v | 1,520 | module MODULE1( VAR4, VAR6, VAR15, VAR2, VAR1, VAR11, VAR9 );
input VAR2, VAR1, VAR6, VAR4;
inout VAR11, VAR9;
output VAR15;
wire VAR20;
not VAR7( VAR20, VAR2 );
wire VAR14;
not VAR13( VAR14, VAR1 );
wire VAR16;
and VAR8( VAR16, VAR20, VAR14 );
wire VAR12;
not VAR5( VAR12, VAR6 );
wire VAR10;
not VAR18( VAR10, VAR4 );
... | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_021bits.v | 1,917 | module MODULE1 (
clk,
VAR20, VAR17, VAR15, VAR6, VAR14, VAR21, VAR9, VAR24,
sum,
);
input clk;
input [VAR7+0-1:0] VAR20, VAR17, VAR15, VAR6, VAR14, VAR21, VAR9, VAR24;
output [VAR7 :0] sum;
reg [VAR7 :0] sum;
wire [VAR7+3-1:0] VAR13;
wire [VAR7+2-1:0] VAR27, VAR2;
wire [VAR7+1-1:0] VAR12, VAR23, VAR22, VAR31;
reg [VAR7... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor2/sky130_fd_sc_lp__xnor2_m.v | 2,129 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR2 ,
VAR7,
VAR3,
VAR9 ,
VAR6
);
output VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR7;
input VAR3;
input VAR9 ;
input VAR6 ;
VAR5 VAR8 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR1,
VAR4,
VAR2
);
output VAR1;
... | apache-2.0 |
monotone-RK/FACE | MCSoC-15/4-way/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_calib_top.v | 76,571 | module MODULE1 #
(
parameter VAR4 = 100,
parameter VAR290 = 2, parameter VAR354 = 2500, parameter VAR226 = 3333, parameter VAR137 = 3, parameter VAR312 = "VAR241", parameter VAR272 = 8, parameter VAR355 = 4,
parameter VAR275 = 3,
parameter VAR351 = "VAR166", parameter VAR71 = 4'hc,
parameter VAR289 = 4'hf,
parameter VA... | mit |
lvd2/zxevo | fpga/sdload/trunk/video/video_vga_double.v | 2,890 | module MODULE1(
input wire clk,
input wire VAR9,
input wire VAR5,
input wire [ 5:0] VAR6,
input wire VAR1,
output reg [ 5:0] VAR7
);
reg [9:0] VAR10; reg [9:0] VAR8;
reg VAR2;
reg VAR4;
wire [ 7:0] VAR3;
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_hdivops.v | 1,888 | module MODULE1(
input VAR7,
input VAR21,
output VAR3,
input VAR17,
output VAR9,
input signed [11:0] VAR5,
input signed [11:0] VAR13,
input signed [17:0] VAR2,
input signed [17:0] VAR10,
input signed [17:0] VAR1,
input signed [17:0] VAR4,
output reg VAR12,
input VAR14,
output reg signed [11:0] VAR15,
output reg signed [... | lgpl-3.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/whr_ip_ctrl_mac.v | 27,632 | module MODULE1
(clk, reset, VAR57, VAR43, VAR174, VAR173, VAR76,
VAR133, VAR104, VAR3, VAR121, VAR109,
VAR145, VAR66, VAR134, VAR152,
VAR61, VAR114);
parameter VAR4 = 8;
localparam VAR17 = VAR171(VAR4);
parameter VAR79 = 4;
parameter VAR98 = 4;
localparam VAR53 = VAR171(VAR98);
parameter VAR100 = 2;
localparam VAR91 = ... | mit |
hoglet67/CoPro6502 | src/Arlet/cpu_65c02.v | 39,673 | module MODULE1( clk, reset, VAR83, VAR148, VAR118, VAR145, VAR127, VAR85, VAR18 );
input clk; input reset; output reg [15:0] VAR83; input [7:0] VAR148; output [7:0] VAR118; output VAR145; input VAR127; input VAR85; input VAR18;
reg [15:0] VAR214; reg [7:0] VAR237; reg [7:0] VAR66; wire [7:0] VAR92;
reg [7:0] VAR240; re... | gpl-3.0 |
dawsonjon/FPGA-TX | synthesis/cmod_a7_15/tx/main_0.v | 379,615 | module MODULE1(VAR1,VAR36,VAR49,VAR72,VAR79,VAR45,VAR22,VAR107,VAR31,VAR90,VAR4,VAR65,clk,rst,VAR13,VAR104,VAR14,VAR84,VAR83,VAR103,VAR94,VAR59,VAR66,VAR47,VAR53,VAR68,VAR87,VAR54,VAR61,VAR89);
integer VAR82;
parameter VAR102 = 4'd0,
VAR81 = 4'd1,
VAR108 = 4'd2,
VAR5 = 4'd3,
VAR40 = 4'd4,
VAR60 = 4'd5,
read = 4'd6,
wri... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/maj3/sky130_fd_sc_ls__maj3_1.v | 2,174 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR2 ,
VAR3 ,
VAR8,
VAR10,
VAR7 ,
VAR9
);
output VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR8;
input VAR10;
input VAR7 ;
input VAR9 ;
VAR5 VAR6 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/sdr_lib/cic_interp.v | 2,632 | module MODULE1(VAR6,reset,enable,VAR8,VAR15,VAR1,VAR2,VAR18);
parameter VAR19 = 16;
parameter VAR9 = 4;
parameter VAR5 = 7;
parameter VAR3 = (VAR9-1)*VAR5;
input VAR6;
input reset;
input enable;
input [7:0] VAR8;
input VAR15,VAR1;
input [VAR19-1:0] VAR2;
wire [VAR19-1:0] VAR2;
output [VAR19-1:0] VAR18;
wire [VAR19-1:0]... | gpl-3.0 |
P3Stor/P3Stor | pcie/IP core/pcie_command_send_fifo.v | 13,660 | module MODULE1(
rst,
VAR167,
VAR313,
din,
VAR271,
VAR413,
dout,
VAR245,
VAR392,
VAR399,
VAR4,
VAR52,
VAR23
);
input rst;
input VAR167;
input VAR313;
input [127 : 0] din;
input VAR271;
input VAR413;
output [127 : 0] dout;
output VAR245;
output VAR392;
output VAR399;
output VAR4;
output [8 : 0] VAR52;
output [8 : 0] VAR2... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buflp/sky130_fd_sc_lp__buflp.functional.v | 1,244 | module MODULE1 (
VAR4,
VAR5
);
output VAR4;
input VAR5;
wire VAR2;
buf VAR1 (VAR2, VAR5 );
buf VAR3 (VAR4 , VAR2 );
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cpu/sprdma.v | 4,663 | module MODULE1
(
input wire VAR12, input wire VAR10, input wire [15:0] VAR3, input wire [ 7:0] VAR21, input wire [ 7:0] VAR8, input wire VAR11, output wire VAR13, output reg [15:0] VAR5, output reg [ 7:0] VAR15, output reg VAR1 );
localparam [1:0] VAR14 = 2'h0,
VAR20 = 2'h1,
VAR2 = 2'h2;
reg [ 1:0] VAR16, VAR7; reg [15... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22o/sky130_fd_sc_hd__a22o.functional.pp.v | 2,151 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR13 ,
VAR10 ,
VAR15 ,
VAR12,
VAR17,
VAR14 ,
VAR7
);
output VAR2 ;
input VAR1 ;
input VAR13 ;
input VAR10 ;
input VAR15 ;
input VAR12;
input VAR17;
input VAR14 ;
input VAR7 ;
wire VAR8 ;
wire VAR11 ;
wire VAR18 ;
wire VAR9;
and VAR4 (VAR8 , VAR10, VAR15 );
and VAR5 (VAR11 , VAR1, VAR13 )... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buflp/sky130_fd_sc_lp__buflp.pp.blackbox.v | 1,244 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR5,
VAR2,
VAR6 ,
VAR4
);
output VAR1 ;
input VAR3 ;
input VAR5;
input VAR2;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
forthy42/gforth | arch/misc/misc.v | 3,567 | module MODULE1(VAR5, VAR6, addr, VAR13, VAR11);
parameter VAR19=16, VAR15=10;
input VAR5;
inout VAR16 VAR6;
output VAR16 addr;
output VAR13;
output VAR11;
reg VAR16 VAR8, VAR22, VAR10, VAR1;
reg [0:1] state;
reg VAR21, VAR9;
wire VAR16 VAR18;
wire VAR12, VAR3, VAR4, VAR20;
wire VAR16 VAR2, VAR17, VAR14;
wire [0:2] VAR7... | gpl-3.0 |
everskar2013/PentiumX | Hardware/Code/clk_div.v | 1,033 | module MODULE1(
clk,
rst,
VAR2,
MODULE1,
VAR1
);
input wire clk,
rst;
input wire VAR2;
output reg [31: 0] MODULE1 = 0;
output wire VAR1;
always @ (posedge clk or posedge rst) begin
if (rst) begin
MODULE1 <= 0;
end
else begin
MODULE1 <= MODULE1 + 32'b1;
end
end
assign VAR1 = VAR2 ? MODULE1[24] : MODULE1[1];
endmodule | mit |
defano/digital-design | lsuc/rtl/gpio_ctrl.v | 6,151 | module MODULE1 (
clk,
reset,
VAR38,
VAR4,
VAR2,
VAR16,
VAR25,
VAR21,
addr,
VAR31,
req,
VAR24,
VAR30,
VAR8,
VAR14
);
input clk;
input reset;
output [7:0] VAR38; input [6:0] VAR4; input VAR2; input VAR16; input VAR25; input VAR21;
input [7:0] addr; input VAR31; input req; inout VAR24; input [7:0] VAR30; output [7:0] VAR8... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.behavioral.v | 3,306 | module MODULE1( VAR4, VAR3, VAR7, VAR8, VAR2, VAR5 );
input VAR2, VAR5, VAR7, VAR3, VAR8;
output VAR4;
VAR1 VAR9(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR8(VAR8),.VAR2(VAR2),.VAR5(VAR5));
VAR1 VAR6(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR8(VAR8),.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
Microsoft/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/pcie_dma_engine/egress_fifo_wrapper.v | 9,208 | module MODULE1(
input wire VAR18,
input wire VAR6,
input wire VAR3,
input wire [127:0] VAR12,
output wire VAR23,
output wire VAR45,
input wire VAR7,
input wire VAR20,
output reg [127:0] VAR4,
output wire VAR26,
output wire VAR50
);
localparam VAR30 = 2'b00;
localparam VAR46 = 2'b01;
localparam VAR10 = 2'b10;
localparam... | bsd-2-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/triple_speed_ethernet-library/altera_tse_xcvr_resync.v | 2,673 | module MODULE1 #(
parameter VAR13 = 2, parameter VAR3 = 1, parameter VAR6 = 0 ) (
input wire clk,
input wire [VAR3-1:0] VAR8,
output wire [VAR3-1:0] VAR2
);
localparam VAR7 = (VAR13 > 0) ? VAR13 : 1;
genvar VAR4;
generate begin
for(VAR4=0;VAR4<VAR3;VAR4=VAR4+1) begin : VAR9
wire din; reg [VAR7-1:0] VAR12 = {VAR7{1'b0}}... | mit |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pwm/niosii/synthesis/submodules/niosii_uart_0.v | 27,280 | module MODULE4 (
VAR21,
VAR69,
clk,
VAR37,
VAR12,
VAR14,
VAR44,
VAR33,
VAR72,
VAR15,
VAR45,
VAR89,
VAR26
)
;
output VAR15;
output VAR45;
output VAR89;
output VAR26;
input [ 15: 0] VAR21;
input VAR69;
input clk;
input VAR37;
input VAR12;
input VAR14;
input VAR44;
input [ 7: 0] VAR33;
input VAR72;
reg VAR57;
reg [ 15: 0]... | mit |
Willster419/ELEC3725_vivado_projects | assignment_2/assignment_2.srcs/sources_1/new/alupipe.v | 5,803 | module MODULE6(VAR7, VAR23, VAR24, clk, VAR13, VAR2);
input [31:0] VAR23;
input [31:0] VAR24;
input clk;
input [2:0] VAR7;
input VAR13;
output [31:0] VAR2;
wire [31:0] VAR6; wire [31:0] VAR31; wire [31:0] VAR26;
MODULE3 VAR3(.VAR33(VAR6), .VAR28(VAR31), .VAR13(VAR13), .VAR9(VAR26), .VAR7(VAR7));
MODULE4 VAR15(.VAR29(VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_4.behavioral.v | 3,431 | module MODULE1( VAR9, VAR2, VAR6, VAR3, VAR8, VAR7 );
input VAR6, VAR9, VAR2, VAR7, VAR8;
output VAR3;
VAR4 VAR5(.VAR9(VAR9),.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3),.VAR8(VAR8),.VAR7(VAR7));
VAR4 VAR1(.VAR9(VAR9),.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3),.VAR8(VAR8),.VAR7(VAR7)); | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/mig.v | 7,449 | module MODULE1 (
inout [15:0] VAR39,
inout [1:0] VAR3,
inout [1:0] VAR27,
output [12:0] VAR9,
output [2:0] VAR7,
output VAR15,
output VAR5,
output VAR28,
output [0:0] VAR29,
output [0:0] VAR30,
output [0:0] VAR14,
output [0:0] VAR22,
output [1:0] VAR26,
output [0:0] VAR19,
input VAR1,
input [26:0] VAR38,
input [2:0] VA... | bsd-2-clause |
hcabrera-/lancetfish | RTL/router/rtl/routing_algorithm/dor_xy.v | 5,412 | module MODULE1 #(
parameter VAR23 = VAR9,
parameter VAR5 = 2,
parameter VAR30 = 2
)
(
input wire VAR12,
input wire [VAR18-1:0] VAR14,
input wire [VAR18-1:0] VAR24,
output reg [3:0] VAR31
);
wire VAR10;
wire VAR22;
assign VAR10 = (VAR14 > VAR5) ? 1'b1 : 1'b0;
assign VAR22 = (VAR14 == VAR5) ? 1'b1 : 1'b0;
wire VAR27;
wir... | gpl-3.0 |
SpinalHDL/VexRiscv | scripts/Murax/arty_a7/toplevel.v | 1,602 | module MODULE1(
input wire VAR36,
input wire VAR21,
input wire VAR41,
input wire VAR22,
input wire VAR24,
input wire VAR17, output reg VAR7,
input wire VAR33,
output wire VAR1,
input wire VAR28,
input wire VAR34,
input wire VAR35,
input wire VAR30,
input wire VAR26,
input wire VAR2,
input wire VAR6,
input wire VAR40,
o... | mit |
lsnow/mips32 | MIPS32r1.v | 9,052 | module MODULE1(
VAR125, VAR31,
rst, clk, VAR87, VAR106, VAR75
);
input rst;
input clk;
input VAR87;
input VAR106;
input [4:0] VAR75;
output VAR125;
output VAR31;
reg [31:0] VAR99;
reg [31:0] VAR10;
wire [31:0] VAR105, VAR61;
wire [31:0] VAR81;
wire [31:0] VAR59;
wire [31:0] VAR43;
wire [31:0] VAR29;
wire [4:0] VAR21, V... | gpl-2.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_arbiter_resp.v | 7,888 | module MODULE1 #
(
parameter VAR22 = "none",
parameter integer VAR31 = 4, parameter integer VAR17 = 2, parameter integer VAR26 = 0, parameter integer VAR12 = 1 )
(
input wire VAR25,
input wire VAR15,
input wire [VAR31-1:0] VAR14, output wire [VAR31-1:0] VAR2, output wire [VAR17-1:0] VAR20, output wire [VAR31-1:0] VAR21... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcon/sky130_fd_sc_hs__fahcon.functional.pp.v | 2,600 | module MODULE1 (
VAR5,
VAR2 ,
VAR12 ,
VAR4 ,
VAR11 ,
VAR24 ,
VAR3
);
output VAR5;
output VAR2 ;
input VAR12 ;
input VAR4 ;
input VAR11 ;
input VAR24 ;
input VAR3 ;
wire VAR10 ;
wire VAR8 ;
wire VAR17 ;
wire VAR23 ;
wire VAR22 ;
wire VAR19 ;
wire VAR6;
xor VAR14 (VAR10 , VAR12, VAR4, VAR11 );
VAR20 VAR9 (VAR8 , VAR10, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlclkp/sky130_fd_sc_ms__dlclkp.behavioral.pp.v | 1,924 | module MODULE1 (
VAR10,
VAR4,
VAR9 ,
VAR6,
VAR3,
VAR1 ,
VAR12
);
output VAR10;
input VAR4;
input VAR9 ;
input VAR6;
input VAR3;
input VAR1 ;
input VAR12 ;
wire VAR2 ;
wire VAR7 ;
wire VAR13 ;
wire VAR5;
reg VAR17 ;
wire VAR11 ;
not VAR14 (VAR7 , VAR13 );
VAR15 VAR8 (VAR2 , VAR5, VAR7, VAR17, VAR6, VAR3);
and VAR16 (VAR... | apache-2.0 |
azonenberg/antikernel-ipcores | dataflow/UnorderedSet.v | 6,897 | module MODULE1 #(
parameter VAR7 = 16, parameter VAR13 = 4,
parameter VAR5 = 16 ) (
input wire clk,
input wire VAR11, input wire[VAR5-1:0] VAR2, output reg VAR1 = 0,
input wire VAR16, input wire VAR10, input wire[VAR13-1:0] VAR15, output reg VAR14 = 0, output reg[VAR13-1:0] VAR17 = 0, output reg[VAR5-1:0] VAR12 = 0,
in... | bsd-3-clause |
asicguy/gplgpu | hdl/math/flt_fx_mult.v | 4,673 | module MODULE1
(
input clk,
input VAR28,
input [23:0] VAR7,
input [31:0] VAR14,
output reg [31:0] VAR19
);
reg VAR21; reg [23:0] VAR30;
reg [4:0] VAR40; reg [47:0] VAR24; reg [47:0] VAR31; reg VAR8;
reg VAR4;
reg [7:0] VAR25; reg [7:0] VAR32; reg VAR11; reg VAR1;
reg VAR3;
always @* begin
if(VAR7[23]) begin
VAR21 = 1;
... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_2.behavioral.pp.v | 1,254 | module MODULE1( VAR5, VAR6, VAR2, VAR7, VAR1 );
input VAR2, VAR5;
inout VAR7, VAR1;
output VAR6;
VAR3 VAR8(.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1));
VAR3 VAR4(.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/conb/sky130_fd_sc_ms__conb.symbol.v | 1,270 | module MODULE1 (
output VAR1,
output VAR3
);
supply1 VAR5;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
cybero/Verilog | src/PicoBlaze (kcpsm6)/Utilities/KCPSM6_Release9_30Sept14/UART_and_PicoTerm/ATLYS_design/uart6_atlys.v | 14,495 | module MODULE1 (
input VAR61,
output VAR54,
output [7:0] VAR13,
input [7:0] VAR50,
input VAR40,
input clk );
wire [11:0] address;
wire [17:0] VAR39;
wire VAR2;
reg [7:0] VAR9;
wire [7:0] VAR33;
wire [7:0] VAR30;
wire VAR22;
wire VAR44;
wire VAR26;
reg interrupt;
wire VAR1;
wire VAR23;
wire VAR49;
wire VAR24;
wire [7:0]... | mit |
jacgoudsmit/P8X32A_Emulation | P8X32A_Nexys4/src/hub.v | 7,358 | module MODULE1
(
input VAR43,
input VAR15,
input VAR2,
input [7:0] VAR26,
input VAR45,
input VAR39,
input VAR6,
input [1:0] VAR37,
input [15:0] VAR4,
input [31:0] VAR47,
output reg [31:0] VAR40,
output VAR16,
output [7:0] VAR44,
output reg [7:0] VAR24,
output [7:0] VAR50,
output [27:0] VAR22,
output reg [7:0] VAR41
);
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlclkp/sky130_fd_sc_hvl__dlclkp_1.v | 2,162 | module MODULE2 (
VAR8,
VAR6,
VAR2 ,
VAR3,
VAR7,
VAR5 ,
VAR1
);
output VAR8;
input VAR6;
input VAR2 ;
input VAR3;
input VAR7;
input VAR5 ;
input VAR1 ;
VAR4 VAR9 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR8,
VAR6,
VAR2
);
output VAR8;
inpu... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2.behavioral.v | 3,781 | module MODULE1( VAR12, VAR24, VAR8, VAR31 );
input VAR12, VAR24, VAR8;
output VAR31;
reg VAR2;
VAR7 VAR27(.VAR12(VAR12),.VAR24(VAR24),.VAR8(VAR8),.VAR31(VAR31),.VAR2(VAR2));
VAR7 VAR9(.VAR12(VAR12),.VAR24(VAR24),.VAR8(VAR8),.VAR31(VAR31),.VAR2(VAR2));
not VAR28(VAR32,VAR24);
and VAR1(VAR30,VAR8,VAR32);
and VAR22(VAR20,... | apache-2.0 |
takeshineshiro/fpga_linear_128 | mult8x8.v | 4,466 | module MODULE1 (
VAR1,
VAR14,
VAR8);
input [7:0] VAR1;
input [7:0] VAR14;
output [15:0] VAR8;
wire [15:0] VAR3;
wire [15:0] VAR8 = VAR3[15:0];
VAR7 VAR17 (
.VAR1 (VAR1),
.VAR14 (VAR14),
.VAR8 (VAR3),
.VAR2 (1'b0),
.VAR4 (1'b1),
.VAR16 (1'b0),
.sum (1'b0));
VAR17.VAR11 = "VAR10=5",
VAR17.VAR9 = "VAR5",
VAR17.VAR6 = "VA... | mit |
svofski/mahponk | src/scorecopymux_bb.v | 3,183 | module MODULE1 (
VAR4,
VAR1,
VAR5,
VAR2,
sel,
VAR3);
input [3:0] VAR4;
input [3:0] VAR1;
input [3:0] VAR5;
input [3:0] VAR2;
input [1:0] sel;
output [3:0] VAR3;
endmodule | bsd-2-clause |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Computer_System/synthesis/submodules/Top.v | 87,897 | module MODULE1(
input VAR4,
input reset,
input VAR24,
input VAR12,
input VAR22,
input VAR15,
input VAR10,
input [31:0] VAR1,
input [31:0] VAR18,
input VAR7,
output VAR14,
output VAR11,
output VAR8,
output VAR21,
output [31:0] VAR20
);
reg VAR23;
reg [31:0] VAR6;
wire VAR13;
wire VAR16;
wire VAR27;
reg VAR17;
reg [31:0]... | mit |
bigeagle/riffa | fpga/riffa_hdl/rxc_engine_ultrascale.v | 19,259 | module MODULE1
parameter VAR109 = 128,
parameter VAR95=10,
parameter VAR99 = 0,
parameter VAR121 = 1
)
(
input VAR108,
input VAR122,
input VAR92,
input VAR8,
input [VAR109-1:0] VAR27,
input [(VAR109/32)-1:0] VAR84,
input [VAR15-1:0] VAR65,
output VAR100,
output [VAR109-1:0] VAR3,
output VAR98,
output [(VAR109/32)-1:0] ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtn/sky130_fd_sc_ms__sdfrtn.symbol.v | 1,508 | module MODULE1 (
input VAR9 ,
output VAR1 ,
input VAR4,
input VAR2 ,
input VAR7 ,
input VAR5
);
supply1 VAR8;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfstp/sky130_fd_sc_hd__dfstp_1.v | 2,273 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR3 ,
VAR9,
VAR8 ,
VAR7 ,
VAR2 ,
VAR5
);
output VAR1 ;
input VAR4 ;
input VAR3 ;
input VAR9;
input VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR5 ;
VAR6 VAR10 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE1... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_clsp_clkgn_nstep.v | 5,982 | module MODULE1(
VAR15, VAR26, VAR10,
VAR29, VAR1, VAR24,
VAR12, VAR18,
VAR2, VAR7,
VAR3, VAR16, VAR8, VAR23,
VAR27, VAR13, VAR14, VAR25,
VAR5, VAR19, VAR6, VAR9
);
input VAR29;
input VAR1;
input VAR24;
input VAR12;
input VAR18;
input VAR2;
input VAR7;
input [3:0] VAR3;
input [2:0] VAR16;
input VAR8;
input VAR23;
input ... | gpl-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_regfile.v | 5,002 | module MODULE1(
input [VAR1-1:0] VAR12,
input [VAR1-1:0] VAR15,
output [VAR7-1:0] VAR11,
output [VAR7-1:0] VAR23,
input VAR26,
input [VAR1-1:0] VAR9,
input [VAR7-1:0] VAR14,
output [VAR7-1:0] VAR8,
input VAR21,
input clk,
input VAR2
);
wire [VAR7-1:0] VAR18 [VAR22-1:0];
wire [VAR22-1:0] VAR5;
VAR24 #(VAR7) VAR3 (VAR26,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtn/sky130_fd_sc_ls__sdfrtn.pp.symbol.v | 1,513 | module MODULE1 (
input VAR10 ,
output VAR7 ,
input VAR2,
input VAR5 ,
input VAR6 ,
input VAR8 ,
input VAR3 ,
input VAR1 ,
input VAR9 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probe_p/sky130_fd_sc_hvl__probe_p.symbol.v | 1,281 | module MODULE1 (
input VAR1,
output VAR4
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcon/sky130_fd_sc_ms__fahcon.symbol.v | 1,358 | module MODULE1 (
input VAR8 ,
input VAR3 ,
input VAR2 ,
output VAR6,
output VAR7
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/inv/sky130_fd_sc_hd__inv.behavioral.v | 1,321 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR6;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR5 ;
wire VAR7;
not VAR8 (VAR7, VAR2 );
buf VAR9 (VAR4 , VAR7 );
endmodule | apache-2.0 |
fbalakirev/red-pitaya-notes | cores/axis_gate_controller_v1_0/axis_gate_controller.v | 2,190 | module MODULE1
(
input wire VAR17,
input wire VAR10,
output wire VAR16,
input wire [127:0] VAR13,
input wire VAR8,
output wire [31:0] VAR18,
output wire sync,
output wire dout
);
reg VAR15, VAR7;
reg VAR2, VAR14;
reg VAR12, VAR4;
reg VAR11, VAR9;
reg [31:0] VAR3, VAR6;
reg [127:0] VAR5, VAR1;
always @(posedge VAR17)
be... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111ai/sky130_fd_sc_lp__o2111ai.functional.pp.v | 2,086 | module MODULE1 (
VAR10 ,
VAR14 ,
VAR18 ,
VAR11 ,
VAR12 ,
VAR7 ,
VAR9,
VAR1,
VAR17 ,
VAR3
);
output VAR10 ;
input VAR14 ;
input VAR18 ;
input VAR11 ;
input VAR12 ;
input VAR7 ;
input VAR9;
input VAR1;
input VAR17 ;
input VAR3 ;
wire VAR13 ;
wire VAR15 ;
wire VAR16;
or VAR2 (VAR13 , VAR18, VAR14 );
nand VAR6 (VAR15 , VAR... | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Timer_Counter/clk_generator.v | 1,132 | module MODULE1(
input clk,
input en,
input rst,
input [31:0] VAR6,
input [31:0] VAR3,
output reg VAR5,
output reg VAR4
);
reg [31:0] VAR1;
VAR2 VAR5 = 1'b0;
VAR2 VAR1 = 32'h00000000;
always@(negedge clk) begin
if(en) begin
if(VAR3 > VAR1) begin VAR1 <= VAR3 + VAR6; VAR5 <= ~VAR5; end
else begin
VAR1 <= VAR1; VAR5 <= VA... | mit |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/pixelq_op_Block_proc.v | 4,012 | module MODULE1 (
VAR5,
VAR19,
VAR7,
VAR11,
VAR18,
VAR3,
VAR15,
VAR4,
VAR12,
VAR27,
VAR21
);
parameter VAR6 = 1'b1;
parameter VAR1 = 1'b0;
parameter VAR13 = 1'b1;
parameter VAR24 = 32'b00000000000000000000000000000000;
parameter VAR22 = 1'b1;
parameter VAR10 = 12'b10000111000;
parameter VAR9 = 12'b11110000000;
parameter... | gpl-2.0 |
MIPSfpga/schoolMIPS | src/sm_cpu.v | 5,245 | module MODULE3
(
input clk, input VAR14, input [ 4:0] VAR23, output [31:0] VAR37, output [31:0] VAR33, input [31:0] VAR39 );
wire VAR5;
wire VAR30;
wire VAR4;
wire VAR27;
wire VAR1;
wire [ 2:0] VAR34;
wire [31:0] VAR11;
wire [31:0] VAR16;
wire [31:0] VAR13 = VAR11 + 1;
wire [31:0] VAR31 = ~VAR5 ? VAR13 : VAR16;
VAR28 V... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_mul_u16.v | 9,220 | module MODULE1 (
clk,
VAR32,
VAR36,
VAR19,
VAR13,
VAR5);
parameter VAR3 = 16;
parameter VAR30 = VAR3 - 1;
input clk;
input [15:0] VAR32;
input [15:0] VAR36;
output [31:0] VAR19;
input [VAR30:0] VAR13;
output [VAR30:0] VAR5;
reg [VAR30:0] VAR2 = 'd0;
reg [31:0] VAR15 = 'd0;
reg [31:0] VAR29 = 'd0;
reg [31:0] VAR26 = 'd0... | mit |
ngoel9/progressive-learning-platform | reference/hw/verilog/cpu_ex.v | 4,806 | module MODULE1(rst, clk, VAR24, VAR40, VAR7, VAR15,
VAR4, VAR9, VAR16, VAR14, VAR13,
VAR2, VAR35, VAR50, VAR17, VAR32,
VAR22, VAR39, VAR29, VAR8, VAR48,
VAR45, VAR18, VAR47, VAR6, VAR21,
VAR46, VAR44, VAR5, VAR42, VAR27,
VAR37, VAR12, VAR43, VAR23, VAR28, VAR1, VAR41);
input rst, clk, VAR24;
input VAR40;
input [1:0] VA... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_mem/bsg_mem_1r1w.v | 6,201 | if (VAR10 == VAR21 && VAR24 == VAR20) \
begin: VAR4 \
wire [VAR10-1:0] VAR25 = (VAR1 << VAR12); \
wire [VAR10-1:0] VAR13 = (VAR7 << VAR29); \
\
VAR31 VAR19 \
( .VAR9(VAR16) \
,.VAR15(VAR17) \
,.VAR26(VAR25) \
,.VAR28 (VAR13) \
,.VAR30(VAR23) \
); \
end
module MODULE1 #(parameter VAR14(VAR24)
, parameter VAR14(VAR10)
, ... | bsd-3-clause |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/clocking/mig_7series_v2_0_iodelay_ctrl.v | 9,682 | module MODULE1 #
(
parameter VAR6 = 100,
parameter VAR18 = "VAR37",
parameter VAR31 = "VAR11",
parameter VAR5 = "VAR11",
parameter VAR30 = "VAR42",
parameter VAR44 = 1,
parameter VAR36 = "VAR35"
)
(
input VAR7,
input VAR1,
input VAR33,
input VAR43,
output VAR22,
output VAR25,
output VAR45
);
localparam VAR12 = 15;
wire... | bsd-2-clause |
jhoward321/pacman | usb_system/synthesis/submodules/usb_system_jtag_uart.v | 16,904 | module MODULE5 (
clk,
VAR35,
VAR47,
VAR33,
VAR20,
VAR36,
VAR52
)
;
output VAR33;
output [ 7: 0] VAR20;
output VAR36;
output [ 5: 0] VAR52;
input clk;
input [ 7: 0] VAR35;
input VAR47;
wire VAR33;
wire [ 7: 0] VAR20;
wire VAR36;
wire [ 5: 0] VAR52;
always @(posedge clk)
begin
if (VAR47)
("%VAR27", VAR35);
end
assign VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2a/sky130_fd_sc_hd__o2bb2a.blackbox.v | 1,389 | module MODULE1 (
VAR1 ,
VAR7,
VAR3,
VAR6 ,
VAR5
);
output VAR1 ;
input VAR7;
input VAR3;
input VAR6 ;
input VAR5 ;
supply1 VAR4;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
kDaniu/miaow | src/verilog/rtl/sgpr/reg_512x32b_3r_3w.v | 14,391 | module MODULE1 (
VAR49, VAR40, VAR62,
clk,
VAR10, VAR61, VAR52,
VAR59, VAR60, VAR32,
VAR55, VAR35, VAR37, VAR30, VAR4, VAR27
);
input clk;
output [127:0] VAR49;
output [63:0] VAR40;
output [63:0] VAR62;
input [8:0] VAR10;
input [8:0] VAR61;
input [8:0] VAR52;
input [8:0] VAR59;
input [8:0] VAR60;
input [8:0] VAR32;
inp... | bsd-3-clause |
ptracton/Picoblaze | Picoblaze/UART_and_PicoTerm/KC705_design/uart6_kc705.v | 15,644 | module MODULE1 ( input VAR13,
output VAR11,
input VAR66,
input VAR14);
wire VAR5;
wire clk;
wire [7:0] VAR44;
wire [11:0] address;
wire [17:0] VAR57;
wire VAR40;
reg [7:0] VAR23;
wire [7:0] VAR12;
wire [7:0] VAR61;
wire VAR64;
wire VAR32;
wire VAR15;
wire interrupt;
wire VAR51;
wire VAR65;
wire VAR17;
wire VAR34;
wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill/sky130_fd_sc_ms__fill.behavioral.v | 1,110 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/xgmii_baser_enc_64.v | 9,633 | module MODULE1 #
(
parameter VAR4 = 64,
parameter VAR6 = (VAR4/8),
parameter VAR7 = 2
)
(
input wire clk,
input wire rst,
input wire [VAR4-1:0] VAR1,
input wire [VAR6-1:0] VAR2,
output wire [VAR4-1:0] VAR3,
output wire [VAR7-1:0] VAR5
); | mit |
jhennessy/parallella-hw-old | fpga/projects/parallella_7020_headless/parallella_7020_headless.srcs/sources_1/imports/parallella_7020_headless/system_stub.v | 20,312 | module MODULE1
(
VAR89,
VAR3,
VAR6,
VAR79,
VAR63,
VAR69,
VAR77,
VAR48,
VAR44,
VAR29,
VAR35,
VAR60,
VAR37,
VAR80,
VAR32,
VAR7,
VAR40,
VAR18,
VAR72,
VAR24,
VAR53,
VAR71,
VAR102,
VAR83,
VAR66,
VAR91,
VAR58,
VAR51,
VAR95,
VAR93,
VAR34,
VAR99,
VAR27,
VAR98,
VAR31,
VAR2,
VAR103,
VAR4,
VAR67,
VAR84,
VAR97,
VAR104,
VAR22,
VAR2... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpu/integracion_fisica/front_end/source/KOA_1c.v | 5,700 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR17,
input wire [VAR35-1:0] VAR7,
input wire [VAR35-1:0] VAR8,
output wire [2*VAR35-1:0] VAR2
);
wire [1:0] VAR13;
wire [3:0] VAR11;
assign VAR13 = 2'b00;
assign VAR11 = 4'b0000;
wire [VAR35/2-1:0] VAR29;
wire [VAR35/2:0] VAR36;
wire [VAR35/2-3:0] VAR24;
wir... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/1_unroll_kernel_traversal/syn/verilog/convolve_kernel_adEe.v | 1,305 | module MODULE1(
input [5 - 1:0] VAR2,
input [2 - 1:0] VAR5,
input [6 - 1:0] VAR13,
output [9 - 1:0] dout);
wire signed [18 - 1:0] VAR11;
wire signed [25 - 1:0] VAR6;
wire signed [25 - 1:0] VAR14;
wire signed [43 - 1:0] VAR1;
wire signed [25 - 1:0] VAR9;
assign VAR6 = (VAR2);
assign VAR14 = (VAR5);
assign VAR11 = (VAR13... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvp/sky130_fd_sc_ms__einvp.functional.v | 1,206 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3
);
output VAR2 ;
input VAR1 ;
input VAR3;
notif1 VAR4 (VAR2 , VAR1, VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd.blackbox.v | 1,219 | module MODULE1 ();
supply1 VAR2;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/16-way_2-parallel/ise/ipcore_dir/dram/user_design/rtl/controller/mig_7series_v1_9_rank_cntrl.v | 22,688 | module MODULE1 #
(
parameter VAR88 = 100, parameter VAR46 = "8", parameter VAR63 = 2, parameter VAR87 = 5, parameter VAR34 = 5, parameter VAR85 = 0, parameter VAR69 = 4, parameter VAR81 = 2, parameter VAR35 = 30, parameter VAR97 = 8, parameter VAR43 = 4, parameter VAR89 = 4, parameter VAR12 = 20, parameter VAR91 = 16, ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr_2.v | 2,265 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR6,
VAR1 ,
VAR3 ,
VAR8 ,
VAR5
);
output VAR7 ;
input VAR9 ;
input VAR6;
input VAR1 ;
input VAR3 ;
input VAR8 ;
input VAR5 ;
VAR4 VAR2 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR7,
VAR9
);
output VAR7;
inpu... | apache-2.0 |
LSaldyt/qnp | output/vs/opt_var20_multi.v | 34,560 | module MODULE1(VAR7, VAR4, VAR10, VAR6, VAR13, VAR14, VAR2, VAR18, VAR8, VAR5, VAR12, VAR17, VAR15, VAR20, VAR11, VAR9, VAR16, VAR3, VAR19, VAR1, valid);
wire 0000;
wire 0001;
wire 0002;
wire 0003;
wire 0004;
wire 0005;
wire 0006;
wire 0007;
wire 0008;
wire 0009;
wire 0010;
wire 0011;
wire 0012;
wire 0013;
wire 0014;
w... | mit |
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