repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
sirchuckalot/zet | cores/vga/rtl/vga_mem_arbitrer.v | 1,992 | module MODULE1 (
input VAR8,
input VAR14,
input [17:1] VAR20,
input [ 1:0] VAR7,
input VAR5,
input [15:0] VAR2,
output [15:0] VAR19,
input VAR17,
output VAR4,
input [17:1] VAR10,
output [15:0] VAR13,
input VAR11,
output [17:1] VAR1,
output [ 1:0] VAR12,
output VAR18,
output [15:0] VAR3,
input [15:0] VAR16
);
reg [1:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211a/sky130_fd_sc_ls__o211a_1.v | 2,348 | module MODULE2 (
VAR1 ,
VAR7 ,
VAR9 ,
VAR8 ,
VAR4 ,
VAR5,
VAR11,
VAR2 ,
VAR3
);
output VAR1 ;
input VAR7 ;
input VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR5;
input VAR11;
input VAR2 ;
input VAR3 ;
VAR6 VAR10 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR... | apache-2.0 |
hanw/connectal | contrib/parallella/parallella.v | 35,890 | module MODULE1 (
VAR222, VAR175, VAR234, VAR25, VAR137, VAR46,
VAR187, VAR194, VAR27, VAR213, VAR152,
VAR144, VAR134, VAR178, VAR36,
VAR165, VAR107, VAR168, VAR127, VAR31,
VAR189, VAR12, VAR190, VAR9,
VAR95, VAR48, VAR209, VAR81, VAR233,
VAR167, VAR76, VAR69, VAR7, VAR52,
VAR80, VAR71, VAR157, VAR200, VAR79,
VAR192, VA... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/bd_0/hdl/bd_350b.v | 20,005 | module MODULE1
(VAR87,
VAR5,
VAR14,
VAR23,
VAR204,
VAR154,
VAR201,
VAR153,
VAR371,
VAR174,
VAR144,
VAR52,
VAR170,
VAR274,
VAR21,
VAR184,
VAR186,
VAR30,
VAR336,
VAR364,
VAR221,
VAR347,
VAR107,
VAR257,
VAR172,
VAR134,
VAR136,
VAR351,
VAR143,
VAR291,
VAR196,
VAR233,
VAR220,
VAR222,
VAR206,
VAR55,
VAR43,
VAR126,
VAR76,
VAR... | mit |
VCTLabs/DE1_SOC_Linux_FB | ip/TERASIC_IRM/TERASIC_IRM.v | 1,175 | module MODULE1(
clk, VAR8,
irq,
VAR11,
VAR4,
VAR9,
VAR7,
VAR16,
VAR10
);
input clk;
input VAR8;
output reg irq;
input VAR11;
input VAR4;
output [31:0] VAR9;
input VAR7;
input [31:0] VAR16;
input VAR10;
wire VAR6;
reg VAR5;
always @ (posedge clk or negedge VAR8)
begin
if (~VAR8)
VAR5 <= 1'b0;
end
else
VAR5 <= VAR6;
end
... | epl-1.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_src0_cols_V.v | 2,983 | module MODULE1 (
clk,
VAR20,
VAR15,
VAR24,
VAR27);
parameter VAR13 = 32'd12;
parameter VAR6 = 32'd2;
parameter VAR18 = 32'd3;
input clk;
input [VAR13-1:0] VAR20;
input VAR15;
input [VAR6-1:0] VAR24;
output [VAR13-1:0] VAR27;
reg[VAR13-1:0] VAR9 [0:VAR18-1];
integer VAR19;
always @ (posedge clk)
begin
if (VAR15)
begin
f... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/hpdmc_ddr32/rtl/spartan6/hpdmc_iobuf32.v | 3,149 | module MODULE1(
input [31:0] VAR34,
input [31:0] VAR9,
output [31:0] VAR27,
inout [31:0] VAR15
);
VAR18 VAR26(
.VAR34(VAR34[0]),
.VAR9(VAR9[0]),
.VAR27(VAR27[0]),
.VAR15(VAR15[0])
);
VAR18 VAR24(
.VAR34(VAR34[1]),
.VAR9(VAR9[1]),
.VAR27(VAR27[1]),
.VAR15(VAR15[1])
);
VAR18 VAR17(
.VAR34(VAR34[2]),
.VAR9(VAR9[2]),
.VAR2... | lgpl-3.0 |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ip/image_processing_2d_design_image_capture_manager_0_0/synth/image_processing_2d_design_image_capture_manager_0_0.v | 6,877 | module MODULE1 (
VAR5,
VAR13,
reset,
VAR25,
VAR21,
VAR14,
VAR29,
VAR24,
VAR11,
VAR27,
VAR26,
VAR17,
VAR23,
VAR6,
VAR16,
VAR20,
VAR30,
VAR8,
VAR22,
VAR9,
VAR18,
VAR19,
VAR7,
VAR10
);
output wire VAR5;
output wire VAR13;
output wire reset;
input wire VAR25;
input wire VAR21;
input wire [3 : 0] VAR14;
input wire [2 : 0] V... | gpl-2.0 |
alan4186/ParCNN | Hardware/v/FFN/np_matrix_mult.v | 2,480 | module MODULE1(
input VAR16,
input reset,
input [VAR6:0] VAR7,
input [VAR6:0] VAR4,
input [VAR17:0] VAR18,
input en,
output [VAR17:0] VAR3
);
wire [VAR17:0] VAR2;
wire [VAR6:0] VAR8;
wire [VAR6:0] VAR12;
wire [VAR17:0] VAR13;
wire [VAR17:0] VAR19;
reg [VAR17:0] sum;
assign VAR8 = en ? VAR7 : VAR10'd0;
assign VAR12 = en... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3/sky130_fd_sc_hs__nor3.functional.v | 1,733 | module MODULE1 (
VAR7,
VAR12,
VAR10 ,
VAR8 ,
VAR11 ,
VAR5
);
input VAR7;
input VAR12;
output VAR10 ;
input VAR8 ;
input VAR11 ;
input VAR5 ;
wire VAR9 ;
wire VAR4;
nor VAR2 (VAR9 , VAR5, VAR8, VAR11 );
VAR3 VAR1 (VAR4, VAR9, VAR7, VAR12);
buf VAR6 (VAR10 , VAR4 );
endmodule | apache-2.0 |
nyaxt/dmix | spi_trx.v | 2,226 | module MODULE1 (
input wire clk,
input wire VAR12,
output wire VAR3,
input wire VAR13,
input wire VAR15,
output wire VAR17,
output wire [7:0] VAR8,
output wire VAR5,
input wire [7:0] VAR7,
input wire VAR19);
reg [1:0] VAR4;
always @(posedge clk) begin
VAR4 <= {VAR4[0], VAR12};
end
reg [1:0] VAR1;
always @(posedge clk) ... | mit |
zhaishaomin/ring_network-based-multicore- | communication_assist/m_d_areg.v | 1,283 | module MODULE1( clk,
rst,
VAR5,
VAR2,
VAR4,
VAR6,
VAR3,
VAR8
);
input clk;
input rst;
input [143:0] VAR5;
input VAR2;
input VAR4;
output [143:0] VAR6;
output VAR3;
output VAR8;
reg VAR7;
reg [143:0] VAR1;
assign VAR3=VAR7;
assign VAR8=VAR7; always@(posedge clk)
begin
if(rst||VAR4)
VAR1<=144'h0000;
end
else if(VAR2)
VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/diode/sky130_fd_sc_hd__diode.pp.blackbox.v | 1,226 | module MODULE1 (
VAR1,
VAR4 ,
VAR2 ,
VAR3 ,
VAR5
);
input VAR1;
input VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
meteorcloudy/CPU_verilog | regfile.v | 1,209 | module MODULE1(VAR6,VAR8,VAR4,VAR9,VAR1,clk,VAR3,VAR7,VAR2
);
input [4:0] VAR6,VAR8,VAR9;
input [31:0] VAR4;
input VAR1,clk,VAR3;
output [31:0] VAR7,VAR2;
integer VAR5;
reg [31:0] register [1:31]; assign VAR7=((VAR6==0)?0:register[VAR6]);
assign VAR2=((VAR8==0)?0:register[VAR8]);
always @(negedge clk or negedge VAR3)
i... | mit |
stevenokm/mor1kx | rtl/verilog/mor1kx_rf_cappuccino.v | 11,262 | module MODULE1
parameter VAR23 = "VAR70",
parameter VAR14 = 0,
parameter VAR56 = 0,
parameter VAR5 = 5,
parameter VAR26 = 32,
parameter VAR27 = "VAR70",
parameter VAR40 = 32
)
(
input clk,
input rst,
input VAR85,
input VAR64,
input VAR88,
input VAR52,
input VAR37,
input [VAR5-1:0] VAR79,
input [VAR5-1:0] VAR42,
input [... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvn/sky130_fd_sc_hvl__einvn_1.v | 2,158 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR1,
VAR4,
VAR5,
VAR9 ,
VAR6
);
output VAR2 ;
input VAR8 ;
input VAR1;
input VAR4;
input VAR5;
input VAR9 ;
input VAR6 ;
VAR3 VAR7 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR2 ,
VAR8 ,
VAR1
);
output VAR2 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd.behavioral.pp.v | 1,200 | module MODULE1 (
VAR2,
VAR1,
VAR3 ,
VAR4
);
input VAR2;
input VAR1;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/hls_gamma_correction_AXILiteS_s_axi.v | 6,860 | module MODULE1
VAR19 = 6,
VAR8 = 32
)(
input wire VAR20,
input wire VAR2,
input wire VAR50,
input wire [VAR19-1:0] VAR4,
input wire VAR21,
output wire VAR27,
input wire [VAR8-1:0] VAR29,
input wire [VAR8/8-1:0] VAR51,
input wire VAR13,
output wire VAR24,
output wire [1:0] VAR52,
output wire VAR44,
input wire VAR5,
inpu... | mit |
Sajid3/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_aes/rtl/verilog/crypto_aes_top.v | 2,447 | module MODULE1 (
input VAR20,
input VAR32,
input VAR4,
input [31:0] VAR24,
input [31:0] VAR14,
input [3:0] VAR12,
input VAR13,
input [1:0] VAR27,
input [2:0] VAR35,
input VAR18,
input VAR26,
output VAR31,
output VAR23,
output VAR15,
output [31:0] VAR1
);
wire [255:0] VAR25;
wire VAR30;
wire [1:0] VAR21;
wire [127:0] VA... | apache-2.0 |
drichmond/riffa | fpga/xilinx/ac701/AC701_Gen1x4If64/hdl/AC701_Gen1x4If64.v | 20,969 | module MODULE1
parameter VAR65 = 4,
parameter VAR64 = 64,
parameter VAR57 = 256,
parameter VAR113 = 5
)
(output [(VAR65 - 1) : 0] VAR73,
output [(VAR65 - 1) : 0] VAR81,
input [(VAR65 - 1) : 0] VAR72,
input [(VAR65 - 1) : 0] VAR27,
output [3:0] VAR36,
input VAR84,
input VAR99,
input VAR88
);
wire VAR146;
wire VAR118;
wi... | bsd-3-clause |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_fpu_fcmp.v | 6,609 | module MODULE1(VAR9, VAR31, VAR29, VAR23, VAR27, VAR6, VAR17, VAR14);
input [31:0] VAR9, VAR31;
output VAR29;
output VAR23, VAR27, VAR6;
output VAR17, VAR14;
reg VAR23, VAR27, VAR6;
wire VAR32, VAR11;
wire [7:0] VAR7, VAR18;
wire [22:0] VAR33, VAR12;
wire VAR4, VAR15, VAR21, VAR10;
wire VAR3, VAR16, VAR20, VAR13, VAR5,... | mit |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/riffa/tx_data_fifo.v | 13,994 | parameter VAR85 = 128,
parameter VAR70 = 1,
parameter VAR29 = 256)
( input VAR49,
input VAR56,
input [VAR85-1:0] VAR81,
input VAR41,
input VAR30,
input [(VAR85/32)-1:0] VAR86,
input [(VAR85/32)-1:0] VAR50,
output VAR76,
input [(VAR85/32)-1:0] VAR39,
output [VAR85-1:0] VAR14,
output VAR66,
output [(VAR85/32)-1:0] VAR51,... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_4.behavioral.v | 8,258 | module MODULE1( VAR10, VAR4, VAR7, VAR5, VAR1, VAR8, VAR3 );
input VAR3, VAR8, VAR10, VAR7, VAR4, VAR1;
output VAR5;
VAR2 VAR9(.VAR10(VAR10),.VAR4(VAR4),.VAR7(VAR7),.VAR5(VAR5),.VAR1(VAR1),.VAR8(VAR8),.VAR3(VAR3));
VAR2 VAR6(.VAR10(VAR10),.VAR4(VAR4),.VAR7(VAR7),.VAR5(VAR5),.VAR1(VAR1),.VAR8(VAR8),.VAR3(VAR3)); | apache-2.0 |
xcthulhu/periphondemand | src/library/components/uart16550/hdl/uart_tfifo.v | 9,034 | module MODULE1 (clk,
VAR8, VAR3, VAR12,
VAR22, VAR10, VAR16,
VAR5,
VAR15,
VAR14
);
parameter VAR27 = VAR6;
parameter VAR4 = VAR26;
parameter VAR18 = VAR7;
parameter VAR23 = VAR20;
input clk;
input VAR8;
input VAR22;
input VAR10;
input [VAR27-1:0] VAR3;
input VAR15;
input VAR14;
output [VAR27-1:0] VAR12;
output VAR16;
o... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2i/sky130_fd_sc_hd__mux2i_1.v | 2,214 | module MODULE2 (
VAR2 ,
VAR6 ,
VAR4 ,
VAR3 ,
VAR1,
VAR10,
VAR9 ,
VAR8
);
output VAR2 ;
input VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR1;
input VAR10;
input VAR9 ;
input VAR8 ;
VAR7 VAR5 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
bluespec/Flute | builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkTop_HW_Side.v | 8,770 | module MODULE1(VAR11,
VAR4);
input VAR11;
input VAR4;
reg VAR6;
wire VAR50, VAR73;
wire [352 : 0] VAR43;
wire [255 : 0] VAR58;
wire VAR45,
VAR57,
VAR61,
VAR2;
wire [352 : 0] VAR44;
wire [255 : 0] VAR86;
wire [63 : 0] VAR48,
VAR79;
wire [7 : 0] VAR56,
VAR65,
VAR59;
wire [3 : 0] VAR1;
wire VAR15,
VAR27,
VAR80,
VAR72,
VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufinv/sky130_fd_sc_ms__bufinv.functional.pp.v | 1,782 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR8,
VAR11,
VAR4 ,
VAR2
);
output VAR7 ;
input VAR5 ;
input VAR8;
input VAR11;
input VAR4 ;
input VAR2 ;
wire VAR1 ;
wire VAR6;
not VAR3 (VAR1 , VAR5 );
VAR10 VAR12 (VAR6, VAR1, VAR8, VAR11);
buf VAR9 (VAR7 , VAR6 );
endmodule | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_xbar_0/synth/zc702_xbar_0.v | 13,292 | module MODULE1 (
VAR93,
VAR120,
VAR96,
VAR66,
VAR115,
VAR40,
VAR86,
VAR61,
VAR67,
VAR51,
VAR43,
VAR99,
VAR5,
VAR82,
VAR46,
VAR48,
VAR17,
VAR54,
VAR35,
VAR16,
VAR81,
VAR39,
VAR107,
VAR132,
VAR112,
VAR27,
VAR9,
VAR3,
VAR100,
VAR104,
VAR87,
VAR21,
VAR8,
VAR7,
VAR75,
VAR58,
VAR30,
VAR119,
VAR111,
VAR108
);
input wire VAR93... | mit |
JakeMercer/mac | station_management_mdo_mdi.v | 5,644 | module MODULE1
parameter VAR14 = 4'd0,
parameter VAR16 = 4'd1,
parameter VAR25 = 4'd2,
parameter VAR32 = 4'd3,
parameter VAR28 = 4'd4,
parameter VAR13 = 4'd5,
parameter VAR20 = 4'd6,
parameter VAR7 = 4'd7,
parameter VAR4 = 4'd8,
parameter VAR27 = 1'b0,
parameter VAR21 = 1'b1
)(
input wire reset,
input wire VAR8,
output... | mit |
MeshSr/onetswitch45 | ons45-app21-ref_switch/vivado/onets_7045_4x_ref_switch/ip/ref_switch_core/src/core/pipeline_switch.v | 22,311 | module MODULE1#(
parameter integer VAR137 = 32,
parameter integer VAR154 = 27,
parameter integer VAR72 = 32,
parameter integer VAR231 = 32,
parameter integer VAR112 = 32,
parameter integer VAR227 = 32,
parameter integer VAR4 = 32,
parameter integer VAR30 = 32,
parameter integer VAR205 = 32,
parameter integer VAR187 = 3... | lgpl-2.1 |
AngelTerrones/ADA | rtl/ada_exmem_stage.v | 5,187 | module MODULE1(
input clk, input rst, input [31:0] VAR13, input [31:0] VAR18, input VAR5, input VAR1, input VAR7, input VAR22, input VAR11, input VAR2, input [4:0] VAR21, input VAR15, input VAR26, input [31:0] VAR20, input VAR10, input VAR14, input VAR9, input VAR4, output reg [31:0] VAR24, output reg [31:0] VAR17, out... | mit |
dutra/vgacontroller | mkSocKit.v | 22,676 | module MODULE1(VAR63,
VAR48,
VAR20,
VAR103,
VAR23,
VAR26,
VAR109,
VAR58,
VAR62,
VAR112);
input VAR63;
input VAR48;
output [3 : 0] VAR20;
output [7 : 0] VAR103;
output [7 : 0] VAR23;
output [7 : 0] VAR26;
output VAR109;
output VAR58;
output VAR62;
output VAR112;
wire [7 : 0] VAR26, VAR23, VAR103;
wire [3 : 0] VAR20;
wir... | mit |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/CvtColor_1.v | 35,780 | module MODULE1 (
VAR100,
VAR115,
VAR110,
VAR6,
VAR122,
VAR96,
VAR157,
VAR139,
VAR198,
VAR76,
VAR200,
VAR75,
VAR21,
VAR48,
VAR187,
VAR101,
VAR57,
VAR172,
VAR199,
VAR61,
VAR30,
VAR130,
VAR155,
VAR9,
VAR15,
VAR184,
VAR178,
VAR20,
VAR181,
VAR138,
VAR58
);
parameter VAR158 = 4'd1;
parameter VAR190 = 4'd2;
parameter VAR14 = ... | mit |
DougFirErickson/parallella-hw | fpga/src/memory/hdl/fifo_async.v | 3,404 | module MODULE1
(
VAR7, VAR17, VAR15, VAR25,
reset, VAR19, VAR1, VAR2, VAR3, VAR9
);
parameter VAR12 = 104;
parameter VAR14 = 2;
input reset;
input VAR19; input VAR1;
input VAR2;
input [VAR12-1:0] VAR3;
input VAR9;
output [VAR12-1:0] VAR7;
output VAR17;
output VAR15;
output VAR25;
wire [VAR12/8-1:0] VAR20;
wire [VAR14:0... | gpl-3.0 |
donnaware/TabX1 | rtl/tabx1/pcm_dac.v | 3,479 | module MODULE2 (
input clk, input [15:0] VAR11, input [15:0] VAR10, input VAR3, input VAR14, output VAR6, output VAR8 );
always @(posedge VAR3) begin
VAR13 <= {~VAR11[15], VAR11[14:0]};
end
always @(posedge VAR14) begin
VAR4 <= {~VAR10[15], VAR10[14:0]};
end
wire VAR2 = VAR7[4];
reg [8:0] VAR7;
always @(posedge clk) VA... | gpl-3.0 |
secworks/rosc_entropy | src/rtl/rosc.v | 3,615 | module MODULE1 #(parameter VAR6 = 2)
(
input wire clk,
input wire VAR8,
input wire VAR3,
input wire [(VAR6 - 1) : 0] VAR1,
input wire [(VAR6 - 1) : 0] VAR5,
output wire dout
);
reg VAR7;
reg VAR4;
assign dout = VAR7;
always @ (posedge clk or negedge VAR8)
begin
if (!VAR8)
begin
VAR7 <= 1'b0;
end
else
begin
if (VAR3)
be... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15.behavioral.v | 1,405 | module MODULE1 (
VAR5,
VAR7
);
output VAR5;
input VAR7;
supply1 VAR3;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR2 ;
wire VAR1;
buf VAR9 (VAR1, VAR7 );
buf VAR8 (VAR5 , VAR1 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/cmm_errman_ram4x26.v | 4,628 | module MODULE1 (
VAR5,
VAR2, VAR8,
VAR3,
VAR7,
rst,
clk
);
output [49:0] VAR5;
input [49:0] VAR2;
input [1:0] VAR8;
input [1:0] VAR3;
input VAR7;
input rst;
input clk;
reg [49:0] VAR1 [0:3];
always @(posedge clk) begin
if (VAR7)
VAR1[VAR8] <= #VAR4 VAR2;
end
reg [49:0] VAR6;
always @(posedge clk or posedge rst)
begin
i... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221oi/sky130_fd_sc_lp__a221oi_2.v | 2,457 | module MODULE2 (
VAR4 ,
VAR7 ,
VAR6 ,
VAR9 ,
VAR11 ,
VAR3 ,
VAR10,
VAR1,
VAR8 ,
VAR5
);
output VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR9 ;
input VAR11 ;
input VAR3 ;
input VAR10;
input VAR1;
input VAR8 ;
input VAR5 ;
VAR2 VAR12 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR10(V... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/yacc/pc_module.v | 2,802 | module MODULE1(VAR3,VAR15,VAR10,VAR5,VAR7,VAR26,VAR13,
VAR16 ,VAR12,VAR27,VAR6,VAR11,VAR22, VAR8);
input VAR3;
input VAR15;
input [31:0] VAR26;
input [2:0] VAR10;
input VAR13;
input [25:0] VAR7;
input [25:0] VAR22;
output [11:0] VAR5;
output [25:0] VAR5;
input VAR16;
input VAR12,VAR27;
input VAR6;
input [7:0] VAR11;
re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111a/sky130_fd_sc_ls__o2111a_1.v | 2,448 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR7 ,
VAR10 ,
VAR5 ,
VAR1 ,
VAR8,
VAR2,
VAR9 ,
VAR12
);
output VAR3 ;
input VAR6 ;
input VAR7 ;
input VAR10 ;
input VAR5 ;
input VAR1 ;
input VAR8;
input VAR2;
input VAR9 ;
input VAR12 ;
VAR4 VAR11 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR8(VA... | apache-2.0 |
lowRISC/flexpret | Counter.v | 5,144 | module MODULE1(VAR1, VAR9, VAR16, VAR15, VAR12, VAR8, VAR6);
parameter VAR14 = 32,
VAR10 = 0,
VAR2 = 0,
VAR7 = {VAR14{1'VAR11}},
VAR4 = 0,
VAR13 = 0;
input VAR1, VAR9, VAR16, VAR15, VAR12;
input [VAR14-1:0] VAR8;
output [VAR14-1:0] VAR6;
wire VAR19;
wire VAR5;
wire [VAR14-1:0] VAR3;
assign VAR19 = !VAR10;
assign VAR5 =... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32o/sky130_fd_sc_hs__a32o_2.v | 2,342 | module MODULE2 (
VAR6 ,
VAR9 ,
VAR5 ,
VAR7 ,
VAR10 ,
VAR8 ,
VAR4,
VAR2
);
output VAR6 ;
input VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR10 ;
input VAR8 ;
input VAR4;
input VAR2;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODUL... | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/dram_mon.v | 388,206 | module MODULE1 ( clk, VAR2);
input clk; input VAR2;
reg VAR1;
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin
begin
begi... | gpl-2.0 |
Murailab-arch/magukara | cores/fifo9togmii/rtl/fifo9togmii.v | 4,095 | module MODULE1 (
input VAR18,
input [8:0] dout,
input VAR8,
output VAR10,
output VAR2,
input VAR33,
output VAR19,
output [7:0] VAR23
);
assign VAR2 = VAR33;
wire VAR28;
wire [31:0] VAR7;
reg VAR29;
reg [7:0] VAR32;
assign VAR21 = ~VAR29;
VAR12 VAR6 (
.VAR17(VAR18),
.VAR22(VAR33),
.VAR20(VAR28),
.VAR27(VAR32),
.VAR5(VAR... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/byte_group_io.v | 19,272 | module MODULE1 #(
parameter VAR123 = "VAR169",
parameter VAR107 = 12'b111111111111,
parameter VAR104 = 12'b000000000000,
parameter VAR24 = "VAR154",
parameter VAR23 = 4,
parameter VAR35 = "VAR128",
parameter VAR22 = "VAR68",
parameter VAR99 = 00,
parameter VAR14 = "VAR75",
parameter VAR164 = 12
)
(
input [9:0] VAR105,
... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_20.behavioral.pp.v | 1,172 | module MODULE1( VAR3, VAR6, VAR5, VAR1 );
input VAR3;
inout VAR5, VAR1;
output VAR6;
VAR7 VAR4(.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5),.VAR1(VAR1));
VAR7 VAR2(.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/soc_system/synthesis/soc_system.v | 10,319 | module MODULE1 (
input wire VAR17, input wire [28:0] VAR43, input wire [7:0] VAR101, output wire VAR105, output wire [63:0] VAR26, output wire VAR78, input wire VAR88, input wire [28:0] VAR41, input wire [7:0] VAR39, output wire VAR107, output wire [63:0] VAR86, output wire VAR3, input wire VAR53, input wire [28:0] VAR... | apache-2.0 |
peteasa/oh | src/common/hdl/oh_fifo_cdc.v | 2,027 | module MODULE1 # (parameter VAR1 = 104, parameter VAR6 = 32, parameter VAR21 = "VAR12" )
(
input VAR8, input VAR4, input VAR14, input [VAR1-1:0] VAR3, output VAR22, input VAR19, output reg VAR15, output [VAR1-1:0] VAR17, input VAR20, output VAR16, output VAR23, output VAR2 );
wire VAR10;
wire VAR13;
assign VAR10 = VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/inv/sky130_fd_sc_hvl__inv_1.v | 2,003 | module MODULE2 (
VAR3 ,
VAR7 ,
VAR5,
VAR6,
VAR1 ,
VAR4
);
output VAR3 ;
input VAR7 ;
input VAR5;
input VAR6;
input VAR1 ;
input VAR4 ;
VAR2 VAR8 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR3,
VAR7
);
output VAR3;
input VAR7;
supply1 VAR5;
supply0 VAR6;... | apache-2.0 |
JohnOrlando/gnuradio-bitshark | gr-radar-mono/src/fpga/top/dacpll.v | 14,131 | module MODULE1 (
VAR35,
VAR28,
VAR70);
input VAR35;
input VAR28;
output VAR70;
wire [5:0] VAR93;
wire [0:0] VAR91 = 1'h0;
wire [0:0] VAR60 = VAR93[0:0];
wire VAR70 = VAR60;
wire VAR14 = VAR28;
wire [1:0] VAR75 = {VAR91, VAR14};
VAR41 VAR81 (
.VAR32 (VAR75),
.VAR35 (VAR35),
.clk (VAR93),
.VAR2 (),
.VAR8 (),
.VAR87 ({6{1... | gpl-3.0 |
ptracton/vscale_soc | rtl/wb_riscvscale/vscale_regfile.v | 1,065 | module MODULE1(
input clk,
input [VAR7-1:0] VAR1,
output [VAR5-1:0] VAR6,
input [VAR7-1:0] VAR11,
output [VAR5-1:0] VAR10,
input VAR2,
input [VAR7-1:0] VAR12,
input [VAR5-1:0] VAR4
);
reg [VAR5-1:0] VAR3 [31:0];
wire VAR9;
assign VAR9 = VAR2 && |VAR12;
assign VAR6 = |VAR1 ? VAR3[VAR1] : 0;
assign VAR10 = |VAR11 ? VAR3[... | mit |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v | 6,970 | module MODULE1 (
VAR6,
VAR23,
VAR31,
VAR50,
VAR39,
VAR18,
VAR64,
VAR9,
VAR1,
VAR91,
VAR63,
VAR40,
VAR48,
VAR92,
VAR89,
VAR82,
VAR53,
VAR42,
VAR16,
VAR58,
VAR84,
VAR4,
VAR28,
VAR37,
VAR20,
VAR52,
VAR43,
VAR3,
VAR90,
VAR14,
VAR80,
VAR61,
VAR78,
VAR69,
VAR17,
VAR65,
VAR34,
VAR77
);
input [7-1:0] VAR77;
input VAR6;
input V... | gpl-3.0 |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/video_scaler_mul_jbC.v | 1,335 | module MODULE1(clk, VAR5, VAR15, VAR10, VAR3);
input clk;
input VAR5;
input[32 - 1 : 0] VAR15;
input[16 - 1 : 0] VAR10;
output[32 - 1 : 0] VAR3;
reg signed [32 - 1 : 0] VAR11;
reg signed [16 - 1 : 0] VAR12;
wire signed [32 - 1 : 0] VAR6;
reg signed [32 - 1 : 0] VAR8;
assign VAR3 = VAR8;
assign VAR6 = VAR11 * VAR12;
alw... | mit |
xarteaga/7A35T_Arty_RemoteLedControl | fpga/hw_system/ip_repo/massive_pwm_1.0/hdl/massive_pwm_v1_0.v | 2,444 | module MODULE1 #
(
parameter integer VAR24 = 4,
parameter integer VAR22 = 32,
parameter integer VAR29 = 6
)
(
input wire clk,
input wire rst,
output wire [(3*VAR24-1): 0] VAR43,
input wire VAR31,
input wire VAR40,
input wire [VAR29-1 : 0] VAR4,
input wire [2 : 0] VAR28,
input wire VAR49,
output wire VAR3,
input wire [V... | mit |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/PackSum.v | 2,192 | module MODULE1(
input [1:0] VAR11,
input [31:0] VAR10,
input [1:0] VAR19,
input VAR6,
input VAR12,
input [27:0] VAR3,
input [7:0] VAR13,
input VAR8,
output reg [31:0] VAR14,
output reg [1:0] VAR21,
output reg VAR20,
output reg VAR16,
output reg [7:0] VAR15
);
parameter VAR5 =2'b01,
VAR18 =2'b00,
VAR17=2'b11;
parameter ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.v | 2,419 | module MODULE1 (
VAR9 ,
VAR6,
VAR2,
VAR1 ,
VAR7 ,
VAR8,
VAR11,
VAR5 ,
VAR10
);
output VAR9 ;
input VAR6;
input VAR2;
input VAR1 ;
input VAR7 ;
input VAR8;
input VAR11;
input VAR5 ;
input VAR10 ;
VAR3 VAR4 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR10(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor2/sky130_fd_sc_hd__xor2.blackbox.v | 1,264 | module MODULE1 (
VAR3,
VAR2,
VAR1
);
output VAR3;
input VAR2;
input VAR1;
supply1 VAR7;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_axi_basic_tx_pipeline.v | 22,390 | module MODULE1 #(
parameter VAR49 = 128, parameter VAR59 = "VAR34", parameter VAR42 = 1,
parameter VAR35 = (VAR49 == 128) ? 2 : 1, parameter VAR50 = VAR49 / 8 ) (
input [VAR49-1:0] VAR62, input VAR28, output VAR53, input [VAR50-1:0] VAR5, input VAR44, input [3:0] VAR24,
output [VAR49-1:0] VAR32, output VAR48, output VA... | mit |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_mem_if_out.v | 12,800 | module MODULE1
(
input VAR70, input [8:0] VAR82, input [8:0] VAR11, input [31:0] VAR62, input [31:0] VAR40, input [31:0] VAR49, input [31:0] VAR66, input [31:0] VAR57, input [31:0] VAR15, input [31:0] VAR22, input [31:0] VAR20, input [31:0] VAR69, input [2:0] VAR26, input [4:0] VAR60, input VAR4, input VAR87,
input VAR... | gpl-3.0 |
carstenbru/fpga-log | spartanmc/hardware/timestamp_counter/src/spmc_timestamp_counter.v | 3,208 | module MODULE1 #(
parameter VAR7 = 16000000, parameter VAR9 = 10'h0) (
input wire VAR17, input wire [17:0] VAR4, output wire [17:0] VAR18, input wire [9:0] VAR22, input wire VAR19, input wire VAR13,
input wire reset,
output reg [35:0] VAR11, output reg [35:0] VAR23 );
parameter VAR6 = 2'b00; parameter VAR20 = 2'b01; pa... | gpl-3.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_samq_tracker.v | 5,113 | module MODULE1
(clk, reset, VAR18, VAR15, VAR30, VAR4, VAR22,
VAR27, VAR24, VAR10, VAR19, VAR32, VAR26);
parameter VAR8 = 4;
parameter VAR28 = 8;
parameter VAR12 = 0;
parameter VAR21 = 0;
parameter VAR3 = 0;
parameter VAR20 = VAR33;
input clk;
input reset;
input VAR18;
input VAR15;
input [0:VAR8-1] VAR30;
input VAR4;
i... | gpl-2.0 |
buhii/LGA-FHP2 | cppg.v | 5,794 | module MODULE1
(
input VAR43,
input VAR70,
input VAR67,
input VAR22,
input [9:0] VAR30,
input [13:0] VAR19,
input [9:0] VAR51,
input [9:0] VAR53,
input VAR65,
input VAR36,
input [63:0] VAR42,
output [63:0] VAR15,
output reg [7:0] VAR55
);
reg [8:0] VAR37;
always @ ( negedge VAR70 or posedge VAR43 ) begin
if ( ~VAR70 )
... | mit |
FAST-Switch/fast | projects/SDTS/example/hw-src/triple_speed_ethernet-library/altera_tse_rgmii_module.v | 7,352 | module MODULE1 ( VAR26,
VAR39,
VAR2,
VAR20,
VAR25,
VAR1,
VAR22,
VAR37,
VAR8,
VAR38,
VAR11,
VAR17,
VAR6,
VAR9,
VAR31,
VAR51,
VAR50,
VAR29,
VAR23,
VAR32,
VAR15,
VAR52,
VAR36
)
;
output [ 3: 0] VAR9;
output [ 7: 0] VAR31;
output [ 3: 0] VAR51;
output VAR50;
output VAR29;
output VAR23;
output VAR32;
output VAR15;
output VA... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_port_lookup/cam_router/src/ip_lpm.v | 8,030 | module MODULE1
parameter VAR34 = 5,
parameter VAR32 = VAR53,
parameter VAR63 = VAR62(VAR32)
)
( input [VAR49-1:0] VAR41,
output reg [31:0] VAR42,
output reg [VAR34-1:0] VAR64,
output reg VAR1,
output reg VAR15,
input VAR51,
input VAR39,
input [VAR63-1:0] VAR14, input VAR44, output [31:0] VAR36, output [31:0] VAR70, out... | mit |
peteasa/oh | src/common/dv/dv_ctrl.v | 2,766 | module MODULE1(
VAR9, VAR1, VAR7, VAR13, VAR11, VAR15,
VAR12, VAR2, VAR18
);
parameter VAR16 = 10;
parameter VAR3 = VAR16/2;
parameter VAR6 = 100;
parameter VAR10 = VAR6/2;
parameter VAR5 = 50000;
output VAR9; output VAR1; output VAR7; output VAR13; output VAR11; output VAR15;
input VAR12; input VAR2; input VAR18;
reg ... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9122_v6_00_a/hdl/verilog/axi_ad9122_if.v | 7,548 | module MODULE1 (
VAR67,
VAR39,
VAR41,
VAR53,
VAR70,
VAR52,
VAR22,
VAR20,
VAR7,
VAR43,
VAR13,
VAR10,
VAR42,
VAR45,
VAR21,
VAR55,
VAR9,
VAR73,
VAR72,
VAR15,
VAR38,
VAR64,
VAR35,
VAR16,
VAR68,
VAR34,
VAR54,
VAR31,
VAR36,
VAR28,
VAR5,
VAR19,
VAR66,
VAR49,
VAR1,
VAR14,
VAR44);
parameter VAR61 = 0;
parameter VAR60 = 1;
param... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/spw_babasu_FLAGS.v | 1,851 | module MODULE1 (
address,
clk,
VAR2,
VAR4,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input [ 10: 0] VAR2;
input VAR4;
wire VAR1;
wire [ 10: 0] VAR5;
wire [ 10: 0] VAR6;
reg [ 31: 0] VAR3;
assign VAR1 = 1;
assign VAR6 = {11 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR4)
begin
if (... | gpl-3.0 |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/wasca_bb.v | 2,192 | module MODULE1 (
VAR25,
VAR11,
VAR20,
VAR3,
VAR28,
VAR2,
VAR26,
VAR12,
VAR10,
VAR23,
VAR13,
VAR6,
VAR15,
VAR16,
VAR17,
VAR4,
VAR7,
VAR29,
VAR18,
VAR8,
VAR27,
VAR21,
VAR19,
VAR1,
VAR24,
VAR22,
VAR9,
VAR30,
VAR14,
VAR5);
input [9:0] VAR25;
input [2:0] VAR11;
input VAR20;
input [1:0] VAR3;
output VAR28;
output VAR2;
inout... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ba/sky130_fd_sc_hs__o21ba_1.v | 2,189 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR6 ,
VAR4,
VAR3,
VAR5
);
output VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR4;
input VAR3;
input VAR5;
VAR7 VAR2 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR1 ,
VAR8 ,
VAR6 ,
VAR4
);
output VAR1 ;
input VAR8 ;
input VAR6 ... | apache-2.0 |
gbraad/minimig-de1 | lib/models/mt48lc16m16a2.v | 50,471 | module MODULE1 (VAR17, VAR77, VAR15, VAR42, VAR80, VAR64, VAR82, VAR105, VAR54, VAR51);
parameter VAR13 = 13;
parameter VAR47 = 10;
parameter VAR25 = 8388608;
parameter VAR13 = 13;
parameter VAR47 = 9;
parameter VAR25 = 4194304;
parameter VAR13 = 12;
parameter VAR47 = 8;
parameter VAR25 = 1048576;
parameter VAR62 = 16;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111ai/sky130_fd_sc_hd__o2111ai.blackbox.v | 1,402 | module MODULE1 (
VAR8 ,
VAR7,
VAR6,
VAR4,
VAR1,
VAR10
);
output VAR8 ;
input VAR7;
input VAR6;
input VAR4;
input VAR1;
input VAR10;
supply1 VAR3;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2o/sky130_fd_sc_ms__a2bb2o.functional.v | 1,609 | module MODULE1 (
VAR9 ,
VAR6,
VAR11,
VAR8 ,
VAR7
);
output VAR9 ;
input VAR6;
input VAR11;
input VAR8 ;
input VAR7 ;
wire VAR1 ;
wire VAR2 ;
wire VAR10;
and VAR4 (VAR1 , VAR8, VAR7 );
nor VAR5 (VAR2 , VAR6, VAR11 );
or VAR12 (VAR10, VAR2, VAR1);
buf VAR3 (VAR9 , VAR10 );
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/cdp/tx139_gmii_1000.v | 16,614 | module MODULE1(
clk,
reset,
VAR7,
VAR9,
VAR39,
VAR46,
VAR3,
VAR19,
VAR29,
VAR17,
VAR14, VAR47
);
input clk; input reset;
input VAR7;
input VAR9; input [138:0]VAR39;
input VAR46; input VAR3;
output [7:0]VAR19; output VAR29;
output VAR17;
output [7:0]VAR14; output VAR47;
reg VAR47;
reg [7:0]VAR19;
reg VAR29;
reg VAR17;
r... | apache-2.0 |
juan199/Lab_Digitales | exp2/Collaterals.v | 1,262 | module MODULE3 # (parameter VAR8=16)
(
input wire VAR12, VAR2,
input wire [VAR8-1:0] VAR10,
input wire VAR7,
output reg [VAR8-1:0] VAR4
);
always @(posedge VAR12 )
begin
if (VAR2)
VAR4 = VAR10;
end
else
begin
if (VAR7)
VAR4 = VAR4 + 1;
end
end
endmodule
module MODULE1 # ( parameter VAR8=8 )
(
input wire VAR12,
input wi... | lgpl-3.0 |
Lan-Hekary/ARM | ARM.v | 1,520 | module MODULE1(input clk,input reset,input [31:0] VAR9,input [31:0]VAR1,output [31:0] VAR7 ,
output [31:0] VAR5,
output VAR8,output reg [31:0] VAR13);
wire[3:0] VAR6;
wire VAR11,VAR3,VAR15;
wire [1:0]VAR2;
wire VAR4;
wire [1:0]VAR12;
wire VAR10;
wire [1:0]VAR14; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probec_p/sky130_fd_sc_hvl__probec_p.pp.blackbox.v | 1,273 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR4,
VAR2,
VAR3 ,
VAR5
);
output VAR1 ;
input VAR6 ;
input VAR4;
input VAR2;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2b/sky130_fd_sc_lp__nor2b_1.v | 2,173 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR9 ,
VAR6,
VAR7,
VAR1 ,
VAR5
);
output VAR3 ;
input VAR4 ;
input VAR9 ;
input VAR6;
input VAR7;
input VAR1 ;
input VAR5 ;
VAR2 VAR8 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR3 ,
VAR4 ,
VAR9
);
output VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buf/sky130_fd_sc_lp__buf_4.v | 1,993 | module MODULE2 (
VAR7 ,
VAR8 ,
VAR5,
VAR3,
VAR2 ,
VAR1
);
output VAR7 ;
input VAR8 ;
input VAR5;
input VAR3;
input VAR2 ;
input VAR1 ;
VAR6 VAR4 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7,
VAR8
);
output VAR7;
input VAR8;
supply1 VAR5;
supply0 VAR3;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2b/sky130_fd_sc_hd__or2b_1.v | 2,127 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR6 ,
VAR2,
VAR5,
VAR9 ,
VAR4
);
output VAR8 ;
input VAR7 ;
input VAR6 ;
input VAR2;
input VAR5;
input VAR9 ;
input VAR4 ;
VAR1 VAR3 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR8 ,
VAR7 ,
VAR6
);
output VAR8... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/4-way/src/riffa/ram_1clk_1w_1r.v | 3,207 | module MODULE1
parameter VAR11 = 32,
parameter VAR2 = 1024
)
(
input VAR8,
input [VAR6(VAR2)-1:0] VAR7,
input VAR12,
input [VAR6(VAR2)-1:0] VAR5,
input [VAR11-1:0] VAR3,
output [VAR11-1:0] VAR9
);
localparam VAR4 = VAR6(VAR2);
reg [VAR11-1:0] VAR1 [VAR2-1:0];
reg [VAR11-1:0] VAR10;
assign VAR9 = VAR10;
always @(posedge... | mit |
danthemango/IC7400 | sn74151/behaviour.v | 1,269 | module MODULE1 (VAR14,VAR6,VAR12,VAR7,VAR5,VAR2,VAR13,VAR10,VAR4,VAR16,VAR11,VAR1,VAR15,VAR9,VAR3,VAR17);
input wire VAR7, VAR12, VAR6, VAR14, VAR3, VAR9, VAR15, VAR1, VAR13, VAR11, VAR16, VAR4, VAR10, VAR17;
output reg VAR5; output wire VAR2;
assign VAR2 = ~VAR5;
always @(VAR14, VAR6, VAR12, VAR7, VAR13, VAR10, VAR4, ... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/verilog/FIFO_image_filter_p_src_rows_V_channel1.v | 3,023 | module MODULE2 (
clk,
VAR23,
VAR20,
VAR6,
VAR4);
parameter VAR16 = 32'd12;
parameter VAR24 = 32'd2;
parameter VAR7 = 32'd3;
input clk;
input [VAR16-1:0] VAR23;
input VAR20;
input [VAR24-1:0] VAR6;
output [VAR16-1:0] VAR4;
reg[VAR16-1:0] VAR14 [0:VAR7-1];
integer VAR27;
always @ (posedge clk)
begin
if (VAR20)
begin
for ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31ai/sky130_fd_sc_ms__o31ai.symbol.v | 1,354 | module MODULE1 (
input VAR3,
input VAR5,
input VAR9,
input VAR1,
output VAR7
);
supply1 VAR4;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
valkwarble/finalProject | source/video_decoder.v | 31,047 | module MODULE2(clk, reset, VAR24, VAR16, VAR21, VAR31, VAR14, VAR12);
input clk;
input reset;
input [9:0] VAR24; output [29:0] VAR16;
output VAR21;
output VAR31;
output VAR14;
output VAR12;
parameter VAR27 = 0;
parameter VAR2 = 1;
parameter VAR25 = 2;
parameter VAR11 = 3;
parameter VAR23 = 4;
parameter VAR26 = 5;
param... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcadc2/common/fmcadc2_spi.v | 4,326 | module MODULE1 (
VAR1,
VAR18,
VAR12,
VAR7,
VAR14,
VAR11,
VAR22,
VAR4);
input VAR1;
input VAR18;
input VAR12;
input VAR7;
input VAR14;
output VAR11;
inout VAR22;
inout VAR4;
reg [ 5:0] VAR15 = 'd0;
reg VAR19 = 'd0;
reg VAR3 = 'd0;
wire VAR9;
wire VAR5;
wire VAR2;
wire VAR20;
assign VAR9 = VAR18 & VAR12 & VAR7;
assign VA... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/SGMII_RX.v | 6,692 | module MODULE1
(reset,
VAR14,
VAR21,
VAR24,
VAR26,
VAR16,
VAR13,
VAR9,
VAR19,
VAR22,
VAR3,
VAR23,
VAR18,
VAR7,
VAR10,
VAR5,
VAR1,
VAR11,
VAR17,
VAR25,
VAR4
);
input reset;
input VAR14;
output VAR21;
input [31:0] VAR24;
input [1:0] VAR26;
input VAR16;
input VAR13;
input [5:0] VAR9;
input [17:0] VAR19;
input [3:0] VAR22;... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v6es_gtx_x4_250/example_design/PIO_64_RX_ENGINE.v | 19,161 | module MODULE1 (
clk,
VAR36,
VAR33,
VAR52,
VAR34,
VAR31,
VAR14,
VAR56,
VAR20,
VAR55,
VAR47,
VAR40,
VAR48, VAR53, VAR38, VAR9, VAR19, VAR21, VAR12, VAR16, VAR45,
VAR28, VAR50, VAR37, VAR27, VAR26
);
input clk;
input VAR36;
input [63:0] VAR33;
input [7:0] VAR52;
input VAR34;
input VAR31;
input VAR14;
input VAR56;
input [... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_hvc_wpadv2/sky130_fd_io__top_power_hvc_wpadv2.symbol.v | 1,677 | module MODULE1 (
inout VAR16 ,
inout VAR11,
inout VAR13
);
supply1 VAR15 ;
supply1 VAR5 ;
supply0 VAR7;
supply1 VAR4 ;
supply1 VAR3 ;
supply1 VAR12 ;
supply1 VAR9 ;
supply1 VAR10 ;
supply1 VAR17 ;
supply1 VAR8 ;
supply0 VAR14 ;
supply0 VAR2 ;
supply0 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_cmd_gen.v | 120,771 | module MODULE1
VAR290 = 33,
VAR103 = 3,
VAR210 = 8,
VAR166 = 4,
VAR25 = 4,
VAR148 = 5,
VAR10 = 2,
VAR264 = 2,
VAR227 = 5,
VAR163 = 2,
VAR280 = 2, VAR116 = 8,
VAR309 = 1, VAR89 = 1, VAR140 = 3,
VAR185 = 13,
VAR317 = 10,
VAR175 = 10,
VAR292 = 1,
VAR180 = 1,
VAR55 = 0,
VAR289 = 4,
VAR215 = 4,
VAR256 = 8,
VAR320 = 12,
VAR5... | gpl-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_spram.v | 5,238 | module MODULE1
(
VAR4, VAR1, VAR5,
clk, VAR6, VAR2, addr, VAR8, VAR13
);
parameter VAR7 = 10;
parameter VAR10 = 32;
input VAR4;
input [VAR11 - 1:0] VAR5;
output VAR1;
input clk; input VAR6; input VAR2; input [VAR7-1:0] addr; input [VAR10-1:0] VAR8; output [VAR10-1:0] VAR13;
reg [VAR10-1:0] VAR12 [(1<<VAR7)-1:0] ;
reg [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor3/sky130_fd_sc_hd__xnor3_4.v | 2,184 | module MODULE2 (
VAR1 ,
VAR9 ,
VAR3 ,
VAR5 ,
VAR4,
VAR8,
VAR6 ,
VAR2
);
output VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR5 ;
input VAR4;
input VAR8;
input VAR6 ;
input VAR2 ;
VAR7 VAR10 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE2 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111oi/sky130_fd_sc_ms__a2111oi.pp.blackbox.v | 1,435 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR10 ,
VAR1 ,
VAR8 ,
VAR4 ,
VAR2,
VAR5,
VAR7 ,
VAR6
);
output VAR9 ;
input VAR3 ;
input VAR10 ;
input VAR1 ;
input VAR8 ;
input VAR4 ;
input VAR2;
input VAR5;
input VAR7 ;
input VAR6 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/yacc/uart_write_cyclone.v | 3,552 | module MODULE1( VAR29, clk, VAR8, VAR21 , VAR25,VAR17,VAR1);
input VAR29,clk;
input [7:0] VAR21;
input VAR25;
output VAR8,VAR17;
output VAR1;
wire VAR5;
wire VAR14, VAR35;
wire [7:0] VAR27;
reg VAR30;
reg [8:0] VAR31;
reg [2:0] VAR12;
reg [2:0] VAR36;
reg [7:0] VAR6;
reg VAR15;
reg VAR8;
wire VAR9, VAR23, VAR19,
VAR4, ... | mit |
asicguy/gplgpu | hdl/altera_rams/ram_32x32_dp_be.v | 11,040 | module MODULE1 (
VAR37,
VAR9,
VAR43,
VAR33,
VAR52,
VAR51,
VAR36,
VAR13,
VAR10,
VAR16,
VAR41);
input [4:0] VAR37;
input [4:0] VAR9;
input [3:0] VAR43;
input VAR33;
input VAR52;
input [31:0] VAR51;
input [31:0] VAR36;
input VAR13;
input VAR10;
output [31:0] VAR16;
output [31:0] VAR41;
tri1 [3:0] VAR43;
tri1 VAR33;
tri0 V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.v | 2,262 | module MODULE1 (
VAR4,
VAR6 ,
VAR2,
VAR1 ,
VAR9,
VAR3,
VAR10 ,
VAR8
);
output VAR4;
input VAR6 ;
input VAR2;
input VAR1 ;
input VAR9;
input VAR3;
input VAR10 ;
input VAR8 ;
VAR7 VAR5 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/maj3/sky130_fd_sc_lp__maj3.behavioral.v | 1,581 | module MODULE1 (
VAR7,
VAR4,
VAR3,
VAR14
);
output VAR7;
input VAR4;
input VAR3;
input VAR14;
supply1 VAR16;
supply0 VAR12;
supply1 VAR6 ;
supply0 VAR9 ;
wire VAR10 ;
wire VAR11 ;
wire VAR2 ;
wire VAR15;
or VAR13 (VAR10 , VAR3, VAR4 );
and VAR5 (VAR11 , VAR10, VAR14 );
and VAR8 (VAR2 , VAR4, VAR3 );
or VAR1 (VAR15, VAR... | apache-2.0 |
fominok/spilol | verilog/spi.v | 1,426 | module MODULE1 #(
parameter VAR7=8 )
(
input clk, input rst,
input [7:0] VAR4, output reg[7:0] VAR6, input VAR12, output VAR2,
input VAR1, output VAR5, output VAR10, output VAR8 );
reg[ 3:0] VAR9;
reg[ 7:0] VAR3;
reg[31:0] VAR11;
assign VAR8 = VAR9 == 0;
assign VAR10 = !VAR9[0] || VAR8;
assign VAR5 = VAR3[VAR9 >> 1];
a... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111ai/sky130_fd_sc_hd__o2111ai_4.v | 2,461 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR9 ,
VAR6 ,
VAR5 ,
VAR8 ,
VAR1,
VAR4,
VAR12 ,
VAR11
);
output VAR7 ;
input VAR3 ;
input VAR9 ;
input VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR1;
input VAR4;
input VAR12 ;
input VAR11 ;
VAR10 VAR2 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd.pp.blackbox.v | 1,226 | module MODULE1 (
VAR4,
VAR1,
VAR3 ,
VAR2
);
input VAR4;
input VAR1;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
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