repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
EmbeddedANT/ALTERA_DE0-Nano | DE0Nano_Leds/DE0Nano_Leds.v | 1,882 | module MODULE1(
VAR8,
VAR4
);
input VAR8;
output [7:0]VAR4;
wire VAR3;
reg [7:0]VAR2=8'h00;
VAR9 #(.VAR1 (28)) VAR10
( .VAR5(VAR8),
.VAR7(VAR3),
.VAR6(28'd25000000));
always @ (posedge VAR3) begin
VAR2<=VAR2+1;
end
assign VAR4 = VAR2;
endmodule | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_cordic_Arch2/integracion_fisica/front_end/source/lut_CASE_32.v | 1,776 | module MODULE1 #(parameter VAR2=32,VAR1=3)
(
input wire [VAR1-1:0] address,
output reg [VAR2-1:0] VAR3
);
always @(*) begin
case (address)
4'd0 : begin
VAR3 =32'h3f490fdb;
end
4'd1 : begin
VAR3 =32'h3eed6338;
end
4'd2 : begin
VAR3 =32'h3e7adbb0;
end
4'd3 : begin
VAR3 =32'h3dfeadd5;
end
4'd4 : begin
VAR3 =32'h3d7faade;
... | gpl-3.0 |
hoglet67/CoPro6502 | src/zet/wb_switch/wb_switch.v | 9,419 | module MODULE1 #(
parameter VAR95 = 20'h00000, parameter VAR139 = 20'h00000,
parameter VAR71 = 20'h00000,
parameter VAR118 = 20'h00000,
parameter VAR107 = 20'h00000,
parameter VAR28 = 20'h00000,
parameter VAR6 = 20'h00000,
parameter VAR79 = 20'h00000,
parameter VAR102 = 20'h00000,
parameter VAR37 = 20'h00000,
parameter... | gpl-3.0 |
olajep/oh | src/adi/hdl/library/altera/common/ad_dcfilter.v | 2,868 | module MODULE1 #(
parameter VAR9 = 0) (
input clk,
input valid,
input [15:0] VAR11,
output reg VAR1,
output reg [15:0] VAR2,
input VAR5,
input [15:0] VAR8,
input [15:0] VAR4);
reg VAR3 = 'd0;
reg [15:0] VAR6 = 'd0;
reg VAR10 = 'd0;
reg [15:0] VAR12 = 'd0;
wire [47:0] VAR7;
always @(posedge clk) begin
VAR3 <= valid;
if ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfstp/sky130_fd_sc_lp__sdfstp.behavioral.pp.v | 2,802 | module MODULE1 (
VAR13 ,
VAR8 ,
VAR12 ,
VAR29 ,
VAR25 ,
VAR27,
VAR18 ,
VAR9 ,
VAR16 ,
VAR20
);
output VAR13 ;
input VAR8 ;
input VAR12 ;
input VAR29 ;
input VAR25 ;
input VAR27;
input VAR18 ;
input VAR9 ;
input VAR16 ;
input VAR20 ;
wire VAR19 ;
wire VAR4 ;
wire VAR28 ;
reg VAR24 ;
wire VAR2 ;
wire VAR17 ;
wire VAR14 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2.blackbox.v | 1,288 | module MODULE1 (
VAR2,
VAR5
);
output VAR2;
input VAR5;
supply1 VAR3;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_GeArN8R1P1_syn.v | 7,491 | module MODULE1 ( VAR38, VAR270, VAR133, VAR209 );
input [15:0] VAR270;
input [15:0] VAR133;
output [16:0] VAR209;
input VAR38;
wire VAR62, VAR206, VAR69, VAR58, VAR104, VAR21, VAR198, VAR64, VAR55, VAR148, VAR73, VAR25, VAR120, VAR68,
VAR129, VAR87, VAR86, VAR1, VAR89, VAR152, VAR202, VAR32, VAR214, VAR221, VAR121, VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2/sky130_fd_sc_ls__nand2.functional.pp.v | 1,792 | module MODULE1 (
VAR10 ,
VAR13 ,
VAR11 ,
VAR2,
VAR6,
VAR9 ,
VAR1
);
output VAR10 ;
input VAR13 ;
input VAR11 ;
input VAR2;
input VAR6;
input VAR9 ;
input VAR1 ;
wire VAR3 ;
wire VAR12;
nand VAR5 (VAR3 , VAR11, VAR13 );
VAR8 VAR4 (VAR12, VAR3, VAR2, VAR6);
buf VAR7 (VAR10 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxtp/sky130_fd_sc_hd__sdfxtp.behavioral.pp.v | 2,370 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR3 ,
VAR10 ,
VAR25 ,
VAR22,
VAR18,
VAR8 ,
VAR23
);
output VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR10 ;
input VAR25 ;
input VAR22;
input VAR18;
input VAR8 ;
input VAR23 ;
wire VAR19 ;
wire VAR14 ;
reg VAR2 ;
wire VAR20 ;
wire VAR24;
wire VAR7;
wire VAR12;
wire VAR16 ;
wire VAR13 ;
wire... | apache-2.0 |
mbuesch/toprammer | libtoprammer/fpga/src/m8c-issp/m8c-issp.v | 10,190 | module MODULE1(VAR23, VAR8, write, read, VAR4, VAR21);
inout [7:0] VAR23;
input VAR8;
input write;
input read;
input VAR4;
inout [48:1] VAR21;
wire VAR22;
reg [7:0] address;
reg [7:0] VAR27;
wire VAR26, VAR30;
reg [1:0] VAR10;
reg [7:0] VAR33;
reg [VAR9-1:0] VAR20;
reg [5:0] VAR13;
reg [7:0] VAR2;
reg [3:0] VAR7;
wire ... | gpl-2.0 |
sabertazimi/hust-lab | architecture/design/fpga/src/decoder.v | 1,178 | module MODULE1
(
input [31:0] VAR15,
output [5:0] VAR14,
output [4:0] VAR6,
output [4:0] VAR7,
output [4:0] rd,
output [4:0] VAR1,
output [5:0] VAR13,
output [15:0] VAR12,
output [25:0] VAR16
);
assign VAR14 = VAR15[VAR3];
assign VAR6 = VAR15[VAR2];
assign VAR7 = VAR15[VAR4];
assign rd = VAR15[VAR10];
assign VAR1 = VAR... | mit |
efabless/openlane | designs/picorv32a/src/picorv32a.v | 92,423 | module MODULE1 #(
parameter [ 0:0] VAR33 = 1,
parameter [ 0:0] VAR21 = 1,
parameter [ 0:0] VAR59 = 0,
parameter [ 0:0] VAR100 = 0,
parameter [ 0:0] VAR69 = 0,
parameter [ 0:0] VAR84 = 1,
parameter [ 0:0] VAR62 = 1,
parameter [ 0:0] VAR64 = 0,
parameter [ 0:0] VAR26 = 1,
parameter [ 0:0] VAR85 = 0,
parameter [ 0:0] VAR5... | apache-2.0 |
liqimai/ZPC | PersonalComputer/VHDControler.v | 9,191 | module MODULE1(
input clk,
input VAR3,
output VAR11,
input[8:0] VAR4,
input VAR9,
input[31:0] VAR8,
input VAR10,
input VAR2,
input VAR6,
input VAR12,
output reg [31:0] VAR5,
output reg VAR7
);
reg[31:0] VAR13;
reg[15:0] VAR1;
reg[15:0] ready;
reg[5:0] state; | gpl-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_019.v | 1,387 | module MODULE2 (
VAR3,
VAR2
);
input [31:0] VAR3;
output [31:0]
VAR2;
wire [31:0]
VAR8,
VAR1,
VAR5,
VAR6,
VAR7,
VAR9;
assign VAR8 = VAR3;
assign VAR9 = VAR7 << 2;
assign VAR7 = VAR6 - VAR8;
assign VAR6 = VAR5 << 6;
assign VAR1 = VAR8 << 2;
assign VAR5 = VAR8 + VAR1;
assign VAR2 = VAR9;
endmodule
module MODULE1(
VAR3,
V... | mit |
AloriumTechnology/XLR8Pong | extras/rtl/vid_timer16.v | 4,036 | module MODULE1(clk,
VAR14,
VAR1,
VAR3,
VAR12,
VAR15
);
input clk;
input VAR14;
output reg VAR1;
output VAR3;
output reg[8:0] VAR12;
output reg[8:0] VAR15;
parameter VAR6 = 1016;
parameter VAR11 = 507;
parameter VAR10 = 1016-75;
parameter VAR9 = 507-75;
reg[10:0] VAR2;
reg[11:0] VAR17;
wire VAR8;
wire VAR5;
reg[7:0] VAR... | lgpl-3.0 |
HarmonInstruments/hififo | hdl/pcie_tx.v | 9,045 | module MODULE3
(
input VAR78,
input reset,
input [15:0] VAR54,
input [31:0] VAR41,
input [31:0] VAR10,
input VAR6,
output reg VAR25,
input VAR50,
output reg VAR69,
input [63:0] VAR51,
input [7:0] VAR72,
input VAR14,
output VAR79, input [63:0] VAR39,
input [63:0] VAR34,
input VAR11,
input VAR4,
output [63:0] VAR22,
outp... | gpl-3.0 |
LordRafa/Sobel-FPGA | Project_Without_Cache/MisArchivos/vga_serial.v | 1,133 | module MODULE1 (
input [23:0] VAR1,
input VAR4,
input VAR6,
input VAR7,
input VAR15,
output reg [7:0] VAR5,
output VAR11,
output VAR3,
output VAR8
);
reg VAR2;
reg VAR13;
reg VAR10;
reg VAR16;
always @(posedge VAR15) begin
VAR2 <= VAR6;
VAR13 <= VAR2;
VAR16 <= VAR7;
VAR10 <= VAR4;
end
reg [1:0] VAR12;
wire VAR9 = (VAR2... | gpl-2.0 |
HarmonInstruments/verilog | sincos/cos_int.v | 2,247 | module MODULE1
(
input VAR3,
input [13:0] VAR17,
input VAR50,
input [34:0] VAR60,
output signed [VAR21-1:0] VAR53
);
parameter VAR21 = 23;
reg [2:0] VAR57 = 0;
reg [21:0] VAR51 = 0;
wire [47:0] VAR28;
reg [13:0] VAR37 = 0;
always @ (posedge VAR3) begin
VAR37 <= VAR17;
VAR57 <= {VAR57[1:0], ~VAR50};
VAR51 <= VAR60[34:13... | gpl-3.0 |
alexforencich/verilog-ethernet | example/520N_MX/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v | 10,175 | module MODULE1 (
input wire VAR72,
input wire VAR2,
input wire VAR79,
output wire [3:0] VAR22,
input wire [3:0] VAR27,
output wire VAR87,
output wire VAR71,
input wire [63:0] VAR69,
input wire [7:0] VAR59,
output wire VAR34,
output wire VAR46,
output wire [63:0] VAR7,
output wire [7:0] VAR28,
output wire VAR14,
output ... | mit |
skatpgusskat/KoreaUnivHomework_2015_1 | Computer Architecture/Homework/Lab09/regfile_beh.v | 2,061 | module MODULE1(VAR4, VAR1, VAR9, VAR8, VAR7, VAR5, clk, VAR3, VAR2);
input [4:0] VAR4,VAR9, VAR7;
input [31:0] VAR5;
input clk, VAR3, VAR2;
output [31:0] VAR1, VAR8;
reg [31:0] VAR1, VAR8;
reg [31:0] register [31:0];
integer VAR6;
begin
end
begin
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dff_p/sky130_fd_sc_hd__udp_dff_p.blackbox.v | 1,202 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR3;
endmodule | apache-2.0 |
bargei/NoC264 | NoC264_3x3/vga_driver.v | 3,533 | module MODULE1 (
VAR5,VAR9,VAR22,
VAR27,VAR24,request,
VAR18,VAR3,VAR21,VAR6,VAR8,VAR2,VAR13,
VAR19,VAR7);
input [9:0] VAR5,VAR9,VAR22;
output [9:0] VAR27;
output [9:0] VAR24;
output request;
output [9:0] VAR18, VAR3, VAR21;
output VAR6, VAR8, VAR2, VAR13;
input VAR19, VAR7;
parameter VAR4 = 16;
parameter VAR1 = 96;
pa... | mit |
Murailab-arch/magukara | cores/measure/rtl/measure.v | 25,643 | module MODULE1 (
input VAR93,
input VAR85,
input VAR38,
input VAR68,
output [7:0] VAR75,
output VAR92,
input [7:0] VAR71,
input VAR28,
input VAR72,
input VAR108,
output [7:0] VAR152,
output VAR142,
input [7:0] VAR130,
input VAR4,
input VAR5,
input VAR34,
output [7:0] VAR16,
output VAR13,
input [7:0] VAR53,
input VAR78,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf.functional.v | 1,257 | module MODULE1 (
VAR4,
VAR3
);
output VAR4;
input VAR3;
wire VAR5;
buf VAR2 (VAR5, VAR3 );
buf VAR1 (VAR4 , VAR5 );
endmodule | apache-2.0 |
aj-michael/Digital-Systems | Lab2-Part2-Controller7SegmentDisplayKeypadScanner/Lab2Part1Fall2015AJM.v | 1,455 | module MODULE1(VAR21, VAR27, VAR5, VAR13, VAR2, VAR19, VAR4, VAR28, VAR6);
input [3:0] VAR21;
input VAR27, VAR5, VAR13;
output [3:0] VAR2;
output VAR19, VAR4;
output [7:0] VAR28;
output [3:0] VAR6;
wire VAR11, VAR29;
wire VAR33, VAR38;
wire [3:0] VAR10;
wire [3:0] VAR12;
wire [7:0] VAR23;
wire [7:0] VAR20;
wire [7:0] V... | mit |
hanw/sonic-lite | hw/verilog/traffic_controller/shiftreg_data.v | 4,691 | module MODULE1 (
VAR8,
VAR7,
VAR12,
VAR5,
VAR13,
VAR1);
input VAR8;
input VAR7;
input VAR12;
input [63:0] VAR5;
output [63:0] VAR13;
output [63:0] VAR1;
wire [63:0] VAR11;
wire [63:0] VAR4;
wire [63:0] VAR1 = VAR11[63:0];
wire [63:0] VAR13 = VAR4[63:0];
VAR10 VAR15 (
.VAR7 (VAR7),
.VAR8 (VAR8),
.VAR12 (VAR12),
.VAR5 (V... | mit |
ngoel9/progressive-learning-platform | reference/hw/verilog/cpu_mem.v | 2,233 | module MODULE1(rst, clk, VAR21, VAR14, VAR15, VAR16,
VAR10, VAR12, VAR13, VAR8, VAR1,
VAR11, VAR7, VAR18, VAR3, VAR6,
VAR19, VAR4, VAR5, VAR17, VAR20,
VAR2);
input rst, clk, VAR21;
input VAR14;
input [1:0] VAR15;
input [1:0] VAR16;
input [31:0] VAR10;
input [31:0] VAR12;
input [4:0] VAR13;
input [31:0] VAR8;
input [4:0... | gpl-3.0 |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/mig_wrap_mig_7series_0_0_mig.v | 73,489 | module MODULE1 #
(
parameter VAR407 = 3,
parameter VAR63 = 1,
parameter VAR115 = 10,
parameter VAR396 = 1,
parameter VAR113 = 1,
parameter VAR404 = 1,
parameter VAR122 = 5,
parameter VAR64 = 6,
parameter VAR35 = 8,
parameter VAR156 = 8,
parameter VAR410 = 64,
parameter VAR361 = 8,
parameter VAR429 = 3,
parameter VAR234... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_narrowed.v | 2,272 | module MODULE1
, parameter VAR11(VAR20 )
, parameter VAR11(VAR6 )
, parameter VAR16 = 1
, parameter VAR14 = 0
)
( input VAR5
, input VAR12
, input [VAR21-1:0] VAR8
, input VAR15
, output VAR17
, output VAR3
, output [VAR6-1:0] VAR7
, input VAR2
);
logic [VAR21-1:0] VAR10;
logic VAR19;
VAR4 #(.VAR21(VAR21)
,.VAR20(VAR20... | bsd-3-clause |
alankarkotwal/lc-3b-processor | memory.v | 1,489 | module MODULE1(address,in,out,write,clk);
input [7:0] in;
input clk,write;
input [14:0] address;
output [7:0] out;
reg [7:0] VAR7 [0:255];
reg [14:0] VAR3;
always @(negedge clk)
begin
if(write ==1'b0)
begin
VAR7[address] <= in;
VAR3 <= address;
end
end
assign out = VAR7[VAR3];
endmodule
module MODULE2(address, write,cl... | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_01/02 verilog/ultrasonido_modulo_1/Periferico/j1soc.v | 2,164 | module MODULE1#(
parameter VAR7 = "../VAR2/VAR5/VAR16.VAR4" )(
VAR11, VAR20, VAR1, [15:0]VAR21
VAR3, VAR15
);
input VAR3, VAR15, VAR11;
output VAR20, VAR1, [15:0]VAR21;
output VAR1;
wire VAR17; wire VAR14; wire [15:0] VAR18; reg [15:0] VAR12; wire [15:0] VAR24;
reg [1:4]VAR22; wire [15:0]VAR6;
VAR16 #(VAR7) VAR9(VAR3, ... | gpl-3.0 |
gtaylormb/fpga_nes | hw/src/hci/hci.v | 23,499 | module MODULE1
(
input wire clk, input wire rst, input wire VAR85, input wire VAR64, input wire [ 7:0] VAR42, input wire [ 7:0] VAR47, input wire [ 7:0] VAR15, output wire VAR28, output wire VAR83, output reg VAR4, output wire [15:0] VAR56, output reg [ 7:0] VAR53, output reg [ 3:0] VAR19, output reg [ 7:0] VAR43, outp... | bsd-2-clause |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/timer.v | 1,240 | module MODULE1 #
(
parameter VAR2 = 64,
parameter VAR14 = 0,
parameter VAR3 = 2
)
(
input clk,
input VAR6,
input VAR11,
input [VAR3-1:0] VAR10, input [VAR2-1:0] VAR9,
input VAR8,
input VAR1,
input [VAR2/8-1:0] VAR5,
output VAR4,
output [VAR2-1:0] VAR12,
output VAR13
);
reg [VAR2-1:0] counter;
reg [VAR2-1:0] VAR15;
reg ... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_017.v | 1,533 | module MODULE1 (
VAR13,
VAR4
);
input [31:0] VAR13;
output [31:0]
VAR4;
wire [31:0]
VAR6,
VAR8,
VAR9,
VAR11,
VAR14,
VAR5,
VAR12,
VAR10,
VAR2;
assign VAR6 = VAR13;
assign VAR14 = VAR11 - VAR6;
assign VAR11 = VAR6 << 4;
assign VAR5 = VAR9 << 3;
assign VAR12 = VAR9 + VAR5;
assign VAR9 = VAR8 - VAR6;
assign VAR8 = VAR6 << ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlrtp/sky130_fd_sc_lp__srdlrtp.functional.pp.v | 1,983 | module MODULE1 (
VAR14 ,
VAR13,
VAR15 ,
VAR8 ,
VAR11,
VAR16 ,
VAR4 ,
VAR1 ,
VAR3 ,
VAR17
);
output VAR14 ;
input VAR13;
input VAR15 ;
input VAR8 ;
input VAR11;
input VAR16 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR17 ;
wire VAR5;
wire VAR6;
not VAR12 (VAR6 , VAR13 );
VAR9 VAR2 VAR7 (VAR5 , VAR15, VAR8, VAR6, VA... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/dbg_interface/dbg_top.v | 50,172 | module MODULE1(
VAR103, VAR43, VAR3, VAR149, VAR33, VAR54,
VAR81, VAR19, VAR140, VAR111, VAR44, VAR125,
VAR9, VAR193, VAR194, VAR38, VAR35,
VAR160, VAR89, VAR112, VAR150, VAR163, VAR115,
VAR120, VAR173,
VAR136, VAR210, VAR96, VAR50, VAR6, VAR175,
VAR108, VAR202, VAR18, VAR168
);
parameter VAR94 = 1;
input VAR103; input... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sgb/dac_buf.v | 9,176 | module MODULE1 (
VAR38,
VAR23,
VAR4,
VAR13,
VAR11,
VAR19);
input VAR38;
input [7:0] VAR23;
input [8:0] VAR4;
input [10:0] VAR13;
input VAR11;
output [31:0] VAR19;
tri1 VAR38;
tri0 VAR11;
wire [31:0] VAR30;
wire [31:0] VAR19 = VAR30[31:0];
VAR35 VAR53 (
.VAR33 (VAR13),
.VAR60 (VAR4),
.VAR5 (VAR38),
.VAR25 (VAR23),
.VAR2... | gpl-2.0 |
alexforencich/verilog-axis | rtl/axis_frame_len.v | 3,292 | module MODULE1 #
(
parameter VAR5 = 64,
parameter VAR15 = (VAR5>8),
parameter VAR14 = ((VAR5+7)/8),
parameter VAR4 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR14-1:0] VAR10,
input wire VAR7,
input wire VAR6,
input wire VAR16,
output wire [VAR4-1:0] VAR11,
output wire VAR13
);
reg [VAR4-1:0] VAR1 = 0, VAR3;
... | mit |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_example_top_17.v | 7,205 | module MODULE1 (
VAR57,
VAR45,
VAR36,
VAR51,
VAR21,
VAR9,
VAR63,
VAR4,
VAR52,
VAR54,
VAR30,
VAR38,
VAR60,
VAR20,
VAR47,
VAR23,
VAR32,
VAR72,
VAR7,
VAR31,
VAR26
)
;
output [ 12: 0] VAR36;
output [ 2: 0] VAR51;
output VAR21;
output [ 0: 0] VAR9;
inout [ 0: 0] VAR63;
inout [ 0: 0] VAR4;
output [ 0: 0] VAR52;
output [ 3: 0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a221oi/sky130_fd_sc_hdll__a221oi_1.v | 2,473 | module MODULE2 (
VAR4 ,
VAR12 ,
VAR5 ,
VAR6 ,
VAR11 ,
VAR8 ,
VAR9,
VAR2,
VAR3 ,
VAR7
);
output VAR4 ;
input VAR12 ;
input VAR5 ;
input VAR6 ;
input VAR11 ;
input VAR8 ;
input VAR9;
input VAR2;
input VAR3 ;
input VAR7 ;
VAR1 VAR10 (
.VAR4(VAR4),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR9(... | apache-2.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/Loop_loop_height_g8j.v | 1,187 | module MODULE1 (
VAR3, VAR6, VAR5, clk);
parameter VAR1 = 8;
parameter VAR4 = 8;
parameter VAR7 = 256;
input[VAR4-1:0] VAR3;
input VAR6;
output reg[VAR1-1:0] VAR5;
input clk;
reg [VAR1-1:0] VAR2[0:VAR7-1];
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41o/sky130_fd_sc_ms__a41o.functional.pp.v | 2,058 | module MODULE1 (
VAR17 ,
VAR2 ,
VAR10 ,
VAR13 ,
VAR6 ,
VAR5 ,
VAR11,
VAR7,
VAR8 ,
VAR16
);
output VAR17 ;
input VAR2 ;
input VAR10 ;
input VAR13 ;
input VAR6 ;
input VAR5 ;
input VAR11;
input VAR7;
input VAR8 ;
input VAR16 ;
wire VAR12 ;
wire VAR18 ;
wire VAR14;
and VAR9 (VAR12 , VAR2, VAR10, VAR13, VAR6 );
or VAR15 (V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.functional.pp.v | 2,125 | module MODULE1( VAR8, VAR15, VAR2, VAR27, VAR22, VAR9, VAR23, VAR1 );
input VAR22, VAR9, VAR27, VAR2, VAR15;
inout VAR23, VAR1;
output VAR8;
wire VAR21;
not VAR20( VAR21, VAR22 );
wire VAR16;
not VAR6( VAR16, VAR27 );
wire VAR26;
not VAR11( VAR26, VAR15 );
wire VAR10;
and VAR13( VAR10, VAR21, VAR16, VAR26 );
wire VAR3;... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_bypass.v | 1,121 | module MODULE1
, parameter logic VAR14 = 0
)
(input [VAR12-1:0] VAR7 , input VAR2 , output logic VAR15
, output logic [VAR12-1:0] VAR5 , output logic VAR9 , input VAR11
, output logic [VAR12-1:0] VAR3 , output logic VAR13 , input VAR4
, input [VAR12-1:0] VAR10 , input VAR6 , output VAR8 );
wire VAR1 = VAR14 ? VAR2 : (V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41oi/sky130_fd_sc_ls__a41oi.pp.symbol.v | 1,396 | module MODULE1 (
input VAR9 ,
input VAR2 ,
input VAR8 ,
input VAR7 ,
input VAR5 ,
output VAR4 ,
input VAR6 ,
input VAR10,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
CospanDesign/sdio-device | rtl/function/sdio_function_template.v | 1,507 | module MODULE1 (
input clk,
input rst
);
localparam VAR1 = 32'h00000000;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311oi/sky130_fd_sc_lp__a311oi_0.v | 2,450 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR5 ,
VAR8 ,
VAR3 ,
VAR7 ,
VAR9,
VAR1,
VAR11 ,
VAR2
);
output VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR7 ;
input VAR9;
input VAR1;
input VAR11 ;
input VAR2 ;
VAR12 VAR10 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9)... | apache-2.0 |
tmolteno/TART | hardware/FPGA/fifo/fifo15m.v | 4,054 | module MODULE1 (
VAR3,
VAR4,
VAR1,
VAR25, VAR21, VAR28,
VAR11,
VAR7,
VAR13,
VAR19
);
parameter VAR8 = 8'd16;
input VAR3;
input VAR4;
input VAR1;
input VAR25;
input VAR21;
input [VAR8 - 1:0] VAR28;
output [VAR8 - 1:0] VAR11;
output VAR7;
output VAR13;
output VAR19;
reg [3:0] VAR14 = 4'h1;
reg [3:0] VAR22 = 4'h1;
wire [3... | lgpl-3.0 |
zeldin/iceGDROM | fpga/source/cdda/digital_sound_output.v | 2,405 | module MODULE1 (
input clk,
input rst,
input VAR6,
input[15:0] VAR12,
input[15:0] VAR22,
output VAR24,
output VAR19,
output VAR27,
output VAR16
);
parameter VAR26 = 33868800;
localparam VAR11 = (VAR26 / 44100 / 64 / 2);
function integer VAR17;
input integer VAR10;
begin
VAR10 = VAR10-1;
for (VAR17=0; VAR10>0; VAR17=VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211ai/sky130_fd_sc_hd__o211ai_4.v | 2,361 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR10 ,
VAR3 ,
VAR6 ,
VAR1,
VAR4,
VAR8 ,
VAR9
);
output VAR7 ;
input VAR5 ;
input VAR10 ;
input VAR3 ;
input VAR6 ;
input VAR1;
input VAR4;
input VAR8 ;
input VAR9 ;
VAR2 VAR11 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311o/sky130_fd_sc_hd__a311o_4.v | 2,437 | module MODULE2 (
VAR2 ,
VAR3 ,
VAR1 ,
VAR9 ,
VAR8 ,
VAR11 ,
VAR5,
VAR6,
VAR7 ,
VAR10
);
output VAR2 ;
input VAR3 ;
input VAR1 ;
input VAR9 ;
input VAR8 ;
input VAR11 ;
input VAR5;
input VAR6;
input VAR7 ;
input VAR10 ;
VAR12 VAR4 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR5(VA... | apache-2.0 |
freecores/zet86 | impl/virtex4-ml403ep/mem/zbt_cntrl.v | 2,847 | module MODULE1 (
output reg [2:0] VAR18,
output VAR19,
input VAR17,
input VAR13,
input [15:0] VAR7,
output reg [15:0] VAR3,
input [19:1] VAR5,
input VAR15,
input [ 1:0] VAR16,
input VAR12,
input VAR6,
output reg VAR14,
output VAR2,
output reg [20:0] VAR8,
inout [31:0] VAR20,
output reg VAR10,
output reg [ 3:0] VAR4,
ou... | gpl-3.0 |
masc-ucsc/cmpe220fall16 | rtl/arbl2tlb.v | 11,338 | module MODULE1(
input clk
,input reset
,input logic VAR85
,output logic VAR39
,input VAR19 VAR57
,output logic VAR21
,input logic VAR10
,output VAR97 VAR103
,input VAR63
,output VAR83
,input VAR93 VAR9
,input logic VAR33
,output logic VAR28
,input VAR68 VAR92
,output logic VAR14
,input logic VAR13
,output VAR80 VAR48
,... | apache-2.0 |
polysome/hydra | implementation/smart_sche_unit.v | 5,673 | module MODULE1 ( VAR1 , VAR24 , VAR14 , VAR38 ,
VAR2 , VAR29 , VAR32 , VAR8 , VAR26 , VAR6 ,
clk , VAR50 , VAR40 , VAR23 , VAR9 ,
VAR33 , VAR45 , VAR16
);
parameter VAR37 = 31;
parameter VAR20 = 5'h7;
parameter VAR17 = 5'h9;
parameter VAR27 = 5'ha;
parameter VAR41 = 1'b0;
parameter VAR46 = 1'b1;
output [VAR37-1:0] VAR1... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_23.v | 18,386 | module MODULE2 (
clk,
reset,
VAR61,
VAR69,
VAR24,
VAR70,
VAR68
);
parameter VAR72 = 18;
parameter VAR139 = 23;
parameter VAR47 = 12;
localparam VAR55 = 29;
input clk;
input reset;
input VAR61;
input VAR69;
input [VAR72-1:0] VAR24; output VAR70;
output [VAR72-1:0] VAR68;
localparam VAR13 = 18; localparam VAR111 = 36; lo... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probe_p/sky130_fd_sc_hd__probe_p.functional.pp.v | 1,788 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR3,
VAR12 ,
VAR8 ,
VAR4
);
output VAR7 ;
input VAR9 ;
input VAR3;
input VAR12 ;
input VAR8 ;
input VAR4;
wire VAR5 ;
wire VAR6;
buf VAR10 (VAR5 , VAR9 );
VAR2 VAR11 (VAR6, VAR5, VAR4, VAR3);
buf VAR1 (VAR7 , VAR6 );
endmodule | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/acl_fp_acos.v | 1,346 | module MODULE1(VAR10, VAR13, enable, VAR5, VAR8);
input VAR10, VAR13, enable;
input [31:0] VAR5;
output [31:0] VAR8;
VAR2 VAR11(
.VAR4(VAR10),
.reset(~VAR13),
.enable(enable),
.VAR9(VAR5[31]),
.VAR7(VAR5[30:23]),
.VAR3(VAR5[22:0]),
.VAR1(VAR8[31]),
.VAR6(VAR8[30:23]),
.VAR12(VAR8[22:0])
);
endmodule | mit |
kyzhai/NUNY | src/hardware/bg5.v | 6,444 | module MODULE1 (
address,
VAR12,
VAR50);
input [13:0] address;
input VAR12;
output [11:0] VAR50;
tri1 VAR12;
wire [11:0] VAR20;
wire [11:0] VAR50 = VAR20[11:0];
VAR9 VAR28 (
.VAR38 (address),
.VAR26 (VAR12),
.VAR3 (VAR20),
.VAR15 (1'b0),
.VAR6 (1'b0),
.VAR1 (1'b1),
.VAR42 (1'b0),
.VAR21 (1'b0),
.VAR31 (1'b1),
.VAR5 (1'... | gpl-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/8-hazards/Hazard_unit.v | 3,272 | module MODULE1(
input wire [4:0] VAR7, input wire [4:0] VAR10, input wire [4:0] VAR24,
input wire [4:0] VAR17,
input wire VAR8,
input wire VAR22,
output reg [1:0] VAR26,
output reg [1:0] VAR6,
input wire [4:0] VAR25, input wire [4:0] VAR1, input wire VAR3, output reg VAR12,
output reg VAR13,
output reg VAR5,
input wire... | gpl-3.0 |
dtysky/LD3320_AXI | src/LIST/LIST_stub.v | 1,334 | module MODULE1(VAR5, VAR3, VAR7, VAR4, VAR6, VAR2, VAR1)
;
input VAR5;
input [0:0]VAR3;
input [7:0]VAR7;
input [7:0]VAR4;
input VAR6;
input [7:0]VAR2;
output [7:0]VAR1;
endmodule | mit |
UCR-CS179-SUMMER2014/NES_FPGA | source/etc/hardware/VGA/vga_stripes.v | 1,174 | module MODULE1(
VAR10,
VAR8,
VAR5,
VAR1,
VAR9,
VAR2,
VAR4
);
input VAR10;
input [9:0] VAR8;
input [9:0] VAR5;
output [7:0] VAR1;
output [7:0] VAR9;
output [7:0] VAR2;
input [17:0] VAR4;
reg [7:0] VAR3, VAR7, VAR6;
assign VAR1 = VAR3;
assign VAR9 = VAR7;
assign VAR2 = VAR6;
always @ (VAR10, VAR5)
begin
VAR3 <= 8'b000000... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvp/sky130_fd_sc_lp__einvp.behavioral.v | 1,302 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR5
);
output VAR1 ;
input VAR2 ;
input VAR5;
supply1 VAR8;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR3 ;
notif1 VAR4 (VAR1 , VAR2, VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_pwrgood_pp_g/sky130_fd_sc_ms__udp_pwrgood_pp_g.blackbox.v | 1,251 | module MODULE1 (
VAR2,
VAR1 ,
VAR3
);
output VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/up_tdd_cntrl.v | 16,657 | module MODULE1 #(
parameter VAR58 = 0) (
input clk,
input rst,
output VAR28,
output VAR37,
output VAR53,
output VAR70,
output VAR30,
output VAR62,
output [ 7:0] VAR60,
output [23:0] VAR90,
output [23:0] VAR64,
output VAR87,
output [23:0] VAR76,
output [23:0] VAR50,
output [23:0] VAR4,
output [23:0] VAR63,
output [23:0]... | mit |
MeshSr/onetswitch30 | ons30-app52-ref_ofshw/vivado/onets_7030_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/core/small_fifo.v | 2,385 | module MODULE1
parameter VAR9 = 3,
parameter VAR1 = 2**VAR9 - 1
)
(
input [VAR10-1:0] din, input VAR4,
input VAR3,
output reg [VAR10-1:0] dout, output VAR8,
output VAR2,
output VAR6,
output VAR5,
input reset,
input clk
);
localparam VAR11 = 2 ** VAR9;
reg [VAR10-1:0] VAR13 [VAR11 - 1 : 0];
reg [VAR9 - 1 : 0] VAR12;
reg... | lgpl-2.1 |
bnossum/uart_ice40 | src/icestickuart.v | 4,066 | module MODULE1
( input VAR14, VAR13,
output VAR8, VAR6, VAR36
);
wire [7:0] VAR25;
wire clk,VAR5,VAR2,VAR23,VAR41;
reg [4:0] VAR34;
wire VAR15; wire [7:0] VAR37; wire [1:0] VAR9; wire VAR42; wire VAR3; assign VAR5 = 1'b1;
VAR29 VAR40
( .VAR30(VAR13), .VAR20(clk));
VAR43 #( .VAR27(6'b011111)) VAR12 ( .VAR30(VAR8), .VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrbp/sky130_fd_sc_ms__sdfrbp.behavioral.pp.v | 3,037 | module MODULE1 (
VAR7 ,
VAR19 ,
VAR20 ,
VAR16 ,
VAR14 ,
VAR24 ,
VAR2,
VAR25 ,
VAR30 ,
VAR28 ,
VAR11
);
output VAR7 ;
output VAR19 ;
input VAR20 ;
input VAR16 ;
input VAR14 ;
input VAR24 ;
input VAR2;
input VAR25 ;
input VAR30 ;
input VAR28 ;
input VAR11 ;
wire VAR10 ;
wire VAR5 ;
wire VAR15 ;
reg VAR1 ;
wire VAR3 ;
wir... | apache-2.0 |
CeesWolfs/ceespu | src/ceespu_execute.v | 3,362 | module MODULE1(
input VAR33,
input VAR1,
input [3:0] VAR9,
input VAR5,
input [1:0] VAR3,
input VAR42,
input VAR4,
input [2:0] VAR32,
input [31:0] VAR27,
input [31:0] VAR38,
input [31:0] VAR7,
input [1:0] VAR23,
input [4:0] VAR15,
input VAR6,
input VAR37,
input [2:0] VAR30,
input [13:0] VAR39,
input [13:0] VAR11,
output... | mit |
EmbeddedANT/ALTERA_DE0-Nano | DE0Nano_Switch/DE0Nano_Switch.v | 3,665 | module MODULE1(
VAR1,
VAR13,
VAR7
);
parameter VAR5 =11'b10000001000;
parameter VAR10 =11'b01000010001;
parameter VAR12 =11'b00100100010;
parameter VAR8 =11'b00011000011;
parameter VAR18 =11'b00100100100;
parameter VAR14 =11'b01000010101;
input VAR1;
output [7:0]VAR13;
input [3:0]VAR7;
wire VAR6;
reg [10:0]VAR11;
reg [... | gpl-3.0 |
chipsalliance/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/ffs_map.v | 3,541 | module \VAR15 (VAR25, VAR31, VAR24, VAR1, VAR14, VAR10);
input VAR25;
input VAR31;
input VAR24;
input VAR1;
input VAR14;
output VAR10;
VAR26 VAR13 (.VAR10(VAR10), .VAR14(VAR14), .VAR25(VAR25), .VAR1(VAR1), .VAR24(VAR24), .VAR31(VAR31));
endmodule
module \VAR7 (VAR25, VAR31, VAR24, VAR1, VAR14, VAR10);
input VAR25;
inpu... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/hyperram_ctl.v | 14,368 | module MODULE1(
input wire VAR12,
input wire VAR64,
output reg VAR60,
input wire [23:0] VAR20, input wire [15:0] VAR62,
output wire [15:0] VAR55,
output wire VAR53, input wire [2:0] VAR76,
input wire VAR13, output wire VAR65,
input wire [7:0] VAR29,
output reg [7:0] VAR70,
output reg VAR68,
input wire VAR46,
output reg... | gpl-3.0 |
sergev/vak-opensource | hardware/verilog/uart/uart.v | 19,752 | module MODULE1 (
VAR87,
VAR70,
VAR104,
VAR23,
VAR118,
VAR41,
VAR33,
VAR19,
VAR60,
VAR6,
VAR78,
VAR73,
VAR29,
VAR58,
VAR48,
VAR25
);
parameter VAR108 = 6'h09; parameter VAR111 = 6'h0A; parameter VAR79 = 6'h0B; parameter VAR121 = 6'h0C;
input VAR87;
input VAR70;
input[5:0] VAR104;
input[7:0] VAR23;
output[7:0] VAR118;
wi... | apache-2.0 |
iamllama/EE2020 | ee2020.srcs/sources_1/new/sine.v | 1,168 | module MODULE1(
input VAR1,
input[31:0] VAR10,
input signed[15:0] VAR8,
input signed[15:0] VAR11,
output[11:0] VAR7
);
wire VAR12;
reg VAR6 = 1;
wire signed[16:0] VAR15;
wire[23:0] VAR3 = (VAR10*83886)/10000;
VAR13 VAR2(VAR1, VAR6, VAR3, VAR12, VAR15);
reg signed[16:0] VAR4 = 16'b0;
reg signed[16:0] VAR9 = 16'b0;
reg s... | gpl-3.0 |
zhijian-liu/mips-cpu | src/cpu/latch/latch_mem_wb.v | 2,063 | module MODULE1 (
input VAR5 ,
input reset ,
input [ 5:0] VAR7 ,
input VAR4 ,
output reg VAR18 ,
input [ 4:0] VAR20 ,
output reg [ 4:0] VAR19 ,
input [31:0] VAR11 ,
output reg [31:0] VAR16 ,
input VAR12,
output reg VAR10 ,
input [31:0] VAR13 ,
output reg [31:0] VAR1 ,
input VAR15,
output reg VAR2 ,
input [31:0] VAR3 ,
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor2/sky130_fd_sc_ls__xnor2.pp.symbol.v | 1,304 | module MODULE1 (
input VAR5 ,
input VAR2 ,
output VAR3 ,
input VAR1 ,
input VAR7,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor3/sky130_fd_sc_ms__xnor3.pp.symbol.v | 1,295 | module MODULE1 (
input VAR3 ,
input VAR4 ,
input VAR1 ,
output VAR5 ,
input VAR6 ,
input VAR7,
input VAR8,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fah/sky130_fd_sc_hs__fah_1.v | 2,156 | module MODULE1 (
VAR9,
VAR2 ,
VAR7 ,
VAR6 ,
VAR4 ,
VAR5,
VAR3
);
output VAR9;
output VAR2 ;
input VAR7 ;
input VAR6 ;
input VAR4 ;
input VAR5;
input VAR3;
VAR8 VAR1 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR9,
VAR2 ,
VAR7 ,
VAR6 ,
VAR4
)... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_avalon_master_171/synth/ghrd_10as066n2_fpga_m_altera_jtag_avalon_master_171_wqhllki.v | 25,719 | module MODULE1 #(
parameter VAR25 = 0,
parameter VAR41 = 50000,
parameter VAR45 = 2
) (
input wire VAR21, input wire VAR14, output wire [31:0] VAR47, input wire [31:0] VAR22, output wire VAR35, output wire VAR30, output wire [31:0] VAR20, input wire VAR38, input wire VAR6, output wire [3:0] VAR43, output wire VAR33 );
... | mit |
GLADICOS/SPACEWIRESYSTEMC | rtl/DEBUG_VERILOG/debounce.v | 1,991 | module MODULE1(
input VAR5,
input VAR4,
output reg VAR2,
output reg VAR1
);
reg VAR3;
reg [15:0] counter;
always@(*)
begin
VAR2 = 1'b1;
if(VAR5)
begin
if(VAR3)
VAR2 = 1'b0;
end
else if(!VAR5)
begin
if(VAR3)
VAR2 = 1'b0;
end
end
always@(posedge VAR5)
begin
if(VAR4)
begin
VAR3 <= 1'b0;
counter <= 16'd0;
VAR1 <= 1'b0;
end... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufkapwr/sky130_fd_sc_lp__bufkapwr.behavioral.v | 1,392 | module MODULE1 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR2 ;
supply0 VAR7 ;
supply1 VAR6;
supply1 VAR5 ;
supply0 VAR4 ;
wire VAR1;
buf VAR10 (VAR1, VAR3 );
buf VAR9 (VAR8 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4bb/sky130_fd_sc_ms__nor4bb.pp.blackbox.v | 1,351 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR1 ,
VAR6 ,
VAR5 ,
VAR4,
VAR2,
VAR9 ,
VAR7
);
output VAR3 ;
input VAR8 ;
input VAR1 ;
input VAR6 ;
input VAR5 ;
input VAR4;
input VAR2;
input VAR9 ;
input VAR7 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/fabric/logicBlock.v | 3,787 | module MODULE1(
VAR10, VAR19, VAR12, VAR3, VAR11, VAR4,
VAR16,
VAR1, out,
VAR8
);
input [31:0] VAR10;
input [31:0] VAR12;
input [31:0] VAR19; input [31:0] VAR3; input [31:0] VAR11; input VAR4; input [2:0] VAR1; input VAR16;
output out;
output VAR8;
reg out;
wire VAR8;
wire [31:0] VAR14 = VAR10 & VAR19;
wire [31:0] VAR2... | mit |
fbalakirev/red-pitaya-notes | cores/axis_averager_v1_0/axis_averager.v | 2,789 | module MODULE1 #
(
parameter integer VAR13 = 32,
parameter integer VAR5 = 16,
parameter VAR31 = "VAR22"
)
(
input wire VAR16,
input wire VAR4,
input wire [VAR5-1:0] VAR7,
input wire [VAR5-1:0] VAR26,
output wire VAR11,
input wire [VAR13-1:0] VAR3,
input wire VAR25,
input wire VAR30,
output wire [VAR13-1:0] VAR6,
output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.v | 2,463 | module MODULE1 (
VAR2 ,
VAR9,
VAR5,
VAR11 ,
VAR3 ,
VAR7,
VAR10,
VAR8 ,
VAR1
);
output VAR2 ;
input VAR9;
input VAR5;
input VAR11 ;
input VAR3 ;
input VAR7;
input VAR10;
input VAR8 ;
input VAR1 ;
VAR4 VAR6 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR1... | apache-2.0 |
praveendath92/securePUF | source/puf_files/pufInputNetwork.v | 1,852 | module MODULE1 #(parameter VAR4 = 32)
(input wire [VAR4-1:0] VAR5,
output wire [VAR4-1:0] VAR8);
parameter VAR2 = VAR4;
wire [VAR4:1] VAR3;
wire [VAR4:1] VAR6;
assign VAR3[VAR4:1] = VAR5[VAR4-1:0];
assign VAR8[VAR4-1:0] = VAR6[VAR4:1];
assign VAR6[(VAR4+2)/2] = VAR3[1];
genvar VAR7;
generate
for (VAR7 = 2; VAR7 < VAR2;... | gpl-2.0 |
P3Stor/P3Stor | DDR3/phy/phy_init.v | 123,761 | module MODULE1 #
(
parameter VAR218 = 100,
parameter VAR246 = 2, parameter VAR92 = 3333, parameter VAR200 = 2,
parameter VAR235 = 10,
parameter VAR110 = 1, parameter VAR126 = 64,
parameter VAR241 = 14,
parameter VAR139 = 1,
parameter VAR137 = 1, parameter VAR249 = "VAR209",
parameter VAR112 = "VAR65",
parameter VAR232 ... | gpl-2.0 |
hydai/Verilog-Practice | DigitalDesign/SYN/hw5/datapath.v | 5,087 | module MODULE1 (
output reg VAR2,
output reg VAR36,
output reg VAR29,
output reg VAR16,
output [15:0] VAR17,
output [15:0] VAR35,
output [15:0] VAR21,
output [15:0] VAR15,
output [15:0] VAR3,
output [15:0] VAR41,
output [15:0] VAR19,
output [15:0] VAR23,
output [15:0] VAR32,
output [15:0] VAR39,
output [15:0] VAR13,
ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21bai/sky130_fd_sc_hd__o21bai.blackbox.v | 1,389 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR6 ,
VAR3
);
output VAR8 ;
input VAR5 ;
input VAR6 ;
input VAR3;
supply1 VAR2;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3/sky130_fd_sc_hd__and3.pp.blackbox.v | 1,287 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR4 ,
VAR5 ,
VAR8,
VAR2,
VAR3 ,
VAR1
);
output VAR6 ;
input VAR7 ;
input VAR4 ;
input VAR5 ;
input VAR8;
input VAR2;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/IBUFGDS.v | 2,610 | module MODULE1 (VAR1, VAR8, VAR5);
parameter VAR7 = "VAR3";
parameter VAR11 = "VAR6";
parameter VAR9 = "0";
parameter VAR4 = "VAR10";
output VAR1;
input VAR8, VAR5;
reg VAR2;
buf b0 (VAR1, VAR2); | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3b/sky130_fd_sc_hd__or3b_4.v | 2,209 | module MODULE2 (
VAR3 ,
VAR2 ,
VAR8 ,
VAR4 ,
VAR5,
VAR10,
VAR9 ,
VAR6
);
output VAR3 ;
input VAR2 ;
input VAR8 ;
input VAR4 ;
input VAR5;
input VAR10;
input VAR9 ;
input VAR6 ;
VAR1 VAR7 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/LX150_makomk_dualcore/hdl/sha256_transform.v | 15,445 | module MODULE6 (
input clk,
input [255:0] VAR10,
input [30:0] VAR49,
input [95:0] VAR93,
output reg [255:0] VAR24, VAR63
);
reg [95:0] VAR6;
reg [30:0] VAR9;
reg [31:0] VAR38, VAR68, VAR91, VAR84, VAR62, VAR55, VAR18;
wire [31:0] VAR72, VAR52, VAR67, VAR94, VAR73;
wire [31:0] VAR47, VAR14, VAR77, VAR3;
VAR97 VAR89 (VAR... | gpl-3.0 |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/slave/wb_artemis_pcie_platform/rtl/c/axi_basic_rx_null_gen.v | 15,692 | module MODULE1 #(
parameter VAR38 = 128, parameter VAR25 = 1,
parameter VAR35 = VAR38 / 8 ) (
input [VAR38-1:0] VAR6, input VAR19, input VAR2, input VAR18, input [21:0] VAR26,
output VAR11, output VAR29, output [VAR35-1:0] VAR16, output VAR23, output reg [4:0] VAR32,
input VAR7, input VAR12 );
localparam VAR31 = (VAR38... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn_1.v | 2,148 | module MODULE2 (
VAR9 ,
VAR6 ,
VAR3,
VAR1,
VAR7,
VAR5 ,
VAR8
);
output VAR9 ;
input VAR6 ;
input VAR3;
input VAR1;
input VAR7;
input VAR5 ;
input VAR8 ;
VAR4 VAR2 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR9 ,
VAR6 ,
VAR3
);
output VAR9 ;... | apache-2.0 |
masc-ucsc/cmpe220fall16 | rtl/ram_1port_dense.v | 2,056 | module MODULE1 #(parameter VAR22 = 64, VAR18=128, VAR28=0)(
input clk
,input reset
,input VAR8
,output VAR16
,input VAR12
,input [VAR21(VAR18)-1:0] VAR4
,input [VAR22-1:0] VAR30
,output VAR14
,input VAR5
,output [VAR22-1:0] VAR24
);
logic [VAR22-1:0] VAR25;
VAR9
VAR1 (
.VAR3 (VAR4)
,.VAR29 (VAR8 & VAR12)
,.VAR2 (VAR30)... | apache-2.0 |
DigitalLogicSummerTerm2015/mips-cpu-pipeline | ppcpu/forwardunit.v | 1,750 | module MODULE1(VAR1,VAR4,VAR5,VAR6,VAR13,VAR9,VAR10,VAR7,VAR3,VAR12,VAR11,VAR8,VAR2,VAR14);
input [4:0] VAR1;
input [4:0] VAR4;
input [4:0] VAR5;
input [4:0] VAR6;
input [4:0] VAR13;
input [4:0] VAR9;
input [4:0] VAR10;
input VAR7;
input VAR3;
input VAR12;
output [1:0] VAR11;
reg [1:0] VAR11;
output [1:0] VAR8;
reg [1:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3b/sky130_fd_sc_lp__and3b_m.v | 2,215 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR7 ,
VAR5 ,
VAR8,
VAR3,
VAR2 ,
VAR10
);
output VAR6 ;
input VAR4 ;
input VAR7 ;
input VAR5 ;
input VAR8;
input VAR3;
input VAR2 ;
input VAR10 ;
VAR1 VAR9 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/busInterface/wishBoneBI.v | 8,439 | module MODULE1 (
address, VAR20, VAR36, VAR25,
VAR21,
VAR26,
clk, rst,
VAR7,
VAR45, VAR11,
VAR22,
VAR2, VAR43, VAR34, VAR24,
VAR16, VAR14, VAR3, VAR19,
VAR10,
VAR1,
VAR18,
VAR30,
VAR41,
VAR35, VAR4, VAR29, VAR33,
VAR15, VAR5, VAR13, VAR38,
VAR28
);
input clk;
input rst;
input [7:0] address;
input [7:0] VAR20;
output [7... | gpl-3.0 |
Jawanga/ece385final | finalproject/synthesis/submodules/altera_avalon_dc_fifo.v | 26,090 | module MODULE1(
VAR48,
VAR76,
VAR69,
VAR7,
VAR94,
VAR59,
VAR55,
VAR90,
VAR70,
VAR12,
VAR4,
VAR20,
VAR78,
VAR86,
VAR28,
VAR15,
VAR31,
VAR49,
VAR58,
VAR8,
VAR106,
VAR38,
VAR83,
VAR107,
VAR61,
VAR19,
VAR101,
VAR43,
VAR3,
VAR82,
VAR10,
VAR67,
VAR26,
VAR50,
VAR63
);
parameter VAR68 = 1;
parameter VAR95 = 8;
parameter VAR29 ... | apache-2.0 |
martinmiranda14/Digitales | Lab5/Display.v | 1,919 | module MODULE1(
input VAR6,
input [31:0] VAR3,
input [7:0] VAR9,
output [7:0] VAR8,
output reg [7:0] VAR5
);
reg [2:0] counter;
reg [3:0] VAR2;
always @(posedge VAR6) begin
counter <= counter+3'b1;
end
always @(counter) begin
case (counter)
4'd0: VAR5= 8'b01111111;
4'd1: VAR5= 8'b10111111;
4'd2: VAR5= 8'b11011111;
4'd3... | apache-2.0 |
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