repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6T_INVBUF_SRAM_TT_210930.v | 14,992 | module MODULE1 (VAR1, VAR2);
output VAR1;
input VAR2;
buf (VAR1, VAR2); | bsd-3-clause |
brandonpelfrey/ice40-nes | src/mod_sdram_controller.v | 13,435 | module MODULE1 (
input VAR31,
input VAR41,
output VAR79,
output VAR21,
output VAR72,
output VAR54,
output VAR2,
output VAR19,
output [1:0] VAR63,
output [11:0] VAR30,
inout [7:0] VAR48,
input [21:0] VAR35, input VAR82, input [31:0] VAR23, output [31:0] VAR7, output VAR26, input VAR78, output VAR9 );
localparam VAR64 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.v | 2,226 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR5 ,
VAR8 ,
VAR9,
VAR2,
VAR1 ,
VAR3
);
output VAR6 ;
output VAR10 ;
input VAR5 ;
input VAR8 ;
input VAR9;
input VAR2;
input VAR1 ;
input VAR3 ;
VAR7 VAR4 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221o/sky130_fd_sc_hs__a221o.functional.pp.v | 2,100 | module MODULE1 (
VAR14,
VAR16,
VAR4 ,
VAR10 ,
VAR11 ,
VAR15 ,
VAR13 ,
VAR2
);
input VAR14;
input VAR16;
output VAR4 ;
input VAR10 ;
input VAR11 ;
input VAR15 ;
input VAR13 ;
input VAR2 ;
wire VAR13 VAR8 ;
wire VAR13 VAR12 ;
wire VAR9 ;
wire VAR5;
and VAR6 (VAR8 , VAR15, VAR13 );
and VAR18 (VAR12 , VAR10, VAR11 );
or VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1p/sky130_fd_sc_hd__lpflow_inputiso1p.behavioral.v | 1,409 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR4
);
output VAR8 ;
input VAR2 ;
input VAR4;
supply1 VAR7;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR5 ;
or VAR1 (VAR8 , VAR2, VAR4 );
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_4d_2c_v1_00_a/hdl/verilog/cf_ddsv_intp_1.v | 4,027 | module MODULE1 (
clk,
VAR5,
VAR15,
VAR14,
VAR16,
VAR7,
VAR13);
input clk;
input [15:0] VAR5;
input [15:0] VAR15;
input [15:0] VAR14;
input [15:0] VAR16;
output [15:0] VAR7;
output [15:0] VAR13;
reg [15:0] VAR4 = 'd0;
reg [15:0] VAR2 = 'd0;
reg [15:0] VAR7 = 'd0;
reg [15:0] VAR13 = 'd0;
wire [15:0] VAR9;
wire [15:0] VAR... | mit |
shaform/ArkanoidOnVerilog | state_control.v | 6,249 | module MODULE1
parameter VAR76 = 2,
parameter VAR19 = 2
)
(
input VAR15, reset, VAR24, VAR39, VAR78,
input [3:0] VAR17,
input VAR87,
input [3:0] VAR56,
input [9:0] VAR41, VAR55,
output reg [5:0] VAR27, VAR53,
output [VAR76*10-1:0] VAR26, VAR86,
output reg [VAR76-1:0] VAR28,
output reg [VAR19*2-1:0] VAR1, VAR50,
output ... | gpl-3.0 |
davidkoltak/tawas-core | ip/debug_ip/rtl/debug_state.v | 5,874 | module MODULE1
(
input VAR18,
input VAR25,
input [9:0] VAR11,
input VAR5,
input VAR27,
input [31:0] VAR24,
output reg [31:0] VAR7,
output reg VAR10,
output reg [7:0] VAR16,
input VAR4,
input VAR23,
input [95:0] VAR3
);
parameter VAR1 = 1;
parameter VAR33 = 0;
parameter VAR14 = 8'd0;
reg [1:0] VAR41;
reg [1:0] VAR32;
re... | mit |
keith-epidev/VHDL-lib | top/stereo_radio/ip/clk_108MHz/clk_108MHz_stub.v | 1,171 | module MODULE1(VAR2, MODULE1, VAR1)
;
input VAR2;
output MODULE1;
output VAR1;
endmodule | gpl-2.0 |
joaocarlos/udlx-verilog | rtl/top/top.v | 5,877 | module MODULE1
parameter VAR66 = 32,
parameter VAR6 = 32,
parameter VAR83 = 20,
parameter VAR17 = 4,
parameter VAR38 = 2
)
(
input clk,
input VAR63,
input VAR18,
output VAR40,
output [VAR83-1:0] VAR47,
input [VAR66-1:0] VAR65,
output VAR41,
output VAR1,
output VAR78,
output VAR44,
output VAR76,
output [VAR6-1:0] VAR50,... | lgpl-3.0 |
jotego/jt51 | hdl/jt51_eg.v | 12,624 | module MODULE1(
input VAR27,
input rst,
input clk,
input VAR77,
input VAR9,
input [4:0] VAR59,
input [4:0] VAR35,
input [4:0] VAR26,
input [4:0] VAR71,
input [3:0] VAR12,
input [3:0] VAR63,
input [1:0] VAR39,
input VAR1,
output reg VAR31,
input [6:0] VAR11,
input [7:0] VAR23,
input [1:0] VAR81,
input VAR58,
output [9:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21o/sky130_fd_sc_hd__a21o.behavioral.pp.v | 1,994 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR14 ,
VAR1 ,
VAR5,
VAR11,
VAR15 ,
VAR6
);
output VAR7 ;
input VAR4 ;
input VAR14 ;
input VAR1 ;
input VAR5;
input VAR11;
input VAR15 ;
input VAR6 ;
wire VAR3 ;
wire VAR10 ;
wire VAR9;
and VAR13 (VAR3 , VAR4, VAR14 );
or VAR16 (VAR10 , VAR3, VAR1 );
VAR8 VAR12 (VAR9, VAR10, VAR5, VAR11);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a222o/sky130_fd_sc_ls__a222o.pp.blackbox.v | 1,456 | module MODULE1 (
VAR11 ,
VAR1 ,
VAR8 ,
VAR6 ,
VAR10 ,
VAR5 ,
VAR9 ,
VAR3,
VAR2,
VAR7 ,
VAR4
);
output VAR11 ;
input VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR10 ;
input VAR5 ;
input VAR9 ;
input VAR3;
input VAR2;
input VAR7 ;
input VAR4 ;
endmodule | apache-2.0 |
SiLab-Bonn/monopix_daq | firmware/src/monopix_mio.v | 6,373 | module MODULE1 (
input wire VAR60,
inout wire [7:0] VAR33,
input wire [15:0] VAR75,
input wire VAR2,
input wire VAR83,
inout wire [7:0] VAR12,
input wire VAR61,
input wire VAR81,
input wire VAR56,
output wire [4:0] VAR39,
output wire [19:0] VAR6,
inout wire [15:0] VAR53,
output wire VAR25,
output wire VAR28,
output wir... | gpl-2.0 |
theapi/de0-nano | pong/pong_export.v | 2,878 | module MODULE1(
VAR39,
VAR22,
VAR18,
VAR29,
VAR2,
VAR44,
VAR55,
VAR10,
VAR15,
VAR7
);
input wire VAR39;
input wire VAR22;
input wire VAR18;
input wire VAR29;
output wire VAR2;
output wire VAR44;
output wire VAR55;
output wire VAR10;
output wire VAR15;
output wire [7:0] VAR7;
wire [7:0] VAR31;
wire VAR6;
wire VAR56;
wir... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/triple_speed_ethernet-library/altera_tse_rgmii_module.v | 7,700 | module MODULE1 ( VAR56,
VAR44,
VAR41,
VAR51,
VAR25,
VAR16,
VAR55,
VAR3,
VAR52,
VAR48,
VAR17,
VAR27,
VAR45,
VAR33,
VAR15,
VAR11,
VAR6,
VAR59,
VAR28,
VAR29,
VAR8,
VAR9,
VAR31
);
parameter VAR47 = 3;
output [ 3: 0] VAR33;
output [ 7: 0] VAR15;
output [ 3: 0] VAR11;
output VAR6;
output VAR59;
output VAR28;
output VAR29;
ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxbp/sky130_fd_sc_ms__edfxbp.symbol.v | 1,448 | module MODULE1 (
input VAR4 ,
output VAR6 ,
output VAR1,
input VAR9 ,
input VAR7
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wrap_cmd.v | 6,467 | module MODULE1 #
(
parameter integer VAR8 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR8-1:0] VAR20 ,
input wire [7:0] VAR23 ,
input wire [2:0] VAR15 ,
input wire VAR2 ,
output wire [VAR8-1:0] VAR3 ,
input wire VAR6 ,
output reg VAR10
);
reg VAR14;
wire [11:0] VAR24;
wire [3:0] VAR1;
reg [11:0] VAR19;
re... | gpl-3.0 |
pavel-demin/red-pitaya-notes | cores/axis_bram_writer_v1_0/axis_bram_writer.v | 1,701 | module MODULE1 #
(
parameter integer VAR15 = 32,
parameter integer VAR14 = 32,
parameter integer VAR13 = 10
)
(
input wire VAR11,
input wire VAR3,
output wire [VAR13-1:0] VAR5,
output wire VAR17,
input wire [VAR15-1:0] VAR12,
input wire VAR18,
output wire VAR10,
output wire VAR6,
output wire [VAR13-1:0] VAR9,
output wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21o/sky130_fd_sc_lp__a21o_2.v | 2,248 | module MODULE2 (
VAR6 ,
VAR5 ,
VAR8 ,
VAR3 ,
VAR7,
VAR1,
VAR10 ,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR7;
input VAR1;
input VAR10 ;
input VAR2 ;
VAR9 VAR4 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/ultrascale_plus/bsg_misc/bsg_mul_add_unsigned.v | 1,746 | module MODULE1 #(
parameter VAR8(VAR18)
,parameter VAR8(VAR31)
,parameter VAR25 = VAR18 + VAR31
,parameter VAR20 = VAR21( ((1 << VAR18) - 1) * ((1 << VAR31) - 1) +
((1 << VAR25)-1) + 1 )
,parameter VAR15 = 0
) (
input VAR2
,input [VAR18-1 : 0] VAR5
,input [VAR31-1 : 0] VAR16
,input [VAR25-1 : 0] VAR10
,output [VAR20-1 ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4bb/sky130_fd_sc_ls__and4bb_2.v | 2,323 | module MODULE2 (
VAR6 ,
VAR8 ,
VAR5 ,
VAR2 ,
VAR4 ,
VAR11,
VAR3,
VAR10 ,
VAR1
);
output VAR6 ;
input VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR11;
input VAR3;
input VAR10 ;
input VAR1 ;
VAR9 VAR7 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR10(VAR10),
.... | apache-2.0 |
erdmannp/de2 | rtl/verilog/wb_intercon.v | 17,924 | module MODULE1
(input VAR79,
input VAR71,
input [31:0] VAR227,
input [31:0] VAR175,
input [3:0] VAR128,
input VAR115,
input VAR120,
input VAR205,
input [2:0] VAR50,
input [1:0] VAR103,
output [31:0] VAR231,
output VAR55,
output VAR61,
output VAR17,
input [31:0] VAR8,
input [31:0] VAR1,
input [3:0] VAR72,
input VAR30,
i... | gpl-2.0 |
mithro/HDMI2USB | hdl/UART/uart_main.v | 3,291 | module MODULE1
parameter VAR36 = 8,
VAR40 = 16,
VAR30 = 326, VAR5 = 9, VAR26 = 4
)
(
input wire clk, reset,
input wire VAR22, VAR28, VAR2,
input wire [7:0] VAR17,
output wire VAR37, VAR19, VAR13,
output wire [7:0] VAR38
);
wire VAR25, VAR31, VAR18;
wire VAR1, VAR24;
wire [7:0] VAR8, VAR34;
assign VAR4=clk;
counter #(.V... | bsd-2-clause |
Cognoscan/BoostDSP | verilog/src/control/piController.v | 3,139 | module MODULE1 #(
parameter VAR6 = 16, parameter VAR15 = 0, parameter VAR10 = 0, parameter VAR2 = 0, parameter VAR12 = VAR6, parameter VAR1 = 1, parameter VAR4 = 1, parameter VAR16 = 0, parameter VAR13 = 0, parameter VAR3 = 0 )
(
input wire clk,
input wire reset,
input wire signed [VAR6-1:0] VAR5,
output reg signed [VA... | apache-2.0 |
HarmonInstruments/hififo | hdl/pcie_rx.v | 3,341 | module MODULE1
(
input VAR13,
input reset,
output reg VAR30 = 0,
output reg VAR2 = 0,
output reg [5:0] VAR20 = 0,
output [7:0] VAR7,
output reg [63:0] VAR6 = 0,
output [5:0] address,
output [23:0] VAR18,
output [7:0] VAR4,
output VAR38,
input VAR24,
input VAR17,
input VAR29,
input [63:0] VAR27
);
function [31:0] VAR28;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4/sky130_fd_sc_hd__and4_2.v | 2,242 | module MODULE2 (
VAR9 ,
VAR4 ,
VAR5 ,
VAR2 ,
VAR8 ,
VAR11,
VAR3,
VAR1 ,
VAR6
);
output VAR9 ;
input VAR4 ;
input VAR5 ;
input VAR2 ;
input VAR8 ;
input VAR11;
input VAR3;
input VAR1 ;
input VAR6 ;
VAR7 VAR10 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR... | apache-2.0 |
alexforencich/verilog-ethernet | example/ExaNIC_X10/fpga/rtl/fpga.v | 8,555 | module MODULE1 (
input wire VAR144,
input wire VAR62,
output wire [1:0] VAR172,
output wire [1:0] VAR176,
output wire [1:0] VAR65,
input wire VAR141,
input wire VAR70,
output wire VAR148,
output wire VAR131,
input wire VAR175,
input wire VAR73,
output wire VAR56,
output wire VAR64,
input wire VAR89,
input wire VAR2,
ou... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_4.functional.pp.v | 1,168 | module MODULE1( VAR1, VAR9, VAR7, VAR5, VAR2 );
input VAR9, VAR1;
inout VAR5, VAR2;
output VAR7;
wire VAR6;
not VAR12( VAR6, VAR1 );
wire VAR11;
and VAR13( VAR11, VAR6, VAR9 );
wire VAR3;
not VAR14( VAR3, VAR9 );
wire VAR8;
and VAR10( VAR8, VAR3, VAR1 );
or VAR4( VAR7, VAR11, VAR8 );
endmodule | apache-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/7-uart/uart.v | 1,847 | module MODULE1
(
input wire clk,
input wire reset,
input wire VAR10,
input wire VAR3,
input wire VAR25,
input wire [VAR28-1:0] VAR22,
output wire VAR5,
output wire VAR23,
output wire VAR16,
output wire [VAR28-1:0] VAR2
);
wire VAR6, VAR11;
wire [VAR28-1:0] VAR1, VAR20;
VAR29 #(.VAR9(VAR17)) VAR27
( .clk(clk), .reset(re... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd.behavioral.pp.v | 1,200 | module MODULE1 (
VAR2,
VAR3,
VAR1 ,
VAR4
);
input VAR2;
input VAR3;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
omicronns/studies-sys-rek | de1-soc-proc/ip/alu_sub.v | 4,578 | module MODULE1 (
VAR5,
VAR6,
VAR13);
input [7:0] VAR5;
input [7:0] VAR6;
output [7:0] VAR13;
wire [7:0] VAR1;
wire [7:0] VAR13 = VAR1[7:0];
VAR20 VAR19 (
.VAR5 (VAR5),
.VAR6 (VAR6),
.VAR13 (VAR1)
,
.VAR9 (),
.VAR22 (),
.VAR23 (),
.VAR2 (),
.VAR21 (),
.VAR18 (),
.VAR11 ()
);
VAR19.VAR10 = "VAR15",
VAR19.VAR24 = "VAR17=... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211oi/sky130_fd_sc_hd__a211oi.behavioral.v | 1,553 | module MODULE1 (
VAR3 ,
VAR5,
VAR7,
VAR6,
VAR2
);
output VAR3 ;
input VAR5;
input VAR7;
input VAR6;
input VAR2;
supply1 VAR11;
supply0 VAR9;
supply1 VAR13 ;
supply0 VAR10 ;
wire VAR1 ;
wire VAR8;
and VAR14 (VAR1 , VAR5, VAR7 );
nor VAR12 (VAR8, VAR1, VAR6, VAR2);
buf VAR4 (VAR3 , VAR8 );
endmodule | apache-2.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_ddr_axic_register_slice.v | 19,168 | module MODULE1 #
(
parameter VAR7 = "VAR4",
parameter VAR13 = 32,
parameter VAR1 = 32'h00000000
)
(
input wire VAR6,
input wire VAR9,
input wire [VAR13-1:0] VAR20,
input wire VAR18,
output wire VAR5,
output wire [VAR13-1:0] VAR24,
output wire VAR15,
input wire VAR8
);
generate
if (VAR1 == 32'h00000000)
begin
assign VAR... | mit |
origintfj/riscv | rv32i/rtl/merlin_alu.v | 5,878 | module MODULE1
(
input wire VAR17,
input wire VAR4,
input wire VAR1,
input wire [VAR9-1:0] VAR20,
input wire [VAR9-1:0] VAR11,
output reg [VAR9-1:0] VAR3,
input wire [VAR12] VAR10,
input wire [VAR9-1:0] VAR6,
input wire [VAR9-1:0] VAR5,
output reg VAR18,
input wire [2:0] VAR7
);
reg [VAR9-1:0] VAR8;
genvar VAR15;
reg [... | apache-2.0 |
hcabrera-/lancetfish | RTL/node_mesh/des_network_core/rtl/des_network_core.v | 7,517 | module MODULE1
(
input wire clk,
input wire reset,
input wire [0:(VAR38 * VAR28)-1] VAR40,
output wire [0:VAR38-1] VAR35,
input wire [0:(VAR38 * VAR28)-1] VAR42,
output wire [0:VAR38-1] VAR47,
input wire [0:(VAR27 * VAR28)-1] VAR41,
output wire [0:VAR27-1] VAR31,
input wire [0:(VAR27 * VAR28)-1] VAR34,
output wire [0:V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3/sky130_fd_sc_hdll__nand3.pp.symbol.v | 1,294 | module MODULE1 (
input VAR1 ,
input VAR4 ,
input VAR7 ,
output VAR6 ,
input VAR8 ,
input VAR3,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | systemverilog/cadence/Verilog/Lab6-1/alu.v | 1,099 | module MODULE1
( input wire [VAR2-1:0] VAR1,
input wire [VAR2-1:0] VAR3,
input wire [2:0] VAR4,
output reg [VAR2-1:0] VAR5,
output wire VAR6 );
assign VAR6 = VAR1 ? 1'b0: 1'b1;
always @ ( * )
begin
if ( VAR4 == 3'b000 )
begin
VAR5 = VAR1;
end
else if ( VAR4 == 3'b001 )
begin
VAR5 = VAR1;
end
else if ( VAR4 == 3'b010 )
... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/input_arbiter/rr_input_arbiter/src/in_arb_regs.v | 6,740 | module MODULE1
parameter VAR21 = VAR35/8,
parameter VAR10 = 2
)
(
input VAR20,
input VAR27,
input VAR43,
input [VAR13-1:0] VAR42,
input [VAR15-1:0] VAR6,
input [VAR10-1:0] VAR14,
output reg VAR4,
output reg VAR28,
output reg VAR5,
output reg [VAR13-1:0] VAR11,
output reg [VAR15-1:0] VAR7,
output reg [VAR10-1:0] VAR22,
... | mit |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_phy.v | 31,434 | module MODULE1 (
VAR49,
VAR79,
VAR76,
VAR58,
VAR48,
VAR74,
VAR99,
VAR22,
VAR17,
VAR20,
VAR50,
VAR5,
VAR2,
VAR72,
VAR56,
VAR57,
VAR21,
VAR62,
VAR82,
VAR100,
VAR90,
VAR73,
VAR75,
VAR24,
VAR26,
VAR51,
VAR31,
VAR15,
VAR16,
VAR87,
VAR32,
VAR59,
VAR78,
VAR86,
VAR19,
VAR96,
VAR92,
VAR4,
VAR43,
VAR66,
VAR11,
VAR69,
VAR80,
VAR9... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fill/sky130_fd_sc_lp__fill.pp.blackbox.v | 1,173 | module MODULE1 (
VAR1,
VAR3,
VAR2 ,
VAR4
);
input VAR1;
input VAR3;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
wcandillon/linguist | samples/Verilog/t_sqrt_pipelined.v | 2,152 | module MODULE1();
parameter
VAR1 = 4;
localparam
VAR2 = VAR1 / 2 + VAR1 % 2;
reg [VAR1-1:0] VAR8;
reg clk, VAR7, VAR3;
wire [VAR2-1:0] VAR5;
wire VAR6;
VAR4
.VAR1(VAR1)
)
VAR4
(
.clk(clk),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5)
); | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3/sky130_fd_sc_hd__and3.functional.pp.v | 1,810 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR6 ,
VAR5 ,
VAR13,
VAR7,
VAR4 ,
VAR9
);
output VAR8 ;
input VAR10 ;
input VAR6 ;
input VAR5 ;
input VAR13;
input VAR7;
input VAR4 ;
input VAR9 ;
wire VAR1 ;
wire VAR2;
and VAR11 (VAR1 , VAR5, VAR10, VAR6 );
VAR12 VAR3 (VAR2, VAR1, VAR13, VAR7);
buf VAR14 (VAR8 , VAR2 );
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/triple_speed_ethernet-library/altera_tse_reset_synchronizer.v | 3,349 | module MODULE1
parameter VAR3 = 1,
parameter VAR5 = 2
)
(
input VAR4 ,
input clk,
output VAR1
);
reg [VAR5-1:0] VAR2;
generate if (VAR3) begin
always @(posedge clk or posedge VAR4) begin
if (VAR4) begin
VAR2 <= {VAR5{1'b1}};
end
else begin
VAR2[VAR5-2:0] <= VAR2[VAR5-1:1];
VAR2[VAR5-1] <= 0;
end
end
assign VAR1 = VAR2[... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_4.behavioral.v | 1,429 | module MODULE1( VAR4, VAR5, VAR1 );
input VAR5, VAR4;
output VAR1;
VAR2 VAR3(.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1));
VAR2 VAR6(.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/correlator/correlate_cos_sin.v | 2,772 | module MODULE1
parameter VAR12 = VAR11-1,
parameter VAR6 = 0, parameter VAR15 = 3)
(
input clk,
input en,
input VAR5,
input VAR1,
input VAR27,
input VAR20,
input [VAR12:0] VAR23,
input [VAR12:0] VAR13,
output reg valid = 0,
output [VAR12:0] VAR9,
output [VAR12:0] VAR25
);
wire VAR10 = VAR6 && VAR5 ? VAR27 == 1'b1 : VAR... | lgpl-3.0 |
Murailab-arch/magukara | boards/ecp3versa/rtl/ipexpress/ecp3/rcx1/pcie_eval/models/ecp3/ctc.v | 13,203 | module MODULE1
(
VAR59, VAR46, VAR45,
VAR1, VAR42, VAR68, VAR53, VAR57,
VAR61, VAR48, VAR72, VAR5, VAR12, VAR26, VAR79, VAR40, VAR58 );
input VAR59;
input VAR46;
input VAR45;
input VAR1;
input [7:0] VAR42;
input VAR68;
input [2:0] VAR53;
input VAR57;
output VAR61;
output VAR48;
output VAR72;
output [7:0] VAR5;
output V... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v | 10,689 | module MODULE1 #
( parameter
VAR3 = 40,
VAR13 = 8,
VAR29 = 0,
VAR4 = 7,
VAR9 = 7,
VAR19 = 1
)
(
VAR33,
VAR15,
VAR28,
VAR21,
VAR10,
VAR2,
VAR11,
VAR23,
VAR1
);
localparam VAR18 = (VAR3 > 8) ? (VAR3 - VAR13) : (VAR3);
input VAR33;
input VAR15;
input [VAR4 - 1 : 0] VAR28;
input [VAR9 - 1 : 0] VAR21;
input [VAR19 - 1 : 0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21a/sky130_fd_sc_lp__o21a_2.v | 2,248 | module MODULE2 (
VAR6 ,
VAR9 ,
VAR3 ,
VAR7 ,
VAR10,
VAR2,
VAR8 ,
VAR1
);
output VAR6 ;
input VAR9 ;
input VAR3 ;
input VAR7 ;
input VAR10;
input VAR2;
input VAR8 ;
input VAR1 ;
VAR4 VAR5 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41oi/sky130_fd_sc_ms__a41oi.functional.v | 1,476 | module MODULE1 (
VAR9 ,
VAR11,
VAR8,
VAR7,
VAR10,
VAR5
);
output VAR9 ;
input VAR11;
input VAR8;
input VAR7;
input VAR10;
input VAR5;
wire VAR3 ;
wire VAR2;
and VAR4 (VAR3 , VAR11, VAR8, VAR7, VAR10 );
nor VAR1 (VAR2, VAR5, VAR3 );
buf VAR6 (VAR9 , VAR2 );
endmodule | apache-2.0 |
jas0n1ee/THU-DSD | FB/binary_vga.v | 2,341 | module MODULE1 (
input wire VAR13, output wire [9:0] VAR10, output wire [9:0] VAR19, output wire [9:0] VAR9, output wire VAR18, output wire VAR3, output wire VAR2, output wire VAR17, output wire VAR7, input wire VAR8, output wire [15:0] VAR4, input wire [15:0] VAR14, input wire [18:0] VAR16, input wire VAR12, input wir... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/common/wb_mem_2_ppfifo/rtl/wb_mem_2_ppfifo.v | 9,023 | module MODULE1(
input clk,
input rst,
output [31:0] VAR21,
input VAR20,
input [31:0] VAR31,
input [31:0] VAR13,
output [31:0] VAR16,
input VAR8,
output VAR1,
input [31:0] VAR17,
input [31:0] VAR23,
input [31:0] VAR43,
output [31:0] VAR29,
input VAR15,
output VAR35,
input [31:0] VAR27,
output reg VAR44,
output reg VAR25... | mit |
freecores/tiny_tate_bilinear_pairing | group_size_is_697_bits/rtl/cubic.v | 65,935 | module MODULE2(VAR2, VAR1);
input [1005:0] VAR2;
output [1005:0] VAR1;
assign VAR1[1:0] = VAR2[1:0];
assign VAR1[3:2] = VAR2[337:336];
assign VAR1[5:4] = VAR2[673:672];
assign VAR1[7:6] = VAR2[3:2];
assign VAR1[9:8] = VAR2[339:338];
assign VAR1[11:10] = VAR2[675:674];
assign VAR1[13:12] = VAR2[5:4];
assign VAR1[15:14] ... | apache-2.0 |
Mahdi89/eTeak | SELF_files/SRLOR_L.v | 1,115 | module MODULE1(
output VAR12,
input VAR5,
input VAR3,
input rst
);
wire VAR13;
wire VAR11;
wire VAR3;
wire VAR12 ;
VAR4 VAR2 (VAR3, ~VAR3, ~rst);
VAR4 VAR8 (VAR13, VAR3, VAR5);
VAR4 VAR10 (VAR11, VAR3, ~VAR5);
VAR9 VAR6 (VAR12, VAR13, VAR12);
VAR1 VAR7 (VAR12, VAR12, VAR11, rst);
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22oi/sky130_fd_sc_ms__a22oi.blackbox.v | 1,364 | module MODULE1 (
VAR6 ,
VAR5,
VAR2,
VAR9,
VAR1
);
output VAR6 ;
input VAR5;
input VAR2;
input VAR9;
input VAR1;
supply1 VAR8;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
eda-globetrotter/PicenoDecoders | extra_credit/syn/netlist/spare/decoder4to16.v | 1,420 | module MODULE1 (in,out);
output reg [15:1] out;
input [3:0] in;
reg [3:0] VAR1;
always @(*)
begin
VAR1=~in;
out[1]=in[0] & VAR1[1] & VAR1[2] & VAR1[3];
out[2]=VAR1[0] & in[1] & VAR1[2] & VAR1[3];
out[3]=in[0] & in[1] & VAR1[2] & VAR1[3];
out[4]=VAR1[0] & VAR1[1] & in[2] & VAR1[3];
out[5]=in[0] & VAR1[1] & in[2] & VAR1[... | mit |
trevortheblack/NewLondo16 | Verilog/RFT/FF32.v | 1,281 | module MODULE1(VAR28, VAR3, VAR32, VAR25);
input [31:0] VAR28;
input VAR3, VAR32;
output [31:0] VAR25;
VAR31 VAR37 (VAR28[00], VAR3, VAR32, VAR25[00]);
VAR31 VAR23 (VAR28[01], VAR3, VAR32, VAR25[01]);
VAR31 VAR9 (VAR28[02], VAR3, VAR32, VAR25[02]);
VAR31 VAR1 (VAR28[03], VAR3, VAR32, VAR25[03]);
VAR31 VAR13 (VAR28[04],... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31ai/sky130_fd_sc_lp__o31ai_4.v | 2,335 | module MODULE2 (
VAR2 ,
VAR11 ,
VAR5 ,
VAR10 ,
VAR1 ,
VAR6,
VAR3,
VAR9 ,
VAR8
);
output VAR2 ;
input VAR11 ;
input VAR5 ;
input VAR10 ;
input VAR1 ;
input VAR6;
input VAR3;
input VAR9 ;
input VAR8 ;
VAR4 VAR7 (
.VAR2(VAR2),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfstp/sky130_fd_sc_ls__sdfstp.blackbox.v | 1,418 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR1 ,
VAR2 ,
VAR9 ,
VAR4
);
output VAR6 ;
input VAR10 ;
input VAR1 ;
input VAR2 ;
input VAR9 ;
input VAR4;
supply1 VAR3;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/4-way_2-tree/src/ip_dram/phy/mig_7series_v2_3_ddr_mc_phy.v | 89,245 | module MODULE1
parameter VAR414 = 4'b1111,
parameter VAR340 = 4'b0000,
parameter VAR136 = 4'b0000,
parameter VAR321 = 4'b0000,
parameter VAR19 = 4'b0000,
parameter VAR367 = 4'hc,
parameter VAR458 = 4'hf,
parameter VAR384 = 4'hf,
parameter VAR463 = 4'hf,
parameter VAR345 = 4'hf,
parameter VAR178 = 0,
parameter VAR145 = ... | mit |
hoangt/NOCulator | hring/hw/buffered/verif/router/packet_source.v | 26,749 | module MODULE1
(clk, reset, VAR78, VAR152, VAR90, VAR126, VAR32, VAR62,
VAR149);
parameter VAR18 = 0;
parameter VAR96 = 1000;
parameter VAR144 = 25;
parameter VAR45 = 32;
parameter VAR127 = 0;
parameter VAR84 = VAR138;
parameter VAR150 = 8;
parameter VAR130 = 4;
parameter VAR106 = 2;
parameter VAR114 = 2;
localparam VA... | mit |
SeanZarzycki/openSPARC-FPU | project/src/fpu_in2_gt_in1_2b.v | 1,772 | module MODULE1 (
VAR3,
VAR5,
VAR4,
VAR2
);
input [1:0] VAR3; input [1:0] VAR5;
output VAR4; output VAR2;
wire [1:0] VAR1;
wire VAR4;
wire VAR2;
assign VAR1[1:0]= (~(VAR3 ^ VAR5));
assign VAR4= (!(&VAR1));
assign VAR2= ((!VAR3[1]) && VAR5[1])
|| (VAR1[1] && (!VAR3[0]) && VAR5[0]);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.v | 2,396 | module MODULE2 (
VAR1 ,
VAR11 ,
VAR3 ,
VAR10,
VAR6 ,
VAR9 ,
VAR8,
VAR5 ,
VAR2
);
output VAR1 ;
input VAR11 ;
input VAR3 ;
input VAR10;
input VAR6 ;
input VAR9 ;
input VAR8;
input VAR5 ;
input VAR2 ;
VAR7 VAR4 (
.VAR1(VAR1),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5),
.... | apache-2.0 |
muraj/trv_proc | rtl/trv_decoder.v | 3,372 | module MODULE1
(
input wire [31:0] VAR19,
output wire [2:0] VAR32,
output wire [5:0] VAR4,
output wire VAR5,
output wire VAR9,
output wire VAR14,
output wire [4:0] rd,
output wire [4:0] VAR29,
output wire [4:0] VAR15,
output wire [31:0] VAR16,
output wire VAR8,
output wire VAR30,
output wire VAR22,
output wire VAR3,
);... | mit |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/verilog/axi_vdma_v6_2_axis_infrastructure_v1_0_util_axis2vector.v | 7,433 | module MODULE1 #
(
parameter integer VAR19 = 32,
parameter integer VAR21 = 1,
parameter integer VAR31 = 1,
parameter integer VAR22 = 1,
parameter integer VAR8 = 44,
parameter [31:0] VAR4 = 32'hFF
)
(
input wire [VAR19-1:0] VAR33,
input wire [VAR19/8-1:0] VAR25,
input wire [VAR19/8-1:0] VAR14,
input wire VAR1,
input wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/buf/sky130_fd_sc_hdll__buf.blackbox.v | 1,210 | module MODULE1 (
VAR3,
VAR2
);
output VAR3;
input VAR2;
supply1 VAR4;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | MAX10_SLAVE/phyIniCommand0_and.v | 1,189 | module MODULE1
(
input [(VAR6-1):0] VAR4,
input [(VAR2-1):0] addr,
input VAR5, clk,
output [(VAR6-1):0] VAR7
);
reg [VAR6-1:0] VAR3[2**VAR2-1:0];
reg [VAR2-1:0] VAR1;
begin | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_convolve_kernel_0_1/synth/design_1_convolve_kernel_0_1.v | 20,426 | module MODULE1 (
VAR19,
VAR8,
VAR38,
VAR22,
VAR10,
VAR6,
VAR4,
VAR33,
VAR40,
VAR41,
VAR35,
VAR18,
VAR42,
VAR17,
VAR36,
VAR37,
VAR15,
VAR13,
VAR12,
interrupt,
VAR25,
VAR32,
VAR44,
VAR21,
VAR28,
VAR3,
VAR9,
VAR24,
VAR26,
VAR39,
VAR11,
VAR16,
VAR7,
VAR29,
VAR1,
VAR23,
VAR30,
VAR34,
VAR27,
VAR5,
VAR20
);
input wire [3 : 0]... | mit |
kevintownsend/R3 | coregen/fifo_fwft_96x512_hf.v | 57,235 | module MODULE1 (
clk, VAR161, rst, VAR146, VAR2, VAR56, VAR4, VAR60, dout, din
);
input clk;
input VAR161;
input rst;
output VAR146;
input VAR2;
output VAR56;
output VAR4;
output VAR60;
output [95 : 0] dout;
input [95 : 0] din;
wire VAR131;
wire VAR173;
wire \VAR1/VAR155/VAR159.VAR50/VAR10.VAR24/VAR42/VAR26 ;
wire \VAR... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/ter_cam/src/ram_based_cam.v | 3,659 | module MODULE1 (clk,rst,VAR22,VAR10,VAR17,VAR3,
VAR12,VAR16,ready,VAR1);
parameter VAR21 = 4; parameter VAR14 = 5;
localparam VAR19 = 8; localparam VAR9 = VAR21 * VAR19;
localparam VAR13 = (1 << VAR14);
input clk,rst,VAR22;
input [VAR14-1:0] VAR10;
input [VAR9-1:0] VAR17,VAR3;
input [VAR9-1:0] VAR12;
output [VAR13-1:0]... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/ip_pid_controller/hdl/xlclockdriver_rd.v | 5,331 | module MODULE1 (VAR1, VAR17, VAR2, clk, VAR3, VAR16, VAR10);
parameter signed [31:0] VAR11 = 1;
parameter signed [31:0] period = 2;
parameter signed [31:0] VAR25 = 1'b0;
parameter signed [31:0] VAR21 = 5;
input VAR1;
input VAR17;
input VAR2;
output clk;
output VAR3;
output VAR16;
output VAR10;
parameter signed [31:0] V... | gpl-3.0 |
google/myelin-acorn-electron-hardware | a3000_rom_emulator/cpld/a3000_rom_emulator.v | 16,487 | module MODULE1(
inout wire [31:0] VAR31, input wire [19:0] VAR14, input wire VAR53, input wire VAR27,
output wire [21:0] VAR42,
inout wire [15:0] VAR21,
inout wire [15:0] VAR13,
output wire VAR24,
output wire VAR6,
output wire VAR49,
input wire VAR46,
input wire VAR41,
input wire VAR34, input wire VAR18,
input wire VAR... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.behavioral.pp.v | 1,259 | module MODULE1( VAR5, VAR3, VAR6, VAR8, VAR2 );
input VAR6, VAR5;
inout VAR8, VAR2;
output VAR3;
VAR7 VAR1(.VAR5(VAR5),.VAR3(VAR3),.VAR6(VAR6),.VAR8(VAR8),.VAR2(VAR2));
VAR7 VAR4(.VAR5(VAR5),.VAR3(VAR3),.VAR6(VAR6),.VAR8(VAR8),.VAR2(VAR2)); | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkQBGMAC.v | 30,585 | module MODULE1(VAR156,
VAR39,
VAR113,
VAR193,
VAR71,
VAR162,
VAR177,
VAR194,
VAR85,
VAR91,
VAR13,
VAR51,
VAR180,
VAR55,
VAR60,
VAR119,
VAR96,
VAR192,
VAR35,
VAR82,
VAR188,
VAR172,
VAR102,
VAR1,
VAR147,
VAR145,
VAR170,
VAR182,
VAR164,
VAR197,
VAR191,
VAR67,
VAR104,
VAR22,
VAR2);
input VAR156;
input VAR39;
input VAR113;
... | lgpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/nf2_reg_grp.v | 11,168 | module MODULE1 (
input VAR35, output reg VAR32,
input VAR58,
input [VAR67-1:0] VAR36,
input [VAR33-1:0] VAR31,
output reg [VAR33-1:0] VAR48,
output reg VAR20,
output wire VAR39,
output reg VAR17,
output reg VAR45,
output reg [VAR18-1:0] VAR56,
output reg [VAR33-1:0] VAR22,
input VAR9,
input [VAR33-1:0] VAR53,
output re... | apache-2.0 |
vvk/sysrek | skin_color_segm/ipcore_dir/sub10.v | 16,284 | module MODULE2 (
clk, VAR68, VAR51, VAR196, VAR193
);
input clk;
input VAR68;
input [9 : 0] VAR51;
input [9 : 0] VAR196;
output [9 : 0] VAR193;
wire \VAR152/VAR12 ;
wire \VAR152/VAR101 ;
wire \VAR152/VAR48 ;
wire \VAR152/VAR4 ;
wire \VAR152/VAR39 ;
wire \VAR152/VAR132 ;
wire \VAR152/VAR81 ;
wire \VAR152/VAR9 ;
wire \VA... | gpl-2.0 |
rkrajnc/minimig-de1 | rtl/minimig/Agnus.v | 50,694 | module MODULE6
(
input clk, input VAR147, input VAR61, input reset, input VAR41, input rd, input VAR81, input VAR171, input [15:0] VAR15, output [15:0] VAR167, input [8:1] VAR122, output reg [20:1] VAR191, output [8:1] VAR144, output reg VAR119, output reg VAR96, output VAR169, output VAR139, output VAR40, output VAR19... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfsbp/sky130_fd_sc_ms__sdfsbp.behavioral.pp.v | 2,949 | module MODULE1 (
VAR15 ,
VAR7 ,
VAR33 ,
VAR29 ,
VAR32 ,
VAR17 ,
VAR16,
VAR26 ,
VAR2 ,
VAR28 ,
VAR3
);
output VAR15 ;
output VAR7 ;
input VAR33 ;
input VAR29 ;
input VAR32 ;
input VAR17 ;
input VAR16;
input VAR26 ;
input VAR2 ;
input VAR28 ;
input VAR3 ;
wire VAR23 ;
wire VAR20 ;
wire VAR14 ;
reg VAR25 ;
wire VAR21 ;
wi... | apache-2.0 |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/tag/uid.v | 1,623 | module MODULE1(reset, VAR5, VAR7, VAR1,
VAR9, VAR8, VAR10);
input reset, VAR5;
output VAR7, VAR1, VAR10;
input [7:0] VAR9;
output [3:0] VAR8;
wire [15:0] VAR2;
assign VAR2 = 16'h3000;
reg [3:0] VAR6;
reg [3:0] VAR8;
reg VAR4;
reg VAR3;
assign VAR7 = (!VAR3) ? VAR2[VAR6] : VAR9[VAR6[2:0]];
assign VAR1 = (VAR6 == 4'd0 &&... | gpl-3.0 |
chiralhat/fpga-pulses-ice | ECP5/pulse_gen.v | 2,923 | module MODULE1(
input VAR6,
input VAR43, input VAR20, output VAR37, output VAR10, output VAR32, output VAR14, output VAR33,
output VAR27,
output [6:0] VAR4,
output [6:0] VAR55
);
wire [31:0] period;
wire [15:0] VAR28;
wire [15:0] delay;
wire [15:0] VAR24;
wire [15:0] VAR56;
wire [15:0] VAR40;
wire [15:0] VAR17;
wire [1... | bsd-3-clause |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/gpr.v | 2,112 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR1] VAR4, output wire [VAR12] VAR11,
input wire [VAR1] VAR13, output wire [VAR12] VAR7,
input wire VAR15, input wire [VAR1] VAR14, input wire [VAR12] VAR3 );
reg [VAR12] MODULE1 [VAR9-1:0]; integer VAR10;
assign VAR11 = ((VAR15 == VAR8) && (VAR14 == VAR4)... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/RAM16_s36_s36_altera_bb.v | 9,029 | module MODULE1 (
VAR4,
VAR5,
VAR7,
VAR8,
VAR6,
VAR10,
VAR2,
VAR3,
VAR1,
VAR9);
input [9:0] VAR4;
input [9:0] VAR5;
input VAR7;
input VAR8;
input [31:0] VAR6;
input [31:0] VAR10;
input VAR2;
input VAR3;
output [31:0] VAR1;
output [31:0] VAR9;
tri1 VAR7;
tri0 VAR2;
tri0 VAR3;
endmodule | mit |
lkesteloot/alice | alice4/fpga/Alice4-DE0/Vga_clock_bb.v | 10,669 | module MODULE1 (
VAR1,
VAR2);
input VAR1;
output VAR2;
endmodule | apache-2.0 |
dtysky/FPGA-Imaging-Library | Point/ContrastTransform/HDL/ContrastTransform.srcs/sources_1/new/ContrastTransform.v | 4,105 | module MODULE1(
clk,
VAR3,
VAR27,
VAR15,
VAR7,
VAR14,
VAR22
);
parameter[0 : 0] VAR23 = 0;
parameter VAR13 = 3;
parameter[3: 0] VAR17 = 8;
parameter VAR28 = 3;
input clk;
input VAR3;
input[23 : 0] VAR27;
input VAR15;
input [VAR13 * VAR17 - 1 : 0] VAR7;
output VAR14;
output[VAR13 * VAR17 - 1 : 0] VAR22;
reg[2 : 0] VAR24... | lgpl-2.1 |
sundw2014/carADS | fpga_firmware/I2C.v | 15,964 | module MODULE1(
clk,
VAR8,
VAR28,
VAR3,
VAR6,
VAR12
);
input clk,VAR3;
output VAR8;
inout VAR28;
output reg VAR6;
output wire [15:0] VAR12;
reg [2:0]VAR61;reg [8:0]VAR5;reg VAR36;
reg [19:0]VAR17;
always@(posedge clk or negedge VAR3)
if(!VAR3)
VAR17 <= 20'd0;
else
VAR17 <= VAR17+1'b1;
always@(posedge clk or negedge VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fah/sky130_fd_sc_lp__fah.pp.symbol.v | 1,291 | module MODULE1 (
input VAR3 ,
input VAR7 ,
input VAR1 ,
output VAR4,
output VAR6 ,
input VAR2 ,
input VAR8,
input VAR5,
input VAR9
);
endmodule | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_avalon_master_171/synth/ghrd_10as066n2_f2sdram0_m_altera_jtag_avalon_master_171_wqhllki.v | 25,739 | module MODULE1 #(
parameter VAR38 = 0,
parameter VAR23 = 50000,
parameter VAR8 = 2
) (
input wire VAR3, input wire VAR46, output wire [31:0] VAR11, input wire [31:0] VAR41, output wire VAR21, output wire VAR36, output wire [31:0] VAR29, input wire VAR35, input wire VAR20, output wire [3:0] VAR14, output wire VAR47 );
w... | mit |
lvd2/ngs | fpga/obsolete/fpgaE_dma/common/spi2.v | 5,702 | module MODULE1(
VAR1,
VAR5, VAR12, VAR8, VAR13,
VAR4, VAR7,
VAR11,
din, dout );
input VAR1;
output VAR5;
wire VAR5;
output VAR12;
input VAR8;
output reg VAR13;
input VAR4;
output VAR7;
input [1:0] VAR11;
input [7:0] din;
output reg [7:0] dout;
reg [4:0] counter;
wire VAR6;
reg [6:0] VAR9;
reg [7:0] VAR2;
wire VAR10;
wi... | gpl-3.0 |
osrf/wandrr | firmware/motor_controller/fpga/fp_sqrt.v | 81,141 | module MODULE1
(
VAR66,
VAR80,
VAR8,
VAR74,
VAR72) ;
input VAR66;
input VAR80;
input VAR8;
input [25:0] VAR74;
output [24:0] VAR72;
tri0 VAR66;
tri1 VAR80;
tri0 VAR8;
reg [23:0] VAR45;
reg [23:0] VAR13;
reg [23:0] VAR77;
reg [23:0] VAR100;
reg [23:0] VAR102;
reg [23:0] VAR128;
reg [23:0] VAR64;
reg [23:0] VAR142;
reg [... | apache-2.0 |
andykarpov/radio-86rk-wxeda | src/video/k580wg75.v | 4,840 | module MODULE1(
input clk,
input VAR25,
input VAR55,
input[7:0] VAR28,
input VAR12,
input VAR22,
input VAR42,
input VAR21,
input VAR47,
input[7:0] VAR31,
output reg VAR41,
output reg irq,
output[7:0] VAR62,
output[3:0] VAR49,
output reg[6:0] VAR4,
output VAR52,
output VAR24,
output VAR9,
output VAR34,
output[1:0] VAR6,... | bsd-2-clause |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/soc_system_sysid_qsys.v | 1,419 | module MODULE1 (
address,
VAR3,
VAR1,
VAR2
)
;
output [ 31: 0] VAR2;
input address;
input VAR3;
input VAR1;
wire [ 31: 0] VAR2;
assign VAR2 = address ? 1390537961 : 2899645186;
endmodule | mit |
fallen/milkymist-mmu | cores/hpdmc_ddr32/rtl/spartan6/hpdmc_ddrio.v | 3,039 | module MODULE1(
input VAR8,
input VAR51,
input VAR45,
input [7:0] VAR53,
input [63:0] do,
output [63:0] VAR33,
output [3:0] VAR23,
inout [31:0] VAR25,
inout [3:0] VAR37,
input VAR54,
input VAR56,
input VAR28,
input VAR1
);
wire [31:0] VAR3;
wire [31:0] VAR38;
wire [31:0] VAR57;
wire [31:0] VAR27;
VAR20 VAR2(
.VAR47(VAR... | lgpl-3.0 |
MarcoVogt/basil | firmware/modules/tlu/tlu_controller_fsm.v | 23,920 | module MODULE1
parameter VAR6 = 8,
parameter VAR43 = 17,
parameter VAR35 = 32
) (
input wire VAR15,
input wire VAR40,
output reg VAR25,
output reg [31:0] VAR19,
output reg VAR52,
input wire VAR59,
output reg [VAR35-1:0] VAR9,
output reg [31:0] VAR10,
output reg [31:0] VAR8,
output reg [31:0] VAR56,
input wire VAR45,
in... | bsd-3-clause |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_sao_type_dicision.v | 62,680 | module MODULE1(
clk ,
VAR55 ,
VAR8 ,
VAR36 ,
VAR1 ,
VAR307 ,
VAR304 ,
VAR221 ,
VAR68 ,
VAR136 ,
VAR140 ,
VAR133 ,
VAR154 ,
VAR180 ,
VAR27 ,
VAR82 ,
VAR87 ,
VAR163 ,
VAR127 ,
VAR80 ,
VAR91 ,
VAR130 ,
VAR78 ,
VAR256 ,
VAR223 ,
VAR139 ,
VAR100 ,
VAR309 ,
VAR3 ,
VAR311 ,
VAR179 ,
VAR312 ,
VAR250 ,
VAR129 ,
VAR11 ,
VAR199 ,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlclkp/sky130_fd_sc_hs__dlclkp_4.v | 2,027 | module MODULE1 (
VAR5,
VAR2,
VAR1 ,
VAR3,
VAR6
);
output VAR5;
input VAR2;
input VAR1 ;
input VAR3;
input VAR6;
VAR7 VAR4 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR5,
VAR2,
VAR1
);
output VAR5;
input VAR2;
input VAR1 ;
supply1 VAR3;
supply0 VAR6;
VAR7 VAR4 (
.VAR... | apache-2.0 |
benjaminfjones/fpga-tunes | src/triangle.v | 1,367 | module MODULE1 #(parameter VAR3 = 8) (
input clk,
input rst,
input [VAR3-1:0] VAR7,
output [VAR3-1:0] out
);
reg VAR8, VAR1;
reg [VAR3-1:0] VAR4, VAR6;
reg [VAR3-1:0] VAR5, VAR2;
assign out = VAR1;
always@(VAR6) begin
VAR4 = VAR6 + 1'b1;
end
always@(*) begin
if (VAR6 > VAR7) begin
VAR8 = VAR1 + VAR2; VAR6 = 1'b0; end
i... | gpl-3.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/ip/altsource_probe/hps_reset.v | 4,061 | module MODULE1 (
VAR28,
VAR31,
VAR26);
input VAR28;
input VAR31;
output [2:0] VAR26;
wire [2:0] VAR27;
wire [2:0] VAR26 = VAR27[2:0];
VAR30 VAR14 (
.VAR28 (VAR28),
.VAR31 (VAR31),
.VAR26 (VAR27)
,
.VAR25 (),
.VAR5 (),
.VAR8 (),
.VAR9 (),
.VAR15 (),
.VAR1 (),
.VAR4 (),
.VAR22 (),
.VAR6 (),
.VAR20 (),
.VAR16 (),
.VAR2 ()... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_1.behavioral.v | 1,193 | module MODULE1( VAR2, VAR5, VAR6 );
input VAR5, VAR2;
output VAR6;
VAR1 VAR3(.VAR2(VAR2),.VAR5(VAR5),.VAR6(VAR6));
VAR1 VAR4(.VAR2(VAR2),.VAR5(VAR5),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22oi/sky130_fd_sc_ms__a22oi.pp.blackbox.v | 1,393 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR3 ,
VAR6 ,
VAR2 ,
VAR5,
VAR7,
VAR8 ,
VAR1
);
output VAR4 ;
input VAR9 ;
input VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR5;
input VAR7;
input VAR8 ;
input VAR1 ;
endmodule | apache-2.0 |
manili/Pipelined_6502 | Memory.v | 3,095 | module MODULE1(
VAR25,
VAR13,
VAR8,
VAR14,
VAR22,
VAR12,
VAR2,
VAR16,
VAR7,
VAR18,
VAR5,
VAR23,
VAR1,
VAR21,
VAR4
,VAR19
);
input wire VAR25;
input wire VAR13;
input wire [1:0] VAR8;
input wire [1:0] VAR14;
input wire [3 * VAR15 - 1:0] VAR22;
input wire [VAR17 - 1:0] VAR12;
input wire [VAR17 - 1:0] VAR2;
input wire [VA... | gpl-3.0 |
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