repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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UA3MQJ/fpga-synth | modules/note_mono_harray.v | 1,523 | module MODULE1(clk, rst, VAR6, VAR4, VAR5, VAR3, VAR1);
input wire clk, rst, VAR6, VAR4;
input wire [6:0] VAR5;
output wire [6:0] VAR3;
output reg VAR1;
VAR11 VAR1 <= 0;
reg [6:0] VAR9;
VAR11 VAR9 <= 7'd0;
assign VAR3 = VAR9;
reg [127:0] VAR2;
VAR11 VAR2 <= 128'd0;
reg [6:0] VAR8;
parameter VAR10 = 1'd0;
parameter VAR7... | gpl-3.0 |
Iuliiapl/schoolMIPS | board/max_10_neek/max_10_neek.v | 7,518 | module MODULE1(
input VAR130,
inout VAR71,
output VAR109,
input VAR67,
inout VAR89,
output VAR62,
input VAR12,
inout VAR88,
output VAR15,
output VAR51,
inout VAR21,
output VAR81,
inout VAR78,
output VAR59,
inout VAR44,
output VAR42,
inout VAR20,
output VAR31,
output VAR101,
output [14:0] VAR82,
output [2:0] VAR3,
outpu... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4.behavioral.pp.v | 3,755 | module MODULE1( VAR5, VAR29, VAR3, VAR4, VAR1, VAR30 );
input VAR5, VAR29, VAR3;
inout VAR1, VAR30;
output VAR4;
reg VAR6;
VAR18 VAR16(.VAR5(VAR5),.VAR29(VAR29),.VAR3(VAR3),.VAR4(VAR4),.VAR1(VAR1),.VAR30(VAR30),.VAR6(VAR6));
VAR18 VAR14(.VAR5(VAR5),.VAR29(VAR29),.VAR3(VAR3),.VAR4(VAR4),.VAR1(VAR1),.VAR30(VAR30),.VAR6(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buflp/sky130_fd_sc_lp__buflp_m.v | 2,021 | module MODULE2 (
VAR2 ,
VAR1 ,
VAR8,
VAR7,
VAR3 ,
VAR5
);
output VAR2 ;
input VAR1 ;
input VAR8;
input VAR7;
input VAR3 ;
input VAR5 ;
VAR4 VAR6 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
supply1 VAR8;
supply0 VAR7;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_4.behavioral.v | 1,193 | module MODULE1( VAR2, VAR6, VAR3 );
input VAR2, VAR6;
output VAR3;
VAR4 VAR5(.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3));
VAR4 VAR1(.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3)); | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/alt_mem_ddrx_csr.v | 52,602 | module MODULE1 #
( parameter
VAR37 = 2,
VAR98 = 1,
VAR192 = 1,
VAR113 = 0,
VAR114 = 0,
VAR171 = 8,
VAR189 = 32,
VAR115 = 1,
VAR178 = 72,
VAR32 = 1, VAR53 = 13, VAR175 = 10, VAR100 = 3,
VAR195 = 1,
VAR9 = 1,
VAR71 = 0,
VAR36 = 4, VAR157 = 4, VAR185 = 4, VAR101 = 5, VAR48 = 4, VAR165 = 6, VAR7 = 9, VAR124 = 14, VAR190 = ... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small_credit_on_input.v | 1,834 | module MODULE1 #( parameter VAR7(VAR10 )
, parameter VAR7(VAR12 )
)
( input VAR3
, input VAR5
, input [VAR10-1:0] VAR8
, input VAR14
, output logic VAR16
, output VAR11
, output [VAR10-1:0] VAR2
, input VAR4
);
logic ready;
VAR1 @ (posedge VAR3)
if (VAR5)
VAR16 <= 0;
else
VAR16 <= VAR4;
VAR6 #( .VAR10(VAR10)
, .VAR12(V... | bsd-3-clause |
emeb/icehat | verilog/src/rpi_tst.v | 3,521 | module MODULE1(
input VAR35,
input VAR37,
output VAR26,
input VAR9,
output wire VAR4,
output wire VAR32,
output wire VAR27
);
parameter VAR11 = 32'h1CE50100;
wire clk;
VAR50 #(.VAR3("0b00")) VAR10 (
.VAR2(1'b1),
.VAR16(1'b1),
.VAR29(clk)
) ;
reg [3:0] VAR6 = 4'hf;
reg reset = 1'b1;
always @(posedge clk)
begin
reset <= ... | mit |
LSaldyt/qnp | output/vs/var11_multi.v | 1,025 | module MODULE1 (VAR12, VAR8, VAR6, VAR7, VAR17, VAR15, VAR3, VAR14, VAR13, VAR11, VAR5, valid);
input VAR12, VAR8, VAR6, VAR7, VAR17, VAR15, VAR3, VAR14, VAR13, VAR11, VAR5;
output valid;
wire [7:0] VAR4 = 8'd107;
wire [7:0] VAR16 = 8'd60;
wire [7:0] VAR1 = 8'd60;
wire [7:0] VAR10 =
VAR12 * 8'd4
+ VAR8 * 8'd8
+ VAR6 * ... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v | 5,176 | module MODULE1(addr, VAR10, VAR11, VAR12);
parameter VAR4 = VAR2;
input [1:0] addr;
input [VAR13-1:0] VAR10;
input [VAR4-1:0] VAR11;
output [VAR4-1:0] VAR12;
reg [7:0] VAR6;
reg [7:0] VAR5;
reg [7:0] VAR3;
reg [7:0] VAR1;
assign VAR12 = {VAR6, VAR5, VAR3, VAR1};
always @(VAR10 or addr or VAR11) begin
casex({VAR10, addr... | gpl-2.0 |
swallat/yosys | techlibs/xilinx/brams_map.v | 8,255 | module \VAR25 (VAR38, VAR8, VAR6, VAR33, VAR51, VAR18, VAR49, VAR41);
parameter VAR15 = 1;
parameter VAR24 = 1;
parameter [36863:0] VAR61 = 36864'VAR30;
input VAR38;
input VAR8;
input [8:0] VAR6;
output [71:0] VAR33;
input VAR51;
input [8:0] VAR18;
input [71:0] VAR49;
input [7:0] VAR41;
wire [15:0] VAR19 = {VAR6, 6'b0}... | isc |
lbl-cal/StanfordNoC | router/src/clib/c_wf_alloc.v | 5,278 | module MODULE1
(clk, reset, VAR26, VAR19, VAR23, VAR7, VAR22);
parameter VAR15 = 8;
parameter VAR21 = 1;
parameter VAR12 = 0;
parameter VAR6 = VAR5;
parameter VAR14 = VAR20;
input clk;
input reset;
input VAR26;
input [0:VAR21*VAR15*VAR15-1] VAR19;
output [0:VAR21*VAR15*VAR15-1] VAR23;
wire [0:VAR21*VAR15*VAR15-1] VAR23... | bsd-2-clause |
ludisu13/Estructuras2 | Tarea_final_Decodificador/generador_decodificador.v | 1,435 | module MODULE2(
output clk, VAR2, VAR11, VAR5, VAR3, VAR10, VAR8;
output [7:0] VAR9;
output [15:0] VAR7;
);
MODULE1 MODULE1(clk);
VAR6 VAR4(VAR9, VAR2, VAR11, VAR5, VAR3, VAR10, VAR8, VAR7);
endmodule
module MODULE1(clk);
output reg clk;
begin
begin
begin | gpl-3.0 |
bgamari/timetag-fpga | fx2_timetag.v | 1,748 | module MODULE1(
VAR11,
VAR36,
VAR2,
VAR17,
VAR35,
VAR21,
VAR12,
VAR40,
VAR7,
VAR16,
VAR8,
VAR9,
VAR13
);
input VAR11;
input [2:0] VAR36;
output VAR2;
output VAR17;
output VAR35;
output VAR21;
output VAR12;
inout [7:0] VAR40;
output [1:0] VAR7;
input VAR16;
input [3:0] VAR9;
output [3:0] VAR8;
output [1:0] VAR13;
wire c... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.v | 2,020 | module MODULE1 (
VAR3,
VAR1 ,
VAR5 ,
VAR2 ,
VAR7
);
input VAR3;
input VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR7 ;
VAR6 VAR4 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE1 ();
supply1 VAR3;
supply1 VAR1 ;
supply0 VAR5 ;
supply1 VAR2 ;
supply0 VAR7 ;
VAR6 VAR4 ();
endmodul... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_1.behavioral.v | 2,113 | module MODULE1( VAR9, VAR11, VAR10 );
input VAR9, VAR11;
output VAR10;
reg VAR8;
VAR3 VAR6(.VAR9(VAR9),.VAR11(VAR11),.VAR10(VAR10),.VAR8(VAR8));
VAR3 VAR7(.VAR9(VAR9),.VAR11(VAR11),.VAR10(VAR10),.VAR8(VAR8));
not VAR5(VAR2,VAR11);
buf VAR4(VAR1,VAR11); | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/vfabric_down_converter.v | 4,017 | module MODULE1(VAR18, VAR8, VAR20,
VAR17, VAR7, VAR13,
VAR21, VAR9, VAR1);
parameter VAR12 = 32;
parameter VAR19 = 8;
input VAR18, VAR8, VAR20;
input [VAR12-1:0] VAR17;
input VAR7;
output VAR13;
output [VAR19-1:0] VAR21;
input VAR9;
output VAR1;
parameter VAR5 = 3'b100;
parameter VAR10 = 3'b000;
parameter VAR15 = 3'b00... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2i/sky130_fd_sc_ms__mux2i.pp.symbol.v | 1,347 | module MODULE1 (
input VAR7 ,
input VAR8 ,
output VAR1 ,
input VAR3 ,
input VAR2 ,
input VAR6,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor3/sky130_fd_sc_hdll__xor3.behavioral.pp.v | 1,863 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR6 ,
VAR13 ,
VAR11,
VAR14,
VAR4 ,
VAR9
);
output VAR3 ;
input VAR2 ;
input VAR6 ;
input VAR13 ;
input VAR11;
input VAR14;
input VAR4 ;
input VAR9 ;
wire VAR1 ;
wire VAR5;
xor VAR8 (VAR1 , VAR2, VAR6, VAR13 );
VAR10 VAR7 (VAR5, VAR1, VAR11, VAR14);
buf VAR12 (VAR3 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2b/sky130_fd_sc_lp__and2b_m.v | 2,133 | module MODULE2 (
VAR2 ,
VAR3 ,
VAR8 ,
VAR7,
VAR5,
VAR1 ,
VAR6
);
output VAR2 ;
input VAR3 ;
input VAR8 ;
input VAR7;
input VAR5;
input VAR1 ;
input VAR6 ;
VAR4 VAR9 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR2 ,
VAR3,
VAR8
);
output VAR2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2.functional.v | 1,309 | module MODULE1 (
VAR5,
VAR2
);
output VAR5;
input VAR2;
wire VAR1;
buf VAR3 (VAR1, VAR2 );
buf VAR4 (VAR5 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2i/sky130_fd_sc_ms__mux2i_4.v | 2,214 | module MODULE2 (
VAR1 ,
VAR10 ,
VAR8 ,
VAR3 ,
VAR6,
VAR5,
VAR7 ,
VAR4
);
output VAR1 ;
input VAR10 ;
input VAR8 ;
input VAR3 ;
input VAR6;
input VAR5;
input VAR7 ;
input VAR4 ;
VAR9 VAR2 (
.VAR1(VAR1),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_mm_interconnect_0_avalon_st_adapter_007.v | 6,185 | module MODULE1 #(
parameter VAR19 = 130,
parameter VAR5 = 0,
parameter VAR8 = 130,
parameter VAR3 = 0,
parameter VAR4 = 0,
parameter VAR20 = 0,
parameter VAR1 = 1,
parameter VAR22 = 1,
parameter VAR13 = 0,
parameter VAR11 = 130,
parameter VAR24 = 0,
parameter VAR15 = 1,
parameter VAR10 = 0,
parameter VAR9 = 1,
paramete... | gpl-3.0 |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/video_scaler_mul_kbM.v | 1,445 | module MODULE2(clk, VAR14, VAR5, VAR3, VAR16);
input clk;
input VAR14;
input[28 - 1 : 0] VAR5;
input[20 - 1 : 0] VAR3;
output[48 - 1 : 0] VAR16;
reg signed [28 - 1 : 0] VAR11;
reg signed [20 - 1 : 0] VAR18;
wire signed [48 - 1 : 0] VAR6;
reg signed [48 - 1 : 0] VAR13;
reg signed [48 - 1 : 0] VAR2;
reg signed [48 - 1 : ... | mit |
sabertazimi/hust-lab | digitalLogic/design/washmach_design/src/selector_mode.v | 1,926 | module MODULE1
(
input [31:0]clk,
input VAR7,
input VAR3,
input VAR6,
input [1:0]VAR8,
output reg VAR2,
output reg [2:0] VAR4
);
reg VAR1;
wire VAR5; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tap/sky130_fd_sc_hd__tap.blackbox.v | 1,208 | module MODULE1 ();
supply1 VAR2;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
zaqwes8811/hdl-fpga | ip-cores/rtl_vlog/counters_lib.v | 13,510 | module MODULE10(
clk, rst, VAR14,
VAR15, VAR11, VAR9, VAR16
);
parameter VAR6 = 7;
parameter VAR2 = 8;
input clk, rst, VAR14;
input VAR15;
input [VAR2-1:0] VAR9;
output VAR11;
reg VAR3;
assign VAR11 = VAR3;
output [VAR2-1:0] VAR16;
reg [VAR2-1:0] VAR12; assign VAR16 = VAR12;
always @(posedge clk or posedge rst) begin
i... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_6sig.v | 10,566 | module MODULE1(VAR4 ,VAR17 ,VAR5 ,VAR8 ,
VAR82 ,VAR19 ,VAR58 ,VAR37 ,VAR16 ,VAR27 ,
VAR34 ,VAR52 ,VAR43 ,VAR13 ,VAR50 ,
VAR21 ,VAR61 ,VAR46 ,VAR45 ,VAR6 ,
VAR70 ,VAR14 ,VAR71 ,VAR74 ,VAR68 ,VAR60 ,VAR3 ,VAR15 ,
VAR51 ,VAR76 ,VAR29 ,VAR59 ,
VAR83 ,VAR81 ,VAR7 ,VAR36, VAR55 ,VAR79 ,
VAR42 ,VAR80 ,VAR44 ,VAR25 ,VAR75 ,
VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211oi/sky130_fd_sc_hs__a211oi_2.v | 2,234 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR4 ,
VAR2 ,
VAR1 ,
VAR6,
VAR3
);
output VAR5 ;
input VAR8 ;
input VAR4 ;
input VAR2 ;
input VAR1 ;
input VAR6;
input VAR3;
VAR9 VAR7 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR5 ,
VAR8,
VAR4,
VAR2,
VAR1
);... | apache-2.0 |
oblivioncth/DE0-Verilog-Processor | src/mux_4to1_19bit.v | 1,240 | module MODULE1(VAR8, VAR22, VAR11, VAR4, VAR15, VAR21);
input[18:0] VAR22, VAR11, VAR4, VAR15;
input[1:0] VAR8;
output[18:0] VAR21;
VAR19 VAR20(VAR8, VAR22[0], VAR11[0], VAR4[0], VAR15[0], VAR21[0]);
VAR19 VAR10(VAR8, VAR22[1], VAR11[1], VAR4[1], VAR15[1], VAR21[1]);
VAR19 VAR23(VAR8, VAR22[2], VAR11[2], VAR4[2], VAR15... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/dest_axi_mm.v | 7,266 | module MODULE1 (
input VAR29,
input VAR66,
input VAR1,
output VAR18,
input [31:VAR37] VAR59,
input [VAR21-1:0] VAR50,
input [VAR37-1:0] VAR7,
input enable,
output VAR49,
input VAR74,
input VAR52,
output VAR51,
output VAR55,
input VAR20,
output [1:0] VAR65,
output VAR53,
input [VAR43-1:0] VAR72,
output [VAR43-1:0] VAR83... | gpl-3.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Proyectos Funcionales Francis Jeffrey/CORDICO/CORDICO.srcs/sources_1/imports/Floating-Point-Unit-master/Coprocesador_CORDIC_RTL/sine_cosine_CORDIC/CORDIC_Arch2.v | 20,547 | module MODULE1 #(parameter VAR93 = 32, parameter VAR45 = 8, parameter VAR53 = 23, parameter VAR139=26, parameter VAR27 = 5)/*#(parameter VAR93 = 64, parameter VAR45 = 11, parameter VAR53 = 52, parameter VAR139 = 55, parameter VAR27 = 6) (
input wire clk, input wire rst, input wire VAR41, input wire VAR123, input wire V... | gpl-3.0 |
kyzhai/NUNY | src/hardware/diploma_new_bb.v | 5,052 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ha/sky130_fd_sc_ls__ha.behavioral.v | 1,511 | module MODULE1 (
VAR13,
VAR11 ,
VAR3 ,
VAR7
);
output VAR13;
output VAR11 ;
input VAR3 ;
input VAR7 ;
supply1 VAR5;
supply0 VAR4;
supply1 VAR9 ;
supply0 VAR14 ;
wire VAR6;
wire VAR1 ;
and VAR10 (VAR6, VAR3, VAR7 );
buf VAR12 (VAR13 , VAR6 );
xor VAR8 (VAR1 , VAR7, VAR3 );
buf VAR2 (VAR11 , VAR1 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_2.functional.v | 1,218 | module MODULE1( VAR10, VAR1, VAR8, VAR6 );
input VAR6, VAR8, VAR1;
output VAR10;
wire VAR11;
not VAR3( VAR11, VAR6 );
wire VAR2;
not VAR9( VAR2, VAR8 );
wire VAR7;
not VAR5( VAR7, VAR1 );
or VAR4( VAR10, VAR11, VAR2, VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_nsr/sky130_fd_sc_ls__udp_dff_nsr.blackbox.v | 1,345 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR4,
VAR3,
VAR1
);
output VAR5 ;
input VAR2 ;
input VAR4;
input VAR3;
input VAR1 ;
endmodule | apache-2.0 |
tommythorn/yari | shared/rtl/soclib/sram_ctrl.v | 4,837 | module MODULE1
(input wire VAR19
,input wire rst
,output VAR11
,input [1:0] VAR7
,input [29:0] VAR36
,input VAR23
,input VAR12
,input [31:0] VAR20
,input [3:0] VAR33
,output reg [31:0] VAR1
,output reg [1:0] VAR34 = 0
,output reg [29:0] VAR32
,inout wire [31:0] VAR28
,output reg VAR6 = 1
,output reg [3:0] VAR5
,output ... | gpl-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/HPS/synthesis/HPS.v | 6,599 | module MODULE1 (
output wire [14:0] VAR53, output wire [2:0] VAR31, output wire VAR67, output wire VAR59, output wire VAR44, output wire VAR58, output wire VAR50, output wire VAR57, output wire VAR70, output wire VAR42, inout wire [31:0] VAR76, inout wire [3:0] VAR36, inout wire [3:0] VAR8, output wire VAR1, output wir... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_4.behavioral.v | 5,359 | module MODULE1( VAR2, VAR3, VAR9, VAR8, VAR10, VAR1, VAR7 );
input VAR10, VAR1, VAR7, VAR9, VAR2, VAR3;
output VAR8;
VAR5 VAR6(.VAR2(VAR2),.VAR3(VAR3),.VAR9(VAR9),.VAR8(VAR8),.VAR10(VAR10),.VAR1(VAR1),.VAR7(VAR7));
VAR5 VAR4(.VAR2(VAR2),.VAR3(VAR3),.VAR9(VAR9),.VAR8(VAR8),.VAR10(VAR10),.VAR1(VAR1),.VAR7(VAR7)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_2.functional.pp.v | 1,804 | module MODULE1( VAR6, VAR26, VAR4, VAR27, VAR13, VAR2, VAR22, VAR19, VAR21, VAR16 );
input VAR27, VAR4, VAR2, VAR6, VAR13, VAR26, VAR19, VAR21, VAR16;
output VAR22;
not VAR29( VAR31, VAR2 );
not VAR24( VAR28, VAR13 );
wire VAR30;
not VAR20( VAR30, VAR4 );
wire VAR25;
not VAR5( VAR25, VAR6 );
wire VAR17;
and VAR9( VAR17... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerPeripheralHdlAdi_tc.v | 2,685 | module MODULE1
(
VAR14,
reset,
VAR15,
VAR9,
VAR8,
VAR5,
VAR4
);
input VAR14;
input reset;
input VAR15;
output VAR9;
output VAR8;
output VAR5;
output VAR4;
reg [10:0] VAR13; wire VAR7;
reg VAR12;
wire VAR6;
reg VAR3;
wire VAR10;
always @ ( posedge VAR14)
begin: VAR2
if (reset == 1'b1) begin
VAR13 <= 11'b00000000001;
end... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dff_pr/sky130_fd_sc_hd__udp_dff_pr.symbol.v | 1,317 | module MODULE1 (
input VAR2 ,
output VAR4 ,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3/sky130_fd_sc_lp__and3.pp.symbol.v | 1,280 | module MODULE1 (
input VAR3 ,
input VAR1 ,
input VAR8 ,
output VAR5 ,
input VAR7 ,
input VAR6,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr.functional.pp.v | 1,940 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR7 ,
VAR12 ,
VAR13,
VAR3 ,
VAR9
);
output VAR11 ;
input VAR2 ;
input VAR7 ;
input VAR12 ;
input VAR13;
input VAR3 ;
input VAR9 ;
wire VAR10 ;
wire VAR8;
buf VAR5 (VAR10 , VAR2 );
VAR4 VAR1 (VAR8, VAR10, VAR13, VAR12);
buf VAR6 (VAR11 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25.functional.v | 1,343 | module MODULE1 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
wire VAR2;
buf VAR1 (VAR2, VAR4 );
buf VAR3 (VAR5 , VAR2 );
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/ethernet_port_interface.v | 13,330 | module MODULE1
(
input wire clk,
input wire reset,
input wire VAR138,
input wire [26:0] VAR81,
input wire VAR3,
output wire [31:0] VAR39,
input wire VAR182,
input wire [31:0] VAR85,
output wire VAR159,
input wire [7:0] VAR58,
output wire VAR13,
input wire VAR119,
input wire [5:0] VAR115,
input wire VAR169,
input wire V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22a/sky130_fd_sc_ls__o22a_1.v | 2,339 | module MODULE2 (
VAR5 ,
VAR4 ,
VAR8 ,
VAR2 ,
VAR10 ,
VAR6,
VAR11,
VAR3 ,
VAR9
);
output VAR5 ;
input VAR4 ;
input VAR8 ;
input VAR2 ;
input VAR10 ;
input VAR6;
input VAR11;
input VAR3 ;
input VAR9 ;
VAR1 VAR7 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR3(VAR3),
.... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_02/02 verilog/proyecto directo/Microfono/FSM.v | 1,693 | module MODULE1(VAR12,VAR9,VAR11,VAR4,VAR2,VAR5,VAR3, VAR8);
input wire VAR12;
input wire VAR9;
input wire VAR11;
input wire VAR4;
input wire VAR2;
output reg VAR5;
output reg VAR3;
output reg VAR8;
localparam VAR13 = 2'b00;
localparam VAR1 = 2'b01;
localparam VAR10 = 2'b11;
reg [1:0] VAR7 = VAR13;
reg [1:0] VAR6 = VAR1... | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_avalon_master_171/synth/ghrd_10as066n2_f2sdram2_m_altera_jtag_avalon_master_171_wqhllki.v | 25,739 | module MODULE1 #(
parameter VAR23 = 0,
parameter VAR22 = 50000,
parameter VAR33 = 2
) (
input wire VAR17, input wire VAR12, output wire [31:0] VAR20, input wire [31:0] VAR47, output wire VAR31, output wire VAR25, output wire [31:0] VAR34, input wire VAR9, input wire VAR2, output wire [3:0] VAR38, output wire VAR10 );
w... | mit |
glennchid/font5-firmware | src/verilog/synthesis/auxOut_select.v | 1,235 | module MODULE1(
input clk,
input VAR4,
input VAR3,
input VAR1,
output reg VAR2,
output reg VAR6,
output reg VAR7,
output reg VAR8
);
reg VAR10;
reg VAR5;
always @(posedge clk) begin
VAR10 <= VAR4;
VAR5 <= VAR10;
VAR2 <= (VAR5) ? VAR3 : 1'VAR9;
VAR6 <= (VAR5) ? VAR1 : 1'VAR9;
VAR7 <= (VAR5) ? 1'VAR9 : ~VAR3; VAR8 <= (VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4/sky130_fd_sc_ms__or4.functional.v | 1,286 | module MODULE1 (
VAR5,
VAR6,
VAR2,
VAR8,
VAR7
);
output VAR5;
input VAR6;
input VAR2;
input VAR8;
input VAR7;
wire VAR4;
or VAR3 (VAR4, VAR7, VAR8, VAR2, VAR6 );
buf VAR1 (VAR5 , VAR4 );
endmodule | apache-2.0 |
INTI-CMNB/Lattuino_IP_Core | Work/lattuino_1_bl_8.v | 2,367 | module MODULE1
parameter VAR1=16, parameter VAR10=0, parameter VAR6=13 )
(
input VAR4,
input [VAR6-1:0] VAR9,
output [VAR1-1:0] VAR2,
input VAR7,
input [VAR1-1:0] VAR3
);
localparam VAR11=2**VAR6;
reg [VAR6-1:0] VAR8;
reg [VAR1-1:0] VAR5[0:VAR11-1]; | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/byte_lane.v | 28,116 | module MODULE1 #(
parameter VAR83 = "VAR241", parameter VAR122 = "VAR19",
parameter VAR101 = 12'b111111111111,
parameter VAR270 = 12'b000000000000,
parameter VAR260 = "VAR248",
parameter VAR229 = "VAR272",
parameter VAR17 = 1,
parameter VAR214 = "VAR272",
parameter VAR166 = 4,
parameter VAR219 = 1,
parameter VAR182 = 1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill/sky130_fd_sc_hs__fill.behavioral.v | 1,110 | module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211ai/sky130_fd_sc_hdll__o211ai.blackbox.v | 1,376 | module MODULE1 (
VAR4 ,
VAR1,
VAR3,
VAR6,
VAR2
);
output VAR4 ;
input VAR1;
input VAR3;
input VAR6;
input VAR2;
supply1 VAR9;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
azonenberg/antikernel-ipcores | noc/rpcv3/RPCv3RouterCrossbar.v | 8,600 | module MODULE1
parameter VAR13 = 32,
parameter VAR21 = 1'b0,
parameter VAR22 = 4,
parameter VAR19 = 32'h20202020,
parameter VAR14 = {4'b1111},
parameter VAR24 = 32'h20202020,
parameter VAR10 = 4'h0,
parameter VAR1 = 4'h0
)
(
input wire clk,
output reg[(VAR22+4)-1 : 0] VAR7 = 0,
input wire[(VAR22+4)-1 : 0] VAR5,
input w... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/dram_sc_0_rep2.v | 5,330 | module MODULE1(
VAR34, VAR29,
VAR35, VAR36,
VAR4, VAR14,
VAR6, VAR23,
VAR20, VAR33, VAR3,
VAR9, VAR38,
VAR7, VAR16,
VAR24, VAR15,
VAR10, VAR18,
VAR21, VAR27, VAR22,
VAR25, VAR2,
VAR11, VAR26, VAR1,
VAR31, VAR17, VAR12,
VAR30, VAR37, VAR8,
VAR32, VAR28,
VAR5, VAR19,
VAR13
);
input [127:0] VAR21;
input [27:0] VAR27;
outp... | gpl-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/altpllpll_bb.v | 11,641 | module MODULE1 (
VAR1,
VAR3,
VAR2);
input VAR1;
output VAR3;
output VAR2;
endmodule | apache-2.0 |
cliffordwolf/picorv32 | picosoc/spiflash.v | 8,549 | module MODULE1 (
input VAR33,
input clk,
inout VAR21, inout VAR20, inout VAR3,
inout VAR16
);
localparam VAR28 = 0;
localparam integer VAR7 = 8;
reg [7:0] buffer;
integer VAR36 = 0;
integer VAR37 = 0;
integer VAR22 = 0;
reg [7:0] VAR31;
reg [7:0] VAR6 = 0;
reg [23:0] VAR19;
reg [7:0] VAR26;
reg [7:0] VAR8;
reg VAR32;
r... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31ai/sky130_fd_sc_hs__o31ai.behavioral.pp.v | 1,928 | module MODULE1 (
VAR10,
VAR13,
VAR2 ,
VAR15 ,
VAR11 ,
VAR5 ,
VAR14
);
input VAR10;
input VAR13;
output VAR2 ;
input VAR15 ;
input VAR11 ;
input VAR5 ;
input VAR14 ;
wire VAR14 VAR7 ;
wire VAR9 ;
wire VAR3;
or VAR1 (VAR7 , VAR11, VAR15, VAR5 );
nand VAR12 (VAR9 , VAR14, VAR7 );
VAR6 VAR8 (VAR3, VAR9, VAR10, VAR13);
buf ... | apache-2.0 |
nickdesaulniers/Omicron | execute.v | 1,812 | module MODULE1(
input VAR1,
input VAR15,
input [6:0] VAR19,
input [15:0] VAR12,
input [15:0] VAR8,
input [6:0] VAR18,
input [2:0] VAR3,
input [10:0] VAR7,
input VAR14,
output [6:0] VAR2,
output VAR16,
output [15:0] VAR6,
output [15:0] VAR13,
output [2:0] VAR5
);
wire [15:0] VAR9;
assign VAR9 = VAR14 ? VAR18 : VAR8;
ass... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1.behavioral.v | 1,405 | module MODULE1 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR6;
supply0 VAR4;
supply1 VAR9 ;
supply0 VAR1 ;
wire VAR5;
buf VAR7 (VAR5, VAR3 );
buf VAR2 (VAR8 , VAR5 );
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_03_a/hdl/verilog/user_logic.v | 28,048 | module MODULE1
(
VAR55,
VAR25,
VAR116,
VAR72,
VAR19,
VAR46,
VAR88,
VAR12,
VAR83,
VAR59,
VAR99,
VAR112,
VAR47,
VAR130,
VAR73,
VAR40,
VAR82,
VAR68,
VAR95,
VAR10,
VAR121,
VAR51,
VAR109,
VAR9,
VAR102,
VAR139,
VAR119,
VAR103,
VAR118,
VAR106,
VAR7,
VAR29,
VAR98,
VAR54,
VAR5,
VAR57,
VAR8,
VAR122,
VAR97,
VAR131,
VAR45,
VAR41,
... | bsd-2-clause |
flycrow/pyxdl | logicanalyzer/serial_wb_mcu.v | 6,820 | module MODULE1(
VAR27, VAR32,
VAR14, VAR16,
VAR25,
VAR7,
VAR13,
VAR15,
VAR28
);
input VAR27;
input VAR32;
output [9:0] VAR14;
input [15:0] VAR16;
output reg [7:0] VAR25;
output reg [7:0] VAR7;
output VAR13;
input wire [7:0] VAR15;
output VAR28;
wire VAR27;
wire VAR32;
reg [9:0] VAR14;
wire [15:0] VAR16;
reg VAR13;
reg ... | gpl-2.0 |
alexforencich/xfcp | rtl/xfcp_mod_axil.v | 26,237 | module MODULE1 #
(
parameter VAR5 = 16'h0001,
parameter VAR29 = "VAR8 VAR10",
parameter VAR12 = 0,
parameter VAR46 = "",
parameter VAR17 = 16,
parameter VAR2 = 32,
parameter VAR14 = 32,
parameter VAR9 = (VAR2/8)
)
(
input wire clk,
input wire rst,
input wire [7:0] VAR38,
input wire VAR18,
output wire VAR26,
input wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_4.v | 2,262 | module MODULE1 (
VAR4,
VAR9 ,
VAR6,
VAR2 ,
VAR8,
VAR5,
VAR1 ,
VAR7
);
output VAR4;
input VAR9 ;
input VAR6;
input VAR2 ;
input VAR8;
input VAR5;
input VAR1 ;
input VAR7 ;
VAR3 VAR10 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR... | apache-2.0 |
nlsynth/nli | lib/fp/fp16baddsub.v | 6,354 | module MODULE1(
input clk,
input rst,
input [15:0] VAR65,
input [15:0] VAR22,
input VAR53,
output [15:0] VAR54,
output [15:0] VAR12,
output VAR10,
output VAR3);
wire [15:0] VAR37;
wire [15:0] VAR27;
wire VAR4;
wire VAR16;
wire VAR1;
wire [15:0] VAR56;
wire VAR25;
wire [7:0] VAR8;
wire [7:0] VAR36;
wire VAR11;
wire VAR4... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtp/sky130_fd_sc_hd__sdfrtp.behavioral.pp.v | 2,884 | module MODULE1 (
VAR15 ,
VAR31 ,
VAR17 ,
VAR22 ,
VAR3 ,
VAR29,
VAR4 ,
VAR13 ,
VAR12 ,
VAR2
);
output VAR15 ;
input VAR31 ;
input VAR17 ;
input VAR22 ;
input VAR3 ;
input VAR29;
input VAR4 ;
input VAR13 ;
input VAR12 ;
input VAR2 ;
wire VAR6 ;
wire VAR7 ;
wire VAR27 ;
reg VAR23 ;
wire VAR24 ;
wire VAR14 ;
wire VAR1 ;
wi... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_non_blocking_decode.v | 1,692 | module MODULE1
import VAR23::*;
(
input VAR37 VAR26
, output VAR41 VAR32
);
VAR20 begin
case (VAR26)
VAR10, VAR14: VAR32.VAR8 = 2'b11;
VAR42, VAR6, VAR34: VAR32.VAR8 = 2'b10;
VAR11, VAR16, VAR36: VAR32.VAR8 = 2'b01;
VAR13, VAR43, VAR17: VAR32.VAR8 = 2'b00;
default: VAR32.VAR8 = 2'b00;
endcase
end
assign VAR32.VAR33 = (... | bsd-3-clause |
Mw1993/5CPipelinedCPU | unified_mem.v | 3,552 | module MODULE1(clk,VAR12,addr,VAR15,VAR8,VAR5,VAR7,VAR10);
input clk,VAR12;
input VAR15,VAR8;
input [14:0] addr; input [31:0] VAR5;
output reg [31:0] VAR7;
output reg VAR10;
reg [15:0] VAR9[0:65535];
localparam VAR13 = 2'b00;
localparam VAR6 = 2'b01;
localparam VAR11 = 2'b10;
reg [14:0] VAR1; reg [1:0] state,VAR16; reg... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/usdrx1/a5gt/system_top.v | 17,387 | module MODULE1 (
VAR133,
VAR206,
VAR164,
VAR162,
VAR216,
VAR122,
VAR214,
VAR83,
VAR301,
VAR17,
VAR2,
VAR46,
VAR264,
VAR190,
VAR145,
VAR107,
VAR71,
VAR148,
VAR120,
VAR274,
VAR15,
VAR81,
VAR41,
VAR62,
VAR151,
VAR121,
VAR192,
VAR175,
VAR186,
VAR152,
VAR259,
VAR33,
VAR24,
VAR39,
VAR260,
VAR154,
VAR111,
VAR225,
VAR127,
VAR1... | gpl-3.0 |
AngelTerrones/Antares | Hardware/verilog/antares_idex_register.v | 9,850 | module MODULE1 (
input clk, input rst, input [4:0] VAR44, input [31:0] VAR3, input [31:0] VAR38, input VAR45, input VAR32, input VAR25, input [1:0] VAR54, input [1:0] VAR58, input [1:0] VAR20, input VAR56, input VAR5, input VAR36, input [4:0] VAR59, input [4:0] VAR39, input [3:0] VAR46,
input VAR57, input [15:0] VAR53,... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_dq_pscan.v | 2,920 | module MODULE1(VAR2 ,VAR11 ,VAR35 ,VAR39 ,clk ,
VAR15 ,VAR3 ,VAR34 );
output VAR11 ;
input VAR2 ;
input VAR35 ;
input VAR39 ;
input clk ;
input VAR15 ;
input VAR3 ;
input VAR34 ;
supply0 VAR44 ;
wire VAR1 ;
wire VAR13 ;
wire VAR7 ;
wire VAR33 ;
wire VAR29 ;
wire VAR46 ;
wire VAR5 ;
wire VAR42 ;
wire VAR19 ;
wire VAR25 ... | gpl-2.0 |
csturton/wirepatch | system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v | 6,623 | module MODULE1 (
VAR8,
VAR13,
VAR18,
VAR1,
VAR15,
VAR6,
VAR19,
VAR14,
VAR7
);
input [VAR9 - 1:0] VAR8;
input VAR13;
input VAR18;
input VAR1;
input VAR15;
input VAR6;
output [VAR9 - 1:0] VAR19;
output VAR14;
output VAR7;
reg VAR3;
wire [2:1] VAR16;
reg VAR10, VAR17, VAR5;
reg VAR11, VAR12, VAR2;
reg VAR4;
reg VAR7;
alwa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pr_pp_pkg_s/sky130_fd_sc_hs__udp_dff_pr_pp_pkg_s.symbol.v | 1,498 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR4 ,
input VAR7 ,
input VAR3,
input VAR8 ,
input VAR2 ,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s.symbol.v | 1,358 | module MODULE1 (
input VAR2,
output VAR1
);
supply1 VAR3;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3b/sky130_fd_sc_hdll__nor3b.pp.symbol.v | 1,349 | module MODULE1 (
input VAR5 ,
input VAR7 ,
input VAR6 ,
output VAR4 ,
input VAR2 ,
input VAR8,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
sehugg/8bitworkshop | presets/verilog/cpu8.v | 7,395 | module MODULE1(VAR1, VAR5, VAR6, VAR7, VAR10);
parameter VAR3 = 8; input [VAR3-1:0] VAR1; input [VAR3-1:0] VAR5; input VAR6; input [3:0] VAR7; output reg [VAR3:0] VAR10;
always @
if (VAR9[7] == 0)
VAR8 = VAR4[VAR9[6:0]];
else
VAR8 = VAR2[VAR9[6:0]]; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.v | 2,154 | module MODULE1 (
VAR4,
VAR9,
VAR6 ,
VAR2,
VAR3,
VAR8 ,
VAR5
);
output VAR4;
input VAR9;
input VAR6 ;
input VAR2;
input VAR3;
input VAR8 ;
input VAR5 ;
VAR1 VAR7 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR4,
VAR9,
VAR6
);
output VAR4;
inpu... | apache-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/flash_writer.v | 3,064 | module MODULE1(
input VAR6,
input VAR22,
input VAR15,
input VAR26 ,
input VAR10 ,
input VAR7 ,
input VAR17 ,
input VAR23 ,
input VAR24,
input VAR13 ,
output VAR11,
output VAR25,
output [21:0] VAR4,
output reg [3:0] VAR2,
output VAR21
);
always @(posedge VAR26)begin
case ({VAR24,VAR23,VAR13,VAR17,VAR7,VAR10})
6'b000100:... | apache-2.0 |
kyzhai/NUNY | src/hardware/diploma_new.v | 6,442 | module MODULE1 (
address,
VAR44,
VAR23);
input [11:0] address;
input VAR44;
output [11:0] VAR23;
tri1 VAR44;
wire [11:0] VAR4;
wire [11:0] VAR23 = VAR4[11:0];
VAR10 VAR22 (
.VAR29 (address),
.VAR24 (VAR44),
.VAR12 (VAR4),
.VAR28 (1'b0),
.VAR31 (1'b0),
.VAR39 (1'b1),
.VAR16 (1'b0),
.VAR11 (1'b0),
.VAR47 (1'b1),
.VAR20 (... | gpl-2.0 |
ellisgl/Driver-YL-3 | mojo_top.v | 2,426 | module MODULE1(
input clk,
input VAR12,
output VAR4, output VAR7, output VAR2 );
reg [63:0] VAR18;
reg VAR6;
reg [2:0] VAR8 = 3'b0;
reg [16:0] VAR1 = 17'b0;
wire [7:0] VAR9 [0:5][0:7];
wire rst = ~VAR12; wire ready;
localparam VAR20 = 17'd124999;
assign VAR9[0][0] = " ";
assign VAR9[0][1] = " ";
assign VAR9[0][2] = " "... | bsd-3-clause |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_buffer.v | 4,029 | module MODULE1
parameter
VAR22 = 3,
VAR9 = 8,
VAR56 = 0
)
(
VAR30,
VAR27,
VAR48,
VAR23,
VAR8,
VAR37,
VAR24,
VAR59
);
localparam VAR33 = VAR16(VAR22);
localparam VAR28 = (VAR56) ? "VAR38" : "VAR6";
input VAR30;
input VAR27;
input VAR48;
input [VAR22-1:0] VAR23;
input [VAR9-1:0] VAR8;
input VAR37;
input [VAR22-1:0] VAR24... | gpl-2.0 |
Elphel/x393_sata | host/elastic1632.v | 9,357 | module MODULE1#(
parameter VAR46 = 4, parameter VAR20 = 7 )(
input VAR17,
input VAR11,
input VAR15,
input [1:0] VAR42,
input [1:0] VAR29,
input [1:0] VAR49,
input [15:0] VAR8,
output VAR16,
output reg [3:0] VAR62,
output reg [3:0] VAR28,
output reg [3:0] VAR34,
output reg [31:0] VAR33,
output VAR54,
output VAR45
);
loc... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/8-way/src/ip_dram/phy/mig_7series_v2_3_ddr_of_pre_fifo.v | 8,024 | module MODULE1 #
(
parameter VAR14 = 100, parameter VAR20 = 4, parameter VAR2 = 32 )
(
input clk, input rst, input VAR4, input VAR19, input [VAR2-1:0] din, output VAR15, output [VAR2-1:0] dout, output VAR5 );
localparam VAR7
= (VAR20 == 2) ? 1 :
((VAR20 == 3) || (VAR20 == 4)) ? 2 :
(((VAR20 == 5) || (VAR20 == 6) ||
(VA... | mit |
efabless/openlane | designs/zipdiv/src/zipdiv.v | 16,124 | module MODULE1(VAR10, VAR8, VAR16, VAR27, VAR19, VAR20,
VAR6, VAR9, VAR24, VAR2, VAR25);
parameter VAR18=32, VAR5 = 5;
input wire VAR10, VAR8;
input wire VAR16, VAR27;
input wire [(VAR18-1):0] VAR19, VAR20;
output reg VAR6, VAR9, VAR24;
output reg [(VAR18-1):0] VAR2;
output wire [3:0] VAR25;
reg VAR22;
reg [(2*VAR18-2)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31oi/sky130_fd_sc_ms__a31oi_1.v | 2,350 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR8 ,
VAR2 ,
VAR3 ,
VAR7,
VAR1,
VAR9 ,
VAR11
);
output VAR6 ;
input VAR4 ;
input VAR8 ;
input VAR2 ;
input VAR3 ;
input VAR7;
input VAR1;
input VAR9 ;
input VAR11 ;
VAR5 VAR10 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR11... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad6676/axi_ad6676.v | 9,620 | module MODULE1 (
VAR8,
VAR9,
VAR45,
VAR76,
VAR98,
VAR81,
VAR10,
VAR51,
VAR88,
VAR47,
VAR1,
VAR20,
VAR86,
VAR24,
VAR25,
VAR13,
VAR115,
VAR67,
VAR60,
VAR44,
VAR100,
VAR63,
VAR49,
VAR6,
VAR27,
VAR120,
VAR105,
VAR66,
VAR12,
VAR11);
parameter VAR123 = 0;
parameter VAR110 = 0;
parameter VAR34 = "VAR101";
input VAR8;
input [6... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22oi/sky130_fd_sc_ms__a22oi.pp.symbol.v | 1,376 | module MODULE1 (
input VAR3 ,
input VAR1 ,
input VAR2 ,
input VAR4 ,
output VAR6 ,
input VAR5 ,
input VAR7,
input VAR9,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31ai/sky130_fd_sc_ls__o31ai.functional.v | 1,447 | module MODULE1 (
VAR4 ,
VAR8,
VAR1,
VAR5,
VAR2
);
output VAR4 ;
input VAR8;
input VAR1;
input VAR5;
input VAR2;
wire VAR3 ;
wire VAR10;
or VAR7 (VAR3 , VAR1, VAR8, VAR5 );
nand VAR9 (VAR10, VAR2, VAR3 );
buf VAR6 (VAR4 , VAR10 );
endmodule | apache-2.0 |
MartinMosbeck/NoCMonitor | buildCONNECT4x4/mkOutPortFIFO.v | 20,764 | module MODULE1(VAR68,
VAR84,
VAR19,
VAR8,
VAR86,
VAR16,
VAR43,
VAR52,
VAR34,
VAR69,
VAR29,
VAR35,
VAR2,
VAR80,
VAR89,
VAR59,
VAR85);
input VAR68;
input VAR84;
input [2 : 0] VAR19;
input VAR8;
output VAR86;
input VAR16;
output VAR43;
output [2 : 0] VAR52;
output VAR34;
output VAR69;
output VAR29;
output VAR35;
output VA... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/cores/axi_sts_register_v1_0/src/axi_sts_register.v | 2,686 | module MODULE1 #
(
parameter integer VAR10 = 1024,
parameter integer VAR20 = 32,
parameter integer VAR21 = 32
)
(
input wire VAR26,
input wire VAR14,
input wire [VAR10-1:0] VAR6,
input wire [VAR21-1:0] VAR7, input wire VAR8, output wire VAR15, output wire [VAR20-1:0] VAR22, output wire [1:0] VAR3, output wire VAR2, inp... | gpl-3.0 |
PerezFederico/UART_Arquitectura | ConcatenadorNumeros.v | 4,402 | module MODULE1
(input clk, input reset, input [7:0] VAR38, input VAR39, input VAR30,
output integer VAR22, output reg VAR1
);
VAR4 VAR1 = 0;
VAR4 VAR22 = 0;
wire [7:0] VAR27; wire [5:0] VAR21; wire VAR10; wire VAR23; reg [7:0] VAR43 = 0;
reg VAR2 = 0; reg VAR19 = 0; reg VAR20 = 1;
reg [4:0] state = VAR9;
reg [4:0] VAR3... | gpl-3.0 |
qeedquan/fpga | de2-115/nios_lights/lights/synthesis/submodules/lights_onchip_memory2_0.v | 3,094 | module MODULE1 (
address,
VAR17,
VAR19,
clk,
VAR35,
VAR15,
reset,
VAR1,
write,
VAR7,
VAR30
)
;
parameter VAR32 = "MODULE1.VAR12";
output [ 31: 0] VAR30;
input [ 9: 0] address;
input [ 3: 0] VAR17;
input VAR19;
input clk;
input VAR35;
input VAR15;
input reset;
input VAR1;
input write;
input [ 31: 0] VAR7;
wire VAR24;
wi... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/vfabric_log.v | 2,275 | module MODULE1(VAR2, VAR14,
VAR1, VAR16, VAR13,
VAR5, VAR23, VAR8);
parameter VAR9 = 32;
parameter VAR15 = 21;
parameter VAR20 = 64;
input VAR2, VAR14;
input [VAR9-1:0] VAR1;
input VAR16;
output VAR13;
output [VAR9-1:0] VAR5;
output VAR23;
input VAR8;
reg [VAR15-1:0] VAR17;
wire [VAR9-1:0] VAR18;
wire VAR7;
wire VAR25;... | mit |
AngelTerrones/Antares | Hardware/verilog/antares_mux_4_1.v | 1,111 | module MODULE1 #(parameter VAR4 = 32)
(
input [1:0] select,
input [VAR4-1:0] VAR3,
input [VAR4-1:0] VAR1,
input [VAR4-1:0] VAR2,
input [VAR4-1:0] VAR5,
output reg [VAR4-1:0] out
);
always @ ( VAR3 or VAR1 or VAR2 or VAR5 or select) begin
case (select)
2'b00: out = VAR3;
2'b01: out = VAR1;
2'b10: out = VAR2;
2'b11: out ... | mit |
UCLONG/NetEmulation | BEE3_top/ring32b_bidir.v | 6,288 | module MODULE1(
input VAR29, input VAR25, input VAR35, input VAR16,
input [63:0] din,
output[63:0] dout,
output [31:0] VAR51,
input [31:0] VAR20,
input VAR22,
output VAR39,
output [31:0] VAR28
);
reg VAR42;
reg VAR1;
reg VAR12;
reg VAR47;
reg [63:0] VAR49;
reg [63:0] VAR5;
wire [31:0] VAR82;
wire [31:0] VAR43; wire [31... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbp/sky130_fd_sc_hs__dfbbp_1.v | 2,438 | module MODULE2 (
VAR9 ,
VAR1 ,
VAR4 ,
VAR10 ,
VAR2 ,
VAR8,
VAR7 ,
VAR5
);
output VAR9 ;
output VAR1 ;
input VAR4 ;
input VAR10 ;
input VAR2 ;
input VAR8;
input VAR7 ;
input VAR5 ;
VAR6 VAR3 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MOD... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/altera_jtag_sld_node.v | 6,704 | module MODULE1 (
VAR33,
VAR41,
VAR67,
VAR45,
VAR48,
VAR65,
VAR50,
VAR16,
VAR30,
VAR10,
VAR71,
VAR59,
VAR40
);
parameter VAR27 = 20;
localparam VAR6 = (1000/VAR27)/2;
localparam VAR73 = 3;
input [VAR73 - 1:0] VAR33;
input VAR41;
output reg [VAR73 - 1:0] VAR67;
output VAR45;
output reg VAR48 = 1'b0;
output VAR65;
output ... | gpl-3.0 |
mbuesch/toprammer | libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.v | 7,039 | module MODULE1(VAR15, VAR14, write, read, VAR2, VAR18);
inout [7:0] VAR15;
input VAR14;
input write;
input read;
input VAR2;
inout [48:1] VAR18;
wire VAR20;
reg [7:0] address;
reg [7:0] VAR19;
wire VAR1, VAR7;
reg [1:0] VAR5;
reg [3:0] VAR17;
reg [3:0] VAR16;
reg [3:0] VAR6;
reg VAR13;
reg [7:0] VAR12;
reg VAR8;
reg VA... | gpl-2.0 |
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