repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2/sky130_fd_sc_lp__nor2.functional.v | 1,254 | module MODULE1 (
VAR3,
VAR6,
VAR5
);
output VAR3;
input VAR6;
input VAR5;
wire VAR1;
nor VAR4 (VAR1, VAR6, VAR5 );
buf VAR2 (VAR3 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ai/sky130_fd_sc_hdll__o21ai.pp.symbol.v | 1,360 | module MODULE1 (
input VAR4 ,
input VAR7 ,
input VAR1 ,
output VAR5 ,
input VAR3 ,
input VAR2,
input VAR8,
input VAR6
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x8_125/source/endpoint_blk_plus_v1_14.v | 19,616 | module MODULE1 # (
parameter VAR8 = "VAR96",
parameter VAR190 = 0,
parameter VAR59 = 8,
parameter VAR81 = 1,
parameter VAR195 = 0,
parameter VAR75 = 64,
parameter VAR114 = 8,
parameter VAR79 = 4,
parameter VAR77 = 7,
parameter VAR168 = 8,
parameter VAR12 = 12,
parameter VAR7 = 32,
parameter VAR11 = 10,
parameter VAR147... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4b/sky130_fd_sc_lp__or4b_2.v | 2,291 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR10 ,
VAR5 ,
VAR11 ,
VAR7,
VAR8,
VAR3 ,
VAR2
);
output VAR4 ;
input VAR6 ;
input VAR10 ;
input VAR5 ;
input VAR11 ;
input VAR7;
input VAR8;
input VAR3 ;
input VAR2 ;
VAR9 VAR1 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/buf/sky130_fd_sc_hs__buf.functional.v | 1,635 | module MODULE1 (
VAR10,
VAR9,
VAR1 ,
VAR6
);
input VAR10;
input VAR9;
output VAR1 ;
input VAR6 ;
wire VAR7 ;
wire VAR8;
buf VAR3 (VAR7 , VAR6 );
VAR2 VAR4 (VAR8, VAR7, VAR10, VAR9);
buf VAR5 (VAR1 , VAR8 );
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/butterfly3_32.v | 6,410 | module MODULE1(
enable,
VAR8,
VAR21,
VAR41,
VAR50,
VAR53,
VAR31,
VAR37,
VAR20,
VAR27,
VAR63,
VAR16,
VAR25,
VAR52,
VAR49,
VAR45,
VAR43,
VAR39,
VAR3,
VAR36,
VAR42,
VAR34,
VAR7,
VAR46,
VAR44,
VAR57,
VAR1,
VAR9,
VAR60,
VAR38,
VAR12,
VAR24,
VAR10,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7,
VAR14,
VAR18,
o10,
o11,
o12,
o13,
o14,
o15,
o... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4bb/sky130_fd_sc_ls__nor4bb_4.v | 2,325 | module MODULE1 (
VAR4 ,
VAR11 ,
VAR8 ,
VAR9 ,
VAR3 ,
VAR2,
VAR5,
VAR10 ,
VAR6
);
output VAR4 ;
input VAR11 ;
input VAR8 ;
input VAR9 ;
input VAR3 ;
input VAR2;
input VAR5;
input VAR10 ;
input VAR6 ;
VAR1 VAR7 (
.VAR4(VAR4),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a222oi/sky130_fd_sc_hdll__a222oi.behavioral.v | 1,839 | module MODULE1 (
VAR16 ,
VAR4,
VAR17,
VAR8,
VAR5,
VAR1,
VAR13
);
output VAR16 ;
input VAR4;
input VAR17;
input VAR8;
input VAR5;
input VAR1;
input VAR13;
supply1 VAR14;
supply0 VAR2;
supply1 VAR7 ;
supply0 VAR10 ;
wire VAR20 ;
wire VAR9 ;
wire VAR6 ;
wire VAR19;
nand VAR11 (VAR20 , VAR17, VAR4 );
nand VAR12 (VAR9 , VAR... | apache-2.0 |
amrmorsey/Digital-Design-Project | sbox7.v | 3,547 | module MODULE1(
VAR1,
VAR2
);
input [6:1] VAR1;
output reg [4:1] VAR2;
wire [6:1] VAR3;
assign VAR3 = {VAR1[6], VAR1[1], VAR1[5 : 2]};
always @(VAR3)
begin
case (VAR3)
6'b000000: VAR2 <= 4'd4;
6'b000001: VAR2 <= 4'd11;
6'b000010: VAR2 <= 4'd2;
6'b000011: VAR2 <= 4'd14;
6'b000100: VAR2 <= 4'd15;
6'b000101: VAR2 <= 4'd0;... | gpl-2.0 |
kwantam/multiexp-a5gx | ocram/t_ram.v | 9,675 | module MODULE1 (
VAR20,
VAR47,
VAR33,
VAR10,
VAR23,
VAR1,
VAR53,
VAR2);
input VAR20;
input VAR47;
input [26:0] VAR33;
input [14:0] VAR10;
input VAR23;
input [14:0] VAR1;
input VAR53;
output [26:0] VAR2;
tri0 VAR20;
tri1 VAR47;
tri1 VAR23;
tri0 VAR53;
wire [26:0] VAR57;
wire [26:0] VAR2 = VAR57[26:0];
VAR59 VAR46 (
.VAR... | gpl-3.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_audio_bit_counter.v | 6,802 | module MODULE1 (
clk,
reset,
VAR7,
VAR5,
VAR8,
VAR2,
VAR3
);
parameter VAR1 = 5'h0F;
input clk;
input reset;
input VAR7;
input VAR5;
input VAR8;
input VAR2;
output reg VAR3;
wire VAR4;
reg [ 4: 0] VAR6;
always @(posedge clk)
begin
if (reset == 1'b1)
VAR6 <= 5'h00;
end
else if (VAR4 == 1'b1)
VAR6 <= VAR1;
else if ((VAR5... | mit |
iamllama/EE2020 | ee2020.ip_user_files/ip/dds_compiler_0/dds_compiler_0_stub.v | 1,469 | module MODULE1(VAR4, VAR2,
VAR3, VAR5, VAR1)
;
input VAR4;
input VAR2;
input [23:0]VAR3;
output VAR5;
output [15:0]VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvn/sky130_fd_sc_ls__einvn_2.v | 2,150 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR3,
VAR7,
VAR4,
VAR6 ,
VAR9
);
output VAR2 ;
input VAR8 ;
input VAR3;
input VAR7;
input VAR4;
input VAR6 ;
input VAR9 ;
VAR1 VAR5 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR2 ,
VAR8 ,
VAR3
);
output VAR2 ;... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/clock_control.v | 4,378 | module MODULE1
(input reset,
input VAR13, input VAR6, output [1:0] VAR7, output [1:0] VAR12, input VAR11, input VAR15,
output VAR2, output VAR3, input VAR10,
output VAR8
);
wire read = 1'b0; wire [1:0] VAR9 = 2'b00;
assign VAR12 = 2'b00; assign VAR7 = 2'b11;
reg [20:0] VAR16;
reg [5:0] VAR14;
reg VAR4;
reg [7:0] counte... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_tdd_control.v | 18,161 | module MODULE1(
clk,
rst,
VAR3,
VAR67,
VAR21,
VAR44,
VAR77,
VAR31,
VAR52,
VAR51,
VAR72,
VAR70,
VAR62,
VAR16,
VAR10,
VAR1,
VAR12,
VAR54,
VAR69,
VAR27,
VAR34,
VAR73,
VAR45,
VAR79,
VAR8,
VAR63,
VAR2,
VAR40,
VAR39,
VAR78,
VAR19,
VAR74,
VAR59,
VAR4,
VAR17);
localparam VAR76 = 1;
localparam VAR47 = 0;
input clk;
input rst;
i... | gpl-3.0 |
asicguy/gplgpu | hdl/de/der_misc.v | 4,146 | module MODULE1
(
input VAR13,
input VAR18,
input VAR6,
input VAR11,
input [1:0] VAR20, input VAR17,
input [31:0] VAR7,
input [31:0] VAR4,
input [1:0] VAR10,
input VAR19,
output reg VAR3,
output VAR9,
output VAR16,
output VAR2,
output VAR1,
output [31:0] VAR12,
output [31:0] VAR14,
output [27:0] VAR15,
output [27:0] VAR... | gpl-3.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_xfer_cntrl.v | 5,008 | module MODULE1 (
VAR21,
VAR11,
VAR10,
VAR20,
VAR5,
VAR8,
VAR19);
parameter VAR18 = 8;
localparam VAR1 = VAR18 - 1;
input VAR21;
input VAR11;
input [VAR1:0] VAR10;
output VAR20;
input VAR5;
input VAR8;
output [VAR1:0] VAR19;
reg VAR15 = 'd0;
reg VAR17 = 'd0;
reg VAR7 = 'd0;
reg [ 5:0] VAR4 = 'd0;
reg VAR20 = 'd0;
reg VA... | lgpl-3.0 |
hoglet67/CoPro6502 | src/amber23/a23_register_bank.v | 14,399 | module MODULE1 (
input VAR29,
input VAR43,
input [1:0] VAR53, input [1:0] VAR40, input [3:0] VAR63, input VAR88,
input VAR42,
input [3:0] VAR34,
input [3:0] VAR41,
input [3:0] VAR26,
input VAR58,
input [14:0] VAR47,
input [23:0] VAR87, input [31:0] VAR57,
input [3:0] VAR61,
input VAR19,
input VAR11,
output [31:0] VAR69... | gpl-3.0 |
charlie-x/layerone2016 | BadgeFirmware/StripLightLib.cylib/B_WS2811_v1_2/B_WS2811_v1_2.v | 14,164 | module MODULE1 (
irq,
VAR69,
VAR38,
clk,
reset
);
output irq;
output VAR69;
output VAR38;
input clk;
input reset;
reg VAR10; reg [1:0] VAR4; reg [1:0] state; reg [2:0] VAR36; reg VAR65; reg VAR74;
wire VAR18; wire VAR59; wire VAR17; wire enable; wire VAR38; wire VAR23;
wire VAR34;
wire VAR50; wire VAR54; wire VAR73; wi... | unlicense |
azonenberg/yosys | techlibs/xilinx/cells_map.v | 4,580 | module \VAR61 (input VAR44, VAR54, output VAR58); VAR35 #(.VAR34(|0), .VAR17(|1), .VAR29(|0), .VAR62(|0)) VAR64 (.VAR44(VAR44), .VAR58(VAR58), .VAR54(VAR54), .VAR60(1'b1), .VAR18(1'b0)); endmodule
module \VAR2 (input VAR44, VAR54, output VAR58); VAR35 #(.VAR34(|0), .VAR17(|0), .VAR29(|0), .VAR62(|0)) VAR64 (.VAR44(VAR4... | isc |
gajjanag/6111_Project | src/audioManager.v | 10,581 | module MODULE1(
input wire VAR11, input wire reset,
input wire VAR15,
input wire [6:0] VAR46,
input wire VAR28, output wire [63:0] VAR29,
input wire VAR33,
input wire ready, input wire [7:0] VAR1, output reg [7:0] VAR64,
output wire [15:0] VAR7,
output wire [23:0] VAR13,
output wire VAR67,
output wire VAR37,
output wir... | gpl-3.0 |
ptracton/wb_soc_template | rtl/ALTERA/wb_rom_32x8192.v | 6,543 | module MODULE1 (
address,
VAR28,
VAR33);
input [12:0] address;
input VAR28;
output [31:0] VAR33;
tri1 VAR28;
wire [31:0] VAR46;
wire [31:0] VAR33 = VAR46[31:0];
VAR40 VAR53 (
.VAR18 (address),
.VAR19 (VAR28),
.VAR34 (VAR46),
.VAR9 (1'b0),
.VAR25 (1'b0),
.VAR24 (1'b1),
.VAR43 (1'b0),
.VAR20 (1'b0),
.VAR10 (1'b1),
.VAR13... | mit |
timtian090/Playground | UVM/UVMPlayground/Lab3/Lab3-Project/CDC_Input_Synchronizer.v | 1,861 | module MODULE1
parameter VAR2 = 2
)
(
input VAR8,
output VAR7,
input VAR5
);
reg VAR3;
always @(posedge VAR5)
begin
VAR3 <= VAR8;
end
genvar VAR1;
generate
begin
if (VAR2 < 1)
begin
assign VAR7 = VAR3;
end
else
begin
reg [VAR2-1:0] VAR4;
assign VAR7 = VAR4[VAR2-1];
for (VAR1=0; VAR1 < VAR2; VAR1=VAR1+1)
begin : VAR6
if... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfstp/sky130_fd_sc_ms__sdfstp.symbol.v | 1,498 | module MODULE1 (
input VAR9 ,
output VAR6 ,
input VAR10,
input VAR2 ,
input VAR8 ,
input VAR7
);
supply1 VAR5;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_rdata_path.v | 50,268 | module MODULE1
parameter
VAR192 = 8,
VAR264 = 2,
VAR132 = 3, VAR35 = 3,
VAR158 = 32,
VAR145 = 5,
VAR69 = 2,
VAR93 = 3,
VAR229 = 13,
VAR141 = 10,
VAR143 = 4, VAR131 = "VAR202", VAR71 = 2,
VAR133 = 3,
VAR240 = 2,
VAR165 = 1,
VAR26 = 8,
VAR201 = 3,
VAR149 = 1,
VAR34 = 1,
VAR8 = 1,
VAR212 = 5,
VAR109 = 2,
VAR153 = 9,
VAR16... | lgpl-3.0 |
esonghori/TinyGarble | circuit_synthesis/mult/mult.v | 1,114 | module MODULE1
parameter VAR7=128,
parameter VAR9=1
)
(
clk,
rst,
VAR2,
VAR8,
VAR4
);
input clk;
input rst;
input [VAR7-1:0] VAR2;
input [VAR7-1:0] VAR8;
output [VAR7-1:0] VAR4;
wire [2*VAR7-1:0] VAR6;
assign VAR4 = VAR6[VAR7-1:0];
VAR10
.VAR7(VAR7),
.VAR3(VAR7/VAR9)
) VAR1 (
.VAR12(VAR2),
.VAR11(VAR8),
.VAR5(VAR6)
);
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtp/sky130_fd_sc_hs__dfrtp.behavioral.v | 2,165 | module MODULE1 (
VAR8,
VAR15 ,
VAR17 ,
VAR3 ,
VAR6 ,
VAR9
);
input VAR8;
input VAR15 ;
input VAR17 ;
output VAR3 ;
input VAR6 ;
input VAR9 ;
wire VAR16 ;
wire VAR4 ;
reg VAR1 ;
wire VAR7 ;
wire VAR2;
wire VAR18 ;
wire VAR13 ;
wire VAR14 ;
wire VAR10 ;
not VAR5 (VAR4 , VAR2 );
VAR11 VAR12 (VAR16 , VAR7, VAR18, VAR4, VAR... | apache-2.0 |
olajep/oh | src/common/hdl/oh_fifo_cdc.v | 2,219 | module MODULE1 # (parameter VAR23 = 104, parameter VAR4 = 32, parameter VAR7 = "VAR16" )
(
input VAR11, input VAR20, input VAR28, input [VAR23-1:0] VAR9, output VAR10, input VAR13, output reg VAR24, output [VAR23-1:0] VAR18, input VAR22, output VAR1, output VAR27, output VAR12 );
wire VAR2;
wire VAR15;
wire VAR8;
VAR3 ... | mit |
eda-globetrotter/MarcheProcessor | src/prog_counter2.v | 1,341 | module MODULE1 (VAR1,rst,clk);
output [0:31] VAR1;
input clk;
input rst;
reg [0:31] VAR1;
always @(posedge clk)
begin
if(rst==1)
begin
VAR1<=32'd0;
end
else
begin
VAR1<=VAR1+32'd4;
end
end
endmodule | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9680/axi_ad9680.v | 9,521 | module MODULE1 (
VAR107,
VAR65,
VAR76,
VAR62,
VAR12,
VAR5,
VAR37,
VAR95,
VAR96,
VAR43,
VAR88,
VAR58,
VAR4,
VAR106,
VAR84,
VAR13,
VAR2,
VAR21,
VAR97,
VAR50,
VAR29,
VAR35,
VAR64,
VAR102,
VAR117,
VAR124,
VAR118,
VAR75,
VAR52,
VAR126,
VAR127,
VAR72);
parameter VAR38 = 0;
parameter VAR82 = 0;
parameter VAR99 = "VAR49";
inpu... | gpl-3.0 |
dengjeffrey/BirthdayClockVerilog | project.v | 28,078 | module MODULE1 (VAR39,VAR60,VAR44,VAR22,VAR64, VAR74, VAR77);
output [25:0]VAR39;
output [0:17]VAR22;
output [0:6]VAR64;
input VAR74;
input VAR77;
input[16:0] VAR60;
input VAR44;
wire VAR63;
wire VAR9;
reg [0:7] VAR12,VAR66,VAR25,VAR3,VAR55,VAR48,VAR68,VAR57;
wire reset = 1'b0;
wire [7:0] VAR73;
reg [7:0] VAR31;
wire r... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufbuf/sky130_fd_sc_hdll__bufbuf.pp.symbol.v | 1,266 | module MODULE1 (
input VAR6 ,
output VAR2 ,
input VAR3 ,
input VAR4,
input VAR5,
input VAR1
);
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/de3d/de3d_fog_table.v | 12,612 | module MODULE1
(
input select, input VAR1, input [6:2] VAR44, input [7:0] VAR21, input [31:0] VAR55, input [5:0] VAR68, input [5:0] VAR26,
output [31:0] VAR45, output [7:0] VAR62, output [7:0] VAR51, output [7:0] VAR54 );
reg [7:0] VAR62;
reg [7:0] VAR51;
reg [7:0] VAR7, VAR58,
VAR2, VAR61,
VAR63, VAR59,
VAR49, VAR72,
... | gpl-3.0 |
LSaldyt/qnp | output/vs/opt_var17_multi.v | 23,329 | module MODULE1(VAR1, VAR17, VAR8, VAR2, VAR6, VAR10, VAR5, VAR13, VAR3, VAR12, VAR7, VAR14, VAR11, VAR4, VAR16, VAR9, VAR15, valid);
wire 000;
wire 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 01... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapmet1/sky130_fd_sc_ls__tapmet1.functional.v | 1,071 | module MODULE1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi_1.v | 2,477 | module MODULE1 (
VAR11 ,
VAR10,
VAR4,
VAR1 ,
VAR7 ,
VAR9,
VAR3,
VAR8 ,
VAR2
);
output VAR11 ;
input VAR10;
input VAR4;
input VAR1 ;
input VAR7 ;
input VAR9;
input VAR3;
input VAR8 ;
input VAR2 ;
VAR6 VAR5 (
.VAR11(VAR11),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probec_p/sky130_fd_sc_hdll__probec_p.pp.symbol.v | 1,290 | module MODULE1 (
input VAR5 ,
output VAR1 ,
input VAR2 ,
input VAR3,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregsbp/sky130_fd_sc_lp__sregsbp.behavioral.v | 2,848 | module MODULE1 (
VAR24 ,
VAR25 ,
VAR11 ,
VAR28 ,
VAR2 ,
VAR8 ,
VAR18
);
output VAR24 ;
output VAR25 ;
input VAR11 ;
input VAR28 ;
input VAR2 ;
input VAR8 ;
input VAR18;
supply1 VAR5;
supply0 VAR22;
supply1 VAR1 ;
supply0 VAR14 ;
wire VAR10 ;
wire VAR13 ;
wire VAR7 ;
reg VAR32 ;
wire VAR9 ;
wire VAR17 ;
wire VAR20 ;
wir... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/ip_dram/phy/mig_7series_v2_3_ddr_phy_oclkdelay_cal.v | 24,062 | module MODULE1 #
(parameter VAR78 = 100,
parameter VAR137 = 4,
parameter VAR62 = 8,
parameter VAR68 = 3,
parameter VAR85 = 8,
parameter VAR51 = 64,
parameter VAR56 = 10,
parameter VAR113 = 2,
parameter VAR84 = 95,
parameter VAR45 = "VAR38",
parameter VAR33 = 95,
parameter VAR26 = "VAR13",
parameter VAR128 = 8,
paramete... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221o/sky130_fd_sc_hs__a221o_1.v | 2,317 | module MODULE2 (
VAR8 ,
VAR7 ,
VAR6 ,
VAR10 ,
VAR2 ,
VAR3 ,
VAR4,
VAR5
);
output VAR8 ;
input VAR7 ;
input VAR6 ;
input VAR10 ;
input VAR2 ;
input VAR3 ;
input VAR4;
input VAR5;
VAR1 VAR9 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODUL... | apache-2.0 |
yanhongwang/ColorImage | ColorImageProcessChip_Sequential/ColorImageProcess.v | 71,674 | module MODULE1#
(
parameter[ 2 : 0 ]VAR89 = 0, parameter[ 2 : 0 ]VAR86 = 1, parameter[ 2 : 0 ]VAR81 = 2, parameter[ 2 : 0 ]VAR33 = 3, parameter[ 2 : 0 ]VAR62 = 4
)
(
input VAR83,
input VAR80,
input[ VAR19 - 1 : 0 ]VAR74,
input[ VAR19 - 1 : 0 ]VAR67,
input[ VAR19 - 1 : 0 ]VAR37,
output reg[ VAR19 - 1 : 0 ]VAR34,
output ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_4.behavioral.v | 1,098 | module MODULE1( VAR5, VAR3 );
input VAR5;
output VAR3;
VAR1 VAR2(.VAR5(VAR5),.VAR3(VAR3));
VAR1 VAR4(.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/ip_dram/controller/mig_7series_v2_3_bank_common.v | 18,372 | module MODULE1 #
(
parameter VAR99 = 100,
parameter VAR34 = 2,
parameter VAR96 = 1,
parameter VAR7 = 4,
parameter VAR78 = 2,
parameter VAR12 = 0,
parameter VAR112 = 44,
parameter VAR11 = 512,
parameter VAR65 = 2,
parameter VAR68 = 4,
parameter VAR21 = 5,
parameter VAR10 = 64
)
(
VAR66, VAR110, VAR31, VAR20,
VAR101, VAR... | mit |
Tao-J/nexys3MIPSSoC | vgabase.v | 2,124 | module MODULE1(
input wire clk,
input wire VAR12,
output reg VAR2,
output reg VAR8,
output reg [11:0] hc,
output reg [11:0] VAR6,
output wire VAR1
);
parameter VAR3 = 12'd1344;
parameter VAR5 = 12'd806;
parameter VAR10 = 12'd136;
parameter VAR11 = 12'd160;
parameter VAR7 = 12'd24;
parameter VAR13 = 12'd6;
parameter VAR... | gpl-3.0 |
joaocarlos/udlx-verilog | rtl/inst_memory_controll/inst_memory_controll.v | 1,190 | module MODULE1
parameter VAR12 = 32,
parameter VAR9 = 32,
parameter VAR7 = 20,
parameter VAR8 = 16
)
(
input clk,
input VAR5,
output VAR13,
output VAR15,
output [VAR9-1:0] VAR6,
input [VAR12-1:0] VAR17,
output [VAR12-1:0] VAR10,
output [VAR7-1:0] VAR2,
output VAR11,
inout [VAR8-1:0] VAR16,
output VAR1,
output VAR4,
out... | lgpl-3.0 |
lowRISC/flexpret | UAReceiver.v | 11,325 | module MODULE1(VAR12, VAR15, VAR18, VAR3, VAR2, VAR20);
parameter VAR9 = 27000000,
VAR13 = 115200,
VAR19 = 8,
VAR16 = 0,
VAR10 = 1;
localparam VAR6 = VAR9 / VAR13,
VAR14 = VAR7(VAR6),
VAR1 = (VAR6 / 2),
VAR5 = VAR19 + VAR10 + (VAR16 ? 1 : 0) + 1,
VAR17 = VAR7(VAR5 + 1),
VAR11 = VAR9 / VAR6;
localparam real VAR8 = VAR9 ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o_4.v | 2,348 | module MODULE2 (
VAR8 ,
VAR9 ,
VAR4 ,
VAR1 ,
VAR3 ,
VAR5,
VAR6,
VAR7 ,
VAR11
);
output VAR8 ;
input VAR9 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR5;
input VAR6;
input VAR7 ;
input VAR11 ;
VAR2 VAR10 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR11... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbp/sky130_fd_sc_hs__dfbbp.pp.symbol.v | 1,435 | module MODULE1 (
input VAR7 ,
output VAR6 ,
output VAR2 ,
input VAR1,
input VAR5 ,
input VAR3 ,
input VAR8 ,
input VAR4
);
endmodule | apache-2.0 |
jschiefer/hdfs | lib/tutorial/counter.v | 1,412 | module MODULE1 #(
parameter VAR5 = 16
) (
input VAR2, reset, enable, VAR4,
input [VAR5-1:0] VAR6,
output reg [VAR5-1:0] VAR9
);
always @(posedge VAR2, posedge reset)
if (reset)
VAR9 <= 0;
else if (enable)
if (VAR4) VAR9 <= VAR6;
else VAR9 <= VAR9 + 1;
endmodule
module MODULE5 #(
parameter VAR5 = 16
) (
input VAR2, rese... | lgpl-2.1 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/sdr_lib/gen_sync.v | 1,256 | module MODULE1
( input VAR1,
input reset,
input enable,
input [7:0] VAR2,
output wire sync );
reg [7:0] counter;
assign sync = |(((VAR2+1)>>1)& counter);
always @(posedge VAR1)
if(reset || ~enable)
counter <= 0;
else if(counter == VAR2)
counter <= 0;
else
counter <= counter + 8'd1;
endmodule | gpl-3.0 |
qeedquan/fpga | de2-115/nios_lights/lights/synthesis/submodules/lights_mm_interconnect_0_avalon_st_adapter.v | 6,152 | module MODULE1 #(
parameter VAR24 = 34,
parameter VAR18 = 0,
parameter VAR7 = 34,
parameter VAR25 = 0,
parameter VAR17 = 0,
parameter VAR6 = 0,
parameter VAR2 = 1,
parameter VAR12 = 1,
parameter VAR8 = 0,
parameter VAR16 = 34,
parameter VAR21 = 0,
parameter VAR22 = 1,
parameter VAR19 = 0,
parameter VAR10 = 1,
parameter... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4bb/sky130_fd_sc_ls__and4bb.functional.v | 1,416 | module MODULE1 (
VAR1 ,
VAR2,
VAR9,
VAR8 ,
VAR10
);
output VAR1 ;
input VAR2;
input VAR9;
input VAR8 ;
input VAR10 ;
wire VAR4 ;
wire VAR7;
nor VAR5 (VAR4 , VAR2, VAR9 );
and VAR6 (VAR7, VAR4, VAR8, VAR10 );
buf VAR3 (VAR1 , VAR7 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/common/rtl/ctu_sync_header.v | 10,467 | module MODULE1 (
VAR15, VAR53, VAR39, VAR32,
VAR38, VAR55, VAR46, VAR13,
VAR6, VAR18, VAR17, VAR20
);
input VAR38; input VAR55; input VAR46; input VAR13; input VAR6; input VAR18; input VAR17; input VAR20;
output VAR15; output VAR53; output VAR39; output VAR32; wire VAR31; wire VAR19; wire VAR24; wire VAR47; wire VAR25;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtn/sky130_fd_sc_lp__dfrtn.functional.v | 1,775 | module MODULE1 (
VAR12 ,
VAR1 ,
VAR13 ,
VAR10
);
output VAR12 ;
input VAR1 ;
input VAR13 ;
input VAR10;
wire VAR3 ;
wire VAR2 ;
wire VAR9;
not VAR4 (VAR2 , VAR10 );
not VAR5 (VAR9, VAR1 );
VAR11 VAR8 VAR7 (VAR3 , VAR13, VAR9, VAR2);
buf VAR6 (VAR12 , VAR3 );
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_2c_v1_00_a/hdl/verilog/cf_adc_wr.v | 13,144 | module MODULE1 (
VAR48,
VAR62,
VAR23,
VAR19,
VAR78,
VAR74,
VAR52,
VAR22,
VAR35,
VAR73,
VAR43,
VAR63,
VAR79, VAR14, VAR47, VAR12, VAR16, VAR10, VAR37, VAR4, VAR59, VAR66, VAR76, VAR50, VAR61,
VAR31,
VAR75,
VAR1, VAR54,
VAR57,
VAR42,
VAR40,
VAR11, VAR15,
VAR13,
VAR60,
VAR32,
VAR51,
VAR28,
VAR24,
VAR39,
VAR8,
VAR2,
VAR7);... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2_lp.v | 2,083 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR4 ,
VAR5,
VAR3,
VAR2 ,
VAR8
);
output VAR6 ;
input VAR1 ;
input VAR4 ;
input VAR5;
input VAR3;
input VAR2 ;
input VAR8 ;
VAR7 VAR9 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR6,
VAR1,
VAR4
);
output VAR6;
... | apache-2.0 |
everskar2013/PentiumX | Hardware/Code/data_path.v | 7,381 | module MODULE1(
clk,
reset,
VAR48,
VAR53,
VAR13,
VAR65,
VAR42,
VAR27,
VAR57,
VAR7,
VAR44,
VAR33,
VAR23,
VAR9,
VAR35,
VAR41,
VAR1,
VAR26,
VAR19,
VAR8,
VAR11,
VAR59,
VAR36,
VAR38,
VAR67,
VAR75,
VAR18,
VAR25,
VAR60,
VAR56,
VAR73
);
input wire clk, reset;
input wire VAR48, VAR53, VAR42, VAR13, VAR9,
VAR35, VAR41, VAR57, VA... | mit |
binary-logic/vj-uart | rtl/vjtag.v | 7,723 | module MODULE1 (
VAR47,
VAR49,
VAR4,
VAR3,
VAR38,
VAR17,
VAR2,
VAR12,
VAR33,
VAR34,
VAR26,
VAR22,
VAR25);
input [1:0] VAR47;
input VAR49;
output [1:0] VAR4;
output VAR3;
output VAR38;
output VAR17;
output VAR2;
output VAR12;
output VAR33;
output VAR34;
output VAR26;
output VAR22;
output VAR25;
wire VAR14;
wire VAR6;
wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux4/sky130_fd_sc_ls__mux4_4.v | 2,444 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR8 ,
VAR11 ,
VAR12 ,
VAR7 ,
VAR4 ,
VAR1,
VAR13,
VAR5 ,
VAR3
);
output VAR6 ;
input VAR10 ;
input VAR8 ;
input VAR11 ;
input VAR12 ;
input VAR7 ;
input VAR4 ;
input VAR1;
input VAR13;
input VAR5 ;
input VAR3 ;
VAR2 VAR9 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR12(VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_2.behavioral.pp.v | 1,561 | module MODULE1( VAR2, VAR6, VAR3, VAR4, VAR7, VAR8 );
input VAR4, VAR3, VAR2;
inout VAR7, VAR8;
output VAR6;
VAR9 VAR1(.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3),.VAR4(VAR4),.VAR7(VAR7),.VAR8(VAR8));
VAR9 VAR5(.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3),.VAR4(VAR4),.VAR7(VAR7),.VAR8(VAR8)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decap/sky130_fd_sc_lp__decap.behavioral.v | 1,135 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/old/hdl/elink-gold/ewrapper_io_tx_slow.v | 7,479 | module MODULE1
(
VAR17, VAR68, VAR40,
VAR25,
VAR19, VAR2, VAR66, VAR38, VAR58, VAR70,
VAR30
);
input VAR19; input VAR2; input VAR66; input VAR38;
input VAR58;
input VAR70;
input [71:0] VAR30;
output [8:0] VAR17;
output [8:0] VAR68;
output VAR40;
output VAR25;
reg [1:0] VAR39;
reg VAR50;
reg VAR44;
reg [8:0] VAR51;
reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21oi/sky130_fd_sc_hd__a21oi.blackbox.v | 1,334 | module MODULE1 (
VAR1 ,
VAR5,
VAR7,
VAR3
);
output VAR1 ;
input VAR5;
input VAR7;
input VAR3;
supply1 VAR6;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
AngelTerrones/ADA | rtl/ada_exu.v | 8,428 | module MODULE1(
input clk, input rst, input [31:0] VAR31, input [31:0] VAR7, input [4:0] VAR24, input VAR32, input VAR16, output reg [31:0] VAR2, output VAR19, output VAR28 );
reg [63:0] VAR9; reg VAR26; reg VAR15;
wire [31:0] VAR1;
wire [31:0] VAR20;
wire signed [31:0] VAR23;
wire signed [31:0] VAR12;
wire signed [31:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32ai/sky130_fd_sc_ls__o32ai_1.v | 2,441 | module MODULE2 (
VAR5 ,
VAR3 ,
VAR4 ,
VAR1 ,
VAR8 ,
VAR2 ,
VAR7,
VAR12,
VAR9 ,
VAR6
);
output VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR1 ;
input VAR8 ;
input VAR2 ;
input VAR7;
input VAR12;
input VAR9 ;
input VAR6 ;
VAR10 VAR11 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr_16.v | 2,271 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR6,
VAR3 ,
VAR7 ,
VAR9 ,
VAR5
);
output VAR8 ;
input VAR1 ;
input VAR6;
input VAR3 ;
input VAR7 ;
input VAR9 ;
input VAR5 ;
VAR4 VAR2 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR8,
VAR1
);
output VAR8;
inpu... | apache-2.0 |
cr88192/bgbtech_bjx1core | srvcore/FpuFp32.v | 1,630 | module MODULE1(
clk,
VAR24,
VAR12,
VAR23,
VAR1
);
input clk;
input[3:0] VAR24;
input[31:0] VAR12;
input[31:0] VAR23;
output[31:0] VAR1;
parameter[3:0] VAR4 = 4'h00;
parameter[3:0] VAR20 = 4'h01;
parameter[3:0] VAR22 = 4'h02;
parameter[3:0] VAR11 = 4'h03;
parameter[3:0] VAR7 = 4'h04;
parameter[3:0] VAR13 = 4'h05;
parame... | mit |
spesialstyrker/boula | src/tx_bridge.v | 8,801 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR10,
output reg VAR32,
input wire [VAR12 - 1:0] VAR40,
input wire [VAR17 - 1:0] VAR3,
input wire VAR36,
input wire VAR38,
output reg VAR31,
input wire [VAR12 - 1:0] VAR33,
input wire [VAR17 - 1:0] VAR8,
input wire VAR27,
output reg VAR21,
input wire VAR19,
... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/ram_loader.v | 7,085 | module MODULE1
(
input VAR16,
input VAR36,
input VAR45,
output wire [31:0] VAR24,
output wire [VAR18-1:0] VAR35,
output VAR5,
output reg [3:0] VAR4,
output VAR1,
output reg VAR37,
input VAR8,
input VAR23,
output reg VAR34,
output reg VAR17,
output reg VAR15,
input VAR2
);
localparam VAR42 = 0;
localparam VAR27 = 1;
loc... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21boi/sky130_fd_sc_ls__a21boi.functional.v | 1,543 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR3 ,
VAR10
);
output VAR7 ;
input VAR11 ;
input VAR3 ;
input VAR10;
wire VAR8 ;
wire VAR9 ;
wire VAR5;
not VAR2 (VAR8 , VAR10 );
and VAR1 (VAR9 , VAR11, VAR3 );
nor VAR6 (VAR5, VAR8, VAR9 );
buf VAR4 (VAR7 , VAR5 );
endmodule | apache-2.0 |
alankarkotwal/lca-processor | pipeline/fetch.v | 2,945 | module MODULE2(VAR17,VAR23,VAR49,VAR42 ,VAR3 ,VAR20, VAR69,VAR66, VAR59, VAR68, VAR16, VAR41, VAR4, VAR43, VAR44, VAR19, VAR2, clk, reset);
output [15:0] VAR44, VAR19, VAR2;
input [15:0]VAR23;
wire [15:0] VAR7; input VAR17;
input [15:0] VAR66, VAR59, VAR68, VAR16, VAR41, VAR4;
input [15:0] VAR42 ,VAR3 ,VAR20, VAR69;
wi... | gpl-2.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v | 6,705 | module MODULE1
( output VAR30,
input VAR46
);
wire VAR73;
wire VAR5;
VAR47 VAR22
(.VAR2 (VAR73),
.VAR8 (VAR46));
wire VAR75;
wire VAR71;
wire VAR12;
wire VAR59;
wire VAR23;
wire VAR63;
wire VAR26;
wire [15:0] VAR16;
wire VAR10;
wire VAR33;
wire VAR15;
wire VAR21;
wire VAR61;
wire VAR27;
wire VAR40;
wire VAR24;
wire VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.functional.pp.v | 1,184 | module MODULE1( VAR4, VAR8, VAR6, VAR13, VAR7 );
input VAR8, VAR4;
inout VAR13, VAR7;
output VAR6;
wire VAR12;
and VAR2( VAR12, VAR8, VAR4 );
wire VAR11;
not VAR14( VAR11, VAR8 );
wire VAR9;
not VAR5( VAR9, VAR4 );
wire VAR1;
and VAR10( VAR1, VAR11, VAR9 );
or VAR3( VAR6, VAR12, VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4bb/sky130_fd_sc_ls__and4bb.behavioral.pp.v | 1,998 | module MODULE1 (
VAR13 ,
VAR16 ,
VAR8 ,
VAR11 ,
VAR4 ,
VAR7,
VAR3,
VAR1 ,
VAR17
);
output VAR13 ;
input VAR16 ;
input VAR8 ;
input VAR11 ;
input VAR4 ;
input VAR7;
input VAR3;
input VAR1 ;
input VAR17 ;
wire VAR15 ;
wire VAR6 ;
wire VAR14;
nor VAR5 (VAR15 , VAR16, VAR8 );
and VAR2 (VAR6 , VAR15, VAR11, VAR4 );
VAR9 VAR... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mux.v | 3,550 | if (VAR6 && VAR23 == VAR25 && VAR3 == VAR31) \
begin: VAR17 \
wire [VAR23-1:0] VAR24 = VAR23 ' (1'b1 << VAR38); \
\
VAR39 VAR8 \
(.* \
, .VAR41(VAR24) \
); \
end
if (VAR21 && VAR6 && (VAR23==4)) \
begin: VAR17 \
wire [VAR3-1:0] VAR22; \
\
\
VAR13 VAR29 (.VAR9 (VAR18[0]) \
,.VAR2(VAR18[1]) \
,.VAR7(VAR18[2]) \
,.VAR34(V... | bsd-3-clause |
walkthetalk/fsref | ip/fslcd/src/fslcd.v | 1,979 | module MODULE1 #
(
parameter integer VAR3 = 8,
parameter integer VAR5 = 6
) (
input VAR11,
input VAR6,
input [VAR3*3-1:0] VAR17,
input VAR13,
input VAR18,
output [VAR5-1:0] VAR9,
output [VAR5-1:0] VAR1,
output [VAR5-1:0] VAR12,
output VAR4,
output VAR15,
output VAR14,
output VAR19
);
function integer VAR10 (input integ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111o/sky130_fd_sc_lp__a2111o.functional.pp.v | 2,070 | module MODULE1 (
VAR10 ,
VAR11 ,
VAR13 ,
VAR14 ,
VAR16 ,
VAR7 ,
VAR9,
VAR1,
VAR8 ,
VAR6
);
output VAR10 ;
input VAR11 ;
input VAR13 ;
input VAR14 ;
input VAR16 ;
input VAR7 ;
input VAR9;
input VAR1;
input VAR8 ;
input VAR6 ;
wire VAR18 ;
wire VAR5 ;
wire VAR15;
and VAR12 (VAR18 , VAR11, VAR13 );
or VAR17 (VAR5 , VAR16,... | apache-2.0 |
sheiksadique/USB-Uart | UART_RX.v | 2,427 | module MODULE1(
input VAR6,
output VAR2, input VAR4,
input VAR10, output reg [7:0] VAR1, output VAR5
);
reg [1:0] VAR11;
always @(posedge VAR4) if(VAR10) VAR11 <= {VAR11[0], VAR6};
reg [2:0] VAR7=7;
reg VAR8;
always @(posedge VAR4)
if(VAR10)
begin
end
if(VAR11[1] && VAR7!=3'b111) VAR7 <= VAR7 + 1; else if(~VAR11[1] && ... | gpl-2.0 |
hanyazou/vivado-ws | playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.v | 4,030 | module MODULE1
(
input VAR3,
output VAR5,
input reset,
output VAR4
);
VAR1 VAR2
(
.VAR3(VAR3),
.VAR5(VAR5),
.reset(reset),
.VAR4(VAR4)
);
endmodule | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/top/rtl/chip.v | 12,703 | module MODULE1 (
input wire clk, input wire clk, input wire reset
);
wire [VAR25] VAR23; wire VAR96; wire VAR42; wire [VAR33] VAR47; wire VAR65; wire VAR31; wire [VAR25] VAR43; wire VAR34; wire VAR3; wire [VAR33] VAR70; wire VAR79; wire VAR71; wire [VAR25] VAR15; wire VAR55; wire VAR50; wire [VAR33] VAR19; wire VAR85; ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrbp/sky130_fd_sc_hd__dfrbp.behavioral.v | 2,313 | module MODULE1 (
VAR23 ,
VAR1 ,
VAR16 ,
VAR2 ,
VAR17
);
output VAR23 ;
output VAR1 ;
input VAR16 ;
input VAR2 ;
input VAR17;
supply1 VAR12;
supply0 VAR11;
supply1 VAR21 ;
supply0 VAR14 ;
wire VAR15 ;
wire VAR9 ;
reg VAR6 ;
wire VAR13 ;
wire VAR7;
wire VAR10 ;
wire VAR20 ;
wire VAR22 ;
wire VAR5 ;
not VAR18 (VAR9 , VAR7... | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/system/boot_mem128.v | 6,658 | module MODULE1 #(
parameter VAR2 = 128,
parameter VAR9 = 16,
parameter VAR24 = 10
)(
input VAR23,
input [31:0] VAR12,
input [VAR9-1:0] VAR19,
input VAR8,
output [VAR2-1:0] VAR28,
input [VAR2-1:0] VAR1,
input VAR15,
input VAR27,
output VAR16,
output VAR6
);
wire VAR11;
wire VAR5;
wire [VAR2-1:0] VAR4;
wire [VAR2-1:0] VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbp/sky130_fd_sc_ls__dlxbp.pp.symbol.v | 1,358 | module MODULE1 (
input VAR8 ,
output VAR1 ,
output VAR7 ,
input VAR6,
input VAR3 ,
input VAR4,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf.symbol.v | 1,262 | module MODULE1 (
input VAR4,
output VAR1
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.behavioral.v | 18,884 | module MODULE1( VAR207, VAR35, VAR52, VAR173, VAR193, VAR274 );
input VAR173, VAR52, VAR207, VAR193, VAR35;
output VAR274;
reg VAR138;
VAR28 VAR56(.VAR207(VAR207),.VAR35(VAR35),.VAR52(VAR52),.VAR173(VAR173),.VAR193(VAR193),.VAR274(VAR274),.VAR138(VAR138));
VAR28 VAR132(.VAR207(VAR207),.VAR35(VAR35),.VAR52(VAR52),.VAR17... | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Lab1/sietesegmentos/pruebaalonso.v | 1,595 | module MODULE1;
reg VAR14;
reg VAR21;
reg VAR7;
reg VAR3;
reg VAR18;
reg VAR11;
reg VAR10;
reg VAR16;
wire VAR8;
wire VAR6;
wire VAR5;
wire VAR13;
wire VAR9;
wire VAR2;
wire VAR17;
wire VAR15;
wire VAR1;
wire VAR19;
wire VAR12;
VAR4 VAR20 (
.VAR14(VAR14),
.VAR21(VAR21),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR18(VAR18),
.VAR11(V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222oi/sky130_fd_sc_hs__a222oi.pp.symbol.v | 1,394 | module MODULE1 (
input VAR3 ,
input VAR6 ,
input VAR5 ,
input VAR4 ,
input VAR2 ,
input VAR9 ,
output VAR8 ,
input VAR7,
input VAR1
);
endmodule | apache-2.0 |
chebykinn/university | io/lab3/v-src/BRAMInterconnect.v | 2,881 | module MODULE1(VAR20,VAR4,VAR7,VAR10,VAR18,VAR21,VAR13,VAR9,VAR8,VAR6,VAR12,VAR5,VAR16,VAR24,VAR22,VAR23,VAR2,VAR19,VAR11,VAR3,VAR14,VAR17);
output [31:0] VAR20;
output [12:0] VAR4;
output [31:0] VAR7;
output VAR10;
output [3:0] VAR18;
output [12:0] VAR21;
output [31:0] VAR13;
output VAR9;
output [3:0] VAR8;
output [12... | mit |
olajep/oh | src/common/hdl/oh_edgealign.v | 1,479 | module MODULE1 (
VAR5,
VAR3, VAR1
);
input VAR3;
input VAR1;
output VAR5;
reg VAR4;
reg VAR2;
reg VAR5;
always @ (negedge VAR3)
VAR4 <= VAR1;
always @ (posedge VAR3)
begin
VAR2 <= VAR4;
VAR5 <= ~VAR4 & VAR2;
end
endmodule | mit |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_axi_master.v | 20,876 | module MODULE1 (
VAR43,
VAR16,
VAR26,
VAR59,
VAR51,
VAR27,
VAR57,
VAR53,
VAR25,
VAR1,
VAR4,
VAR12,
VAR39,
VAR37,
VAR46,
VAR42,
VAR9,
VAR47,
VAR11,
VAR15,
VAR20,
VAR22,
VAR63,
VAR18,
VAR2,
VAR55, VAR60, VAR45,
VAR58,
VAR38,
VAR62,
VAR34,
VAR30,
VAR61,
VAR35,
VAR10,
VAR32,
VAR52,
VAR56,
VAR13
);
parameter VAR31 = 0;
para... | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/05MicroSD/Version_02/02 verilog/J1_soc-master/hdl/SD/peripheral_SD.v | 1,731 | module MODULE1(clk , reset , din , VAR10 , addr , rd , wr, dout, VAR2, VAR7, VAR3, VAR5 );
input clk;
input [15:0]din;
input VAR10;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
input reset;
output VAR2;
input VAR3;
output VAR7;
output VAR5;
reg [5:0] VAR6;
reg [15:0] VAR11=0;
reg enable=0;
wire [15:0] VA... | gpl-3.0 |
mbus/mbus | layer_controller_v1/verilog/int_action_rom.v | 2,811 | module MODULE1(
VAR3,
VAR4
);
parameter VAR9 = 8;
parameter VAR10 = 128; parameter VAR12 = 65536;
output [VAR7*VAR9-1:0] VAR3;
output [(VAR6<<1)*VAR9-1:0] VAR4;
reg [VAR7-1:0] VAR2 [0:VAR9-1];
reg [(VAR6<<1)-1:0] VAR8 [0:VAR9-1];
genvar VAR5;
generate
for (VAR5=0; VAR5<VAR9; VAR5=VAR5+1)
begin: VAR11
assign VAR3[VAR7*(... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_4.behavioral.v | 1,180 | module MODULE1( VAR4, VAR5, VAR6 );
input VAR4, VAR5;
output VAR6;
VAR3 VAR2(.VAR4(VAR4),.VAR5(VAR5),.VAR6(VAR6));
VAR3 VAR1(.VAR4(VAR4),.VAR5(VAR5),.VAR6(VAR6)); | apache-2.0 |
Ribster/opl3_fpga | fpga/modules/clks/ip/clk_gen/clk_gen.v | 3,919 | module MODULE1
(
input VAR2,
output clk,
output VAR1
);
VAR3 VAR4
(
.VAR2(VAR2),
.clk(clk),
.VAR1(VAR1)
);
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4/sky130_fd_sc_ms__and4.pp.blackbox.v | 1,314 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR1 ,
VAR6,
VAR5,
VAR8 ,
VAR9
);
output VAR2 ;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR1 ;
input VAR6;
input VAR5;
input VAR8 ;
input VAR9 ;
endmodule | apache-2.0 |
fallen/milkymist-mmu | cores/pfpu/rtl/pfpu_ctlif.v | 4,229 | module MODULE1 #(
parameter VAR37 = 4'h0
) (
input VAR25,
input VAR19,
input [13:0] VAR33,
input VAR2,
input [31:0] VAR34,
output [31:0] VAR22,
output reg irq,
output reg VAR35,
input VAR30,
output reg [28:0] VAR18,
output reg [6:0] VAR13,
output reg [6:0] VAR31,
output [6:0] VAR26,
input [31:0] VAR15,
output [31:0] VA... | lgpl-3.0 |
jas0n1ee/THU-DSD | FB/timer.v | 5,552 | module MODULE1 (
address,
VAR25,
clk,
VAR28,
VAR27,
VAR13,
irq,
VAR7
)
;
output irq;
output [ 15: 0] VAR7;
input [ 2: 0] address;
input VAR25;
input clk;
input VAR28;
input VAR27;
input [ 15: 0] VAR13;
wire VAR3;
wire VAR24;
reg VAR16;
wire VAR15;
reg VAR26;
wire VAR12;
wire [ 15: 0] VAR6;
reg [ 15: 0] VAR14;
reg VAR18... | mit |
kyzhai/NUNY | src/hardware/phd_new_bb.v | 5,006 | module MODULE1 (
address,
VAR2,
VAR1);
input [11:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/sctag_pcx_rptr_0.v | 1,969 | module MODULE1 (
VAR2,
VAR1
);
output [163:0] VAR2;
input [163:0] VAR1;
assign VAR2 = VAR1;
endmodule | gpl-2.0 |
borti4938/sd2snes | verilog/sd2snes_gsu/gsu_mult.v | 4,349 | module MODULE1 (
VAR4,
VAR15,
VAR8);
input [7:0] VAR4;
input [7:0] VAR15;
output [15:0] VAR8;
wire [15:0] VAR14;
wire [15:0] VAR8 = VAR14[15:0];
VAR12 VAR9 (
.VAR4 (VAR4),
.VAR15 (VAR15),
.VAR8 (VAR14),
.VAR7 (1'b0),
.VAR2 (1'b1),
.VAR5 (1'b0),
.VAR19 (1'b0),
.sum (1'b0));
VAR9.VAR13 = "VAR3=5",
VAR9.VAR18 = "VAR1",
V... | gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.