repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0p/sky130_fd_sc_hdll__inputiso0p.behavioral.v | 1,461 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR6
);
output VAR1 ;
input VAR3 ;
input VAR6;
supply1 VAR5;
supply0 VAR9;
supply1 VAR10 ;
supply0 VAR7 ;
wire VAR8;
not VAR2 (VAR8, VAR6 );
and VAR4 (VAR1 , VAR3, VAR8 );
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/m32632/ICACHE.v | 10,709 | module MODULE1( VAR44, VAR81, VAR138, VAR92, VAR133, VAR40, VAR85, VAR77, VAR53, VAR61, VAR49,
VAR123, VAR122, VAR14, VAR89, VAR132, VAR88, VAR96, VAR82, VAR47, VAR27, VAR134, VAR54, VAR55,
VAR73, VAR68, VAR66, VAR130, VAR75, VAR10, VAR25, VAR114, VAR119, VAR117,
VAR93, VAR46, VAR109, VAR30, VAR9, VAR103 );
input VAR44... | gpl-3.0 |
asicguy/gplgpu | hdl/vga/ram_16x32_dp.v | 2,315 | module MODULE1
(
input [15:0] VAR5,
input VAR1,
input [4:0] VAR6,
input [4:0] VAR2,
input VAR3,
input VAR4,
output reg [15:0] VAR7
);
reg [15:0] VAR8 [0:31];
always @(posedge VAR3) if(VAR1) VAR8[VAR6] <= VAR5;
always @(posedge VAR4) VAR7 <= VAR8[VAR2];
endmodule | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab4/axi_interfaces_prj/solution2/impl/ip/hdl/verilog/axi_interfaces_AXILiteS_s_axi.v | 9,024 | module MODULE1
VAR25 = 4,
VAR5 = 32
)(
input wire VAR56,
input wire VAR17,
input wire VAR4,
input wire [VAR25-1:0] VAR16,
input wire VAR21,
output wire VAR46,
input wire [VAR5-1:0] VAR42,
input wire [VAR5/8-1:0] VAR41,
input wire VAR57,
output wire VAR9,
output wire [1:0] VAR23,
output wire VAR24,
input wire VAR2,
inpu... | mit |
GSejas/Aproximate-Arithmetic-Operators | src_lib/multlib/UDMnxnv2.v | 1,335 | module MODULE1
input wire [VAR17-1:0] VAR7,
input wire [VAR17-1:0] VAR5,
output wire [2*VAR17-1:0] VAR20
);
wire [VAR17/2-1:0] VAR9;
wire [VAR17/2-1:0] VAR8;
wire [VAR17/2-1:0] VAR13;
wire [VAR17/2-1:0] VAR14;
generate
if (VAR17==2) begin : VAR1
wire [2:0] VAR19;
VAR3 VAR3 (.VAR7(VAR7), .VAR5(VAR5), .VAR20(VAR19));
ass... | apache-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/db/altera_mult_add_ujt2.v | 17,288 | module MODULE1
(
VAR27,
VAR101,
VAR31,
VAR116,
VAR268) ;
input VAR27;
input VAR101;
input [15:0] VAR31;
input [15:0] VAR116;
output [31:0] VAR268;
tri0 VAR27;
tri1 VAR101;
tri0 [15:0] VAR31;
tri0 [15:0] VAR116;
wire [31:0] VAR186;
VAR36 VAR240
(
.VAR27(VAR27),
.VAR138(),
.VAR101(VAR101),
.VAR31(VAR31),
.VAR116(VAR116),... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/BCHSharedKESforTiger4/src/d_KES_top.v | 38,555 | module MODULE1
(
input wire VAR123,
input wire VAR6,
input wire VAR81,
input wire [3:0] VAR83,
input wire VAR152,
input wire VAR175,
input wire VAR77,
input wire VAR127,
input wire VAR151,
output reg VAR39,
output wire VAR60,
output wire VAR55,
output reg [3:0] VAR33,
output reg VAR136,
output reg VAR17,
output reg [VA... | gpl-3.0 |
iAklis/teoca | EXPR10/MAIN.v | 8,699 | module MODULE1(
);
endmodule
module MODULE4(
input clk,
input VAR18,
input rst,
output [31:0] VAR12, VAR34,
output [31:0] VAR49,
output [6:0] VAR7,
output reg VAR51, VAR15,
output [31:0] VAR41,
output [31:0] VAR14
);
reg VAR42;
reg VAR20;
reg [2:0] VAR45;
wire [31:0] VAR36;
wire [5:0] VAR2;
wire [4:0] VAR55;
wire [4:0]... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/hps_sdram_p0_acv_ldc.v | 3,413 | module MODULE1
(
VAR13,
VAR4,
VAR21,
VAR14,
VAR36,
VAR5,
VAR17,
VAR22,
VAR35
);
parameter VAR27 = "";
parameter VAR23 = 0;
parameter VAR2 = "false";
parameter VAR26 = "false";
input VAR13;
input VAR4;
input VAR21;
input [VAR27-1:0] VAR14;
output VAR36;
output VAR5;
output VAR17;
output VAR22;
output VAR35;
wire VAR25;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311o/sky130_fd_sc_lp__a311o.functional.v | 1,471 | module MODULE1 (
VAR3 ,
VAR2,
VAR1,
VAR5,
VAR9,
VAR4
);
output VAR3 ;
input VAR2;
input VAR1;
input VAR5;
input VAR9;
input VAR4;
wire VAR11 ;
wire VAR6;
and VAR8 (VAR11 , VAR5, VAR2, VAR1 );
or VAR10 (VAR6, VAR11, VAR4, VAR9);
buf VAR7 (VAR3 , VAR6 );
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/adder_trees/verilog/adder_tree.v | 1,946 | module MODULE2 (
clk,
VAR29, VAR23, VAR22, VAR4, VAR13, VAR20, VAR5, VAR12,
sum,
);
input clk;
input [VAR9+0-1:0] VAR29, VAR23, VAR22, VAR4, VAR13, VAR20, VAR5, VAR12;
output [VAR9 :0] sum;
reg [VAR9 :0] sum;
wire [VAR9+3-1:0] VAR27;
wire [VAR9+2-1:0] VAR17, VAR32;
wire [VAR9+1-1:0] VAR15, VAR2, VAR33, VAR3;
reg [VAR9+... | mit |
SeanZarzycki/openSPARC-FPU | project/src/swrvr_clib.v | 20,922 | module MODULE2 (din, clk, VAR13, VAR16, VAR17, VAR26);
parameter VAR20 = 1;
input [VAR20-1:0] din ; input clk ;
output [VAR20-1:0] VAR13 ;
input VAR16 ; input [VAR20-1:0] VAR17 ; output [VAR20-1:0] VAR26 ;
reg [VAR20-1:0] VAR13 ;
always @ (posedge clk)
VAR13[VAR20-1:0] <= din[VAR20-1:0] ;
always @ (posedge clk)
VAR13[V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221ai/sky130_fd_sc_hs__o221ai.blackbox.v | 1,367 | module MODULE1 (
VAR2 ,
VAR7,
VAR1,
VAR4,
VAR3,
VAR6
);
output VAR2 ;
input VAR7;
input VAR1;
input VAR4;
input VAR3;
input VAR6;
supply1 VAR8;
supply0 VAR5;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3.behavioral.v | 1,759 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR9,
VAR1
);
output VAR5 ;
input VAR6 ;
input VAR9;
input VAR1;
wire VAR7 ;
wire VAR4;
not VAR3 (VAR7 , VAR6 );
VAR2 VAR10 (VAR4, VAR7, VAR9, VAR1);
buf VAR8 (VAR5 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2/sky130_fd_sc_ms__and2.pp.symbol.v | 1,263 | module MODULE1 (
input VAR4 ,
input VAR2 ,
output VAR1 ,
input VAR7 ,
input VAR3,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22ai/sky130_fd_sc_hd__o22ai.symbol.v | 1,371 | module MODULE1 (
input VAR3,
input VAR9,
input VAR5,
input VAR2,
output VAR6
);
supply1 VAR7;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
alexforencich/hdg2000 | fpga/rtl/srl_fifo_reg.v | 2,741 | module MODULE1 #
(
parameter VAR4 = 8
)
(
input wire clk,
input wire rst,
input wire VAR7, input wire [VAR4-1:0] VAR9,
input wire VAR17, output wire [VAR4-1:0] VAR6,
output wire VAR8, output wire VAR11 );
reg [VAR4-1:0] VAR2[1:0];
reg VAR12[1:0];
reg VAR1 = 0;
reg VAR5 = 0;
assign VAR6 = VAR2[VAR1];
assign VAR8 = VAR5;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221ai/sky130_fd_sc_ms__o221ai.pp.blackbox.v | 1,436 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR5 ,
VAR2 ,
VAR7 ,
VAR10 ,
VAR9,
VAR4,
VAR6 ,
VAR1
);
output VAR3 ;
input VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR7 ;
input VAR10 ;
input VAR9;
input VAR4;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
alexforencich/xfcp | rtl/xfcp_mod_gty.v | 18,265 | module MODULE1 #
(
parameter VAR4 = 16'h8A82,
parameter VAR149 = "VAR123 VAR35",
parameter VAR23 = 0,
parameter VAR122 = "",
parameter VAR1 = 10
)
(
input wire clk,
input wire rst,
input wire [7:0] VAR128,
input wire VAR76,
output wire VAR158,
input wire VAR22,
input wire VAR163,
output wire [7:0] VAR50,
output wire VA... | mit |
alexforencich/xfcp | lib/eth/rtl/arp_cache.v | 6,909 | module MODULE1 #(
parameter VAR46 = 9
)
(
input wire clk,
input wire rst,
input wire VAR26,
output wire VAR37,
input wire [31:0] VAR18,
output wire VAR57,
input wire VAR28,
output wire VAR20,
output wire [47:0] VAR31,
input wire VAR15,
output wire VAR5,
input wire [31:0] VAR7,
input wire [47:0] VAR10,
input wire VAR4
)... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sata/rtl/sata_dma_interface.v | 8,082 | module MODULE1 (
input clk,
input rst,
input enable,
output reg [7:0] VAR15,
output reg VAR26, output reg [47:0] VAR13, output reg [15:0] VAR39,
input VAR34,
input VAR25,
input [63:0] VAR14,
output VAR17,
input [23:0] VAR10,
input VAR1,
input [1:0] VAR2,
input VAR32,
input VAR12,
output VAR20,
input VAR7,
input [63:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111o/sky130_fd_sc_ms__a2111o_2.v | 2,448 | module MODULE2 (
VAR3 ,
VAR9 ,
VAR12 ,
VAR10 ,
VAR8 ,
VAR11 ,
VAR7,
VAR4,
VAR6 ,
VAR5
);
output VAR3 ;
input VAR9 ;
input VAR12 ;
input VAR10 ;
input VAR8 ;
input VAR11 ;
input VAR7;
input VAR4;
input VAR6 ;
input VAR5 ;
VAR2 VAR1 (
.VAR3(VAR3),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR11(VAR11),
.VA... | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0.v | 61,932 | module MODULE1 (
input wire VAR70, input wire VAR259, input wire VAR379, input wire [29:0] VAR141, output wire VAR329, input wire [0:0] VAR377, input wire [3:0] VAR123, input wire VAR297, output wire [31:0] VAR205, output wire VAR261, input wire VAR320, input wire [31:0] VAR239, output wire [29:0] VAR352, output wire V... | mit |
SymbiFlow/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v | 4,288 | module MODULE1 (
input [19:0] VAR2,
input [17:0] VAR30,
input [ 3:0] VAR16,
output [37:0] VAR9,
output [17:0] VAR17,
input VAR22,
input VAR33,
input [2:0] VAR27,
input VAR43,
input VAR20,
input VAR41,
input [2:0] VAR36,
input VAR10,
input [5:0] VAR29,
input VAR38,
input VAR7,
input VAR12
);
parameter [19:0] VAR40 = 20'... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b_2.v | 2,147 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR8 ,
VAR5,
VAR9,
VAR1 ,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR8 ;
input VAR5;
input VAR9;
input VAR1 ;
input VAR3 ;
VAR6 VAR7 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR4 ,
VAR2,
VAR8
);
output VAR4 ... | apache-2.0 |
asicguy/gplgpu | hdl/ramdac_sp/cur_ram_blk.v | 2,551 | module MODULE1
(
VAR3,
write,
VAR6,
VAR4,
VAR15,
VAR16,
VAR7,
VAR5
);
input VAR3;
input write;
input [8:0] VAR6;
input [7:0] VAR4;
input VAR15;
input [8:0] VAR16;
output [7:0] VAR7,
VAR5;
VAR2 VAR13
(
.VAR18 (VAR3),
.VAR10 (write),
.VAR19 (VAR6),
.VAR14 (VAR4),
.VAR11 (VAR15),
.VAR9 (1'b0),
.VAR8 (VAR16),
.VAR17 (8'b0)... | gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/comm_uart.v | 6,812 | module MODULE1 # (
parameter VAR65 = 100000000,
parameter VAR68 = 115200
) (
input VAR77,
input VAR79,
output VAR30,
input VAR9,
input VAR58,
input [31:0] VAR60,
output reg VAR49 = 1'b0,
output [255:0] VAR21,
output [95:0] VAR53
);
localparam VAR74 = VAR65 * 4;
reg VAR19 = 1'b0;
wire VAR43, VAR61;
wire [31:0] VAR6;
VAR... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_spram_64x24.v | 13,044 | module MODULE1(
VAR30, VAR27, VAR14,
clk, rst, VAR6, VAR26, VAR37, addr, VAR10, VAR13
);
parameter VAR23 = 6;
parameter VAR32 = 24;
input VAR30;
input [VAR1 - 1:0] VAR14;
output VAR27;
input clk; input rst; input VAR6; input VAR26; input VAR37; input [VAR23-1:0] addr; input [VAR32-1:0] VAR10; output [VAR32-1:0] VAR13;
... | gpl-2.0 |
grantae/uart | src/RAM_SP_AR.v | 1,094 | module MODULE1(clk, addr, VAR5, din, dout);
parameter VAR4 = 8;
parameter VAR3 = 8;
localparam VAR2 = 1 << VAR3;
input clk;
input [(VAR3-1):0] addr;
input VAR5;
input [(VAR4-1):0] din;
output [(VAR4-1):0] dout;
reg [(VAR4-1):0] VAR1 [0:(VAR2-1)];
assign dout = VAR1[addr];
always @(posedge clk) begin
if (VAR5) begin
VAR... | mit |
cpulabs/gci-std-display | rtl/display_controller/gci_std_display_font.v | 5,241 | module MODULE1(
input wire [6:0] VAR2,
output wire [111:0] VAR4
);
function [111:0] VAR3; input [6:0] VAR1;
begin
case(VAR1)
7'd0: VAR3 = 112'h0000000000000000000000000000;
7'd1: VAR3 = 112'h0000181818181010100000181800;
7'd2: VAR3 = 112'h006c6c2448000000000000000000;
7'd3: VAR3 = 112'h00002424247e2424487e48484800;
7'd... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1n/sky130_fd_sc_lp__iso1n.functional.v | 1,271 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR2
);
output VAR5 ;
input VAR1 ;
input VAR2;
wire VAR3;
not VAR4 (VAR3 , VAR2 );
or VAR6 (VAR5 , VAR1, VAR3 );
endmodule | apache-2.0 |
cokeboL/linguist | samples/Verilog/sqrt_pipelined.v | 7,437 | module MODULE1
(
input clk, input VAR13, input VAR8, input [VAR6-1:0] VAR12, output reg VAR4, output reg [VAR9-1:0] VAR7 );
parameter
VAR6 = 16; localparam
VAR9 = VAR6 / 2 + VAR6 % 2;
reg [VAR9-1:0] VAR11; reg [VAR9*VAR6-1:0] VAR10; reg [VAR9*VAR6-1:0] VAR15; wire [VAR9*VAR6-1:0] VAR5;
always @ (posedge clk or negedge ... | mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_1_stub.v | 1,409 | module MODULE1(clk, rst, din, VAR2, VAR4, dout, VAR3, VAR1)
;
input clk;
input rst;
input [93:0]din;
input VAR2;
input VAR4;
output [93:0]dout;
output VAR3;
output VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31o/sky130_fd_sc_hdll__a31o.functional.v | 1,442 | module MODULE1 (
VAR3 ,
VAR5,
VAR8,
VAR7,
VAR1
);
output VAR3 ;
input VAR5;
input VAR8;
input VAR7;
input VAR1;
wire VAR9 ;
wire VAR4;
and VAR2 (VAR9 , VAR7, VAR5, VAR8 );
or VAR10 (VAR4, VAR9, VAR1 );
buf VAR6 (VAR3 , VAR4 );
endmodule | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab4/db/ip/nios_system/submodules/nios_system_alu_carry_out.v | 1,938 | module MODULE1 (
address,
clk,
VAR1,
VAR4,
VAR2
)
;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input clk;
input VAR1;
input VAR4;
wire VAR6;
wire VAR5;
wire VAR3;
reg [ 31: 0] VAR2;
assign VAR6 = 1;
assign VAR3 = {1 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR4)
begin
if (VAR4 == 0)
VAR2 <= 0;
end
el... | gpl-3.0 |
aospan/NetUP_Dual_Universal_CI-fpga | ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v | 19,870 | module MODULE1 (
VAR102,
VAR29,
VAR33,
VAR24,
VAR73,
VAR92,
VAR108,
VAR109,
VAR90,
VAR10,
VAR50,
VAR81,
VAR122,
VAR42,
VAR47,
VAR116,
VAR4,
VAR110,
VAR67,
VAR45);
input [0:0] VAR102;
input [0:0] VAR29;
input [0:0] VAR33;
input [0:0] VAR24;
input [0:0] VAR73;
input [0:0] VAR92;
input [0:0] VAR108;
input [0:0] VAR109;
in... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221a/sky130_fd_sc_hd__o221a.blackbox.v | 1,395 | module MODULE1 (
VAR4 ,
VAR7,
VAR1,
VAR9,
VAR8,
VAR10
);
output VAR4 ;
input VAR7;
input VAR1;
input VAR9;
input VAR8;
input VAR10;
supply1 VAR6;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6T_INVBUF_LVT_SS_210930.v | 14,913 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
buf (VAR2, VAR1); | bsd-3-clause |
nyaxt/dmix | rom_firbank_32_48.v | 2,434 | module MODULE1(
input wire clk,
input wire [5:0] addr,
output wire [23:0] VAR2);
reg [23:0] VAR1;
assign VAR2 = VAR1;
always @(posedge clk) begin
case(addr)
0: VAR1 <= 24'hF55B94; 1: VAR1 <= 24'h0A4478; 2: VAR1 <= 24'hFE1404; 3: VAR1 <= 24'hFD27DD; 4: VAR1 <= 24'h023120; 5: VAR1 <= 24'h001A34; 6: VAR1 <= 24'hFF135A; 7:... | mit |
jayrandez/Processor | vga_text.v | 2,348 | module MODULE1(
VAR1,
VAR13,
VAR14,
VAR19,
VAR8,
VAR4,
VAR11,
VAR18,
VAR16,
VAR7,
VAR2
);
input wire VAR1;
input wire[9:0] VAR13;
input wire[9:0] VAR14;
input wire[13:0] VAR18;
input wire[7:0] VAR11;
input wire[3:0] VAR19;
input wire[3:0] VAR8;
input wire[3:0] VAR4;
output wire[7:0] VAR2;
output reg[9:0] VAR7;
output r... | apache-2.0 |
mbus/mbus | m3_mbus_releases/r04p2g/source/lname_mbus_master_node.v | 6,329 | module MODULE1 (
input VAR31,
input VAR27,
input VAR22,
output VAR83,
input VAR8,
output VAR36,
input [VAR3-1:0] VAR82,
input [VAR87-1:0] VAR75,
input VAR54,
input VAR51,
input VAR14,
output VAR85,
output [VAR3-1:0] VAR7,
output [VAR87-1:0] VAR24,
output VAR47,
input VAR78,
output VAR66,
output VAR5,
output VAR77,
outp... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1n/sky130_fd_sc_lp__iso1n.functional.pp.v | 2,048 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR13,
VAR12 ,
VAR7 ,
VAR14 ,
VAR9
);
output VAR1 ;
input VAR2 ;
input VAR13;
input VAR12 ;
input VAR7 ;
input VAR14 ;
input VAR9 ;
wire VAR4 ;
wire VAR15 ;
wire VAR11;
not VAR6 (VAR4 , VAR13 );
VAR3 VAR8 (VAR15 , VAR2, VAR12, VAR7 );
VAR3 VAR5 (VAR11, VAR4, VAR12, VAR7 );
or VAR10 (VAR1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0n/sky130_fd_sc_lp__iso0n.pp.blackbox.v | 1,297 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR5,
VAR7 ,
VAR4 ,
VAR2 ,
VAR6
);
output VAR3 ;
input VAR1 ;
input VAR5;
input VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
ultraembedded/altor32 | rtl/peripheral/intr_periph.v | 6,528 | module MODULE1
(
VAR16,
VAR19,
VAR9,
VAR24,
VAR8,
VAR20,
VAR25,
VAR10,
VAR11,
VAR13,
VAR5,
VAR2,
VAR18,
VAR14,
VAR12,
VAR1,
VAR15
);
parameter VAR6 = 1;
parameter VAR23 = VAR6 + 8;
input VAR16 ;
input VAR19 ;
output VAR9 ;
input VAR24 ;
input VAR8 ;
input VAR20 ;
input VAR25 ;
input VAR10 ;
input VAR11 ;
input VAR13 ;
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211oi/sky130_fd_sc_lp__a211oi.functional.v | 1,457 | module MODULE1 (
VAR5 ,
VAR2,
VAR8,
VAR10,
VAR7
);
output VAR5 ;
input VAR2;
input VAR8;
input VAR10;
input VAR7;
wire VAR3 ;
wire VAR4;
and VAR6 (VAR3 , VAR2, VAR8 );
nor VAR1 (VAR4, VAR3, VAR10, VAR7);
buf VAR9 (VAR5 , VAR4 );
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/subsys/e203_subsys_top.v | 44,453 | module MODULE1(
input VAR138,
output VAR227,
input VAR249,
output VAR310,
input VAR22,
input VAR115,
input VAR109,
input VAR161,
output VAR52,
output VAR383,
output VAR277,
output VAR223,
output VAR150,
input VAR46,
output VAR148,
output VAR352,
output VAR168,
output VAR280,
output VAR244,
input VAR54,
output VAR37,
ou... | apache-2.0 |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/sdram_control/sdram_pll0/sdram_pll0_0002.v | 2,148 | module MODULE1(
input wire VAR49,
input wire rst,
output wire VAR50,
output wire VAR48,
output wire VAR31
);
VAR28 #(
.VAR68("false"),
.VAR29("50.0 VAR21"),
.VAR15("VAR51"),
.VAR24(2),
.VAR17("100.000000 VAR21"),
.VAR43("0 VAR58"),
.VAR53(50),
.VAR33("100.000000 VAR21"),
.VAR34("-3000 VAR58"),
.VAR39(50),
.VAR25("0 VAR... | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/01BLUETOOTH/Version_02/02 verilog/periferico_BT/recepcion.v | 1,057 | module MODULE1(input VAR1,
output reg VAR2,
output reg [7:0] dout,
input wire VAR3); | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtn/sky130_fd_sc_hd__dlxtn.functional.pp.v | 1,777 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR7,
VAR9 ,
VAR13 ,
VAR10 ,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR7;
input VAR9 ;
input VAR13 ;
input VAR10 ;
input VAR3 ;
wire VAR6 ;
wire VAR2;
not VAR11 (VAR6 , VAR7 );
VAR8 VAR12 (VAR2 , VAR1, VAR6, , VAR9, VAR13);
buf VAR5 (VAR4 , VAR2 );
endmodule | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v | 1,152 | module MODULE1(
clk,
VAR4,
din,
dout
);
parameter VAR1 = 1;
parameter VAR7 = 3;
input clk;
input VAR4;
input [VAR1-1:0] din;
output [VAR1-1:0] dout;
genvar VAR3;
generate
for (VAR3=0; VAR3<VAR1; VAR3=VAR3+1)
begin : sync
VAR5 #(.VAR2(VAR7))
VAR6 (
.clk(clk),
.VAR4(VAR4),
.din(din[VAR3]),
.dout(dout[VAR3])
);
end
endgen... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2b/sky130_fd_sc_hs__and2b_4.v | 2,009 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR3 ,
VAR4,
VAR5
);
output VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR4;
input VAR5;
VAR7 VAR2 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR6 ,
VAR1,
VAR3
);
output VAR6 ;
input VAR1;
input VAR3 ;
supply1 VAR4;
supply0 VAR5;
VAR7 VAR2 ... | apache-2.0 |
pwwu/FPGA | VGAbased/vga_game_text.v | 8,917 | module MODULE1
(
input wire clk,
input wire [1:0] VAR15,
input wire [3:0] VAR23, VAR7,
input wire [9:0] VAR14, VAR5,
output wire [3:0] VAR26,
output reg [2:0] VAR31
);
wire [10:0] VAR3;
reg [6:0] VAR25, VAR9, VAR4,
VAR2, VAR10;
reg [3:0] VAR22;
wire [3:0] VAR20, VAR19, VAR30, VAR13;
reg [2:0] VAR21;
wire [2:0] VAR11, V... | mit |
P3Stor/P3Stor | ftl/command_issue.v | 9,892 | module MODULE1(
clk,
rst,
VAR49,
VAR13,
VAR41,
VAR28,
VAR38,
VAR2,
VAR9,
VAR20,
VAR52,
VAR29,
VAR42,
VAR32,
VAR6,
VAR30,
addr,
VAR27,
VAR23,
VAR12,
VAR44,
VAR21,
VAR43,
VAR26,
VAR1,
VAR18, VAR25,
state
);
input clk;
input rst;
input VAR49;
input VAR13;
input VAR41;
input VAR28;
input [VAR45*4-1:0] VAR38;
input [VAR45*4... | gpl-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_du.v | 45,458 | module MODULE1(
clk, rst,
VAR83, VAR56, VAR160, VAR26,
VAR82, VAR142,
VAR58, VAR52, VAR64, VAR169,
VAR158, VAR131,
VAR213, VAR36, VAR168, VAR98, VAR111,
VAR176, VAR139, VAR59, VAR214,
VAR189, VAR97, VAR208, VAR68, VAR51,
VAR102, VAR193, VAR27, VAR191, VAR202, VAR173,
VAR196, VAR185, VAR181, VAR182, VAR212, VAR6
);
para... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111oi/sky130_fd_sc_hs__a2111oi.pp.symbol.v | 1,375 | module MODULE1 (
input VAR2 ,
input VAR1 ,
input VAR6 ,
input VAR7 ,
input VAR3 ,
output VAR5 ,
input VAR4,
input VAR8
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_2.functional.pp.v | 1,386 | module MODULE1( VAR11, VAR5, VAR7, VAR10, VAR2, VAR15 );
input VAR10, VAR7, VAR11;
inout VAR2, VAR15;
output VAR5;
wire VAR17;
not VAR12( VAR17, VAR10 );
wire VAR1;
not VAR4( VAR1, VAR11 );
wire VAR13;
and VAR9( VAR13, VAR17, VAR1 );
wire VAR8;
not VAR14( VAR8, VAR7 );
wire VAR3;
and VAR6( VAR3, VAR8, VAR1 );
or VAR16(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_mux_2to1_n/sky130_fd_sc_hs__udp_mux_2to1_n.symbol.v | 1,289 | module MODULE1 (
input VAR3,
input VAR1,
output VAR4 ,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1p/sky130_fd_sc_lp__iso1p_lp.v | 2,156 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR6,
VAR4,
VAR1 ,
VAR2 ,
VAR8
);
output VAR7 ;
input VAR9 ;
input VAR6;
input VAR4;
input VAR1 ;
input VAR2 ;
input VAR8 ;
VAR5 VAR3 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR7 ,
VAR9 ,
VAR6
);
output VAR7... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbn/sky130_fd_sc_hd__sdfbbn.behavioral.v | 3,407 | module MODULE1 (
VAR7 ,
VAR18 ,
VAR20 ,
VAR28 ,
VAR12 ,
VAR34 ,
VAR2 ,
VAR30
);
output VAR7 ;
output VAR18 ;
input VAR20 ;
input VAR28 ;
input VAR12 ;
input VAR34 ;
input VAR2 ;
input VAR30;
supply1 VAR23;
supply0 VAR37;
supply1 VAR36 ;
supply0 VAR17 ;
wire VAR39 ;
wire VAR38 ;
wire VAR11 ;
wire VAR22 ;
reg VAR35 ;
wir... | apache-2.0 |
alexforencich/verilog-ethernet | lib/axis/rtl/axis_async_fifo_adapter.v | 12,583 | module MODULE1 #
(
parameter VAR24 = 4096,
parameter VAR4 = 8,
parameter VAR28 = (VAR4>8),
parameter VAR40 = ((VAR4+7)/8),
parameter VAR53 = 8,
parameter VAR14 = (VAR53>8),
parameter VAR27 = ((VAR53+7)/8),
parameter VAR17 = 0,
parameter VAR32 = 8,
parameter VAR34 = 0,
parameter VAR36 = 8,
parameter VAR30 = 1,
parameter... | mit |
golfit/QcmMasterController | QcmMcCalibrate.v | 6,402 | module MODULE1(clk, VAR10, VAR7, VAR9, VAR11, VAR6, VAR2, VAR1, VAR12, VAR3, VAR5);
input clk, VAR10; output wire [6:0] VAR7, VAR9; output VAR11, VAR6; output VAR2; output VAR1; output VAR12; output VAR3; output VAR5;
wire [13:0] VAR4; wire [6:0] state;
reg [3:0] VAR8; | mit |
fabianz66/cursos-tec | taller-digital/Lab2/laboratorio2/completo.v | 1,838 | module MODULE1;
reg clk;
reg rst;
reg VAR5;
reg VAR16;
reg VAR10;
reg VAR18;
reg VAR4;
reg VAR13;
reg VAR15;
reg VAR14;
reg VAR3;
wire VAR8;
wire VAR1;
wire VAR2;
wire VAR6;
wire VAR12;
wire VAR7;
wire VAR17;
VAR11 VAR9 (
.clk(clk),
.rst(rst),
.VAR5(VAR5),
.VAR16(VAR16),
.VAR10(VAR10),
.VAR18(VAR18),
.VAR4(VAR4),
.VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.symbol.v | 1,257 | module MODULE1 (
input VAR2,
input VAR3,
output VAR1 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2/sky130_fd_sc_hdll__mux2.pp.symbol.v | 1,333 | module MODULE1 (
input VAR7 ,
input VAR4 ,
output VAR3 ,
input VAR6 ,
input VAR2 ,
input VAR5,
input VAR1,
input VAR8
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_circular_ptr.v | 2,333 | module MODULE1 #(parameter VAR7(VAR5)
, parameter VAR7(VAR11)
, parameter VAR3 = VAR19(VAR5)
)
(input clk
, input VAR20
, input [VAR12(VAR11+1)-1:0] VAR17
, output [VAR3-1:0] VAR13
, output [VAR3-1:0] VAR15
);
logic [VAR3-1:0] VAR9, VAR4, VAR16;
logic [VAR3:0] VAR21;
assign VAR13 = VAR9;
assign VAR15 = VAR4;
always @(p... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbn/sky130_fd_sc_ls__dfbbn_2.v | 2,601 | module MODULE1 (
VAR10 ,
VAR5 ,
VAR7 ,
VAR4 ,
VAR11 ,
VAR8,
VAR2 ,
VAR3 ,
VAR9 ,
VAR1
);
output VAR10 ;
output VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR11 ;
input VAR8;
input VAR2 ;
input VAR3 ;
input VAR9 ;
input VAR1 ;
VAR6 VAR12 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR8(VAR8),
.VA... | apache-2.0 |
jayant-sharma/ft2232h-fifo | hdl/FT_AsyncMode.v | 1,527 | module MODULE1 #(
parameter VAR17 = 8,
parameter VAR4 = 12
)(
input clk,
input VAR14,
input [VAR17-1:0] VAR3,
input VAR9,
output reg VAR6,
output reg [VAR17-1:0] VAR10,
input VAR5,
output reg VAR16,
input VAR11,
output VAR20,
inout [VAR17-1:0] VAR17
);
reg [2:0] VAR15, VAR12;
reg [2:0] VAR18, VAR19;
reg [1:0] VAR13;
pa... | unlicense |
ace8957/EECE6017C | mem.v | 1,460 | module MODULE1(VAR12, VAR8, VAR11, VAR6, VAR7, VAR2);
input VAR12, VAR8, VAR11, VAR6;
output VAR7;
output [8:0] VAR2;
wire [4:0] VAR9; wire [8:0] VAR4;
counter VAR5(VAR12, VAR11, VAR9);
memory VAR1(VAR9, VAR12, VAR4);
VAR3 VAR10(VAR4, VAR11, VAR8, VAR6, VAR7, VAR2);
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_1.functional.v | 1,142 | module MODULE1( VAR6, VAR5, VAR12 );
input VAR5, VAR6;
output VAR12;
wire VAR3;
not VAR8( VAR3, VAR6 );
wire VAR9;
and VAR2( VAR9, VAR3, VAR5 );
wire VAR10;
not VAR11( VAR10, VAR5 );
wire VAR1;
and VAR7( VAR1, VAR10, VAR6 );
or VAR4( VAR12, VAR9, VAR1 );
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_4d_2c_v1_00_a/hdl/verilog/cf_ddsv_intp.v | 10,190 | module MODULE1 (
VAR44,
VAR40,
VAR6,
VAR2,
VAR16,
VAR38,
VAR21,
VAR11,
VAR4,
VAR43,
VAR9,
VAR8,
VAR36,
VAR47,
VAR26);
input VAR44;
output VAR40;
input [95:0] VAR6;
output [15:0] VAR2;
output [15:0] VAR16;
output [15:0] VAR38;
output [15:0] VAR21;
output [15:0] VAR11;
output [15:0] VAR4;
input VAR43;
input VAR9;
input [... | mit |
mrehkopf/sd2snes | verilog/sd2snes_cx4/cx4_pgmrom.v | 9,197 | module MODULE1 (
VAR38,
VAR5,
VAR22,
VAR10,
VAR59,
VAR42);
input VAR38;
input [7:0] VAR5;
input [8:0] VAR22;
input [9:0] VAR10;
input VAR59;
output [15:0] VAR42;
tri1 VAR38;
tri0 VAR59;
wire [15:0] VAR60;
wire [15:0] VAR42 = VAR60[15:0];
VAR18 VAR8 (
.VAR29 (VAR10),
.VAR37 (VAR22),
.VAR21 (VAR38),
.VAR27 (VAR5),
.VAR50... | gpl-2.0 |
olajep/oh | src/common/hdl/oh_memory_dp.v | 2,662 | module MODULE1 # (parameter VAR7 = 104, parameter VAR8 = 32, parameter VAR21 = "", parameter VAR16 = 8, parameter VAR18 = VAR20(VAR8) )
( input VAR28, input VAR1, input [VAR7-1:0] VAR12, input [VAR18-1:0] VAR11, input [VAR7-1:0] VAR13, input VAR6, input VAR5, input [VAR18-1:0] VAR25, output [VAR7-1:0] VAR9, input VAR26... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41ai/sky130_fd_sc_ms__o41ai.pp.symbol.v | 1,381 | module MODULE1 (
input VAR6 ,
input VAR4 ,
input VAR1 ,
input VAR10 ,
input VAR2 ,
output VAR8 ,
input VAR9 ,
input VAR5,
input VAR7,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21bo/sky130_fd_sc_lp__a21bo.blackbox.v | 1,383 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR3 ,
VAR6
);
output VAR1 ;
input VAR8 ;
input VAR3 ;
input VAR6;
supply1 VAR5;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_pipe_eq.v | 34,356 | module MODULE1 #
(
parameter VAR72 = "VAR132",
parameter VAR11 = 1
)
(
input VAR24,
input VAR112,
input VAR59,
input [ 1:0] VAR2,
input [ 3:0] VAR60,
input [ 3:0] VAR124,
input [ 5:0] VAR97,
input [ 1:0] VAR14,
input [ 2:0] VAR20,
input [ 5:0] VAR12,
input [ 3:0] VAR135,
input VAR36,
input [17:0] VAR106,
input VAR48,
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31a/sky130_fd_sc_hd__o31a_1.v | 2,322 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR5 ,
VAR2 ,
VAR10 ,
VAR3,
VAR7,
VAR6 ,
VAR1
);
output VAR4 ;
input VAR9 ;
input VAR5 ;
input VAR2 ;
input VAR10 ;
input VAR3;
input VAR7;
input VAR6 ;
input VAR1 ;
VAR11 VAR8 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR... | apache-2.0 |
vvk/sysrek | skin_color_segm/rgb2hsv.v | 5,888 | module MODULE1(
input clk,
input VAR81,
input [7:0] VAR26,
input [7:0] VAR42,
input [7:0] VAR59,
input VAR7, input VAR54, input VAR1,
output [7:0] VAR4,
output [7:0] VAR63,
output [7:0] VAR36,
output VAR28, output VAR62, output VAR48
);
wire [7:0] VAR32;
wire [7:0] VAR12;
wire [7:0] VAR80;
wire [7:0] VAR15;
wire [7:0] ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtp/sky130_fd_sc_hs__dfrtp.pp.blackbox.v | 1,302 | module MODULE1 (
VAR6,
VAR2 ,
VAR5 ,
VAR3 ,
VAR4 ,
VAR1
);
input VAR6;
input VAR2 ;
input VAR5 ;
output VAR3 ;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_4.functional.v | 1,494 | module MODULE1( VAR6, VAR9, VAR13, VAR11, VAR16 );
input VAR16, VAR11, VAR9, VAR6;
output VAR13;
wire VAR10;
not VAR8( VAR10, VAR16 );
wire VAR1;
not VAR15( VAR1, VAR11 );
wire VAR2;
and VAR12( VAR2, VAR10, VAR1 );
wire VAR3;
not VAR5( VAR3, VAR9 );
wire VAR17;
not VAR7( VAR17, VAR6 );
wire VAR14;
and VAR18( VAR14, VAR... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_4.behavioral.pp.v | 2,820 | module MODULE1( VAR3, VAR10, VAR11, VAR25, VAR7, VAR9 );
input VAR11, VAR10, VAR3;
inout VAR7, VAR9;
output VAR25;
reg VAR1;
VAR16 VAR4(.VAR3(VAR3),.VAR10(VAR10),.VAR11(VAR11),.VAR25(VAR25),.VAR7(VAR7),.VAR9(VAR9),.VAR1(VAR1));
VAR16 VAR15(.VAR3(VAR3),.VAR10(VAR10),.VAR11(VAR11),.VAR25(VAR25),.VAR7(VAR7),.VAR9(VAR9),.V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtn/sky130_fd_sc_lp__dlrtn.blackbox.v | 1,354 | module MODULE1 (
VAR4 ,
VAR2,
VAR3 ,
VAR6
);
output VAR4 ;
input VAR2;
input VAR3 ;
input VAR6 ;
supply1 VAR7;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_dmmu_top.v | 10,222 | module MODULE1(
clk, rst,
VAR25, VAR2, VAR52, VAR6, VAR3, VAR23,
VAR40, VAR51,
VAR21, VAR27, VAR16, VAR30, VAR39,
VAR34, VAR20, VAR47,
VAR32, VAR29, VAR35, VAR1, VAR36
);
parameter VAR31 = VAR12;
parameter VAR8 = VAR12;
input clk;
input rst;
input VAR25;
input VAR2;
input VAR52;
input [VAR8-1:0] VAR6;
input VAR3;
input... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/0_default_implementation/syn/verilog/convolve_kernel.v | 19,131 | module MODULE1 (
VAR123,
VAR49,
VAR107,
VAR82,
VAR35,
VAR79,
VAR24,
VAR70,
VAR29,
VAR31,
VAR4,
VAR65,
VAR51,
VAR15,
VAR7,
VAR89,
VAR12,
VAR23,
VAR127,
VAR138,
VAR149,
VAR97,
VAR108,
VAR95,
VAR34,
VAR116,
VAR146
);
parameter VAR72 = 18'd1;
parameter VAR10 = 18'd2;
parameter VAR41 = 18'd4;
parameter VAR8 = 18'd8;
paramet... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_intp2_16.v | 7,408 | module MODULE1 (
clk,
VAR18,
VAR43,
VAR8,
VAR53,
VAR32,
VAR66,
VAR51,
VAR30,
VAR62,
VAR5,
VAR54,
VAR35,
VAR45,
VAR9,
VAR70,
VAR2,
VAR61);
input clk;
input [15:0] VAR18;
output [15:0] VAR43;
output [15:0] VAR8;
output [15:0] VAR53;
output [15:0] VAR32;
output [15:0] VAR66;
output [15:0] VAR51;
output [15:0] VAR30;
outpu... | mit |
plindstroem/oh | common/hdl/arbiter_priority.v | 1,398 | module MODULE1(
VAR1, VAR5,
request
);
parameter VAR2=99;
input [VAR2-1:0] request; output [VAR2-1:0] VAR1; output [VAR2-1:0] VAR5;
genvar VAR4;
assign VAR5[0] = 1'b0;
generate for (VAR4=VAR2-1; VAR4>=1; VAR4=VAR4-1) begin : VAR3
assign VAR5[VAR4] = |request[VAR4-1:0];
end
endgenerate
assign VAR1[VAR2-1:0] = request[VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4b/sky130_fd_sc_hs__and4b.functional.v | 1,876 | module MODULE1 (
VAR8,
VAR13,
VAR11 ,
VAR1 ,
VAR14 ,
VAR7 ,
VAR15
);
input VAR8;
input VAR13;
output VAR11 ;
input VAR1 ;
input VAR14 ;
input VAR7 ;
input VAR15 ;
wire VAR15 VAR2 ;
wire VAR12 ;
wire VAR6;
not VAR10 (VAR2 , VAR1 );
and VAR4 (VAR12 , VAR2, VAR14, VAR7, VAR15 );
VAR3 VAR5 (VAR6, VAR12, VAR8, VAR13);
buf V... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/8-way/src/ip_pcie/PCIeGen2x8If128_stub.v | 7,229 | module MODULE1(VAR59, VAR5, VAR52, VAR63, VAR45, VAR2, VAR24, VAR32, VAR19, VAR29, VAR8, VAR25, VAR80, VAR11, VAR79, VAR47, VAR62, VAR78, VAR35, VAR9, VAR14, VAR81, VAR4, VAR50, VAR73, VAR83, VAR75, VAR41, VAR27, VAR56, VAR3, VAR15, VAR46, VAR87, VAR66, VAR34, VAR33, VAR37, VAR76, VAR18, VAR21, VAR36, VAR84, VAR31, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/inv/sky130_fd_sc_hd__inv.pp.blackbox.v | 1,225 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR2,
VAR5,
VAR6 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR2;
input VAR5;
input VAR6 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4b/sky130_fd_sc_hd__nand4b_4.v | 2,311 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR10 ,
VAR4 ,
VAR1 ,
VAR6,
VAR9,
VAR3 ,
VAR2
);
output VAR7 ;
input VAR5 ;
input VAR10 ;
input VAR4 ;
input VAR1 ;
input VAR6;
input VAR9;
input VAR3 ;
input VAR2 ;
VAR8 VAR11 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn.functional.pp.v | 1,872 | module MODULE1 (
VAR4 ,
VAR11 ,
VAR5,
VAR10,
VAR8,
VAR2 ,
VAR3
);
output VAR4 ;
input VAR11 ;
input VAR5;
input VAR10;
input VAR8;
input VAR2 ;
input VAR3 ;
wire VAR12 ;
wire VAR1;
VAR9 VAR6 (VAR12 , VAR11, VAR10, VAR8 );
VAR9 VAR13 (VAR1, VAR5, VAR10, VAR8 );
notif0 VAR7 (VAR4 , VAR12, VAR1);
endmodule | apache-2.0 |
xesscorp/pygmyhdl | docs/_build/singlehtml/notebooks/4_blockram/record_play.v | 3,117 | module MODULE1 (
VAR11,
VAR2,
VAR14,
VAR1
);
input VAR11;
input VAR2;
input VAR14;
output [4:0] VAR1;
reg [4:0] VAR1;
reg [0:0] VAR13;
reg wr;
reg VAR5;
reg [0:0] VAR12;
reg reset;
reg [2:0] state;
reg [10:0] VAR7;
reg [10:0] addr;
reg [16:0] VAR6;
reg [0:0] VAR15;
reg [0:0] VAR10 [0:2048-1];
always @(posedge VAR11) be... | mit |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/hb/acc.v | 1,210 | module MODULE1 (input VAR2, input reset, input VAR4, input VAR5, output reg VAR1,
input signed [30:0] VAR3, output reg signed [33:0] sum );
always @(posedge VAR2)
if(reset)
sum <= 34'd0;
else if(VAR4)
sum <= VAR3;
else if(VAR5)
sum <= sum + VAR3;
always @(posedge VAR2)
VAR1 <= VAR5;
endmodule | gpl-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_39.v | 28,296 | module MODULE1 (
clk,
reset,
VAR75,
VAR154,
VAR66,
VAR198,
VAR184
);
parameter VAR186 = 18;
parameter VAR159 = 39;
parameter VAR17 = 20;
localparam VAR48 = 46;
input clk;
input reset;
input VAR75;
input VAR154;
input [VAR186-1:0] VAR66; output VAR198;
output [VAR186-1:0] VAR184;
localparam VAR152 = 18; localparam VAR68... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/triple_speed_ethernet-library/altera_tse_rgmii_out4.v | 4,352 | module MODULE1 (
VAR18,
VAR19,
VAR4,
VAR17,
VAR9);
input VAR18;
input [3:0] VAR19;
input [3:0] VAR4;
input VAR17;
output [3:0] VAR9;
wire [3:0] VAR13;
wire [3:0] VAR9 = VAR13[3:0];
VAR2 VAR14 (
.VAR17 (VAR17),
.VAR19 (VAR19),
.VAR18 (VAR18),
.VAR4 (VAR4),
.VAR9 (VAR13),
.VAR15 (1'b0),
.VAR12 (1'b1),
.VAR10 (1'b1));
VA... | mit |
aj-michael/Digital-Systems | Lab4-Part2-RAMwithHyperTerminalDisplay/HEXto7Segment.v | 1,053 | module MODULE1(VAR7,VAR18);
input [3:0] VAR7;
output reg [7:0] VAR18;
always @ (VAR7)
case (VAR7)
0: VAR18 <= 8'VAR4;
1: VAR18 <= 8'VAR19;
2: VAR18 <= 8'VAR2;
3: VAR18 <= 8'VAR3;
4: VAR18 <= 8'VAR8;
5: VAR18 <= 8'VAR12;
6: VAR18 <= 8'VAR16;
7: VAR18 <= 8'VAR14;
8: VAR18 <= 8'VAR10;
9: VAR18 <= 8'VAR11;
10: VAR18 <= 8'V... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_common/syn/v/bsg_mem_3r1w_sync.v | 4,215 | if (VAR5 == VAR36 && VAR33 == VAR3) \
begin: VAR23 \
VAR20 \
VAR22 \
(.VAR6 ( VAR6 ) \
,.VAR11 ( VAR11 ) \
,.VAR12 ( VAR12 ) \
,.VAR47( VAR47 ) \
,.VAR4( VAR4 ) \
,.VAR45 ( VAR25 ) \
,.VAR52( VAR35 ) \
,.VAR8( VAR1 ) \
); \
VAR20 \
VAR39 \
(.VAR6 ( VAR6 ) \
,.VAR11 ( VAR11 ) \
,.VAR12 ( VAR12 ) \
,.VAR47( VAR47 ) \
,.V... | bsd-3-clause |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/FIFO_DDR_DATA_IN.v | 13,419 | module MODULE1(
rst,
VAR134,
VAR2,
din,
VAR88,
VAR275,
dout,
VAR194,
VAR36
);
input rst;
input VAR134;
input VAR2;
input [15 : 0] din;
input VAR88;
input VAR275;
output [15 : 0] dout;
output VAR194;
output VAR36;
VAR96 #(
.VAR50(0),
.VAR7(0),
.VAR45(0),
.VAR57(0),
.VAR329(0),
.VAR51(0),
.VAR345(0),
.VAR324(32),
.VAR22(... | gpl-2.0 |
alexforencich/hdg2000 | fpga/rtl/soc_interface_wb_32.v | 12,927 | module MODULE1
(
input wire clk,
input wire rst,
input wire [7:0] VAR5,
input wire VAR42,
output wire VAR21,
input wire VAR2,
output wire [7:0] VAR30,
output wire VAR9,
input wire VAR33,
output wire VAR12,
output wire [35:0] VAR39, input wire [31:0] VAR22, output wire [31:0] VAR20, output wire VAR26, output wire [3:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22oi/sky130_fd_sc_hdll__a22oi.behavioral.pp.v | 2,186 | module MODULE1 (
VAR18 ,
VAR5 ,
VAR6 ,
VAR12 ,
VAR19 ,
VAR16,
VAR11,
VAR2 ,
VAR4
);
output VAR18 ;
input VAR5 ;
input VAR6 ;
input VAR12 ;
input VAR19 ;
input VAR16;
input VAR11;
input VAR2 ;
input VAR4 ;
wire VAR10 ;
wire VAR13 ;
wire VAR8 ;
wire VAR1;
nand VAR17 (VAR10 , VAR6, VAR5 );
nand VAR14 (VAR13 , VAR19, VAR12... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4b/sky130_fd_sc_hd__or4b_1.v | 2,291 | module MODULE2 (
VAR2 ,
VAR11 ,
VAR3 ,
VAR9 ,
VAR5 ,
VAR10,
VAR1,
VAR8 ,
VAR4
);
output VAR2 ;
input VAR11 ;
input VAR3 ;
input VAR9 ;
input VAR5 ;
input VAR10;
input VAR1;
input VAR8 ;
input VAR4 ;
VAR6 VAR7 (
.VAR2(VAR2),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR8(VAR8),
.... | apache-2.0 |
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