repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
CospanDesign/nysa-artemis-usb2-platform | artemis_usb2/slave/wb_artemis_pcie_platform/rtl/c/axi_basic_rx.v | 8,384 | module MODULE1 #(
parameter VAR4 = 128, parameter VAR19 = "VAR29", parameter VAR25 = "VAR3", parameter VAR11 = "VAR3", parameter VAR36 = 1,
parameter VAR35 = (VAR4 == 128) ? 2 : 1, parameter VAR27 = VAR4 / 8 ) (
output [VAR4-1:0] VAR20, output VAR12, input VAR32, output [VAR27-1:0] VAR10, output VAR15, output [21:0] VA... | gpl-2.0 |
rbarzic/arty-cm0-designstart | ips/clock_manager/arty_mmcm/arty_mmcm_clk_wiz.v | 6,510 | module MODULE1
( input VAR6,
output VAR23,
input VAR54,
output VAR33
);
VAR47 VAR53
(.VAR70 (VAR56),
.VAR12 (VAR6));
wire [15:0] VAR64;
wire VAR32;
wire VAR10;
wire VAR79;
wire VAR15;
wire VAR41;
wire VAR51;
wire VAR17;
wire VAR5;
wire VAR82;
wire VAR18;
wire VAR81;
wire VAR55;
wire VAR25;
wire VAR57;
wire VAR42;
wire ... | gpl-2.0 |
chriswynnyk/american-put-verilog | american_put_stratix/src/amer_put.v | 15,970 | module MODULE1(
VAR202,
VAR66,
VAR234,
VAR191,
VAR282,
VAR216,
VAR317,
VAR108,
VAR10,
VAR254,
VAR80
);
input VAR202;
input VAR66;
input VAR234;
input VAR191;
input VAR282;
input [63:0] VAR216;
input [63:0] VAR317;
input [63:0] VAR108;
input [63:0] VAR10;
input [63:0] VAR254;
output [63:0] VAR80;
wire [63:0] VAR244;
wir... | apache-2.0 |
lbl-cal/StanfordNoC | router/src/clib/c_select_mofn.v | 2,782 | module MODULE1
(select, VAR8, VAR1);
parameter VAR7 = 4;
parameter VAR2 = 32;
parameter VAR4 = VAR16;
parameter VAR10 = VAR14;
input [0:VAR7-1] select;
input [0:VAR7*VAR2-1] VAR8;
output [0:VAR2-1] VAR1;
wire [0:VAR2-1] VAR1;
generate
genvar VAR9;
for(VAR9 = 0; VAR9 < VAR2; VAR9 = VAR9 + 1)
begin:VAR13
wire [0:VAR7-1] ... | bsd-2-clause |
ShirmanXia/EE469SPRING16 | lab3/db/ip/nios_system/submodules/nios_system_onchip_memory2_0.v | 3,121 | module MODULE1 (
address,
VAR28,
VAR33,
clk,
VAR19,
reset,
VAR25,
write,
VAR23,
VAR21
)
;
parameter VAR6 = "MODULE1.VAR16";
output [ 31: 0] VAR21;
input [ 14: 0] address;
input [ 3: 0] VAR28;
input VAR33;
input clk;
input VAR19;
input reset;
input VAR25;
input write;
input [ 31: 0] VAR23;
wire VAR11;
wire [ 31: 0] VAR2... | gpl-3.0 |
vvk/sysrek | arithm/arithm2.v | 2,198 | module MODULE1(
input clk,
input VAR18,
input [17:0] VAR6,
input [7:0] VAR21,
input [11:0] VAR13,
input [7:0] VAR19,
input [13:0] VAR27,
input [18:0] VAR34,
output [36:0] VAR26
);
wire signed [12:0] VAR32;
wire signed [18:0] VAR37;
wire signed [11:0] VAR2;
wire signed [10:0] VAR33;
wire signed [14:0] VAR24;
wire signed... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2i/sky130_fd_sc_ms__mux2i.pp.blackbox.v | 1,317 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR3 ,
VAR6 ,
VAR2,
VAR7,
VAR5 ,
VAR1
);
output VAR4 ;
input VAR8 ;
input VAR3 ;
input VAR6 ;
input VAR2;
input VAR7;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
andykarpov/radio-86rk-wxeda | src/rom/font.v | 6,349 | module MODULE1 (
address,
VAR6,
VAR33);
input [9:0] address;
input VAR6;
output [7:0] VAR33;
tri1 VAR6;
wire [7:0] VAR32;
wire [7:0] VAR33 = VAR32[7:0];
VAR37 VAR26 (
.VAR48 (VAR6),
.VAR45 (address),
.VAR49 (VAR32),
.VAR16 (1'b0),
.VAR46 (1'b0),
.VAR4 (1'b1),
.VAR21 (1'b0),
.VAR43 (1'b0),
.VAR41 (1'b1),
.VAR42 (1'b1),
... | bsd-2-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/tse_mac3_loopback.v | 3,192 | module MODULE1 (
VAR4,
VAR1,
VAR2
);
output VAR4;
input VAR1;
output VAR2;
reg VAR3; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbn/sky130_fd_sc_hd__dlrbn.functional.pp.v | 2,214 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR19,
VAR13 ,
VAR10 ,
VAR7 ,
VAR5 ,
VAR3 ,
VAR6
);
output VAR11 ;
output VAR2 ;
input VAR19;
input VAR13 ;
input VAR10 ;
input VAR7 ;
input VAR5 ;
input VAR3 ;
input VAR6 ;
wire VAR12 ;
wire VAR8;
wire VAR16 ;
not VAR18 (VAR12 , VAR19 );
not VAR14 (VAR8, VAR10 );
VAR15 VAR17 VAR4 (VAR16... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/011J1G2/hdl/divider/peripheral_div.v | 1,709 | module MODULE1(clk , rst , din , VAR10 , addr , rd , wr, dout );
input clk;
input rst;
input [15:0]din;
input VAR10;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
reg [5:0] VAR9;
reg [15:0] VAR3=0;reg [15:0] VAR11=0;
reg VAR2=0;
wire [15:0] VAR6; wire VAR5;
always @(*) VAR1 (addr)
4'h0:begin VAR9 = (VAR10... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_tu_edge.v | 18,779 | module MODULE1(
VAR4,
VAR16,VAR1,VAR6 ,VAR13 ,VAR12 ,VAR15 ,VAR10 ,VAR11 ,
VAR14,VAR2,VAR8,VAR7,VAR9,VAR5,VAR3,VAR17,
h1,h2,h3,h4,h5,h6,h7
);
input [20:0] VAR4 ;
output [6:0] VAR16,VAR1,VAR6 ,VAR13 ,VAR12 ,VAR15 ,VAR10 ,VAR11 ;
output [6:0] VAR14,VAR2,VAR8,VAR7,VAR9,VAR5,VAR3,VAR17;
output [15:0] h1,h2,h3,h4,h5,h6,h7 ;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2/sky130_fd_sc_hdll__or2.behavioral.pp.v | 1,792 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR10 ,
VAR12,
VAR3,
VAR7 ,
VAR6
);
output VAR5 ;
input VAR4 ;
input VAR10 ;
input VAR12;
input VAR3;
input VAR7 ;
input VAR6 ;
wire VAR8 ;
wire VAR1;
or VAR11 (VAR8 , VAR10, VAR4 );
VAR13 VAR2 (VAR1, VAR8, VAR12, VAR3);
buf VAR9 (VAR5 , VAR1 );
endmodule | apache-2.0 |
dries007/Basys3 | FPGA-Z/FPGA-Z.ip_user_files/ip/ClockDivider/ClockDivider_stub.v | 1,241 | module MODULE1(VAR4, VAR2, VAR1, VAR5, VAR3)
;
input VAR4;
output VAR2;
output VAR1;
output VAR5;
output VAR3;
endmodule | mit |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v | 26,458 | module MODULE1 #
(
parameter VAR36 = "none",
parameter integer VAR103 = 1,
parameter integer VAR58 = 32,
parameter integer VAR40 = 32,
parameter integer VAR38 = 0,
parameter integer VAR153 = 1,
parameter integer VAR72 = 1,
parameter integer VAR141 = 1,
parameter integer VAR62 = 1,
parameter integer VAR50 = 1,
parameter... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_read_datapath.v | 25,836 | module MODULE1(
VAR70,
VAR96,
VAR6,
VAR62,
VAR68,
VAR87,
VAR33,
VAR56,
VAR91,
VAR29,
VAR21,
VAR19,
VAR34,
VAR76,
VAR46,
VAR18,
VAR123,
VAR133,
VAR125,
VAR51
);
parameter VAR20 = "";
parameter VAR92 = "";
parameter VAR59 = "";
parameter VAR73 = "";
parameter VAR52 = "";
parameter VAR121 = "";
parameter VAR72 = "";
param... | lgpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1/niosII_system/synthesis/submodules/niosII_system_switch.v | 1,893 | module MODULE1 (
address,
clk,
VAR4,
VAR3,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input VAR4;
input VAR3;
wire VAR2;
wire VAR6;
wire VAR5;
reg [ 31: 0] VAR1;
assign VAR2 = 1;
assign VAR5 = {1 {(address == 0)}} & VAR6;
always @(posedge clk or negedge VAR3)
begin
if (VAR3 == 0)
VAR1 <= 0;
end
el... | gpl-2.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | bloque_prueba_frames.v | 3,535 | module MODULE1
(
input wire [1:0]VAR15,
output reg [3:0] VAR19, VAR2, VAR3, VAR21, VAR11, VAR20,VAR22, VAR18, VAR5, VAR7, VAR14, VAR6,VAR23, VAR17, VAR10, VAR16, VAR24, VAR13,output reg VAR9,output reg [1:0]VAR12,output reg [1:0] VAR4,output reg VAR8,output reg VAR1);
always@*
begin
case(VAR15)
2'h0:
begin
VAR19 = 4'b0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111o/sky130_fd_sc_ms__a2111o.blackbox.v | 1,394 | module MODULE1 (
VAR5 ,
VAR1,
VAR7,
VAR6,
VAR3,
VAR2
);
output VAR5 ;
input VAR1;
input VAR7;
input VAR6;
input VAR3;
input VAR2;
supply1 VAR4;
supply0 VAR10;
supply1 VAR8 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
sam-falvo/kestrel | cores/MGIA/rtl/verilog/MGIA.v | 1,477 | module MODULE1(
input VAR36,
input VAR52,
output VAR18,
output VAR45,
output VAR33,
output [2:0] VAR23,
output [2:0] VAR21,
output [2:1] VAR2,
output [13:1] VAR40,
input [15:0] VAR51,
output VAR53,
output VAR25,
input VAR10
);
wire VAR44;
wire VAR41;
wire VAR55;
wire VAR34;
wire VAR28;
wire [ 5:0] VAR48;
wire [15:0] VA... | mpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/cmp_sram_redhdr.v | 7,674 | module MODULE1 (
VAR13, VAR28, VAR31,
VAR16, VAR27, VAR46,
VAR33, VAR52, VAR43, VAR11, VAR51, VAR6,
VAR3, VAR24, VAR12,
VAR42, VAR35, VAR49
);
input VAR33;
input VAR52;
input VAR43; input VAR11;
input VAR51;
input VAR6;
input VAR3;
input VAR24;
input VAR12; input VAR42;
input [7:0] VAR35; input [1:0] VAR49;
output VAR1... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_4.behavioral.pp.v | 2,375 | module MODULE1( VAR4, VAR2, VAR1, VAR10, VAR5, VAR8, VAR3 );
input VAR5, VAR10, VAR1, VAR4;
inout VAR8, VAR3;
output VAR2;
VAR9 VAR7(.VAR4(VAR4),.VAR2(VAR2),.VAR1(VAR1),.VAR10(VAR10),.VAR5(VAR5),.VAR8(VAR8),.VAR3(VAR3));
VAR9 VAR6(.VAR4(VAR4),.VAR2(VAR2),.VAR1(VAR1),.VAR10(VAR10),.VAR5(VAR5),.VAR8(VAR8),.VAR3(VAR3)); | apache-2.0 |
jameshegarty/rigel | platform/camera2.0/vsrc/top.v | 22,653 | module MODULE1
(
inout [53:0] VAR65,
inout VAR42,
inout VAR289,
inout VAR156,
inout VAR66,
inout VAR274,
inout VAR22,
inout VAR51,
inout VAR90,
inout VAR352,
output VAR305,
inout [2:0] VAR187,
inout [14:0] VAR234,
inout VAR333,
inout VAR126,
inout [31:0] VAR144,
inout [3:0] VAR207,
inout [3:0] VAR317,
inout [3:0] VAR21... | mit |
ZipCPU/wbuart32 | bench/verilog/speechfifo.v | 11,133 | module MODULE1 #(
parameter VAR25 = 31'd868,
localparam VAR5=2203
) (
input wire VAR2,
input wire [30:0] VAR24,
output wire VAR17
);
reg VAR4;
reg VAR3;
reg [1:0] VAR11;
reg [31:0] VAR23;
wire VAR14;
wire VAR20, VAR10;
wire [31:0] VAR16;
wire VAR15, VAR12;
wire VAR1;
reg VAR7;
reg [7:0] VAR13 [0:4095];
reg [30:0] VAR22... | gpl-3.0 |
sh-chris110/chris | FPGA/chris.bak/db/ip/soc_design/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR3,
VAR2,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR3;
input VAR2;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1500009189 : 255;
endmodule | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v | 1,050 | module MODULE1
(input clk,
input [VAR2-1:0] VAR1,
input [VAR2-1:0] VAR3,
output reg [VAR2-1:0] sum);
wire [VAR2-1:0] VAR4;
VAR6 #(.VAR2(VAR2)) VAR5 (.VAR1(VAR1),.VAR3(VAR3),.sum(VAR4));
always @(posedge clk)
sum <= VAR4;
endmodule | gpl-2.0 |
alexforencich/xfcp | lib/eth/rtl/axis_baser_rx_64.v | 20,508 | module MODULE1 #
(
parameter VAR18 = 64,
parameter VAR6 = (VAR18/8),
parameter VAR17 = 2,
parameter VAR14 = 4'h6,
parameter VAR1 = 16'h6666,
parameter VAR13 = 0,
parameter VAR20 = 96,
parameter VAR7 = (VAR13 ? VAR20 : 0) + 1
)
(
input wire clk,
input wire rst,
input wire [VAR18-1:0] VAR8,
input wire [VAR17-1:0] VAR10,
... | mit |
ptracton/wb_soc_template | rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v | 6,797 | module MODULE1 (
VAR16,
VAR2,
VAR18,
VAR12,
VAR6,
VAR14,
VAR17,
VAR3,
VAR15
);
input [VAR4 - 1:0] VAR16;
input VAR2;
input VAR18;
input VAR12;
input VAR6;
input VAR14;
output [VAR4 - 1:0] VAR17;
output VAR3;
output VAR15;
reg VAR13;
wire [2:1] VAR1;
reg VAR19, VAR10, VAR11;
reg VAR5, VAR8, VAR9;
reg VAR7;
reg VAR15;
al... | mit |
scalable-networks/ext | uhd/fpga/usrp1/megacells/mylpm_addsub.v | 4,482 | module MODULE1 (
VAR7,
VAR11,
VAR6,
VAR15,
VAR5);
input VAR7;
input [15:0] VAR11;
input [15:0] VAR6;
input VAR15;
output [15:0] VAR5;
wire [15:0] VAR16;
wire [15:0] VAR5 = VAR16[15:0];
VAR13 VAR3 (
.VAR11 (VAR11),
.VAR7 (VAR7),
.VAR6 (VAR6),
.VAR15 (VAR15),
.VAR5 (VAR16));
VAR3.VAR4 = 16,
VAR3.VAR17 = "VAR10",
VAR3.VA... | gpl-2.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/etc/software/cpu.v | 5,843 | module MODULE1(
VAR8,
VAR109,
VAR39,
VAR81, VAR11,
VAR35, VAR115, VAR65,
VAR20,
VAR113, VAR86, VAR71,
VAR6, VAR102, );
input VAR8;
output VAR109;
output VAR39;
output [15:0] VAR81;
inout [7:0] VAR11;
input VAR35;
input VAR115;
input VAR65;
output VAR20;
output VAR113; output VAR86; output VAR71;
inout VAR6; inout VAR10... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/usbf/usbf_mem_arb.v | 8,424 | module MODULE1( VAR2, VAR23, rst,
VAR1, VAR3, VAR10, VAR5, VAR13,
VAR14, VAR12, VAR18, VAR9, VAR20, VAR7,
VAR16, VAR15, VAR11, VAR8, VAR21, VAR22
);
parameter VAR17 = 14;
input VAR2, VAR23, rst;
output [VAR17:0] VAR1;
input [31:0] VAR3;
output [31:0] VAR10;
output VAR5, VAR13;
input [VAR17:0] VAR14;
output [31:0] VAR12... | gpl-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/fpconv.v | 33,814 | module MODULE1
(
VAR1,
VAR16,
VAR11,
VAR12,
VAR15,
VAR5) ;
input VAR1;
input VAR16;
input VAR11;
input [53:0] VAR12;
input [5:0] VAR15;
output [53:0] VAR5;
tri0 VAR1;
tri1 VAR16;
tri0 VAR11;
reg [1:0] VAR6;
reg [53:0] VAR4;
reg [53:0] VAR17;
reg VAR18;
reg VAR8;
reg VAR7;
wire [6:0] VAR13;
wire VAR3;
wire [31:0] VAR2;
... | apache-2.0 |
chaohu/Daily-Learning | Verilog/lab2/lab2_2/lab2_1_1/lab2_1_1.srcs/sources_1/new/bcdto7segment_dataflow.v | 1,104 | module MODULE1(
input [3:0] VAR1,
output [3:0] VAR3,
output [6:0] VAR2
);
assign VAR3 = VAR1;
assign VAR2[6] = (VAR1[2]&(~VAR1[1])&(~VAR1[0]))|((~VAR1[3])&(~VAR1[2])&(~VAR1[1])&VAR1[0]);
assign VAR2[5] = (VAR1[2]&(~VAR1[1])&VAR1[0])|(VAR1[2]&VAR1[1]&(~VAR1[0]));
assign VAR2[4] = (~VAR1[3])&(~VAR1[2])&VAR1[1]&(~VAR1[0])... | mit |
intelligenttoasters/CPC2.0 | FPGA/rtl/Altera/video720.v | 17,217 | module MODULE1 (
input wire VAR2, input wire rst, output wire VAR3 );
VAR5 VAR4 (
.VAR2 (VAR2), .rst (rst), .VAR3 (VAR3), .VAR1 () );
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4/sky130_fd_sc_hdll__nor4.symbol.v | 1,329 | module MODULE1 (
input VAR6,
input VAR2,
input VAR7,
input VAR5,
output VAR3
);
supply1 VAR4;
supply0 VAR8;
supply1 VAR9 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
lab1-ufba/Genius | rom_botao.v | 6,431 | module MODULE1 (
address,
VAR42,
VAR25);
input [6:0] address;
input VAR42;
output [20:0] VAR25;
tri1 VAR42;
wire [20:0] VAR20;
wire [20:0] VAR25 = VAR20[20:0];
VAR38 VAR10 (
.VAR30 (address),
.VAR3 (VAR42),
.VAR4 (VAR20),
.VAR46 (1'b0),
.VAR51 (1'b0),
.VAR44 (1'b1),
.VAR45 (1'b0),
.VAR14 (1'b0),
.VAR21 (1'b1),
.VAR2 (1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2a/sky130_fd_sc_ms__o2bb2a.symbol.v | 1,386 | module MODULE1 (
input VAR2,
input VAR9,
input VAR6 ,
input VAR3 ,
output VAR8
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
lvd2/zxevo | fpga/base_trdemu/trunk/vg93/vg93.v | 6,647 | module MODULE1(
input VAR5, input VAR52,
input VAR30,
output VAR10,
output reg VAR42,
input [7:0] din, output VAR46,VAR2, input VAR3,
output reg VAR47,
output wire VAR11,
output wire VAR29,
output reg [1:0] VAR44, output reg VAR8,
output reg VAR51,
input VAR37, input VAR21,VAR39,VAR40,
input VAR43,
input VAR4,
input VA... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/Altera/audio_clock.v | 17,232 | module MODULE1 (
input wire VAR4, input wire rst, output wire VAR2 );
VAR3 VAR1 (
.VAR4 (VAR4), .rst (rst), .VAR2 (VAR2), .VAR5 () );
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrbp/sky130_fd_sc_hd__dfrbp_1.v | 2,441 | module MODULE2 (
VAR10 ,
VAR4 ,
VAR2 ,
VAR1 ,
VAR3,
VAR7 ,
VAR6 ,
VAR5 ,
VAR11
);
output VAR10 ;
output VAR4 ;
input VAR2 ;
input VAR1 ;
input VAR3;
input VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR11 ;
VAR8 VAR9 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
... | apache-2.0 |
merckhung/zet | cores/hpdmc_sdr16/rtl/hpdmc_sdrio.v | 1,244 | module MODULE1(
input VAR9,
input VAR3,
input VAR4,
input [ 1:0] VAR7,
input [15:0] dout,
output reg [15:0] VAR1,
output [ 1:0] VAR8,
inout [15:0] VAR2
);
wire [15:0] VAR6;
assign VAR2 = VAR3 ? VAR6 : 16'VAR5;
assign VAR8 = VAR7;
assign VAR6 = dout;
always @(posedge VAR9) VAR1 <= VAR2;
endmodule | gpl-3.0 |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/hls_cores/vector_add/vectoradd_prj/solution1/syn/verilog/vectoradd.v | 16,418 | module MODULE1 (
VAR51,
VAR44,
VAR47,
VAR16,
VAR42,
VAR9,
VAR41,
VAR80,
VAR27,
VAR79,
VAR23,
VAR34,
VAR82,
VAR4,
VAR6,
VAR48,
VAR68,
VAR58,
VAR45,
VAR50,
VAR26,
VAR5,
VAR60,
VAR19,
VAR21,
VAR72,
VAR8,
VAR57,
VAR22
);
parameter VAR46 = 1'b1;
parameter VAR49 = 1'b0;
parameter VAR40 = 3'b000;
parameter VAR59 = 3'b1;
param... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbp/sky130_fd_sc_lp__dlrbp.pp.blackbox.v | 1,440 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR6,
VAR1 ,
VAR3 ,
VAR8 ,
VAR7 ,
VAR9 ,
VAR4
);
output VAR5 ;
output VAR2 ;
input VAR6;
input VAR1 ;
input VAR3 ;
input VAR8 ;
input VAR7 ;
input VAR9 ;
input VAR4 ;
endmodule | apache-2.0 |
zKarp/Karpentium-Processor | src/verilog/memory_data_register.v | 1,033 | module MODULE1 (clk,VAR6,VAR1,VAR3,enable,VAR4);
input clk,VAR4,enable;
input [1:0] VAR3;
inout [15:0] VAR1;
inout [15:0] VAR6;
reg [15:0] VAR2;
always @(posedge(clk))
begin
if(VAR4) begin VAR2 <= 16'd0; end
else
case({enable,VAR3})
3'b100 : begin
VAR2 <= VAR1;
end
3'b101 : begin
VAR2 <= VAR6;
end
default: begin
VAR2 <... | gpl-2.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_1/hdl/verilog/feedforward_ddiv_64ns_64ns_64_31.v | 1,927 | module MODULE1
VAR7 = 2,
VAR23 = 31,
VAR19 = 64,
VAR22 = 64,
VAR11 = 64
)(
input wire clk,
input wire reset,
input wire VAR18,
input wire [VAR19-1:0] VAR15,
input wire [VAR22-1:0] VAR1,
output wire [VAR11-1:0] dout
);
wire VAR6;
wire VAR8;
wire VAR14;
wire [63:0] VAR4;
wire VAR24;
wire [63:0] VAR16;
wire VAR13;
wire [6... | gpl-3.0 |
briburrell/amica | device/bitstream/bitstream.srcs/sources_1/imports/bitstream/salsaengine.v | 20,907 | module MODULE1 (VAR73, reset, din, dout, VAR43, VAR38, VAR13, VAR30 );
input VAR73;
input reset; input VAR43;
input VAR38; output VAR13;
output reg VAR30 = 1'b0;
parameter VAR40 = 8; input [VAR40-1:0] din;
output [VAR40-1:0] dout;
parameter VAR53 = 11;
parameter VAR17 = 8;
function integer VAR47; input integer VAR50;
b... | gpl-3.0 |
csturton/wirepatch | system/hardware/cores/uart16550/rtl/verilog/uart_tfifo.v | 8,939 | module MODULE1 (clk,
VAR11, VAR8, VAR6,
VAR7, VAR26, VAR16,
VAR5,
VAR20,
VAR19
);
parameter VAR4 = VAR21;
parameter VAR23 = VAR10;
parameter VAR3 = VAR22;
parameter VAR9 = VAR17;
input clk;
input VAR11;
input VAR7;
input VAR26;
input [VAR4-1:0] VAR8;
input VAR20;
input VAR19;
output [VAR4-1:0] VAR6;
output VAR16;
outpu... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/AXI4MasterInterface.v | 8,969 | module MODULE1
(
parameter VAR83 = 32 ,
parameter VAR70 = 32 ,
parameter VAR45 = 16 ,
parameter VAR47 = 16
)
(
VAR51 ,
VAR54 ,
VAR85 ,
VAR10 ,
VAR71 ,
VAR34 ,
VAR41 ,
VAR93 ,
VAR1 ,
VAR52 ,
VAR60 ,
VAR76 ,
VAR97 ,
VAR29 ,
VAR6 ,
VAR7 ,
VAR68 ,
VAR96 ,
VAR75 ,
VAR65 ,
VAR56 ,
VAR84 ,
VAR95 ,
VAR26 ,
VAR78 ,
VAR66 ,
VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor2/sky130_fd_sc_ls__xor2.behavioral.v | 1,381 | module MODULE1 (
VAR10,
VAR1,
VAR8
);
output VAR10;
input VAR1;
input VAR8;
supply1 VAR6;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR5 ;
wire VAR7;
xor VAR9 (VAR7, VAR8, VAR1 );
buf VAR3 (VAR10 , VAR7 );
endmodule | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_AO_LVT_FF_210930.v | 231,277 | module MODULE1 (VAR9, VAR8, VAR11, VAR1, VAR10);
output VAR9;
input VAR8, VAR11, VAR1, VAR10;
wire VAR5, VAR4, VAR3;
wire VAR6, VAR7, VAR2;
not (VAR6, VAR10);
not (VAR3, VAR1);
not (VAR4, VAR11);
and (VAR7, VAR4, VAR3);
not (VAR5, VAR8);
and (VAR2, VAR5, VAR3);
or (VAR9, VAR2, VAR7, VAR6); | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_chip/bsg_rocket/bsg_rocket_core_fsb.v | 5,196 | module MODULE1
import VAR73::VAR57;
, parameter VAR80 ="VAR40"
, parameter VAR2 = 16
, parameter VAR90=(VAR57))
(input VAR15
, input VAR74
, input VAR129
, input [1:0] VAR66
, input [1:0][VAR90-1:0] VAR14
, output [1:0] VAR112
, output [1:0] VAR47
, output [1:0] [VAR90-1:0] VAR94
, input [1:0] VAR81
);
wire VAR11, VAR1... | bsd-3-clause |
kyzhai/NUNY | src/hardware/ninja3_bb.v | 4,986 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/7GFLOPs/syn/verilog/convolve_kernel_fcud.v | 1,881 | module MODULE1
VAR11 = 26,
VAR15 = 5,
VAR10 = 32,
VAR9 = 32,
VAR16 = 32
)(
input wire clk,
input wire reset,
input wire VAR3,
input wire [VAR10-1:0] VAR20,
input wire [VAR9-1:0] VAR2,
output wire [VAR16-1:0] dout
);
wire VAR22;
wire VAR13;
wire VAR7;
wire [31:0] VAR26;
wire VAR6;
wire [31:0] VAR21;
wire VAR18;
wire [31... | mit |
ptracton/Picoblaze | library/timers/timer.v | 1,297 | module MODULE1 (
VAR4,
clk, VAR6, VAR1, VAR2
) ;
input clk;
input [31:0] VAR6;
input VAR1;
input VAR2;
output VAR4;
reg [31:0] VAR3 = 32'h00000000;
reg VAR4 = 1'b0;
reg interrupt = 1'b0;
assign VAR5 = (VAR3 >= VAR6);
always @(posedge clk)
if (VAR1 && !VAR5) begin
VAR3 <= VAR3 + 1;
end else begin
VAR3 <= 32'h00000000;
e... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux4/sky130_fd_sc_lp__mux4_2.v | 2,444 | module MODULE2 (
VAR1 ,
VAR9 ,
VAR6 ,
VAR3 ,
VAR11 ,
VAR12 ,
VAR5 ,
VAR13,
VAR8,
VAR4 ,
VAR10
);
output VAR1 ;
input VAR9 ;
input VAR6 ;
input VAR3 ;
input VAR11 ;
input VAR12 ;
input VAR5 ;
input VAR13;
input VAR8;
input VAR4 ;
input VAR10 ;
VAR7 VAR2 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR11(VAR11)... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/rxr_engine_ultrascale.v | 21,070 | module MODULE1
parameter VAR107=10
)
(
input VAR3,
input VAR9,
input VAR83,
input VAR135,
input [VAR53-1:0] VAR113,
input [(VAR53/32)-1:0] VAR103,
input [VAR92-1:0] VAR80,
output VAR115,
output [VAR53-1:0] VAR81,
output VAR112,
output [(VAR53/32)-1:0] VAR64,
output VAR8,
output [VAR90(VAR53/32)-1:0] VAR61,
output VAR67... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.behavioral.v | 1,027 | module MODULE1( );
VAR2 VAR1();
VAR2 VAR3(); | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2_ctrl_module/ddr2_interface2um.v | 6,044 | module MODULE1(
VAR38, VAR58, VAR14, VAR48, VAR66, VAR22, VAR40, VAR5, VAR27, VAR33, VAR10, VAR28, VAR13, VAR37, VAR35, VAR34,
VAR16,
VAR68,
VAR12,
VAR41,
VAR30,
VAR4,
VAR59,
VAR65,
VAR31,
VAR23,
VAR8,
VAR26
);
input VAR58; input VAR38; inout VAR14; inout VAR48; output [15:0] VAR66; output [2:0] VAR22;
output VAR40; ou... | apache-2.0 |
HackLinux/CPU-Design | cpu/DCACHE.v | 6,369 | module MODULE1(VAR12, address, VAR24, read, write, VAR1, VAR7, VAR4, VAR19, VAR16, VAR9, VAR8, VAR18);
input [31:0] address;
inout [31:0] VAR24, VAR4;
input read, write;
input [63:0] VAR9;
input VAR12;
output [31:0] VAR7;
output VAR19, VAR16;
output [63:0] VAR8;
output VAR18;
output VAR1;
reg [31:0] MODULE1 [14'h3FFF:0... | bsd-2-clause |
MIPSfpga/schoolMIPS | board/de1_soc/de1_soc.v | 6,310 | module MODULE1(
output VAR41,
output VAR71,
input VAR35,
output VAR88,
input VAR106,
inout VAR48,
inout VAR43,
output VAR99,
inout VAR32,
output VAR39,
input VAR47,
input VAR55,
input VAR15,
input VAR117,
output [12:0] VAR50,
output [1:0] VAR94,
output VAR31,
output VAR56,
output VAR108,
output VAR19,
inout [15:0] VAR8... | mit |
Raamakrishnan/MyProc | MyProc2/DMem.v | 1,226 | module MODULE1(
input wire VAR4,
input wire [VAR2 - 1:0] VAR12,
inout wire [VAR2 - 1:0] VAR14,
input wire wr,
input wire rd,
output reg VAR10,
input wire [1:0] VAR8 VAR11 VAR3
,input wire VAR5
);
reg [7:0] VAR13 [0:VAR2 - 1];
reg [VAR2 - 1:0] VAR7;
assign VAR14 = (rd == 1)? VAR7 : 32'VAR9;
always @(posedge wr) begin
ca... | mit |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/alu_y_pipelined.v | 7,893 | module MODULE1(
input [31:0] VAR67,
input [31:0] VAR34,
input [31:0] VAR65,
input [1:0] VAR85,
input VAR6,
input VAR19,
input [7:0] VAR93,
input reset,
input VAR51,
output [31:0] VAR60,
output VAR25
);
wire [1:0] VAR64,VAR30,VAR36,VAR61,VAR74,VAR23,VAR71;
wire [32:0] VAR87,VAR89;
wire [31:0] VAR41,VAR70,VAR90,VAR94,VAR... | apache-2.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/nios_system_timer_0.v | 6,967 | module MODULE1 (
address,
VAR13,
clk,
VAR33,
VAR14,
VAR23,
irq,
VAR25
)
;
output irq;
output [ 15: 0] VAR25;
input [ 2: 0] address;
input VAR13;
input clk;
input VAR33;
input VAR14;
input [ 15: 0] VAR23;
wire VAR26;
wire VAR31;
wire VAR9;
reg [ 3: 0] VAR21;
wire VAR1;
reg VAR20;
wire VAR11;
wire [ 31: 0] VAR18;
reg [ 3... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_4.behavioral.pp.v | 1,246 | module MODULE1( VAR3, VAR7, VAR5, VAR6, VAR1 );
input VAR3, VAR7;
inout VAR6, VAR1;
output VAR5;
VAR2 VAR8(.VAR3(VAR3),.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR1(VAR1));
VAR2 VAR4(.VAR3(VAR3),.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ai/sky130_fd_sc_hd__o21ai.behavioral.pp.v | 2,010 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR12 ,
VAR10 ,
VAR15,
VAR6,
VAR14 ,
VAR2
);
output VAR7 ;
input VAR11 ;
input VAR12 ;
input VAR10 ;
input VAR15;
input VAR6;
input VAR14 ;
input VAR2 ;
wire VAR8 ;
wire VAR9 ;
wire VAR1;
or VAR3 (VAR8 , VAR12, VAR11 );
nand VAR16 (VAR9 , VAR10, VAR8 );
VAR5 VAR13 (VAR1, VAR9, VAR15, VAR... | apache-2.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ip/fmrv32im_artya7_xlconstant_0_0/synth/fmrv32im_artya7_xlconstant_0_0.v | 2,988 | module MODULE1 (
dout
);
output wire [0 : 0] dout;
VAR3 #(
.VAR1(1),
.VAR2('VAR4)
) VAR5 (
.dout(dout)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4/sky130_fd_sc_hs__nor4.behavioral.v | 1,762 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR11,
VAR13
);
output VAR8 ;
input VAR9 ;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR11;
input VAR13;
wire VAR1 ;
wire VAR10;
nor VAR12 (VAR1 , VAR9, VAR7, VAR3, VAR4 );
VAR6 VAR5 (VAR10, VAR1, VAR11, VAR13);
buf VAR2 (VAR8 , VAR10 );
endmodule | apache-2.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite.v | 20,912 | module MODULE1 #(
parameter [5:0]VAR6 = 17,
parameter [2:0]VAR246 = 0,
parameter [0:0]VAR257 = 1,
parameter [0:0]VAR207 = 0,
parameter [0:0]VAR70 = 0,
parameter [0:0]VAR136 = 0,
parameter [0:0]VAR85 = 0,
parameter [0:0]VAR251 = 0,
parameter [0:0]VAR133 = 0,
parameter [0:0]VAR235 = 0,
parameter [0:0]VAR233 = 0,
paramete... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_pmod_tft/rtl/nh_lcd_command.v | 2,396 | module MODULE1 (
input rst,
input clk,
output [31:0] VAR6,
input VAR9,
input VAR13,
input [7:0] VAR2,
output reg [7:0] VAR12,
input VAR10,
input VAR16,
output reg VAR5,
output VAR17,
output reg VAR4,
output reg VAR15,
output reg [7:0] VAR3,
input [7:0] VAR7,
output reg VAR11
);
localparam VAR14 = 4'h0;
localparam VAR8 ... | mit |
camacazio/icestick_JSTK2_ORGB | source/PmodOLED_Source/OledInit.v | 7,655 | module MODULE1(
VAR8,
VAR20,
VAR42,
VAR48,
VAR45,
VAR10,
VAR25,
VAR7,
VAR52,
VAR31,
VAR35
);
input VAR8;
input VAR20;
input VAR42;
output VAR48;
output VAR45;
output VAR10;
output VAR25;
output VAR7;
output VAR52;
output VAR31;
output VAR35;
wire VAR45, VAR25, VAR31, VAR35, VAR10;
wire VAR48, VAR7, VAR52;
reg [103:0] V... | gpl-3.0 |
ILoveSpeccy/Aeon-Lite | cores/bashkiria-2m/src/b2m_de1.v | 6,910 | module MODULE1(
input VAR87,
inout [15:0] VAR77, output [17:0] VAR43, output VAR94, output VAR18, output VAR51, output VAR21, output VAR132,
output VAR2,
output VAR25,
output VAR34,
output VAR28,
output [3:0] VAR42,
output [3:0] VAR104,
output [3:0] VAR59,
input VAR119,
input VAR133,
input VAR73, output VAR22, output V... | gpl-3.0 |
mbus/mbus | releases/mbus_example-v1.2/verilog/mbus_wire_ctrl.v | 2,027 | module MODULE1(
input VAR4,
input VAR5,
input VAR7,
input VAR2,
input VAR11,
input VAR6,
input VAR9,
output reg VAR3,
output reg VAR8
);
always @ *
begin
if (~VAR4)
VAR8 <= VAR10 1'b1;
end
else if (VAR6==VAR1)
VAR8 <= VAR10 VAR11;
else
VAR8 <= VAR10 VAR7;
if (~VAR4)
VAR3 <= VAR10 1'b1;
else if (VAR9)
VAR3 <= VAR10 0;
e... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp.functional.pp.v | 2,384 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR6 ,
VAR4 ,
VAR8 ,
VAR10 ,
VAR7,
VAR22 ,
VAR14 ,
VAR3 ,
VAR12
);
output VAR5 ;
output VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR8 ;
input VAR10 ;
input VAR7;
input VAR22 ;
input VAR14 ;
input VAR3 ;
input VAR12 ;
wire VAR15 ;
wire VAR21 ;
wire VAR19;
not VAR18 (VAR21 , VAR7 );
VAR20 VAR... | apache-2.0 |
spacemonkeydelivers/mor1kx | rtl/verilog/mor1kx_wb_mux_cappuccino.v | 1,473 | module MODULE1
parameter VAR8 = 32
)
(
input clk,
input rst,
input [VAR8-1:0] VAR5,
input [VAR8-1:0] VAR10,
input [VAR8-1:0] VAR6,
input [VAR8-1:0] VAR3,
output [VAR8-1:0] VAR2,
input VAR7,
input VAR1,
input VAR4
);
reg [VAR8-1:0] VAR11;
reg VAR9;
assign VAR2 = VAR9 ? VAR6 : VAR11;
always @(posedge clk)
if (VAR4)
VAR11... | mpl-2.0 |
lab11/M-ulator | platforms/HT_m3/hardware/ICE/hdl/ice_bus_controller.v | 3,634 | module MODULE1(clk, rst, VAR24, VAR6, VAR12, VAR36, VAR15, VAR21, VAR7, VAR35, VAR31, VAR3, VAR22, VAR29, VAR34, VAR1, VAR4, VAR18);
parameter VAR5=2;
input clk;
input rst;
input [7:0] VAR24;
input VAR6;
output [7:0] VAR12;
output VAR36;
input VAR15;
output reg VAR21;
output reg [7:0] VAR7;
output [7:0] VAR35;
output r... | apache-2.0 |
defano/digital-design | lsuc/rtl/uart_ctrl.v | 5,065 | module MODULE1 (
clk,
reset,
VAR26,
VAR20,
addr,
VAR21,
req,
VAR11,
VAR19,
VAR10,
VAR8);
input clk;
input reset;
output VAR26; input VAR20;
input [7:0] addr;
input VAR21;
input req;
inout VAR11;
input [7:0] VAR19;
output [7:0] VAR10;
output VAR8;
reg VAR8;
reg [7:0] VAR10;
wire VAR2;
wire VAR13;
reg VAR4;
reg [7:0] VAR... | mit |
asicguy/gplgpu | hdl/de/ded_cactrl_rd.v | 14,846 | module MODULE1
(
input VAR22,
input VAR59,
input VAR51,
input VAR5,
input VAR27,
input VAR72,
input VAR76,
input VAR30,
input [9:0] din,
input [8:0] VAR67,
input [4:0] VAR12,
input [6:0] VAR8,
input [1:0] VAR13,
input [1:0] VAR58,
input [1:0] VAR4,
input [1:0] VAR21,
input VAR6,
input VAR26,
input VAR71,
input [2:0] VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2.functional.pp.v | 1,867 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR1,
VAR8,
VAR3 ,
VAR2
);
output VAR7 ;
input VAR5 ;
input VAR1;
input VAR8;
input VAR3 ;
input VAR2 ;
wire VAR12 ;
wire VAR11;
not VAR6 (VAR12 , VAR5 );
VAR10 VAR4 (VAR11, VAR12, VAR1, VAR8);
buf VAR9 (VAR7 , VAR11 );
endmodule | apache-2.0 |
alan4186/Hardware-CNN | Hardware/v/softmax/matrix_multiply.v | 2,063 | module MODULE1( input VAR23,
input reset,
input [(VAR18*VAR4)-1:0] VAR19,
input [(VAR18*VAR4*VAR5)-1:0] VAR28,
output [(VAR18*2*VAR5)-1:0] VAR31
);
wire [VAR13:0] VAR3 [VAR4];
wire [VAR29:0] VAR22 [VAR5];
wire [VAR29:0] VAR15 [VAR4][VAR5]; wire [VAR29:0] VAR7 [VAR4][VAR5];
wire [VAR29:0] VAR32 [VAR17][VAR5];
genvar VAR... | mit |
cr88192/bgbtech_bjx1core | bjx1core32/FpuFp64_Rcp.v | 3,802 | module MODULE1(
clk,
VAR2,
VAR6
);
input clk;
input[63:0] VAR2;
output[63:0] VAR6;
reg[12:0] VAR10;
reg[12:0] VAR1;
reg[52:0] VAR3;
reg[52:0] VAR9;
reg[52:0] VAR4;
reg[52:0] VAR8;
reg[63:0] VAR5;
assign VAR6 = VAR5;
reg[15:0] VAR7[255:0];
begin
begin
end
begin | mit |
subailong/miaow | src/verilog/rtl/alu/alu.v | 13,942 | module MODULE1(
VAR194,
VAR197,
VAR99,
VAR146,
VAR157,
VAR33,
VAR97,
VAR181,
VAR59,
VAR28,
VAR11,
VAR96,
VAR114,
VAR27,
VAR31,
VAR134,
VAR40,
VAR95,
VAR88,
VAR119,
VAR129,
VAR23,
VAR161,
VAR81,
VAR83,
VAR142,
VAR164,
VAR152,
VAR43,
VAR184,
VAR22,
VAR74,
VAR65,
VAR127,
VAR139,
VAR87,
VAR102,
VAR20,
VAR192,
VAR190,
VAR11... | bsd-3-clause |
KestrelComputer/kestrel | cores/common/queue.v | 1,167 | module MODULE1(
input VAR18,
input VAR1,
input [VAR17:0] VAR13,
input VAR5,
input VAR21,
input VAR4,
output [VAR17:0] VAR16,
output VAR20,
output VAR12,
output [VAR6:0] VAR14,
output [VAR6:0] VAR2,
output [VAR6+1:0] VAR10
);
parameter VAR11 = 4;
parameter VAR8 = 8;
parameter VAR17 = VAR8 - 1;
parameter VAR6 = VAR11 - 1... | mpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v | 49,596 | module MODULE1 #
( parameter
VAR60 = 80,
VAR28 = 32,
VAR97 = 2,
VAR112 = 40,
VAR123 = 5,
VAR2 = 8,
VAR122 = 1,
VAR42 = 0,
VAR94 = 0,
VAR79 = 0,
VAR44 = 0,
VAR56 = 8,
VAR88 = 1,
VAR118 = 1,
VAR36 = 1,
VAR96 = 1,
VAR64 = 1,
VAR35 = 1,
VAR14 = 1,
VAR23 = 1,
VAR100 = 1,
VAR70 = 1,
VAR78 = 8,
VAR16 = 8,
VAR46 = 1,
VAR37 = 8... | gpl-3.0 |
xuwenyihust/MapReduce_NoC | RTL/reducer.v | 4,157 | module MODULE1(clk, rst, VAR2, VAR5, VAR22);
parameter VAR15 = 32;
parameter VAR8 = 128;
parameter VAR19 = 64;
parameter VAR7 = 4'b0000;
parameter VAR13 = 4'b0001;
parameter VAR16 = 4'b0010;
input clk;
input rst;
input VAR2;
input [VAR15-1:0] VAR5; output reg [31:0] VAR22;
reg [3:0] VAR3;
reg VAR17;
reg VAR21;
always@(... | mit |
8l/kestrel | 2/nexys2/uxa/ps2io/M_uxa_ps2_busctl.v | 2,306 | module MODULE1(
input VAR15,
input VAR8,
input VAR4,
input VAR6,
input VAR10,
input VAR11,
output VAR2,
output VAR5,
output VAR12,
output VAR9
);
reg VAR1;
assign VAR2 = VAR1;
reg VAR3;
reg VAR7;
assign VAR12 = VAR3;
assign VAR9 = VAR7;
reg VAR14;
wire VAR13 = (~VAR8 & VAR6 & VAR4);
assign VAR5 = VAR14;
always @(posedg... | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii/altera_reset_controller.v | 12,329 | module MODULE1
parameter VAR36 = 6,
parameter VAR63 = 0,
parameter VAR49 = 0,
parameter VAR22 = 0,
parameter VAR35 = 0,
parameter VAR52 = 0,
parameter VAR55 = 0,
parameter VAR77 = 0,
parameter VAR16 = 0,
parameter VAR70 = 0,
parameter VAR71 = 0,
parameter VAR58 = 0,
parameter VAR30 = 0,
parameter VAR38 = 0,
parameter V... | apache-2.0 |
mfkiwl/parallella-platform | hdl/pulse2toggle.v | 1,402 | module MODULE1(
out,
clk, in, reset
);
input clk;
input in;
output out;
input reset;
reg out;
wire VAR1;
assign VAR1 = in ? ~out :
out;
always @ (posedge clk or posedge reset)
if(reset)
out <= 1'b0;
else
out <= VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfsbp/sky130_fd_sc_ls__dfsbp_2.v | 2,377 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR6 ,
VAR8 ,
VAR4,
VAR2 ,
VAR5 ,
VAR11 ,
VAR7
);
output VAR9 ;
output VAR1 ;
input VAR6 ;
input VAR8 ;
input VAR4;
input VAR2 ;
input VAR5 ;
input VAR11 ;
input VAR7 ;
VAR3 VAR10 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR11(VAR11),
.... | apache-2.0 |
LordRafa/Sobel-FPGA | Project_With_Cache/ip/SIS/Sobel.v | 6,380 | module MODULE1 (
input clk,
input rst,
output [31:0] VAR39,
output VAR48,
input wire [8:0] VAR15,
output wire[31:0] VAR45,
input VAR12,
input VAR14,
output wire[3:0] VAR29,
output wire VAR25,
input wire[31:0] VAR34,
output wire[5:0] VAR17,
input VAR3,
output VAR2,
input [31:0] VAR36
);
parameter VAR33=32;
parameter VAR... | gpl-2.0 |
sh-chris110/chris | FPGA/chris/Qsys/soc_design/synthesis/submodules/soc_design_SDRAM.v | 23,745 | module MODULE2 (
clk,
rd,
VAR67,
wr,
VAR52,
VAR74,
VAR57,
VAR3,
VAR30,
VAR21
)
;
output VAR74;
output VAR57;
output VAR3;
output VAR30;
output [ 43: 0] VAR21;
input clk;
input rd;
input VAR67;
input wr;
input [ 43: 0] VAR52;
wire VAR74;
wire VAR57;
wire VAR3;
reg [ 1: 0] VAR18;
reg [ 43: 0] VAR10;
reg [ 43: 0] VAR80;
w... | gpl-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_0_ecc_buf.v | 6,293 | module MODULE1
parameter VAR4 = 100,
parameter VAR38 = 64,
parameter VAR26 = 4,
parameter VAR37 = 1,
parameter VAR35 = 64,
parameter VAR39 = 4
)
(
VAR41,
clk, rst, VAR21, VAR36, VAR7,
VAR29, VAR2, VAR43
);
input clk;
input rst;
input [VAR26-1:0] VAR21;
input [VAR37-1:0] VAR36;
wire [4:0] VAR25;
input [VAR26-1:0] VAR7;
... | apache-2.0 |
AbhishekShah212/School_Projects | ELEN232/pset5/ALU.v | 1,350 | module MODULE1(
input [2:0] VAR4,
input [3:0] VAR2,
input [3:0] VAR1,
output reg [3:0] VAR3,
output reg VAR5
);
always @ (VAR2 or VAR1 or VAR4)
begin
VAR5 = 0;
case (VAR4)
3'b000: begin
VAR3 = ~VAR2;
end
3'b001: begin
VAR3 = ~(VAR2&VAR1);
end
3'b010: begin
VAR3 = ~(VAR2|VAR1);
end
3'b011: begin
VAR3 = VAR2 ^ VAR1;
end
... | mit |
anderson1008/NOCulator | hring/hw/bless_mc/paraPortAlloc_st2.v | 5,515 | module MODULE1 # (parameter VAR17 = 2'd3) (
VAR10,
VAR14,
VAR1,
VAR22,
VAR16,
VAR9,
VAR8,
VAR20,
VAR12
);
input [VAR4-2:0] VAR10, VAR14, VAR1, VAR22, VAR16, VAR9, VAR8, VAR20;
output [VAR4-2:0] VAR12;
wire [VAR4-2:0] VAR19;
wire [VAR4-2:0] VAR3, VAR13;
generate
if (VAR17 == 2'd3) begin : VAR11
assign VAR19 = ~(VAR10 | ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3b/sky130_fd_sc_hs__or3b_1.v | 2,082 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR8 ,
VAR7 ,
VAR4,
VAR3
);
output VAR1 ;
input VAR5 ;
input VAR8 ;
input VAR7 ;
input VAR4;
input VAR3;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR1 ,
VAR5 ,
VAR8 ,
VAR7
);
output VAR1 ;
input VAR5 ;
input VAR... | apache-2.0 |
jakubfi/mera400f | src/msg_rx.v | 2,321 | module MODULE1(
input VAR36,
input [0:7] VAR9,
input VAR30,
output reg ready,
output reg VAR40,
output reg VAR21,
output reg in,
output reg VAR34,
output reg VAR15,
output reg VAR24,
output reg en,
output reg VAR2,
output reg VAR35,
output reg VAR28,
output reg VAR10,
output reg [0:7] VAR6,
output reg [0:15] VAR33,
out... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/conb/sky130_fd_sc_ms__conb.pp.symbol.v | 1,268 | module MODULE1 (
output VAR1 ,
output VAR6 ,
input VAR3 ,
input VAR5,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/I2C_Controller.v | 3,885 | module MODULE1 (
VAR12,
VAR8, VAR10, VAR11, VAR1, VAR16, VAR6, VAR2, VAR13,
VAR5,
VAR7
);
input VAR12;
input [23:0]VAR11;
input VAR1;
input VAR13;
input VAR6;
inout VAR10;
output VAR8;
output VAR16;
output VAR2;
output [5:0] VAR5;
output VAR7;
reg VAR7;
reg VAR3;
reg VAR16;
reg [23:0]VAR15;
reg [5:0]VAR5;
wire VAR8=VAR... | apache-2.0 |
myriadrf/A2300 | hdl/wca/WcaDducController.v | 4,448 | module MODULE1(
input VAR27,
input reset,
input enable,
input wire VAR21,
output wire [7:0] VAR10, output wire [12:0] VAR9, output wire VAR4,
output wire [3:0] VAR19,
output wire VAR15, output wire VAR11, output wire [31:0] VAR13,
input wire [11:0] VAR2, inout wire [7:0] VAR28 );
parameter VAR6 = 0;
parameter VAR12 = 1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.v | 2,480 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR11,
VAR4 ,
VAR7 ,
VAR3 ,
VAR10 ,
VAR9 ,
VAR1
);
output VAR5 ;
output VAR8 ;
input VAR11;
input VAR4 ;
input VAR7 ;
input VAR3 ;
input VAR10 ;
input VAR9 ;
input VAR1 ;
VAR2 VAR6 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR9(VAR9)... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_qpll_drp.v | 15,334 | module MODULE1 #
(
parameter VAR62 = "VAR5", parameter VAR29 = 0, parameter VAR55 = 3'd4
)
(
input VAR58,
input VAR57,
input VAR13,
input VAR32,
input VAR42,
input [15:0] VAR19,
input VAR52,
output [ 7:0] VAR12,
output VAR7,
output [15:0] VAR18,
output VAR47,
output VAR21,
output [ 5:0] VAR2,
output [ 6:0] VAR46
);
reg... | lgpl-3.0 |
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