repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
m-labs/milkymist | cores/fmlbrg/rtl/fmlbrg_tagmem.v | 1,371 | module MODULE1 #(
parameter VAR3 = 2,
parameter VAR8 = 2
) (
input VAR2,
input [VAR3-1:0] VAR11,
input VAR4,
input [VAR8-1:0] VAR10,
output [VAR8-1:0] do,
input [VAR3-1:0] VAR5,
output [VAR8-1:0] VAR6
);
reg [VAR8-1:0] VAR7[0:(1 << VAR3)-1];
reg [VAR3-1:0] VAR1;
reg [VAR3-1:0] VAR12;
always @(posedge VAR2) begin
VAR1 <... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decap/sky130_fd_sc_lp__decap.symbol.v | 1,211 | module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
plindstroem/oh | memory/hdl/fifo_full_block.v | 3,413 | module MODULE1 (
VAR8, VAR13, VAR3, VAR5,
reset, VAR12, VAR2, VAR1
);
parameter VAR7 = 2;
input reset;
input VAR12;
input [VAR7:0] VAR2; input VAR1;
output VAR8;
output VAR13;
output [VAR7-1:0] VAR3;
output [VAR7:0] VAR5;
reg [VAR7:0] VAR5;
reg [VAR7:0] VAR10;
reg VAR8;
wire VAR4;
wire [VAR7:0] VAR9;
wire [VAR7:0] VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtn/sky130_fd_sc_hs__dlxtn.symbol.v | 1,305 | module MODULE1 (
input VAR4 ,
output VAR3 ,
input VAR1
);
supply1 VAR5;
supply0 VAR2;
endmodule | apache-2.0 |
iAklis/teoca | EXPR4_DIGITAL/MAIN.v | 4,700 | module MODULE2(VAR27, VAR24, VAR12, clk, VAR8, VAR30, VAR15, VAR1
);
parameter VAR16 = 5;
parameter VAR6 = 8;
input clk, VAR8;
input [VAR16-1:0] VAR27;
input VAR24, VAR30;
input [1:0] VAR12;
output reg [7:0] VAR1;
output wire [3:0] VAR15;
reg [31:0] VAR7;
wire [31:0] VAR11, VAR5, VAR18;
wire [63:0] VAR29;
assign VAR18 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfrtp/sky130_fd_sc_hdll__dfrtp.behavioral.v | 2,220 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR14 ,
VAR17
);
output VAR1 ;
input VAR10 ;
input VAR14 ;
input VAR17;
supply1 VAR4;
supply0 VAR18;
supply1 VAR15 ;
supply0 VAR9 ;
wire VAR3 ;
wire VAR7 ;
reg VAR8 ;
wire VAR20 ;
wire VAR6;
wire VAR19 ;
wire VAR2 ;
wire VAR21 ;
wire VAR5 ;
not VAR12 (VAR7 , VAR6 );
VAR13 VAR16 (VAR3 , V... | apache-2.0 |
vvk/sysrek | rgb2hsv/src/hdmi_main.v | 9,993 | module MODULE1
(
input wire VAR98, input wire VAR92,
input wire [3:0] VAR115,
input wire [3:0] VAR139,
output wire [3:0] VAR35,
output wire [3:0] VAR10,
output wire [7:0] VAR54
);
wire VAR89, VAR113;
VAR133 #(.VAR12("VAR27"), .VAR135(5))
VAR76 (.VAR67(VAR113), .VAR140(), .VAR80(), .VAR69(VAR92));
VAR14 VAR68 (.VAR69(VA... | gpl-2.0 |
jotego/jt51 | hdl/jt51_timers.v | 3,233 | module MODULE2(
input rst,
input clk,
input VAR12,
input VAR10,
input [9:0] VAR27,
input [7:0] VAR5,
input VAR24,
input VAR8,
input VAR16,
input VAR18,
input VAR1,
input VAR11,
output VAR25,
output VAR17,
output VAR20,
output VAR4
);
assign VAR4 = ~( (VAR25&VAR1) | (VAR17&VAR11) );
MODULE1 #(.VAR7(10)) VAR14(
.rst ( rs... | gpl-3.0 |
JohnOrlando/gnuradio-bitshark | gr-radar-mono/src/fpga/models/fifo_1clk.v | 2,013 | module MODULE1(VAR9, VAR2, VAR6, VAR14, VAR10, VAR13,
VAR1, VAR3, VAR5);
parameter VAR4 = 32;
parameter VAR11 = 4096;
input [31:0] VAR9;
input VAR2;
input VAR6;
input VAR14;
input VAR10;
output [31:0] VAR13;
output VAR1;
output VAR3;
output [11:0] VAR5;
reg [VAR4-1:0] VAR12 [0:VAR11-1];
reg [7:0] VAR8;
reg [7:0] VAR15;... | gpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_mul_hc.v | 1,567 | module MODULE1(
input logic VAR12,
input logic VAR7,
input logic VAR9,
input logic VAR3,
output logic VAR6,
output logic VAR5,
input logic [31:0] VAR1,
input logic [31:0] VAR4,
output logic [31:0] VAR2
);
VAR8 #(
.VAR10(1)
)
VAR11(
.VAR12(VAR12),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VA... | mit |
sh-chris110/chris | FPGA/HPS.bak/Qsys/hps_design/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v | 4,036 | module MODULE1
(
VAR8,
VAR24,
VAR10) ;
input [0:0] VAR8;
output [0:0] VAR24;
output [0:0] VAR10;
wire [0:0] VAR35;
wire [0:0] VAR4;
wire [0:0] VAR6;
wire [0:0] VAR20;
wire [0:0] VAR19;
wire [0:0] VAR15;
wire [0:0] VAR16;
wire [0:0] VAR5;
wire [0:0] VAR23;
wire [0:0] VAR29;
VAR7 VAR9
(
.VAR32(VAR15),
.VAR12(VAR35[0:0]),... | gpl-2.0 |
YosysHQ/yosys | techlibs/nexus/brams_map.v | 15,573 | module MODULE1 (...);
parameter VAR165 = 0;
parameter VAR123 = "VAR55";
parameter VAR57 = 18;
parameter VAR144 = 2;
input VAR154;
input VAR78;
input VAR136;
input VAR89;
input VAR125;
input [13:0] VAR75;
input [VAR144-1:0] VAR139;
input [VAR57-1:0] VAR43;
output [VAR57-1:0] VAR26;
parameter VAR39 = "VAR55";
parameter V... | isc |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_031.v | 1,479 | module MODULE2 (
VAR11,
VAR2
);
input [31:0] VAR11;
output [31:0]
VAR2;
wire [31:0]
VAR5,
VAR6,
VAR8,
VAR12,
VAR7,
VAR1,
VAR13,
VAR10;
assign VAR5 = VAR11;
assign VAR6 = VAR5 << 7;
assign VAR8 = VAR5 + VAR6;
assign VAR7 = VAR8 + VAR12;
assign VAR13 = VAR1 - VAR7;
assign VAR1 = VAR8 << 4;
assign VAR10 = VAR13 << 4;
assi... | mit |
tmolteno/TART | hardware/FPGA/ddrmem/Micron/ddr.v | 51,843 | module MODULE1 (VAR60, VAR2, VAR94, VAR110, VAR113, VAR16, VAR97, VAR86, VAR93, VAR50, VAR121, VAR89);
inout [VAR63 - 1 : 0] VAR60;
inout [VAR114 - 1 : 0] VAR2;
input [VAR115 - 1 : 0] VAR94;
input [1 : 0] VAR110;
input VAR113;
input VAR16;
input VAR97;
input VAR86;
input VAR93;
input VAR50;
input VAR121;
input [VAR90 -... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21o/sky130_fd_sc_lp__a21o.pp.blackbox.v | 1,351 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR1 ,
VAR7 ,
VAR8,
VAR6,
VAR4 ,
VAR2
);
output VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR8;
input VAR6;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/soc_system_fpga_only_master.v | 21,649 | module MODULE1 #(
parameter VAR23 = 0,
parameter VAR37 = 50000,
parameter VAR1 = 2
) (
input wire VAR13, input wire VAR41, output wire [31:0] VAR44, input wire [31:0] VAR26, output wire VAR38, output wire VAR5, output wire [31:0] VAR3, input wire VAR25, input wire VAR16, output wire [3:0] VAR35, output wire VAR48 );
wi... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.ip_user_files/ipstatic/axis_infrastructure_v1_1_0/hdl/verilog/axis_infrastructure_v1_1_mux_enc.v | 9,828 | module MODULE1 #
(
parameter VAR31 = "VAR16",
parameter integer VAR6 = 4,
parameter integer VAR13 = 2,
parameter integer VAR10 = 1
)
(
input wire [VAR13-1:0] VAR30,
input wire [VAR6*VAR10-1:0] VAR33,
output wire [VAR10-1:0] VAR22,
input wire VAR4
);
wire [VAR10-1:0] VAR8;
genvar VAR5;
function [VAR10-1:0] VAR35
(
input... | mit |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter_001.v | 6,161 | module MODULE1 #(
parameter VAR1 = 34,
parameter VAR11 = 0,
parameter VAR7 = 34,
parameter VAR20 = 0,
parameter VAR22 = 0,
parameter VAR9 = 0,
parameter VAR4 = 1,
parameter VAR25 = 1,
parameter VAR14 = 0,
parameter VAR6 = 34,
parameter VAR10 = 0,
parameter VAR16 = 1,
parameter VAR13 = 0,
parameter VAR24 = 1,
parameter ... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small.v | 1,955 | module MODULE1 #( parameter VAR6(VAR20 )
, parameter VAR6(VAR7 )
, parameter VAR17 = 0
, parameter VAR19 = 0
)
( input VAR12
, input VAR16
, input VAR22
, output VAR5
, input [VAR20-1:0] VAR21
, output VAR10
, output [VAR20-1:0] VAR4
, input VAR1
);
if (VAR17 == 0)
begin: VAR15
if (VAR7 == 2) begin:VAR13
VAR9 #(.VAR20(... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111oi/sky130_fd_sc_ms__a2111oi.pp.symbol.v | 1,408 | module MODULE1 (
input VAR3 ,
input VAR5 ,
input VAR4 ,
input VAR1 ,
input VAR7 ,
output VAR8 ,
input VAR2 ,
input VAR6,
input VAR10,
input VAR9
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4bb/sky130_fd_sc_lp__and4bb.behavioral.v | 1,512 | module MODULE1 (
VAR13 ,
VAR7,
VAR9,
VAR1 ,
VAR8
);
output VAR13 ;
input VAR7;
input VAR9;
input VAR1 ;
input VAR8 ;
supply1 VAR2;
supply0 VAR12;
supply1 VAR10 ;
supply0 VAR4 ;
wire VAR11 ;
wire VAR6;
nor VAR3 (VAR11 , VAR7, VAR9 );
and VAR5 (VAR6, VAR11, VAR1, VAR8 );
buf VAR14 (VAR13 , VAR6 );
endmodule | apache-2.0 |
rfotino/consolite-hardware | src/vga_block_ram.v | 1,296 | module MODULE1
(
input VAR9,
input VAR14,
input [5:0] VAR19,
input [31:0] VAR23,
input VAR8,
input [7:0] VAR18,
output [7:0] VAR11
);
wire [31:0] VAR2;
assign VAR11 = VAR2[{VAR18[1:0], 3'b0}+:8];
VAR25
.VAR26("9Kb"),
.VAR12("VAR17"),
.VAR15(32),
.VAR22(32),
.VAR21(0),
.VAR30("VAR4"),
.VAR24(72'b0),
.VAR29(72'b0)
)
VAR1... | mit |
google/xls | xls/uncore_rtl/ice40/uart_transmitter.v | 5,875 | module MODULE1(
input wire clk,
input wire VAR6,
input wire [7:0] VAR22,
input wire VAR1,
output wire VAR12,
output wire VAR17
);
parameter VAR15 = VAR18;
localparam VAR13 = VAR2(VAR15);
localparam VAR8 = VAR15-1;
localparam
VAR3 = 'd0,
VAR21 = 'd1,
VAR9 = 'd2,
VAR24 = 'd3;
localparam VAR11 = 2;
reg VAR10 = 1;
reg VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3b/sky130_fd_sc_lp__nor3b.functional.v | 1,417 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR8 ,
VAR5
);
output VAR2 ;
input VAR3 ;
input VAR8 ;
input VAR5;
wire VAR7 ;
wire VAR9;
nor VAR6 (VAR7 , VAR3, VAR8 );
and VAR1 (VAR9, VAR5, VAR7 );
buf VAR4 (VAR2 , VAR9 );
endmodule | apache-2.0 |
theapi/nand2tetris_fpga | hack/ip/qsys/qsys/synthesis/submodules/altera_reset_controller.v | 12,023 | module MODULE1
parameter VAR37 = 6,
parameter VAR17 = 0,
parameter VAR58 = 0,
parameter VAR28 = 0,
parameter VAR1 = 0,
parameter VAR71 = 0,
parameter VAR78 = 0,
parameter VAR18 = 0,
parameter VAR57 = 0,
parameter VAR47 = 0,
parameter VAR9 = 0,
parameter VAR56 = 0,
parameter VAR2 = 0,
parameter VAR13 = 0,
parameter VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32ai/sky130_fd_sc_ms__o32ai_2.v | 2,441 | module MODULE2 (
VAR5 ,
VAR12 ,
VAR8 ,
VAR11 ,
VAR10 ,
VAR7 ,
VAR1,
VAR2,
VAR3 ,
VAR4
);
output VAR5 ;
input VAR12 ;
input VAR8 ;
input VAR11 ;
input VAR10 ;
input VAR7 ;
input VAR1;
input VAR2;
input VAR3 ;
input VAR4 ;
VAR9 VAR6 (
.VAR5(VAR5),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR7(VAR7),
.VA... | apache-2.0 |
GuzTech/swapforth | j1b/verilog/uart.v | 4,295 | module MODULE2(
input wire clk,
input wire VAR7,
input wire [31:0] VAR6,
input wire VAR25,
output wire VAR30);
parameter VAR23 = 1000000;
wire [38:0] VAR3 = VAR23;
reg [38:0] VAR18;
wire [38:0] VAR14 = VAR18[38] ? ({4'd0, VAR6}) : (({4'd0, VAR6}) - VAR3);
wire [38:0] VAR16 = VAR25 ? 0 : (VAR18 + VAR14);
wire VAR31 = ~V... | bsd-3-clause |
skatpgusskat/KoreaUnivHomework_2015_1 | Computer Architecture/Homework/Lab10/components.v | 4,124 | module MODULE1(VAR2, VAR5, clk, VAR3, VAR6);
input [31:0] VAR2;
output [31:0] VAR5;
input clk, VAR3, VAR6;
reg [31:0] register;
always @(posedge clk or posedge VAR3)
begin
if(VAR3)
register = 0;
end
else
if(VAR6 == 1)
register = VAR2;
end
assign VAR5 = register;
endmodule
module MODULE2;
reg [31:0] VAR1;
wire [31:0] VA... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA_2_cycles/integracion_fisica/front_end/source/submidRecursiveKOA2.v | 5,297 | module MODULE1
(
input wire clk,
input wire [VAR13-1:0] VAR20,
input wire [VAR13-1:0] VAR3,
output reg [2*VAR13-1:0] VAR6
);
wire [1:0] VAR31;
wire [3:0] VAR9;
assign VAR31 = 2'b00;
assign VAR9 = 4'b0000;
wire [VAR13/2-1:0] VAR30;
wire [VAR13/2:0] VAR14;
wire [VAR13/2-3:0] VAR22;
wire [VAR13/2-4:0] VAR21;
reg [4*(VAR13... | gpl-3.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.cache/ip/2018.2/744763d6063ca1bf/zybo_zynq_design_auto_pc_0_stub.v | 4,585 | module MODULE1(VAR1, VAR41, VAR20, VAR5,
VAR35, VAR25, VAR53, VAR12, VAR3, VAR23,
VAR13, VAR21, VAR17, VAR49, VAR27, VAR46, VAR44,
VAR15, VAR26, VAR6, VAR8, VAR34, VAR30, VAR36,
VAR4, VAR29, VAR58, VAR28, VAR59, VAR9,
VAR52, VAR14, VAR32, VAR2, VAR57, VAR40, VAR33,
VAR39, VAR42, VAR54, VAR18, VAR22, VAR43,
VAR56, VAR50... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/synth/design_1_auto_pc_0.v | 16,145 | module MODULE1 (
VAR5,
VAR77,
VAR81,
VAR7,
VAR104,
VAR96,
VAR38,
VAR73,
VAR57,
VAR2,
VAR31,
VAR98,
VAR29,
VAR37,
VAR75,
VAR28,
VAR49,
VAR90,
VAR20,
VAR34,
VAR64,
VAR76,
VAR82,
VAR78,
VAR74,
VAR102,
VAR48,
VAR23,
VAR87,
VAR17,
VAR11,
VAR3,
VAR21,
VAR69,
VAR19,
VAR56,
VAR92,
VAR8,
VAR84,
VAR4,
VAR42,
VAR108,
VAR27,
VAR80... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/dma_engine_ctrl.v | 13,563 | module MODULE1 (
output reg VAR64, output reg VAR67,
output reg [3:0] VAR4,
input [31:0] VAR55,
input VAR31, input VAR57,
output reg VAR59, output reg VAR42,
output reg VAR61, output reg VAR66,
output reg VAR17, output reg VAR77,
output reg VAR65, output reg VAR71,
output VAR26,
output VAR3,
output reg VAR72,
input [15... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvn/sky130_fd_sc_hs__einvn_1.v | 2,020 | module MODULE1 (
VAR1 ,
VAR6,
VAR3 ,
VAR4,
VAR2
);
input VAR1 ;
input VAR6;
output VAR3 ;
input VAR4;
input VAR2;
VAR7 VAR5 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR1 ,
VAR6,
VAR3
);
input VAR1 ;
input VAR6;
output VAR3 ;
supply1 VAR4;
supply0 VAR2;
VAR7 VAR5 (
... | apache-2.0 |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_LCD/picoblze/kcuart_tx.v | 12,235 | module MODULE1
(VAR30,
VAR53,
VAR25,
VAR64,
VAR42,
clk);
input [7:0] VAR30;
input VAR53;
input VAR25;
output VAR64;
output VAR42;
input clk;
wire VAR44;
wire VAR27;
wire VAR18;
wire VAR49;
wire VAR59;
wire VAR40;
wire VAR41;
wire [2:0] VAR69;
wire [2:0] VAR39;
wire [2:0] VAR83;
wire [2:0] VAR50;
wire [2:0] VAR51;
wire ... | gpl-3.0 |
openPOWERLINK/openPOWERLINK_V2 | hardware/boards/altera-c5soc/common/ipcore/pll/pll_0002.v | 2,576 | module MODULE1(
input wire VAR27,
input wire rst,
output wire VAR8,
output wire VAR20,
output wire VAR62
);
VAR35 #(
.VAR58("false"),
.VAR6("50.0 VAR9"),
.VAR28("VAR30"),
.VAR31(2),
.VAR11("50.000000 VAR9"),
.VAR39("0 VAR23"),
.VAR14(50),
.VAR70("100.000000 VAR9"),
.VAR72("0 VAR23"),
.VAR71(50),
.VAR49("0 VAR9"),
.VAR6... | gpl-2.0 |
plindstroem/oh | common/hdl/pulse2toggle.v | 1,323 | module MODULE1(
out,
clk, in, reset
);
input clk;
input in;
output out;
input reset;
reg out;
wire VAR1;
assign VAR1 = in ? ~out :
out;
always @ (posedge clk or posedge reset)
if(reset)
out <= 1'b0;
else
out <= VAR1;
endmodule | gpl-3.0 |
freecores/eco32 | fpga/src/ram/ram.v | 8,044 | module MODULE1(clk, VAR27, reset,
en, wr, VAR8, addr,
VAR20, VAR31, VAR18,
VAR19, VAR5,
VAR4, VAR10,
VAR35, VAR14, VAR7,
VAR34, VAR28, VAR22);
input clk;
input VAR27;
input reset;
input en;
input wr;
input [1:0] VAR8;
input [24:0] addr;
input [31:0] VAR20;
output reg [31:0] VAR31;
output reg VAR18;
output VAR19;
output... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211o/sky130_fd_sc_ls__a211o.functional.pp.v | 2,032 | module MODULE1 (
VAR5 ,
VAR14 ,
VAR15 ,
VAR4 ,
VAR3 ,
VAR17,
VAR11,
VAR1 ,
VAR8
);
output VAR5 ;
input VAR14 ;
input VAR15 ;
input VAR4 ;
input VAR3 ;
input VAR17;
input VAR11;
input VAR1 ;
input VAR8 ;
wire VAR10 ;
wire VAR12 ;
wire VAR2;
and VAR16 (VAR10 , VAR14, VAR15 );
or VAR9 (VAR12 , VAR10, VAR3, VAR4 );
VAR6 VA... | apache-2.0 |
shaform/ArkanoidOnVerilog | draw_back.v | 1,739 | module MODULE1 (
input [10:0] VAR17,
input [11:0] VAR4,
input VAR9, VAR10, VAR13,
output reg [3:0] out
);
localparam VAR14 = 72;
wire VAR5;
wire [4:0] VAR11, VAR7;
reg [1:0] VAR16;
assign VAR11 = (VAR4-VAR6)/16;
assign VAR7 = (VAR17-VAR2)/16;
word VAR15(.VAR3(VAR7),.VAR1(VAR11),.select(VAR16),.word(VAR5));
always @
beg... | gpl-3.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v | 56,935 | module MODULE1 (
input wire VAR181, input wire VAR141, input wire VAR225, input wire [31:0] VAR69, output wire VAR37, input wire [4:0] VAR123, input wire [31:0] VAR7, input wire VAR293, output wire [255:0] VAR255, output wire VAR113, input wire VAR23, input wire [255:0] VAR129, output wire [26:0] VAR54, output wire VAR... | mit |
peteasa/oh | src/axi/hdl/esaxi.v | 17,064 | module MODULE1 (
VAR68, VAR15, VAR8, VAR50, VAR87, VAR13,
VAR81, VAR96, VAR56, VAR46, VAR14,
VAR34, VAR6, VAR5, VAR99, VAR66,
VAR106, VAR85, VAR42, VAR37, VAR57, VAR91,
VAR90, VAR70, VAR103, VAR17,
VAR75, VAR102, VAR112, VAR98, VAR25,
VAR9, VAR53, VAR51, VAR93,
VAR31, VAR28, VAR83, VAR107,
VAR4, VAR3, VAR74, VAR12,
VAR... | mit |
cynngah/virtualsynthesizer | sound_files/audio_and_video_config.v | 9,750 | module MODULE1 (
clk,
reset,
VAR12,
VAR35
);
parameter VAR49 = 1'b0;
parameter VAR56 = 8'h01;
parameter VAR47 = 6'h00;
parameter VAR43 = 6'h32;
parameter VAR52 = 9'h01A;
parameter VAR33 = 9'h01A;
parameter VAR8 = 9'h07B;
parameter VAR48 = 9'h07B;
parameter VAR9 = 9'd149;
parameter VAR55 = 9'h006;
parameter VAR15 = 9'h0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2i/sky130_fd_sc_hd__mux2i.symbol.v | 1,344 | module MODULE1 (
input VAR5,
input VAR2,
output VAR4 ,
input VAR7
);
supply1 VAR3;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2b/sky130_fd_sc_ls__nor2b_4.v | 2,173 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR7 ,
VAR8,
VAR5,
VAR9 ,
VAR1
);
output VAR2 ;
input VAR4 ;
input VAR7 ;
input VAR8;
input VAR5;
input VAR9 ;
input VAR1 ;
VAR6 VAR3 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR2 ,
VAR4 ,
VAR7
);
output VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1.pp.blackbox.v | 1,347 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR5 ,
VAR1,
VAR3,
VAR7 ,
VAR6
);
output VAR4 ;
input [3:0] VAR2 ;
input [3:0] VAR5 ;
input VAR1;
input VAR3;
input VAR7 ;
input VAR6 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/buf_ram_1p_6x85.v | 2,866 | module MODULE1 (
clk ,
VAR7 ,
VAR6 ,
addr ,
VAR8 ,
VAR12
);
input clk ;
input VAR7 ;
input VAR6 ;
input [9:0] addr ;
input [5:0] VAR8 ;
output [5:0] VAR12 ;
VAR9 #(.VAR10(10), .VAR11(6))
VAR2 (
.clk ( clk ),
.VAR4 ( ~VAR7 ),
.VAR5 ( 1'b0 ),
.VAR1 ( ~VAR6 ),
.VAR3 ( addr ),
.VAR8 ( VAR8 ),
.VAR12 ( VAR12 )
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isolatch/sky130_fd_sc_lp__isolatch.behavioral.v | 1,830 | module MODULE1 (
VAR11 ,
VAR13 ,
VAR6
);
output VAR11 ;
input VAR13 ;
input VAR6;
supply1 VAR14;
supply1 VAR5 ;
supply0 VAR2 ;
supply1 VAR7 ;
supply0 VAR1 ;
wire VAR15 ;
wire VAR10;
wire VAR9 ;
reg VAR8 ;
VAR3 VAR12 (VAR15 , VAR9, VAR10, VAR8, VAR14, VAR2, VAR5);
buf VAR4 (VAR11 , VAR15 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapmet1/sky130_fd_sc_ms__tapmet1.pp.symbol.v | 1,232 | module MODULE1 (
input VAR2 ,
input VAR4,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4b/sky130_fd_sc_ms__nor4b.pp.symbol.v | 1,324 | module MODULE1 (
input VAR2 ,
input VAR7 ,
input VAR3 ,
input VAR6 ,
output VAR4 ,
input VAR1 ,
input VAR9,
input VAR8,
input VAR5
);
endmodule | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | PWM/peripherial_pwm.v | 1,820 | module MODULE1 (
input clk,
input rst,
input [15:0] din,
input VAR8,
input [3:0]addr, input rd,
input wr,
output [2:0] VAR10 ,
output reg [2:0] dout
);
reg [5:0] VAR9; reg VAR7 = 0;
reg [9:0] VAR6;
reg [9:0] VAR4;
reg [9:0] VAR11;
always @(*) begin case (addr)
4'h0: begin VAR9 = (VAR8 && wr) ? 5'b00001 : 5'b00000 ;end ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ba/sky130_fd_sc_hdll__o21ba.functional.pp.v | 2,057 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR12 ,
VAR16,
VAR7,
VAR6,
VAR4 ,
VAR15
);
output VAR1 ;
input VAR8 ;
input VAR12 ;
input VAR16;
input VAR7;
input VAR6;
input VAR4 ;
input VAR15 ;
wire VAR11 ;
wire VAR13 ;
wire VAR10;
nor VAR9 (VAR11 , VAR8, VAR12 );
nor VAR5 (VAR13 , VAR16, VAR11 );
VAR3 VAR2 (VAR10, VAR13, VAR7, VAR6)... | apache-2.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/soc_system_pll_stream.v | 2,082 | module MODULE1(
input wire VAR70,
input wire rst,
output wire VAR46,
output wire VAR21
);
VAR62 #(
.VAR58("true"),
.VAR35("50.0 VAR33"),
.VAR18("VAR27"),
.VAR54(1),
.VAR39("130.000000 VAR33"),
.VAR48("0 VAR22"),
.VAR13(50),
.VAR55("0 VAR33"),
.VAR38("0 VAR22"),
.VAR24(50),
.VAR31("0 VAR33"),
.VAR53("0 VAR22"),
.VAR49(5... | epl-1.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/de0_nano/rtl/verilog/clkgen.v | 3,735 | module MODULE1
(
input VAR7,
input VAR1,
output VAR15,
output VAR16,
output VAR12,
input VAR22,
output VAR3,
output VAR5,
output VAR18
);
wire VAR2;
wire VAR13;
assign VAR13 = VAR1;
assign VAR2 = ~VAR13;
assign VAR15 = ~VAR13;
assign VAR3 = VAR22;
wire VAR19;
wire VAR21;
VAR9 VAR8
(
.VAR10 (VAR2),
.VAR11 (VAR7),
.VAR6 ... | gpl-2.0 |
manu3193/TextEditor | text_screen_gen.v | 9,787 | module MODULE1
(
input wire clk, reset,
input wire VAR16,
input wire [2:0] VAR9,
input wire [1:0] VAR24,
input wire [9:0] VAR49, VAR34,
input wire VAR29,
output reg [2:0] VAR21,
output wire VAR38
);
wire [10:0] VAR30;
reg [6:0] VAR51;
reg [3:0] VAR35;
reg [2:0] VAR23;
wire [7:0] VAR52;
wire VAR40;
wire VAR59, VAR2, VAR... | mit |
mashanz/FinalProject | Code/fpga/spartan3a/netgen/synthesis/protection_synthesis.v | 6,486 | module MODULE1 (
VAR31, VAR114, VAR50, VAR38, VAR69, VAR40, VAR73
);
input VAR31;
input VAR114;
input VAR50;
output [7 : 0] VAR38;
input [7 : 0] VAR69;
input [7 : 0] VAR40;
input [1 : 0] VAR73;
wire VAR65;
wire VAR83;
wire VAR72;
wire VAR104;
wire VAR1;
wire VAR23;
wire VAR3;
wire VAR78;
wire VAR74;
wire VAR36;
wire VA... | gpl-3.0 |
olofk/oh | emmu/hdl/emmu.v | 5,927 | module MODULE1 (
VAR13, VAR7, VAR9, VAR21,
reset, VAR25, VAR11, VAR22, VAR31, VAR29, VAR19, VAR36,
VAR28, VAR14, VAR17, VAR20,
VAR1
);
parameter VAR4 = 32; parameter VAR27 = 32; parameter VAR37 = 104;
parameter VAR30 = 136; parameter VAR34 = 48; parameter VAR18 = 12; parameter VAR10 = 0;
input reset; input VAR25;
input... | gpl-3.0 |
revaldinho/opc | opc5/opc5system/avnet_microboard/opc5wrapper.v | 2,552 | module MODULE1
(
input VAR4,
output VAR20,
output [0:0] VAR2,
inout VAR19,
inout VAR11,
inout VAR52,
inout VAR24,
input VAR12,
input VAR53,
input VAR56,
input VAR35,
input VAR60,
output [3:0] VAR10,
input VAR58,
output VAR44,
inout VAR30,
input VAR55,
output [12:0] VAR14,
output [1:0] VAR46,
inout [15:0] VAR32,
output ... | gpl-3.0 |
eda-globetrotter/PicenoDecoders | final/src/tosynth Folder/alu.v | 176,762 | module MODULE1 (VAR22,VAR17,VAR23,VAR36,VAR21);
output [0:127] VAR21;
input [0:127] VAR22;
input [0:127] VAR17;
input [0:1] VAR23;
input [0:4] VAR36;
parameter VAR3 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR21;
reg [0:127] VAR11;
reg [0:15] VAR9;
reg [0:15] VAR37;
reg [0:15] VAR18;
reg [0:15] VAR29;
reg [... | mit |
hhuang25/uwaterloo_ece224 | Lab1Good/jtag_uart_0.v | 21,785 | module MODULE4 (
clk,
VAR85,
VAR27,
valid
)
;
input clk;
input [ 7: 0] VAR85;
input VAR27;
input valid;
reg [31:0] VAR42; VAR24 VAR42 =
always @(posedge clk) begin
if (valid && VAR27) begin
("%VAR21", ((VAR85 == 8'hd) ? 8'ha : VAR85));
VAR63 (VAR42);
end
end
endmodule
module MODULE6 (
clk,
VAR2,
VAR39,
VAR56,
VAR14,
VA... | mit |
csail-csg/recycle-bsv-lib | src/v/SRAM_1R1W_BE.v | 1,115 | module MODULE1 (
input clk,
input VAR6,
input [VAR11-1:0] VAR13,
input [VAR12-1:0] VAR7,
input [(VAR11*8)-1:0] VAR8,
input VAR4,
input [VAR12-1:0] VAR1,
output [(VAR11*8)-1:0] VAR9
);
parameter VAR12 = 9;
parameter VAR11 = 8;
parameter VAR5 = 512;
reg [(VAR11*8)-1:0] VAR3 [VAR5-1:0];
reg [(VAR11*8)-1:0] VAR2;
generate
... | mit |
bubnikv/omniasdrbasicfirmware | basic.cydsn/iambic/iambic.v | 9,690 | module MODULE1(input clk, input VAR6, input VAR24, output VAR45);
wire [7:0] VAR56;
wire VAR71;
wire VAR15;
wire VAR5;
wire VAR30;
assign VAR71 = VAR56[0];
assign VAR15 = VAR56[1];
assign VAR5 = VAR56[2];
assign VAR30 = VAR56[7];
VAR42 #(.VAR41(8'b10000001), .VAR43(VAR37))
VAR8(.VAR19(VAR56));
reg [1:0] VAR23;
wire VAR... | apache-2.0 |
lloves/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_OSERDES_MSG.v | 4,033 | module MODULE1(VAR15, VAR21, VAR34, VAR7, VAR8, VAR32);
output VAR15;
input VAR21, VAR34;
input [7:0] VAR7;
input VAR8, VAR32;
wire VAR12, VAR3;
VAR31 VAR27 (
.VAR15(VAR15), .VAR28(), .VAR22(), .VAR1(), .VAR21(VAR21), .VAR34(VAR34), .VAR26(VAR7[7]), .VAR16(VAR7[6]), .VAR33(VAR7[5]), .VAR6(VAR7[4]), .VAR11(VAR7[3]), .VA... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai.functional.v | 1,578 | module MODULE1 (
VAR7 ,
VAR2,
VAR11,
VAR8 ,
VAR9
);
output VAR7 ;
input VAR2;
input VAR11;
input VAR8 ;
input VAR9 ;
wire VAR1 ;
wire VAR10 ;
wire VAR3;
nand VAR5 (VAR1 , VAR11, VAR2 );
or VAR12 (VAR10 , VAR9, VAR8 );
nand VAR4 (VAR3, VAR1, VAR10);
buf VAR6 (VAR7 , VAR3 );
endmodule | apache-2.0 |
kkiningh/cs231n-project | src/rtl/MatrixInputQueue/aFifo.v | 4,165 | module MODULE1
VAR3 = 8,
VAR26 = (1 << VAR3))
(output reg [VAR11-1:0] VAR16,
output reg VAR15,
input wire VAR18,
input wire VAR5,
input wire [VAR11-1:0] VAR12,
output reg VAR2,
input wire VAR21,
input wire VAR24,
input wire VAR23);
reg [VAR11-1:0] VAR22 [VAR26-1:0];
wire [VAR3-1:0] VAR4, VAR28;
wire VAR14;
wire VAR19, ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22a/sky130_fd_sc_hd__o22a_2.v | 2,339 | module MODULE2 (
VAR6 ,
VAR10 ,
VAR1 ,
VAR9 ,
VAR11 ,
VAR5,
VAR2,
VAR8 ,
VAR7
);
output VAR6 ;
input VAR10 ;
input VAR1 ;
input VAR9 ;
input VAR11 ;
input VAR5;
input VAR2;
input VAR8 ;
input VAR7 ;
VAR4 VAR3 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.... | apache-2.0 |
Seeed-Studio/DSOQuad_SourceCode | FPGA_V2.5/FPGA_V25.v | 4,481 | module MODULE1( VAR80, VAR52, VAR75, VAR83, VAR42, VAR6, VAR64, VAR4, VAR62,
VAR19, VAR8, VAR28, VAR43);
input VAR80; input VAR52; input VAR75; input VAR83; input VAR42; input VAR6; input VAR64; input VAR4; input [17:0]VAR62;
output VAR19; output VAR8; output VAR28;
inout [15:0]VAR43;
wire [11:0]VAR68; wire [11:0]VAR34... | mit |
kyzhai/NUNY | src/hardware/four_new2.v | 6,400 | module MODULE1 (
address,
VAR27,
VAR11);
input [9:0] address;
input VAR27;
output [11:0] VAR11;
tri1 VAR27;
wire [11:0] VAR9;
wire [11:0] VAR11 = VAR9[11:0];
VAR21 VAR28 (
.VAR13 (address),
.VAR4 (VAR27),
.VAR36 (VAR9),
.VAR51 (1'b0),
.VAR39 (1'b0),
.VAR23 (1'b1),
.VAR12 (1'b0),
.VAR22 (1'b0),
.VAR10 (1'b1),
.VAR24 (1'... | gpl-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/ciop_iob.v | 14,893 | module MODULE1(
VAR76, VAR23, VAR92,
VAR158, VAR114, VAR157,
VAR71, VAR62, VAR150,
VAR154, VAR121, VAR39, VAR129,
VAR61, VAR81, VAR40, VAR105,
VAR37, VAR118, VAR97,
VAR10, VAR90, VAR42,
VAR116, VAR147, VAR117,
VAR146, VAR50, VAR149,
VAR17, VAR15, VAR127, VAR46,
VAR22, VAR27,
VAR84, VAR47, VAR136,
VAR36, VAR56, VAR54, V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4/sky130_fd_sc_ls__nand4.functional.v | 1,312 | module MODULE1 (
VAR7,
VAR2,
VAR8,
VAR4,
VAR5
);
output VAR7;
input VAR2;
input VAR8;
input VAR4;
input VAR5;
wire VAR6;
nand VAR3 (VAR6, VAR5, VAR4, VAR8, VAR2 );
buf VAR1 (VAR7 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111ai/sky130_fd_sc_ls__o2111ai.symbol.v | 1,401 | module MODULE1 (
input VAR6,
input VAR2,
input VAR10,
input VAR1,
input VAR3,
output VAR7
);
supply1 VAR5;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_top.v | 31,309 | module MODULE1(
VAR353, VAR111, VAR192, VAR266, VAR236,
VAR172, VAR378, VAR191, VAR303, VAR165, VAR299,
VAR139, VAR85, VAR345, VAR296, VAR138, VAR25,
VAR262, VAR248, VAR149, VAR88, VAR28, VAR156,
VAR14, VAR210, VAR274, VAR258, VAR225, VAR141,
VAR72, VAR42, VAR180, VAR142,
VAR60, VAR170, VAR252, VAR211, VAR293, VAR414,
... | gpl-2.0 |
ymei/TMSPlane | Firmware/src/aurora64b66b/TE07412C1/aurora_64b66b_0_support.v | 13,051 | module MODULE1
(
input [0:63] VAR33,
input VAR48,
output VAR37,
output [0:63] VAR116,
output VAR47,
input VAR13,
input [0:63] VAR90,
input [0:7] VAR64,
input VAR40,
output VAR10,
output [0:63] VAR45,
output [0:7] VAR70,
output VAR115,
output VAR107,
output VAR109,
input VAR92,
input VAR44,
output VAR74,
output VAR103,
... | bsd-3-clause |
alan4186/16bit-Processor | main_memory_sxm_d.v | 7,485 | module MODULE1 (
address,
VAR42,
VAR28,
VAR38,
VAR17);
input [7:0] address;
input VAR42;
input [15:0] VAR28;
input VAR38;
output [15:0] VAR17;
tri1 VAR42;
wire [15:0] VAR4;
wire [15:0] VAR17 = VAR4[15:0];
VAR27 VAR34 (
.VAR31 (address),
.VAR37 (VAR42),
.VAR10 (VAR28),
.VAR18 (VAR38),
.VAR35 (VAR4),
.VAR49 (1'b0),
.VAR3... | mit |
nickdesaulniers/Omicron | omicron.v | 2,692 | module MODULE1(
input wire VAR8,
input wire VAR7,
output wire [7:0] VAR12
);
wire clk; wire VAR1;
wire VAR6;
wire VAR14;
wire [10:0] VAR15;
wire VAR17;
wire VAR20;
wire [3:0] VAR3;
wire [1:0] VAR21;
wire VAR5;
assign VAR5 = VAR8;
VAR23 VAR10 (
.VAR18(VAR7),
.VAR22(!VAR8),
.VAR19(clk),
.VAR11(VAR1)
);
VAR13 VAR9 (
.clk(... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA/integracion_fisica/front_end/source/RKOA.v | 5,981 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR2,
input wire [VAR36-1:0] VAR29,
input wire [VAR36-1:0] VAR26,
output reg [2*VAR36-1:0] VAR19
);
wire [1:0] VAR1;
wire [3:0] VAR23;
assign VAR1 = 2'b00;
assign VAR23 = 4'b0000;
wire [VAR36/2-1:0] VAR24;
wire [VAR36/2:0] VAR20;
wire [VAR36/2-3:0] VAR3;
wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtp/sky130_fd_sc_hd__sdfrtp.functional.pp.v | 2,211 | module MODULE1 (
VAR2 ,
VAR20 ,
VAR17 ,
VAR16 ,
VAR4 ,
VAR7,
VAR15 ,
VAR12 ,
VAR13 ,
VAR10
);
output VAR2 ;
input VAR20 ;
input VAR17 ;
input VAR16 ;
input VAR4 ;
input VAR7;
input VAR15 ;
input VAR12 ;
input VAR13 ;
input VAR10 ;
wire VAR9 ;
wire VAR3 ;
wire VAR19;
not VAR14 (VAR3 , VAR7 );
VAR8 VAR1 (VAR19, VAR17, VA... | apache-2.0 |
CospanDesign/vivado-ip-cores | ip/axi_lite_i2c/sources_1/axi_lite_slave.v | 6,464 | module MODULE1 #(
parameter VAR16 = 32,
parameter VAR24 = 32,
parameter VAR15 = (VAR24 / 8)
)(
input clk,
input rst,
input VAR19,
input [VAR16 - 1: 0] VAR2,
output reg VAR20,
input VAR7,
output reg VAR8,
input [VAR24 - 1: 0] VAR14,
output reg VAR27,
input VAR9,
output reg [1:0] VAR12,
input VAR3,
output reg VAR11,
inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311a/sky130_fd_sc_hd__o311a.pp.symbol.v | 1,379 | module MODULE1 (
input VAR5 ,
input VAR3 ,
input VAR8 ,
input VAR1 ,
input VAR6 ,
output VAR2 ,
input VAR10 ,
input VAR7,
input VAR4,
input VAR9
);
endmodule | apache-2.0 |
pseudoincorrect/FPGA_MCU_wifi | FPGA/src/SRAM_modules/fifo_spi_SRAM.v | 12,135 | module MODULE1 (clk, VAR30, VAR35, VAR81, din, dout, VAR52, VAR72, VAR41, VAR33,
VAR5, VAR67, VAR2, VAR63,
VAR9, VAR29, VAR8, VAR13, VAR55);
input clk;
input VAR30;
input VAR35;
input VAR81;
input [31:0] din;
output VAR52;
output VAR72;
output dout;
output VAR41;
output reg VAR33;
output wire [19:0] VAR5;
inout [15:0] ... | mit |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_cpu_jtag_debug_module_wrapper.v | 9,822 | module MODULE1 (
VAR49,
VAR16,
clk,
VAR18,
VAR23,
VAR4,
VAR34,
VAR45,
VAR59,
VAR53,
VAR5,
VAR52,
VAR33,
VAR42,
VAR55,
VAR46,
VAR28,
VAR57,
VAR32,
VAR51,
VAR44,
VAR38,
VAR27,
VAR48,
VAR22,
VAR6,
VAR30,
VAR41,
VAR40,
VAR25,
VAR17,
VAR15,
VAR24,
VAR36,
VAR14,
VAR7
)
;
output [ 37: 0] VAR44;
output VAR38;
output VAR27;
out... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbn/sky130_fd_sc_ls__dlrbn_2.v | 2,480 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR8,
VAR3 ,
VAR9 ,
VAR4 ,
VAR10 ,
VAR11 ,
VAR1
);
output VAR2 ;
output VAR5 ;
input VAR8;
input VAR3 ;
input VAR9 ;
input VAR4 ;
input VAR10 ;
input VAR11 ;
input VAR1 ;
VAR7 VAR6 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR11(VAR11)... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_2.behavioral.v | 8,258 | module MODULE1( VAR9, VAR5, VAR6, VAR2, VAR8, VAR7, VAR3 );
input VAR3, VAR7, VAR9, VAR6, VAR5, VAR8;
output VAR2;
VAR1 VAR4(.VAR9(VAR9),.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR8(VAR8),.VAR7(VAR7),.VAR3(VAR3));
VAR1 VAR10(.VAR9(VAR9),.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR8(VAR8),.VAR7(VAR7),.VAR3(VAR3)); | apache-2.0 |
rbarzic/async_logic | async_lib/clock_selector/clock_selector.v | 2,111 | module MODULE1 (
VAR14, VAR9, VAR7,
VAR6, VAR10, VAR11, VAR5, select, VAR8
);
input VAR6;
input VAR10;
input VAR11;
output VAR14;
input VAR5;
output VAR9;
output VAR7;
input select;
input VAR8;
reg VAR14;
reg VAR9;
wire select; wire VAR12;
reg VAR13;
reg VAR3;
wire VAR1;
reg VAR4;
reg VAR2;
wire VAR7;
assign VAR12 = !s... | gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/i2c/i2c_slave_model.v | 11,656 | module MODULE1 (VAR26, VAR5);
parameter VAR10 = 7'b1010000;
input VAR26;
inout VAR5;
wire VAR21 = 1'b0;
reg [7:0] VAR20 [3:0]; reg [7:0] VAR18; reg [7:0] VAR14;
reg VAR7, VAR13;
reg VAR17, VAR12;
reg [7:0] VAR23; reg VAR8;
wire VAR11; wire VAR2; reg [2:0] VAR19; wire VAR15; reg VAR16;
reg VAR1; wire VAR6;
parameter VAR... | gpl-2.0 |
praveendath92/securePUF | source/puf_files/back_up/pdl_block.v | 1,534 | module MODULE1(VAR15,VAR10,VAR5);
input VAR15;
input VAR5;
output VAR10;
wire VAR4;
wire VAR5;
VAR2 #(
.VAR12(64'h5555555555555555) ) VAR1 (
.VAR9(VAR4), .VAR13(VAR15), .VAR3(VAR5), .VAR14(VAR5), .VAR11(VAR5), .VAR8(VAR5), .VAR6(VAR5) );
VAR2 #(
.VAR12(64'h5555555555555555) ) VAR7 (
.VAR9(VAR10), .VAR13(VAR4), .VAR3(VA... | gpl-2.0 |
rkrajnc/minimig-mist | rtl/minimig/gayle.v | 11,557 | module MODULE1
(
input clk,
input VAR36,
input reset,
input [23:1] VAR31,
input [15:0] VAR32,
output [15:0] VAR17,
input rd,
input VAR26,
input VAR6,
input VAR18, input VAR63, output irq,
output VAR56, input [1:0] VAR11,
output VAR40,
output VAR38,
input [2:0] VAR57,
input [15:0] VAR19,
output [15:0] VAR69,
input VAR16... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/16-way/src/ip_pcie/source/PCIeGen2x8If128_qpll_reset.v | 14,672 | module MODULE1 #
(
parameter VAR30 = "VAR47", parameter VAR23 = "VAR16", parameter VAR8 = 1, parameter VAR26 = 1
)
(
input VAR18,
input VAR42,
input VAR20,
input [VAR8-1:0] VAR21,
input [(VAR8-1)>>2:0]VAR39,
input [(VAR8-1)>>2:0]VAR10,
input [ 1:0] VAR44,
input [VAR8-1:0] VAR48,
input [VAR8-1:0] VAR31,
output VAR4,
out... | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/mem/rom.v | 5,607 | module MODULE1 #(
parameter VAR8 = 32,
parameter VAR10 = 11
)(
input wire clk, input wire reset, input wire VAR1, input wire VAR7, input wire [VAR6] addr, output wire [VAR4] VAR15, output reg VAR9 );
always @(posedge clk or VAR3 reset) begin
if (reset == VAR17)
begin
VAR9 <= VAR5;
end
else begin
if ((VAR1 == VAR13) && ... | apache-2.0 |
asicguy/gplgpu | hdl/vga/attr_reg_dec.v | 5,812 | module MODULE1
(
input VAR5,
input VAR28,
input VAR27,
input VAR31,
input [15:0] VAR37,
input VAR17,
input VAR29,
input VAR4, input VAR6,
input VAR26, input [15:0] VAR19,
output VAR32, output VAR36, output [7:0] VAR2,
output [7:0] VAR33,
output VAR24,
output VAR14,
output VAR18,
output VAR7, output VAR12
);
reg VAR15;
... | gpl-3.0 |
asicguy/gplgpu | stim/max_core_3d_stim.v | 48,640 | module MODULE1;
parameter
VAR40 = 4,
VAR107 = 2,
VAR40 = 8,
VAR107 = 3,
VAR40 = 16,
VAR107 = 4,
VAR40 = 32,
VAR107 = 5,
VAR89 = 32'h800,
VAR17 = 0;
reg VAR283; reg VAR210;
reg VAR55; tri [63:00] VAR53; tri VAR4; tri VAR20; tri VAR139; tri VAR151; wire VAR188; tri VAR56; wire VAR126; reg VAR48; wire VAR118; tri [7:0] VA... | gpl-3.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/divider.v | 5,159 | module MODULE2 (clk,rst,VAR12,VAR16,VAR25,VAR3,VAR15,ready);
parameter VAR7 = 32;
parameter VAR4 = 32;
localparam VAR24 = VAR5(VAR7);
localparam VAR20 = (VAR7 <VAR4 ? VAR7 : VAR4);
input clk,rst;
input VAR12; input [VAR7-1:0] VAR16; input [VAR4-1:0] VAR25; output [VAR7-1:0] VAR3; output [VAR4-1:0] VAR15; output ready;
... | gpl-3.0 |
schelleg/PYNQ | boards/ip/boolean_generator_1.1/hdl/boolean_generator_v1_1_S_AXI.v | 55,979 | module MODULE1 #
(
parameter VAR27 = 24,
parameter integer VAR126 = 32,
parameter integer VAR3 = 8
)
(
input [VAR27-1:0] VAR43,
output [VAR27-1:0] VAR12,
output [VAR27-1:0] VAR8,
input wire VAR73,
input wire VAR125,
input wire [VAR3-1 : 0] VAR123,
input wire [2 : 0] VAR119,
input wire VAR50,
output wire VAR38,
input wi... | bsd-3-clause |
ZipCPU/wbuart32 | bench/verilog/helloworld.v | 5,029 | module MODULE1 #(
parameter VAR8 = 31'd868
) (
input wire VAR1,
input wire [30:0] VAR12,
output wire VAR3
);
reg [7:0] VAR11 [0:15];
reg VAR10;
reg [27:0] counter;
wire VAR2, VAR5;
reg VAR9;
reg [3:0] VAR4;
reg [7:0] VAR6;
wire VAR7;
assign VAR12 = VAR8;
VAR13 VAR10 = 1'b1;
always @(posedge VAR1)
VAR10 <= 1'b0; | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/rtl/bw_clk_cl_jbi_cmp.v | 1,964 | module MODULE1(VAR13,VAR7 ,VAR11 ,VAR4 ,VAR3 ,VAR6 ,
VAR8 ,VAR12 ,VAR2 ,VAR5 ,VAR10 ,VAR1 );
output VAR13 ;
output VAR7 ;
output VAR11 ;
output VAR4 ;
input VAR3 ;
input VAR6 ;
input VAR8 ;
input VAR12 ;
input VAR2 ;
input VAR5 ;
input VAR10 ;
input VAR1 ;
VAR9 VAR14 (
.VAR4 (VAR4 ),
.VAR13 (VAR13 ),
.VAR7 (VAR7 ),
.VA... | gpl-2.0 |
hakehuang/pycpld | ips/ip/quadpwm/quadpwm.v | 1,286 | module MODULE1(VAR9, VAR11, enable, VAR4, VAR7);
input VAR9;
input VAR11;
input enable;
input VAR4;
output VAR5;
output VAR13;
output VAR14;
output VAR17;
reg VAR2;
reg VAR15;
reg VAR8;
reg VAR3;
reg[31:0] VAR16;
reg VAR7;
reg [31:0] VAR6;
reg VAR18;
always @(posedge VAR11 or negedge VAR9) begin
if (!VAR9) begin
VAR6 <... | mit |
ptracton/wb_soc_template | rtl/ZIP/rtl/cpuops.v | 11,390 | module MODULE1(VAR8,VAR25, VAR48, VAR9, VAR4, VAR19, VAR47, VAR20, VAR1,
VAR23);
parameter VAR6 = VAR18;
input wire VAR8, VAR25, VAR48;
input wire [3:0] VAR9;
input wire [31:0] VAR4, VAR19;
output reg [31:0] VAR47;
output wire [3:0] VAR20;
output reg VAR1;
output wire VAR23;
wire [32:0] VAR40, VAR15, VAR34;
wire signed... | mit |
scalable-networks/ext | uhd/fpga/usrp2/models/M24LC02B.v | 19,888 | module MODULE1 (VAR19, VAR32, VAR5, VAR25, VAR14, VAR27, VAR17);
input VAR19; input VAR32; input VAR5;
input VAR25;
inout VAR14; input VAR27;
input VAR17;
reg VAR23; reg VAR34;
wire VAR13; reg VAR20;
reg [03:00] VAR22;
reg VAR35; reg VAR11; reg VAR1; reg VAR10; reg VAR33;
reg VAR4; reg VAR2;
reg [07:00] VAR15;
reg [07:... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2a/sky130_fd_sc_ms__o2bb2a.behavioral.v | 1,658 | module MODULE1 (
VAR5 ,
VAR9,
VAR10,
VAR12 ,
VAR16
);
output VAR5 ;
input VAR9;
input VAR10;
input VAR12 ;
input VAR16 ;
supply1 VAR13;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR7 ;
wire VAR14 ;
wire VAR2 ;
wire VAR3;
nand VAR6 (VAR14 , VAR10, VAR9 );
or VAR11 (VAR2 , VAR16, VAR12 );
and VAR1 (VAR3, VAR14, VAR2);
buf VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill_diode/sky130_fd_sc_ms__fill_diode_2.v | 1,901 | module MODULE1 (
VAR3,
VAR2,
VAR5 ,
VAR6
);
input VAR3;
input VAR2;
input VAR5 ;
input VAR6 ;
VAR4 VAR1 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR6 ;
VAR4 VAR1 ();
endmodule | apache-2.0 |
ptracton/vscale_soc | rtl/wb_riscvscale/vscale_hasti_bridge.v | 1,941 | module MODULE1(
output [VAR32-1:0] VAR10,
output VAR6,
output [VAR15-1:0] VAR3,
output [VAR27-1:0] VAR31,
output VAR16,
output [VAR22-1:0] VAR4,
output [VAR20-1:0] VAR29,
output [VAR18-1:0] VAR26,
input [VAR18-1:0] VAR11,
input VAR17,
input [VAR5-1:0] VAR14,
input VAR12,
input VAR2,
input [VAR15-1:0] VAR21,
input [VAR3... | mit |
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