repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_keys.v | 1,915 | module MODULE1 (
address,
clk,
VAR6,
VAR5,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 3: 0] VAR6;
input VAR5;
wire VAR3;
wire [ 3: 0] VAR2;
wire [ 3: 0] VAR4;
reg [ 31: 0] VAR1;
assign VAR3 = 1;
assign VAR4 = {4 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR5)
begin
if (VAR5... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_rxeq_scan.v | 14,858 | module MODULE1 #
(
parameter VAR20 = "VAR6", parameter VAR8 = "VAR16", parameter VAR22 = 1, parameter VAR34 = 22'd3125000, parameter VAR14 = 23'd4687500 )
(
input VAR3,
input VAR37,
input [ 1:0] VAR15,
input [ 2:0] VAR35,
input VAR25,
input [ 3:0] VAR49,
input [17:0] VAR45,
input VAR2,
input [ 5:0] VAR4,
input [ 5:0] V... | gpl-3.0 |
martinmiranda14/Digitales | Lab_6/clkdiv/clkdiv.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v | 1,235 | module MODULE1(VAR2, reset, VAR1, VAR3)
;
output VAR2;
input reset;
output VAR1;
input VAR3;
endmodule | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_auto_us_df_1/synth/zc702_auto_us_df_1.v | 14,585 | module MODULE1 (
VAR35,
VAR66,
VAR39,
VAR8,
VAR15,
VAR6,
VAR9,
VAR49,
VAR16,
VAR67,
VAR40,
VAR53,
VAR2,
VAR37,
VAR14,
VAR80,
VAR4,
VAR28,
VAR43,
VAR62,
VAR85,
VAR22,
VAR26,
VAR94,
VAR50,
VAR27,
VAR79,
VAR83,
VAR84,
VAR89,
VAR17,
VAR65,
VAR58,
VAR23,
VAR77,
VAR87,
VAR64,
VAR63,
VAR48,
VAR88,
VAR86,
VAR46,
VAR93,
VAR7,
V... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Lundgren FPU/trunk/fpu_mul.v | 14,594 | module MODULE1( clk, rst, enable, VAR4, VAR50, VAR2, VAR42, VAR31);
input clk;
input rst;
input enable;
input [63:0] VAR4, VAR50;
output VAR2;
output [55:0] VAR42;
output [11:0] VAR31;
reg [5:0] VAR39;
reg [5:0] VAR29;
reg VAR2;
reg [51:0] VAR18;
reg [51:0] VAR7;
reg [10:0] VAR12;
reg [10:0] VAR33;
reg VAR16;
reg VAR8;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4bb/sky130_fd_sc_ms__or4bb.behavioral.pp.v | 1,988 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR11 ,
VAR2 ,
VAR4 ,
VAR3,
VAR6,
VAR16 ,
VAR5
);
output VAR8 ;
input VAR9 ;
input VAR11 ;
input VAR2 ;
input VAR4 ;
input VAR3;
input VAR6;
input VAR16 ;
input VAR5 ;
wire VAR7 ;
wire VAR10 ;
wire VAR17;
nand VAR12 (VAR7 , VAR4, VAR2 );
or VAR15 (VAR10 , VAR11, VAR9, VAR7 );
VAR14 VAR1 (... | apache-2.0 |
vad-rulezz/megabot | minsoc/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v | 9,172 | module MODULE1 (
VAR46, VAR40,
VAR15, VAR11, VAR17, VAR20, VAR16, VAR19,
VAR29, VAR13, VAR4
);
parameter VAR21 = 13; localparam VAR1 = 11; localparam VAR45 = (1<<(VAR21-VAR1));
input VAR46;
input VAR40;
input [31:0] VAR15;
output [31:0] VAR11;
input [31:0] VAR17;
input [3:0] VAR20;
input VAR16;
input VAR19;
input VAR29... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.blackbox.v | 1,437 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR1 ,
VAR2 ,
VAR4,
VAR7 ,
VAR3
);
output VAR6 ;
input VAR5 ;
input VAR1 ;
input VAR2 ;
input VAR4;
input VAR7 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ai/sky130_fd_sc_ls__o21ai.functional.pp.v | 2,010 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR10 ,
VAR1 ,
VAR6,
VAR13,
VAR14 ,
VAR7
);
output VAR4 ;
input VAR5 ;
input VAR10 ;
input VAR1 ;
input VAR6;
input VAR13;
input VAR14 ;
input VAR7 ;
wire VAR8 ;
wire VAR16 ;
wire VAR9;
or VAR15 (VAR8 , VAR10, VAR5 );
nand VAR11 (VAR16 , VAR1, VAR8 );
VAR2 VAR3 (VAR9, VAR16, VAR6, VAR13);... | apache-2.0 |
AloriumTechnology/XLR8Pong | extras/rtl/vid_score.v | 4,529 | module MODULE1 #(parameter VAR2 = 114 )
(clk,
VAR8,
VAR6,
VAR4,
VAR7,
VAR5,
VAR1
);
localparam VAR3 = VAR2;
localparam VAR9 = VAR2+3;
input clk;
input VAR8;
input wire[3:0] VAR6;
input wire VAR4;
input wire[8:0] VAR7;
input wire[7:0] VAR5;
output reg VAR1;
always @(posedge clk) begin
if(~VAR8) begin
VAR1 <= 0; end else... | lgpl-3.0 |
pdaxrom/p601zero | tvout.v | 1,329 | module MODULE1 (
input VAR3,
input rst,
output reg [8:0] VAR8,
output reg [8:0] VAR5,
output wire VAR1,
output wire VAR6,
output wire VAR4
);
wire VAR10 = (VAR8 < 37) ? 1'b0 : 1'b1;
wire VAR9 = ((VAR5 >= 5) & (VAR5 < 309)) ? 1'b0 : 1'b1;
reg VAR2;
reg VAR7;
always @ (posedge VAR3) begin
if (rst) begin
VAR8 <= 0;
VAR5 <... | gpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/adv_debug_sys/Hardware/jtag/cells/rtl/verilog/ControlCell.v | 3,621 | module MODULE1( VAR3, VAR8, VAR12, VAR9, VAR2, VAR11, VAR10, VAR4, VAR6);
input VAR3;
input VAR8;
input VAR12;
input VAR9;
input VAR2;
input VAR11;
input VAR10;
reg VAR1;
output VAR4;
output VAR6;
reg VAR4;
reg VAR5;
wire VAR7 = VAR12? VAR3 : VAR8;
always @ (posedge VAR10)
begin
if(VAR12 | VAR9)
VAR1<=VAR7;
end
always ... | mit |
Digilent/vivado-library | ip/Pmods/PmodWIFI_v1_0/src/PmodWIFI.v | 20,605 | module MODULE1
(VAR100,
VAR125,
VAR267,
VAR255,
VAR247,
VAR50,
VAR215,
VAR119,
VAR45,
VAR65,
VAR171,
VAR12,
VAR276,
VAR156,
VAR19,
VAR1,
VAR220,
VAR278,
VAR228,
VAR129,
VAR109,
VAR95,
VAR219,
VAR259,
VAR121,
VAR249,
VAR98,
VAR90,
VAR54,
VAR177,
VAR213,
VAR80,
VAR79,
VAR141,
VAR28,
VAR204,
VAR93,
VAR218,
VAR197,
VAR251,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15_1.v | 2,163 | module MODULE2 (
VAR5 ,
VAR3 ,
VAR4,
VAR2,
VAR8 ,
VAR6
);
output VAR5 ;
input VAR3 ;
input VAR4;
input VAR2;
input VAR8 ;
input VAR6 ;
VAR1 VAR7 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
supply1 VAR4;
supply0 VAR2;... | apache-2.0 |
cpulabs/mist1032sa | src/core/execute/old_execute/mul.v | 2,755 | module MODULE2(
input [3 : 0] VAR13,
input [3 : 0] VAR1,
output [7 : 0] VAR15);
assign VAR15 = ((VAR13[0])? VAR1 : 7'h00) + ((VAR13[1])? VAR1 << 1 : 7'h00) + ((VAR13[2])? VAR1 << 2 : 7'h00) + ((VAR13[3])? VAR1 << 3 : 7'h00);
endmodule
module MODULE1(
input [31 : 0] VAR13,
input [31 : 0] VAR1,
output [63 : 0] VAR6,
outp... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbp/sky130_fd_sc_hs__dlrbp.blackbox.v | 1,370 | module MODULE1 (
VAR3,
VAR7 ,
VAR5 ,
VAR6 ,
VAR2
);
input VAR3;
input VAR7 ;
input VAR5 ;
output VAR6 ;
output VAR2 ;
supply1 VAR4;
supply0 VAR1;
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_ic_top.v | 12,220 | module MODULE1(
clk, rst,
VAR41, VAR16, VAR6, VAR34, VAR70, VAR33, VAR37,
VAR22, VAR39, VAR56,
VAR55,
VAR42, VAR35, VAR20,
VAR19, VAR14,
VAR28, VAR45, VAR18, VAR57, VAR50,
VAR7, VAR25, VAR43,
VAR11, VAR48, VAR36
);
parameter VAR62 = VAR2;
input clk;
input rst;
output [VAR62-1:0] VAR41;
output [31:0] VAR16;
output VAR6;... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_3.behavioral.pp.v | 1,167 | module MODULE1( VAR3, VAR2, VAR1, VAR5 );
input VAR3;
inout VAR1, VAR5;
output VAR2;
VAR7 VAR4(.VAR3(VAR3),.VAR2(VAR2),.VAR1(VAR1),.VAR5(VAR5));
VAR7 VAR6(.VAR3(VAR3),.VAR2(VAR2),.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1.behavioral.v | 1,440 | module MODULE1 (
VAR5,
VAR2
);
output VAR5;
input VAR2;
supply1 VAR6;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR7 ;
wire VAR9;
not VAR8 (VAR9, VAR2 );
buf VAR4 (VAR5 , VAR9 );
endmodule | apache-2.0 |
karshan/fpga-rgbmatrix | src/mojo_top.v | 2,187 | module MODULE1(
input clk,
input VAR35,
input VAR14,
output[7:0]VAR31,
output VAR8,
input VAR24,
input VAR22,
input VAR30,
output [3:0] VAR26,
input VAR28, output VAR39, input VAR43,
output VAR27,
output VAR9,
output VAR40,
output VAR32,
output VAR18,
output VAR33,
output VAR23,
output VAR12,
output VAR17,
output VAR4,... | gpl-3.0 |
Jawanga/ece385final | usb_system/synthesis/submodules/altera_avalon_st_clock_crosser.v | 5,155 | module MODULE1(
VAR8,
VAR4,
VAR12,
VAR1,
VAR13,
VAR6,
VAR32,
VAR14,
VAR19,
VAR24
);
parameter VAR20 = 1;
parameter VAR23 = 8;
parameter VAR10 = 2;
parameter VAR18 = 2;
parameter VAR27 = 1;
localparam VAR11 = VAR20 * VAR23;
input VAR8;
input VAR4;
output VAR12;
input VAR1;
input [VAR11-1:0] VAR13;
input VAR6;
input VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfsbp/sky130_fd_sc_lp__dfsbp.pp.symbol.v | 1,412 | module MODULE1 (
input VAR3 ,
output VAR8 ,
output VAR2 ,
input VAR6,
input VAR9 ,
input VAR4 ,
input VAR7 ,
input VAR1 ,
input VAR5
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_rank_timer.v | 112,565 | module MODULE1 #
( parameter
VAR60 = 2,
VAR106 = 4,
VAR162 = "VAR120",
VAR153 = 1,
VAR173 = 1,
VAR15 = 4,
VAR192 = 2,
VAR160 = 0,
VAR39 = 0,
VAR212 = 0,
VAR69 = 0,
VAR72 = 5,
VAR44 = 0,
VAR30 = 0,
VAR6 = 0,
VAR119 = 0,
VAR205 = 0,
VAR167 = 0,
VAR146 = 0,
VAR194 = 0,
VAR157 = 0,
VAR17 = 0,
VAR190 = 0,
VAR102 = 0
)
(
VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfsbp/sky130_fd_sc_ls__sdfsbp.behavioral.pp.v | 2,949 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR20 ,
VAR23 ,
VAR3 ,
VAR4 ,
VAR26,
VAR32 ,
VAR10 ,
VAR27 ,
VAR28
);
output VAR5 ;
output VAR6 ;
input VAR20 ;
input VAR23 ;
input VAR3 ;
input VAR4 ;
input VAR26;
input VAR32 ;
input VAR10 ;
input VAR27 ;
input VAR28 ;
wire VAR15 ;
wire VAR18 ;
wire VAR9 ;
reg VAR29 ;
wire VAR25 ;
wire ... | apache-2.0 |
marqs85/ossc | rtl/char_rom.v | 6,591 | module MODULE1 (
address,
VAR8,
VAR7);
input [7:0] address;
input VAR8;
output [63:0] VAR7;
tri1 VAR8;
wire [63:0] VAR15;
wire [63:0] VAR7 = VAR15[63:0];
VAR56 VAR25 (
.VAR40 (address),
.VAR21 (VAR8),
.VAR26 (VAR15),
.VAR35 (1'b0),
.VAR9 (1'b0),
.VAR30 (1'b1),
.VAR4 (1'b0),
.VAR42 (1'b0),
.VAR31 (1'b1),
.VAR37 (1'b1),
... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/ac97/rtl/ac97_framer.v | 4,838 | module MODULE1(
input VAR11,
input VAR2,
input VAR14,
output VAR3,
output reg VAR13,
output reg VAR12,
input en,
output reg VAR16,
input VAR10,
input [19:0] addr,
input VAR7,
input [19:0] VAR6,
input VAR18,
input [19:0] VAR9,
input VAR8,
input [19:0] VAR17
);
reg [7:0] VAR15;
reg VAR4;
always @(*) begin
case(VAR15)
8'd... | lgpl-3.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkBranch_Predictor.v | 24,978 | module MODULE1(VAR129,
VAR116,
VAR76,
VAR83,
VAR121,
VAR134,
VAR87,
VAR66,
VAR101,
VAR41,
VAR33,
VAR47,
VAR12,
VAR7,
VAR25,
VAR68);
input VAR129;
input VAR116;
input VAR76;
output VAR83;
input [63 : 0] VAR121;
input VAR134;
output VAR87;
input VAR66;
input [31 : 0] VAR101;
output [63 : 0] VAR41;
input [63 : 0] VAR33;
i... | apache-2.0 |
BigEd/beeb816 | pcb/beeb816_mk2b.v | 11,898 | module MODULE1();
supply0 VAR279;
supply1 VAR259;
supply1 VAR323;
supply1 VAR5;
supply1 VAR172;
wire VAR233, VAR103, VAR4, VAR249, VAR228, VAR235, VAR49, VAR174;
wire VAR92, VAR39, VAR77, VAR170, VAR197, VAR113, VAR248, VAR200;
wire VAR223, VAR7, VAR291, VAR110, VAR270, VAR184, VAR158, VAR57;
wire VAR313, VAR315, VAR10... | lgpl-2.1 |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.cache/ip/985f4b7c6650e49d/design_1_processing_system7_0_0_stub.v | 5,608 | module MODULE1(VAR18, VAR63, VAR55, VAR39,
VAR71, VAR13, VAR16, VAR6, VAR61, VAR77, VAR34,
VAR40, VAR15, VAR17, VAR51,
VAR50, VAR53, VAR47, VAR57,
VAR25, VAR72, VAR23, VAR60, VAR43,
VAR54, VAR7, VAR31, VAR8,
VAR64, VAR69, VAR24, VAR4, VAR56,
VAR5, VAR11, VAR37, VAR20, VAR9,
VAR44, VAR62, VAR33, VAR49, VAR19,
VAR35, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux4/sky130_fd_sc_hs__mux4.pp.symbol.v | 1,343 | module MODULE1 (
input VAR1 ,
input VAR5 ,
input VAR4 ,
input VAR6 ,
output VAR8 ,
input VAR9 ,
input VAR3 ,
input VAR2,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapmet1/sky130_fd_sc_ls__tapmet1.behavioral.pp.v | 1,204 | module MODULE1 (
VAR2,
VAR3,
VAR1 ,
VAR4
);
input VAR2;
input VAR3;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dmac_v1_00_a/hdl/verilog/axi_register_slice.v | 4,385 | module MODULE1 (
input clk,
input VAR2,
input VAR9,
output VAR20,
input [VAR6-1:0] VAR7,
output VAR15,
input VAR5,
output [VAR6-1:0] VAR14
);
parameter VAR6 = 32;
parameter VAR13 = 0;
parameter VAR11 = 0;
wire [VAR6-1:0] VAR18;
wire VAR12;
wire VAR19;
wire [VAR6-1:0] VAR3;
wire VAR8;
wire VAR10;
generate if (VAR13 == 1... | mit |
xcthulhu/periphondemand | src/library/components/uart16550/hdl/uart_wb.v | 11,445 | module MODULE1 (clk, VAR6,
VAR22, VAR2, VAR17, VAR10, VAR9,
VAR26, VAR7, VAR15, VAR18, VAR5, VAR12, VAR19,
VAR21, VAR16 );
input clk;
input VAR6;
input VAR22;
input VAR2;
input VAR17;
input [3:0] VAR19;
input [VAR8-1:0] VAR9;
input [7:0] VAR7; output [7:0] VAR15;
reg [7:0] VAR15;
wire [7:0] VAR7;
reg [7:0] VAR13;
reg [... | lgpl-2.1 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/butterfly1.v | 15,885 | module MODULE1(
VAR77,
VAR37,
VAR30,
VAR34,
VAR14,
VAR58,
VAR35,
VAR22,
VAR61,
VAR23,
VAR85,
VAR28,
VAR7,
VAR47,
VAR51,
VAR72,
VAR64,
VAR80,
VAR25,
VAR59,
VAR41,
VAR8,
VAR62,
VAR29,
VAR50,
VAR81,
VAR39,
VAR63,
VAR4,
VAR90,
VAR83,
VAR3,
VAR2,
VAR40,
o0 ,
o1 ,
o2 ,
o3 ,
o4 ,
o5 ,
o6 ,
o7 ,
VAR24 ,
VAR57 ,
o10,
o11,
o12,
... | gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_1/hdl/verilog/feedforward_p_uOut.v | 1,713 | module MODULE2 (VAR8, VAR1, VAR13, VAR11, VAR14, VAR4, VAR2, VAR7, clk);
parameter VAR6 = 64;
parameter VAR17 = 8;
parameter VAR16 = 140;
input[VAR17-1:0] VAR8;
input VAR1;
input[VAR6-1:0] VAR13;
input VAR11;
output reg[VAR6-1:0] VAR14;
input[VAR17-1:0] VAR4;
input VAR2;
output reg[VAR6-1:0] VAR7;
input clk;
reg [VAR6-... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/SINGLE/Exp_Operation_syn.v | 10,897 | module MODULE9 ( VAR46, VAR79, VAR106, VAR126, VAR7 );
input [8:0] VAR46;
input [8:0] VAR79;
output [8:0] VAR126;
input VAR106;
output VAR7;
wire VAR89, VAR90;
wire [8:1] VAR116;
VAR8 VAR144 ( .VAR46(VAR46[7]), .VAR79(VAR79[7]), .VAR41(VAR116[7]), .VAR7(VAR126[8]), .VAR39(VAR126[7])
);
VAR8 VAR28 ( .VAR46(VAR46[1]), .V... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_buf_pdr.v | 1,824 | module MODULE1(
VAR2,
VAR1
);
output [4:0] VAR2;
input [4:0] VAR1;
assign VAR2 = ~VAR1;
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_4.behavioral.v | 3,431 | module MODULE1( VAR9, VAR4, VAR6, VAR1, VAR5, VAR7 );
input VAR6, VAR9, VAR4, VAR7, VAR5;
output VAR1;
VAR2 VAR8(.VAR9(VAR9),.VAR4(VAR4),.VAR6(VAR6),.VAR1(VAR1),.VAR5(VAR5),.VAR7(VAR7));
VAR2 VAR3(.VAR9(VAR9),.VAR4(VAR4),.VAR6(VAR6),.VAR1(VAR1),.VAR5(VAR5),.VAR7(VAR7)); | apache-2.0 |
hoangt/NOCulator | hring/hw/buffered/src/tc_node_mac.v | 58,665 | module MODULE1
(clk, reset, address, VAR15, VAR22, VAR170,
VAR129, VAR173, VAR27, VAR79, VAR82,
VAR144, VAR210, VAR108, VAR64, VAR178, VAR89);
parameter VAR81 = 8;
parameter VAR140 = 4;
parameter VAR127 = 2;
parameter VAR134 = 2;
localparam VAR199 = VAR127 * VAR134;
localparam VAR35 = VAR33(VAR199);
parameter VAR18 = 1... | mit |
aselectroworks/HDL | rtl/verilog/tdm_to_i2s_converter.v | 4,633 | module MODULE1(
VAR17,
VAR12,
VAR4,
VAR5,
VAR7,
VAR11,
VAR16,
VAR15
);
input VAR17;
input VAR12;
input VAR4;
input VAR5;
output VAR7;
output VAR11;
output VAR16;
output reg [3:0] VAR15;
assign rst = VAR17;
reg VAR14;
always @ (posedge VAR12 or posedge rst) begin
if(rst) begin
VAR14 <= 1'b0;
end
else begin
VAR14 <= VAR4... | bsd-3-clause |
bigeagle/riffa | fpga/riffa_hdl/translation_xilinx.v | 10,699 | module MODULE1
parameter VAR44 = 256
)
(
input VAR33,
input VAR29,
input [VAR44-1:0] VAR30,
input [(VAR44/8)-1:0] VAR83,
input VAR69,
input VAR38,
output VAR76,
input [VAR11-1:0] VAR9,
output VAR14,
output VAR78,
output [VAR44-1:0] VAR57,
output [(VAR44/8)-1:0] VAR58,
output VAR35,
output VAR63,
input VAR24,
output [VA... | bsd-3-clause |
m-labs/milkymist | cores/tmu2/rtl/tmu2_pixout.v | 3,057 | module MODULE1 #(
parameter VAR6 = 26
) (
input VAR10,
input VAR20,
output reg VAR12,
input VAR15,
output reg VAR1,
input [VAR6-5-1:0] VAR7,
input [15:0] VAR11,
input [255:0] VAR9,
output reg [VAR6-1:0] VAR8,
output reg VAR2,
input VAR13,
output reg [7:0] VAR19,
output reg [63:0] VAR16
);
reg [15:0] VAR21;
reg [255:0] ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3/sky130_fd_sc_hdll__or3.pp.symbol.v | 1,282 | module MODULE1 (
input VAR8 ,
input VAR7 ,
input VAR4 ,
output VAR2 ,
input VAR5 ,
input VAR3,
input VAR1,
input VAR6
);
endmodule | apache-2.0 |
mballance/wb_dma | rtl/wb_dma_top.v | 32,434 | module MODULE1(VAR441, VAR64,
VAR58, VAR344, VAR354, VAR251, VAR113, VAR307,
VAR415, VAR55, VAR339, VAR323,
VAR397, VAR22, VAR133, VAR373, VAR309, VAR281,
VAR352, VAR431, VAR224, VAR51,
VAR4, VAR340, VAR293, VAR54, VAR29, VAR283,
VAR304, VAR368, VAR205, VAR310,
VAR278, VAR261, VAR117, VAR447, VAR69, VAR81,
VAR34, VAR19... | apache-2.0 |
Elphel/x353 | sensor/histogram353.v | 15,530 | module MODULE1 (VAR62, VAR48, VAR66, VAR80, VAR70, VAR30,
VAR20, VAR53, VAR29, VAR51, VAR10, VAR7, VAR27 );
input VAR62;
input VAR48;
input VAR66;
input VAR80;
input VAR70;
input [ 2:0] VAR30;
output [31:0] VAR20;
input [15:0] VAR53;
input VAR29;
input VAR51;
input [15:0] VAR10;
input VAR7;
input [ 1:0] VAR27;
wire [17... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_tagdp_ctl.v | 48,490 | module MODULE1(
VAR160, VAR181, VAR76,
VAR21, VAR101, VAR239,
VAR151, VAR33, VAR56,
VAR212, VAR89,
VAR87, VAR86, VAR36,
VAR88, VAR30, VAR51, VAR104,
VAR138, VAR74, VAR128,
VAR150, VAR37, VAR16,
VAR227, VAR1, VAR32,
VAR190, VAR63, VAR124,
VAR69, VAR231, VAR156, VAR244,
VAR184, VAR115, VAR64,
VAR166, VAR234, VAR154, VAR1... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_4.behavioral.v | 1,262 | module MODULE1( VAR7, VAR3, VAR4, VAR6 );
input VAR6, VAR7, VAR4;
output VAR3;
VAR2 VAR5(.VAR7(VAR7),.VAR3(VAR3),.VAR4(VAR4),.VAR6(VAR6));
VAR2 VAR1(.VAR7(VAR7),.VAR3(VAR3),.VAR4(VAR4),.VAR6(VAR6)); | apache-2.0 |
PeterMagnusson/modexp | src/rtl/blockmem_rw32_r256.v | 7,702 | module MODULE1(
input wire clk,
input wire VAR47,
input wire [07 : 0] VAR12,
input wire [31 : 0] VAR40,
output wire [31 : 0] VAR5,
input wire [04 : 0] VAR23,
output wire [255 : 0] VAR37
);
reg [31 : 0] VAR2 [0 : 31];
reg [31 : 0] VAR17 [0 : 31];
reg [31 : 0] VAR31 [0 : 31];
reg [31 : 0] VAR8 [0 : 31];
reg [31 : 0] VAR2... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3/sky130_fd_sc_hd__and3_2.v | 2,164 | module MODULE2 (
VAR10 ,
VAR4 ,
VAR5 ,
VAR7 ,
VAR2,
VAR6,
VAR9 ,
VAR8
);
output VAR10 ;
input VAR4 ;
input VAR5 ;
input VAR7 ;
input VAR2;
input VAR6;
input VAR9 ;
input VAR8 ;
VAR1 VAR3 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/dst.v | 3,955 | module MODULE1(
clk,
rst,
VAR20,
VAR21,
VAR7,
VAR8,
VAR1,
o0,
o1,
o2,
o3
);
input clk;
input rst;
input VAR20;
input signed [18:0] VAR21;
input signed [18:0] VAR7;
input signed [18:0] VAR8;
input signed [18:0] VAR1;
output reg signed [27:0] o0;
output reg signed [27:0] o1;
output reg signed [27:0] o2;
output reg signed... | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/old/e_transmit/hdl/e_tx_io.v | 9,811 | module MODULE1 (
VAR31, VAR81, VAR17, VAR70, VAR101, VAR58,
VAR53, VAR28,
reset, VAR9, VAR66, VAR90, VAR95,
VAR29, VAR31, VAR65, VAR21, VAR17, VAR101,
VAR57, VAR87, VAR23, VAR26
);
parameter VAR39 = "VAR71";
output VAR31, VAR81; input reset;
input VAR9;
output VAR17, VAR70; output [7:0] VAR101, VAR58;
input VAR66, VAR9... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor2/sky130_fd_sc_hd__xnor2.pp.symbol.v | 1,304 | module MODULE1 (
input VAR5 ,
input VAR3 ,
output VAR4 ,
input VAR2 ,
input VAR7,
input VAR1,
input VAR6
);
endmodule | apache-2.0 |
pdaxrom/p601zero | uart_tx.v | 3,129 | module MODULE1 #
(
parameter VAR4 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR4-1:0] VAR12,
input wire VAR5,
output wire VAR7,
output wire VAR13,
output wire VAR9,
input wire [15:0] VAR6
);
reg VAR1 = 0;
reg VAR10 = 1;
reg VAR11 = 0;
reg [VAR4:0] VAR8 = 0;
reg [18:0] VAR2 = 0;
reg [3:0] VAR3 = 0;
assign VAR7... | gpl-3.0 |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlslice_0_1/RAT_xlslice_0_1_stub.v | 1,235 | module MODULE1(VAR2, VAR1)
;
input [9:0]VAR2;
output [7:0]VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3b/sky130_fd_sc_lp__and3b.blackbox.v | 1,295 | module MODULE1 (
VAR2 ,
VAR3,
VAR4 ,
VAR8
);
output VAR2 ;
input VAR3;
input VAR4 ;
input VAR8 ;
supply1 VAR7;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_longpwbck.v | 6,448 | module MODULE1(
input VAR36, output VAR12, input [VAR14-1:0] VAR39,
input [VAR40 -1:0] VAR30,
input VAR27 , input VAR41 ,
input [VAR25 -1:0] VAR29,
input VAR50,
input VAR43,
output VAR28, input VAR33, output [VAR46-1:0] VAR16,
output [5-1:0] VAR15,
output [VAR10 -1:0] VAR7,
output VAR24,
output VAR4,
input VAR31,
outpu... | apache-2.0 |
rossmacarthur/verilog-utilities | pmodda4/PmodDA4_Control.v | 1,835 | module MODULE1 (
input clk,
input rst,
input [11:0] VAR9, output reg VAR5, output VAR2, output VAR3 );
localparam VAR11 = 3'd0,
VAR6 = 3'd1,
VAR7 = 3'd2,
VAR1 = 3'd3,
VAR8 = 3'd4;
wire [31:0] VAR4;
reg [2:0] state;
reg [4:0] VAR10;
assign VAR4 = ((state == VAR6) || (state == VAR7)) ? {8'h8, 24'h1} : {12'h3F, VAR9, 8'h0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4bb/sky130_fd_sc_ms__and4bb.pp.blackbox.v | 1,351 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR4 ,
VAR1 ,
VAR6 ,
VAR9,
VAR3,
VAR8 ,
VAR7
);
output VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR1 ;
input VAR6 ;
input VAR9;
input VAR3;
input VAR8 ;
input VAR7 ;
endmodule | apache-2.0 |
Madh93/scpu | modules/printvga.v | 1,955 | module MODULE1(input wire clk, reset, VAR6,
input wire [15:0] VAR2,
output wire [7:0] VAR5, VAR4,
output wire VAR3);
integer VAR1; | mit |
bkboggy/MIPS | PIPELINE.v | 4,390 | module MODULE1(input clk);
wire [31:0] VAR29;
wire [31:0] VAR52;
wire [1:0] VAR41;
wire [2:0] VAR78;
wire [3:0] VAR17;
wire [31:0] VAR9;
wire [31:0] VAR82;
wire [31:0] VAR25;
wire [31:0] VAR57;
wire [4:0] VAR56;
wire [4:0] VAR74;
wire [4:0] VAR18;
wire [1:0] VAR62;
wire [2:0] VAR67;
wire [31:0] VAR42;
wire VAR40;
wire ... | mit |
trivoldus28/pulsarch-verilog | verif/env/cmp/err_inject.v | 265,960 | module MODULE1 ();
task VAR53;
input [63:0] VAR78;
input [7:0] VAR131;
output VAR115;
begin
VAR115 = VAR78[0] ^ VAR78[1] ^ VAR78[2] ^ VAR78[3] ^ VAR78[4] ^ VAR78[5] ^ VAR78[6] ^ VAR78[7]
^ VAR78[8] ^ VAR78[9] ^ VAR78[10] ^ VAR78[11] ^ VAR78[12] ^ VAR78[13] ^ VAR78[14] ^ VAR78[15]
^ VAR78[16] ^ VAR78[17] ^ VAR78[18] ^ V... | gpl-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_36.v | 26,367 | module MODULE5 (
clk,
reset,
VAR57,
VAR32,
VAR106,
VAR193,
VAR67
);
parameter VAR85 = 18;
parameter VAR121 = 36;
parameter VAR74 = 18;
localparam VAR167 = 43;
input clk;
input reset;
input VAR57;
input VAR32;
input [VAR85-1:0] VAR106; output VAR193;
output [VAR85-1:0] VAR67;
localparam VAR14 = 18; localparam VAR145 = 3... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_mc_current_monitor/dec256sinc24b.v | 6,497 | module MODULE1
(
input VAR18,
input VAR6,
input VAR17,
output VAR15, output reg [15:0] VAR2 );
reg [23:0] VAR16;
reg [23:0] VAR11;
reg [23:0] VAR5;
reg [23:0] VAR4;
reg [23:0] VAR7;
reg [23:0] VAR14;
reg [23:0] VAR13;
reg [23:0] VAR8;
reg [23:0] VAR1;
reg [23:0] VAR3;
reg [23:0] VAR10;
reg [7:0] VAR12;
reg VAR9;
assign... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/IPE_IF.v | 35,766 | module MODULE1(
clk,
VAR130,
VAR139,
VAR252,
VAR344,
VAR245,
VAR66,
VAR77,
reset,
VAR136,
VAR71,
VAR184,
VAR54,
VAR109,
VAR293,
VAR62,
VAR190,
VAR355,
VAR64,
VAR141,
VAR85,
VAR280,
VAR168,
VAR29,
VAR176,
VAR178,
VAR96,
VAR159,
VAR234,
VAR288,
VAR319,
VAR35,
VAR146,
VAR132,
VAR22,
VAR263,
VAR228,
VAR205,
VAR187,
VAR37,
... | apache-2.0 |
mahdienan/Spongent | verilog/Absorb.v | 2,672 | module MODULE1(VAR18, VAR17, clk, rst, en, VAR3);
input [263:0] VAR18;
input rst;
input clk;
input en;
output reg[263:0] VAR17;
output reg VAR3;
reg VAR15;
reg [15:0] VAR1, VAR2;
reg [31:0] VAR7;
reg [263:0] VAR4;
reg VAR14;
reg [15:0] VAR11;
reg [263:0] VAR16;
reg VAR8;
wire [263:0] VAR13;
wire [15:0] VAR12;
wire VAR5... | gpl-2.0 |
bigeagle/riffa | fpga/riffa_hdl/shiftreg.v | 3,169 | module MODULE1
parameter VAR8=10,
parameter VAR1=32
)
(
input VAR7,
input VAR9,
input [VAR1-1:0] VAR6,
output [(VAR8+1)*VAR1-1:0] VAR5
);
wire [(VAR8+1)*VAR1-1:0] VAR4;
reg [VAR1-1:0] VAR10[VAR8:0];
assign VAR4[(VAR1*0)+:VAR1] = VAR6;
always @(posedge VAR7) begin
VAR10[0] <= VAR6;
end
genvar VAR2;
generate
for (VAR2 = ... | bsd-3-clause |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_static_top.v | 16,735 | module MODULE1 #
(
parameter VAR50 = 32 ,
parameter VAR92 = 1 ,
parameter VAR36 = 1 ,
parameter VAR30 = 1 ,
parameter VAR66 = 1 ,
parameter VAR96 = 32 ,
parameter VAR24 = 32 ,
parameter VAR47 = 32'h12A00000 ,
parameter VAR5 = 32'h13A00000 ,
parameter VAR20 = 32'h12A00FFF,
parameter VAR90 = 32'h13A00FFF,
parameter VAR55... | gpl-3.0 |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ip/image_processing_2d_design_auto_pc_0_1/synth/image_processing_2d_design_auto_pc_0.v | 12,869 | module MODULE1 (
VAR31,
VAR49,
VAR43,
VAR17,
VAR61,
VAR99,
VAR78,
VAR100,
VAR58,
VAR70,
VAR102,
VAR22,
VAR93,
VAR101,
VAR4,
VAR84,
VAR105,
VAR94,
VAR44,
VAR8,
VAR71,
VAR34,
VAR76,
VAR45,
VAR32,
VAR1,
VAR18,
VAR21,
VAR12,
VAR15,
VAR2,
VAR90,
VAR97,
VAR56,
VAR73,
VAR98,
VAR63,
VAR106,
VAR64,
VAR28,
VAR20,
VAR110,
VAR65,
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufbuf/sky130_fd_sc_hd__bufbuf.symbol.v | 1,258 | module MODULE1 (
input VAR2,
output VAR4
);
supply1 VAR3;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
fisherdj/avgai | src/SRAM.v | 1,527 | module MODULE1(input clk, read, write,
input [7:0] VAR7, VAR8, input [11:0] VAR1,
output [11:0] VAR4, output reg VAR2,
output reg [11:0] VAR10);
parameter VAR5 = 200, VAR6 = 150;
reg [11:0] VAR9[VAR5*VAR6-1:0];
reg [11:0] VAR3;
assign VAR4 = ~VAR3;
always @(posedge clk) begin
if (read)
VAR3 <= VAR9[VAR8*VAR5 + VAR7];
e... | gpl-3.0 |
alan4186/ParCNN | DE2_115_CAMERA/v/I2C_Controller.v | 3,918 | module MODULE1 (
VAR5,
VAR3, VAR17, VAR15, VAR1, VAR16, VAR10, VAR11, VAR2
);
input VAR5;
input [31:0]VAR15;
input VAR1;
input VAR2;
input VAR10;
inout VAR17;
output VAR3;
output VAR16;
output VAR11;
reg VAR4;
reg VAR18;
reg VAR16;
reg [31:0]VAR14;
reg [6:0]VAR12;
wire VAR3=VAR18 | ( ((VAR12 >= 4) & (VAR12 <=39))? ~VAR... | mit |
EliasLuiz/TCC | Leon3/lib/micron/sdram/mobile_sdr.v | 95,562 | module MODULE1 (
clk ,
VAR33 ,
addr ,
VAR139 ,
VAR43 ,
VAR8 ,
VAR152 ,
VAR15 ,
VAR53 ,
VAR41
);
parameter VAR106 = 13; parameter VAR23 = 13; parameter VAR144 = 32; parameter VAR30 = 4; parameter VAR56 = 9; parameter VAR19 = 2; else VAR91 VAR130
parameter VAR106 = 13; parameter VAR23 = 13; parameter VAR144 = 16; paramet... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3b/sky130_fd_sc_ms__nand3b_2.v | 2,229 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR7 ,
VAR5 ,
VAR1,
VAR4,
VAR3 ,
VAR8
);
output VAR2 ;
input VAR9 ;
input VAR7 ;
input VAR5 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR8 ;
VAR6 VAR10 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 (... | apache-2.0 |
golfit/QcmPhaseDelayBoard | PhaseDelaySerialInMain.v | 6,614 | module MODULE1(clk, VAR13, VAR6, VAR7);
parameter VAR5=6; parameter VAR4=9; parameter VAR2=VAR5+VAR4;
input [VAR5-1:0] VAR13;
input clk, VAR6;
output wire VAR7;
wire [VAR4-1:0] VAR11;
wire [(VAR5-1):0] VAR16;
reg [(VAR5-1):0] VAR1;
reg [VAR4-1:0] VAR15;
reg [VAR2-1:0] VAR14;
counter VAR8(clk,VAR6,VAR11);
VAR10 VAR9(cl... | mit |
bangonkali/quartus-sockit | pll_vga/pll_vga_0002.v | 2,068 | module MODULE1(
input wire VAR17,
input wire rst,
output wire VAR68,
output wire VAR58
);
VAR27 #(
.VAR31("false"),
.VAR10("50.0 VAR39"),
.VAR19("VAR13"),
.VAR30(1),
.VAR57("25.0 VAR39"),
.VAR26("0 VAR34"),
.VAR63(50),
.VAR38("0 VAR39"),
.VAR46("0 VAR34"),
.VAR14(50),
.VAR15("0 VAR39"),
.VAR18("0 VAR34"),
.VAR20(50),
.... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_auto_pc_0/synth/zybo_zynq_design_auto_pc_0.v | 14,706 | module MODULE1 (
VAR67,
VAR91,
VAR46,
VAR114,
VAR60,
VAR44,
VAR24,
VAR34,
VAR76,
VAR112,
VAR70,
VAR7,
VAR52,
VAR38,
VAR85,
VAR16,
VAR12,
VAR71,
VAR40,
VAR89,
VAR108,
VAR80,
VAR17,
VAR42,
VAR50,
VAR23,
VAR51,
VAR1,
VAR37,
VAR83,
VAR107,
VAR45,
VAR55,
VAR57,
VAR58,
VAR94,
VAR79,
VAR3,
VAR101,
VAR59,
VAR18,
VAR73,
VAR110,... | mit |
bluespec/Flute | src_SSITH_P2/Verilog_RTL/mkRISCV_MBox.v | 31,300 | module MODULE1(VAR176,
VAR116,
VAR77,
VAR43,
VAR97,
VAR3,
VAR42,
VAR124,
VAR75,
VAR71,
VAR36,
VAR96,
VAR94,
VAR55,
valid,
word);
input VAR176;
input VAR116;
input [3 : 0] VAR77;
input VAR43;
output VAR97;
input VAR3;
output VAR42;
input VAR124;
output VAR75;
input VAR71;
input [2 : 0] VAR36;
input [63 : 0] VAR96;
input... | apache-2.0 |
OSCES/OSCES-FRAMEWORK | src/bsp/fpga/src/VgaRenderer.v | 2,261 | module MODULE1
(
input VAR3 ,
input wire [10:0] VAR2 ,
input wire [9:0] VAR17 ,
input wire VAR22,
input wire VAR15,
input wire [ 7:0] VAR1 ,
output wire [18:0] VAR13 ,
output wire VAR9 ,
output wire VAR11 ,
output wire VAR16 ,
output wire [ 4:0] VAR8 ,
output wire [ 4:0] VAR19 ,
output wire [ 4:0] VAR6
);
localparam VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.blackbox.v | 1,437 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR5 ,
VAR4 ,
VAR3,
VAR6 ,
VAR1
);
output VAR2 ;
input VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR3;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdaptevaLib/elink-gold/fpgacfg.v | 21,876 | module MODULE1 (
VAR137, VAR112, VAR20, VAR4,
VAR99, VAR58, VAR27,
VAR66, VAR135, VAR31,
VAR118, VAR133, VAR115, VAR136,
VAR38, VAR68, VAR19, VAR100,
VAR91, VAR131, VAR23, VAR35,
VAR64,
VAR76, VAR30, reset, VAR81, VAR55,
VAR96, VAR29, VAR36,
VAR129, VAR134, VAR25,
VAR60, VAR119, VAR113, VAR17,
VAR120, VAR79, VAR93, VAR... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/Booth_Multipliers-master/Src/Booth_Multiplier.v | 5,224 | module MODULE1 #(
parameter VAR1 = 4 )(
input VAR3, input VAR8,
input VAR5, input [(2**VAR1 - 1):0] VAR12, input [(2**VAR1 - 1):0] VAR11, output reg VAR6, output reg [(2**(VAR1+1) - 1):0] VAR7 );
reg [2**VAR1:0] VAR10; reg [ VAR1:0] VAR4; reg [2**VAR1:0] VAR9;
reg [(2**(VAR1+1) + 1):0] VAR2;
always @(posedge VAR8)
begi... | gpl-3.0 |
hoangt/NOCulator | hring/hw/buffered/src/c_prio_enc.v | 3,091 | module MODULE1
(VAR5, VAR14);
parameter VAR10 = 8;
localparam VAR7 = VAR6(VAR10);
input [0:VAR10-1] VAR5;
output [0:VAR7-1] VAR14;
wire [0:VAR7-1] VAR14;
wire [(VAR7+1)*VAR10-1] VAR12;
assign VAR12[0:VAR10-1] = {VAR10{1'b1}};
generate
genvar VAR13;
for(VAR13 = 0; VAR13 < VAR7; VAR13 = VAR13 + 1)
begin:VAR8
wire sel;
wi... | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/pcie_7x_v1_8_axi_basic_rx_null_gen.v | 15,537 | module MODULE1 # (
parameter VAR11 = 128, parameter VAR29 = 1,
parameter VAR36 = VAR11 / 8 ) (
input [VAR11-1:0] VAR34, input VAR26, input VAR31, input VAR23, input [21:0] VAR37,
output VAR24, output VAR16, output [VAR36-1:0] VAR1, output VAR7, output reg [4:0] VAR33,
input VAR30, input VAR21 );
localparam VAR8 = (VAR1... | mit |
SI-RISCV/e200_opensource | rtl/e203/core/e203_lsu.v | 13,488 | module MODULE1(
input VAR1,
input VAR18,
input VAR62,
output VAR9,
output [VAR97 -1:0] VAR45,
output VAR49 ,
output VAR11,
output VAR21,
output [VAR14 -1:0] VAR99,
output VAR85 ,
input VAR23, output VAR78, input [VAR14-1:0] VAR98, input VAR26, input [VAR96-1:0] VAR41,
input [VAR96/8-1:0] VAR76,
input VAR57,
input VAR10... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s.pp.symbol.v | 1,322 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR4,
input VAR1
);
endmodule | apache-2.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_except.v | 16,461 | module MODULE1(
clk, rst,
VAR2, VAR11, VAR18, VAR32, VAR17, VAR103, VAR91,
VAR83, VAR90, VAR24, VAR82, VAR3, VAR100,
VAR56, VAR66, VAR110, VAR104, VAR9, VAR30,
VAR97, VAR60, VAR41, VAR88, VAR63, VAR98, VAR28,
VAR51, VAR71, VAR50,
VAR108, VAR23, VAR105, VAR55, VAR67, VAR42, VAR16, VAR44, VAR1, VAR52,
VAR102, VAR34, VAR7... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxtp/sky130_fd_sc_ms__sdfxtp.behavioral.v | 2,340 | module MODULE1 (
VAR17 ,
VAR23,
VAR3 ,
VAR10,
VAR13
);
output VAR17 ;
input VAR23;
input VAR3 ;
input VAR10;
input VAR13;
supply1 VAR5;
supply0 VAR24;
supply1 VAR25 ;
supply0 VAR4 ;
wire VAR21 ;
wire VAR22 ;
reg VAR12 ;
wire VAR20 ;
wire VAR18;
wire VAR8;
wire VAR2;
wire VAR15 ;
wire VAR1 ;
wire VAR6 ;
wire VAR19 ;
VAR... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Otros/Audio-SB/Microfono/microfono.v | 1,072 | module MODULE1
(
input enable,
input clk,
output VAR1,
output reg VAR3,
input VAR4,
input reset,
output reg VAR13,
output reg VAR6,
output reg VAR9 );
reg [17:0] VAR10;
reg [0:31] VAR12;
reg [17:0] VAR11;
VAR7 VAR3 =0;
VAR8 VAR5(.clk(clk),.reset(reset),.VAR2(VAR1));
always @(negedge VAR1)
if (reset)
begin
VAR6=0;
if (e... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp.pp.blackbox.v | 1,374 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR6,
VAR2,
VAR7,
VAR3 ,
VAR5
);
output VAR4 ;
input VAR1 ;
input VAR6;
input VAR2;
input VAR7;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_frame_fifo.v | 4,566 | module MODULE1 #
(
parameter VAR20 = 12,
parameter VAR5 = 8,
parameter VAR18 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR5-1:0] VAR14,
input wire VAR19,
output wire VAR16,
input wire VAR15,
input wire VAR23,
output wire [VAR5-1:0] VAR8,
output wire VAR9,
input wire VAR13,
output wire VAR4
);
reg [VAR20:0] VA... | mit |
olofk/oh | elink/hdl/ecfg_elink.v | 4,957 | module MODULE1 (
VAR37, VAR30, VAR14, VAR12,
VAR13,
clk, VAR32, VAR19, VAR1
);
parameter VAR9 = 6; parameter VAR24 = 104; parameter VAR17 = 12'h000;
parameter VAR3 = 12'h808;
input clk;
input VAR32;
input VAR19;
input [VAR24-1:0] VAR1;
output VAR37;
output VAR30; output VAR14; output [15:0] VAR12; output [11:0] VAR13;
... | gpl-3.0 |
alr46664/lab4 | verilog_source/ula.v | 3,894 | module MODULE1( VAR15, VAR10, VAR8, out, VAR3 );
input [VAR6-1:0] VAR15;
input signed [VAR11-1:0] VAR10, VAR8;
output reg signed [VAR11-1:0] out;
output reg [VAR4-1:0] VAR3;
reg VAR16;
reg signed [VAR11-1:0] VAR9;
always @(*) begin
out = VAR10;
VAR3 = 0;
VAR9 = 0;
VAR16 = VAR10[VAR11-1] ^ VAR8[VAR11-1];
if (VAR15 == VA... | gpl-3.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_Alpha_Blender.v | 8,435 | module MODULE1 (
clk,
reset,
VAR14,
VAR13,
VAR12,
VAR2,
VAR7,
VAR1,
VAR19,
VAR5,
VAR23,
VAR25,
VAR11,
VAR22,
VAR16,
VAR10,
VAR9,
VAR3,
VAR17,
VAR21
);
input clk;
input reset;
input [29: 0] VAR14;
input VAR13;
input VAR12;
input [ 1: 0] VAR2;
input VAR7;
input [39: 0] VAR1;
input VAR19;
input VAR5;
input [ 1: 0] VAR23;
... | mit |
sehugg/8bitworkshop | presets/verilog/sprite_scanline_renderer.v | 7,315 | module MODULE1(addr, VAR2);
input [15:0] addr;
output [15:0] VAR2;
reg [15:0] VAR1[0:255];
assign VAR2 = VAR1[addr & 15]; | gpl-3.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/acl_fp_custom_dynamic_align.v | 15,875 | module MODULE1( VAR46, VAR31,
VAR20, VAR81, VAR85,
VAR30, VAR1, VAR10, VAR69,
enable);
parameter VAR12 = 0;
parameter VAR78 = 0;
input VAR46, VAR31;
input [37:0] VAR20;
input [37:0] VAR81;
output [37:0] VAR85;
input enable, VAR30, VAR10;
output VAR1, VAR69;
wire [27:0] VAR53 = VAR20[27:0];
wire [8:0] VAR87 = VAR20[36:2... | mit |
hoglet67/opc | system/blackice/memory_controller_2_wait_states.v | 3,150 | module MODULE1
(
VAR19,
VAR18,
VAR14,
VAR7,
VAR1,
VAR6,
VAR15,
VAR9,
VAR13,
VAR3,
VAR10,
VAR17,
VAR4,
VAR12,
VAR20
);
parameter VAR2 = 32;
parameter VAR5 = 20;
input VAR19;
input VAR18;
input VAR14;
input VAR7;
output VAR1;
input [VAR5-1:0] VAR6;
input [VAR2-1:0] VAR15;
output [VAR2-1:0] VAR9;
output VAR13;
output VAR3... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/yacc/uart_read.v | 2,525 | module MODULE1( VAR6, clk, VAR2,VAR18, VAR7);
input VAR6;
input clk, VAR2;
output [7:0] VAR18;
output VAR7;
reg VAR8;
reg [8:0] VAR10;
reg [2:0] VAR11;
reg [2:0] VAR15;
reg [7:0] VAR4; reg VAR7;
reg [7:0] VAR18;
wire VAR1, VAR16, VAR3,
VAR5, VAR13 ;
wire VAR14;
always @(posedge clk ) begin
VAR8 <=VAR2 ;
end
always @(po... | mit |
monotone-RK/FACE | IEICE-Trans/4-way_2-tree/src/ip_dram/phy/mig_7series_v2_3_ddr_if_post_fifo.v | 8,567 | module MODULE1 #
(
parameter VAR25 = 100, parameter VAR15 = 4, parameter VAR27 = 32 )
(
input clk, input rst, input [3:0] VAR5,
input VAR4,
input [VAR27-1:0] din, output VAR28,
output VAR26,
output [VAR27-1:0] dout );
localparam VAR9
= (VAR15 == 2) ? 1 :
(((VAR15 == 3) || (VAR15 == 4)) ? 2 : 'VAR6);
integer VAR8;
reg [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbp/sky130_fd_sc_ls__dfbbp.blackbox.v | 1,435 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR7 ,
VAR9 ,
VAR6 ,
VAR4
);
output VAR8 ;
output VAR5 ;
input VAR7 ;
input VAR9 ;
input VAR6 ;
input VAR4;
supply1 VAR10;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221oi/sky130_fd_sc_ls__a221oi.pp.symbol.v | 1,409 | module MODULE1 (
input VAR1 ,
input VAR9 ,
input VAR2 ,
input VAR10 ,
input VAR6 ,
output VAR5 ,
input VAR8 ,
input VAR4,
input VAR7,
input VAR3
);
endmodule | apache-2.0 |
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