repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
jefflieu/recon | hw/cmn/timer/recon_timer.v | 4,747 | module MODULE1 (
address,
VAR14,
clk,
VAR20,
write,
read,
VAR1,
VAR13,
irq,
VAR24,
VAR3,
VAR18
);
parameter VAR11 = 50000000;
parameter VAR27 = VAR11/1000-1;
parameter VAR26 = VAR11/1000000-1;
output [ 31: 0] VAR13;
input [ 2: 0] address;
input VAR14;
input clk;
input VAR20;
input write;
input read;
input [ 31: 0] VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s.functional.pp.v | 1,766 | module MODULE1 (
VAR2,
VAR7,
VAR8 ,
VAR5
);
input VAR2;
input VAR7;
output VAR8 ;
input VAR5 ;
wire VAR10 ;
wire VAR6;
buf VAR9 (VAR10 , VAR5 );
VAR1 VAR4 (VAR6, VAR10, VAR2, VAR7);
buf VAR3 (VAR8 , VAR6 );
endmodule | apache-2.0 |
yipenghuang0302/csee4840_14 | rtl/ik_swift_32/full_jacobian/full_mat/t_block/sincos/mult_21/mult_21.v | 2,184 | module MODULE1 (
VAR1,
VAR5,
VAR8,
VAR21,
VAR16);
input VAR1;
input VAR5;
input [20:0] VAR8;
input [20:0] VAR21;
output [41:0] VAR16;
wire [41:0] VAR14;
wire [41:0] VAR16 = VAR14[41:0];
VAR6 VAR17 (
.VAR5 (VAR5),
.VAR21 (VAR21),
.VAR1 (VAR1),
.VAR8 (VAR8),
.VAR16 (VAR14),
.VAR12 (1'b0),
.sum (1'b0));
VAR17.VAR9 = "VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221ai/sky130_fd_sc_hdll__o221ai_1.v | 2,473 | module MODULE2 (
VAR3 ,
VAR10 ,
VAR2 ,
VAR11 ,
VAR12 ,
VAR8 ,
VAR9,
VAR7,
VAR4 ,
VAR6
);
output VAR3 ;
input VAR10 ;
input VAR2 ;
input VAR11 ;
input VAR12 ;
input VAR8 ;
input VAR9;
input VAR7;
input VAR4 ;
input VAR6 ;
VAR5 VAR1 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR12(VAR12),
.VAR8(VAR8),
.VA... | apache-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_samq_ctrl.v | 7,572 | module MODULE1
(clk, reset, VAR48, VAR23, VAR22, VAR2, VAR46,
VAR45, VAR43, VAR35, VAR7, VAR56,
VAR21, VAR24, VAR41);
parameter VAR3 = 4;
parameter VAR33 = 8;
parameter VAR27 = 0;
parameter VAR10 = 0;
parameter VAR5 = 0;
parameter VAR44 = VAR47;
localparam VAR18 = VAR3 * VAR33;
localparam VAR31 = VAR15(VAR18);
localpar... | gpl-2.0 |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v | 11,960 | module MODULE1 (
VAR28, VAR51, VAR55, VAR5, VAR54,
VAR47, VAR24, VAR11, VAR16, VAR21, VAR44, VAR31, VAR13, VAR46, VAR41 );
output [5:0] VAR28; output [15:0] VAR51; output VAR55; output VAR5; output VAR54;
input VAR47; input [15:0] VAR24; input VAR11; input VAR16; input VAR21; input VAR44; input VAR31; input VAR13; inpu... | bsd-3-clause |
plindstroem/oh | common/hdl/clock_divider.v | 2,832 | module MODULE1(
VAR9,
VAR2, VAR3, reset
);
input VAR2; input [3:0] VAR3; input reset; output VAR9;
reg VAR1;
reg [7:0] counter;
reg [7:0] VAR7;
reg [3:0] VAR6;
wire VAR4;
wire VAR5;
wire VAR8;
always @ (VAR3[3:0])
casez (VAR3[3:0])
4'b0001 : VAR7[7:0] = 8'b00000010; 4'b0010 : VAR7[7:0] = 8'b00000100; 4'b0011 : VAR7[7:0... | gpl-3.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_reg2mem.v | 5,398 | module MODULE1(addr, VAR2, VAR5, VAR9);
parameter VAR13 = VAR8;
input [1:0] addr;
input [VAR1-1:0] VAR2;
input [VAR13-1:0] VAR5;
output [VAR13-1:0] VAR9;
reg [7:0] VAR12;
reg [7:0] VAR6;
reg [7:0] VAR7;
reg [7:0] VAR4;
assign VAR9 = {VAR12, VAR6, VAR7, VAR4};
always @(VAR2 or addr or VAR5) begin
casex({VAR2, addr[1:0]}... | apache-2.0 |
linuxbest/lzs | decode/rtl/verilog/decode.v | 3,429 | module MODULE1(
VAR2, VAR6, VAR7, VAR5,
VAR1, rst, VAR9, VAR10, VAR19, clk, VAR13
);
output [15:0] VAR5; output VAR7; output VAR6; output VAR2;
input VAR13; input clk; input [63:0] VAR19; input VAR10; input VAR9; input rst; input VAR1;
wire [7:0] VAR16; wire VAR8; wire VAR3; wire VAR20; wire [12:0] VAR11; wire VAR18; w... | gpl-2.0 |
archlabo/Frix | fpga/nexys4_ddr/rtl/clock/clock.v | 1,700 | module MODULE1(VAR4, VAR1, VAR2);
input VAR4, VAR1;
output VAR2;
reg [7:0] VAR3;
assign VAR2 = VAR3[7];
always @(posedge VAR4 or negedge VAR1) begin
if (!VAR1) VAR3 <= 0;
end
else if (~VAR2) VAR3 <= (VAR3 + 1'b1);
end
endmodule | bsd-2-clause |
CospanDesign/nysa-verilog | verilog/wishbone/master/wishbone_master.v | 23,596 | module MODULE1 #(
parameter VAR133 = 9, parameter VAR131 = 9, parameter VAR57 = 0, parameter VAR4 = 0, parameter VAR45 = 32'd100000000 )(
input clk,
input rst,
input VAR82,
output [1:0] VAR107,
input [1:0] VAR11,
input VAR91,
input [31:0] VAR49,
output [23:0] VAR29,
input VAR110,
output VAR105,
input VAR74,
input VAR2,... | mit |
fabianz66/cursos-tec | taller-digital/Proyecto Final/CON SOLO NCO/tec-drums/fsm.v | 1,602 | module MODULE1(input VAR2, input reset, input VAR4, output reg VAR5);
parameter VAR1 = 0;
parameter VAR7 = 1;
parameter VAR6 = 2;
parameter VAR3 = 3;
reg [2:0] state;
begin
begin
begin
end
begin
begin
end
begin
begin
end
begin
begin | mit |
vvk/sysrek | arithm/ipcore_dir/sum1.v | 27,062 | module MODULE2 (
clk, VAR148, VAR257, VAR73, VAR29
);
input clk;
input VAR148;
output [18 : 0] VAR257;
input [17 : 0] VAR73;
input [12 : 0] VAR29;
wire \VAR50/VAR164 ;
wire \VAR50/VAR234 ;
wire \VAR50/VAR285 ;
wire \VAR50/VAR92 ;
wire \VAR50/VAR242 ;
wire \VAR50/VAR142 ;
wire \VAR50/VAR186 ;
wire \VAR50/VAR10 ;
wire \V... | gpl-2.0 |
olajep/oh | src/adi/hdl/library/common/up_dac_channel.v | 14,394 | module MODULE1 #(
parameter VAR29 = 6'h11,
parameter VAR59 = 4'h0,
parameter VAR44 = 0,
parameter VAR17 = 0,
parameter VAR28 = 0) (
input VAR11,
input VAR61,
output [15:0] VAR31,
output [15:0] VAR22,
output [15:0] VAR5,
output [15:0] VAR52,
output [15:0] VAR84,
output [15:0] VAR71,
output [15:0] VAR60,
output [15:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill_diode/sky130_fd_sc_hs__fill_diode.symbol.v | 1,217 | module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/V2NFC100DDR_v1_0_0/81152d2e/src/NPCG_Toggle_MNC_readST.v | 16,507 | module MODULE1
(
parameter VAR63 = 4
)
(
VAR31 ,
VAR41 ,
VAR24 ,
VAR55 ,
VAR30 ,
VAR47 ,
VAR39 ,
VAR49 ,
VAR35 ,
VAR37 ,
VAR48 ,
VAR58 ,
VAR61 ,
VAR32 ,
VAR23 ,
VAR42 ,
VAR34 ,
VAR33 ,
VAR3 ,
VAR40 ,
VAR57 ,
VAR10 ,
VAR46 ,
VAR4 ,
VAR22 ,
VAR45
);
input VAR31 ;
input VAR41 ;
input [5:0] VAR24 ;
input [4:0] VAR55 ;
inpu... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_phy_top.v | 17,170 | module MODULE1 #
(
parameter VAR93 = 2,
parameter VAR1 = 1,
parameter VAR105 = 1,
parameter VAR12 = 10,
parameter VAR70 = 0,
parameter VAR88 = 1,
parameter VAR76 = 1,
parameter VAR109 = 1,
parameter VAR69 = 9,
parameter VAR111 = 72,
parameter VAR113 = 7,
parameter VAR40 = 8,
parameter VAR47 = 9,
parameter VAR82 = 4,
pa... | lgpl-3.0 |
asicguy/gplgpu | stim/max_core_3d_stim_gate.v | 46,555 | module MODULE1;
parameter
VAR60 = 4,
VAR240 = 2,
VAR60 = 8,
VAR240 = 3,
VAR60 = 16,
VAR240 = 4,
VAR60 = 32,
VAR240 = 5,
VAR187 = 32'h800,
VAR145 = 0;
reg VAR86; reg VAR176;
reg VAR227; tri [63:00] VAR219; tri VAR292; tri VAR25; tri VAR147; tri VAR73; wire VAR141; tri VAR169; wire VAR226; reg VAR228; wire VAR218; tri [7... | gpl-3.0 |
theHawke/real-dcpu | ALU/ashift16.v | 3,874 | module MODULE1 (
VAR19,
VAR17,
VAR13);
input [31:0] VAR19;
input [3:0] VAR17;
output [31:0] VAR13;
wire [31:0] VAR2;
wire VAR4 = 1'h1;
wire [31:0] VAR13 = VAR2[31:0];
VAR11 VAR10 (
.VAR19 (VAR19),
.VAR5 (VAR4),
.VAR17 (VAR17),
.VAR13 (VAR2)
,
.VAR1 (),
.VAR7 (),
.VAR18 (),
.VAR16 (),
.VAR12 ()
);
VAR10.VAR3 = "VAR15",... | gpl-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_itcm_ram.v | 2,579 | module MODULE1(
input VAR13,
input VAR14,
input VAR2,
input VAR3,
input VAR6,
input [VAR15-1:0] addr,
input [VAR9-1:0] VAR5,
input [VAR10-1:0] din,
output [VAR10-1:0] dout,
input VAR8,
input clk
);
VAR12 #(
.VAR7(VAR10),
.VAR11(VAR9),
.VAR4(VAR15)
) VAR1(
.VAR13 (VAR13 ),
.VAR14 (VAR14 ),
.VAR2 (VAR2 ),
.VAR8 (VAR8 ),
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai.blackbox.v | 1,397 | module MODULE1 (
VAR9 ,
VAR2,
VAR7,
VAR6 ,
VAR8
);
output VAR9 ;
input VAR2;
input VAR7;
input VAR6 ;
input VAR8 ;
supply1 VAR4;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbn/sky130_fd_sc_ms__dlrbn.pp.symbol.v | 1,458 | module MODULE1 (
input VAR7 ,
output VAR2 ,
output VAR4 ,
input VAR1,
input VAR5 ,
input VAR6 ,
input VAR9 ,
input VAR3 ,
input VAR8
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkPktFork.v | 8,362 | module MODULE1(VAR1,
VAR5,
VAR2,
VAR59,
VAR62,
VAR12,
VAR26,
VAR57,
VAR58,
VAR20,
VAR50,
VAR28);
input [13 : 0] VAR1;
input VAR5;
input VAR2;
input [152 : 0] VAR59;
input VAR62;
output VAR12;
input VAR26;
output [152 : 0] VAR57;
output VAR58;
input VAR20;
output [152 : 0] VAR50;
output VAR28;
wire [152 : 0] VAR57, VAR5... | lgpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/fifo/ram_36_512.v | 11,205 | module MODULE1 (
VAR61,
VAR56,
VAR29,
VAR62,
VAR44,
VAR12,
VAR10,
VAR50,
VAR40,
VAR26,
VAR22);
input [8:0] VAR61;
input [8:0] VAR56;
input VAR29;
input [35:0] VAR62;
input [35:0] VAR44;
input VAR12;
input VAR10;
input VAR50;
input VAR40;
output [35:0] VAR26;
output [35:0] VAR22;
tri1 VAR29;
tri1 VAR12;
tri1 VAR10;
tri0... | apache-2.0 |
anguslin/RISC | top.v | 3,749 | module MODULE1(VAR5, VAR46, VAR28, VAR47, VAR39, VAR18, VAR19, VAR15, VAR41);
input [1:0] VAR5;
input VAR46;
output [9:0] VAR28;
output [6:0] VAR47, VAR39, VAR18, VAR19, VAR15, VAR41;
wire [15:0] VAR3, VAR22, VAR8, VAR12, VAR45, VAR37;
wire write, VAR31, VAR17, VAR44, VAR20, VAR27, VAR32, VAR10, VAR2, VAR43;
wire [2:0]... | mit |
ultraembedded/riscv | top_cache_axi/src_v/dcache_mux.v | 6,624 | module MODULE1
(
input VAR26
,input VAR22
,input [ 31:0] VAR41
,input [ 31:0] VAR18
,input VAR42
,input [ 3:0] VAR30
,input VAR5
,input [ 10:0] VAR21
,input VAR43
,input VAR3
,input VAR39
,input [ 31:0] VAR35
,input VAR16
,input VAR14
,input VAR23
,input [ 10:0] VAR49
,input [ 31:0] VAR19
,input VAR33
,input VAR24
,inp... | bsd-3-clause |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/V2NFC100DDR_v1_0_0/81152d2e/src/NPhy_Toggle_Top_DDR100.v | 11,495 | module MODULE1
(
parameter VAR1 = 7,
parameter VAR25 = 0,
parameter VAR82 = 4
)
(
VAR60 ,
VAR77 ,
VAR21 ,
VAR48 ,
VAR8 ,
VAR40 ,
VAR66 ,
VAR85 ,
VAR75 ,
VAR51 ,
VAR81 ,
VAR65 ,
VAR50 ,
VAR10 ,
VAR49 ,
VAR69 ,
VAR71 ,
VAR80 ,
VAR58 ,
VAR56 ,
VAR27 ,
VAR28 ,
VAR26 ,
VAR46 ,
VAR89 ,
VAR73 ,
VAR6 ,
VAR5 ,
VAR78 ,
VAR16 ,
V... | gpl-3.0 |
kyzhai/NUNY | src/hardware/bg5_bb.v | 5,032 | module MODULE1 (
address,
VAR1,
VAR2);
input [13:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/trigger_divider.v | 4,576 | module MODULE1(
input clk,
input VAR40,
input VAR32,
input VAR36,
input VAR8,
input VAR17,
input [1:0] VAR16,
input [1:0] VAR19,
input VAR21,
input VAR30,
input VAR15,
output reg VAR25 = 1'b0,
output reg VAR20 = 1'b0,
output reg [5:0] VAR4 = 6'd0,
output reg VAR29
);
reg VAR27 = 1'b0, VAR23 = 1'b0;
reg VAR12 = 1'b0, VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2_0.v | 2,086 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR9 ,
VAR2,
VAR1,
VAR8 ,
VAR3
);
output VAR6 ;
input VAR4 ;
input VAR9 ;
input VAR2;
input VAR1;
input VAR8 ;
input VAR3 ;
VAR7 VAR5 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR6,
VAR4,
VAR9
);
output VAR6;
... | apache-2.0 |
manili/Pipelined_6502 | Execution.v | 2,475 | module MODULE1(
VAR29,
VAR26,
VAR41,
VAR27,
VAR32,
VAR2,
VAR8,
VAR13,
VAR1,
VAR37,
VAR5,
VAR40,
VAR16,
VAR36,
VAR23,
VAR3
,VAR7
);
input wire VAR29;
input wire VAR26;
input wire VAR41;
input wire VAR27;
input wire [7:0] VAR32;
input wire [7:0] VAR2;
input wire [7:0] VAR8;
input wire [VAR21 - 1:0] VAR13;
input wire [15:... | gpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_spram_64x24.v | 11,118 | module MODULE1(
VAR15, VAR18, VAR25,
clk, rst, VAR49, VAR2, VAR44, addr, VAR22, VAR36
);
parameter VAR35 = 6;
parameter VAR24 = 24;
input VAR15;
input [VAR46 - 1:0] VAR25;
output VAR18;
input clk; input rst; input VAR49; input VAR2; input VAR44; input [VAR35-1:0] addr; input [VAR24-1:0] VAR22; output [VAR24-1:0] VAR36;... | mit |
MCDELTAT/CSE311 | lab3/debouncer.v | 2,955 | module MODULE1
(
input wire clk, reset,
input wire VAR10,
output reg VAR3
);
localparam [2:0]
VAR9 = 3'b000,
VAR8 = 3'b001,
VAR7 = 3'b010,
VAR4 = 3'b011,
VAR15 = 3'b100,
VAR16 = 3'b101,
VAR13 = 3'b110,
VAR12 = 3'b111;
localparam VAR2 =19;
reg [VAR2-1:0] VAR1;
wire [VAR2-1:0] VAR5;
wire VAR11;
reg [2:0] VAR6, VAR14;
alw... | mit |
rkrajnc/minimig-mist | rtl/audio/I2C_Controller.v | 2,797 | module MODULE1 (
VAR10,
VAR2, VAR8, VAR13, VAR1, VAR14, VAR15, VAR11,
VAR6,
VAR3
);
input VAR10;
input [23:0]VAR13;
input VAR1;
input VAR11;
inout VAR8;
output VAR2;
output VAR14;
output VAR15;
output [5:0] VAR6;
output VAR3;
reg VAR3;
reg VAR5;
reg VAR14;
reg [23:0]VAR12;
reg [5:0]VAR6;
wire VAR2=VAR5 | ( ((VAR6 >= 4)... | gpl-3.0 |
ultraembedded/riscv | top_tcm_axi/src_v/tcm_mem_pmem.v | 13,516 | module MODULE2
(
input VAR49
,input VAR1
,input VAR70
,input [ 31:0] VAR53
,input [ 3:0] VAR86
,input [ 7:0] VAR18
,input [ 1:0] VAR36
,input VAR76
,input [ 31:0] VAR2
,input [ 3:0] VAR48
,input VAR29
,input VAR33
,input VAR9
,input [ 31:0] VAR66
,input [ 3:0] VAR46
,input [ 7:0] VAR84
,input [ 1:0] VAR62
,input VAR26
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221o/sky130_fd_sc_ms__a221o.functional.v | 1,566 | module MODULE1 (
VAR3 ,
VAR2,
VAR11,
VAR7,
VAR10,
VAR13
);
output VAR3 ;
input VAR2;
input VAR11;
input VAR7;
input VAR10;
input VAR13;
wire VAR4 ;
wire VAR12 ;
wire VAR8;
and VAR1 (VAR4 , VAR7, VAR10 );
and VAR6 (VAR12 , VAR2, VAR11 );
or VAR9 (VAR8, VAR12, VAR4, VAR13);
buf VAR5 (VAR3 , VAR8 );
endmodule | apache-2.0 |
ptracton/pmodacl2 | rtl/system_controller.v | 1,105 | module MODULE1 (
clk, rst, VAR8,
VAR7, VAR5
) ;
input wire VAR7;
input wire VAR5;
output wire clk;
output wire rst;
output wire VAR8;
wire VAR2;
VAR9 VAR3(.VAR1(VAR7), .VAR4(VAR2));
assign clk = VAR7;
reg [4:0] VAR6 =0;
assign rst = |VAR6;
assign VAR8 = ~rst;
always @(posedge VAR7 or posedge VAR5)
if (VAR5) begin
VAR6 ... | mit |
ptracton/wb_soc_template | rtl/lm32_top/rtl/verilog/lm32_adder.v | 4,890 | module MODULE1 (
VAR5,
VAR19,
VAR21,
VAR17,
VAR14,
VAR4,
VAR7
);
input VAR5; input VAR19; input [VAR1] VAR21; input [VAR1] VAR17;
output [VAR1] VAR14; wire [VAR1] VAR14;
output VAR4; wire VAR4;
output VAR7; reg VAR7;
wire VAR11; wire VAR10; wire VAR8;
VAR2 VAR16 (
.VAR12 (VAR21),
.VAR9 (VAR17),
.VAR15 (VAR5),
.VAR22 (V... | mit |
golfit/QcmMasterController | driver.v | 4,014 | module MODULE1 (clk, state, enable);
input clk;
input [6:0] state; output enable; reg VAR5;
reg [2:0] VAR3;
reg [4:0] VAR4;
reg VAR7; reg VAR1;
reg [6:0] VAR8;
parameter VAR6=3'b111;
parameter VAR2=5'b11111; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/buf/sky130_fd_sc_hd__buf_6.v | 1,993 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR8,
VAR2,
VAR4 ,
VAR1
);
output VAR5 ;
input VAR6 ;
input VAR8;
input VAR2;
input VAR4 ;
input VAR1 ;
VAR7 VAR3 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR5,
VAR6
);
output VAR5;
input VAR6;
supply1 VAR8;
supply0 VAR2;... | apache-2.0 |
polysome/hydra | implementation/Hydra_inst_wo_load_new.v | 18,558 | module MODULE1 ( ready , VAR64 ,
clk , VAR10 ,
VAR45 , VAR28 ,
VAR36 , VAR33 ,
VAR43
);
parameter VAR46 = 31;
parameter VAR13 = 5'h0;
parameter VAR69 = 5'h1;
parameter VAR29 = 5'h2;
parameter VAR68 = 5'h3;
parameter VAR22 = 5'h4;
parameter VAR56 = 5'h5;
parameter VAR30 = 5'h6;
parameter VAR3 = 5'h7;
parameter VAR53 = 5... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buflp/sky130_fd_sc_lp__buflp_0.v | 2,024 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR2,
VAR1,
VAR3 ,
VAR4
);
output VAR8 ;
input VAR5 ;
input VAR2;
input VAR1;
input VAR3 ;
input VAR4 ;
VAR6 VAR7 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR8,
VAR5
);
output VAR8;
input VAR5;
supply1 VAR2;
supply0 VAR1;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2/sky130_fd_sc_hs__nand2.behavioral.pp.v | 1,690 | module MODULE1 (
VAR7,
VAR3,
VAR11 ,
VAR6 ,
VAR4
);
input VAR7;
input VAR3;
output VAR11 ;
input VAR6 ;
input VAR4 ;
wire VAR5 ;
wire VAR10;
nand VAR9 (VAR5 , VAR4, VAR6 );
VAR8 VAR1 (VAR10, VAR5, VAR7, VAR3);
buf VAR2 (VAR11 , VAR10 );
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_except.v | 20,360 | module MODULE1(
clk, rst,
VAR87, VAR69, VAR42, VAR40, VAR65, VAR60, VAR57,
VAR93, VAR13, VAR70, VAR97, VAR62, VAR88,
VAR29, VAR41, VAR26, VAR3, VAR11, VAR90,
VAR78, VAR76, VAR55, VAR83, VAR94, VAR36, VAR84,
VAR53, VAR89, VAR22,
VAR68, VAR38, VAR16, VAR10, VAR5, VAR23, VAR63, VAR1, VAR31, VAR98,
VAR43, VAR51, VAR21, VAR... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_1.functional.pp.v | 1,416 | module MODULE1( VAR2, VAR10, VAR16, VAR7, VAR4, VAR11, VAR9 );
input VAR4, VAR7, VAR16, VAR2;
inout VAR11, VAR9;
output VAR10;
wire VAR15;
not VAR14( VAR15, VAR4 );
wire VAR1;
not VAR3( VAR1, VAR7 );
wire VAR12;
not VAR6( VAR12, VAR16 );
wire VAR13;
not VAR8( VAR13, VAR2 );
or VAR5( VAR10, VAR15, VAR1, VAR12, VAR13 );
... | apache-2.0 |
sittner/lcnc-mdsio | vhdl/source/can/can_crc.v | 4,577 | module MODULE1 (clk, VAR3, enable, VAR6, VAR5);
parameter VAR4 = 1;
input clk;
input VAR3;
input enable;
input VAR6;
output [14:0] VAR5;
reg [14:0] VAR5;
wire VAR1;
wire [14:0] VAR2;
assign VAR1 = VAR3 ^ VAR5[14];
assign VAR2 = {VAR5[13:0], 1'b0};
always @ (posedge clk)
begin
if(VAR6)
VAR5 <= #VAR4 15'h0;
end
else if (... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3/sky130_fd_sc_ms__nor3.pp.blackbox.v | 1,321 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR3 ,
VAR2 ,
VAR1,
VAR8,
VAR4 ,
VAR5
);
output VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR2 ;
input VAR1;
input VAR8;
input VAR4 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtn/sky130_fd_sc_hd__sdfrtn_1.v | 2,587 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR10 ,
VAR3 ,
VAR9 ,
VAR5,
VAR1 ,
VAR12 ,
VAR11 ,
VAR7
);
output VAR4 ;
input VAR8 ;
input VAR10 ;
input VAR3 ;
input VAR9 ;
input VAR5;
input VAR1 ;
input VAR12 ;
input VAR11 ;
input VAR7 ;
VAR2 VAR6 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR1... | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_wdata_router.v | 6,787 | module MODULE1 #
(
parameter VAR29 = "none", parameter integer VAR30 = 1, parameter integer VAR26 = 1, parameter integer VAR34 = 1, parameter integer VAR24 = 0 )
(
input wire VAR17,
input wire VAR13,
input wire [VAR30-1:0] VAR33,
input wire VAR11,
input wire VAR20,
output wire VAR32,
output wire [VAR30-1:0] VAR1, outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22o/sky130_fd_sc_hs__a22o.pp.blackbox.v | 1,332 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR4 ,
VAR7 ,
VAR6 ,
VAR1,
VAR2
);
output VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR1;
input VAR2;
endmodule | apache-2.0 |
jas0n1ee/THU-DSD | FB/lcd_0.v | 2,049 | module MODULE1 (
address,
VAR3,
clk,
read,
VAR2,
write,
VAR5,
VAR4,
VAR7,
VAR1,
VAR8,
VAR6
)
;
output VAR4;
output VAR7;
output VAR1;
inout [ 7: 0] VAR8;
output [ 7: 0] VAR6;
input [ 1: 0] address;
input VAR3;
input clk;
input read;
input VAR2;
input write;
input [ 7: 0] VAR5;
wire VAR4;
wire VAR7;
wire VAR1;
wire [ 7:... | mit |
Gilberto-Lopez/Arquitectura-Computadoras | Practica3/ALU.v | 1,863 | module MODULE1(
input wire [31:0] VAR24,
input wire [31:0] VAR21,
input wire [3:0] VAR8,
output reg [31:0] VAR25,
output reg VAR6,
output reg VAR2,
output reg VAR17,
output reg VAR28
);
localparam VAR26 = 4'd0;
localparam VAR7 = 4'd1;
localparam VAR1 = 4'd2;
localparam VAR39 = 4'd3;
localparam VAR32 = 4'd4;
localparam ... | lgpl-3.0 |
jotego/jt51 | syn/xilinx/contra_snd/hdl/ymplayer.v | 4,930 | module MODULE1(
input VAR77,
input rst,
output reg VAR94,
output reg VAR110,
input [3:0] VAR58, input VAR1, input VAR79,
output VAR115,
output [7:0] VAR66
);
wire VAR87, VAR121, VAR23;
reg [9:0] VAR65;
wire VAR21 = &VAR65;
always @(posedge VAR77)
VAR65 <= { VAR65[8:0], VAR1 };
wire VAR69, VAR30, VAR54;
VAR96 VAR47(
.rs... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_sig_top_b.v | 81,235 | module MODULE1(VAR395 ,VAR50 ,
VAR104 ,VAR385 ,VAR16 ,VAR145 ,VAR135 ,
VAR140 ,VAR274 ,VAR368 ,VAR215 ,
VAR201 ,VAR315 ,VAR361 ,VAR369 ,VAR4 ,VAR137 ,
VAR282 ,VAR386 ,VAR144 ,VAR237 ,
VAR21 ,VAR46 ,
VAR255 ,VAR389 ,VAR328 , VAR130,
VAR294 ,VAR94 ,VAR161 ,
VAR266 ,VAR168 ,VAR15 ,VAR310 ,VAR204 ,
VAR408 ,VAR263 ,VAR8 ,VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31o/sky130_fd_sc_lp__a31o_2.v | 2,337 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR2,
VAR8,
VAR11 ,
VAR1
);
output VAR9 ;
input VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR2;
input VAR8;
input VAR11 ;
input VAR1 ;
VAR10 VAR5 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR... | apache-2.0 |
SymbiFlow/prjuray | spec/slice_memory.v | 21,862 | module MODULE3 #(
parameter [1023:0] VAR106 = "",
parameter [63:0] VAR207 = 64'h00C0FFEE,
parameter [63:0] VAR55 = 64'h00C0FFEE,
parameter [63:0] VAR145 = 64'h00C0FFEE,
parameter [63:0] VAR142 = 64'h00C0FFEE,
parameter [63:0] VAR218 = 64'h00C0FFEE,
parameter [63:0] VAR126 = 64'h00C0FFEE,
parameter [63:0] VAR269 = 64'h0... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_2.v | 2,583 | module MODULE2 (
VAR10 ,
VAR4 ,
VAR2 ,
VAR7 ,
VAR9 ,
VAR6,
VAR5 ,
VAR12 ,
VAR1 ,
VAR8
);
output VAR10 ;
input VAR4 ;
input VAR2 ;
input VAR7 ;
input VAR9 ;
input VAR6;
input VAR5 ;
input VAR12 ;
input VAR1 ;
input VAR8 ;
VAR3 VAR11 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mesosync_io/src/bsg_mesosync_output.v | 9,167 | module MODULE1
, parameter VAR36(VAR53 )
)
( input clk
, input reset
, input VAR39 VAR57
, input [VAR16-1:0] VAR31
, output logic VAR21
, output logic [VAR16-1:0] VAR73
, input VAR74
, input VAR62
, output VAR5
, output logic VAR9
, output logic VAR13
);
logic [1:0] VAR56, VAR55;
logic VAR43; VAR26 VAR42;
logic [VAR18-... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_2.behavioral.pp.v | 3,497 | module MODULE1( VAR3, VAR5, VAR8, VAR4, VAR2, VAR6, VAR10, VAR1 );
input VAR8, VAR5, VAR3, VAR6, VAR2;
inout VAR10, VAR1;
output VAR4;
VAR11 VAR7(.VAR3(VAR3),.VAR5(VAR5),.VAR8(VAR8),.VAR4(VAR4),.VAR2(VAR2),.VAR6(VAR6),.VAR10(VAR10),.VAR1(VAR1));
VAR11 VAR9(.VAR3(VAR3),.VAR5(VAR5),.VAR8(VAR8),.VAR4(VAR4),.VAR2(VAR2),.VA... | apache-2.0 |
Ribeiro/sd2snes | verilog/sd2sneslite/main.v | 9,700 | module MODULE1(
input VAR29,
input [23:0] VAR32,
input VAR5,
input VAR119,
input VAR82,
inout [7:0] VAR133,
input VAR102,
input VAR79,
output VAR34,
output VAR58,
output VAR49,
input VAR15,
input [7:0] VAR37,
input VAR59,
input VAR69,
inout [15:0] VAR111,
output [22:0] VAR28,
output VAR125,
output VAR104,
output VAR81,... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.v | 2,587 | module MODULE1 (
VAR6 ,
VAR12 ,
VAR4 ,
VAR8 ,
VAR11 ,
VAR2,
VAR1 ,
VAR3 ,
VAR7 ,
VAR10
);
output VAR6 ;
input VAR12 ;
input VAR4 ;
input VAR8 ;
input VAR11 ;
input VAR2;
input VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR10 ;
VAR5 VAR9 (
.VAR6(VAR6),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR2(VAR2),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrbp/sky130_fd_sc_ms__sdfrbp.pp.symbol.v | 1,545 | module MODULE1 (
input VAR5 ,
output VAR8 ,
output VAR4 ,
input VAR10,
input VAR11 ,
input VAR9 ,
input VAR3 ,
input VAR1 ,
input VAR2 ,
input VAR6 ,
input VAR7
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_hip_s4gx_gen2_x8_128/pci_express_compiler-library/altpcie_pclk_align.v | 9,178 | module MODULE1
(
rst,
VAR47,
VAR48,
VAR38,
VAR17,
VAR39,
VAR24,
VAR30,
VAR33,
VAR22,
VAR52,
VAR23,
VAR51,
VAR27,
VAR40
);
input rst;
input VAR47;
input [7:0] VAR48;
input VAR38;
input VAR17;
input VAR39;
input VAR24;
input VAR22;
output VAR30;
output VAR33;
output VAR52;
output VAR23;
output VAR51;
input VAR27;
output ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311oi/sky130_fd_sc_ms__a311oi.symbol.v | 1,395 | module MODULE1 (
input VAR8,
input VAR3,
input VAR9,
input VAR10,
input VAR7,
output VAR4
);
supply1 VAR1;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
hoangt/NOCulator | hring/hw/buffered/src/c_fbmult.v | 4,859 | module MODULE1
(VAR20, VAR36, VAR6, VAR8);
parameter VAR19 = 32;
parameter VAR28 = 1;
input [0:VAR19-1] VAR20;
input VAR36;
input [0:VAR19-1] VAR6;
output [0:VAR19-1] VAR8;
wire [0:VAR19-1] VAR8;
wire [0:VAR19-1] VAR23;
wire [0:VAR19*VAR19-1] VAR3;
generate
if(VAR19 == 1)
begin
assign VAR23 = VAR36 ^ VAR6;
assign VAR3 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2i/sky130_fd_sc_ls__mux2i.behavioral.pp.v | 1,934 | module MODULE1 (
VAR10 ,
VAR3 ,
VAR11 ,
VAR13 ,
VAR14,
VAR4,
VAR7 ,
VAR2
);
output VAR10 ;
input VAR3 ;
input VAR11 ;
input VAR13 ;
input VAR14;
input VAR4;
input VAR7 ;
input VAR2 ;
wire VAR5;
wire VAR8;
VAR15 VAR1 (VAR5, VAR3, VAR11, VAR13 );
VAR6 VAR9 (VAR8, VAR5, VAR14, VAR4);
buf VAR12 (VAR10 , VAR8 );
endmodule | apache-2.0 |
bluespec/Flute | builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkMMIO_AXI4_Adapter_2.v | 75,496 | module MODULE1(VAR231,
VAR21,
VAR186,
VAR42,
VAR268,
VAR162,
VAR54,
VAR259,
VAR58,
VAR71,
VAR242,
VAR214,
VAR275,
VAR215,
VAR302,
VAR123,
VAR84,
VAR225,
VAR164,
VAR153,
VAR267,
VAR82,
VAR271,
VAR60,
VAR47,
VAR33,
VAR300,
VAR243,
VAR25,
VAR326,
VAR273,
VAR307,
VAR258,
VAR99,
VAR342,
VAR163,
VAR206,
VAR14,
VAR139,
VAR316... | apache-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T27-rom-param/genrom.v | 1,541 | module MODULE1 #( parameter VAR6 = 5, parameter VAR3 = 4)
( input clk, input wire [VAR6-1: 0] addr, output reg [VAR3-1: 0] VAR8);
parameter VAR7 = "VAR1.VAR5";
localparam VAR4 = 2 ** VAR6;
reg [VAR3-1: 0] VAR2 [0: VAR4-1];
always @(posedge clk) begin
VAR8 <= VAR2[addr];
end | gpl-2.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v | 24,955 | module MODULE1 (
clk,
reset,
VAR37,
VAR57
);
parameter VAR34 = 5; parameter VAR18 = 3;
parameter VAR17 = 6;
input clk;
input reset;
input[VAR17-2:0] VAR37;
output VAR57;
wire pulse;
wire VAR6;
wire [VAR17-2:0] VAR70 = VAR37;
reg VAR49;
reg [VAR18-1:0] VAR7;
reg [VAR17-1:0] VAR5;
always @(posedge clk)
begin
if (reset) V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3.functional.v | 1,724 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR5,
VAR8
);
output VAR6 ;
input VAR9 ;
input VAR5;
input VAR8;
wire VAR10 ;
wire VAR1;
buf VAR7 (VAR10 , VAR9 );
VAR3 VAR2 (VAR1, VAR10, VAR5, VAR8);
buf VAR4 (VAR6 , VAR1 );
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_reduced_normalize_mult.v | 4,544 | module MODULE1(
VAR19, VAR14,
VAR16, VAR5, VAR6,
VAR20, VAR9, VAR18, VAR10,
enable,
VAR12, VAR3, VAR11);
parameter VAR21 = 1;
parameter VAR1 = 1;
parameter VAR2 = 1;
input VAR19, VAR14;
input VAR20, VAR9;
output VAR18, VAR10;
input enable;
input [27:0] VAR16;
input [8:0] VAR5; input VAR6;
output [26:0] VAR12; output [8... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/stage1.v | 13,627 | module MODULE1(
clk,rst,
VAR126,VAR92,
VAR88,
VAR61 ,VAR29 ,VAR34 ,VAR91 ,
VAR26 ,VAR90 ,VAR82 ,VAR63 ,
VAR44 ,VAR87 ,VAR130,VAR95,
VAR128,VAR68,VAR67,VAR136,
VAR45,VAR55,VAR122,VAR76,
VAR139,VAR10,VAR16,VAR53,
VAR64,VAR12,VAR73,VAR46,
VAR41,VAR112,VAR124,VAR118,
VAR6,
o0 ,o1 ,o2 ,o3 ,
o4 ,o5 ,o6 ,o7 ,
VAR52 ,VAR75 ,o1... | gpl-3.0 |
sh-chris110/chris | FPGA/uCos/system/synthesis/submodules/system_new_sdram_controller_0.v | 24,265 | module MODULE1 (
clk,
rd,
VAR25,
wr,
VAR55,
VAR74,
VAR14,
VAR62,
VAR58,
VAR23
)
;
output VAR74;
output VAR14;
output VAR62;
output VAR58;
output [ 43: 0] VAR23;
input clk;
input rd;
input VAR25;
input wr;
input [ 43: 0] VAR55;
wire VAR74;
wire VAR14;
wire VAR62;
reg [ 1: 0] VAR59;
reg [ 43: 0] VAR46;
reg [ 43: 0] VAR83... | gpl-2.0 |
danbone/core | rtl/riscv_ex_pipe.v | 3,376 | module MODULE1 (
input clk,
input VAR10,
input VAR9,
input [VAR31-1:0] VAR21,
input [31:0] VAR23,
input [31:0] VAR30,
input [VAR33-1:0] VAR16,
input [31:0] VAR34,
input [4:0] VAR24,
input [31:0] VAR5,
input VAR29,
output [31:0] VAR3,
output VAR12,
output VAR38,
output [3:0] VAR18,
output [31:0] VAR40,
output [31:0] VAR... | mit |
binary-logic/vj-uart | rtl/fsm_app.v | 3,171 | module MODULE1(
input VAR1,
input VAR17
);
parameter VAR2 = 0, VAR9 = 1, VAR21 = 2, VAR4 = 3, VAR8 = 4, VAR20 = 5, VAR3 = 6;
reg [2:0] state;
reg [7:0] VAR16;
reg wr, rd;
wire [7:0] VAR7;
wire VAR5, VAR14, VAR11, VAR10;
VAR15 VAR19(
.VAR1( VAR1 ),
.VAR17(VAR17),
.VAR12(wr),
.VAR13(VAR16),
.VAR18(rd),
.VAR6(VAR7),
.VAR5... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3b/sky130_fd_sc_hdll__or3b.functional.v | 1,379 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR6 ,
VAR4
);
output VAR8 ;
input VAR3 ;
input VAR6 ;
input VAR4;
wire VAR7 ;
wire VAR1;
not VAR9 (VAR7 , VAR4 );
or VAR2 (VAR1, VAR6, VAR3, VAR7 );
buf VAR5 (VAR8 , VAR1 );
endmodule | apache-2.0 |
sabertazimi/hust-lab | architecture/design/fpga/src/integer_to_segment.v | 1,393 | module MODULE1
(
input [3:0] VAR1,
output reg [7:0] VAR2
);
always @(VAR1) begin
case (VAR1)
4'b0000: VAR2 <= 8'b11000000; 4'b0001: VAR2 <= 8'b11111001; 4'b0010: VAR2 <= 8'b10100100; 4'b0011: VAR2 <= 8'b10110000; 4'b0100: VAR2 <= 8'b10011001; 4'b0101: VAR2 <= 8'b10010010; 4'b0110: VAR2 <= 8'b10000010; 4'b0111: VAR2 <= ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probe_p/sky130_fd_sc_hdll__probe_p.functional.v | 1,272 | module MODULE1 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
wire VAR1;
buf VAR3 (VAR1, VAR4 );
buf VAR5 (VAR2 , VAR1 );
endmodule | apache-2.0 |
toyoshim/mc6502 | rtl/MC6502.v | 11,239 | module MODULE1(
clk,
VAR109,
VAR10,
VAR25,
VAR100,
VAR35,
VAR70,
VAR148,
VAR122,
VAR50,
VAR182);
input clk;
input VAR109;
input VAR10;
input VAR25;
input VAR100;
inout [ 7:0] VAR35;
output VAR70;
output VAR148;
output VAR122;
output VAR50;
output [15:0] VAR182;
wire [ 7:0] VAR2;
wire VAR6;
wire [15:0] VAR69;
wire VAR62... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211a/sky130_fd_sc_hs__o211a.functional.v | 1,928 | module MODULE1 (
VAR12,
VAR9,
VAR4 ,
VAR13 ,
VAR5 ,
VAR11 ,
VAR2
);
input VAR12;
input VAR9;
output VAR4 ;
input VAR13 ;
input VAR5 ;
input VAR11 ;
input VAR2 ;
wire VAR2 VAR6 ;
wire VAR3 ;
wire VAR1;
or VAR10 (VAR6 , VAR5, VAR13 );
and VAR8 (VAR3 , VAR6, VAR11, VAR2 );
VAR7 VAR14 (VAR1, VAR3, VAR12, VAR9);
buf VAR15 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fah/sky130_fd_sc_lp__fah_1.v | 2,283 | module MODULE1 (
VAR6,
VAR10 ,
VAR11 ,
VAR4 ,
VAR5 ,
VAR2,
VAR7,
VAR8 ,
VAR9
);
output VAR6;
output VAR10 ;
input VAR11 ;
input VAR4 ;
input VAR5 ;
input VAR2;
input VAR7;
input VAR8 ;
input VAR9 ;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR8(VAR8),
.V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3b/sky130_fd_sc_ms__and3b_2.v | 2,218 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR6 ,
VAR1 ,
VAR5,
VAR2,
VAR4 ,
VAR10
);
output VAR7 ;
input VAR9 ;
input VAR6 ;
input VAR1 ;
input VAR5;
input VAR2;
input VAR4 ;
input VAR10 ;
VAR3 VAR8 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Otros/Guia/fifo.v | 2,293 | module MODULE1
parameter VAR16 = 12,
parameter VAR3 = 16
)
(
input reset, clk,
input rd, wr,
input [VAR3-1:0] VAR17,
output [VAR3-1:0] VAR10,
output VAR15,
output VAR9
);
parameter VAR4 = (1 << VAR16);
reg [VAR3-1:0] VAR2 [VAR4-1:0];
reg [VAR16-1:0] VAR13;
reg [VAR16-1:0] VAR7=0;
reg [VAR16-1:0] VAR5, VAR1=0;
reg VAR8,... | gpl-3.0 |
chadharrington/all_spark_cube | fpga/color_component_driver.v | 1,275 | module MODULE1
(
input clk,
input VAR8,
input VAR18,
input VAR12,
input VAR2,
input VAR7,
input [7:0] VAR15,
input [127:0] VAR16,
output VAR1
);
wire [7:0] VAR5;
wire [15:0] VAR4;
wire [15:0] out;
wire [15:0] VAR17;
assign VAR5 = 8'hff; assign VAR4 = {8'h00, VAR5};
VAR13 #(.VAR10(16)) VAR14
(.clk(clk), .VAR8(VAR8),
.VA... | mit |
r2apu/Labo_Digitales | L3/SubR/MiniAlu.v | 7,056 | module MODULE1
(
input wire VAR51,
input wire VAR33,
output wire [7:0] VAR37
);
wire [15:0] VAR67,VAR26;
reg VAR9,VAR10;
wire [27:0] VAR29,VAR61;
wire [3:0] VAR27,VAR53;
reg signed [15:0] VAR18;
wire [7:0] VAR8,VAR60,VAR56, VAR11, VAR12, VAR35;
wire [15:0] VAR4,VAR48,VAR16,VAR24;
reg [15:0] VAR7;
VAR25 VAR17
(
.VAR50( ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probe_p/sky130_fd_sc_hdll__probe_p.pp.blackbox.v | 1,272 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR5,
VAR3,
VAR1 ,
VAR4
);
output VAR6 ;
input VAR2 ;
input VAR5;
input VAR3;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2.functional.v | 1,309 | module MODULE1 (
VAR4,
VAR5
);
output VAR4;
input VAR5;
wire VAR2;
buf VAR3 (VAR2, VAR5 );
buf VAR1 (VAR4 , VAR2 );
endmodule | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | systemverilog/Sequential/FSM/trafficlight_controller.v | 3,652 | module MODULE1 (input wire clk,
input wire rst,
output reg VAR9,
output reg VAR1,
output reg VAR3,
output reg VAR15,
output reg VAR11,
output reg VAR6);
reg [1:0] VAR13;
reg [1:0] VAR4;
reg [15:0] VAR8;
localparam VAR14 = 16'd6000;
localparam VAR2 = 16'd500;
localparam VAR5 = 2'b00;
localparam VAR12 = 2'b01;
localparam... | mit |
andrzej-r/wb_gpio | rtl/wb_gpio.v | 2,172 | module MODULE1
parameter VAR2 = 32 )
(
input VAR13,
input VAR4,
input [2:2] VAR1,
input [VAR2-1:0] VAR16,
input VAR7,
input VAR3,
input VAR9,
input [2:0] VAR11,
input [1:0] VAR12,
output reg [VAR2-1:0] VAR10,
output reg VAR6,
output VAR17,
output VAR14,
input [VAR2-1:0] VAR8,
output reg [VAR2-1:0] VAR18,
output reg [VA... | bsd-2-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/mul/rtl/sparc_mul_top.v | 4,277 | module MODULE1(
VAR34, VAR6, VAR30, VAR8, VAR4,
VAR19, VAR35, VAR24, VAR13, VAR1, VAR32,
VAR23, VAR37, VAR29, VAR14,
VAR21, VAR36, VAR33, VAR11, VAR40
);
input VAR19;
input VAR35; input VAR24; input VAR11; input VAR40; input VAR13; input [63:0] VAR1; input [63:0] VAR32; input VAR23; input VAR37; input VAR29; input VAR1... | gpl-2.0 |
AdriaanSwan/Verilog-Quadrature-Decoder-I2C-Slave | Verilog/top.v | 1,153 | module MODULE1(VAR21, VAR1, VAR24, VAR15, VAR26, VAR9,VAR11, VAR3, VAR16, VAR22, VAR17);
input VAR21;
input VAR1;
inout VAR24;
input VAR15;
input VAR26;
input VAR9;
input VAR11;
input VAR3;
input VAR16;
input VAR22;
input VAR17;
wire[15:0] VAR7;
wire[15:0] VAR18;
wire[15:0] VAR13;
wire[15:0] VAR6;
wire[7:0] VAR4;
wire[... | gpl-2.0 |
alexforencich/verilog-ethernet | rtl/ssio_sdr_out.v | 2,048 | module MODULE1 #
(
parameter VAR3 = "VAR14",
parameter VAR4 = "VAR2",
parameter VAR13 = 1
)
(
input wire clk,
input wire [VAR13-1:0] VAR1,
output wire VAR12,
output wire [VAR13-1:0] VAR9
);
VAR10 #(
.VAR3(VAR3),
.VAR4(VAR4),
.VAR13(1)
)
VAR5 (
.clk(clk),
.VAR7(1'b0),
.VAR8(1'b1),
.VAR6(VAR12)
);
reg [VAR13-1:0] VAR11 =... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_ss_422to444.v | 4,991 | module MODULE1 (
clk,
VAR9,
VAR6,
VAR4,
VAR3,
VAR11);
parameter VAR2 = 0;
parameter VAR12 = 16;
localparam VAR13 = VAR12 - 1;
input clk;
input VAR9;
input [VAR13:0] VAR6;
input [15:0] VAR4;
output [VAR13:0] VAR3;
output [23:0] VAR11;
reg VAR5 = 'd0;
reg VAR16 = 'd0;
reg [VAR13:0] VAR1 = 'd0;
reg VAR18 = 'd0;
reg [7:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dff_p/sky130_fd_sc_hdll__udp_dff_p.symbol.v | 1,260 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR2
);
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/decoder.v | 10,520 | module MODULE1 (
input wire [VAR48] VAR58, input wire [VAR57] VAR3, input wire VAR14,
input wire [VAR57] VAR51, input wire [VAR57] VAR62, output wire [VAR17] VAR42, output wire [VAR17] VAR77,
input wire VAR7, input wire [VAR17] VAR33, input wire VAR1, input wire [VAR66] VAR55, input wire VAR27, input wire [VAR17] VAR15... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2/sky130_fd_sc_ms__nand2_1.v | 2,097 | module MODULE2 (
VAR2 ,
VAR7 ,
VAR9 ,
VAR4,
VAR3,
VAR6 ,
VAR5
);
output VAR2 ;
input VAR7 ;
input VAR9 ;
input VAR4;
input VAR3;
input VAR6 ;
input VAR5 ;
VAR1 VAR8 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR2,
VAR7,
VAR9
);
output VAR2;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tap/sky130_fd_sc_ls__tap.pp.blackbox.v | 1,215 | module MODULE1 (
VAR3,
VAR1,
VAR4 ,
VAR2
);
input VAR3;
input VAR1;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
jobisoft/jTDC | modules/encoder/96bit_encoder.v | 9,099 | module MODULE1 (VAR12,enable,VAR25,VAR7,VAR30,VAR4,VAR1,VAR16);
genvar VAR2;
parameter VAR36 = 9;
input wire VAR7;
input wire VAR30;
input wire [95:0] VAR25;
input wire VAR12;
input wire enable;
output reg [VAR36-1:0] VAR4;
output reg VAR1;
output reg VAR16;
generate
for (VAR2=0; VAR2 < 24; VAR2=VAR2+1) begin : VAR18
r... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21bai/sky130_fd_sc_hdll__o21bai.symbol.v | 1,402 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR8,
output VAR5
);
supply1 VAR7;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
vvk/sysrek | skin_color_segm/erosion3x3.v | 2,740 | module MODULE1 #(
parameter [9:0] VAR29 = 83 )(
input clk,
input VAR24,
input rst,
input VAR26,
input VAR15,
input VAR12,
input VAR1,
output VAR17,
output VAR25,
output VAR2,
output VAR21
);
wire [3:0] VAR30;
reg [3:0] VAR9 [2:0];
wire [3:0] VAR27;
reg [3:0] VAR5 [2:0];
wire [3:0] VAR3;
reg [3:0] VAR11 [2:0];
reg [4:0]... | gpl-2.0 |
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