repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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Alexoner/RiscCPU | cpu.v | 2,251 | module MODULE1(clk,reset,VAR11,rd,wr,addr,VAR1);
input clk,reset;
output rd,wr,addr,VAR11;
inout VAR1;
wire clk,reset,VAR11;
wire [7:0] VAR1;
wire [12:0] addr;
wire rd,wr;
wire VAR6,VAR28,VAR3;
wire [2:0] VAR17;
wire [12:0] VAR24,VAR22;
wire [7:0] VAR8,VAR20;
wire VAR5,VAR25,VAR9,VAR15,VAR32,VAR21,VAR33;
VAR10 VAR18 (.... | gpl-2.0 |
asicguy/gplgpu | hdl/vga/attr.v | 8,376 | module MODULE1
(
input VAR1, input [15:0] VAR42, input VAR3, input VAR58, input VAR36, input VAR61, input VAR60, input VAR47, input VAR33, input VAR66, input VAR5,
input [36:0] VAR13,
input VAR54, input VAR20,
input VAR10,
input VAR6, input VAR15, input VAR52,
input VAR56,
input VAR53,
input VAR32, input VAR65, input V... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v | 1,913 | module MODULE1 (
address,
clk,
VAR2,
VAR6,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR2;
input VAR6;
wire VAR4;
wire [ 7: 0] VAR5;
wire [ 7: 0] VAR1;
reg [ 31: 0] VAR3;
assign VAR4 = 1;
assign VAR1 = {8 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR6)
begin
if (VAR6... | gpl-3.0 |
ptracton/wb_dsp | rtl/wb_dsp_top.v | 10,329 | module MODULE1 (
interrupt, VAR56, VAR41, VAR84,
VAR45, VAR3, VAR16, VAR6,
VAR29, VAR95, VAR78, VAR64,
VAR23,
VAR53, VAR98, VAR96, VAR61, VAR8,
VAR52, VAR83, VAR40, VAR19,
VAR85, VAR82, VAR14, VAR65,
VAR37, VAR46
) ;
parameter VAR59 = 32;
parameter VAR97 = 32;
parameter VAR58 = 32;
parameter VAR42 = 8;
input VAR53;
inp... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbusr/rtl/bw_clk_cl_jbusr_jbus.v | 3,846 | module MODULE1(VAR29 ,VAR5 ,VAR12 ,VAR4 ,VAR26 ,VAR8
,VAR44 ,VAR40 ,VAR35 ,VAR45 ,VAR9 ,VAR11 );
output VAR29 ;
output VAR5 ;
output VAR12 ;
output VAR4 ;
input VAR26 ;
input VAR8 ;
input VAR44 ;
input VAR40 ;
input VAR35 ;
input VAR45 ;
input VAR9 ;
input VAR11 ;
wire [3:0] VAR36 ;
wire [1:0] VAR16 ;
wire VAR22 ;
wire... | gpl-2.0 |
DougFirErickson/parallella-hw | fpga/old/ecfg_split/hdl/ecfg_split.v | 10,193 | module MODULE1(
VAR76, VAR34, VAR24, VAR40,
VAR1, VAR51, VAR20,
VAR15, VAR25, VAR27,
VAR35, VAR2, VAR50,
VAR39, VAR32, VAR53,
VAR29, VAR3, VAR9,
VAR17, VAR43, VAR56,
VAR13, VAR69, VAR41,
VAR21, VAR14, VAR65,
VAR33, VAR78, VAR28,
VAR54, VAR37, VAR73,
VAR16, VAR11, VAR63,
VAR5, VAR26, VAR47,
VAR45, VAR44, VAR62,
VAR71, V... | gpl-3.0 |
fabianz66/cursos-tec | taller-digital/Lab4/lab_pong/mod_fsm_main.v | 2,785 | module MODULE1(clk, VAR28, VAR19, VAR6, VAR9, VAR21, VAR23, VAR1, VAR15, VAR20, VAR2, VAR25, VAR16);
input clk, VAR28, VAR13, VAR6, VAR9, VAR21, VAR1, VAR10, VAR20;
input [4:0] VAR23;
input [9:0] VAR2;
output VAR2, VAR25, VAR16;
wire clk, VAR9, VAR21, VAR11, VAR26, VAR1, VAR10, VAR20;
wire [4:0] VAR23;
wire [9:0] VAR2;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3b/sky130_fd_sc_ls__or3b.pp.symbol.v | 1,301 | module MODULE1 (
input VAR3 ,
input VAR6 ,
input VAR7 ,
output VAR8 ,
input VAR2 ,
input VAR4,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/timer.v | 4,250 | module MODULE1(
clk,
VAR2, delay, VAR10,
reset,
VAR7,
VAR12
);
input clk;
input VAR2;
input reset;
input VAR10;
input [VAR1-1:0] delay; output reg VAR7;
reg [VAR1-1:0] VAR8;
output reg [VAR6-1:0] VAR12;
reg [VAR4-1:0] counter;
always @(posedge clk or negedge VAR2) begin
if (~VAR2)
begin
VAR12 <= #VAR11 VAR13;
counter <... | gpl-2.0 |
UA3MQJ/fpga-synth | modules/note2dds.v | 2,580 | module MODULE1(clk, VAR2, VAR4);
input wire clk;
input wire [8:0] VAR2; output [31:0] VAR4;
reg [31:0] VAR1 [15:0];
reg [3:0] addr;
reg [3:0] VAR3; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tap/sky130_fd_sc_hd__tap_1.v | 1,877 | module MODULE1 (
VAR4,
VAR5,
VAR1 ,
VAR3
);
input VAR4;
input VAR5;
input VAR1 ;
input VAR3 ;
VAR2 VAR6 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE1 ();
supply1 VAR4;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR3 ;
VAR2 VAR6 ();
endmodule | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/altera_reset_synchronizer.v | 3,479 | module MODULE1
parameter VAR4 = 1,
parameter VAR1 = 2
)
(
input VAR3 ,
input clk,
output VAR2
);
reg [VAR1-1:0] VAR6;
reg VAR5;
generate if (VAR4) begin
always @(posedge clk or posedge VAR3) begin
if (VAR3) begin
VAR6 <= {VAR1{1'b1}};
VAR5 <= 1'b1;
end
else begin
VAR6[VAR1-2:0] <= VAR6[VAR1-1:1];
VAR6[VAR1-1] <= 0;
VAR... | mit |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_sdram/db/altera_mult_add_vkp2.v | 17,746 | module MODULE1
(
VAR40,
VAR314,
VAR51,
VAR186,
VAR330,
VAR280) ;
input VAR40;
input VAR314;
input [15:0] VAR51;
input [15:0] VAR186;
input VAR330;
output [31:0] VAR280;
tri0 VAR40;
tri1 VAR314;
tri0 [15:0] VAR51;
tri0 [15:0] VAR186;
tri1 VAR330;
wire [31:0] VAR74;
VAR290 VAR180
(
.VAR40(VAR40),
.VAR117(),
.VAR314(VAR31... | mit |
parallella/oh | common/hdl/oh_dsync.v | 1,258 | module MODULE1 #(parameter VAR3 = 2, parameter VAR2 = 0 )
(
input clk, input VAR5, input din, output dout );
VAR1 VAR1 (.clk(clk),
.VAR5(VAR5),
.din(din),
.dout(dout));
reg [VAR3:0] VAR6;
always @ (posedge clk or negedge VAR5)
if(!VAR5)
VAR6[VAR3:0] <= 'b0;
else
VAR6[VAR3:0] <= {VAR6[VAR3-1:0],din};
assign dout = (VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32ai/sky130_fd_sc_ls__o32ai_4.v | 2,441 | module MODULE1 (
VAR11 ,
VAR4 ,
VAR10 ,
VAR7 ,
VAR3 ,
VAR9 ,
VAR5,
VAR12,
VAR8 ,
VAR2
);
output VAR11 ;
input VAR4 ;
input VAR10 ;
input VAR7 ;
input VAR3 ;
input VAR9 ;
input VAR5;
input VAR12;
input VAR8 ;
input VAR2 ;
VAR1 VAR6 (
.VAR11(VAR11),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5... | apache-2.0 |
keith-epidev/VHDL-lib | top/lab_2/part_4/ip/dds/dds_stub.v | 1,186 | module MODULE1(VAR2, VAR3, VAR1)
;
input VAR2;
output VAR3;
output [7:0]VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4bb/sky130_fd_sc_lp__and4bb.pp.blackbox.v | 1,351 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR9 ,
VAR6 ,
VAR3 ,
VAR1,
VAR5,
VAR4 ,
VAR2
);
output VAR7 ;
input VAR8 ;
input VAR9 ;
input VAR6 ;
input VAR3 ;
input VAR1;
input VAR5;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2/sky130_fd_sc_hdll__nand2.symbol.v | 1,274 | module MODULE1 (
input VAR7,
input VAR6,
output VAR5
);
supply1 VAR1;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/Loop_loop_height_bkb.v | 2,034 | module MODULE1 (
VAR3, VAR14, VAR13, VAR7, VAR11, VAR12, VAR10, VAR5, VAR8, clk);
parameter VAR6 = 8;
parameter VAR9 = 8;
parameter VAR2 = 256;
input[VAR9-1:0] VAR3;
input VAR14;
output reg[VAR6-1:0] VAR13;
input[VAR9-1:0] VAR7;
input VAR11;
output reg[VAR6-1:0] VAR12;
input[VAR9-1:0] VAR10;
input VAR5;
output reg[VAR6... | mit |
e33b1711/rfnoc_pp_channelizer | custom_sources/noc_block_synthese.v | 4,601 | module MODULE1 #(
parameter VAR45 = 64'h11F5000000000000,
parameter VAR7 = 11)
(
input VAR6, input VAR11,
input VAR58, input VAR18,
input [63:0] VAR27, input VAR74, input VAR71, output VAR2,
output [63:0] VAR28, output VAR57, output VAR3, input VAR22,
output [63:0] VAR4,
output [31:0] VAR68
);
wire [31:0] VAR69;
wire [... | gpl-3.0 |
AngelTerrones/ADA | rtl/ada_mem_decoder.v | 16,968 | module MODULE1(
input clk,
input rst,
input [31:0] VAR32, output reg [31:0] VAR52, input [31:0] VAR66, input [31:0] VAR22, input VAR3, input VAR42, input VAR7, input VAR37, input VAR35, input VAR13, output reg [31:0] VAR40, input [31:0] VAR48, input VAR19, output [31:0] VAR62, output [31:0] VAR18, output VAR46, output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o32ai/sky130_fd_sc_hdll__o32ai.behavioral.v | 1,651 | module MODULE1 (
VAR8 ,
VAR15,
VAR7,
VAR2,
VAR11,
VAR14
);
output VAR8 ;
input VAR15;
input VAR7;
input VAR2;
input VAR11;
input VAR14;
supply1 VAR1;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR12 ;
wire VAR13 ;
wire VAR10 ;
wire VAR6;
nor VAR16 (VAR13 , VAR2, VAR15, VAR7 );
nor VAR17 (VAR10 , VAR11, VAR14 );
or VAR3 (VAR6... | apache-2.0 |
Canaan-Creative/MM | verilog/superkdf9/components/alink/rxc.v | 7,758 | module MODULE1(
input clk ,
input rst ,
input VAR24 ,
input [31:0] VAR14 ,
input [31:0] VAR15 ,
input VAR25 ,
input VAR16 ,
input [31:0] VAR6 ,
input VAR5 ,
input [31:0] VAR1 ,
input [31:0] VAR21 ,
input [31:0] VAR23 ,
input [VAR4*32-1:0] VAR19 ,
output reg VAR20 ,
output reg [31:0] VAR13 ,
input [VAR4-1:0] VAR11 ,
inp... | unlicense |
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/MakeClock.v | 4,381 | module MODULE1 ( VAR18, VAR1,
VAR14, VAR11,
VAR15, VAR8,
VAR16, VAR6,
VAR13, VAR17 );
parameter VAR7 = 0;
parameter VAR2 = 1;
input VAR18;
input VAR1;
input VAR14;
input VAR11;
input VAR15;
input VAR8;
output VAR16;
output VAR6;
output VAR13;
output VAR17;
reg VAR10;
reg VAR16;
reg VAR3;
reg VAR5;
always @(posedge VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0n/sky130_fd_sc_hd__lpflow_inputiso0n.symbol.v | 1,435 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR5
);
supply1 VAR4;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2.symbol.v | 1,224 | module MODULE1 (
input VAR3,
input VAR2,
output VAR4
);
supply1 VAR1;
supply0 VAR5;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.behavioral.v | 3,689 | module MODULE1( VAR27, VAR8, VAR29, VAR21 );
input VAR27, VAR8, VAR29;
output VAR21;
reg VAR5;
VAR23 VAR15(.VAR27(VAR27),.VAR8(VAR8),.VAR29(VAR29),.VAR21(VAR21),.VAR5(VAR5));
VAR23 VAR3(.VAR27(VAR27),.VAR8(VAR8),.VAR29(VAR29),.VAR21(VAR21),.VAR5(VAR5));
not VAR19(VAR1,VAR8);
and VAR16(VAR30,VAR29,VAR1);
and VAR25(VAR7,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32ai/sky130_fd_sc_hd__o32ai.pp.blackbox.v | 1,425 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR4 ,
VAR3 ,
VAR6 ,
VAR2 ,
VAR1,
VAR10,
VAR7 ,
VAR5
);
output VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR1;
input VAR10;
input VAR7 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111o/sky130_fd_sc_hs__a2111o.behavioral.pp.v | 1,971 | module MODULE1 (
VAR7,
VAR16,
VAR8 ,
VAR15 ,
VAR4 ,
VAR12 ,
VAR14 ,
VAR3
);
input VAR7;
input VAR16;
output VAR8 ;
input VAR15 ;
input VAR4 ;
input VAR12 ;
input VAR14 ;
input VAR3 ;
wire VAR14 VAR1 ;
wire VAR13 ;
wire VAR6;
and VAR9 (VAR1 , VAR15, VAR4 );
or VAR11 (VAR13 , VAR14, VAR12, VAR1, VAR3 );
VAR5 VAR2 (VAR6, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221o/sky130_fd_sc_lp__a221o_2.v | 2,444 | module MODULE2 (
VAR9 ,
VAR5 ,
VAR7 ,
VAR3 ,
VAR10 ,
VAR8 ,
VAR2,
VAR1,
VAR6 ,
VAR4
);
output VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR10 ;
input VAR8 ;
input VAR2;
input VAR1;
input VAR6 ;
input VAR4 ;
VAR11 VAR12 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR2(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai.blackbox.v | 1,361 | module MODULE1 (
VAR7 ,
VAR2,
VAR5,
VAR4 ,
VAR6
);
output VAR7 ;
input VAR2;
input VAR5;
input VAR4 ;
input VAR6 ;
supply1 VAR3;
supply0 VAR1;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/cm_rom_shared_bb.v | 8,028 | module MODULE1 (
VAR4,
VAR3,
VAR5,
VAR2,
VAR1);
input [8:0] VAR4;
input [8:0] VAR3;
input VAR5;
output [3:0] VAR2;
output [3:0] VAR1;
tri1 VAR5;
endmodule | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9643/axi_ad9643_pnmon.v | 7,207 | module MODULE1 (
VAR10,
VAR15,
VAR5,
VAR12,
VAR2);
input VAR10;
input [13:0] VAR15;
output VAR5;
output VAR12;
input [ 3:0] VAR2;
reg VAR4 = 'd0;
reg [27:0] VAR14 = 'd0;
reg [29:0] VAR16 = 'd0;
wire [27:0] VAR17;
wire [29:0] VAR13;
function [29:0] VAR9;
input [29:0] din;
reg [29:0] dout;
begin
dout[29] = din[22] ^ din[... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.v | 2,325 | module MODULE2 (
VAR10 ,
VAR5 ,
VAR8 ,
VAR7 ,
VAR6 ,
VAR2,
VAR1,
VAR11 ,
VAR9
);
output VAR10 ;
input VAR5 ;
input VAR8 ;
input VAR7 ;
input VAR6 ;
input VAR2;
input VAR1;
input VAR11 ;
input VAR9 ;
VAR3 VAR4 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR11(VAR11),
.... | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_wdata_router.v | 6,788 | module MODULE1 #
(
parameter VAR4 = "none", parameter integer VAR5 = 1, parameter integer VAR35 = 1, parameter integer VAR33 = 1, parameter integer VAR24 = 0 )
(
input wire VAR10,
input wire VAR29,
input wire [VAR5-1:0] VAR23,
input wire VAR18,
input wire VAR17,
output wire VAR8,
output wire [VAR5-1:0] VAR6, output wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxbp/sky130_fd_sc_ls__dfxbp.functional.pp.v | 1,767 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR6 ,
VAR13 ,
VAR11,
VAR2,
VAR4 ,
VAR8
);
output VAR1 ;
output VAR10 ;
input VAR6 ;
input VAR13 ;
input VAR11;
input VAR2;
input VAR4 ;
input VAR8 ;
wire VAR3;
VAR5 VAR14 VAR7 (VAR3 , VAR13, VAR6, , VAR11, VAR2);
buf VAR12 (VAR1 , VAR3 );
not VAR9 (VAR10 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311ai/sky130_fd_sc_hs__o311ai.behavioral.v | 1,959 | module MODULE1 (
VAR10 ,
VAR12 ,
VAR8 ,
VAR16 ,
VAR5 ,
VAR2 ,
VAR3,
VAR13
);
output VAR10 ;
input VAR12 ;
input VAR8 ;
input VAR16 ;
input VAR5 ;
input VAR2 ;
input VAR3;
input VAR13;
wire VAR5 VAR1 ;
wire VAR4 ;
wire VAR14;
or VAR15 (VAR1 , VAR8, VAR12, VAR16 );
nand VAR11 (VAR4 , VAR2, VAR1, VAR5 );
VAR6 VAR7 (VAR14,... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/ipcore_dir/sys_mon.v | 6,856 | module MODULE1
(
VAR16, VAR31, VAR54, VAR58, VAR40, VAR9, VAR64,
VAR43, VAR63,
VAR11, VAR15, VAR53, VAR61);
input [6:0] VAR16;
input VAR31;
input VAR54;
input [15:0] VAR58;
input VAR40;
input VAR9;
input VAR64;
input VAR43;
input VAR63;
input VAR53;
input VAR61;
output [15:0] VAR11;
output VAR15;
wire VAR56;
wire VAR20... | mit |
yanhongwang/ColorImage | ReadWrite/ReadWrite.v | 3,750 | module MODULE2#
(
parameter[ 3 : 0 ]VAR4 = 0, parameter[ 3 : 0 ]VAR6 = 1, parameter[ 3 : 0 ]VAR17 = 2
)
(
input VAR25,
input VAR12,
input[ VAR10 - 1 : 0 ]VAR24,
input[ VAR10 - 1 : 0 ]VAR26,
input[ VAR10 - 1 : 0 ]VAR13,
output reg[ VAR10 - 1 : 0 ]VAR29,
output reg[ VAR10 - 1 : 0 ]VAR15,
output reg[ VAR10 - 1 : 0 ]VAR1
)... | mit |
AntonovAlexander/activecore | designs/rtl/udm/hw/udm_controller.v | 10,795 | module MODULE1
parameter VAR10=(1024*1024*100)
)
(
input VAR16, VAR26,
input VAR25,
input [7:0] VAR18,
output reg [7:0] VAR9,
output reg VAR20,
input VAR50,
output reg VAR37,
output reg VAR17,
input VAR6,
output reg VAR27,
output reg [31:0] VAR29,
output [3:0] VAR43,
output reg [31:0] VAR57,
input VAR42,
input [31:0] V... | apache-2.0 |
ueliem/literate-broccoli | fpga_row.v | 2,259 | module MODULE1(
input clk,
input [VAR33*VAR26*12-1:0] VAR27,
input [(VAR33-1)*(VAR26*VAR26*12)-1:0] VAR10,
input [((VAR33-1)*5)-1:0] VAR11,
inout [VAR26-1:0] VAR15,
inout [VAR26-1:0] VAR19,
inout [VAR33*VAR26-1:0] VAR6,
inout [VAR33*VAR26-1:0] VAR38
);
parameter VAR26 = 3;
parameter VAR33 = 5;
parameter VAR14 = 5;
wire... | gpl-3.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_geninterp18.v | 1,599 | module MODULE1(
input VAR11,
input VAR9,
input VAR12,
input signed [17:0] VAR4,
input VAR14,
input [16:0] VAR10,
input [16:0] VAR2,
input [16:0] VAR1,
output signed [17:0] VAR15
);
reg VAR3;
reg [16:0] VAR8;
reg [16:0] VAR5;
reg [16:0] VAR7;
always @(posedge VAR11) begin
if(VAR9) begin
VAR3 <= VAR14;
VAR8 <= VAR10;
VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21oi/sky130_fd_sc_lp__a21oi_0.v | 2,261 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR7 ,
VAR8 ,
VAR10,
VAR6,
VAR9 ,
VAR5
);
output VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR8 ;
input VAR10;
input VAR6;
input VAR9 ;
input VAR5 ;
VAR4 VAR2 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311a/sky130_fd_sc_hd__o311a.behavioral.pp.v | 2,053 | module MODULE1 (
VAR5 ,
VAR16 ,
VAR6 ,
VAR12 ,
VAR8 ,
VAR11 ,
VAR15,
VAR14,
VAR2 ,
VAR10
);
output VAR5 ;
input VAR16 ;
input VAR6 ;
input VAR12 ;
input VAR8 ;
input VAR11 ;
input VAR15;
input VAR14;
input VAR2 ;
input VAR10 ;
wire VAR18 ;
wire VAR17 ;
wire VAR1;
or VAR13 (VAR18 , VAR6, VAR16, VAR12 );
and VAR3 (VAR17 ... | apache-2.0 |
asicguy/gplgpu | hdl/math/sv_log2.v | 1,870 | module MODULE1;
reg [31:0] VAR2;
reg [31:0] VAR1; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/ebufn/sky130_fd_sc_hs__ebufn.functional.pp.v | 1,773 | module MODULE1 (
VAR1,
VAR3,
VAR6 ,
VAR11 ,
VAR2
);
input VAR1;
input VAR3;
output VAR6 ;
input VAR11 ;
input VAR2;
wire VAR9 ;
wire VAR8;
VAR5 VAR10 (VAR9 , VAR11, VAR1, VAR3 );
VAR5 VAR4 (VAR8, VAR2, VAR1, VAR3 );
bufif0 VAR7 (VAR6 , VAR9, VAR8);
endmodule | apache-2.0 |
whitequark/bfcpu2 | verilog/BrainfuckCore.v | 4,621 | module MODULE2(
clk,
reset,
VAR63,
VAR76,
VAR61,
VAR31,
VAR62,
VAR23,
VAR46,
VAR1,
VAR52,
VAR53,
VAR20,
VAR66,
VAR15,
VAR37,
VAR64
);
parameter VAR44 = 12;
parameter VAR42 = 8;
parameter VAR70 = 12;
parameter VAR36 = 8;
input clk;
input reset;
wire [VAR44 - 1:0] VAR13;
wire VAR35;
VAR8 #(
.VAR55(VAR44)
) VAR74 (
.clk(c... | mit |
zhaishaomin/ring_network-based-multicore- | whole_system/ring_node.v | 26,304 | module MODULE1( clk,
rst,
VAR41, VAR76,
VAR8,
VAR154,
VAR125,
VAR148,
VAR133,
VAR42,
VAR118,
VAR123, VAR28,
VAR48, VAR47, VAR13,
VAR147,
VAR33,
VAR150,
VAR1
);
input clk;
input rst;
input [1:0] VAR41; input [15:0] VAR76;
input [1:0] VAR8;
input VAR154;
input VAR125;
input VAR148;
input VAR133;
input [3:0] VAR42;
input ... | apache-2.0 |
SeanZarzycki/openSPARC-FPU | project/src/fpu_rptr_macros.v | 1,248 | module MODULE1 (
in,
out
);
input [63:0] in;
output [63:0] out;
assign out[63:0] = in[63:0];
endmodule
module MODULE2 (
in,
out
);
input [31:0] in;
output [31:0] out;
assign out[31:0] = in[31:0];
endmodule | gpl-3.0 |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/altera_avalon_sc_fifo.v | 31,349 | module MODULE1
parameter VAR36 = 1,
parameter VAR55 = 8,
parameter VAR93 = 16,
parameter VAR13 = 0,
parameter VAR44 = 0,
parameter VAR5 = 0,
parameter VAR66 = 0,
parameter VAR54 = 0,
parameter VAR75 = 0,
parameter VAR50 = 0,
parameter VAR43 = 3,
parameter VAR32 = 1,
parameter VAR1 = VAR36 * VAR55,
parameter VAR7 = VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15.behavioral.pp.v | 1,866 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR6,
VAR8,
VAR9 ,
VAR4
);
output VAR3 ;
input VAR5 ;
input VAR6;
input VAR8;
input VAR9 ;
input VAR4 ;
wire VAR2 ;
wire VAR11;
buf VAR1 (VAR2 , VAR5 );
VAR7 VAR12 (VAR11, VAR2, VAR6, VAR8);
buf VAR10 (VAR3 , VAR11 );
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_fp_cmp_double.v | 30,424 | module MODULE1
(
VAR31,
VAR15,
VAR34,
VAR68,
VAR25,
VAR29,
VAR66,
VAR4,
VAR107,
VAR103,
VAR21) ;
output VAR31;
output VAR15;
output VAR34;
output VAR68;
output VAR25;
output VAR29;
input VAR66;
input VAR4;
input [63:0] VAR107;
input [63:0] VAR103;
output VAR21;
tri1 VAR66;
reg VAR12;
reg VAR76;
reg VAR99;
reg VAR88;
re... | mit |
carstenbru/fpga-log | spartanmc/hardware/contrast_box/src/spmc_contrast_box.v | 7,938 | module MODULE1 #(parameter VAR31 = 10'h0,
parameter VAR12 = 16000000,
parameter VAR55 = 2,
parameter VAR28 = 1000,
parameter VAR6 = 3, parameter VAR60 = 55, parameter VAR22 = 100, parameter VAR57 = 10, parameter VAR35 = 11, parameter VAR34 = 5, parameter VAR52 = 11) ( input wire VAR19, input wire [17:0] VAR11, output w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2/sky130_fd_sc_hd__and2.pp.symbol.v | 1,263 | module MODULE1 (
input VAR1 ,
input VAR5 ,
output VAR6 ,
input VAR2 ,
input VAR4,
input VAR7,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2b/sky130_fd_sc_hs__nand2b.pp.symbol.v | 1,263 | module MODULE1 (
input VAR5 ,
input VAR3 ,
output VAR4 ,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_clsp_synch_cljl.v | 10,357 | module MODULE1(
VAR21, VAR49, VAR50, VAR36,
VAR13, VAR35, VAR22,
VAR9, VAR6, VAR53, VAR4,
VAR27, VAR7, VAR8,
VAR10,
VAR45, VAR41, VAR30, VAR37, VAR3,
VAR18, VAR28, VAR51,
VAR55, VAR1, VAR32,
VAR20, VAR31, VAR29,
VAR46, VAR5, VAR33,
VAR56
);
input VAR31; input VAR20; input VAR32; input VAR1; input VAR55; input VAR51; in... | gpl-2.0 |
kramble/FPGA-Litecoin-Miner | experimental/LX150-SIXTYFOUR-A/ltcminer_icarus.v | 12,192 | module MODULE1 (VAR6, VAR63, VAR92, VAR4, VAR46, VAR97, VAR18, VAR82, VAR65, VAR47);
function integer VAR54; input integer VAR38;
begin
VAR38 = VAR38-1;
for (VAR54=0; VAR38>0; VAR54=VAR54+1)
VAR38 = VAR38>>1;
end
endfunction
parameter VAR103 = VAR103;
parameter VAR103 = 40; VAR104
parameter VAR109 = VAR109; else
parame... | gpl-3.0 |
slongfield/StereoCensus | verilog/lib/line_buffer.v | 2,836 | module MODULE1#(
parameter VAR17=1,
parameter VAR3=1,
parameter VAR10=1,
parameter VAR6=1
) (
input wire clk,
input wire rst,
input wire [VAR17-1:0] VAR9,
output wire [VAR17*VAR10*VAR6-1:0] VAR13
);
localparam VAR4 = VAR17*VAR10*VAR6;
localparam VAR5 = VAR17*VAR6;
wire[VAR17*VAR6-1:0] VAR1[VAR10];
wire[VAR17-1:0] VAR11... | gpl-3.0 |
SiLab-Bonn/basil | basil/firmware/modules/seq_gen/seq_gen.v | 1,545 | module MODULE1 #(
parameter VAR14 = 16'h0000,
parameter VAR3 = 16'h0000,
parameter VAR2 = 16,
parameter VAR24 = 16384,
parameter VAR17 = 8
) (
input wire VAR4,
input wire VAR16,
input wire [VAR2-1:0] VAR12,
inout wire [7:0] VAR10,
input wire VAR20,
input wire VAR23,
input wire VAR5,
input wire VAR19,
output wire [VAR17... | bsd-3-clause |
m-labs/milkymist | cores/pfpu/rtl/pfpu_alu.v | 4,793 | module MODULE1(
input VAR26,
input VAR17,
input [31:0] VAR11,
input [31:0] VAR56,
input VAR38,
input [3:0] VAR18,
output [31:0] VAR41,
output VAR52,
output reg VAR48,
output VAR8
);
reg [3:0] VAR15;
always @(posedge VAR26) begin
if(VAR17)
VAR15 <= 4'd0;
end
else
VAR15 <= VAR18;
end
always @(posedge VAR26) begin
if(VAR1... | lgpl-3.0 |
jairov4/accel-oil | solution_kintex7/impl/ip/hdl/verilog/nfa_get_finals.v | 12,847 | module MODULE1 (
VAR40,
VAR16,
VAR34,
VAR10,
VAR22,
VAR38,
VAR32,
VAR5,
VAR25,
VAR43,
VAR23,
VAR41,
VAR21,
VAR3,
VAR6,
VAR31,
VAR4,
VAR29
);
input VAR40;
input VAR16;
input VAR34;
output VAR10;
output VAR22;
output VAR38;
output VAR32;
input VAR5;
output VAR25;
input VAR43;
output VAR23;
output [31:0] VAR41;
input [31:... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3/sky130_fd_sc_lp__nand3_1.v | 2,175 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR10 ,
VAR5 ,
VAR3,
VAR1,
VAR8 ,
VAR4
);
output VAR6 ;
input VAR7 ;
input VAR10 ;
input VAR5 ;
input VAR3;
input VAR1;
input VAR8 ;
input VAR4 ;
VAR9 VAR2 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkinv/sky130_fd_sc_ms__clkinv_16.v | 2,042 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR3,
VAR8,
VAR2 ,
VAR7
);
output VAR1 ;
input VAR4 ;
input VAR3;
input VAR8;
input VAR2 ;
input VAR7 ;
VAR6 VAR5 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR3;
supply0 VAR8;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_2.functional.v | 1,436 | module MODULE1( VAR13, VAR8, VAR6, VAR14, VAR4 );
input VAR4, VAR14, VAR6, VAR13;
output VAR8;
wire VAR11;
not VAR16( VAR11, VAR4 );
wire VAR7;
not VAR5( VAR7, VAR14 );
wire VAR10;
not VAR2( VAR10, VAR6 );
wire VAR3;
and VAR12( VAR3, VAR11, VAR7, VAR10 );
wire VAR9;
not VAR1( VAR9, VAR13 );
or VAR15( VAR8, VAR3, VAR9 )... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_pmod_tft/rtl/pixel_reader.v | 3,502 | module MODULE1 (
input clk,
input rst,
input VAR19,
output reg VAR1,
input [23:0] VAR16,
input [24:0] VAR4,
output reg VAR13,
output reg [7:0] VAR20,
output reg [7:0] VAR3,
output reg [7:0] VAR14,
output reg VAR12,
input VAR17,
input VAR2,
input VAR15,
input VAR6,
output reg VAR8
);
reg [7:0] VAR18;
reg [7:0] VAR7;
reg... | mit |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_ADC_ON.v | 2,207 | module MODULE1 (
address,
VAR8,
clk,
VAR4,
VAR2,
VAR7,
VAR6,
VAR3
)
;
output VAR6;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR4;
input VAR2;
input [ 31: 0] VAR7;
wire VAR5;
reg VAR9;
wire VAR6;
wire VAR1;
wire [ 31: 0] VAR3;
assign VAR5 = 1;
assign VAR1 = {1 {(address == 0)}} & VAR9;
a... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xlconcat_0_1/zqynq_lab_1_design_xlconcat_0_1_stub.v | 1,345 | module MODULE1(VAR1, VAR2, dout)
;
input [0:0]VAR1;
input [0:0]VAR2;
output [1:0]dout;
endmodule | mit |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T27-rom-param/notegen.v | 1,811 | module MODULE1(input wire clk, input wire VAR3, input wire [15:0] VAR1, output reg VAR2);
wire VAR5;
reg [15:0] VAR4 = 0;
always @(posedge clk)
if (VAR3 == 0)
VAR4 <= 0;
else if (VAR1 == 0)
VAR4 <= 0;
else if (VAR4 == VAR1 - 1)
VAR4 <= 0;
else
VAR4 <= VAR4 + 1;
assign VAR5 = (VAR4 == 0) ? 1 : 0;
always @(posedge clk)
i... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50.behavioral.v | 1,405 | module MODULE1 (
VAR4,
VAR9
);
output VAR4;
input VAR9;
supply1 VAR8;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
wire VAR6;
buf VAR5 (VAR6, VAR9 );
buf VAR7 (VAR4 , VAR6 );
endmodule | apache-2.0 |
lokisz/openzcore | pippo-0.9/rtl/verilog/pippo_operandmuxes.v | 2,204 | module MODULE1(
VAR7, VAR2, VAR12, VAR11,
VAR5, VAR1,
VAR6, VAR3
);
parameter VAR9 = VAR10;
input [VAR9-1:0] VAR7;
input [VAR9-1:0] VAR2;
input [VAR9-1:0] VAR12;
input [VAR9-1:0] VAR11;
input [VAR8-1:0] VAR5;
input [VAR8-1:0] VAR1;
output [VAR9-1:0] VAR6;
output [VAR9-1:0] VAR3;
reg [VAR9-1:0] VAR6;
reg [VAR9-1:0] VAR3... | gpl-2.0 |
chimeh/stopwatch_verilog | src/scancnt_decod38_mux8_seg7decod.v | 2,803 | module MODULE2(input reset, input VAR6,
output reg [2:0] VAR16);
always @( posedge reset or posedge VAR6) begin
if ( reset) VAR16 <= 0;
end
else VAR16 <= VAR16 + 1;
end
endmodule
module MODULE4 (input [2:0] VAR9,
output reg [7:0] VAR14);
always @(VAR9 ) begin
case(VAR9)
3'd0: VAR14 = ~8'h01;
3'd1: VAR14 = ~8'h02;
3'd2:... | unlicense |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_to_dram_ctrl_tx.v | 2,788 | module MODULE1
, parameter VAR15(VAR35)
, parameter VAR15(VAR12)
, parameter VAR15(VAR45)
, localparam VAR38=(VAR35>>3)
, localparam VAR17=(VAR12/VAR45)
, localparam VAR46=VAR16(VAR37)
, localparam VAR34=VAR16(VAR45)
)
(
input VAR25
, input VAR10
, input VAR4
, input [VAR46-1:0] VAR29
, output logic VAR28
, input [VAR3... | bsd-3-clause |
fallen/milkymist-mmu | cores/hpdmc_ddr32/rtl/hpdmc_datactl.v | 3,569 | module MODULE1(
input VAR10,
input VAR9,
input read,
input write,
input [3:0] VAR11,
output reg VAR19,
output reg VAR17,
output [3:0] VAR3,
output reg VAR7,
output VAR18,
input VAR8,
input [1:0] VAR4
);
reg [2:0] VAR6;
always @(posedge VAR10) begin
if(VAR9) begin
VAR6 <= 3'd0;
VAR19 <= 1'b1;
end else begin
if(read) beg... | lgpl-3.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_vfr_controller.v | 7,720 | module MODULE1
(
VAR35,
reset,
VAR37,
VAR4,
VAR5,
VAR34,
VAR1,
VAR16,
VAR17,
VAR7,
VAR43,
VAR12,
VAR19,
VAR45,
VAR13,
VAR30,
VAR10,
VAR29,
VAR36,
VAR24,
VAR9,
VAR3,
VAR41,
VAR40,
VAR8,
VAR39
);
localparam VAR26 = 32;
localparam VAR33 = 32;
parameter VAR11 = 16;
parameter VAR28 = 4;
parameter VAR23 = 32;
parameter VAR32... | mit |
alonso193/proyecto1 | Pruebas/DATA_SD/probadorPhysical.v | 2,406 | module MODULE1(
output reg VAR10,
output reg VAR5,
output reg VAR12,
output reg VAR11,
output reg [15:0] VAR2,
output reg [3:0] VAR1,
output reg VAR8,
output reg VAR9,
output reg VAR6,
output reg VAR3,
output reg VAR4,
output reg [31:0] VAR13,
output reg [31:0] VAR7
);
always
begin
VAR10= ! VAR10;
end | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4b/sky130_fd_sc_hdll__and4b_4.v | 2,316 | module MODULE2 (
VAR10 ,
VAR9 ,
VAR5 ,
VAR3 ,
VAR7 ,
VAR6,
VAR8,
VAR11 ,
VAR2
);
output VAR10 ;
input VAR9 ;
input VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR6;
input VAR8;
input VAR11 ;
input VAR2 ;
VAR1 VAR4 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR11(VAR11),
.... | apache-2.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi/solution1/syn/verilog/contact_discovery_AXILiteS_s_axi.v | 25,683 | module MODULE2
VAR161 = 11,
VAR129 = 32
)(
input wire VAR144,
input wire VAR148,
input wire VAR12,
input wire [VAR161-1:0] VAR147,
input wire VAR14,
output wire VAR93,
input wire [VAR129-1:0] VAR9,
input wire [VAR129/8-1:0] VAR134,
input wire VAR81,
output wire VAR104,
output wire [1:0] VAR28,
output wire VAR31,
input ... | gpl-3.0 |
bluespec/Flute | builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkTop_HW_Side.v | 13,170 | module MODULE1(VAR86,
VAR78);
input VAR86;
input VAR78;
reg VAR116;
wire VAR2, VAR32;
reg [11 : 0] VAR36;
wire [11 : 0] VAR110;
wire VAR71;
wire [352 : 0] VAR60;
wire [255 : 0] VAR10;
wire VAR98,
VAR88,
VAR3,
VAR26;
wire [352 : 0] VAR47;
wire [255 : 0] VAR18;
wire [63 : 0] VAR77,
VAR69,
VAR42;
wire [7 : 0] VAR67,
VAR28... | apache-2.0 |
dailypips/miaow | src/verilog/rtl/vgpr/rd_port_mux_8to1.v | 2,994 | module MODULE1 (
VAR1,
VAR2,
VAR6,
VAR24,
VAR28,
VAR4,
VAR9,
VAR13,
VAR18,
VAR22,
VAR8,
VAR26,
VAR3,
VAR10,
VAR19,
VAR25,
VAR11,
VAR15,
VAR12,
VAR29
);
output [2047:0] VAR11;
output [9:0] VAR15;
output VAR12;
input VAR1;
input VAR6;
input VAR28;
input VAR9;
input VAR18;
input VAR8;
input VAR3;
input VAR19;
input [9:0] ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdlclkp/sky130_fd_sc_hs__sdlclkp.functional.pp.v | 2,000 | module MODULE1 (
VAR6,
VAR18,
VAR13,
VAR16 ,
VAR5,
VAR20
);
input VAR6;
input VAR18;
output VAR13;
input VAR16 ;
input VAR5;
input VAR20 ;
wire VAR8 ;
wire VAR19 ;
wire VAR9 ;
wire VAR10 ;
wire VAR4 ;
wire VAR15 ;
wire VAR3;
wire VAR14 ;
not VAR11 (VAR19 , VAR8 );
not VAR7 (VAR9 , VAR20 );
nor VAR1 (VAR14, VAR5, VAR16 ... | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/host_interface/ddr3_pcie_controller.v | 14,845 | module MODULE1 (
input clk,
input rst,
input [31:0] VAR14,
input [27:0] VAR91,
input VAR68, input [27:0] VAR62,
input VAR42, output reg VAR3,
input VAR47,
input [31:0] VAR80,
output [1:0] VAR6,
input [1:0] VAR82,
output [23:0] VAR79,
output VAR21,
input VAR17,
output VAR57,
input VAR52,
output [23:0] VAR25,
output [31:... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/high_res_timer.v | 6,908 | module MODULE1 (
address,
VAR15,
clk,
VAR16,
VAR25,
VAR2,
irq,
VAR12
)
;
output irq;
output [ 15: 0] VAR12;
input [ 2: 0] address;
input VAR15;
input clk;
input VAR16;
input VAR25;
input [ 15: 0] VAR2;
wire VAR13;
wire VAR4;
wire VAR7;
reg [ 3: 0] VAR23;
wire VAR1;
reg VAR27;
wire VAR29;
wire [ 31: 0] VAR3;
reg [ 31: 0... | mit |
CeesWolfs/ceespu | src/gpu/primitives/fifo_2x_reducer.v | 1,533 | module MODULE1 (
input rst,
input clk,
input VAR17,
input [29:0] VAR11,
output reg [14:0] VAR2
);
localparam VAR15 = 5'h1e;
wire [1-1:0] VAR6;
wire [30-1:0] VAR18;
wire [1-1:0] VAR19;
reg [30-1:0] VAR9;
reg [1-1:0] VAR23;
reg [1-1:0] VAR7;
VAR21 VAR20 (
.VAR22(clk),
.VAR1(VAR17),
.VAR16(rst),
.VAR4(rst),
.din(VAR9),
.V... | mit |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/led_red.v | 2,135 | module MODULE1 (
address,
VAR8,
clk,
VAR6,
VAR9,
VAR1,
VAR3,
VAR4
)
;
output [ 17: 0] VAR3;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR6;
input VAR9;
input [ 31: 0] VAR1;
wire VAR5;
reg [ 17: 0] VAR7;
wire [ 17: 0] VAR3;
wire [ 17: 0] VAR2;
wire [ 31: 0] VAR4;
assign VAR5 = 1;
assign V... | gpl-3.0 |
P3Stor/P3Stor | pcie/core/pcie_pipe_misc_v6.v | 7,524 | module MODULE1 #
(
parameter VAR21 = 0 )
(
input wire VAR20 ,
input wire VAR17 ,
input wire VAR3 ,
input wire VAR26 ,
input wire [2:0] VAR16 ,
input wire VAR6 ,
output wire VAR25 ,
output wire VAR1 ,
output wire VAR5 ,
output wire VAR19 ,
output wire [2:0] VAR12 ,
output wire VAR27 ,
input wire VAR8 ,
input wire VAR24
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211a/sky130_fd_sc_hd__o211a.behavioral.v | 1,542 | module MODULE1 (
VAR9 ,
VAR14,
VAR1,
VAR13,
VAR12
);
output VAR9 ;
input VAR14;
input VAR1;
input VAR13;
input VAR12;
supply1 VAR5;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR2 ;
wire VAR8 ;
wire VAR4;
or VAR7 (VAR8 , VAR1, VAR14 );
and VAR11 (VAR4, VAR8, VAR13, VAR12);
buf VAR10 (VAR9 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31oi/sky130_fd_sc_hd__a31oi.pp.symbol.v | 1,374 | module MODULE1 (
input VAR6 ,
input VAR5 ,
input VAR4 ,
input VAR9 ,
output VAR7 ,
input VAR3 ,
input VAR2,
input VAR1,
input VAR8
);
endmodule | apache-2.0 |
tfiwits/ALARMCLK_v | mux_case.v | 1,155 | module MODULE1 (
VAR2,
VAR4,
rst,
VAR5,
VAR6,
VAR3,
VAR7,
VAR1
);
input VAR2,rst,VAR4; input VAR6,VAR3,VAR7; output [1:0] VAR5;
output VAR1;
reg VAR1;
reg[1:0] sel=0;
always@(posedge VAR2 or negedge rst or negedge VAR7)
begin
if (rst==0)
begin
sel=0;
end
else
begin
case (sel)
0: if (VAR6==1)
sel<=2'b01;
end
else if(VAR... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_monitor.v | 6,280 | module MODULE1 (
VAR9,
VAR32,
VAR40,
VAR3,
VAR26,
VAR17,
VAR11,
VAR19,
VAR7,
VAR2,
VAR29,
VAR38,
VAR4,
VAR1,
VAR23
);
input VAR9; input VAR32; input [VAR28] VAR40; input VAR11; input VAR3; input [VAR28] VAR26; input [VAR22] VAR17; input VAR19; input VAR7; input [VAR6] VAR2; input [VAR18] VAR29;
output VAR38; reg VAR38;... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4bb/sky130_fd_sc_ms__and4bb.behavioral.pp.v | 1,998 | module MODULE1 (
VAR13 ,
VAR3 ,
VAR15 ,
VAR11 ,
VAR14 ,
VAR10,
VAR8,
VAR6 ,
VAR4
);
output VAR13 ;
input VAR3 ;
input VAR15 ;
input VAR11 ;
input VAR14 ;
input VAR10;
input VAR8;
input VAR6 ;
input VAR4 ;
wire VAR2 ;
wire VAR9 ;
wire VAR7;
nor VAR5 (VAR2 , VAR3, VAR15 );
and VAR12 (VAR9 , VAR2, VAR11, VAR14 );
VAR1 VAR... | apache-2.0 |
zhangry868/MultiCycleCPU | Multiple_Cycles_CPU/MIPS_Register.v | 2,755 | module MODULE1(VAR3,VAR8,VAR2,VAR4,VAR6,VAR7,VAR1,VAR5);
input VAR4;
input [4:0]VAR3,VAR8,VAR2;
input [31:0]VAR7;
input [3:0]VAR6;
output [31:0]VAR1,VAR5;
reg [31:0]register[31:0];
assign VAR1 = register[VAR3];
assign VAR5 = register[VAR8];
begin
begin
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio/sky130_fd_io__top_sio.behavioral.v | 9,054 | module MODULE1 (VAR65, VAR54, VAR69, VAR60, VAR55, VAR61, VAR37,
VAR19, VAR8, VAR14, VAR58, VAR36, VAR41, VAR13, VAR53,
VAR7, VAR5, VAR66, VAR56, VAR34,
VAR6
);
output VAR65;
inout VAR54;
inout VAR69;
input [2:0] VAR60;
input VAR55;
input VAR61;
output VAR37;
input VAR19;
input VAR8;
input VAR14;
input VAR58;
input VAR... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_4.behavioral.v | 1,267 | module MODULE1( VAR7, VAR4, VAR3, VAR6 );
input VAR6, VAR7, VAR4;
output VAR3;
VAR2 VAR1(.VAR7(VAR7),.VAR4(VAR4),.VAR3(VAR3),.VAR6(VAR6));
VAR2 VAR5(.VAR7(VAR7),.VAR4(VAR4),.VAR3(VAR3),.VAR6(VAR6)); | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.cache/ip/2018.2/6e90fda3cffff716/design_1_pointer_basic_0_1_stub.v | 3,195 | module MODULE1(VAR9,
VAR1, VAR4,
VAR3, VAR13,
VAR6, VAR17,
VAR18, VAR15,
VAR8, VAR5,
VAR2, VAR10,
VAR11, VAR7,
VAR14, VAR16, VAR19, VAR12,
interrupt)
;
input [4:0]VAR9;
input VAR1;
output VAR4;
input [31:0]VAR3;
input [3:0]VAR13;
input VAR6;
output VAR17;
output [1:0]VAR18;
output VAR15;
input VAR8;
input [4:0]VAR5;
in... | mit |
theapi/nand2tetris_fpga | hack/rtl/verilog/screen_init.v | 1,803 | module MODULE1(
clk,
reset,
address,
out,
VAR1
);
input clk;
input reset;
output VAR1;
output [12:0] address; output [15:0] out;
reg [15:0] VAR3;
reg [13:0] VAR2;
reg [7:0] counter;
reg VAR4;
always @(posedge clk or posedge reset) begin
if (reset) begin
counter <= 0;
end else begin
if (counter == 8'd16) begin
counter <... | mit |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_1/hdl/verilog/feedforward_ST_WandB.v | 1,457 | module MODULE1 (VAR3, VAR8, VAR2, VAR1, VAR6, clk);
parameter VAR7 = 64;
parameter VAR4 = 13;
parameter VAR9 = 5040;
input[VAR4-1:0] VAR3;
input VAR8;
input[VAR7-1:0] VAR2;
input VAR1;
output reg[VAR7-1:0] VAR6;
input clk;
reg [VAR7-1:0] VAR5[VAR9-1:0];
begin
begin
begin
end | gpl-3.0 |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/eeprom_v1_07_a/hdl/verilog/one_wire_io.v | 4,360 | module MODULE1 (
VAR32, VAR15, VAR23, VAR17, VAR19, VAR2, VAR12, VAR9, VAR27,
VAR29, VAR30, VAR24, VAR6, VAR8, VAR11, VAR22, VAR7,
VAR31, VAR34, VAR25, VAR33, VAR20, VAR35, VAR18, VAR26,
VAR28, VAR16, VAR14, VAR13, VAR4, VAR21, VAR3, VAR5, VAR1);
input VAR32;
input VAR15;
input [7:0] VAR23;
input VAR17;
input VAR19;
ou... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.functional.v | 1,378 | module MODULE1( VAR13, VAR14, VAR5, VAR7, VAR12 );
input VAR12, VAR7, VAR13, VAR5;
output VAR14;
wire VAR8;
not VAR11( VAR8, VAR12 );
wire VAR3;
not VAR6( VAR3, VAR7 );
wire VAR10;
not VAR1( VAR10, VAR13 );
wire VAR9;
not VAR2( VAR9, VAR5 );
and VAR4( VAR14, VAR8, VAR3, VAR10, VAR9 );
endmodule | apache-2.0 |
DeadWitcher/amber-de0-nano | hw/vlog/amber25/a25_wishbone.v | 10,578 | module MODULE1
(
input VAR46,
input VAR23,
output VAR29,
input VAR11,
input [127:0] VAR12,
input [15:0] VAR7,
input [31:0] VAR50,
output [127:0] VAR45,
input VAR26,
output VAR49,
input VAR54,
input [127:0] VAR40,
input [15:0] VAR3,
input [31:0] VAR60,
output [127:0] VAR57,
input VAR2,
output VAR25,
input VAR31,
input [... | lgpl-2.1 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_uart/db/ip/niosii/niosii.v | 28,083 | module MODULE1 (
input wire VAR125, output wire [7:0] VAR168, input wire VAR202, input wire VAR116, output wire VAR142 );
wire [31:0] VAR67; wire VAR82; wire VAR162; wire [17:0] VAR185; wire [3:0] VAR152; wire VAR205; wire VAR74; wire [31:0] VAR195; wire [31:0] VAR73; wire VAR145; wire [17:0] VAR20; wire VAR109; wire V... | mit |
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